1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-xnack -verify-machineinstrs -debug-only=machine-scheduler < %s 2> %t | FileCheck --enable-var-scope --check-prefix=GFX9 %s
3; RUN: FileCheck --enable-var-scope --check-prefix=DBG %s < %t
4; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -debug-only=machine-scheduler < %s 2> %t | FileCheck --enable-var-scope --check-prefix=GFX10 %s
5; RUN: FileCheck --enable-var-scope --check-prefix=DBG %s < %t
6; REQUIRES: asserts
7
8; FIXME: Verifier error with xnack enabled.
9
10; DBG-LABEL: cluster_load_cluster_store:
11
12; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
13; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
14; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
15; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
16; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
17; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
18
19; DBG: Cluster ld/st SU(1) - SU(2)
20
21; DBG: Cluster ld/st SU([[L1:[0-9]+]]) - SU([[L2:[0-9]+]])
22; DBG: Cluster ld/st SU([[L2]]) - SU([[L3:[0-9]+]])
23; DBG: Cluster ld/st SU([[L3]]) - SU([[L4:[0-9]+]])
24
25; DBG-NOT: Cluster ld/st
26
27define amdgpu_kernel void @cluster_load_cluster_store(i32* noalias %lb, i32* noalias %sb) {
28; GFX9-LABEL: cluster_load_cluster_store:
29; GFX9:       ; %bb.0: ; %bb
30; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
31; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
32; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
33; GFX9-NEXT:    v_mov_b32_e32 v0, s2
34; GFX9-NEXT:    v_mov_b32_e32 v1, s3
35; GFX9-NEXT:    flat_load_dword v2, v[0:1]
36; GFX9-NEXT:    flat_load_dword v3, v[0:1] offset:8
37; GFX9-NEXT:    flat_load_dword v4, v[0:1] offset:16
38; GFX9-NEXT:    flat_load_dword v5, v[0:1] offset:24
39; GFX9-NEXT:    v_mov_b32_e32 v0, s0
40; GFX9-NEXT:    v_mov_b32_e32 v1, s1
41; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
42; GFX9-NEXT:    flat_store_dword v[0:1], v2
43; GFX9-NEXT:    flat_store_dword v[0:1], v3 offset:8
44; GFX9-NEXT:    flat_store_dword v[0:1], v4 offset:16
45; GFX9-NEXT:    flat_store_dword v[0:1], v5 offset:24
46; GFX9-NEXT:    s_endpgm
47;
48; GFX10-LABEL: cluster_load_cluster_store:
49; GFX10:       ; %bb.0: ; %bb
50; GFX10-NEXT:    s_clause 0x1
51; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
52; GFX10-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
53; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
54; GFX10-NEXT:    s_add_u32 s0, s2, 8
55; GFX10-NEXT:    s_addc_u32 s1, s3, 0
56; GFX10-NEXT:    s_add_u32 s6, s2, 16
57; GFX10-NEXT:    v_mov_b32_e32 v3, s1
58; GFX10-NEXT:    s_addc_u32 s7, s3, 0
59; GFX10-NEXT:    v_mov_b32_e32 v0, s2
60; GFX10-NEXT:    v_mov_b32_e32 v2, s0
61; GFX10-NEXT:    s_add_u32 s0, s2, 24
62; GFX10-NEXT:    v_mov_b32_e32 v1, s3
63; GFX10-NEXT:    s_addc_u32 s1, s3, 0
64; GFX10-NEXT:    v_mov_b32_e32 v4, s6
65; GFX10-NEXT:    v_mov_b32_e32 v5, s7
66; GFX10-NEXT:    v_mov_b32_e32 v7, s1
67; GFX10-NEXT:    v_mov_b32_e32 v6, s0
68; GFX10-NEXT:    s_clause 0x3
69; GFX10-NEXT:    flat_load_dword v8, v[0:1]
70; GFX10-NEXT:    flat_load_dword v9, v[2:3]
71; GFX10-NEXT:    flat_load_dword v10, v[4:5]
72; GFX10-NEXT:    flat_load_dword v11, v[6:7]
73; GFX10-NEXT:    s_add_u32 s0, s4, 8
74; GFX10-NEXT:    s_addc_u32 s1, s5, 0
75; GFX10-NEXT:    v_mov_b32_e32 v0, s4
76; GFX10-NEXT:    v_mov_b32_e32 v3, s1
77; GFX10-NEXT:    v_mov_b32_e32 v2, s0
78; GFX10-NEXT:    s_add_u32 s0, s4, 16
79; GFX10-NEXT:    s_addc_u32 s1, s5, 0
80; GFX10-NEXT:    s_add_u32 s2, s4, 24
81; GFX10-NEXT:    v_mov_b32_e32 v1, s5
82; GFX10-NEXT:    s_addc_u32 s3, s5, 0
83; GFX10-NEXT:    v_mov_b32_e32 v5, s1
84; GFX10-NEXT:    v_mov_b32_e32 v4, s0
85; GFX10-NEXT:    v_mov_b32_e32 v7, s3
86; GFX10-NEXT:    v_mov_b32_e32 v6, s2
87; GFX10-NEXT:    s_waitcnt vmcnt(3) lgkmcnt(3)
88; GFX10-NEXT:    flat_store_dword v[0:1], v8
89; GFX10-NEXT:    s_waitcnt vmcnt(2) lgkmcnt(3)
90; GFX10-NEXT:    flat_store_dword v[2:3], v9
91; GFX10-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(3)
92; GFX10-NEXT:    flat_store_dword v[4:5], v10
93; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(3)
94; GFX10-NEXT:    flat_store_dword v[6:7], v11
95; GFX10-NEXT:    s_endpgm
96bb:
97  %la0 = getelementptr inbounds i32, i32* %lb, i32 0
98  %ld0 = load i32, i32* %la0
99  %la1 = getelementptr inbounds i32, i32* %lb, i32 2
100  %ld1 = load i32, i32* %la1
101  %la2 = getelementptr inbounds i32, i32* %lb, i32 4
102  %ld2 = load i32, i32* %la2
103  %la3 = getelementptr inbounds i32, i32* %lb, i32 6
104  %ld3 = load i32, i32* %la3
105
106  %sa0 = getelementptr inbounds i32, i32* %sb, i32 0
107  store i32 %ld0, i32* %sa0
108  %sa1 = getelementptr inbounds i32, i32* %sb, i32 2
109  store i32 %ld1, i32* %sa1
110  %sa2 = getelementptr inbounds i32, i32* %sb, i32 4
111  store i32 %ld2, i32* %sa2
112  %sa3 = getelementptr inbounds i32, i32* %sb, i32 6
113  store i32 %ld3, i32* %sa3
114
115  ret void
116}
117
118; DBG-LABEL: cluster_load_valu_cluster_store:
119
120; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
121; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
122; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
123; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
124; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
125; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
126
127; DBG: Cluster ld/st SU(1) - SU(2)
128
129; DBG: Cluster ld/st SU([[L1:[0-9]+]]) - SU([[L2:[0-9]+]])
130; DBG: Cluster ld/st SU([[L2]]) - SU([[L3:[0-9]+]])
131; DBG: Cluster ld/st SU([[L3]]) - SU([[L4:[0-9]+]])
132
133; DBG-NOT: Cluster ld/st
134
135define amdgpu_kernel void @cluster_load_valu_cluster_store(i32* noalias %lb, i32* noalias %sb) {
136; GFX9-LABEL: cluster_load_valu_cluster_store:
137; GFX9:       ; %bb.0: ; %bb
138; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
139; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
140; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
141; GFX9-NEXT:    v_mov_b32_e32 v0, s2
142; GFX9-NEXT:    v_mov_b32_e32 v1, s3
143; GFX9-NEXT:    flat_load_dword v2, v[0:1]
144; GFX9-NEXT:    flat_load_dword v3, v[0:1] offset:8
145; GFX9-NEXT:    flat_load_dword v4, v[0:1] offset:16
146; GFX9-NEXT:    flat_load_dword v5, v[0:1] offset:24
147; GFX9-NEXT:    v_mov_b32_e32 v0, s0
148; GFX9-NEXT:    v_mov_b32_e32 v1, s1
149; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
150; GFX9-NEXT:    flat_store_dword v[0:1], v2
151; GFX9-NEXT:    v_add_u32_e32 v2, 1, v3
152; GFX9-NEXT:    flat_store_dword v[0:1], v4 offset:16
153; GFX9-NEXT:    flat_store_dword v[0:1], v2 offset:8
154; GFX9-NEXT:    flat_store_dword v[0:1], v5 offset:24
155; GFX9-NEXT:    s_endpgm
156;
157; GFX10-LABEL: cluster_load_valu_cluster_store:
158; GFX10:       ; %bb.0: ; %bb
159; GFX10-NEXT:    s_clause 0x1
160; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
161; GFX10-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
162; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
163; GFX10-NEXT:    s_add_u32 s0, s2, 8
164; GFX10-NEXT:    s_addc_u32 s1, s3, 0
165; GFX10-NEXT:    s_add_u32 s6, s2, 16
166; GFX10-NEXT:    v_mov_b32_e32 v3, s1
167; GFX10-NEXT:    v_mov_b32_e32 v2, s0
168; GFX10-NEXT:    s_addc_u32 s7, s3, 0
169; GFX10-NEXT:    s_add_u32 s0, s2, 24
170; GFX10-NEXT:    v_mov_b32_e32 v0, s2
171; GFX10-NEXT:    s_addc_u32 s1, s3, 0
172; GFX10-NEXT:    v_mov_b32_e32 v1, s3
173; GFX10-NEXT:    v_mov_b32_e32 v4, s6
174; GFX10-NEXT:    v_mov_b32_e32 v5, s7
175; GFX10-NEXT:    flat_load_dword v6, v[2:3]
176; GFX10-NEXT:    v_mov_b32_e32 v3, s1
177; GFX10-NEXT:    v_mov_b32_e32 v2, s0
178; GFX10-NEXT:    s_clause 0x2
179; GFX10-NEXT:    flat_load_dword v8, v[0:1]
180; GFX10-NEXT:    flat_load_dword v9, v[4:5]
181; GFX10-NEXT:    flat_load_dword v10, v[2:3]
182; GFX10-NEXT:    s_add_u32 s0, s4, 8
183; GFX10-NEXT:    s_addc_u32 s1, s5, 0
184; GFX10-NEXT:    s_add_u32 s2, s4, 16
185; GFX10-NEXT:    v_mov_b32_e32 v3, s1
186; GFX10-NEXT:    s_addc_u32 s3, s5, 0
187; GFX10-NEXT:    v_mov_b32_e32 v0, s4
188; GFX10-NEXT:    v_mov_b32_e32 v2, s0
189; GFX10-NEXT:    s_add_u32 s0, s4, 24
190; GFX10-NEXT:    v_mov_b32_e32 v1, s5
191; GFX10-NEXT:    v_mov_b32_e32 v5, s3
192; GFX10-NEXT:    s_addc_u32 s1, s5, 0
193; GFX10-NEXT:    v_mov_b32_e32 v4, s2
194; GFX10-NEXT:    s_waitcnt vmcnt(3) lgkmcnt(3)
195; GFX10-NEXT:    v_add_nc_u32_e32 v11, 1, v6
196; GFX10-NEXT:    v_mov_b32_e32 v7, s1
197; GFX10-NEXT:    v_mov_b32_e32 v6, s0
198; GFX10-NEXT:    s_waitcnt vmcnt(2) lgkmcnt(2)
199; GFX10-NEXT:    flat_store_dword v[0:1], v8
200; GFX10-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(2)
201; GFX10-NEXT:    flat_store_dword v[4:5], v9
202; GFX10-NEXT:    flat_store_dword v[2:3], v11
203; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(3)
204; GFX10-NEXT:    flat_store_dword v[6:7], v10
205; GFX10-NEXT:    s_endpgm
206bb:
207  %la0 = getelementptr inbounds i32, i32* %lb, i32 0
208  %ld0 = load i32, i32* %la0
209  %la1 = getelementptr inbounds i32, i32* %lb, i32 2
210  %ld1 = load i32, i32* %la1
211  %la2 = getelementptr inbounds i32, i32* %lb, i32 4
212  %ld2 = load i32, i32* %la2
213  %la3 = getelementptr inbounds i32, i32* %lb, i32 6
214  %ld3 = load i32, i32* %la3
215
216  %sa0 = getelementptr inbounds i32, i32* %sb, i32 0
217  store i32 %ld0, i32* %sa0
218  %sa1 = getelementptr inbounds i32, i32* %sb, i32 2
219  %add = add i32 %ld1, 1
220  store i32 %add, i32* %sa1
221  %sa2 = getelementptr inbounds i32, i32* %sb, i32 4
222  store i32 %ld2, i32* %sa2
223  %sa3 = getelementptr inbounds i32, i32* %sb, i32 6
224  store i32 %ld3, i32* %sa3
225
226  ret void
227}
228
229; Cluster loads from the same texture with different coordinates
230; DBG-LABEL: cluster_image_load:
231; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
232; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
233; DBG: {{^}}Cluster ld/st [[SU1:SU\([0-9]+\)]] - [[SU2:SU\([0-9]+\)]]
234; DBG: {{^}}[[SU1]]: {{.*}} IMAGE_LOAD
235; DBG: {{^}}[[SU2]]: {{.*}} IMAGE_LOAD
236define amdgpu_ps void @cluster_image_load(<8 x i32> inreg %src, <8 x i32> inreg %dst, i32 %x, i32 %y) {
237; GFX9-LABEL: cluster_image_load:
238; GFX9:       ; %bb.0: ; %entry
239; GFX9-NEXT:    v_add_u32_e32 v2, 1, v0
240; GFX9-NEXT:    v_add_u32_e32 v3, 1, v1
241; GFX9-NEXT:    v_add_u32_e32 v6, 2, v0
242; GFX9-NEXT:    v_add_u32_e32 v7, 2, v1
243; GFX9-NEXT:    image_load v[2:5], v[2:3], s[0:7] dmask:0xf unorm
244; GFX9-NEXT:    image_load v[6:9], v[6:7], s[0:7] dmask:0xf unorm
245; GFX9-NEXT:    s_waitcnt vmcnt(0)
246; GFX9-NEXT:    v_add_f32_e32 v5, v5, v9
247; GFX9-NEXT:    v_add_f32_e32 v4, v4, v8
248; GFX9-NEXT:    v_add_f32_e32 v3, v3, v7
249; GFX9-NEXT:    v_add_f32_e32 v2, v2, v6
250; GFX9-NEXT:    image_store v[2:5], v[0:1], s[8:15] dmask:0xf unorm
251; GFX9-NEXT:    s_endpgm
252;
253; GFX10-LABEL: cluster_image_load:
254; GFX10:       ; %bb.0: ; %entry
255; GFX10-NEXT:    v_add_nc_u32_e32 v10, 1, v0
256; GFX10-NEXT:    v_add_nc_u32_e32 v11, 1, v1
257; GFX10-NEXT:    v_add_nc_u32_e32 v12, 2, v0
258; GFX10-NEXT:    v_add_nc_u32_e32 v13, 2, v1
259; GFX10-NEXT:    s_clause 0x1
260; GFX10-NEXT:    image_load v[2:5], v[10:11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
261; GFX10-NEXT:    image_load v[6:9], v[12:13], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
262; GFX10-NEXT:    s_waitcnt vmcnt(0)
263; GFX10-NEXT:    v_add_f32_e32 v5, v5, v9
264; GFX10-NEXT:    v_add_f32_e32 v4, v4, v8
265; GFX10-NEXT:    v_add_f32_e32 v3, v3, v7
266; GFX10-NEXT:    v_add_f32_e32 v2, v2, v6
267; GFX10-NEXT:    image_store v[2:5], v[0:1], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
268; GFX10-NEXT:    s_endpgm
269entry:
270  %x1 = add i32 %x, 1
271  %y1 = add i32 %y, 1
272  %val1 = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %x1, i32 %y1, <8 x i32> %src, i32 0, i32 0)
273  %x2 = add i32 %x, 2
274  %y2 = add i32 %y, 2
275  %val2 = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %x2, i32 %y2, <8 x i32> %src, i32 0, i32 0)
276  %val = fadd fast <4 x float> %val1, %val2
277  call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)
278  ret void
279}
280
281; Don't cluster loads from different textures
282; DBG-LABEL: no_cluster_image_load:
283; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
284; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
285; DBG-NOT: {{^}}Cluster ld/st
286define amdgpu_ps void @no_cluster_image_load(<8 x i32> inreg %src1, <8 x i32> inreg %src2, <8 x i32> inreg %dst, i32 %x, i32 %y) {
287; GFX9-LABEL: no_cluster_image_load:
288; GFX9:       ; %bb.0: ; %entry
289; GFX9-NEXT:    v_mov_b32_e32 v2, 0
290; GFX9-NEXT:    image_load_mip v[3:6], v[0:2], s[0:7] dmask:0xf unorm
291; GFX9-NEXT:    image_load_mip v[7:10], v[0:2], s[8:15] dmask:0xf unorm
292; GFX9-NEXT:    s_waitcnt vmcnt(0)
293; GFX9-NEXT:    v_add_f32_e32 v6, v6, v10
294; GFX9-NEXT:    v_add_f32_e32 v5, v5, v9
295; GFX9-NEXT:    v_add_f32_e32 v4, v4, v8
296; GFX9-NEXT:    v_add_f32_e32 v3, v3, v7
297; GFX9-NEXT:    image_store v[3:6], v[0:1], s[16:23] dmask:0xf unorm
298; GFX9-NEXT:    s_endpgm
299;
300; GFX10-LABEL: no_cluster_image_load:
301; GFX10:       ; %bb.0: ; %entry
302; GFX10-NEXT:    v_mov_b32_e32 v10, 0
303; GFX10-NEXT:    image_load_mip v[2:5], [v0, v1, v10], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
304; GFX10-NEXT:    image_load_mip v[6:9], [v0, v1, v10], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
305; GFX10-NEXT:    s_waitcnt vmcnt(0)
306; GFX10-NEXT:    v_add_f32_e32 v5, v5, v9
307; GFX10-NEXT:    v_add_f32_e32 v4, v4, v8
308; GFX10-NEXT:    v_add_f32_e32 v3, v3, v7
309; GFX10-NEXT:    v_add_f32_e32 v2, v2, v6
310; GFX10-NEXT:    image_store v[2:5], v[0:1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
311; GFX10-NEXT:    s_endpgm
312entry:
313  %val1 = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %x, i32 %y, i32 0, <8 x i32> %src1, i32 0, i32 0)
314  %val2 = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %x, i32 %y, i32 0, <8 x i32> %src2, i32 0, i32 0)
315  %val = fadd fast <4 x float> %val1, %val2
316  call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)
317  ret void
318}
319
320; Cluster loads from the same texture and sampler with different coordinates
321; DBG-LABEL: cluster_image_sample:
322; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
323; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
324; DBG: {{^}}Cluster ld/st [[SU1:SU\([0-9]+\)]] - [[SU2:SU\([0-9]+\)]]
325; DBG: {{^}}[[SU1]]: {{.*}} IMAGE_SAMPLE
326; DBG: {{^}}[[SU2]]: {{.*}} IMAGE_SAMPLE
327define amdgpu_ps void @cluster_image_sample(<8 x i32> inreg %src, <4 x i32> inreg %smp, <8 x i32> inreg %dst, i32 %x, i32 %y) {
328; GFX9-LABEL: cluster_image_sample:
329; GFX9:       ; %bb.0: ; %entry
330; GFX9-NEXT:    v_cvt_f32_i32_e32 v8, v0
331; GFX9-NEXT:    v_cvt_f32_i32_e32 v9, v1
332; GFX9-NEXT:    v_mov_b32_e32 v4, 0
333; GFX9-NEXT:    v_mov_b32_e32 v5, v4
334; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v8
335; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v9
336; GFX9-NEXT:    v_mov_b32_e32 v6, v4
337; GFX9-NEXT:    v_mov_b32_e32 v7, v4
338; GFX9-NEXT:    v_add_f32_e32 v8, 2.0, v8
339; GFX9-NEXT:    v_add_f32_e32 v9, 2.0, v9
340; GFX9-NEXT:    v_mov_b32_e32 v10, 1.0
341; GFX9-NEXT:    v_mov_b32_e32 v11, v10
342; GFX9-NEXT:    v_mov_b32_e32 v12, v10
343; GFX9-NEXT:    v_mov_b32_e32 v13, v10
344; GFX9-NEXT:    image_sample_d v[2:5], v[2:7], s[0:7], s[8:11] dmask:0xf
345; GFX9-NEXT:    image_sample_d v[6:9], v[8:13], s[0:7], s[8:11] dmask:0xf
346; GFX9-NEXT:    s_waitcnt vmcnt(0)
347; GFX9-NEXT:    v_add_f32_e32 v5, v5, v9
348; GFX9-NEXT:    v_add_f32_e32 v4, v4, v8
349; GFX9-NEXT:    v_add_f32_e32 v3, v3, v7
350; GFX9-NEXT:    v_add_f32_e32 v2, v2, v6
351; GFX9-NEXT:    image_store v[2:5], v[0:1], s[12:19] dmask:0xf unorm
352; GFX9-NEXT:    s_endpgm
353;
354; GFX10-LABEL: cluster_image_sample:
355; GFX10:       ; %bb.0: ; %entry
356; GFX10-NEXT:    v_cvt_f32_i32_e32 v8, v0
357; GFX10-NEXT:    v_cvt_f32_i32_e32 v9, v1
358; GFX10-NEXT:    v_mov_b32_e32 v4, 0
359; GFX10-NEXT:    v_mov_b32_e32 v10, 1.0
360; GFX10-NEXT:    v_add_f32_e32 v2, 1.0, v8
361; GFX10-NEXT:    v_add_f32_e32 v3, 1.0, v9
362; GFX10-NEXT:    v_mov_b32_e32 v5, v4
363; GFX10-NEXT:    v_mov_b32_e32 v6, v4
364; GFX10-NEXT:    v_mov_b32_e32 v7, v4
365; GFX10-NEXT:    v_add_f32_e32 v8, 2.0, v8
366; GFX10-NEXT:    v_add_f32_e32 v9, 2.0, v9
367; GFX10-NEXT:    v_mov_b32_e32 v11, v10
368; GFX10-NEXT:    v_mov_b32_e32 v12, v10
369; GFX10-NEXT:    v_mov_b32_e32 v13, v10
370; GFX10-NEXT:    s_clause 0x1
371; GFX10-NEXT:    image_sample_d v[14:17], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
372; GFX10-NEXT:    image_sample_d v[18:21], v[8:13], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
373; GFX10-NEXT:    s_waitcnt vmcnt(0)
374; GFX10-NEXT:    v_add_f32_e32 v5, v17, v21
375; GFX10-NEXT:    v_add_f32_e32 v4, v16, v20
376; GFX10-NEXT:    v_add_f32_e32 v3, v15, v19
377; GFX10-NEXT:    v_add_f32_e32 v2, v14, v18
378; GFX10-NEXT:    image_store v[2:5], v[0:1], s[12:19] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
379; GFX10-NEXT:    s_endpgm
380entry:
381  %s = sitofp i32 %x to float
382  %t = sitofp i32 %y to float
383  %s1 = fadd float %s, 1.0
384  %t1 = fadd float %t, 1.0
385  %val1 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32 15, float %s1, float %t1, float 0.0, float 0.0, float 0.0, float 0.0, <8 x i32> %src, <4 x i32> %smp, i1 false, i32 0, i32 0)
386  %s2 = fadd float %s, 2.0
387  %t2 = fadd float %t, 2.0
388  %val2 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32 15, float %s2, float %t2, float 1.0, float 1.0, float 1.0, float 1.0, <8 x i32> %src, <4 x i32> %smp, i1 false, i32 0, i32 0)
389  %val = fadd fast <4 x float> %val1, %val2
390  call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)
391  ret void
392}
393
394declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg)
395declare <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg)
396declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32)
397declare void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg)
398