1; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -debug-only=machine-scheduler < %s 2> %t | FileCheck --enable-var-scope --check-prefixes=CHECK,GCN %s 2; RUN: FileCheck --enable-var-scope --check-prefixes=CHECK,DBG %s < %t 3; REQUIRES: asserts 4 5; CHECK-LABEL: {{^}}cluster_load_cluster_store: 6define amdgpu_kernel void @cluster_load_cluster_store(i32* noalias %lb, i32* noalias %sb) { 7bb: 8; DBG: Cluster ld/st SU(1) - SU(2) 9 10; DBG: Cluster ld/st SU([[L1:[0-9]+]]) - SU([[L2:[0-9]+]]) 11; DBG: Cluster ld/st SU([[L2]]) - SU([[L3:[0-9]+]]) 12; DBG: Cluster ld/st SU([[L3]]) - SU([[L4:[0-9]+]]) 13; GCN: flat_load_dword [[LD1:v[0-9]+]], v[{{[0-9:]+}}] 14; GCN-NEXT: flat_load_dword [[LD2:v[0-9]+]], v[{{[0-9:]+}}] offset:8 15; GCN-NEXT: flat_load_dword [[LD3:v[0-9]+]], v[{{[0-9:]+}}] offset:16 16; GCN-NEXT: flat_load_dword [[LD4:v[0-9]+]], v[{{[0-9:]+}}] offset:24 17 %la0 = getelementptr inbounds i32, i32* %lb, i32 0 18 %ld0 = load i32, i32* %la0 19 %la1 = getelementptr inbounds i32, i32* %lb, i32 2 20 %ld1 = load i32, i32* %la1 21 %la2 = getelementptr inbounds i32, i32* %lb, i32 4 22 %ld2 = load i32, i32* %la2 23 %la3 = getelementptr inbounds i32, i32* %lb, i32 6 24 %ld3 = load i32, i32* %la3 25 26; DBG: Cluster ld/st SU([[S1:[0-9]+]]) - SU([[S2:[0-9]+]]) 27; DBG: Cluster ld/st SU([[S2]]) - SU([[S3:[0-9]+]]) 28; DBG: Cluster ld/st SU([[S3]]) - SU([[S4:[0-9]+]]) 29; GCN: flat_store_dword v[{{[0-9:]+}}], [[LD1]] 30; GCN-NEXT: flat_store_dword v[{{[0-9:]+}}], [[LD2]] offset:8 31; GCN-NEXT: flat_store_dword v[{{[0-9:]+}}], [[LD3]] offset:16 32; GCN-NEXT: flat_store_dword v[{{[0-9:]+}}], [[LD4]] offset:24 33 %sa0 = getelementptr inbounds i32, i32* %sb, i32 0 34 store i32 %ld0, i32* %sa0 35 %sa1 = getelementptr inbounds i32, i32* %sb, i32 2 36 store i32 %ld1, i32* %sa1 37 %sa2 = getelementptr inbounds i32, i32* %sb, i32 4 38 store i32 %ld2, i32* %sa2 39 %sa3 = getelementptr inbounds i32, i32* %sb, i32 6 40 store i32 %ld3, i32* %sa3 41 42 ret void 43} 44 45; CHECK-LABEL: {{^}}cluster_load_valu_cluster_store: 46define amdgpu_kernel void @cluster_load_valu_cluster_store(i32* noalias %lb, i32* noalias %sb) { 47bb: 48; DBG: Cluster ld/st SU(1) - SU(2) 49 50; DBG: Cluster ld/st SU([[L1:[0-9]+]]) - SU([[L2:[0-9]+]]) 51; DBG: Cluster ld/st SU([[L2]]) - SU([[L3:[0-9]+]]) 52; DBG: Cluster ld/st SU([[L3]]) - SU([[L4:[0-9]+]]) 53; GCN: flat_load_dword [[LD1:v[0-9]+]], v[{{[0-9:]+}}] 54; GCN-NEXT: flat_load_dword [[LD2:v[0-9]+]], v[{{[0-9:]+}}] offset:8 55; GCN-NEXT: flat_load_dword [[LD3:v[0-9]+]], v[{{[0-9:]+}}] offset:16 56; GCN-NEXT: flat_load_dword [[LD4:v[0-9]+]], v[{{[0-9:]+}}] offset:24 57 %la0 = getelementptr inbounds i32, i32* %lb, i32 0 58 %ld0 = load i32, i32* %la0 59 %la1 = getelementptr inbounds i32, i32* %lb, i32 2 60 %ld1 = load i32, i32* %la1 61 %la2 = getelementptr inbounds i32, i32* %lb, i32 4 62 %ld2 = load i32, i32* %la2 63 %la3 = getelementptr inbounds i32, i32* %lb, i32 6 64 %ld3 = load i32, i32* %la3 65 66; DBG: Cluster ld/st SU([[S1:[0-9]+]]) - SU([[S2:[0-9]+]]) 67; DBG: Cluster ld/st SU([[S2]]) - SU([[S3:[0-9]+]]) 68; DBG: Cluster ld/st SU([[S3]]) - SU([[S4:[0-9]+]]) 69; GCN: v_add_u32_e32 [[ST2:v[0-9]+]], 1, [[LD2]] 70; GCN: flat_store_dword v[{{[0-9:]+}}], [[LD1]] 71; GCN-NEXT: flat_store_dword v[{{[0-9:]+}}], [[ST2]] offset:8 72; GCN-NEXT: flat_store_dword v[{{[0-9:]+}}], [[LD3]] offset:16 73; GCN-NEXT: flat_store_dword v[{{[0-9:]+}}], [[LD4]] offset:24 74 %sa0 = getelementptr inbounds i32, i32* %sb, i32 0 75 store i32 %ld0, i32* %sa0 76 %sa1 = getelementptr inbounds i32, i32* %sb, i32 2 77 %add = add i32 %ld1, 1 78 store i32 %add, i32* %sa1 79 %sa2 = getelementptr inbounds i32, i32* %sb, i32 4 80 store i32 %ld2, i32* %sa2 81 %sa3 = getelementptr inbounds i32, i32* %sb, i32 6 82 store i32 %ld3, i32* %sa3 83 84 ret void 85} 86 87; Cluster loads from the same texture with different coordinates 88; CHECK-LABEL: {{^}}cluster_image_load: 89; DBG: {{^}}Cluster ld/st [[SU1:SU\([0-9]+\)]] - [[SU2:SU\([0-9]+\)]] 90; DBG: {{^}}[[SU1]]: {{.*}} IMAGE_LOAD 91; DBG: {{^}}[[SU2]]: {{.*}} IMAGE_LOAD 92; GCN: image_load v 93; GCN-NEXT: image_load v 94define amdgpu_ps void @cluster_image_load(<8 x i32> inreg %src, <8 x i32> inreg %dst, i32 %x, i32 %y) { 95entry: 96 %x1 = add i32 %x, 1 97 %y1 = add i32 %y, 1 98 %val1 = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %x1, i32 %y1, i32 0, <8 x i32> %src, i32 0, i32 0) 99 %x2 = add i32 %x, 2 100 %y2 = add i32 %y, 2 101 %val2 = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %x2, i32 %y2, i32 0, <8 x i32> %src, i32 0, i32 0) 102 %val = fadd fast <4 x float> %val1, %val2 103 call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0) 104 ret void 105} 106 107; Don't cluster loads from different textures 108; CHECK-LABEL: {{^}}no_cluster_image_load: 109; DBG-NOT: {{^}}Cluster ld/st 110define amdgpu_ps void @no_cluster_image_load(<8 x i32> inreg %src1, <8 x i32> inreg %src2, <8 x i32> inreg %dst, i32 %x, i32 %y) { 111entry: 112 %val1 = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %x, i32 %y, i32 0, <8 x i32> %src1, i32 0, i32 0) 113 %val2 = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %x, i32 %y, i32 0, <8 x i32> %src2, i32 0, i32 0) 114 %val = fadd fast <4 x float> %val1, %val2 115 call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0) 116 ret void 117} 118 119; Cluster loads from the same texture and sampler with different coordinates 120; CHECK-LABEL: {{^}}cluster_image_sample: 121; DBG: {{^}}Cluster ld/st [[SU1:SU\([0-9]+\)]] - [[SU2:SU\([0-9]+\)]] 122; DBG: {{^}}[[SU1]]: {{.*}} IMAGE_SAMPLE 123; DBG: {{^}}[[SU2]]: {{.*}} IMAGE_SAMPLE 124; GCN: image_sample_d 125; GCN-NEXT: image_sample_d 126define amdgpu_ps void @cluster_image_sample(<8 x i32> inreg %src, <4 x i32> inreg %smp, <8 x i32> inreg %dst, i32 %x, i32 %y) { 127entry: 128 %s = sitofp i32 %x to float 129 %t = sitofp i32 %y to float 130 %s1 = fadd float %s, 1.0 131 %t1 = fadd float %t, 1.0 132 %val1 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32 15, float %s1, float %t1, float 0.0, float 0.0, float 0.0, float 0.0, <8 x i32> %src, <4 x i32> %smp, i1 false, i32 0, i32 0) 133 %s2 = fadd float %s, 2.0 134 %t2 = fadd float %t, 2.0 135 %val2 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32 15, float %s2, float %t2, float 1.0, float 1.0, float 1.0, float 1.0, <8 x i32> %src, <4 x i32> %smp, i1 false, i32 0, i32 0) 136 %val = fadd fast <4 x float> %val1, %val2 137 call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0) 138 ret void 139} 140 141declare <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) 142declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) 143declare void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) 144