1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-xnack -verify-machineinstrs -debug-only=machine-scheduler < %s 2> %t | FileCheck --enable-var-scope --check-prefix=GFX9 %s
3; RUN: FileCheck --enable-var-scope --check-prefix=DBG %s < %t
4; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -debug-only=machine-scheduler < %s 2> %t | FileCheck --enable-var-scope --check-prefix=GFX10 %s
5; RUN: FileCheck --enable-var-scope --check-prefix=DBG %s < %t
6; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -debug-only=machine-scheduler < %s 2> %t | FileCheck --enable-var-scope --check-prefix=GFX11 %s
7; RUN: FileCheck --enable-var-scope --check-prefixes=DBG,DBG11 %s < %t
8; REQUIRES: asserts
9
10; FIXME: Verifier error with xnack enabled.
11
12; DBG-LABEL: cluster_load_cluster_store:
13
14; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
15; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
16; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
17; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
18; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
19; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
20
21; DBG: Cluster ld/st SU(1) - SU(2)
22
23; DBG: Cluster ld/st SU([[L1:[0-9]+]]) - SU([[L2:[0-9]+]])
24; DBG: Cluster ld/st SU([[L2]]) - SU([[L3:[0-9]+]])
25; DBG: Cluster ld/st SU([[L3]]) - SU([[L4:[0-9]+]])
26
27; DBG11: Cluster ld/st SU([[S1:[0-9]+]]) - SU([[S2:[0-9]+]])
28; DBG11: Cluster ld/st SU([[S2]]) - SU([[S3:[0-9]+]])
29; DBG11: Cluster ld/st SU([[S3]]) - SU([[S4:[0-9]+]])
30
31; DBG-NOT: Cluster ld/st
32
33define amdgpu_kernel void @cluster_load_cluster_store(i32* noalias %lb, i32* noalias %sb) {
34; GFX9-LABEL: cluster_load_cluster_store:
35; GFX9:       ; %bb.0: ; %bb
36; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
37; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
38; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
39; GFX9-NEXT:    v_mov_b32_e32 v0, s2
40; GFX9-NEXT:    v_mov_b32_e32 v1, s3
41; GFX9-NEXT:    flat_load_dword v2, v[0:1]
42; GFX9-NEXT:    flat_load_dword v3, v[0:1] offset:8
43; GFX9-NEXT:    flat_load_dword v4, v[0:1] offset:16
44; GFX9-NEXT:    flat_load_dword v5, v[0:1] offset:24
45; GFX9-NEXT:    v_mov_b32_e32 v0, s0
46; GFX9-NEXT:    v_mov_b32_e32 v1, s1
47; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
48; GFX9-NEXT:    flat_store_dword v[0:1], v2
49; GFX9-NEXT:    flat_store_dword v[0:1], v3 offset:8
50; GFX9-NEXT:    flat_store_dword v[0:1], v4 offset:16
51; GFX9-NEXT:    flat_store_dword v[0:1], v5 offset:24
52; GFX9-NEXT:    s_endpgm
53;
54; GFX10-LABEL: cluster_load_cluster_store:
55; GFX10:       ; %bb.0: ; %bb
56; GFX10-NEXT:    s_clause 0x1
57; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
58; GFX10-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
59; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
60; GFX10-NEXT:    s_add_u32 s0, s2, 8
61; GFX10-NEXT:    s_addc_u32 s1, s3, 0
62; GFX10-NEXT:    s_add_u32 s6, s2, 16
63; GFX10-NEXT:    v_mov_b32_e32 v3, s1
64; GFX10-NEXT:    s_addc_u32 s7, s3, 0
65; GFX10-NEXT:    v_mov_b32_e32 v0, s2
66; GFX10-NEXT:    v_mov_b32_e32 v2, s0
67; GFX10-NEXT:    s_add_u32 s0, s2, 24
68; GFX10-NEXT:    v_mov_b32_e32 v1, s3
69; GFX10-NEXT:    s_addc_u32 s1, s3, 0
70; GFX10-NEXT:    v_mov_b32_e32 v4, s6
71; GFX10-NEXT:    v_mov_b32_e32 v5, s7
72; GFX10-NEXT:    v_mov_b32_e32 v7, s1
73; GFX10-NEXT:    v_mov_b32_e32 v6, s0
74; GFX10-NEXT:    s_clause 0x3
75; GFX10-NEXT:    flat_load_dword v8, v[0:1]
76; GFX10-NEXT:    flat_load_dword v9, v[2:3]
77; GFX10-NEXT:    flat_load_dword v10, v[4:5]
78; GFX10-NEXT:    flat_load_dword v11, v[6:7]
79; GFX10-NEXT:    s_add_u32 s0, s4, 8
80; GFX10-NEXT:    s_addc_u32 s1, s5, 0
81; GFX10-NEXT:    v_mov_b32_e32 v0, s4
82; GFX10-NEXT:    v_mov_b32_e32 v3, s1
83; GFX10-NEXT:    v_mov_b32_e32 v2, s0
84; GFX10-NEXT:    s_add_u32 s0, s4, 16
85; GFX10-NEXT:    s_addc_u32 s1, s5, 0
86; GFX10-NEXT:    s_add_u32 s2, s4, 24
87; GFX10-NEXT:    v_mov_b32_e32 v1, s5
88; GFX10-NEXT:    s_addc_u32 s3, s5, 0
89; GFX10-NEXT:    v_mov_b32_e32 v5, s1
90; GFX10-NEXT:    v_mov_b32_e32 v4, s0
91; GFX10-NEXT:    v_mov_b32_e32 v7, s3
92; GFX10-NEXT:    v_mov_b32_e32 v6, s2
93; GFX10-NEXT:    s_waitcnt vmcnt(3) lgkmcnt(3)
94; GFX10-NEXT:    flat_store_dword v[0:1], v8
95; GFX10-NEXT:    s_waitcnt vmcnt(2) lgkmcnt(3)
96; GFX10-NEXT:    flat_store_dword v[2:3], v9
97; GFX10-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(3)
98; GFX10-NEXT:    flat_store_dword v[4:5], v10
99; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(3)
100; GFX10-NEXT:    flat_store_dword v[6:7], v11
101; GFX10-NEXT:    s_endpgm
102;
103; GFX11-LABEL: cluster_load_cluster_store:
104; GFX11:       ; %bb.0: ; %bb
105; GFX11-NEXT:    s_clause 0x1
106; GFX11-NEXT:    s_load_b64 s[2:3], s[0:1], 0x24
107; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x2c
108; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
109; GFX11-NEXT:    v_mov_b32_e32 v0, s2
110; GFX11-NEXT:    v_mov_b32_e32 v1, s3
111; GFX11-NEXT:    s_clause 0x3
112; GFX11-NEXT:    flat_load_b32 v2, v[0:1]
113; GFX11-NEXT:    flat_load_b32 v3, v[0:1] offset:8
114; GFX11-NEXT:    flat_load_b32 v4, v[0:1] offset:16
115; GFX11-NEXT:    flat_load_b32 v5, v[0:1] offset:24
116; GFX11-NEXT:    v_mov_b32_e32 v0, s0
117; GFX11-NEXT:    v_mov_b32_e32 v1, s1
118; GFX11-NEXT:    s_waitcnt vmcnt(3) lgkmcnt(3)
119; GFX11-NEXT:    flat_store_b32 v[0:1], v2
120; GFX11-NEXT:    s_waitcnt vmcnt(2) lgkmcnt(3)
121; GFX11-NEXT:    flat_store_b32 v[0:1], v3 offset:8
122; GFX11-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(3)
123; GFX11-NEXT:    flat_store_b32 v[0:1], v4 offset:16
124; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(3)
125; GFX11-NEXT:    flat_store_b32 v[0:1], v5 offset:24
126; GFX11-NEXT:    s_endpgm
127bb:
128  %la0 = getelementptr inbounds i32, i32* %lb, i32 0
129  %ld0 = load i32, i32* %la0
130  %la1 = getelementptr inbounds i32, i32* %lb, i32 2
131  %ld1 = load i32, i32* %la1
132  %la2 = getelementptr inbounds i32, i32* %lb, i32 4
133  %ld2 = load i32, i32* %la2
134  %la3 = getelementptr inbounds i32, i32* %lb, i32 6
135  %ld3 = load i32, i32* %la3
136
137  %sa0 = getelementptr inbounds i32, i32* %sb, i32 0
138  store i32 %ld0, i32* %sa0
139  %sa1 = getelementptr inbounds i32, i32* %sb, i32 2
140  store i32 %ld1, i32* %sa1
141  %sa2 = getelementptr inbounds i32, i32* %sb, i32 4
142  store i32 %ld2, i32* %sa2
143  %sa3 = getelementptr inbounds i32, i32* %sb, i32 6
144  store i32 %ld3, i32* %sa3
145
146  ret void
147}
148
149; DBG-LABEL: cluster_load_valu_cluster_store:
150
151; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
152; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
153; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
154; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
155; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
156; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
157
158; DBG: Cluster ld/st SU(1) - SU(2)
159
160; DBG: Cluster ld/st SU([[L1:[0-9]+]]) - SU([[L2:[0-9]+]])
161; DBG: Cluster ld/st SU([[L2]]) - SU([[L3:[0-9]+]])
162; DBG: Cluster ld/st SU([[L3]]) - SU([[L4:[0-9]+]])
163
164; DBG11: Cluster ld/st SU([[S1:[0-9]+]]) - SU([[S2:[0-9]+]])
165; DBG11: Cluster ld/st SU([[S2]]) - SU([[S3:[0-9]+]])
166; DBG11: Cluster ld/st SU([[S3]]) - SU([[S4:[0-9]+]])
167
168; DBG-NOT: Cluster ld/st
169
170define amdgpu_kernel void @cluster_load_valu_cluster_store(i32* noalias %lb, i32* noalias %sb) {
171; GFX9-LABEL: cluster_load_valu_cluster_store:
172; GFX9:       ; %bb.0: ; %bb
173; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
174; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
175; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
176; GFX9-NEXT:    v_mov_b32_e32 v0, s2
177; GFX9-NEXT:    v_mov_b32_e32 v1, s3
178; GFX9-NEXT:    flat_load_dword v2, v[0:1]
179; GFX9-NEXT:    flat_load_dword v3, v[0:1] offset:8
180; GFX9-NEXT:    flat_load_dword v4, v[0:1] offset:16
181; GFX9-NEXT:    flat_load_dword v5, v[0:1] offset:24
182; GFX9-NEXT:    v_mov_b32_e32 v0, s0
183; GFX9-NEXT:    v_mov_b32_e32 v1, s1
184; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
185; GFX9-NEXT:    flat_store_dword v[0:1], v2
186; GFX9-NEXT:    v_add_u32_e32 v2, 1, v3
187; GFX9-NEXT:    flat_store_dword v[0:1], v4 offset:16
188; GFX9-NEXT:    flat_store_dword v[0:1], v2 offset:8
189; GFX9-NEXT:    flat_store_dword v[0:1], v5 offset:24
190; GFX9-NEXT:    s_endpgm
191;
192; GFX10-LABEL: cluster_load_valu_cluster_store:
193; GFX10:       ; %bb.0: ; %bb
194; GFX10-NEXT:    s_clause 0x1
195; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
196; GFX10-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
197; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
198; GFX10-NEXT:    s_add_u32 s0, s2, 8
199; GFX10-NEXT:    s_addc_u32 s1, s3, 0
200; GFX10-NEXT:    s_add_u32 s6, s2, 16
201; GFX10-NEXT:    v_mov_b32_e32 v3, s1
202; GFX10-NEXT:    v_mov_b32_e32 v2, s0
203; GFX10-NEXT:    s_addc_u32 s7, s3, 0
204; GFX10-NEXT:    s_add_u32 s0, s2, 24
205; GFX10-NEXT:    v_mov_b32_e32 v0, s2
206; GFX10-NEXT:    s_addc_u32 s1, s3, 0
207; GFX10-NEXT:    v_mov_b32_e32 v1, s3
208; GFX10-NEXT:    v_mov_b32_e32 v4, s6
209; GFX10-NEXT:    v_mov_b32_e32 v5, s7
210; GFX10-NEXT:    flat_load_dword v6, v[2:3]
211; GFX10-NEXT:    v_mov_b32_e32 v3, s1
212; GFX10-NEXT:    v_mov_b32_e32 v2, s0
213; GFX10-NEXT:    s_clause 0x2
214; GFX10-NEXT:    flat_load_dword v8, v[0:1]
215; GFX10-NEXT:    flat_load_dword v9, v[4:5]
216; GFX10-NEXT:    flat_load_dword v10, v[2:3]
217; GFX10-NEXT:    s_add_u32 s0, s4, 8
218; GFX10-NEXT:    s_addc_u32 s1, s5, 0
219; GFX10-NEXT:    s_add_u32 s2, s4, 16
220; GFX10-NEXT:    v_mov_b32_e32 v3, s1
221; GFX10-NEXT:    s_addc_u32 s3, s5, 0
222; GFX10-NEXT:    v_mov_b32_e32 v0, s4
223; GFX10-NEXT:    v_mov_b32_e32 v2, s0
224; GFX10-NEXT:    s_add_u32 s0, s4, 24
225; GFX10-NEXT:    v_mov_b32_e32 v1, s5
226; GFX10-NEXT:    v_mov_b32_e32 v5, s3
227; GFX10-NEXT:    s_addc_u32 s1, s5, 0
228; GFX10-NEXT:    v_mov_b32_e32 v4, s2
229; GFX10-NEXT:    s_waitcnt vmcnt(3) lgkmcnt(3)
230; GFX10-NEXT:    v_add_nc_u32_e32 v11, 1, v6
231; GFX10-NEXT:    v_mov_b32_e32 v7, s1
232; GFX10-NEXT:    v_mov_b32_e32 v6, s0
233; GFX10-NEXT:    s_waitcnt vmcnt(2) lgkmcnt(2)
234; GFX10-NEXT:    flat_store_dword v[0:1], v8
235; GFX10-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(2)
236; GFX10-NEXT:    flat_store_dword v[4:5], v9
237; GFX10-NEXT:    flat_store_dword v[2:3], v11
238; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(3)
239; GFX10-NEXT:    flat_store_dword v[6:7], v10
240; GFX10-NEXT:    s_endpgm
241;
242; GFX11-LABEL: cluster_load_valu_cluster_store:
243; GFX11:       ; %bb.0: ; %bb
244; GFX11-NEXT:    s_clause 0x1
245; GFX11-NEXT:    s_load_b64 s[2:3], s[0:1], 0x24
246; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x2c
247; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
248; GFX11-NEXT:    v_mov_b32_e32 v0, s2
249; GFX11-NEXT:    v_mov_b32_e32 v1, s3
250; GFX11-NEXT:    s_clause 0x3
251; GFX11-NEXT:    flat_load_b32 v2, v[0:1] offset:8
252; GFX11-NEXT:    flat_load_b32 v3, v[0:1]
253; GFX11-NEXT:    flat_load_b32 v4, v[0:1] offset:16
254; GFX11-NEXT:    flat_load_b32 v5, v[0:1] offset:24
255; GFX11-NEXT:    v_mov_b32_e32 v0, s0
256; GFX11-NEXT:    v_mov_b32_e32 v1, s1
257; GFX11-NEXT:    s_waitcnt vmcnt(3) lgkmcnt(3)
258; GFX11-NEXT:    v_add_nc_u32_e32 v2, 1, v2
259; GFX11-NEXT:    s_waitcnt vmcnt(2) lgkmcnt(2)
260; GFX11-NEXT:    s_clause 0x1
261; GFX11-NEXT:    flat_store_b32 v[0:1], v3
262; GFX11-NEXT:    flat_store_b32 v[0:1], v2 offset:8
263; GFX11-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(3)
264; GFX11-NEXT:    flat_store_b32 v[0:1], v4 offset:16
265; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(3)
266; GFX11-NEXT:    flat_store_b32 v[0:1], v5 offset:24
267; GFX11-NEXT:    s_endpgm
268bb:
269  %la0 = getelementptr inbounds i32, i32* %lb, i32 0
270  %ld0 = load i32, i32* %la0
271  %la1 = getelementptr inbounds i32, i32* %lb, i32 2
272  %ld1 = load i32, i32* %la1
273  %la2 = getelementptr inbounds i32, i32* %lb, i32 4
274  %ld2 = load i32, i32* %la2
275  %la3 = getelementptr inbounds i32, i32* %lb, i32 6
276  %ld3 = load i32, i32* %la3
277
278  %sa0 = getelementptr inbounds i32, i32* %sb, i32 0
279  store i32 %ld0, i32* %sa0
280  %sa1 = getelementptr inbounds i32, i32* %sb, i32 2
281  %add = add i32 %ld1, 1
282  store i32 %add, i32* %sa1
283  %sa2 = getelementptr inbounds i32, i32* %sb, i32 4
284  store i32 %ld2, i32* %sa2
285  %sa3 = getelementptr inbounds i32, i32* %sb, i32 6
286  store i32 %ld3, i32* %sa3
287
288  ret void
289}
290
291; Cluster loads from the same texture with different coordinates
292; DBG-LABEL: cluster_image_load:
293; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
294; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
295; DBG: {{^}}Cluster ld/st [[SU1:SU\([0-9]+\)]] - [[SU2:SU\([0-9]+\)]]
296; DBG: {{^}}[[SU1]]: {{.*}} IMAGE_LOAD
297; DBG: {{^}}[[SU2]]: {{.*}} IMAGE_LOAD
298define amdgpu_ps void @cluster_image_load(<8 x i32> inreg %src, <8 x i32> inreg %dst, i32 %x, i32 %y) {
299; GFX9-LABEL: cluster_image_load:
300; GFX9:       ; %bb.0: ; %entry
301; GFX9-NEXT:    v_add_u32_e32 v2, 1, v0
302; GFX9-NEXT:    v_add_u32_e32 v3, 1, v1
303; GFX9-NEXT:    v_add_u32_e32 v6, 2, v0
304; GFX9-NEXT:    v_add_u32_e32 v7, 2, v1
305; GFX9-NEXT:    image_load v[2:5], v[2:3], s[0:7] dmask:0xf unorm
306; GFX9-NEXT:    image_load v[6:9], v[6:7], s[0:7] dmask:0xf unorm
307; GFX9-NEXT:    s_waitcnt vmcnt(0)
308; GFX9-NEXT:    v_add_f32_e32 v5, v5, v9
309; GFX9-NEXT:    v_add_f32_e32 v4, v4, v8
310; GFX9-NEXT:    v_add_f32_e32 v3, v3, v7
311; GFX9-NEXT:    v_add_f32_e32 v2, v2, v6
312; GFX9-NEXT:    image_store v[2:5], v[0:1], s[8:15] dmask:0xf unorm
313; GFX9-NEXT:    s_endpgm
314;
315; GFX10-LABEL: cluster_image_load:
316; GFX10:       ; %bb.0: ; %entry
317; GFX10-NEXT:    v_add_nc_u32_e32 v10, 1, v0
318; GFX10-NEXT:    v_add_nc_u32_e32 v11, 1, v1
319; GFX10-NEXT:    v_add_nc_u32_e32 v12, 2, v0
320; GFX10-NEXT:    v_add_nc_u32_e32 v13, 2, v1
321; GFX10-NEXT:    s_clause 0x1
322; GFX10-NEXT:    image_load v[2:5], v[10:11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
323; GFX10-NEXT:    image_load v[6:9], v[12:13], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
324; GFX10-NEXT:    s_waitcnt vmcnt(0)
325; GFX10-NEXT:    v_add_f32_e32 v5, v5, v9
326; GFX10-NEXT:    v_add_f32_e32 v4, v4, v8
327; GFX10-NEXT:    v_add_f32_e32 v3, v3, v7
328; GFX10-NEXT:    v_add_f32_e32 v2, v2, v6
329; GFX10-NEXT:    image_store v[2:5], v[0:1], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
330; GFX10-NEXT:    s_endpgm
331;
332; GFX11-LABEL: cluster_image_load:
333; GFX11:       ; %bb.0: ; %entry
334; GFX11-NEXT:    v_add_nc_u32_e32 v2, 1, v0
335; GFX11-NEXT:    v_add_nc_u32_e32 v3, 1, v1
336; GFX11-NEXT:    v_add_nc_u32_e32 v6, 2, v0
337; GFX11-NEXT:    v_add_nc_u32_e32 v7, 2, v1
338; GFX11-NEXT:    s_clause 0x1
339; GFX11-NEXT:    image_load v[2:5], v[2:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
340; GFX11-NEXT:    image_load v[6:9], v[6:7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
341; GFX11-NEXT:    s_waitcnt vmcnt(0)
342; GFX11-NEXT:    v_add_f32_e32 v5, v5, v9
343; GFX11-NEXT:    v_add_f32_e32 v4, v4, v8
344; GFX11-NEXT:    v_add_f32_e32 v3, v3, v7
345; GFX11-NEXT:    v_add_f32_e32 v2, v2, v6
346; GFX11-NEXT:    image_store v[2:5], v[0:1], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
347; GFX11-NEXT:    s_endpgm
348entry:
349  %x1 = add i32 %x, 1
350  %y1 = add i32 %y, 1
351  %val1 = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %x1, i32 %y1, <8 x i32> %src, i32 0, i32 0)
352  %x2 = add i32 %x, 2
353  %y2 = add i32 %y, 2
354  %val2 = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %x2, i32 %y2, <8 x i32> %src, i32 0, i32 0)
355  %val = fadd fast <4 x float> %val1, %val2
356  call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)
357  ret void
358}
359
360; Don't cluster loads from different textures
361; DBG-LABEL: no_cluster_image_load:
362; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
363; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
364; DBG-NOT: {{^}}Cluster ld/st
365define amdgpu_ps void @no_cluster_image_load(<8 x i32> inreg %src1, <8 x i32> inreg %src2, <8 x i32> inreg %dst, i32 %x, i32 %y) {
366; GFX9-LABEL: no_cluster_image_load:
367; GFX9:       ; %bb.0: ; %entry
368; GFX9-NEXT:    v_mov_b32_e32 v2, 0
369; GFX9-NEXT:    image_load_mip v[3:6], v[0:2], s[0:7] dmask:0xf unorm
370; GFX9-NEXT:    image_load_mip v[7:10], v[0:2], s[8:15] dmask:0xf unorm
371; GFX9-NEXT:    s_waitcnt vmcnt(0)
372; GFX9-NEXT:    v_add_f32_e32 v6, v6, v10
373; GFX9-NEXT:    v_add_f32_e32 v5, v5, v9
374; GFX9-NEXT:    v_add_f32_e32 v4, v4, v8
375; GFX9-NEXT:    v_add_f32_e32 v3, v3, v7
376; GFX9-NEXT:    image_store v[3:6], v[0:1], s[16:23] dmask:0xf unorm
377; GFX9-NEXT:    s_endpgm
378;
379; GFX10-LABEL: no_cluster_image_load:
380; GFX10:       ; %bb.0: ; %entry
381; GFX10-NEXT:    v_mov_b32_e32 v10, 0
382; GFX10-NEXT:    image_load_mip v[2:5], [v0, v1, v10], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
383; GFX10-NEXT:    image_load_mip v[6:9], [v0, v1, v10], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
384; GFX10-NEXT:    s_waitcnt vmcnt(0)
385; GFX10-NEXT:    v_add_f32_e32 v5, v5, v9
386; GFX10-NEXT:    v_add_f32_e32 v4, v4, v8
387; GFX10-NEXT:    v_add_f32_e32 v3, v3, v7
388; GFX10-NEXT:    v_add_f32_e32 v2, v2, v6
389; GFX10-NEXT:    image_store v[2:5], v[0:1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
390; GFX10-NEXT:    s_endpgm
391;
392; GFX11-LABEL: no_cluster_image_load:
393; GFX11:       ; %bb.0: ; %entry
394; GFX11-NEXT:    v_mov_b32_e32 v6, 0
395; GFX11-NEXT:    image_load_mip v[2:5], [v0, v1, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
396; GFX11-NEXT:    image_load_mip v[6:9], [v0, v1, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
397; GFX11-NEXT:    s_waitcnt vmcnt(0)
398; GFX11-NEXT:    v_add_f32_e32 v5, v5, v9
399; GFX11-NEXT:    v_add_f32_e32 v4, v4, v8
400; GFX11-NEXT:    v_add_f32_e32 v3, v3, v7
401; GFX11-NEXT:    v_add_f32_e32 v2, v2, v6
402; GFX11-NEXT:    image_store v[2:5], v[0:1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
403; GFX11-NEXT:    s_endpgm
404entry:
405  %val1 = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %x, i32 %y, i32 0, <8 x i32> %src1, i32 0, i32 0)
406  %val2 = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %x, i32 %y, i32 0, <8 x i32> %src2, i32 0, i32 0)
407  %val = fadd fast <4 x float> %val1, %val2
408  call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)
409  ret void
410}
411
412; Cluster loads from the same texture and sampler with different coordinates
413; DBG-LABEL: cluster_image_sample:
414; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
415; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
416; DBG: {{^}}Cluster ld/st [[SU1:SU\([0-9]+\)]] - [[SU2:SU\([0-9]+\)]]
417; DBG: {{^}}[[SU1]]: {{.*}} IMAGE_SAMPLE
418; DBG: {{^}}[[SU2]]: {{.*}} IMAGE_SAMPLE
419define amdgpu_ps void @cluster_image_sample(<8 x i32> inreg %src, <4 x i32> inreg %smp, <8 x i32> inreg %dst, i32 %x, i32 %y) {
420; GFX9-LABEL: cluster_image_sample:
421; GFX9:       ; %bb.0: ; %entry
422; GFX9-NEXT:    v_cvt_f32_i32_e32 v8, v0
423; GFX9-NEXT:    v_cvt_f32_i32_e32 v9, v1
424; GFX9-NEXT:    v_mov_b32_e32 v4, 0
425; GFX9-NEXT:    v_mov_b32_e32 v5, v4
426; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v8
427; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v9
428; GFX9-NEXT:    v_mov_b32_e32 v6, v4
429; GFX9-NEXT:    v_mov_b32_e32 v7, v4
430; GFX9-NEXT:    v_add_f32_e32 v8, 2.0, v8
431; GFX9-NEXT:    v_add_f32_e32 v9, 2.0, v9
432; GFX9-NEXT:    v_mov_b32_e32 v10, 1.0
433; GFX9-NEXT:    v_mov_b32_e32 v11, v10
434; GFX9-NEXT:    v_mov_b32_e32 v12, v10
435; GFX9-NEXT:    v_mov_b32_e32 v13, v10
436; GFX9-NEXT:    image_sample_d v[2:5], v[2:7], s[0:7], s[8:11] dmask:0xf
437; GFX9-NEXT:    image_sample_d v[6:9], v[8:13], s[0:7], s[8:11] dmask:0xf
438; GFX9-NEXT:    s_waitcnt vmcnt(0)
439; GFX9-NEXT:    v_add_f32_e32 v5, v5, v9
440; GFX9-NEXT:    v_add_f32_e32 v4, v4, v8
441; GFX9-NEXT:    v_add_f32_e32 v3, v3, v7
442; GFX9-NEXT:    v_add_f32_e32 v2, v2, v6
443; GFX9-NEXT:    image_store v[2:5], v[0:1], s[12:19] dmask:0xf unorm
444; GFX9-NEXT:    s_endpgm
445;
446; GFX10-LABEL: cluster_image_sample:
447; GFX10:       ; %bb.0: ; %entry
448; GFX10-NEXT:    v_cvt_f32_i32_e32 v8, v0
449; GFX10-NEXT:    v_cvt_f32_i32_e32 v9, v1
450; GFX10-NEXT:    v_mov_b32_e32 v4, 0
451; GFX10-NEXT:    v_mov_b32_e32 v10, 1.0
452; GFX10-NEXT:    v_add_f32_e32 v2, 1.0, v8
453; GFX10-NEXT:    v_add_f32_e32 v3, 1.0, v9
454; GFX10-NEXT:    v_mov_b32_e32 v5, v4
455; GFX10-NEXT:    v_mov_b32_e32 v6, v4
456; GFX10-NEXT:    v_mov_b32_e32 v7, v4
457; GFX10-NEXT:    v_add_f32_e32 v8, 2.0, v8
458; GFX10-NEXT:    v_add_f32_e32 v9, 2.0, v9
459; GFX10-NEXT:    v_mov_b32_e32 v11, v10
460; GFX10-NEXT:    v_mov_b32_e32 v12, v10
461; GFX10-NEXT:    v_mov_b32_e32 v13, v10
462; GFX10-NEXT:    s_clause 0x1
463; GFX10-NEXT:    image_sample_d v[14:17], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
464; GFX10-NEXT:    image_sample_d v[18:21], v[8:13], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
465; GFX10-NEXT:    s_waitcnt vmcnt(0)
466; GFX10-NEXT:    v_add_f32_e32 v5, v17, v21
467; GFX10-NEXT:    v_add_f32_e32 v4, v16, v20
468; GFX10-NEXT:    v_add_f32_e32 v3, v15, v19
469; GFX10-NEXT:    v_add_f32_e32 v2, v14, v18
470; GFX10-NEXT:    image_store v[2:5], v[0:1], s[12:19] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
471; GFX10-NEXT:    s_endpgm
472;
473; GFX11-LABEL: cluster_image_sample:
474; GFX11:       ; %bb.0: ; %entry
475; GFX11-NEXT:    v_cvt_f32_i32_e32 v8, v0
476; GFX11-NEXT:    v_cvt_f32_i32_e32 v9, v1
477; GFX11-NEXT:    v_mov_b32_e32 v4, 0
478; GFX11-NEXT:    v_mov_b32_e32 v10, 1.0
479; GFX11-NEXT:    v_add_f32_e32 v2, 1.0, v8
480; GFX11-NEXT:    v_add_f32_e32 v3, 1.0, v9
481; GFX11-NEXT:    v_mov_b32_e32 v5, v4
482; GFX11-NEXT:    v_mov_b32_e32 v6, v4
483; GFX11-NEXT:    v_mov_b32_e32 v7, v4
484; GFX11-NEXT:    v_add_f32_e32 v8, 2.0, v8
485; GFX11-NEXT:    v_add_f32_e32 v9, 2.0, v9
486; GFX11-NEXT:    v_mov_b32_e32 v11, v10
487; GFX11-NEXT:    v_mov_b32_e32 v12, v10
488; GFX11-NEXT:    v_mov_b32_e32 v13, v10
489; GFX11-NEXT:    s_clause 0x1
490; GFX11-NEXT:    image_sample_d v[2:5], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
491; GFX11-NEXT:    image_sample_d v[6:9], v[8:13], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
492; GFX11-NEXT:    s_waitcnt vmcnt(0)
493; GFX11-NEXT:    v_add_f32_e32 v5, v5, v9
494; GFX11-NEXT:    v_add_f32_e32 v4, v4, v8
495; GFX11-NEXT:    v_add_f32_e32 v3, v3, v7
496; GFX11-NEXT:    v_add_f32_e32 v2, v2, v6
497; GFX11-NEXT:    image_store v[2:5], v[0:1], s[12:19] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
498; GFX11-NEXT:    s_endpgm
499entry:
500  %s = sitofp i32 %x to float
501  %t = sitofp i32 %y to float
502  %s1 = fadd float %s, 1.0
503  %t1 = fadd float %t, 1.0
504  %val1 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32 15, float %s1, float %t1, float 0.0, float 0.0, float 0.0, float 0.0, <8 x i32> %src, <4 x i32> %smp, i1 false, i32 0, i32 0)
505  %s2 = fadd float %s, 2.0
506  %t2 = fadd float %t, 2.0
507  %val2 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32 15, float %s2, float %t2, float 1.0, float 1.0, float 1.0, float 1.0, <8 x i32> %src, <4 x i32> %smp, i1 false, i32 0, i32 0)
508  %val = fadd fast <4 x float> %val1, %val2
509  call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)
510  ret void
511}
512
513declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg)
514declare <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg)
515declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32)
516declare void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg)
517