1; RUN: llc -march=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN-ISEL %s 2 3; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CISI %s 4; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s 5; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s 6; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10,GFX1010,GFX10W32 %s 7; RUN: llc -march=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize32 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10,GFX1030,GFX10W32 %s 8; RUN: llc -march=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10,GFX1030,GFX10W64 %s 9 10; GCN-ISEL-LABEL: name: sadd64rr 11; GCN-ISEL-LABEL: body: 12; GCN-ISEL-LABEL: bb.0.entry: 13; GCN-ISEL: S_ADD_U64_PSEUDO 14 15; GCN-LABEL: @sadd64rr 16; GCN: s_add_u32 17; GCN: s_addc_u32 18define amdgpu_kernel void @sadd64rr(i64 addrspace(1)* %out, i64 %a, i64 %b) { 19entry: 20 %add = add i64 %a, %b 21 store i64 %add, i64 addrspace(1)* %out 22 ret void 23} 24 25; GCN-ISEL-LABEL: name: sadd64ri 26; GCN-ISEL-LABEL: body: 27; GCN-ISEL-LABEL: bb.0.entry: 28; GCN-ISEL: S_ADD_U64_PSEUDO 29 30; GCN-LABEL: @sadd64ri 31; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x56789876 32; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x1234 33define amdgpu_kernel void @sadd64ri(i64 addrspace(1)* %out, i64 %a) { 34entry: 35 %add = add i64 20015998343286, %a 36 store i64 %add, i64 addrspace(1)* %out 37 ret void 38} 39 40; GCN-ISEL-LABEL: name: vadd64rr 41; GCN-ISEL-LABEL: body: 42; GCN-ISEL-LABEL: bb.0.entry: 43; GCN-ISEL: V_ADD_U64_PSEUDO 44 45; GCN-LABEL: @vadd64rr 46; 47; CISI: v_add_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} 48; CISI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc 49; 50; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} 51; VI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc 52; 53; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} 54; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc 55; 56; GFX10W32: v_add_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}} 57; GFX10W64: v_add_co_u32 v{{[0-9]+}}, [[CARRY:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, v{{[0-9]+}} 58; GFX1010: v_add_co_ci_u32_e64 v{{[0-9]+}}, [[CARRY]], s{{[0-9]+}}, 0, [[CARRY]] 59; GFX1030: v_add_co_ci_u32_e64 v{{[0-9]+}}, null, s{{[0-9]+}}, 0, [[CARRY]] 60define amdgpu_kernel void @vadd64rr(i64 addrspace(1)* %out, i64 %a) { 61entry: 62 %tid = call i32 @llvm.amdgcn.workitem.id.x() 63 %tid.ext = sext i32 %tid to i64 64 %add = add i64 %a, %tid.ext 65 store i64 %add, i64 addrspace(1)* %out 66 ret void 67} 68 69; GCN-ISEL-LABEL: name: vadd64ri 70; GCN-ISEL-LABEL: body: 71; GCN-ISEL-LABEL: bb.0.entry: 72; GCN-ISEL: V_ADD_U64_PSEUDO 73 74; GCN-LABEL: @vadd64ri 75; 76; CISI: v_add_i32_e32 v0, vcc, 0x56789876, v0 77; CISI: v_mov_b32_e32 v1, 0x1234 78; CISI: v_addc_u32_e32 v1, vcc, 0, v1, vcc 79; 80; VI: v_add_u32_e32 v0, vcc, 0x56789876, v0 81; VI: v_mov_b32_e32 v1, 0x1234 82; VI: v_addc_u32_e32 v1, vcc, 0, v1, vcc 83; 84; GFX9: v_add_co_u32_e32 v0, vcc, 0x56789876, v0 85; GFX9: v_mov_b32_e32 v1, 0x1234 86; GFX9: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 87; 88; GFX10W32: v_add_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], 0x56789876, v{{[0-9]+}} 89; GFX10W64: v_add_co_u32 v{{[0-9]+}}, [[CARRY:s\[[0-9]+:[0-9]+\]]], 0x56789876, v{{[0-9]+}} 90; GFX1010: v_add_co_ci_u32_e64 v{{[0-9]+}}, [[CARRY]], 0, 0x1234, [[CARRY]] 91; GFX1030: v_add_co_ci_u32_e64 v{{[0-9]+}}, null, 0, 0x1234, [[CARRY]] 92define amdgpu_kernel void @vadd64ri(i64 addrspace(1)* %out) { 93entry: 94 %tid = call i32 @llvm.amdgcn.workitem.id.x() 95 %tid.ext = sext i32 %tid to i64 96 %add = add i64 20015998343286, %tid.ext 97 store i64 %add, i64 addrspace(1)* %out 98 ret void 99} 100 101; GCN-ISEL-LABEL: name: suaddo32 102; GCN-ISEL-LABEL: body: 103; GCN-ISEL-LABEL: bb.0 104; GCN-ISEL: S_ADD_I32 105define amdgpu_kernel void @suaddo32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) #0 { 106 %uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b) 107 %val = extractvalue { i32, i1 } %uadd, 0 108 %carry = extractvalue { i32, i1 } %uadd, 1 109 store i32 %val, i32 addrspace(1)* %out, align 4 110 ret void 111} 112 113 114; GCN-ISEL-LABEL: name: uaddo32_vcc_user 115; GCN-ISEL-LABEL: body: 116; GCN-ISEL-LABEL: bb.0 117; GCN-ISEL: V_ADD_CO_U32_e64 118 119; below we check selection to v_add/addc 120; because the only user of VCC produced by the UADDOis v_cndmask. 121; We select to VALU form to avoid unnecessary s_cselect to copy SCC to VCC 122 123; GCN-LABEL: @uaddo32_vcc_user 124; 125; CISI: v_add_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} 126; CISI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc 127; 128; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} 129; VI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc 130; 131; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} 132; GFX9: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc 133; 134; GFX10W32: v_add_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}} 135; GFX10W64: v_add_co_u32 v{{[0-9]+}}, [[CARRY:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, s{{[0-9]+}} 136; GFX10: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, [[CARRY]] 137define amdgpu_kernel void @uaddo32_vcc_user(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) #0 { 138 %uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b) 139 %val = extractvalue { i32, i1 } %uadd, 0 140 %carry = extractvalue { i32, i1 } %uadd, 1 141 store i32 %val, i32 addrspace(1)* %out, align 4 142 store i1 %carry, i1 addrspace(1)* %carryout 143 ret void 144} 145 146; GCN-ISEL-LABEL: name: suaddo64 147; GCN-ISEL-LABEL: body: 148; GCN-ISEL-LABEL: bb.0 149; GCN-ISEL: S_ADD_U64_PSEUDO 150 151; GCN-LABEL: @suaddo64 152; 153; GCN: s_add_u32 154; GCN: s_addc_u32 155define amdgpu_kernel void @suaddo64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 %a, i64 %b) #0 { 156 %uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) 157 %val = extractvalue { i64, i1 } %uadd, 0 158 %carry = extractvalue { i64, i1 } %uadd, 1 159 store i64 %val, i64 addrspace(1)* %out, align 8 160 store i1 %carry, i1 addrspace(1)* %carryout 161 ret void 162} 163 164; GCN-ISEL-LABEL: name: vuaddo64 165; GCN-ISEL-LABEL: body: 166; GCN-ISEL-LABEL: bb.0 167; GCN-ISEL: V_ADD_U64_PSEUDO 168 169; GCN-LABEL: @vuaddo64 170; 171; CISI: v_add_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0 172; CISI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc 173; 174; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0 175; VI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc 176; 177; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0 178; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc 179; 180; GFX10W32: v_add_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v0 181; GFX10W64: v_add_co_u32 v{{[0-9]+}}, [[CARRY:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, v0 182; GFX1010: v_add_co_ci_u32_e64 v{{[0-9]+}}, [[CARRY]], s{{[0-9]+}}, 0, [[CARRY]] 183; GFX1030: v_add_co_ci_u32_e64 v{{[0-9]+}}, null, s{{[0-9]+}}, 0, [[CARRY]] 184define amdgpu_kernel void @vuaddo64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 %a) #0 { 185 %tid = call i32 @llvm.amdgcn.workitem.id.x() 186 %tid.ext = sext i32 %tid to i64 187 %uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %tid.ext) 188 %val = extractvalue { i64, i1 } %uadd, 0 189 %carry = extractvalue { i64, i1 } %uadd, 1 190 store i64 %val, i64 addrspace(1)* %out, align 8 191 store i1 %carry, i1 addrspace(1)* %carryout 192 ret void 193} 194 195; GCN-ISEL-LABEL: name: ssub64rr 196; GCN-ISEL-LABEL: body: 197; GCN-ISEL-LABEL: bb.0.entry: 198; GCN-ISEL: S_SUB_U64_PSEUDO 199 200; GCN-LABEL: @ssub64rr 201; GCN: s_sub_u32 202; GCN: s_subb_u32 203define amdgpu_kernel void @ssub64rr(i64 addrspace(1)* %out, i64 %a, i64 %b) { 204entry: 205 %sub = sub i64 %a, %b 206 store i64 %sub, i64 addrspace(1)* %out 207 ret void 208} 209 210; GCN-ISEL-LABEL: name: ssub64ri 211; GCN-ISEL-LABEL: body: 212; GCN-ISEL-LABEL: bb.0.entry: 213; GCN-ISEL: S_SUB_U64_PSEUDO 214 215; GCN-LABEL: @ssub64ri 216; GCN: s_sub_u32 s{{[0-9]+}}, 0x56789876, s{{[0-9]+}} 217; GCN: s_subb_u32 s{{[0-9]+}}, 0x1234, s{{[0-9]+}} 218define amdgpu_kernel void @ssub64ri(i64 addrspace(1)* %out, i64 %a) { 219entry: 220 %sub = sub i64 20015998343286, %a 221 store i64 %sub, i64 addrspace(1)* %out 222 ret void 223} 224 225; GCN-ISEL-LABEL: name: vsub64rr 226; GCN-ISEL-LABEL: body: 227; GCN-ISEL-LABEL: bb.0.entry: 228; GCN-ISEL: V_SUB_U64_PSEUDO 229 230; GCN-LABEL: @vsub64rr 231; 232; CISI: v_sub_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} 233; CISI: v_subbrev_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc 234; 235; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} 236; VI: v_subbrev_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc 237; 238; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} 239; GFX9: v_subbrev_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc 240; 241; GFX10W32: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}} 242; GFX10W64: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, v{{[0-9]+}} 243; GFX1010: v_sub_co_ci_u32_e64 v{{[0-9]+}}, [[CARRY]], s{{[0-9]+}}, 0, [[CARRY]] 244; GFX1030: v_sub_co_ci_u32_e64 v{{[0-9]+}}, null, s{{[0-9]+}}, 0, [[CARRY]] 245define amdgpu_kernel void @vsub64rr(i64 addrspace(1)* %out, i64 %a) { 246entry: 247 %tid = call i32 @llvm.amdgcn.workitem.id.x() 248 %tid.ext = sext i32 %tid to i64 249 %sub = sub i64 %a, %tid.ext 250 store i64 %sub, i64 addrspace(1)* %out 251 ret void 252} 253 254; GCN-ISEL-LABEL: name: vsub64ri 255; GCN-ISEL-LABEL: body: 256; GCN-ISEL-LABEL: bb.0.entry: 257; GCN-ISEL: V_SUB_U64_PSEUDO 258 259; GCN-LABEL: @vsub64ri 260; 261; CISI: v_sub_i32_e32 v0, vcc, 0x56789876, v0 262; CISI: v_mov_b32_e32 v1, 0x1234 263; CISI: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc 264; 265; VI: v_sub_u32_e32 v0, vcc, 0x56789876, v0 266; VI: v_mov_b32_e32 v1, 0x1234 267; VI: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc 268; 269; GFX9: v_sub_co_u32_e32 v0, vcc, 0x56789876, v0 270; GFX9: v_mov_b32_e32 v1, 0x1234 271; GFX9: v_subbrev_co_u32_e32 v1, vcc, 0, v1, vcc 272; 273; GFX10W32: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], 0x56789876, v{{[0-9]+}} 274; GFX10W64: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:s\[[0-9]+:[0-9]+\]]], 0x56789876, v{{[0-9]+}} 275; GFX1010: v_sub_co_ci_u32_e64 v{{[0-9]+}}, [[CARRY]], 0x1234, 0, [[CARRY]] 276; GFX1030: v_sub_co_ci_u32_e64 v{{[0-9]+}}, null, 0x1234, 0, [[CARRY]] 277define amdgpu_kernel void @vsub64ri(i64 addrspace(1)* %out) { 278entry: 279 %tid = call i32 @llvm.amdgcn.workitem.id.x() 280 %tid.ext = sext i32 %tid to i64 281 %sub = sub i64 20015998343286, %tid.ext 282 store i64 %sub, i64 addrspace(1)* %out 283 ret void 284} 285 286; GCN-ISEL-LABEL: name: susubo32 287; GCN-ISEL-LABEL: body: 288; GCN-ISEL-LABEL: bb.0 289; GCN-ISEL: S_SUB_I32 290define amdgpu_kernel void @susubo32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) #0 { 291 %usub = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b) 292 %val = extractvalue { i32, i1 } %usub, 0 293 %carry = extractvalue { i32, i1 } %usub, 1 294 store i32 %val, i32 addrspace(1)* %out, align 4 295 ret void 296} 297 298 299; GCN-ISEL-LABEL: name: usubo32_vcc_user 300; GCN-ISEL-LABEL: body: 301; GCN-ISEL-LABEL: bb.0 302; GCN-ISEL: V_SUB_CO_U32_e64 303 304; below we check selection to v_sub/subb 305; because the only user of VCC produced by the USUBOis v_cndmask. 306; We select to VALU form to avoid unnecessary s_cselect to copy SCC to VCC 307 308; GCN-LABEL: @usubo32_vcc_user 309; 310; CISI: v_sub_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} 311; CISI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc 312; 313; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} 314; VI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc 315; 316; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} 317; GFX9: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc 318; 319; GFX10W32: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}} 320; GFX10W64: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, s{{[0-9]+}} 321; GFX10: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, [[CARRY]] 322define amdgpu_kernel void @usubo32_vcc_user(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) #0 { 323 %usub = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b) 324 %val = extractvalue { i32, i1 } %usub, 0 325 %carry = extractvalue { i32, i1 } %usub, 1 326 store i32 %val, i32 addrspace(1)* %out, align 4 327 store i1 %carry, i1 addrspace(1)* %carryout 328 ret void 329} 330 331; GCN-ISEL-LABEL: name: susubo64 332; GCN-ISEL-LABEL: body: 333; GCN-ISEL-LABEL: bb.0 334; GCN-ISEL: S_SUB_U64_PSEUDO 335 336; GCN-LABEL: @susubo64 337; 338; GCN: s_sub_u32 339; GCN: s_subb_u32 340define amdgpu_kernel void @susubo64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 %a, i64 %b) #0 { 341 %usub = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b) 342 %val = extractvalue { i64, i1 } %usub, 0 343 %carry = extractvalue { i64, i1 } %usub, 1 344 store i64 %val, i64 addrspace(1)* %out, align 8 345 store i1 %carry, i1 addrspace(1)* %carryout 346 ret void 347} 348 349; GCN-ISEL-LABEL: name: vusubo64 350; GCN-ISEL-LABEL: body: 351; GCN-ISEL-LABEL: bb.0 352; GCN-ISEL: V_SUB_U64_PSEUDO 353 354; GCN-LABEL: @vusubo64 355; 356; CISI: v_sub_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0 357; CISI: v_subbrev_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc 358; 359; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0 360; VI: v_subbrev_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc 361; 362; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0 363; GFX9: v_subbrev_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc 364; 365; GFX10W32: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v0 366; GFX10W64: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, v0 367; GFX1010: v_sub_co_ci_u32_e64 v{{[0-9]+}}, [[CARRY]], s{{[0-9]+}}, 0, [[CARRY]] 368; GFX1030: v_sub_co_ci_u32_e64 v{{[0-9]+}}, null, s{{[0-9]+}}, 0, [[CARRY]] 369define amdgpu_kernel void @vusubo64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 %a) #0 { 370 %tid = call i32 @llvm.amdgcn.workitem.id.x() 371 %tid.ext = sext i32 %tid to i64 372 %usub = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %tid.ext) 373 %val = extractvalue { i64, i1 } %usub, 0 374 %carry = extractvalue { i64, i1 } %usub, 1 375 store i64 %val, i64 addrspace(1)* %out, align 8 376 store i1 %carry, i1 addrspace(1)* %carryout 377 ret void 378} 379 380; GCN-ISEL-LABEL: name: sudiv64 381; GCN-ISEL-LABEL: body: 382; GCN-ISEL-LABEL: bb.3 383; GCN-ISEL: %[[CARRY:[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 384; GCN-ISEL: S_ADD_CO_PSEUDO %{{[0-9]+}}, killed %{{[0-9]+}}, killed %[[CARRY]] 385; GCN-ISEL: %[[CARRY:[0-9]+]]:sreg_64_xexec = V_SUB_CO_U32_e64 386; GCN-ISEL: S_SUB_CO_PSEUDO killed %{{[0-9]+}}, %{{[0-9]+}}, %[[CARRY]] 387define amdgpu_kernel void @sudiv64(i64 addrspace(1)* %out, i64 %x, i64 %y) { 388 %result = udiv i64 %x, %y 389 store i64 %result, i64 addrspace(1)* %out 390 ret void 391} 392 393 394 395declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64) #1 396 397declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) #1 398 399declare { i64, i1 } @llvm.usub.with.overflow.i64(i64, i64) #1 400 401declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #1 402 403declare i32 @llvm.amdgcn.workitem.id.x() #1 404 405attributes #0 = { nounwind } 406attributes #1 = { nounwind readnone } 407 408