1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
3
4; Make sure we don't crash or assert on spir_kernel calling convention.
5
6; GCN-LABEL: {{^}}kernel:
7; GCN: s_endpgm
8define spir_kernel void @kernel(i32 addrspace(1)* %out) {
9entry:
10  store i32 0, i32 addrspace(1)* %out
11  ret void
12}
13
14; FIXME: This is treated like a kernel
15; XGCN-LABEL: {{^}}func:
16; XGCN: s_endpgm
17; define spir_func void @func(i32 addrspace(1)* %out) {
18; entry:
19;   store i32 0, i32 addrspace(1)* %out
20;   ret void
21; }
22
23; GCN-LABEL: {{^}}ps_ret_cc_f16:
24; SI: v_cvt_f16_f32_e32 v0, v0
25; SI: v_cvt_f32_f16_e32 v0, v0
26; SI: v_add_f32_e32 v0, 1.0, v0
27
28; VI: v_add_f16_e32 v0, 1.0, v0
29; VI: ; return
30define amdgpu_ps half @ps_ret_cc_f16(half %arg0) {
31  %add = fadd half %arg0, 1.0
32  ret half %add
33}
34
35; GCN-LABEL: {{^}}ps_ret_cc_inreg_f16:
36; SI: v_cvt_f16_f32_e32 v0, s0
37; SI: v_cvt_f32_f16_e32 v0, v0
38; SI: v_add_f32_e32 v0, 1.0, v0
39
40; VI: v_add_f16_e64 v0, s0, 1.0
41; VI: ; return
42define amdgpu_ps half @ps_ret_cc_inreg_f16(half inreg %arg0) {
43  %add = fadd half %arg0, 1.0
44  ret half %add
45}
46
47; GCN-LABEL: {{^}}fastcc:
48; GCN: v_add_f32_e32 v0, 4.0, v0
49define fastcc float @fastcc(float %arg0) #0 {
50  %add = fadd float %arg0, 4.0
51  ret float %add
52}
53
54; GCN-LABEL: {{^}}coldcc:
55; GCN: v_add_f32_e32 v0, 4.0, v0
56define coldcc float @coldcc(float %arg0) #0 {
57 %add = fadd float %arg0, 4.0
58 ret float %add
59}
60
61; GCN-LABEL: {{^}}call_coldcc:
62; GCN: v_mov_b32_e32 v0, 1.0
63; GCN: s_swappc_b64
64define amdgpu_kernel void @call_coldcc() #0 {
65  %val = call float @coldcc(float 1.0)
66  store float %val, float addrspace(1)* undef
67  ret void
68}
69
70; GCN-LABEL: {{^}}call_fastcc:
71; GCN: v_mov_b32_e32 v0, 1.0
72; GCN: s_swappc_b64
73define amdgpu_kernel void @call_fastcc() #0 {
74  %val = call float @fastcc(float 1.0)
75  store float %val, float addrspace(1)* undef
76  ret void
77}
78
79attributes #0 = { nounwind noinline }