1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s 2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s 3 4; Make sure we don't crash or assert on spir_kernel calling convention. 5 6; GCN-LABEL: {{^}}kernel: 7; GCN: s_endpgm 8define spir_kernel void @kernel(i32 addrspace(1)* %out) { 9entry: 10 store i32 0, i32 addrspace(1)* %out 11 ret void 12} 13 14; FIXME: This is treated like a kernel 15; XGCN-LABEL: {{^}}func: 16; XGCN: s_endpgm 17; define spir_func void @func(i32 addrspace(1)* %out) { 18; entry: 19; store i32 0, i32 addrspace(1)* %out 20; ret void 21; } 22 23; GCN-LABEL: {{^}}ps_ret_cc_f16: 24; SI: v_cvt_f16_f32_e32 v0, v0 25; SI: v_cvt_f32_f16_e32 v0, v0 26; SI: v_add_f32_e32 v0, 1.0, v0 27 28; VI: v_add_f16_e32 v0, 1.0, v0 29; VI: ; return 30define amdgpu_ps half @ps_ret_cc_f16(half %arg0) { 31 %add = fadd half %arg0, 1.0 32 ret half %add 33} 34 35; GCN-LABEL: {{^}}ps_ret_cc_inreg_f16: 36; SI: v_cvt_f16_f32_e32 v0, s0 37; SI: v_cvt_f32_f16_e32 v0, v0 38; SI: v_add_f32_e32 v0, 1.0, v0 39 40; VI: v_add_f16_e64 v0, s0, 1.0 41; VI: ; return 42define amdgpu_ps half @ps_ret_cc_inreg_f16(half inreg %arg0) { 43 %add = fadd half %arg0, 1.0 44 ret half %add 45} 46 47; GCN-LABEL: {{^}}fastcc: 48; GCN: v_add_f32_e32 v0, 4.0, v0 49define fastcc float @fastcc(float %arg0) #0 { 50 %add = fadd float %arg0, 4.0 51 ret float %add 52} 53 54; GCN-LABEL: {{^}}coldcc: 55; GCN: v_add_f32_e32 v0, 4.0, v0 56define coldcc float @coldcc(float %arg0) #0 { 57 %add = fadd float %arg0, 4.0 58 ret float %add 59} 60 61; GCN-LABEL: {{^}}call_coldcc: 62; GCN: v_mov_b32_e32 v0, 1.0 63; GCN: s_swappc_b64 64define amdgpu_kernel void @call_coldcc() #0 { 65 %val = call float @coldcc(float 1.0) 66 store float %val, float addrspace(1)* undef 67 ret void 68} 69 70; GCN-LABEL: {{^}}call_fastcc: 71; GCN: v_mov_b32_e32 v0, 1.0 72; GCN: s_swappc_b64 73define amdgpu_kernel void @call_fastcc() #0 { 74 %val = call float @fastcc(float 1.0) 75 store float %val, float addrspace(1)* undef 76 ret void 77} 78 79; Mesa compute shader: check for 47176 (COMPUTE_PGM_RSRC1) in .AMDGPU.config 80; GCN-LABEL: .AMDGPU.config 81; GCN: .long 47176 82; GCN-LABEL: {{^}}cs_mesa: 83define amdgpu_cs half @cs_mesa(half %arg0) { 84 %add = fadd half %arg0, 1.0 85 ret half %add 86} 87 88; Mesa pixel shader: check for 45096 (SPI_SHADER_PGM_RSRC1_PS) in .AMDGPU.config 89; GCN-LABEL: .AMDGPU.config 90; GCN: .long 45096 91; GCN-LABEL: {{^}}ps_mesa_f16: 92define amdgpu_ps half @ps_mesa_f16(half %arg0) { 93 %add = fadd half %arg0, 1.0 94 ret half %add 95} 96 97; Mesa vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in .AMDGPU.config 98; GCN-LABEL: .AMDGPU.config 99; GCN: .long 45352 100; GCN-LABEL: {{^}}vs_mesa: 101define amdgpu_vs half @vs_mesa(half %arg0) { 102 %add = fadd half %arg0, 1.0 103 ret half %add 104} 105 106; Mesa geometry shader: check for 45608 (SPI_SHADER_PGM_RSRC1_GS) in .AMDGPU.config 107; GCN-LABEL: .AMDGPU.config 108; GCN: .long 45608 109; GCN-LABEL: {{^}}gs_mesa: 110define amdgpu_gs half @gs_mesa(half %arg0) { 111 %add = fadd half %arg0, 1.0 112 ret half %add 113} 114 115; Mesa hull shader: check for 46120 (SPI_SHADER_PGM_RSRC1_HS) in .AMDGPU.config 116; GCN-LABEL: .AMDGPU.config 117; GCN: .long 46120 118; GCN-LABEL: {{^}}hs_mesa: 119define amdgpu_hs half @hs_mesa(half %arg0) { 120 %add = fadd half %arg0, 1.0 121 ret half %add 122} 123 124; FIXME: Inconsistent ABI between targets 125; GCN-LABEL: {{^}}ps_mesa_v2f16: 126; VI: v_mov_b32_e32 v1, 0x3c00 127; VI-NEXT: v_add_f16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 128; VI-NEXT: v_add_f16_e32 v0, 1.0, v0 129; VI-NEXT: v_or_b32_e32 v0, v0, v1 130; VI-NEXT: ; return 131 132; SI-DAG: v_cvt_f16_f32_e32 [[CVT_ELT0:v[0-9]+]], v0 133; SI-DAG: v_cvt_f16_f32_e32 [[CVT_ELT1:v[0-9]+]], v1 134; SI-DAG: v_cvt_f32_f16_e32 [[RECVT_ELT0:v[0-9]+]], [[CVT_ELT0]] 135; SI-DAG: v_cvt_f32_f16_e32 [[RECVT_ELT1:v[0-9]+]], [[CVT_ELT1]] 136; SI-DAG: v_add_f32_e32 v0, 1.0, [[RECVT_ELT0]] 137; SI-DAG: v_add_f32_e32 v1, 1.0, [[RECVT_ELT1]] 138; SI: ; return to shader part epilog 139define amdgpu_ps <2 x half> @ps_mesa_v2f16(<2 x half> %arg0) { 140 %add = fadd <2 x half> %arg0, <half 1.0, half 1.0> 141 ret <2 x half> %add 142} 143 144; GCN-LABEL: {{^}}ps_mesa_inreg_v2f16: 145; VI: s_lshr_b32 s1, s0, 16 146; VI-NEXT: v_mov_b32_e32 v0, s1 147; VI-NEXT: v_mov_b32_e32 v1, 0x3c00 148; VI-NEXT: v_add_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD 149; VI-NEXT: v_add_f16_e64 v1, s0, 1.0 150; VI-NEXT: v_or_b32_e32 v0, v1, v0 151; VI-NEXT: ; return to shader part epilog 152 153; SI-DAG: v_cvt_f16_f32_e32 [[CVT_ELT0:v[0-9]+]], s0 154; SI-DAG: v_cvt_f16_f32_e32 [[CVT_ELT1:v[0-9]+]], s1 155; SI-DAG: v_cvt_f32_f16_e32 [[RECVT_ELT0:v[0-9]+]], [[CVT_ELT0]] 156; SI-DAG: v_cvt_f32_f16_e32 [[RECVT_ELT1:v[0-9]+]], [[CVT_ELT1]] 157; SI-DAG: v_add_f32_e32 v0, 1.0, [[RECVT_ELT0]] 158; SI-DAG: v_add_f32_e32 v1, 1.0, [[RECVT_ELT1]] 159; SI: ; return to shader part epilog 160define amdgpu_ps <2 x half> @ps_mesa_inreg_v2f16(<2 x half> inreg %arg0) { 161 %add = fadd <2 x half> %arg0, <half 1.0, half 1.0> 162 ret <2 x half> %add 163} 164 165; GCN-LABEL: {{^}}ps_mesa_v2i16: 166; VI: v_mov_b32_e32 v2, 1 167; VI: v_add_u16_e32 v1, 1, v0 168; VI: v_add_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 169; VI: v_or_b32_e32 v0, v1, v0 170 171 172; SI: v_lshlrev_b32_e32 v1, 16, v1 173; SI: v_add_i32_e32 v0, vcc, 1, v0 174; SI: v_and_b32 175; SI: v_or_b32 176; SI: v_add_i32_e32 v0, vcc, 0x10000, v0 177define amdgpu_ps void @ps_mesa_v2i16(<2 x i16> %arg0) { 178 %add = add <2 x i16> %arg0, <i16 1, i16 1> 179 store <2 x i16> %add, <2 x i16> addrspace(1)* undef 180 ret void 181} 182 183; GCN-LABEL: {{^}}ps_mesa_inreg_v2i16: 184; VI: s_and_b32 s1, s0, 0xffff0000 185; VI: s_add_i32 s0, s0, 1 186; VI: s_and_b32 s0, s0, 0xffff 187; VI: s_or_b32 s0, s1, s0 188; VI: s_add_i32 s0, s0, 0x10000 189; VI: v_mov_b32_e32 v0, s0 190 191; SI: s_lshl_b32 s1, s1, 16 192; SI: s_add_i32 s0, s0, 1 193; SI: s_and_b32 s0, s0, 0xffff 194; SI: s_or_b32 s0, s1, s0 195; SI: s_add_i32 s0, s0, 0x10000 196define amdgpu_ps void @ps_mesa_inreg_v2i16(<2 x i16> inreg %arg0) { 197 %add = add <2 x i16> %arg0, <i16 1, i16 1> 198 store <2 x i16> %add, <2 x i16> addrspace(1)* undef 199 ret void 200} 201 202; GCN-LABEL: {{^}}ps_mesa_inreg_v3i32: 203; GCN-DAG: s_add_i32 s0, s0, 1 204; GCN-DAG: s_add_i32 s{{[0-9]*}}, s1, 2 205; GCN-DAG: s_add_i32 s{{[0-9]*}}, s2, 3 206define amdgpu_ps void @ps_mesa_inreg_v3i32(<3 x i32> inreg %arg0) { 207 %add = add <3 x i32> %arg0, <i32 1, i32 2, i32 3> 208 store <3 x i32> %add, <3 x i32> addrspace(1)* undef 209 ret void 210} 211 212; GCN-LABEL: {{^}}ps_mesa_inreg_v3f32: 213; GCN-DAG: v_add_f32{{.*}}, s0, 1.0 214; GCN-DAG: v_add_f32{{.*}}, s1, 2.0 215; GCN-DAG: v_add_f32{{.*}}, s2, 4.0 216define amdgpu_ps void @ps_mesa_inreg_v3f32(<3 x float> inreg %arg0) { 217 %add = fadd <3 x float> %arg0, <float 1.0, float 2.0, float 4.0> 218 store <3 x float> %add, <3 x float> addrspace(1)* undef 219 ret void 220} 221 222; GCN-LABEL: {{^}}ps_mesa_inreg_v5i32: 223; GCN-DAG: s_add_i32 s0, s0, 1 224; GCN-DAG: s_add_i32 s{{[0-9]*}}, s1, 2 225; GCN-DAG: s_add_i32 s{{[0-9]*}}, s2, 3 226; GCN-DAG: s_add_i32 s{{[0-9]*}}, s3, 4 227; GCN-DAG: s_add_i32 s{{[0-9]*}}, s4, 5 228define amdgpu_ps void @ps_mesa_inreg_v5i32(<5 x i32> inreg %arg0) { 229 %add = add <5 x i32> %arg0, <i32 1, i32 2, i32 3, i32 4, i32 5> 230 store <5 x i32> %add, <5 x i32> addrspace(1)* undef 231 ret void 232} 233 234; GCN-LABEL: {{^}}ps_mesa_inreg_v5f32: 235; GCN-DAG: v_add_f32{{.*}}, s0, 1.0 236; GCN-DAG: v_add_f32{{.*}}, s1, 2.0 237; GCN-DAG: v_add_f32{{.*}}, s2, 4.0 238; GCN-DAG: v_add_f32{{.*}}, s3, -1.0 239; GCN-DAG: v_add_f32{{.*}}, s4, 0.5 240define amdgpu_ps void @ps_mesa_inreg_v5f32(<5 x float> inreg %arg0) { 241 %add = fadd <5 x float> %arg0, <float 1.0, float 2.0, float 4.0, float -1.0, float 0.5> 242 store <5 x float> %add, <5 x float> addrspace(1)* undef 243 ret void 244} 245 246; GCN-LABEL: {{^}}ps_mesa_v3i32: 247; GCN-DAG: v_add_{{.*}}, 1, v0 248; GCN-DAG: v_add_{{.*}}, 2, v1 249; GCN-DAG: v_add_{{.*}}, 3, v2 250define amdgpu_ps void @ps_mesa_v3i32(<3 x i32> %arg0) { 251 %add = add <3 x i32> %arg0, <i32 1, i32 2, i32 3> 252 store <3 x i32> %add, <3 x i32> addrspace(1)* undef 253 ret void 254} 255 256; GCN-LABEL: {{^}}ps_mesa_v3f32: 257; GCN-DAG: v_add_{{.*}}, 1.0, v0 258; GCN-DAG: v_add_{{.*}}, 2.0, v1 259; GCN-DAG: v_add_{{.*}}, 4.0, v2 260define amdgpu_ps void @ps_mesa_v3f32(<3 x float> %arg0) { 261 %add = fadd <3 x float> %arg0, <float 1.0, float 2.0, float 4.0> 262 store <3 x float> %add, <3 x float> addrspace(1)* undef 263 ret void 264} 265 266; GCN-LABEL: {{^}}ps_mesa_v5i32: 267; GCN-DAG: v_add_{{.*}}, 1, v0 268; GCN-DAG: v_add_{{.*}}, 2, v1 269; GCN-DAG: v_add_{{.*}}, 3, v2 270; GCN-DAG: v_add_{{.*}}, 4, v3 271; GCN-DAG: v_add_{{.*}}, 5, v4 272define amdgpu_ps void @ps_mesa_v5i32(<5 x i32> %arg0) { 273 %add = add <5 x i32> %arg0, <i32 1, i32 2, i32 3, i32 4, i32 5> 274 store <5 x i32> %add, <5 x i32> addrspace(1)* undef 275 ret void 276} 277 278; GCN-LABEL: {{^}}ps_mesa_v5f32: 279; GCN-DAG: v_add_f32{{.*}}, 1.0, v0 280; GCN-DAG: v_add_f32{{.*}}, 2.0, v1 281; GCN-DAG: v_add_f32{{.*}}, 4.0, v2 282; GCN-DAG: v_add_f32{{.*}}, -1.0, v3 283; GCN-DAG: v_add_f32{{.*}}, 0.5, v4 284define amdgpu_ps void @ps_mesa_v5f32(<5 x float> %arg0) { 285 %add = fadd <5 x float> %arg0, <float 1.0, float 2.0, float 4.0, float -1.0, float 0.5> 286 store <5 x float> %add, <5 x float> addrspace(1)* undef 287 ret void 288} 289 290 291 292attributes #0 = { nounwind noinline } 293