1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
3
4; 64-bit divides and rems should be split into a fast and slow path
5; where the fast path uses a 32-bit operation.
6
7define i64 @sdiv64(i64 %a, i64 %b) {
8; GFX9-LABEL: sdiv64:
9; GFX9:       ; %bb.0:
10; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
11; GFX9-NEXT:    v_or_b32_e32 v5, v1, v3
12; GFX9-NEXT:    v_mov_b32_e32 v4, 0
13; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[4:5]
14; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5
15; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
16; GFX9-NEXT:    s_xor_b64 s[6:7], exec, s[4:5]
17; GFX9-NEXT:    s_cbranch_execz BB0_2
18; GFX9-NEXT:  ; %bb.1:
19; GFX9-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
20; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
21; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
22; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
23; GFX9-NEXT:    v_xor_b32_e32 v3, v3, v4
24; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v2
25; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, v3
26; GFX9-NEXT:    v_sub_co_u32_e32 v7, vcc, 0, v2
27; GFX9-NEXT:    v_subb_co_u32_e32 v8, vcc, 0, v3, vcc
28; GFX9-NEXT:    v_mov_b32_e32 v15, 0
29; GFX9-NEXT:    v_mac_f32_e32 v5, 0x4f800000, v6
30; GFX9-NEXT:    v_rcp_f32_e32 v5, v5
31; GFX9-NEXT:    v_mov_b32_e32 v14, 0
32; GFX9-NEXT:    v_mul_f32_e32 v5, 0x5f7ffffc, v5
33; GFX9-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v5
34; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
35; GFX9-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v6
36; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
37; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v6
38; GFX9-NEXT:    v_mul_lo_u32 v9, v8, v5
39; GFX9-NEXT:    v_mul_hi_u32 v10, v7, v5
40; GFX9-NEXT:    v_mul_lo_u32 v11, v7, v6
41; GFX9-NEXT:    v_mul_lo_u32 v12, v7, v5
42; GFX9-NEXT:    v_add3_u32 v9, v10, v11, v9
43; GFX9-NEXT:    v_mul_lo_u32 v11, v5, v9
44; GFX9-NEXT:    v_mul_hi_u32 v13, v5, v12
45; GFX9-NEXT:    v_mul_hi_u32 v10, v5, v9
46; GFX9-NEXT:    v_mul_hi_u32 v16, v6, v9
47; GFX9-NEXT:    v_mul_lo_u32 v9, v6, v9
48; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v13, v11
49; GFX9-NEXT:    v_mul_lo_u32 v13, v6, v12
50; GFX9-NEXT:    v_mul_hi_u32 v12, v6, v12
51; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v10, vcc
52; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v11, v13
53; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v10, v12, vcc
54; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v14, vcc
55; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
56; GFX9-NEXT:    v_add_co_u32_e64 v5, s[4:5], v5, v9
57; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v11, vcc
58; GFX9-NEXT:    v_addc_co_u32_e64 v9, vcc, v6, v10, s[4:5]
59; GFX9-NEXT:    v_mul_lo_u32 v11, v7, v9
60; GFX9-NEXT:    v_mul_hi_u32 v12, v7, v5
61; GFX9-NEXT:    v_mul_lo_u32 v8, v8, v5
62; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v5
63; GFX9-NEXT:    v_add_u32_e32 v6, v6, v10
64; GFX9-NEXT:    v_add3_u32 v8, v12, v11, v8
65; GFX9-NEXT:    v_mul_lo_u32 v13, v5, v8
66; GFX9-NEXT:    v_mul_hi_u32 v16, v5, v7
67; GFX9-NEXT:    v_mul_hi_u32 v17, v5, v8
68; GFX9-NEXT:    v_mul_hi_u32 v12, v9, v7
69; GFX9-NEXT:    v_mul_lo_u32 v7, v9, v7
70; GFX9-NEXT:    v_add_co_u32_e32 v13, vcc, v16, v13
71; GFX9-NEXT:    v_mul_hi_u32 v11, v9, v8
72; GFX9-NEXT:    v_addc_co_u32_e32 v16, vcc, v15, v17, vcc
73; GFX9-NEXT:    v_mul_lo_u32 v8, v9, v8
74; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v13, v7
75; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v16, v12, vcc
76; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v11, v14, vcc
77; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v8
78; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v15, v9, vcc
79; GFX9-NEXT:    v_addc_co_u32_e64 v6, vcc, v6, v8, s[4:5]
80; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v7
81; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
82; GFX9-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
83; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v7
84; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v7
85; GFX9-NEXT:    v_mul_lo_u32 v8, v0, v6
86; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v5
87; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v6
88; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v7, vcc
89; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v7
90; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
91; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v15, v10, vcc
92; GFX9-NEXT:    v_mul_lo_u32 v10, v1, v5
93; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v5
94; GFX9-NEXT:    v_mul_hi_u32 v11, v1, v6
95; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
96; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v8, v10
97; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v5, vcc
98; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v14, vcc
99; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v6
100; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v8, vcc
101; GFX9-NEXT:    v_mul_lo_u32 v8, v3, v5
102; GFX9-NEXT:    v_mul_lo_u32 v9, v2, v6
103; GFX9-NEXT:    v_mul_hi_u32 v10, v2, v5
104; GFX9-NEXT:    v_mul_lo_u32 v11, v2, v5
105; GFX9-NEXT:    v_add3_u32 v8, v10, v9, v8
106; GFX9-NEXT:    v_sub_u32_e32 v9, v1, v8
107; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, v0, v11
108; GFX9-NEXT:    v_subb_co_u32_e64 v9, s[4:5], v9, v3, vcc
109; GFX9-NEXT:    v_sub_co_u32_e64 v10, s[4:5], v0, v2
110; GFX9-NEXT:    v_subbrev_co_u32_e64 v9, s[4:5], 0, v9, s[4:5]
111; GFX9-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v3
112; GFX9-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
113; GFX9-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v2
114; GFX9-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
115; GFX9-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v3
116; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v8, vcc
117; GFX9-NEXT:    v_cndmask_b32_e64 v9, v11, v10, s[4:5]
118; GFX9-NEXT:    v_add_co_u32_e64 v10, s[4:5], 2, v5
119; GFX9-NEXT:    v_addc_co_u32_e64 v11, s[4:5], 0, v6, s[4:5]
120; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
121; GFX9-NEXT:    v_add_co_u32_e64 v12, s[4:5], 1, v5
122; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
123; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
124; GFX9-NEXT:    v_addc_co_u32_e64 v13, s[4:5], 0, v6, s[4:5]
125; GFX9-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
126; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
127; GFX9-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v9
128; GFX9-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
129; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
130; GFX9-NEXT:    v_cndmask_b32_e64 v1, v12, v10, s[4:5]
131; GFX9-NEXT:    v_cndmask_b32_e64 v9, v13, v11, s[4:5]
132; GFX9-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
133; GFX9-NEXT:    v_xor_b32_e32 v2, v7, v4
134; GFX9-NEXT:    v_cndmask_b32_e32 v0, v6, v9, vcc
135; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v2
136; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v2
137; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, v1, v2
138; GFX9-NEXT:    v_subb_co_u32_e32 v5, vcc, v0, v2, vcc
139; GFX9-NEXT:    ; implicit-def: $vgpr2_vgpr3
140; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1
141; GFX9-NEXT:  BB0_2: ; %Flow
142; GFX9-NEXT:    s_or_saveexec_b64 s[4:5], s[6:7]
143; GFX9-NEXT:    s_xor_b64 exec, exec, s[4:5]
144; GFX9-NEXT:    s_cbranch_execz BB0_4
145; GFX9-NEXT:  ; %bb.3:
146; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
147; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v2
148; GFX9-NEXT:    v_mov_b32_e32 v5, 0
149; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
150; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
151; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
152; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v1
153; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
154; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
155; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
156; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v2
157; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
158; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v3
159; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
160; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v2
161; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
162; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
163; GFX9-NEXT:    v_add_u32_e32 v3, 1, v1
164; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
165; GFX9-NEXT:    v_cndmask_b32_e32 v4, v1, v3, vcc
166; GFX9-NEXT:  BB0_4:
167; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
168; GFX9-NEXT:    v_mov_b32_e32 v0, v4
169; GFX9-NEXT:    v_mov_b32_e32 v1, v5
170; GFX9-NEXT:    s_setpc_b64 s[30:31]
171  %d = sdiv i64 %a, %b
172  ret i64 %d
173}
174
175define i64 @udiv64(i64 %a, i64 %b) {
176; GFX9-LABEL: udiv64:
177; GFX9:       ; %bb.0:
178; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
179; GFX9-NEXT:    v_or_b32_e32 v5, v1, v3
180; GFX9-NEXT:    v_mov_b32_e32 v4, 0
181; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[4:5]
182; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5
183; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
184; GFX9-NEXT:    s_xor_b64 s[6:7], exec, s[4:5]
185; GFX9-NEXT:    s_cbranch_execz BB1_2
186; GFX9-NEXT:  ; %bb.1:
187; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, v2
188; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v3
189; GFX9-NEXT:    v_sub_co_u32_e32 v6, vcc, 0, v2
190; GFX9-NEXT:    v_subb_co_u32_e32 v7, vcc, 0, v3, vcc
191; GFX9-NEXT:    v_mov_b32_e32 v13, 0
192; GFX9-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
193; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
194; GFX9-NEXT:    v_mov_b32_e32 v12, 0
195; GFX9-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
196; GFX9-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
197; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
198; GFX9-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
199; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
200; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
201; GFX9-NEXT:    v_mul_lo_u32 v9, v7, v4
202; GFX9-NEXT:    v_mul_lo_u32 v8, v6, v5
203; GFX9-NEXT:    v_mul_hi_u32 v10, v6, v4
204; GFX9-NEXT:    v_mul_lo_u32 v11, v6, v4
205; GFX9-NEXT:    v_add3_u32 v8, v10, v8, v9
206; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v11
207; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v8
208; GFX9-NEXT:    v_mul_hi_u32 v14, v4, v8
209; GFX9-NEXT:    v_mul_hi_u32 v15, v5, v8
210; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
211; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v10
212; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v14, vcc
213; GFX9-NEXT:    v_mul_lo_u32 v14, v5, v11
214; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v11
215; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v14
216; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
217; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v12, vcc
218; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
219; GFX9-NEXT:    v_add_co_u32_e64 v4, s[4:5], v4, v8
220; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v13, v10, vcc
221; GFX9-NEXT:    v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5]
222; GFX9-NEXT:    v_mul_lo_u32 v10, v6, v8
223; GFX9-NEXT:    v_mul_hi_u32 v11, v6, v4
224; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v4
225; GFX9-NEXT:    v_mul_lo_u32 v6, v6, v4
226; GFX9-NEXT:    v_add_u32_e32 v5, v5, v9
227; GFX9-NEXT:    v_add3_u32 v7, v11, v10, v7
228; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v7
229; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v6
230; GFX9-NEXT:    v_mul_hi_u32 v15, v4, v7
231; GFX9-NEXT:    v_mul_hi_u32 v14, v8, v7
232; GFX9-NEXT:    v_mul_lo_u32 v7, v8, v7
233; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
234; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v6
235; GFX9-NEXT:    v_mul_lo_u32 v6, v8, v6
236; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
237; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v10, v6
238; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v11, vcc
239; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v14, v12, vcc
240; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v7
241; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
242; GFX9-NEXT:    v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5]
243; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
244; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
245; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v5
246; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v4
247; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v5
248; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v5
249; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
250; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
251; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
252; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
253; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
254; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v8
255; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
256; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v9, v12, vcc
257; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v5
258; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v13, v6, vcc
259; GFX9-NEXT:    v_mul_lo_u32 v6, v3, v4
260; GFX9-NEXT:    v_mul_lo_u32 v7, v2, v5
261; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v4
262; GFX9-NEXT:    v_mul_lo_u32 v9, v2, v4
263; GFX9-NEXT:    v_add3_u32 v6, v8, v7, v6
264; GFX9-NEXT:    v_sub_u32_e32 v7, v1, v6
265; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, v0, v9
266; GFX9-NEXT:    v_subb_co_u32_e64 v7, s[4:5], v7, v3, vcc
267; GFX9-NEXT:    v_sub_co_u32_e64 v8, s[4:5], v0, v2
268; GFX9-NEXT:    v_subbrev_co_u32_e64 v7, s[4:5], 0, v7, s[4:5]
269; GFX9-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v3
270; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
271; GFX9-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v2
272; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
273; GFX9-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v3
274; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v6, vcc
275; GFX9-NEXT:    v_cndmask_b32_e64 v7, v9, v8, s[4:5]
276; GFX9-NEXT:    v_add_co_u32_e64 v8, s[4:5], 2, v4
277; GFX9-NEXT:    v_addc_co_u32_e64 v9, s[4:5], 0, v5, s[4:5]
278; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
279; GFX9-NEXT:    v_add_co_u32_e64 v10, s[4:5], 1, v4
280; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
281; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
282; GFX9-NEXT:    v_addc_co_u32_e64 v11, s[4:5], 0, v5, s[4:5]
283; GFX9-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
284; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
285; GFX9-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
286; GFX9-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
287; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
288; GFX9-NEXT:    v_cndmask_b32_e64 v7, v11, v9, s[4:5]
289; GFX9-NEXT:    v_cndmask_b32_e64 v0, v10, v8, s[4:5]
290; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v0, vcc
291; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
292; GFX9-NEXT:    ; implicit-def: $vgpr2_vgpr3
293; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1
294; GFX9-NEXT:  BB1_2: ; %Flow
295; GFX9-NEXT:    s_or_saveexec_b64 s[4:5], s[6:7]
296; GFX9-NEXT:    s_xor_b64 exec, exec, s[4:5]
297; GFX9-NEXT:    s_cbranch_execz BB1_4
298; GFX9-NEXT:  ; %bb.3:
299; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
300; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v2
301; GFX9-NEXT:    v_mov_b32_e32 v5, 0
302; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
303; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
304; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
305; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v1
306; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
307; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
308; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
309; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v2
310; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
311; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v3
312; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
313; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v2
314; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
315; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
316; GFX9-NEXT:    v_add_u32_e32 v3, 1, v1
317; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
318; GFX9-NEXT:    v_cndmask_b32_e32 v4, v1, v3, vcc
319; GFX9-NEXT:  BB1_4:
320; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
321; GFX9-NEXT:    v_mov_b32_e32 v0, v4
322; GFX9-NEXT:    v_mov_b32_e32 v1, v5
323; GFX9-NEXT:    s_setpc_b64 s[30:31]
324  %d = udiv i64 %a, %b
325  ret i64 %d
326}
327
328define i64 @srem64(i64 %a, i64 %b) {
329; GFX9-LABEL: srem64:
330; GFX9:       ; %bb.0:
331; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
332; GFX9-NEXT:    v_or_b32_e32 v5, v1, v3
333; GFX9-NEXT:    v_mov_b32_e32 v4, 0
334; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[4:5]
335; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5
336; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
337; GFX9-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
338; GFX9-NEXT:    s_cbranch_execz BB2_2
339; GFX9-NEXT:  ; %bb.1:
340; GFX9-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
341; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
342; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
343; GFX9-NEXT:    v_xor_b32_e32 v3, v3, v4
344; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
345; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, v2
346; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v3
347; GFX9-NEXT:    v_sub_co_u32_e32 v6, vcc, 0, v2
348; GFX9-NEXT:    v_subb_co_u32_e32 v7, vcc, 0, v3, vcc
349; GFX9-NEXT:    v_mov_b32_e32 v14, 0
350; GFX9-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
351; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
352; GFX9-NEXT:    v_mov_b32_e32 v13, 0
353; GFX9-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
354; GFX9-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
355; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
356; GFX9-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
357; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
358; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
359; GFX9-NEXT:    v_mul_lo_u32 v8, v7, v4
360; GFX9-NEXT:    v_mul_hi_u32 v9, v6, v4
361; GFX9-NEXT:    v_mul_lo_u32 v10, v6, v5
362; GFX9-NEXT:    v_mul_lo_u32 v11, v6, v4
363; GFX9-NEXT:    v_add3_u32 v8, v9, v10, v8
364; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v8
365; GFX9-NEXT:    v_mul_hi_u32 v12, v4, v11
366; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v8
367; GFX9-NEXT:    v_mul_hi_u32 v15, v5, v8
368; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
369; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v12, v10
370; GFX9-NEXT:    v_mul_lo_u32 v12, v5, v11
371; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v11
372; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v14, v9, vcc
373; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v10, v12
374; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v9, v11, vcc
375; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v13, vcc
376; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
377; GFX9-NEXT:    v_add_co_u32_e64 v4, s[4:5], v4, v8
378; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v14, v10, vcc
379; GFX9-NEXT:    v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5]
380; GFX9-NEXT:    v_mul_lo_u32 v10, v6, v8
381; GFX9-NEXT:    v_mul_hi_u32 v11, v6, v4
382; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v4
383; GFX9-NEXT:    v_mul_lo_u32 v6, v6, v4
384; GFX9-NEXT:    v_add_u32_e32 v5, v5, v9
385; GFX9-NEXT:    v_add3_u32 v7, v11, v10, v7
386; GFX9-NEXT:    v_mul_lo_u32 v12, v4, v7
387; GFX9-NEXT:    v_mul_hi_u32 v15, v4, v6
388; GFX9-NEXT:    v_mul_hi_u32 v16, v4, v7
389; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v6
390; GFX9-NEXT:    v_mul_lo_u32 v6, v8, v6
391; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v15, v12
392; GFX9-NEXT:    v_mul_hi_u32 v10, v8, v7
393; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v14, v16, vcc
394; GFX9-NEXT:    v_mul_lo_u32 v7, v8, v7
395; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v12, v6
396; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v11, vcc
397; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v10, v13, vcc
398; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v7
399; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v14, v8, vcc
400; GFX9-NEXT:    v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5]
401; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
402; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
403; GFX9-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
404; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v6
405; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v6
406; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v5
407; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v4
408; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v5
409; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v6, vcc
410; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v6
411; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
412; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v14, v9, vcc
413; GFX9-NEXT:    v_mul_lo_u32 v9, v1, v4
414; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
415; GFX9-NEXT:    v_mul_hi_u32 v10, v1, v5
416; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
417; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v9
418; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
419; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v10, v13, vcc
420; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v5
421; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v14, v7, vcc
422; GFX9-NEXT:    v_mul_lo_u32 v7, v3, v4
423; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v4
424; GFX9-NEXT:    v_mul_lo_u32 v5, v2, v5
425; GFX9-NEXT:    v_mul_lo_u32 v4, v2, v4
426; GFX9-NEXT:    v_add3_u32 v5, v8, v5, v7
427; GFX9-NEXT:    v_sub_u32_e32 v7, v1, v5
428; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, v0, v4
429; GFX9-NEXT:    v_subb_co_u32_e64 v4, s[4:5], v7, v3, vcc
430; GFX9-NEXT:    v_sub_co_u32_e64 v7, s[4:5], v0, v2
431; GFX9-NEXT:    v_subbrev_co_u32_e64 v8, s[6:7], 0, v4, s[4:5]
432; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v8, v3
433; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v5, vcc
434; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[6:7]
435; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v7, v2
436; GFX9-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[6:7]
437; GFX9-NEXT:    v_cmp_eq_u32_e64 s[6:7], v8, v3
438; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
439; GFX9-NEXT:    v_subb_co_u32_e64 v4, s[4:5], v4, v3, s[4:5]
440; GFX9-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[6:7]
441; GFX9-NEXT:    v_sub_co_u32_e64 v10, s[4:5], v7, v2
442; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
443; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
444; GFX9-NEXT:    v_subbrev_co_u32_e64 v4, s[4:5], 0, v4, s[4:5]
445; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
446; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
447; GFX9-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
448; GFX9-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v9
449; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
450; GFX9-NEXT:    v_cndmask_b32_e64 v2, v7, v10, s[4:5]
451; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
452; GFX9-NEXT:    v_cndmask_b32_e64 v4, v8, v4, s[4:5]
453; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
454; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v6
455; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v6
456; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, v0, v6
457; GFX9-NEXT:    v_subb_co_u32_e32 v5, vcc, v1, v6, vcc
458; GFX9-NEXT:    ; implicit-def: $vgpr2_vgpr3
459; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1
460; GFX9-NEXT:  BB2_2: ; %Flow
461; GFX9-NEXT:    s_or_saveexec_b64 s[4:5], s[8:9]
462; GFX9-NEXT:    s_xor_b64 exec, exec, s[4:5]
463; GFX9-NEXT:    s_cbranch_execz BB2_4
464; GFX9-NEXT:  ; %bb.3:
465; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
466; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v2
467; GFX9-NEXT:    v_mov_b32_e32 v5, 0
468; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
469; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
470; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
471; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v1
472; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
473; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
474; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
475; GFX9-NEXT:    v_mul_lo_u32 v1, v1, v2
476; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v1
477; GFX9-NEXT:    v_sub_u32_e32 v1, v0, v2
478; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
479; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
480; GFX9-NEXT:    v_sub_u32_e32 v1, v0, v2
481; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
482; GFX9-NEXT:    v_cndmask_b32_e32 v4, v0, v1, vcc
483; GFX9-NEXT:  BB2_4:
484; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
485; GFX9-NEXT:    v_mov_b32_e32 v0, v4
486; GFX9-NEXT:    v_mov_b32_e32 v1, v5
487; GFX9-NEXT:    s_setpc_b64 s[30:31]
488  %d = srem i64 %a, %b
489  ret i64 %d
490}
491
492define i64 @urem64(i64 %a, i64 %b) {
493; GFX9-LABEL: urem64:
494; GFX9:       ; %bb.0:
495; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
496; GFX9-NEXT:    v_or_b32_e32 v5, v1, v3
497; GFX9-NEXT:    v_mov_b32_e32 v4, 0
498; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[4:5]
499; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5
500; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
501; GFX9-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
502; GFX9-NEXT:    s_cbranch_execz BB3_2
503; GFX9-NEXT:  ; %bb.1:
504; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, v2
505; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v3
506; GFX9-NEXT:    v_sub_co_u32_e32 v6, vcc, 0, v2
507; GFX9-NEXT:    v_subb_co_u32_e32 v7, vcc, 0, v3, vcc
508; GFX9-NEXT:    v_mov_b32_e32 v13, 0
509; GFX9-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
510; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
511; GFX9-NEXT:    v_mov_b32_e32 v12, 0
512; GFX9-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
513; GFX9-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
514; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
515; GFX9-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
516; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
517; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
518; GFX9-NEXT:    v_mul_lo_u32 v9, v7, v4
519; GFX9-NEXT:    v_mul_lo_u32 v8, v6, v5
520; GFX9-NEXT:    v_mul_hi_u32 v10, v6, v4
521; GFX9-NEXT:    v_mul_lo_u32 v11, v6, v4
522; GFX9-NEXT:    v_add3_u32 v8, v10, v8, v9
523; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v11
524; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v8
525; GFX9-NEXT:    v_mul_hi_u32 v14, v4, v8
526; GFX9-NEXT:    v_mul_hi_u32 v15, v5, v8
527; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
528; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v10
529; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v14, vcc
530; GFX9-NEXT:    v_mul_lo_u32 v14, v5, v11
531; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v11
532; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v14
533; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
534; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v12, vcc
535; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
536; GFX9-NEXT:    v_add_co_u32_e64 v4, s[4:5], v4, v8
537; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v13, v10, vcc
538; GFX9-NEXT:    v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5]
539; GFX9-NEXT:    v_mul_lo_u32 v10, v6, v8
540; GFX9-NEXT:    v_mul_hi_u32 v11, v6, v4
541; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v4
542; GFX9-NEXT:    v_mul_lo_u32 v6, v6, v4
543; GFX9-NEXT:    v_add_u32_e32 v5, v5, v9
544; GFX9-NEXT:    v_add3_u32 v7, v11, v10, v7
545; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v7
546; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v6
547; GFX9-NEXT:    v_mul_hi_u32 v15, v4, v7
548; GFX9-NEXT:    v_mul_hi_u32 v14, v8, v7
549; GFX9-NEXT:    v_mul_lo_u32 v7, v8, v7
550; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
551; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v6
552; GFX9-NEXT:    v_mul_lo_u32 v6, v8, v6
553; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
554; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v10, v6
555; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v11, vcc
556; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v14, v12, vcc
557; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v7
558; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
559; GFX9-NEXT:    v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5]
560; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
561; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
562; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v5
563; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v4
564; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v5
565; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v5
566; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
567; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
568; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
569; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
570; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
571; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v8
572; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
573; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v9, v12, vcc
574; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v5
575; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v13, v6, vcc
576; GFX9-NEXT:    v_mul_lo_u32 v6, v3, v4
577; GFX9-NEXT:    v_mul_hi_u32 v7, v2, v4
578; GFX9-NEXT:    v_mul_lo_u32 v5, v2, v5
579; GFX9-NEXT:    v_mul_lo_u32 v4, v2, v4
580; GFX9-NEXT:    v_add3_u32 v5, v7, v5, v6
581; GFX9-NEXT:    v_sub_u32_e32 v6, v1, v5
582; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, v0, v4
583; GFX9-NEXT:    v_subb_co_u32_e64 v4, s[4:5], v6, v3, vcc
584; GFX9-NEXT:    v_sub_co_u32_e64 v6, s[4:5], v0, v2
585; GFX9-NEXT:    v_subbrev_co_u32_e64 v7, s[6:7], 0, v4, s[4:5]
586; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v7, v3
587; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v5, vcc
588; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
589; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v2
590; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[6:7]
591; GFX9-NEXT:    v_cmp_eq_u32_e64 s[6:7], v7, v3
592; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
593; GFX9-NEXT:    v_subb_co_u32_e64 v4, s[4:5], v4, v3, s[4:5]
594; GFX9-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[6:7]
595; GFX9-NEXT:    v_sub_co_u32_e64 v9, s[4:5], v6, v2
596; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
597; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
598; GFX9-NEXT:    v_subbrev_co_u32_e64 v4, s[4:5], 0, v4, s[4:5]
599; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
600; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
601; GFX9-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
602; GFX9-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v8
603; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
604; GFX9-NEXT:    v_cndmask_b32_e64 v4, v7, v4, s[4:5]
605; GFX9-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc
606; GFX9-NEXT:    v_cndmask_b32_e64 v1, v6, v9, s[4:5]
607; GFX9-NEXT:    v_cndmask_b32_e32 v4, v0, v1, vcc
608; GFX9-NEXT:    ; implicit-def: $vgpr2_vgpr3
609; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1
610; GFX9-NEXT:  BB3_2: ; %Flow
611; GFX9-NEXT:    s_or_saveexec_b64 s[4:5], s[8:9]
612; GFX9-NEXT:    s_xor_b64 exec, exec, s[4:5]
613; GFX9-NEXT:    s_cbranch_execz BB3_4
614; GFX9-NEXT:  ; %bb.3:
615; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
616; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v2
617; GFX9-NEXT:    v_mov_b32_e32 v5, 0
618; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
619; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
620; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
621; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v1
622; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
623; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
624; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
625; GFX9-NEXT:    v_mul_lo_u32 v1, v1, v2
626; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v1
627; GFX9-NEXT:    v_sub_u32_e32 v1, v0, v2
628; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
629; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
630; GFX9-NEXT:    v_sub_u32_e32 v1, v0, v2
631; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
632; GFX9-NEXT:    v_cndmask_b32_e32 v4, v0, v1, vcc
633; GFX9-NEXT:  BB3_4:
634; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
635; GFX9-NEXT:    v_mov_b32_e32 v0, v4
636; GFX9-NEXT:    v_mov_b32_e32 v1, v5
637; GFX9-NEXT:    s_setpc_b64 s[30:31]
638  %d = urem i64 %a, %b
639  ret i64 %d
640}
641
642define i32 @sdiv32(i32 %a, i32 %b) {
643; GFX9-LABEL: sdiv32:
644; GFX9:       ; %bb.0:
645; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
646; GFX9-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
647; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
648; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v2
649; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, v1
650; GFX9-NEXT:    v_sub_u32_e32 v4, 0, v1
651; GFX9-NEXT:    v_ashrrev_i32_e32 v5, 31, v0
652; GFX9-NEXT:    v_add_u32_e32 v0, v0, v5
653; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v3
654; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v5
655; GFX9-NEXT:    v_xor_b32_e32 v2, v5, v2
656; GFX9-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
657; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
658; GFX9-NEXT:    v_mul_lo_u32 v4, v4, v3
659; GFX9-NEXT:    v_mul_hi_u32 v4, v3, v4
660; GFX9-NEXT:    v_add_u32_e32 v3, v3, v4
661; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v3
662; GFX9-NEXT:    v_mul_lo_u32 v4, v3, v1
663; GFX9-NEXT:    v_add_u32_e32 v5, 1, v3
664; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v4
665; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
666; GFX9-NEXT:    v_sub_u32_e32 v4, v0, v1
667; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
668; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
669; GFX9-NEXT:    v_add_u32_e32 v4, 1, v3
670; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
671; GFX9-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc
672; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v2
673; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v2
674; GFX9-NEXT:    s_setpc_b64 s[30:31]
675  %d = sdiv i32 %a, %b
676  ret i32 %d
677}
678
679define i32 @udiv32(i32 %a, i32 %b) {
680; GFX9-LABEL: udiv32:
681; GFX9:       ; %bb.0:
682; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
683; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, v1
684; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v1
685; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v2
686; GFX9-NEXT:    v_mul_f32_e32 v2, 0x4f7ffffe, v2
687; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
688; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v2
689; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v3
690; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
691; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
692; GFX9-NEXT:    v_mul_lo_u32 v3, v2, v1
693; GFX9-NEXT:    v_add_u32_e32 v4, 1, v2
694; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v3
695; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
696; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v1
697; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
698; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
699; GFX9-NEXT:    v_add_u32_e32 v3, 1, v2
700; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
701; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc
702; GFX9-NEXT:    s_setpc_b64 s[30:31]
703  %d = udiv i32 %a, %b
704  ret i32 %d
705}
706
707define i32 @srem32(i32 %a, i32 %b) {
708; GFX9-LABEL: srem32:
709; GFX9:       ; %bb.0:
710; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
711; GFX9-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
712; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
713; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v2
714; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, v1
715; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v1
716; GFX9-NEXT:    v_ashrrev_i32_e32 v4, 31, v0
717; GFX9-NEXT:    v_add_u32_e32 v0, v0, v4
718; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v2
719; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
720; GFX9-NEXT:    v_mul_f32_e32 v2, 0x4f7ffffe, v2
721; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
722; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v2
723; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v3
724; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
725; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
726; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v1
727; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v2
728; GFX9-NEXT:    v_sub_u32_e32 v2, v0, v1
729; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
730; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
731; GFX9-NEXT:    v_sub_u32_e32 v2, v0, v1
732; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
733; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
734; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
735; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v4
736; GFX9-NEXT:    s_setpc_b64 s[30:31]
737  %d = srem i32 %a, %b
738  ret i32 %d
739}
740
741define i32 @urem32(i32 %a, i32 %b) {
742; GFX9-LABEL: urem32:
743; GFX9:       ; %bb.0:
744; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
745; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, v1
746; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v1
747; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v2
748; GFX9-NEXT:    v_mul_f32_e32 v2, 0x4f7ffffe, v2
749; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
750; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v2
751; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v3
752; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
753; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
754; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v1
755; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v2
756; GFX9-NEXT:    v_sub_u32_e32 v2, v0, v1
757; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
758; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
759; GFX9-NEXT:    v_sub_u32_e32 v2, v0, v1
760; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
761; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
762; GFX9-NEXT:    s_setpc_b64 s[30:31]
763  %d = urem i32 %a, %b
764  ret i32 %d
765}
766
767define <2 x i64> @sdivrem64(i64 %a, i64 %b) {
768; GFX9-LABEL: sdivrem64:
769; GFX9:       ; %bb.0:
770; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
771; GFX9-NEXT:    v_or_b32_e32 v5, v1, v3
772; GFX9-NEXT:    v_mov_b32_e32 v4, 0
773; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[4:5]
774; GFX9-NEXT:    ; implicit-def: $vgpr6_vgpr7
775; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5
776; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
777; GFX9-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
778; GFX9-NEXT:    s_cbranch_execz BB8_2
779; GFX9-NEXT:  ; %bb.1:
780; GFX9-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
781; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
782; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
783; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
784; GFX9-NEXT:    v_xor_b32_e32 v3, v3, v4
785; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v2
786; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, v3
787; GFX9-NEXT:    v_sub_co_u32_e32 v7, vcc, 0, v2
788; GFX9-NEXT:    v_subb_co_u32_e32 v8, vcc, 0, v3, vcc
789; GFX9-NEXT:    v_mov_b32_e32 v15, 0
790; GFX9-NEXT:    v_mac_f32_e32 v5, 0x4f800000, v6
791; GFX9-NEXT:    v_rcp_f32_e32 v5, v5
792; GFX9-NEXT:    v_mov_b32_e32 v14, 0
793; GFX9-NEXT:    v_mul_f32_e32 v5, 0x5f7ffffc, v5
794; GFX9-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v5
795; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
796; GFX9-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v6
797; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
798; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v6
799; GFX9-NEXT:    v_mul_lo_u32 v9, v8, v5
800; GFX9-NEXT:    v_mul_hi_u32 v10, v7, v5
801; GFX9-NEXT:    v_mul_lo_u32 v11, v7, v6
802; GFX9-NEXT:    v_mul_lo_u32 v12, v7, v5
803; GFX9-NEXT:    v_add3_u32 v9, v10, v11, v9
804; GFX9-NEXT:    v_mul_lo_u32 v11, v5, v9
805; GFX9-NEXT:    v_mul_hi_u32 v13, v5, v12
806; GFX9-NEXT:    v_mul_hi_u32 v10, v5, v9
807; GFX9-NEXT:    v_mul_hi_u32 v16, v6, v9
808; GFX9-NEXT:    v_mul_lo_u32 v9, v6, v9
809; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v13, v11
810; GFX9-NEXT:    v_mul_lo_u32 v13, v6, v12
811; GFX9-NEXT:    v_mul_hi_u32 v12, v6, v12
812; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v10, vcc
813; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v11, v13
814; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v10, v12, vcc
815; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v14, vcc
816; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
817; GFX9-NEXT:    v_add_co_u32_e64 v5, s[4:5], v5, v9
818; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v11, vcc
819; GFX9-NEXT:    v_addc_co_u32_e64 v9, vcc, v6, v10, s[4:5]
820; GFX9-NEXT:    v_mul_lo_u32 v11, v7, v9
821; GFX9-NEXT:    v_mul_hi_u32 v12, v7, v5
822; GFX9-NEXT:    v_mul_lo_u32 v8, v8, v5
823; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v5
824; GFX9-NEXT:    v_add_u32_e32 v6, v6, v10
825; GFX9-NEXT:    v_add3_u32 v8, v12, v11, v8
826; GFX9-NEXT:    v_mul_lo_u32 v13, v5, v8
827; GFX9-NEXT:    v_mul_hi_u32 v16, v5, v7
828; GFX9-NEXT:    v_mul_hi_u32 v17, v5, v8
829; GFX9-NEXT:    v_mul_hi_u32 v12, v9, v7
830; GFX9-NEXT:    v_mul_lo_u32 v7, v9, v7
831; GFX9-NEXT:    v_add_co_u32_e32 v13, vcc, v16, v13
832; GFX9-NEXT:    v_mul_hi_u32 v11, v9, v8
833; GFX9-NEXT:    v_addc_co_u32_e32 v16, vcc, v15, v17, vcc
834; GFX9-NEXT:    v_mul_lo_u32 v8, v9, v8
835; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v13, v7
836; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v16, v12, vcc
837; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v11, v14, vcc
838; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v8
839; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v15, v9, vcc
840; GFX9-NEXT:    v_addc_co_u32_e64 v6, vcc, v6, v8, s[4:5]
841; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v7
842; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
843; GFX9-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
844; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v7
845; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v7
846; GFX9-NEXT:    v_mul_lo_u32 v8, v0, v6
847; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v5
848; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v6
849; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v7, vcc
850; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v7
851; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
852; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v15, v10, vcc
853; GFX9-NEXT:    v_mul_lo_u32 v10, v1, v5
854; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v5
855; GFX9-NEXT:    v_mul_hi_u32 v11, v1, v6
856; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
857; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v8, v10
858; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v5, vcc
859; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v14, vcc
860; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v6
861; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v8, vcc
862; GFX9-NEXT:    v_mul_lo_u32 v8, v3, v5
863; GFX9-NEXT:    v_mul_lo_u32 v9, v2, v6
864; GFX9-NEXT:    v_mul_hi_u32 v10, v2, v5
865; GFX9-NEXT:    v_mul_lo_u32 v11, v2, v5
866; GFX9-NEXT:    v_add3_u32 v8, v10, v9, v8
867; GFX9-NEXT:    v_sub_u32_e32 v9, v1, v8
868; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, v0, v11
869; GFX9-NEXT:    v_subb_co_u32_e64 v9, s[4:5], v9, v3, vcc
870; GFX9-NEXT:    v_sub_co_u32_e64 v10, s[4:5], v0, v2
871; GFX9-NEXT:    v_subbrev_co_u32_e64 v11, s[6:7], 0, v9, s[4:5]
872; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v11, v3
873; GFX9-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[6:7]
874; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v10, v2
875; GFX9-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[6:7]
876; GFX9-NEXT:    v_cmp_eq_u32_e64 s[6:7], v11, v3
877; GFX9-NEXT:    v_cndmask_b32_e64 v12, v12, v13, s[6:7]
878; GFX9-NEXT:    v_add_co_u32_e64 v13, s[6:7], 2, v5
879; GFX9-NEXT:    v_addc_co_u32_e64 v14, s[6:7], 0, v6, s[6:7]
880; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v8, vcc
881; GFX9-NEXT:    v_add_co_u32_e64 v15, s[6:7], 1, v5
882; GFX9-NEXT:    v_addc_co_u32_e64 v16, s[6:7], 0, v6, s[6:7]
883; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
884; GFX9-NEXT:    v_cmp_ne_u32_e64 s[6:7], 0, v12
885; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
886; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
887; GFX9-NEXT:    v_cndmask_b32_e64 v12, v16, v14, s[6:7]
888; GFX9-NEXT:    v_cndmask_b32_e64 v14, 0, -1, vcc
889; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
890; GFX9-NEXT:    v_cndmask_b32_e32 v8, v8, v14, vcc
891; GFX9-NEXT:    v_subb_co_u32_e64 v3, s[4:5], v9, v3, s[4:5]
892; GFX9-NEXT:    v_sub_co_u32_e64 v2, s[4:5], v10, v2
893; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
894; GFX9-NEXT:    v_cndmask_b32_e64 v8, v15, v13, s[6:7]
895; GFX9-NEXT:    v_subbrev_co_u32_e64 v3, s[4:5], 0, v3, s[4:5]
896; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
897; GFX9-NEXT:    v_xor_b32_e32 v8, v7, v4
898; GFX9-NEXT:    v_cndmask_b32_e64 v2, v10, v2, s[6:7]
899; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v12, vcc
900; GFX9-NEXT:    v_xor_b32_e32 v4, v5, v8
901; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
902; GFX9-NEXT:    v_cndmask_b32_e64 v3, v11, v3, s[6:7]
903; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
904; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v8
905; GFX9-NEXT:    v_sub_co_u32_e64 v4, s[8:9], v4, v8
906; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v7
907; GFX9-NEXT:    v_subb_co_u32_e64 v5, s[8:9], v6, v8, s[8:9]
908; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v7
909; GFX9-NEXT:    v_sub_co_u32_e32 v6, vcc, v0, v7
910; GFX9-NEXT:    v_subb_co_u32_e32 v7, vcc, v1, v7, vcc
911; GFX9-NEXT:    ; implicit-def: $vgpr2_vgpr3
912; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1
913; GFX9-NEXT:  BB8_2: ; %Flow
914; GFX9-NEXT:    s_or_saveexec_b64 s[4:5], s[10:11]
915; GFX9-NEXT:    s_xor_b64 exec, exec, s[4:5]
916; GFX9-NEXT:    s_cbranch_execz BB8_4
917; GFX9-NEXT:  ; %bb.3:
918; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
919; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v2
920; GFX9-NEXT:    v_mov_b32_e32 v5, 0
921; GFX9-NEXT:    v_mov_b32_e32 v7, v5
922; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
923; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
924; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
925; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v1
926; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
927; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
928; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
929; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v2
930; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
931; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v3
932; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
933; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v2
934; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
935; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
936; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v2
937; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
938; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
939; GFX9-NEXT:    v_cndmask_b32_e32 v6, v0, v3, vcc
940; GFX9-NEXT:    v_cndmask_b32_e32 v4, v1, v4, vcc
941; GFX9-NEXT:  BB8_4:
942; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
943; GFX9-NEXT:    v_mov_b32_e32 v0, v4
944; GFX9-NEXT:    v_mov_b32_e32 v1, v5
945; GFX9-NEXT:    v_mov_b32_e32 v2, v6
946; GFX9-NEXT:    v_mov_b32_e32 v3, v7
947; GFX9-NEXT:    s_setpc_b64 s[30:31]
948  %d = sdiv i64 %a, %b
949  %r = srem i64 %a, %b
950  %ins.0 = insertelement <2 x i64> undef, i64 %d, i32 0
951  %ins.1 = insertelement <2 x i64> %ins.0, i64 %r, i32 1
952  ret <2 x i64> %ins.1
953}
954
955define <2 x i64> @udivrem64(i64 %a, i64 %b) {
956; GFX9-LABEL: udivrem64:
957; GFX9:       ; %bb.0:
958; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
959; GFX9-NEXT:    v_or_b32_e32 v5, v1, v3
960; GFX9-NEXT:    v_mov_b32_e32 v4, 0
961; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[4:5]
962; GFX9-NEXT:    ; implicit-def: $vgpr6_vgpr7
963; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5
964; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
965; GFX9-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
966; GFX9-NEXT:    s_cbranch_execz BB9_2
967; GFX9-NEXT:  ; %bb.1:
968; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, v2
969; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v3
970; GFX9-NEXT:    v_sub_co_u32_e32 v6, vcc, 0, v2
971; GFX9-NEXT:    v_subb_co_u32_e32 v7, vcc, 0, v3, vcc
972; GFX9-NEXT:    v_mov_b32_e32 v13, 0
973; GFX9-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
974; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
975; GFX9-NEXT:    v_mov_b32_e32 v12, 0
976; GFX9-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
977; GFX9-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
978; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
979; GFX9-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
980; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
981; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
982; GFX9-NEXT:    v_mul_lo_u32 v9, v7, v4
983; GFX9-NEXT:    v_mul_lo_u32 v8, v6, v5
984; GFX9-NEXT:    v_mul_hi_u32 v10, v6, v4
985; GFX9-NEXT:    v_mul_lo_u32 v11, v6, v4
986; GFX9-NEXT:    v_add3_u32 v8, v10, v8, v9
987; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v11
988; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v8
989; GFX9-NEXT:    v_mul_hi_u32 v14, v4, v8
990; GFX9-NEXT:    v_mul_hi_u32 v15, v5, v8
991; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
992; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v10
993; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v14, vcc
994; GFX9-NEXT:    v_mul_lo_u32 v14, v5, v11
995; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v11
996; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v14
997; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
998; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v12, vcc
999; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
1000; GFX9-NEXT:    v_add_co_u32_e64 v4, s[4:5], v4, v8
1001; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v13, v10, vcc
1002; GFX9-NEXT:    v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5]
1003; GFX9-NEXT:    v_mul_lo_u32 v10, v6, v8
1004; GFX9-NEXT:    v_mul_hi_u32 v11, v6, v4
1005; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v4
1006; GFX9-NEXT:    v_mul_lo_u32 v6, v6, v4
1007; GFX9-NEXT:    v_add_u32_e32 v5, v5, v9
1008; GFX9-NEXT:    v_add3_u32 v7, v11, v10, v7
1009; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v7
1010; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v6
1011; GFX9-NEXT:    v_mul_hi_u32 v15, v4, v7
1012; GFX9-NEXT:    v_mul_hi_u32 v14, v8, v7
1013; GFX9-NEXT:    v_mul_lo_u32 v7, v8, v7
1014; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
1015; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v6
1016; GFX9-NEXT:    v_mul_lo_u32 v6, v8, v6
1017; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
1018; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v10, v6
1019; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v11, vcc
1020; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v14, v12, vcc
1021; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v7
1022; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
1023; GFX9-NEXT:    v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5]
1024; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
1025; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
1026; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v5
1027; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v4
1028; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v5
1029; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v5
1030; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
1031; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
1032; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
1033; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
1034; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
1035; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v8
1036; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
1037; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v9, v12, vcc
1038; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v5
1039; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v13, v6, vcc
1040; GFX9-NEXT:    v_mul_lo_u32 v6, v3, v4
1041; GFX9-NEXT:    v_mul_lo_u32 v7, v2, v5
1042; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v4
1043; GFX9-NEXT:    v_mul_lo_u32 v9, v2, v4
1044; GFX9-NEXT:    v_add3_u32 v6, v8, v7, v6
1045; GFX9-NEXT:    v_sub_u32_e32 v7, v1, v6
1046; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, v0, v9
1047; GFX9-NEXT:    v_subb_co_u32_e64 v7, s[4:5], v7, v3, vcc
1048; GFX9-NEXT:    v_sub_co_u32_e64 v8, s[4:5], v0, v2
1049; GFX9-NEXT:    v_subbrev_co_u32_e64 v9, s[6:7], 0, v7, s[4:5]
1050; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v9, v3
1051; GFX9-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[6:7]
1052; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v8, v2
1053; GFX9-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[6:7]
1054; GFX9-NEXT:    v_cmp_eq_u32_e64 s[6:7], v9, v3
1055; GFX9-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[6:7]
1056; GFX9-NEXT:    v_add_co_u32_e64 v11, s[6:7], 2, v4
1057; GFX9-NEXT:    v_addc_co_u32_e64 v12, s[6:7], 0, v5, s[6:7]
1058; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v6, vcc
1059; GFX9-NEXT:    v_add_co_u32_e64 v13, s[6:7], 1, v4
1060; GFX9-NEXT:    v_addc_co_u32_e64 v14, s[6:7], 0, v5, s[6:7]
1061; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
1062; GFX9-NEXT:    v_cmp_ne_u32_e64 s[6:7], 0, v10
1063; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1064; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
1065; GFX9-NEXT:    v_cndmask_b32_e64 v10, v14, v12, s[6:7]
1066; GFX9-NEXT:    v_cndmask_b32_e64 v12, 0, -1, vcc
1067; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
1068; GFX9-NEXT:    v_subb_co_u32_e64 v3, s[4:5], v7, v3, s[4:5]
1069; GFX9-NEXT:    v_sub_co_u32_e64 v2, s[4:5], v8, v2
1070; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v12, vcc
1071; GFX9-NEXT:    v_subbrev_co_u32_e64 v3, s[4:5], 0, v3, s[4:5]
1072; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
1073; GFX9-NEXT:    v_cndmask_b32_e64 v3, v9, v3, s[6:7]
1074; GFX9-NEXT:    v_cndmask_b32_e64 v6, v13, v11, s[6:7]
1075; GFX9-NEXT:    v_cndmask_b32_e32 v7, v1, v3, vcc
1076; GFX9-NEXT:    v_cndmask_b32_e64 v1, v8, v2, s[6:7]
1077; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
1078; GFX9-NEXT:    v_cndmask_b32_e32 v6, v0, v1, vcc
1079; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v10, vcc
1080; GFX9-NEXT:    ; implicit-def: $vgpr2_vgpr3
1081; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1
1082; GFX9-NEXT:  BB9_2: ; %Flow
1083; GFX9-NEXT:    s_or_saveexec_b64 s[4:5], s[8:9]
1084; GFX9-NEXT:    s_xor_b64 exec, exec, s[4:5]
1085; GFX9-NEXT:    s_cbranch_execz BB9_4
1086; GFX9-NEXT:  ; %bb.3:
1087; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
1088; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v2
1089; GFX9-NEXT:    v_mov_b32_e32 v5, 0
1090; GFX9-NEXT:    v_mov_b32_e32 v7, v5
1091; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1092; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
1093; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
1094; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v1
1095; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
1096; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
1097; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
1098; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v2
1099; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
1100; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v3
1101; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
1102; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v2
1103; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1104; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
1105; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v2
1106; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
1107; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
1108; GFX9-NEXT:    v_cndmask_b32_e32 v6, v0, v3, vcc
1109; GFX9-NEXT:    v_cndmask_b32_e32 v4, v1, v4, vcc
1110; GFX9-NEXT:  BB9_4:
1111; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
1112; GFX9-NEXT:    v_mov_b32_e32 v0, v4
1113; GFX9-NEXT:    v_mov_b32_e32 v1, v5
1114; GFX9-NEXT:    v_mov_b32_e32 v2, v6
1115; GFX9-NEXT:    v_mov_b32_e32 v3, v7
1116; GFX9-NEXT:    s_setpc_b64 s[30:31]
1117  %d = udiv i64 %a, %b
1118  %r = urem i64 %a, %b
1119  %ins.0 = insertelement <2 x i64> undef, i64 %d, i32 0
1120  %ins.1 = insertelement <2 x i64> %ins.0, i64 %r, i32 1
1121  ret <2 x i64> %ins.1
1122}
1123
1124define i64 @sdiv64_known32(i64 %a, i64 %b) {
1125; GFX9-LABEL: sdiv64_known32:
1126; GFX9:       ; %bb.0:
1127; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1128; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, v3
1129; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v1
1130; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
1131; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
1132; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
1133; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v2
1134; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
1135; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1136; GFX9-NEXT:    v_mov_b32_e32 v1, 0
1137; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
1138; GFX9-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
1139; GFX9-NEXT:    s_setpc_b64 s[30:31]
1140  %a.ext = ashr i64 %a, 32
1141  %b.ext = ashr i64 %b, 32
1142  %d = udiv i64 %a.ext, %b.ext
1143  ret i64 %d
1144}
1145
1146define i64 @udiv64_known32(i64 %a, i64 %b) {
1147; GFX9-LABEL: udiv64_known32:
1148; GFX9:       ; %bb.0:
1149; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1150; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
1151; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, v0
1152; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1153; GFX9-NEXT:    v_mul_f32_e32 v2, v0, v2
1154; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
1155; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v2
1156; GFX9-NEXT:    v_mad_f32 v0, -v2, v1, v0
1157; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, v1
1158; GFX9-NEXT:    v_mov_b32_e32 v1, 0
1159; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
1160; GFX9-NEXT:    s_setpc_b64 s[30:31]
1161  %a.mask = and i64 %a, 4294967295
1162  %b.mask = and i64 %b, 4294967295
1163  %d = udiv i64 %a.mask, %b.mask
1164  ret i64 %d
1165}
1166