1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
3
4; 64-bit divides and rems should be split into a fast and slow path
5; where the fast path uses a 32-bit operation.
6
7define i64 @sdiv64(i64 %a, i64 %b) {
8; GFX9-LABEL: sdiv64:
9; GFX9:       ; %bb.0:
10; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
11; GFX9-NEXT:    v_mov_b32_e32 v5, v3
12; GFX9-NEXT:    v_or_b32_e32 v4, v1, v5
13; GFX9-NEXT:    v_mov_b32_e32 v3, 0
14; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[3:4]
15; GFX9-NEXT:    ; implicit-def: $vgpr3_vgpr4
16; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
17; GFX9-NEXT:    s_xor_b64 s[6:7], exec, s[4:5]
18; GFX9-NEXT:    s_cbranch_execz BB0_2
19; GFX9-NEXT:  ; %bb.1:
20; GFX9-NEXT:    v_ashrrev_i32_e32 v3, 31, v5
21; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v2, v3
22; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v5, v3, vcc
23; GFX9-NEXT:    v_xor_b32_e32 v4, v4, v3
24; GFX9-NEXT:    v_xor_b32_e32 v5, v5, v3
25; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, v4
26; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, v5
27; GFX9-NEXT:    v_sub_co_u32_e32 v8, vcc, 0, v4
28; GFX9-NEXT:    v_subb_co_u32_e32 v9, vcc, 0, v5, vcc
29; GFX9-NEXT:    v_mov_b32_e32 v16, 0
30; GFX9-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v7
31; GFX9-NEXT:    v_rcp_f32_e32 v6, v6
32; GFX9-NEXT:    v_mov_b32_e32 v15, 0
33; GFX9-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
34; GFX9-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v6
35; GFX9-NEXT:    v_trunc_f32_e32 v7, v7
36; GFX9-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v7
37; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v6
38; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v7
39; GFX9-NEXT:    v_mul_lo_u32 v10, v9, v6
40; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v6
41; GFX9-NEXT:    v_mul_lo_u32 v12, v8, v7
42; GFX9-NEXT:    v_mul_lo_u32 v13, v8, v6
43; GFX9-NEXT:    v_add3_u32 v10, v11, v12, v10
44; GFX9-NEXT:    v_mul_lo_u32 v12, v6, v10
45; GFX9-NEXT:    v_mul_hi_u32 v14, v6, v13
46; GFX9-NEXT:    v_mul_hi_u32 v11, v6, v10
47; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v14, v12
48; GFX9-NEXT:    v_mul_lo_u32 v14, v7, v13
49; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v11, vcc
50; GFX9-NEXT:    v_mul_hi_u32 v13, v7, v13
51; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v12, v14
52; GFX9-NEXT:    v_mul_hi_u32 v12, v7, v10
53; GFX9-NEXT:    v_mul_lo_u32 v10, v7, v10
54; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v11, v13, vcc
55; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v12, v15, vcc
56; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
57; GFX9-NEXT:    v_add_co_u32_e64 v6, s[4:5], v6, v10
58; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v12, vcc
59; GFX9-NEXT:    v_addc_co_u32_e64 v10, vcc, v7, v11, s[4:5]
60; GFX9-NEXT:    v_mul_lo_u32 v12, v8, v10
61; GFX9-NEXT:    v_mul_hi_u32 v13, v8, v6
62; GFX9-NEXT:    v_mul_lo_u32 v9, v9, v6
63; GFX9-NEXT:    v_mul_lo_u32 v8, v8, v6
64; GFX9-NEXT:    v_add_u32_e32 v7, v7, v11
65; GFX9-NEXT:    v_add3_u32 v9, v13, v12, v9
66; GFX9-NEXT:    v_mul_lo_u32 v12, v6, v9
67; GFX9-NEXT:    v_mul_hi_u32 v13, v6, v8
68; GFX9-NEXT:    v_mul_hi_u32 v14, v6, v9
69; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v13, v12
70; GFX9-NEXT:    v_mul_hi_u32 v13, v10, v8
71; GFX9-NEXT:    v_mul_lo_u32 v8, v10, v8
72; GFX9-NEXT:    v_addc_co_u32_e32 v14, vcc, v16, v14, vcc
73; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v12, v8
74; GFX9-NEXT:    v_mul_hi_u32 v8, v10, v9
75; GFX9-NEXT:    v_mul_lo_u32 v9, v10, v9
76; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v14, v13, vcc
77; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v8, v15, vcc
78; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v12, v9
79; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v16, v8, vcc
80; GFX9-NEXT:    v_addc_co_u32_e64 v7, vcc, v7, v8, s[4:5]
81; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v9
82; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
83; GFX9-NEXT:    v_ashrrev_i32_e32 v8, 31, v1
84; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v0, v8
85; GFX9-NEXT:    v_xor_b32_e32 v9, v9, v8
86; GFX9-NEXT:    v_mul_lo_u32 v10, v9, v7
87; GFX9-NEXT:    v_mul_hi_u32 v11, v9, v6
88; GFX9-NEXT:    v_mul_hi_u32 v12, v9, v7
89; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v8, vcc
90; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v8
91; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
92; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v12, vcc
93; GFX9-NEXT:    v_mul_lo_u32 v12, v1, v6
94; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v6
95; GFX9-NEXT:    v_mul_hi_u32 v13, v1, v7
96; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v7
97; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v10, v12
98; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v11, v6, vcc
99; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v15, vcc
100; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v7
101; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v16, v10, vcc
102; GFX9-NEXT:    v_mul_lo_u32 v10, v5, v6
103; GFX9-NEXT:    v_mul_lo_u32 v11, v4, v7
104; GFX9-NEXT:    v_mul_hi_u32 v12, v4, v6
105; GFX9-NEXT:    v_mul_lo_u32 v13, v4, v6
106; GFX9-NEXT:    v_add3_u32 v10, v12, v11, v10
107; GFX9-NEXT:    v_sub_u32_e32 v11, v1, v10
108; GFX9-NEXT:    v_sub_co_u32_e32 v9, vcc, v9, v13
109; GFX9-NEXT:    v_subb_co_u32_e64 v11, s[4:5], v11, v5, vcc
110; GFX9-NEXT:    v_sub_co_u32_e64 v12, s[4:5], v9, v4
111; GFX9-NEXT:    v_subbrev_co_u32_e64 v11, s[4:5], 0, v11, s[4:5]
112; GFX9-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v5
113; GFX9-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
114; GFX9-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v4
115; GFX9-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
116; GFX9-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v5
117; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v10, vcc
118; GFX9-NEXT:    v_cndmask_b32_e64 v11, v13, v12, s[4:5]
119; GFX9-NEXT:    v_add_co_u32_e64 v12, s[4:5], 2, v6
120; GFX9-NEXT:    v_addc_co_u32_e64 v13, s[4:5], 0, v7, s[4:5]
121; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v5
122; GFX9-NEXT:    v_add_co_u32_e64 v14, s[4:5], 1, v6
123; GFX9-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
124; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v9, v4
125; GFX9-NEXT:    v_addc_co_u32_e64 v15, s[4:5], 0, v7, s[4:5]
126; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
127; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v5
128; GFX9-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v11
129; GFX9-NEXT:    v_cndmask_b32_e32 v1, v10, v4, vcc
130; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
131; GFX9-NEXT:    v_cndmask_b32_e64 v4, v14, v12, s[4:5]
132; GFX9-NEXT:    v_cndmask_b32_e64 v11, v15, v13, s[4:5]
133; GFX9-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
134; GFX9-NEXT:    v_xor_b32_e32 v5, v8, v3
135; GFX9-NEXT:    v_cndmask_b32_e32 v1, v7, v11, vcc
136; GFX9-NEXT:    v_xor_b32_e32 v3, v4, v5
137; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v5
138; GFX9-NEXT:    v_sub_co_u32_e32 v3, vcc, v3, v5
139; GFX9-NEXT:    v_subb_co_u32_e32 v4, vcc, v1, v5, vcc
140; GFX9-NEXT:  BB0_2: ; %Flow
141; GFX9-NEXT:    s_or_saveexec_b64 s[4:5], s[6:7]
142; GFX9-NEXT:    s_xor_b64 exec, exec, s[4:5]
143; GFX9-NEXT:    s_cbranch_execz BB0_4
144; GFX9-NEXT:  ; %bb.3:
145; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
146; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v2
147; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
148; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
149; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
150; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v1
151; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
152; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
153; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
154; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v2
155; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
156; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v3
157; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
158; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v2
159; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
160; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
161; GFX9-NEXT:    v_add_u32_e32 v3, 1, v1
162; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
163; GFX9-NEXT:    v_cndmask_b32_e32 v3, v1, v3, vcc
164; GFX9-NEXT:    v_mov_b32_e32 v4, 0
165; GFX9-NEXT:  BB0_4:
166; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
167; GFX9-NEXT:    v_mov_b32_e32 v0, v3
168; GFX9-NEXT:    v_mov_b32_e32 v1, v4
169; GFX9-NEXT:    s_setpc_b64 s[30:31]
170  %d = sdiv i64 %a, %b
171  ret i64 %d
172}
173
174define i64 @udiv64(i64 %a, i64 %b) {
175; GFX9-LABEL: udiv64:
176; GFX9:       ; %bb.0:
177; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
178; GFX9-NEXT:    v_or_b32_e32 v5, v1, v3
179; GFX9-NEXT:    v_mov_b32_e32 v4, 0
180; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[4:5]
181; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5
182; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
183; GFX9-NEXT:    s_xor_b64 s[6:7], exec, s[4:5]
184; GFX9-NEXT:    s_cbranch_execz BB1_2
185; GFX9-NEXT:  ; %bb.1:
186; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, v2
187; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v3
188; GFX9-NEXT:    v_sub_co_u32_e32 v6, vcc, 0, v2
189; GFX9-NEXT:    v_subb_co_u32_e32 v7, vcc, 0, v3, vcc
190; GFX9-NEXT:    v_mov_b32_e32 v13, 0
191; GFX9-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
192; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
193; GFX9-NEXT:    v_mov_b32_e32 v12, 0
194; GFX9-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
195; GFX9-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
196; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
197; GFX9-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
198; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
199; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
200; GFX9-NEXT:    v_mul_lo_u32 v9, v7, v4
201; GFX9-NEXT:    v_mul_lo_u32 v8, v6, v5
202; GFX9-NEXT:    v_mul_hi_u32 v10, v6, v4
203; GFX9-NEXT:    v_mul_lo_u32 v11, v6, v4
204; GFX9-NEXT:    v_add3_u32 v8, v10, v8, v9
205; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v11
206; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v8
207; GFX9-NEXT:    v_mul_hi_u32 v14, v4, v8
208; GFX9-NEXT:    v_mul_hi_u32 v15, v5, v8
209; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
210; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v10
211; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v14, vcc
212; GFX9-NEXT:    v_mul_lo_u32 v14, v5, v11
213; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v11
214; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v14
215; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
216; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v12, vcc
217; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
218; GFX9-NEXT:    v_add_co_u32_e64 v4, s[4:5], v4, v8
219; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v13, v10, vcc
220; GFX9-NEXT:    v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5]
221; GFX9-NEXT:    v_mul_lo_u32 v10, v6, v8
222; GFX9-NEXT:    v_mul_hi_u32 v11, v6, v4
223; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v4
224; GFX9-NEXT:    v_mul_lo_u32 v6, v6, v4
225; GFX9-NEXT:    v_add_u32_e32 v5, v5, v9
226; GFX9-NEXT:    v_add3_u32 v7, v11, v10, v7
227; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v7
228; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v6
229; GFX9-NEXT:    v_mul_hi_u32 v15, v4, v7
230; GFX9-NEXT:    v_mul_hi_u32 v14, v8, v7
231; GFX9-NEXT:    v_mul_lo_u32 v7, v8, v7
232; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
233; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v6
234; GFX9-NEXT:    v_mul_lo_u32 v6, v8, v6
235; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
236; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v10, v6
237; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v11, vcc
238; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v14, v12, vcc
239; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v7
240; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
241; GFX9-NEXT:    v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5]
242; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
243; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
244; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v5
245; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v4
246; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v5
247; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v5
248; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
249; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
250; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
251; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
252; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
253; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v8
254; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
255; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v9, v12, vcc
256; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v5
257; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v13, v6, vcc
258; GFX9-NEXT:    v_mul_lo_u32 v6, v3, v4
259; GFX9-NEXT:    v_mul_lo_u32 v7, v2, v5
260; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v4
261; GFX9-NEXT:    v_mul_lo_u32 v9, v2, v4
262; GFX9-NEXT:    v_add3_u32 v6, v8, v7, v6
263; GFX9-NEXT:    v_sub_u32_e32 v7, v1, v6
264; GFX9-NEXT:    v_sub_co_u32_e32 v8, vcc, v0, v9
265; GFX9-NEXT:    v_subb_co_u32_e64 v7, s[4:5], v7, v3, vcc
266; GFX9-NEXT:    v_sub_co_u32_e64 v9, s[4:5], v8, v2
267; GFX9-NEXT:    v_subbrev_co_u32_e64 v7, s[4:5], 0, v7, s[4:5]
268; GFX9-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v3
269; GFX9-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
270; GFX9-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v2
271; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
272; GFX9-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v3
273; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v6, vcc
274; GFX9-NEXT:    v_cndmask_b32_e64 v7, v10, v9, s[4:5]
275; GFX9-NEXT:    v_add_co_u32_e64 v9, s[4:5], 2, v4
276; GFX9-NEXT:    v_addc_co_u32_e64 v10, s[4:5], 0, v5, s[4:5]
277; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
278; GFX9-NEXT:    v_add_co_u32_e64 v11, s[4:5], 1, v4
279; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
280; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v8, v2
281; GFX9-NEXT:    v_addc_co_u32_e64 v12, s[4:5], 0, v5, s[4:5]
282; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
283; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
284; GFX9-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
285; GFX9-NEXT:    v_cndmask_b32_e32 v1, v6, v8, vcc
286; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
287; GFX9-NEXT:    v_cndmask_b32_e64 v7, v12, v10, s[4:5]
288; GFX9-NEXT:    v_cndmask_b32_e64 v1, v11, v9, s[4:5]
289; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
290; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v1, vcc
291; GFX9-NEXT:  BB1_2: ; %Flow
292; GFX9-NEXT:    s_or_saveexec_b64 s[4:5], s[6:7]
293; GFX9-NEXT:    s_xor_b64 exec, exec, s[4:5]
294; GFX9-NEXT:    s_cbranch_execz BB1_4
295; GFX9-NEXT:  ; %bb.3:
296; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
297; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v2
298; GFX9-NEXT:    v_mov_b32_e32 v5, 0
299; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
300; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
301; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
302; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v1
303; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
304; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
305; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
306; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v2
307; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
308; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v3
309; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
310; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v2
311; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
312; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
313; GFX9-NEXT:    v_add_u32_e32 v3, 1, v1
314; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
315; GFX9-NEXT:    v_cndmask_b32_e32 v4, v1, v3, vcc
316; GFX9-NEXT:  BB1_4:
317; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
318; GFX9-NEXT:    v_mov_b32_e32 v0, v4
319; GFX9-NEXT:    v_mov_b32_e32 v1, v5
320; GFX9-NEXT:    s_setpc_b64 s[30:31]
321  %d = udiv i64 %a, %b
322  ret i64 %d
323}
324
325define i64 @srem64(i64 %a, i64 %b) {
326; GFX9-LABEL: srem64:
327; GFX9:       ; %bb.0:
328; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
329; GFX9-NEXT:    v_mov_b32_e32 v5, v3
330; GFX9-NEXT:    v_or_b32_e32 v4, v1, v5
331; GFX9-NEXT:    v_mov_b32_e32 v3, 0
332; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[3:4]
333; GFX9-NEXT:    ; implicit-def: $vgpr3_vgpr4
334; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
335; GFX9-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
336; GFX9-NEXT:    s_cbranch_execz BB2_2
337; GFX9-NEXT:  ; %bb.1:
338; GFX9-NEXT:    v_ashrrev_i32_e32 v3, 31, v5
339; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v2, v3
340; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v5, v3, vcc
341; GFX9-NEXT:    v_xor_b32_e32 v5, v5, v3
342; GFX9-NEXT:    v_xor_b32_e32 v3, v4, v3
343; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, v3
344; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, v5
345; GFX9-NEXT:    v_sub_co_u32_e32 v7, vcc, 0, v3
346; GFX9-NEXT:    v_subb_co_u32_e32 v8, vcc, 0, v5, vcc
347; GFX9-NEXT:    v_mov_b32_e32 v15, 0
348; GFX9-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v6
349; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
350; GFX9-NEXT:    v_mov_b32_e32 v14, 0
351; GFX9-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
352; GFX9-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v4
353; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
354; GFX9-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v6
355; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
356; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v6
357; GFX9-NEXT:    v_mul_lo_u32 v9, v8, v4
358; GFX9-NEXT:    v_mul_hi_u32 v10, v7, v4
359; GFX9-NEXT:    v_mul_lo_u32 v11, v7, v6
360; GFX9-NEXT:    v_mul_lo_u32 v12, v7, v4
361; GFX9-NEXT:    v_add3_u32 v9, v10, v11, v9
362; GFX9-NEXT:    v_mul_lo_u32 v11, v4, v9
363; GFX9-NEXT:    v_mul_hi_u32 v13, v4, v12
364; GFX9-NEXT:    v_mul_hi_u32 v10, v4, v9
365; GFX9-NEXT:    v_mul_hi_u32 v16, v6, v9
366; GFX9-NEXT:    v_mul_lo_u32 v9, v6, v9
367; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v13, v11
368; GFX9-NEXT:    v_mul_lo_u32 v13, v6, v12
369; GFX9-NEXT:    v_mul_hi_u32 v12, v6, v12
370; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v10, vcc
371; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v11, v13
372; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v10, v12, vcc
373; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v14, vcc
374; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
375; GFX9-NEXT:    v_add_co_u32_e64 v4, s[4:5], v4, v9
376; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v11, vcc
377; GFX9-NEXT:    v_addc_co_u32_e64 v9, vcc, v6, v10, s[4:5]
378; GFX9-NEXT:    v_mul_lo_u32 v11, v7, v9
379; GFX9-NEXT:    v_mul_hi_u32 v12, v7, v4
380; GFX9-NEXT:    v_mul_lo_u32 v8, v8, v4
381; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v4
382; GFX9-NEXT:    v_add_u32_e32 v6, v6, v10
383; GFX9-NEXT:    v_add3_u32 v8, v12, v11, v8
384; GFX9-NEXT:    v_mul_lo_u32 v11, v4, v8
385; GFX9-NEXT:    v_mul_hi_u32 v12, v4, v7
386; GFX9-NEXT:    v_mul_hi_u32 v16, v4, v8
387; GFX9-NEXT:    v_mul_hi_u32 v13, v9, v8
388; GFX9-NEXT:    v_mul_lo_u32 v8, v9, v8
389; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v12, v11
390; GFX9-NEXT:    v_mul_hi_u32 v12, v9, v7
391; GFX9-NEXT:    v_mul_lo_u32 v7, v9, v7
392; GFX9-NEXT:    v_addc_co_u32_e32 v16, vcc, v15, v16, vcc
393; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v11, v7
394; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v16, v12, vcc
395; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v13, v14, vcc
396; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v8
397; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v15, v9, vcc
398; GFX9-NEXT:    v_addc_co_u32_e64 v6, vcc, v6, v8, s[4:5]
399; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v7
400; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
401; GFX9-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
402; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v0, v7
403; GFX9-NEXT:    v_xor_b32_e32 v8, v8, v7
404; GFX9-NEXT:    v_mul_lo_u32 v9, v8, v6
405; GFX9-NEXT:    v_mul_hi_u32 v10, v8, v4
406; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v6
407; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v7, vcc
408; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v7
409; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
410; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v11, vcc
411; GFX9-NEXT:    v_mul_lo_u32 v11, v1, v4
412; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
413; GFX9-NEXT:    v_mul_hi_u32 v12, v1, v6
414; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
415; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v11
416; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v4, vcc
417; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v12, v14, vcc
418; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
419; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v9, vcc
420; GFX9-NEXT:    v_mul_lo_u32 v9, v5, v4
421; GFX9-NEXT:    v_mul_hi_u32 v10, v3, v4
422; GFX9-NEXT:    v_mul_lo_u32 v6, v3, v6
423; GFX9-NEXT:    v_mul_lo_u32 v4, v3, v4
424; GFX9-NEXT:    v_add3_u32 v6, v10, v6, v9
425; GFX9-NEXT:    v_sub_u32_e32 v9, v1, v6
426; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, v8, v4
427; GFX9-NEXT:    v_subb_co_u32_e64 v8, s[4:5], v9, v5, vcc
428; GFX9-NEXT:    v_sub_co_u32_e64 v9, s[4:5], v4, v3
429; GFX9-NEXT:    v_subbrev_co_u32_e64 v10, s[6:7], 0, v8, s[4:5]
430; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v10, v5
431; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v6, vcc
432; GFX9-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[6:7]
433; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v9, v3
434; GFX9-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[6:7]
435; GFX9-NEXT:    v_cmp_eq_u32_e64 s[6:7], v10, v5
436; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v5
437; GFX9-NEXT:    v_subb_co_u32_e64 v8, s[4:5], v8, v5, s[4:5]
438; GFX9-NEXT:    v_cndmask_b32_e64 v11, v11, v12, s[6:7]
439; GFX9-NEXT:    v_sub_co_u32_e64 v12, s[4:5], v9, v3
440; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
441; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v3
442; GFX9-NEXT:    v_subbrev_co_u32_e64 v8, s[4:5], 0, v8, s[4:5]
443; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
444; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v5
445; GFX9-NEXT:    v_cndmask_b32_e32 v3, v6, v3, vcc
446; GFX9-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v11
447; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
448; GFX9-NEXT:    v_cndmask_b32_e64 v3, v9, v12, s[4:5]
449; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
450; GFX9-NEXT:    v_cndmask_b32_e64 v8, v10, v8, s[4:5]
451; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v8, vcc
452; GFX9-NEXT:    v_xor_b32_e32 v3, v3, v7
453; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v7
454; GFX9-NEXT:    v_sub_co_u32_e32 v3, vcc, v3, v7
455; GFX9-NEXT:    v_subb_co_u32_e32 v4, vcc, v1, v7, vcc
456; GFX9-NEXT:  BB2_2: ; %Flow
457; GFX9-NEXT:    s_or_saveexec_b64 s[4:5], s[8:9]
458; GFX9-NEXT:    s_xor_b64 exec, exec, s[4:5]
459; GFX9-NEXT:    s_cbranch_execz BB2_4
460; GFX9-NEXT:  ; %bb.3:
461; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
462; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v2
463; GFX9-NEXT:    v_mov_b32_e32 v4, 0
464; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
465; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
466; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
467; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v1
468; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
469; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
470; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
471; GFX9-NEXT:    v_mul_lo_u32 v1, v1, v2
472; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v1
473; GFX9-NEXT:    v_sub_u32_e32 v1, v0, v2
474; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
475; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
476; GFX9-NEXT:    v_sub_u32_e32 v1, v0, v2
477; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
478; GFX9-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
479; GFX9-NEXT:  BB2_4:
480; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
481; GFX9-NEXT:    v_mov_b32_e32 v0, v3
482; GFX9-NEXT:    v_mov_b32_e32 v1, v4
483; GFX9-NEXT:    s_setpc_b64 s[30:31]
484  %d = srem i64 %a, %b
485  ret i64 %d
486}
487
488define i64 @urem64(i64 %a, i64 %b) {
489; GFX9-LABEL: urem64:
490; GFX9:       ; %bb.0:
491; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
492; GFX9-NEXT:    v_or_b32_e32 v5, v1, v3
493; GFX9-NEXT:    v_mov_b32_e32 v4, 0
494; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[4:5]
495; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5
496; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
497; GFX9-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
498; GFX9-NEXT:    s_cbranch_execz BB3_2
499; GFX9-NEXT:  ; %bb.1:
500; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, v2
501; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v3
502; GFX9-NEXT:    v_sub_co_u32_e32 v6, vcc, 0, v2
503; GFX9-NEXT:    v_subb_co_u32_e32 v7, vcc, 0, v3, vcc
504; GFX9-NEXT:    v_mov_b32_e32 v13, 0
505; GFX9-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
506; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
507; GFX9-NEXT:    v_mov_b32_e32 v12, 0
508; GFX9-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
509; GFX9-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
510; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
511; GFX9-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
512; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
513; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
514; GFX9-NEXT:    v_mul_lo_u32 v9, v7, v4
515; GFX9-NEXT:    v_mul_lo_u32 v8, v6, v5
516; GFX9-NEXT:    v_mul_hi_u32 v10, v6, v4
517; GFX9-NEXT:    v_mul_lo_u32 v11, v6, v4
518; GFX9-NEXT:    v_add3_u32 v8, v10, v8, v9
519; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v11
520; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v8
521; GFX9-NEXT:    v_mul_hi_u32 v14, v4, v8
522; GFX9-NEXT:    v_mul_hi_u32 v15, v5, v8
523; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
524; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v10
525; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v14, vcc
526; GFX9-NEXT:    v_mul_lo_u32 v14, v5, v11
527; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v11
528; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v14
529; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
530; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v12, vcc
531; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
532; GFX9-NEXT:    v_add_co_u32_e64 v4, s[4:5], v4, v8
533; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v13, v10, vcc
534; GFX9-NEXT:    v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5]
535; GFX9-NEXT:    v_mul_lo_u32 v10, v6, v8
536; GFX9-NEXT:    v_mul_hi_u32 v11, v6, v4
537; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v4
538; GFX9-NEXT:    v_mul_lo_u32 v6, v6, v4
539; GFX9-NEXT:    v_add_u32_e32 v5, v5, v9
540; GFX9-NEXT:    v_add3_u32 v7, v11, v10, v7
541; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v7
542; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v6
543; GFX9-NEXT:    v_mul_hi_u32 v15, v4, v7
544; GFX9-NEXT:    v_mul_hi_u32 v14, v8, v7
545; GFX9-NEXT:    v_mul_lo_u32 v7, v8, v7
546; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
547; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v6
548; GFX9-NEXT:    v_mul_lo_u32 v6, v8, v6
549; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
550; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v10, v6
551; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v11, vcc
552; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v14, v12, vcc
553; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v7
554; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
555; GFX9-NEXT:    v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5]
556; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
557; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
558; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v5
559; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v4
560; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v5
561; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v5
562; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
563; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
564; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
565; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
566; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
567; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v8
568; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
569; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v9, v12, vcc
570; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v5
571; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v13, v6, vcc
572; GFX9-NEXT:    v_mul_lo_u32 v6, v3, v4
573; GFX9-NEXT:    v_mul_hi_u32 v7, v2, v4
574; GFX9-NEXT:    v_mul_lo_u32 v5, v2, v5
575; GFX9-NEXT:    v_mul_lo_u32 v4, v2, v4
576; GFX9-NEXT:    v_add3_u32 v5, v7, v5, v6
577; GFX9-NEXT:    v_sub_u32_e32 v6, v1, v5
578; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, v0, v4
579; GFX9-NEXT:    v_subb_co_u32_e64 v6, s[4:5], v6, v3, vcc
580; GFX9-NEXT:    v_sub_co_u32_e64 v7, s[4:5], v4, v2
581; GFX9-NEXT:    v_subbrev_co_u32_e64 v8, s[6:7], 0, v6, s[4:5]
582; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v8, v3
583; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[6:7]
584; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v7, v2
585; GFX9-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[6:7]
586; GFX9-NEXT:    v_cmp_eq_u32_e64 s[6:7], v8, v3
587; GFX9-NEXT:    v_subb_co_u32_e64 v6, s[4:5], v6, v3, s[4:5]
588; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v5, vcc
589; GFX9-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[6:7]
590; GFX9-NEXT:    v_sub_co_u32_e64 v10, s[4:5], v7, v2
591; GFX9-NEXT:    v_subbrev_co_u32_e64 v6, s[4:5], 0, v6, s[4:5]
592; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
593; GFX9-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v9
594; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
595; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v2
596; GFX9-NEXT:    v_cndmask_b32_e64 v6, v8, v6, s[4:5]
597; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
598; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
599; GFX9-NEXT:    v_cndmask_b32_e32 v3, v5, v8, vcc
600; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
601; GFX9-NEXT:    v_cndmask_b32_e32 v5, v1, v6, vcc
602; GFX9-NEXT:    v_cndmask_b32_e64 v1, v7, v10, s[4:5]
603; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v1, vcc
604; GFX9-NEXT:  BB3_2: ; %Flow
605; GFX9-NEXT:    s_or_saveexec_b64 s[4:5], s[8:9]
606; GFX9-NEXT:    s_xor_b64 exec, exec, s[4:5]
607; GFX9-NEXT:    s_cbranch_execz BB3_4
608; GFX9-NEXT:  ; %bb.3:
609; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
610; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v2
611; GFX9-NEXT:    v_mov_b32_e32 v5, 0
612; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
613; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
614; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
615; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v1
616; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
617; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
618; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
619; GFX9-NEXT:    v_mul_lo_u32 v1, v1, v2
620; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v1
621; GFX9-NEXT:    v_sub_u32_e32 v1, v0, v2
622; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
623; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
624; GFX9-NEXT:    v_sub_u32_e32 v1, v0, v2
625; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
626; GFX9-NEXT:    v_cndmask_b32_e32 v4, v0, v1, vcc
627; GFX9-NEXT:  BB3_4:
628; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
629; GFX9-NEXT:    v_mov_b32_e32 v0, v4
630; GFX9-NEXT:    v_mov_b32_e32 v1, v5
631; GFX9-NEXT:    s_setpc_b64 s[30:31]
632  %d = urem i64 %a, %b
633  ret i64 %d
634}
635
636define i32 @sdiv32(i32 %a, i32 %b) {
637; GFX9-LABEL: sdiv32:
638; GFX9:       ; %bb.0:
639; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
640; GFX9-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
641; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
642; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v2
643; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, v1
644; GFX9-NEXT:    v_sub_u32_e32 v4, 0, v1
645; GFX9-NEXT:    v_ashrrev_i32_e32 v5, 31, v0
646; GFX9-NEXT:    v_add_u32_e32 v0, v0, v5
647; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v3
648; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v5
649; GFX9-NEXT:    v_xor_b32_e32 v2, v5, v2
650; GFX9-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
651; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
652; GFX9-NEXT:    v_mul_lo_u32 v4, v4, v3
653; GFX9-NEXT:    v_mul_hi_u32 v4, v3, v4
654; GFX9-NEXT:    v_add_u32_e32 v3, v3, v4
655; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v3
656; GFX9-NEXT:    v_mul_lo_u32 v4, v3, v1
657; GFX9-NEXT:    v_add_u32_e32 v5, 1, v3
658; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v4
659; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
660; GFX9-NEXT:    v_sub_u32_e32 v4, v0, v1
661; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
662; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
663; GFX9-NEXT:    v_add_u32_e32 v4, 1, v3
664; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
665; GFX9-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc
666; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v2
667; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v2
668; GFX9-NEXT:    s_setpc_b64 s[30:31]
669  %d = sdiv i32 %a, %b
670  ret i32 %d
671}
672
673define i32 @udiv32(i32 %a, i32 %b) {
674; GFX9-LABEL: udiv32:
675; GFX9:       ; %bb.0:
676; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
677; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, v1
678; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v1
679; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v2
680; GFX9-NEXT:    v_mul_f32_e32 v2, 0x4f7ffffe, v2
681; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
682; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v2
683; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v3
684; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
685; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
686; GFX9-NEXT:    v_mul_lo_u32 v3, v2, v1
687; GFX9-NEXT:    v_add_u32_e32 v4, 1, v2
688; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v3
689; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
690; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v1
691; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
692; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
693; GFX9-NEXT:    v_add_u32_e32 v3, 1, v2
694; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
695; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc
696; GFX9-NEXT:    s_setpc_b64 s[30:31]
697  %d = udiv i32 %a, %b
698  ret i32 %d
699}
700
701define i32 @srem32(i32 %a, i32 %b) {
702; GFX9-LABEL: srem32:
703; GFX9:       ; %bb.0:
704; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
705; GFX9-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
706; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
707; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v2
708; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, v1
709; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v1
710; GFX9-NEXT:    v_ashrrev_i32_e32 v4, 31, v0
711; GFX9-NEXT:    v_add_u32_e32 v0, v0, v4
712; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v2
713; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
714; GFX9-NEXT:    v_mul_f32_e32 v2, 0x4f7ffffe, v2
715; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
716; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v2
717; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v3
718; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
719; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
720; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v1
721; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v2
722; GFX9-NEXT:    v_sub_u32_e32 v2, v0, v1
723; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
724; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
725; GFX9-NEXT:    v_sub_u32_e32 v2, v0, v1
726; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
727; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
728; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
729; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v4
730; GFX9-NEXT:    s_setpc_b64 s[30:31]
731  %d = srem i32 %a, %b
732  ret i32 %d
733}
734
735define i32 @urem32(i32 %a, i32 %b) {
736; GFX9-LABEL: urem32:
737; GFX9:       ; %bb.0:
738; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
739; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, v1
740; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v1
741; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v2
742; GFX9-NEXT:    v_mul_f32_e32 v2, 0x4f7ffffe, v2
743; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
744; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v2
745; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v3
746; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
747; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
748; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v1
749; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v2
750; GFX9-NEXT:    v_sub_u32_e32 v2, v0, v1
751; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
752; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
753; GFX9-NEXT:    v_sub_u32_e32 v2, v0, v1
754; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
755; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
756; GFX9-NEXT:    s_setpc_b64 s[30:31]
757  %d = urem i32 %a, %b
758  ret i32 %d
759}
760
761define <2 x i64> @sdivrem64(i64 %a, i64 %b) {
762; GFX9-LABEL: sdivrem64:
763; GFX9:       ; %bb.0:
764; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
765; GFX9-NEXT:    v_mov_b32_e32 v7, v3
766; GFX9-NEXT:    v_or_b32_e32 v4, v1, v7
767; GFX9-NEXT:    v_mov_b32_e32 v3, 0
768; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[3:4]
769; GFX9-NEXT:    ; implicit-def: $vgpr5_vgpr6
770; GFX9-NEXT:    ; implicit-def: $vgpr3_vgpr4
771; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
772; GFX9-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
773; GFX9-NEXT:    s_cbranch_execz BB8_2
774; GFX9-NEXT:  ; %bb.1:
775; GFX9-NEXT:    v_ashrrev_i32_e32 v3, 31, v7
776; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v2, v3
777; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v3, vcc
778; GFX9-NEXT:    v_xor_b32_e32 v6, v4, v3
779; GFX9-NEXT:    v_xor_b32_e32 v5, v5, v3
780; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, v6
781; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, v5
782; GFX9-NEXT:    v_sub_co_u32_e32 v8, vcc, 0, v6
783; GFX9-NEXT:    v_subb_co_u32_e32 v9, vcc, 0, v5, vcc
784; GFX9-NEXT:    v_mov_b32_e32 v16, 0
785; GFX9-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v7
786; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
787; GFX9-NEXT:    v_mov_b32_e32 v15, 0
788; GFX9-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
789; GFX9-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v4
790; GFX9-NEXT:    v_trunc_f32_e32 v7, v7
791; GFX9-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v7
792; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
793; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v7
794; GFX9-NEXT:    v_mul_lo_u32 v10, v9, v4
795; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v4
796; GFX9-NEXT:    v_mul_lo_u32 v12, v8, v7
797; GFX9-NEXT:    v_mul_lo_u32 v13, v8, v4
798; GFX9-NEXT:    v_add3_u32 v10, v11, v12, v10
799; GFX9-NEXT:    v_mul_lo_u32 v12, v4, v10
800; GFX9-NEXT:    v_mul_hi_u32 v14, v4, v13
801; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v10
802; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v14, v12
803; GFX9-NEXT:    v_mul_lo_u32 v14, v7, v13
804; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v11, vcc
805; GFX9-NEXT:    v_mul_hi_u32 v13, v7, v13
806; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v12, v14
807; GFX9-NEXT:    v_mul_hi_u32 v12, v7, v10
808; GFX9-NEXT:    v_mul_lo_u32 v10, v7, v10
809; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v11, v13, vcc
810; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v12, v15, vcc
811; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
812; GFX9-NEXT:    v_add_co_u32_e64 v4, s[4:5], v4, v10
813; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v12, vcc
814; GFX9-NEXT:    v_addc_co_u32_e64 v10, vcc, v7, v11, s[4:5]
815; GFX9-NEXT:    v_mul_lo_u32 v12, v8, v10
816; GFX9-NEXT:    v_mul_hi_u32 v13, v8, v4
817; GFX9-NEXT:    v_mul_lo_u32 v9, v9, v4
818; GFX9-NEXT:    v_mul_lo_u32 v8, v8, v4
819; GFX9-NEXT:    v_add_u32_e32 v7, v7, v11
820; GFX9-NEXT:    v_add3_u32 v9, v13, v12, v9
821; GFX9-NEXT:    v_mul_lo_u32 v12, v4, v9
822; GFX9-NEXT:    v_mul_hi_u32 v13, v4, v8
823; GFX9-NEXT:    v_mul_hi_u32 v14, v4, v9
824; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v13, v12
825; GFX9-NEXT:    v_mul_hi_u32 v13, v10, v8
826; GFX9-NEXT:    v_mul_lo_u32 v8, v10, v8
827; GFX9-NEXT:    v_addc_co_u32_e32 v14, vcc, v16, v14, vcc
828; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v12, v8
829; GFX9-NEXT:    v_mul_hi_u32 v8, v10, v9
830; GFX9-NEXT:    v_mul_lo_u32 v9, v10, v9
831; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v14, v13, vcc
832; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v8, v15, vcc
833; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v12, v9
834; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v16, v8, vcc
835; GFX9-NEXT:    v_addc_co_u32_e64 v7, vcc, v7, v8, s[4:5]
836; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v9
837; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
838; GFX9-NEXT:    v_ashrrev_i32_e32 v8, 31, v1
839; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v0, v8
840; GFX9-NEXT:    v_xor_b32_e32 v9, v9, v8
841; GFX9-NEXT:    v_mul_lo_u32 v10, v9, v7
842; GFX9-NEXT:    v_mul_hi_u32 v11, v9, v4
843; GFX9-NEXT:    v_mul_hi_u32 v12, v9, v7
844; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v8, vcc
845; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v8
846; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
847; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v12, vcc
848; GFX9-NEXT:    v_mul_lo_u32 v12, v1, v4
849; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
850; GFX9-NEXT:    v_mul_hi_u32 v13, v1, v7
851; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v7
852; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v10, v12
853; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v11, v4, vcc
854; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v15, vcc
855; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v7
856; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v16, v10, vcc
857; GFX9-NEXT:    v_mul_lo_u32 v10, v5, v4
858; GFX9-NEXT:    v_mul_lo_u32 v11, v6, v7
859; GFX9-NEXT:    v_mul_hi_u32 v12, v6, v4
860; GFX9-NEXT:    v_mul_lo_u32 v13, v6, v4
861; GFX9-NEXT:    v_add3_u32 v10, v12, v11, v10
862; GFX9-NEXT:    v_sub_u32_e32 v11, v1, v10
863; GFX9-NEXT:    v_sub_co_u32_e32 v9, vcc, v9, v13
864; GFX9-NEXT:    v_subb_co_u32_e64 v11, s[4:5], v11, v5, vcc
865; GFX9-NEXT:    v_sub_co_u32_e64 v12, s[4:5], v9, v6
866; GFX9-NEXT:    v_subbrev_co_u32_e64 v13, s[6:7], 0, v11, s[4:5]
867; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v13, v5
868; GFX9-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[6:7]
869; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v12, v6
870; GFX9-NEXT:    v_cndmask_b32_e64 v15, 0, -1, s[6:7]
871; GFX9-NEXT:    v_cmp_eq_u32_e64 s[6:7], v13, v5
872; GFX9-NEXT:    v_cndmask_b32_e64 v14, v14, v15, s[6:7]
873; GFX9-NEXT:    v_add_co_u32_e64 v15, s[6:7], 2, v4
874; GFX9-NEXT:    v_addc_co_u32_e64 v16, s[6:7], 0, v7, s[6:7]
875; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v10, vcc
876; GFX9-NEXT:    v_add_co_u32_e64 v17, s[6:7], 1, v4
877; GFX9-NEXT:    v_addc_co_u32_e64 v18, s[6:7], 0, v7, s[6:7]
878; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v5
879; GFX9-NEXT:    v_cmp_ne_u32_e64 s[6:7], 0, v14
880; GFX9-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
881; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v9, v6
882; GFX9-NEXT:    v_cndmask_b32_e64 v14, v18, v16, s[6:7]
883; GFX9-NEXT:    v_cndmask_b32_e64 v16, 0, -1, vcc
884; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v5
885; GFX9-NEXT:    v_subb_co_u32_e64 v5, s[4:5], v11, v5, s[4:5]
886; GFX9-NEXT:    v_sub_co_u32_e64 v6, s[4:5], v12, v6
887; GFX9-NEXT:    v_cndmask_b32_e32 v10, v10, v16, vcc
888; GFX9-NEXT:    v_subbrev_co_u32_e64 v5, s[4:5], 0, v5, s[4:5]
889; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
890; GFX9-NEXT:    v_cndmask_b32_e64 v5, v13, v5, s[6:7]
891; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
892; GFX9-NEXT:    v_cndmask_b32_e64 v5, v12, v6, s[6:7]
893; GFX9-NEXT:    v_cndmask_b32_e64 v10, v17, v15, s[6:7]
894; GFX9-NEXT:    v_cndmask_b32_e32 v5, v9, v5, vcc
895; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v10, vcc
896; GFX9-NEXT:    v_xor_b32_e32 v10, v8, v3
897; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v14, vcc
898; GFX9-NEXT:    v_xor_b32_e32 v3, v4, v10
899; GFX9-NEXT:    v_xor_b32_e32 v5, v5, v8
900; GFX9-NEXT:    v_xor_b32_e32 v7, v7, v10
901; GFX9-NEXT:    v_sub_co_u32_e64 v3, s[8:9], v3, v10
902; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v8
903; GFX9-NEXT:    v_sub_co_u32_e32 v5, vcc, v5, v8
904; GFX9-NEXT:    v_subb_co_u32_e64 v4, s[8:9], v7, v10, s[8:9]
905; GFX9-NEXT:    v_subb_co_u32_e32 v6, vcc, v1, v8, vcc
906; GFX9-NEXT:  BB8_2: ; %Flow
907; GFX9-NEXT:    s_or_saveexec_b64 s[4:5], s[10:11]
908; GFX9-NEXT:    s_xor_b64 exec, exec, s[4:5]
909; GFX9-NEXT:    s_cbranch_execz BB8_4
910; GFX9-NEXT:  ; %bb.3:
911; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
912; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v2
913; GFX9-NEXT:    v_mov_b32_e32 v4, 0
914; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
915; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
916; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
917; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v1
918; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
919; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
920; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
921; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v2
922; GFX9-NEXT:    v_add_u32_e32 v5, 1, v1
923; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v3
924; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
925; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v2
926; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
927; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
928; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v2
929; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
930; GFX9-NEXT:    v_add_u32_e32 v6, 1, v1
931; GFX9-NEXT:    v_cndmask_b32_e32 v5, v0, v3, vcc
932; GFX9-NEXT:    v_cndmask_b32_e32 v3, v1, v6, vcc
933; GFX9-NEXT:    v_mov_b32_e32 v6, v4
934; GFX9-NEXT:  BB8_4:
935; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
936; GFX9-NEXT:    v_mov_b32_e32 v0, v3
937; GFX9-NEXT:    v_mov_b32_e32 v1, v4
938; GFX9-NEXT:    v_mov_b32_e32 v2, v5
939; GFX9-NEXT:    v_mov_b32_e32 v3, v6
940; GFX9-NEXT:    s_setpc_b64 s[30:31]
941  %d = sdiv i64 %a, %b
942  %r = srem i64 %a, %b
943  %ins.0 = insertelement <2 x i64> undef, i64 %d, i32 0
944  %ins.1 = insertelement <2 x i64> %ins.0, i64 %r, i32 1
945  ret <2 x i64> %ins.1
946}
947
948define <2 x i64> @udivrem64(i64 %a, i64 %b) {
949; GFX9-LABEL: udivrem64:
950; GFX9:       ; %bb.0:
951; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
952; GFX9-NEXT:    v_or_b32_e32 v5, v1, v3
953; GFX9-NEXT:    v_mov_b32_e32 v4, 0
954; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[4:5]
955; GFX9-NEXT:    ; implicit-def: $vgpr6_vgpr7
956; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5
957; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
958; GFX9-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
959; GFX9-NEXT:    s_cbranch_execz BB9_2
960; GFX9-NEXT:  ; %bb.1:
961; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, v2
962; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v3
963; GFX9-NEXT:    v_sub_co_u32_e32 v6, vcc, 0, v2
964; GFX9-NEXT:    v_subb_co_u32_e32 v7, vcc, 0, v3, vcc
965; GFX9-NEXT:    v_mov_b32_e32 v13, 0
966; GFX9-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
967; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
968; GFX9-NEXT:    v_mov_b32_e32 v12, 0
969; GFX9-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
970; GFX9-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
971; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
972; GFX9-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
973; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
974; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
975; GFX9-NEXT:    v_mul_lo_u32 v9, v7, v4
976; GFX9-NEXT:    v_mul_lo_u32 v8, v6, v5
977; GFX9-NEXT:    v_mul_hi_u32 v10, v6, v4
978; GFX9-NEXT:    v_mul_lo_u32 v11, v6, v4
979; GFX9-NEXT:    v_add3_u32 v8, v10, v8, v9
980; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v11
981; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v8
982; GFX9-NEXT:    v_mul_hi_u32 v14, v4, v8
983; GFX9-NEXT:    v_mul_hi_u32 v15, v5, v8
984; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
985; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v10
986; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v14, vcc
987; GFX9-NEXT:    v_mul_lo_u32 v14, v5, v11
988; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v11
989; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v14
990; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
991; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v12, vcc
992; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
993; GFX9-NEXT:    v_add_co_u32_e64 v4, s[4:5], v4, v8
994; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v13, v10, vcc
995; GFX9-NEXT:    v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5]
996; GFX9-NEXT:    v_mul_lo_u32 v10, v6, v8
997; GFX9-NEXT:    v_mul_hi_u32 v11, v6, v4
998; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v4
999; GFX9-NEXT:    v_mul_lo_u32 v6, v6, v4
1000; GFX9-NEXT:    v_add_u32_e32 v5, v5, v9
1001; GFX9-NEXT:    v_add3_u32 v7, v11, v10, v7
1002; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v7
1003; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v6
1004; GFX9-NEXT:    v_mul_hi_u32 v15, v4, v7
1005; GFX9-NEXT:    v_mul_hi_u32 v14, v8, v7
1006; GFX9-NEXT:    v_mul_lo_u32 v7, v8, v7
1007; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
1008; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v6
1009; GFX9-NEXT:    v_mul_lo_u32 v6, v8, v6
1010; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
1011; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v10, v6
1012; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v11, vcc
1013; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v14, v12, vcc
1014; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v7
1015; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
1016; GFX9-NEXT:    v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5]
1017; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
1018; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
1019; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v5
1020; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v4
1021; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v5
1022; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v5
1023; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
1024; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
1025; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
1026; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
1027; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
1028; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v8
1029; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
1030; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v9, v12, vcc
1031; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v5
1032; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v13, v6, vcc
1033; GFX9-NEXT:    v_mul_lo_u32 v6, v3, v4
1034; GFX9-NEXT:    v_mul_lo_u32 v7, v2, v5
1035; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v4
1036; GFX9-NEXT:    v_mul_lo_u32 v9, v2, v4
1037; GFX9-NEXT:    v_add3_u32 v6, v8, v7, v6
1038; GFX9-NEXT:    v_sub_u32_e32 v7, v1, v6
1039; GFX9-NEXT:    v_sub_co_u32_e32 v8, vcc, v0, v9
1040; GFX9-NEXT:    v_subb_co_u32_e64 v7, s[4:5], v7, v3, vcc
1041; GFX9-NEXT:    v_sub_co_u32_e64 v9, s[4:5], v8, v2
1042; GFX9-NEXT:    v_subbrev_co_u32_e64 v10, s[6:7], 0, v7, s[4:5]
1043; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v10, v3
1044; GFX9-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[6:7]
1045; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v9, v2
1046; GFX9-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[6:7]
1047; GFX9-NEXT:    v_cmp_eq_u32_e64 s[6:7], v10, v3
1048; GFX9-NEXT:    v_cndmask_b32_e64 v11, v11, v12, s[6:7]
1049; GFX9-NEXT:    v_add_co_u32_e64 v12, s[6:7], 2, v4
1050; GFX9-NEXT:    v_addc_co_u32_e64 v13, s[6:7], 0, v5, s[6:7]
1051; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v6, vcc
1052; GFX9-NEXT:    v_add_co_u32_e64 v14, s[6:7], 1, v4
1053; GFX9-NEXT:    v_addc_co_u32_e64 v15, s[6:7], 0, v5, s[6:7]
1054; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
1055; GFX9-NEXT:    v_cmp_ne_u32_e64 s[6:7], 0, v11
1056; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1057; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v8, v2
1058; GFX9-NEXT:    v_cndmask_b32_e64 v11, v15, v13, s[6:7]
1059; GFX9-NEXT:    v_cndmask_b32_e64 v13, 0, -1, vcc
1060; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
1061; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v13, vcc
1062; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
1063; GFX9-NEXT:    v_cndmask_b32_e64 v6, v14, v12, s[6:7]
1064; GFX9-NEXT:    v_subb_co_u32_e64 v3, s[4:5], v7, v3, s[4:5]
1065; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
1066; GFX9-NEXT:    v_sub_co_u32_e64 v6, s[4:5], v9, v2
1067; GFX9-NEXT:    v_subbrev_co_u32_e64 v3, s[4:5], 0, v3, s[4:5]
1068; GFX9-NEXT:    v_cndmask_b32_e64 v3, v10, v3, s[6:7]
1069; GFX9-NEXT:    v_cndmask_b32_e32 v7, v1, v3, vcc
1070; GFX9-NEXT:    v_cndmask_b32_e64 v1, v9, v6, s[6:7]
1071; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v11, vcc
1072; GFX9-NEXT:    v_cndmask_b32_e32 v6, v8, v1, vcc
1073; GFX9-NEXT:  BB9_2: ; %Flow
1074; GFX9-NEXT:    s_or_saveexec_b64 s[4:5], s[8:9]
1075; GFX9-NEXT:    s_xor_b64 exec, exec, s[4:5]
1076; GFX9-NEXT:    s_cbranch_execz BB9_4
1077; GFX9-NEXT:  ; %bb.3:
1078; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
1079; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v2
1080; GFX9-NEXT:    v_mov_b32_e32 v5, 0
1081; GFX9-NEXT:    v_mov_b32_e32 v7, v5
1082; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1083; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
1084; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
1085; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v1
1086; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
1087; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
1088; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
1089; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v2
1090; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
1091; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v3
1092; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
1093; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v2
1094; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1095; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
1096; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v2
1097; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
1098; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
1099; GFX9-NEXT:    v_cndmask_b32_e32 v6, v0, v3, vcc
1100; GFX9-NEXT:    v_cndmask_b32_e32 v4, v1, v4, vcc
1101; GFX9-NEXT:  BB9_4:
1102; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
1103; GFX9-NEXT:    v_mov_b32_e32 v0, v4
1104; GFX9-NEXT:    v_mov_b32_e32 v1, v5
1105; GFX9-NEXT:    v_mov_b32_e32 v2, v6
1106; GFX9-NEXT:    v_mov_b32_e32 v3, v7
1107; GFX9-NEXT:    s_setpc_b64 s[30:31]
1108  %d = udiv i64 %a, %b
1109  %r = urem i64 %a, %b
1110  %ins.0 = insertelement <2 x i64> undef, i64 %d, i32 0
1111  %ins.1 = insertelement <2 x i64> %ins.0, i64 %r, i32 1
1112  ret <2 x i64> %ins.1
1113}
1114
1115define i64 @sdiv64_known32(i64 %a, i64 %b) {
1116; GFX9-LABEL: sdiv64_known32:
1117; GFX9:       ; %bb.0:
1118; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1119; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, v3
1120; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v1
1121; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
1122; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
1123; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
1124; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v2
1125; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
1126; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1127; GFX9-NEXT:    v_mov_b32_e32 v1, 0
1128; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
1129; GFX9-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
1130; GFX9-NEXT:    s_setpc_b64 s[30:31]
1131  %a.ext = ashr i64 %a, 32
1132  %b.ext = ashr i64 %b, 32
1133  %d = udiv i64 %a.ext, %b.ext
1134  ret i64 %d
1135}
1136
1137define i64 @udiv64_known32(i64 %a, i64 %b) {
1138; GFX9-LABEL: udiv64_known32:
1139; GFX9:       ; %bb.0:
1140; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1141; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
1142; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, v0
1143; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1144; GFX9-NEXT:    v_mul_f32_e32 v2, v0, v2
1145; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
1146; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v2
1147; GFX9-NEXT:    v_mad_f32 v0, -v2, v1, v0
1148; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, v1
1149; GFX9-NEXT:    v_mov_b32_e32 v1, 0
1150; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
1151; GFX9-NEXT:    s_setpc_b64 s[30:31]
1152  %a.mask = and i64 %a, 4294967295
1153  %b.mask = and i64 %b, 4294967295
1154  %d = udiv i64 %a.mask, %b.mask
1155  ret i64 %d
1156}
1157