1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
3
4; 64-bit divides and rems should be split into a fast and slow path
5; where the fast path uses a 32-bit operation.
6
7define i64 @sdiv64(i64 %a, i64 %b) {
8; GFX9-LABEL: sdiv64:
9; GFX9:       ; %bb.0:
10; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
11; GFX9-NEXT:    v_or_b32_e32 v5, v1, v3
12; GFX9-NEXT:    v_mov_b32_e32 v4, 0
13; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[4:5]
14; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5
15; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
16; GFX9-NEXT:    s_xor_b64 s[6:7], exec, s[4:5]
17; GFX9-NEXT:    s_cbranch_execz .LBB0_2
18; GFX9-NEXT:  ; %bb.1:
19; GFX9-NEXT:    v_ashrrev_i32_e32 v9, 31, v3
20; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v9
21; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v9, vcc
22; GFX9-NEXT:    v_xor_b32_e32 v10, v3, v9
23; GFX9-NEXT:    v_xor_b32_e32 v11, v2, v9
24; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, v11
25; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, v10
26; GFX9-NEXT:    v_sub_co_u32_e32 v7, vcc, 0, v11
27; GFX9-NEXT:    v_subb_co_u32_e32 v8, vcc, 0, v10, vcc
28; GFX9-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
29; GFX9-NEXT:    v_rcp_f32_e32 v2, v2
30; GFX9-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
31; GFX9-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
32; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
33; GFX9-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
34; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v2
35; GFX9-NEXT:    v_cvt_u32_f32_e32 v12, v3
36; GFX9-NEXT:    v_mul_lo_u32 v4, v8, v6
37; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v7, v6, 0
38; GFX9-NEXT:    v_mul_lo_u32 v5, v7, v12
39; GFX9-NEXT:    v_mul_hi_u32 v13, v6, v2
40; GFX9-NEXT:    v_add3_u32 v5, v3, v5, v4
41; GFX9-NEXT:    v_mad_u64_u32 v[3:4], s[4:5], v6, v5, 0
42; GFX9-NEXT:    v_add_co_u32_e32 v13, vcc, v13, v3
43; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v12, v2, 0
44; GFX9-NEXT:    v_addc_co_u32_e32 v14, vcc, 0, v4, vcc
45; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v12, v5, 0
46; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v13, v2
47; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v14, v3, vcc
48; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
49; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
50; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
51; GFX9-NEXT:    v_add_co_u32_e32 v13, vcc, v6, v2
52; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v12, v3, vcc
53; GFX9-NEXT:    v_mul_lo_u32 v4, v7, v12
54; GFX9-NEXT:    v_mul_lo_u32 v5, v8, v13
55; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v7, v13, 0
56; GFX9-NEXT:    v_add3_u32 v5, v3, v4, v5
57; GFX9-NEXT:    v_mad_u64_u32 v[3:4], s[4:5], v12, v5, 0
58; GFX9-NEXT:    v_mad_u64_u32 v[5:6], s[4:5], v13, v5, 0
59; GFX9-NEXT:    v_mul_hi_u32 v14, v13, v2
60; GFX9-NEXT:    v_mad_u64_u32 v[7:8], s[4:5], v12, v2, 0
61; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v14, v5
62; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
63; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v7
64; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v5, v8, vcc
65; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
66; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
67; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
68; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v13, v2
69; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v12, v3, vcc
70; GFX9-NEXT:    v_ashrrev_i32_e32 v4, 31, v1
71; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v4
72; GFX9-NEXT:    v_xor_b32_e32 v6, v0, v4
73; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v1, v4, vcc
74; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v6, v3, 0
75; GFX9-NEXT:    v_mul_hi_u32 v7, v6, v2
76; GFX9-NEXT:    v_xor_b32_e32 v5, v5, v4
77; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v0
78; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v1, vcc
79; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v5, v2, 0
80; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v5, v3, 0
81; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v7, v0
82; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v8, v1, vcc
83; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
84; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v0, v2
85; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
86; GFX9-NEXT:    v_mul_lo_u32 v7, v10, v2
87; GFX9-NEXT:    v_mul_lo_u32 v8, v11, v3
88; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v11, v2, 0
89; GFX9-NEXT:    v_add3_u32 v1, v1, v8, v7
90; GFX9-NEXT:    v_sub_u32_e32 v7, v5, v1
91; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, v6, v0
92; GFX9-NEXT:    v_subb_co_u32_e64 v6, s[4:5], v7, v10, vcc
93; GFX9-NEXT:    v_sub_co_u32_e64 v7, s[4:5], v0, v11
94; GFX9-NEXT:    v_subbrev_co_u32_e64 v6, s[4:5], 0, v6, s[4:5]
95; GFX9-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v10
96; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
97; GFX9-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v11
98; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
99; GFX9-NEXT:    v_cmp_eq_u32_e64 s[4:5], v6, v10
100; GFX9-NEXT:    v_cndmask_b32_e64 v6, v8, v7, s[4:5]
101; GFX9-NEXT:    v_add_co_u32_e64 v7, s[4:5], 2, v2
102; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v5, v1, vcc
103; GFX9-NEXT:    v_addc_co_u32_e64 v8, s[4:5], 0, v3, s[4:5]
104; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v10
105; GFX9-NEXT:    v_add_co_u32_e64 v12, s[4:5], 1, v2
106; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
107; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v11
108; GFX9-NEXT:    v_addc_co_u32_e64 v13, s[4:5], 0, v3, s[4:5]
109; GFX9-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
110; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v10
111; GFX9-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v6
112; GFX9-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
113; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
114; GFX9-NEXT:    v_cndmask_b32_e64 v1, v12, v7, s[4:5]
115; GFX9-NEXT:    v_cndmask_b32_e64 v6, v13, v8, s[4:5]
116; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
117; GFX9-NEXT:    v_xor_b32_e32 v2, v4, v9
118; GFX9-NEXT:    v_cndmask_b32_e32 v0, v3, v6, vcc
119; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v2
120; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v2
121; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, v1, v2
122; GFX9-NEXT:    v_subb_co_u32_e32 v5, vcc, v0, v2, vcc
123; GFX9-NEXT:    ; implicit-def: $vgpr2_vgpr3
124; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1
125; GFX9-NEXT:  .LBB0_2: ; %Flow
126; GFX9-NEXT:    s_or_saveexec_b64 s[4:5], s[6:7]
127; GFX9-NEXT:    s_xor_b64 exec, exec, s[4:5]
128; GFX9-NEXT:    s_cbranch_execz .LBB0_4
129; GFX9-NEXT:  ; %bb.3:
130; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
131; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v2
132; GFX9-NEXT:    v_mov_b32_e32 v5, 0
133; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
134; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
135; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
136; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v1
137; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
138; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
139; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
140; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v2
141; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
142; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v3
143; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v2
144; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
145; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
146; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
147; GFX9-NEXT:    v_add_u32_e32 v3, 1, v1
148; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
149; GFX9-NEXT:    v_cndmask_b32_e32 v4, v1, v3, vcc
150; GFX9-NEXT:  .LBB0_4:
151; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
152; GFX9-NEXT:    v_mov_b32_e32 v0, v4
153; GFX9-NEXT:    v_mov_b32_e32 v1, v5
154; GFX9-NEXT:    s_setpc_b64 s[30:31]
155  %d = sdiv i64 %a, %b
156  ret i64 %d
157}
158
159define i64 @udiv64(i64 %a, i64 %b) {
160; GFX9-LABEL: udiv64:
161; GFX9:       ; %bb.0:
162; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
163; GFX9-NEXT:    v_or_b32_e32 v5, v1, v3
164; GFX9-NEXT:    v_mov_b32_e32 v4, 0
165; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[4:5]
166; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5
167; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
168; GFX9-NEXT:    s_xor_b64 s[6:7], exec, s[4:5]
169; GFX9-NEXT:    s_cbranch_execz .LBB1_2
170; GFX9-NEXT:  ; %bb.1:
171; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, v2
172; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v3
173; GFX9-NEXT:    v_sub_co_u32_e32 v10, vcc, 0, v2
174; GFX9-NEXT:    v_subb_co_u32_e32 v11, vcc, 0, v3, vcc
175; GFX9-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
176; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
177; GFX9-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
178; GFX9-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
179; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
180; GFX9-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
181; GFX9-NEXT:    v_cvt_u32_f32_e32 v8, v5
182; GFX9-NEXT:    v_cvt_u32_f32_e32 v9, v4
183; GFX9-NEXT:    v_mul_lo_u32 v6, v10, v8
184; GFX9-NEXT:    v_mul_lo_u32 v7, v11, v9
185; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v10, v9, 0
186; GFX9-NEXT:    v_add3_u32 v7, v5, v6, v7
187; GFX9-NEXT:    v_mul_hi_u32 v12, v9, v4
188; GFX9-NEXT:    v_mad_u64_u32 v[5:6], s[4:5], v9, v7, 0
189; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v12, v5
190; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v8, v4, 0
191; GFX9-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v6, vcc
192; GFX9-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], v8, v7, 0
193; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v12, v4
194; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v13, v5, vcc
195; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
196; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
197; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
198; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v9, v4
199; GFX9-NEXT:    v_addc_co_u32_e32 v13, vcc, v8, v5, vcc
200; GFX9-NEXT:    v_mul_lo_u32 v6, v10, v13
201; GFX9-NEXT:    v_mul_lo_u32 v7, v11, v12
202; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v10, v12, 0
203; GFX9-NEXT:    v_add3_u32 v7, v5, v6, v7
204; GFX9-NEXT:    v_mad_u64_u32 v[5:6], s[4:5], v13, v7, 0
205; GFX9-NEXT:    v_mad_u64_u32 v[7:8], s[4:5], v12, v7, 0
206; GFX9-NEXT:    v_mul_hi_u32 v11, v12, v4
207; GFX9-NEXT:    v_mad_u64_u32 v[9:10], s[4:5], v13, v4, 0
208; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v11, v7
209; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
210; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v9
211; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v10, vcc
212; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
213; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v5
214; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
215; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v12, v4
216; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v5, vcc
217; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v0, v7, 0
218; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v6
219; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v8, v4
220; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v5, vcc
221; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v1, v6, 0
222; GFX9-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], v1, v7, 0
223; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v8, v4
224; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
225; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
226; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v4, v6
227; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v5, vcc
228; GFX9-NEXT:    v_mul_lo_u32 v8, v3, v6
229; GFX9-NEXT:    v_mul_lo_u32 v9, v2, v7
230; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v2, v6, 0
231; GFX9-NEXT:    v_add3_u32 v5, v5, v9, v8
232; GFX9-NEXT:    v_sub_u32_e32 v8, v1, v5
233; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, v0, v4
234; GFX9-NEXT:    v_subb_co_u32_e64 v4, s[4:5], v8, v3, vcc
235; GFX9-NEXT:    v_sub_co_u32_e64 v8, s[4:5], v0, v2
236; GFX9-NEXT:    v_subbrev_co_u32_e64 v4, s[4:5], 0, v4, s[4:5]
237; GFX9-NEXT:    v_cmp_ge_u32_e64 s[4:5], v4, v3
238; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
239; GFX9-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v2
240; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
241; GFX9-NEXT:    v_cmp_eq_u32_e64 s[4:5], v4, v3
242; GFX9-NEXT:    v_cndmask_b32_e64 v4, v9, v8, s[4:5]
243; GFX9-NEXT:    v_add_co_u32_e64 v8, s[4:5], 2, v6
244; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v5, vcc
245; GFX9-NEXT:    v_addc_co_u32_e64 v9, s[4:5], 0, v7, s[4:5]
246; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
247; GFX9-NEXT:    v_add_co_u32_e64 v10, s[4:5], 1, v6
248; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
249; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
250; GFX9-NEXT:    v_addc_co_u32_e64 v11, s[4:5], 0, v7, s[4:5]
251; GFX9-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
252; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
253; GFX9-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v4
254; GFX9-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
255; GFX9-NEXT:    v_cndmask_b32_e64 v4, v11, v9, s[4:5]
256; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
257; GFX9-NEXT:    v_cndmask_b32_e64 v0, v10, v8, s[4:5]
258; GFX9-NEXT:    v_cndmask_b32_e32 v5, v7, v4, vcc
259; GFX9-NEXT:    v_cndmask_b32_e32 v4, v6, v0, vcc
260; GFX9-NEXT:    ; implicit-def: $vgpr2_vgpr3
261; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1
262; GFX9-NEXT:  .LBB1_2: ; %Flow
263; GFX9-NEXT:    s_or_saveexec_b64 s[4:5], s[6:7]
264; GFX9-NEXT:    s_xor_b64 exec, exec, s[4:5]
265; GFX9-NEXT:    s_cbranch_execz .LBB1_4
266; GFX9-NEXT:  ; %bb.3:
267; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
268; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v2
269; GFX9-NEXT:    v_mov_b32_e32 v5, 0
270; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
271; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
272; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
273; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v1
274; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
275; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
276; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
277; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v2
278; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
279; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v3
280; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v2
281; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
282; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
283; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
284; GFX9-NEXT:    v_add_u32_e32 v3, 1, v1
285; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
286; GFX9-NEXT:    v_cndmask_b32_e32 v4, v1, v3, vcc
287; GFX9-NEXT:  .LBB1_4:
288; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
289; GFX9-NEXT:    v_mov_b32_e32 v0, v4
290; GFX9-NEXT:    v_mov_b32_e32 v1, v5
291; GFX9-NEXT:    s_setpc_b64 s[30:31]
292  %d = udiv i64 %a, %b
293  ret i64 %d
294}
295
296define i64 @srem64(i64 %a, i64 %b) {
297; GFX9-LABEL: srem64:
298; GFX9:       ; %bb.0:
299; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
300; GFX9-NEXT:    v_or_b32_e32 v5, v1, v3
301; GFX9-NEXT:    v_mov_b32_e32 v4, 0
302; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[4:5]
303; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5
304; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
305; GFX9-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
306; GFX9-NEXT:    s_cbranch_execz .LBB2_2
307; GFX9-NEXT:  ; %bb.1:
308; GFX9-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
309; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
310; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
311; GFX9-NEXT:    v_xor_b32_e32 v9, v3, v4
312; GFX9-NEXT:    v_xor_b32_e32 v10, v2, v4
313; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, v10
314; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, v9
315; GFX9-NEXT:    v_sub_co_u32_e32 v7, vcc, 0, v10
316; GFX9-NEXT:    v_subb_co_u32_e32 v8, vcc, 0, v9, vcc
317; GFX9-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
318; GFX9-NEXT:    v_rcp_f32_e32 v2, v2
319; GFX9-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
320; GFX9-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
321; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
322; GFX9-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
323; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v2
324; GFX9-NEXT:    v_cvt_u32_f32_e32 v11, v3
325; GFX9-NEXT:    v_mul_lo_u32 v4, v8, v6
326; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v7, v6, 0
327; GFX9-NEXT:    v_mul_lo_u32 v5, v7, v11
328; GFX9-NEXT:    v_mul_hi_u32 v12, v6, v2
329; GFX9-NEXT:    v_add3_u32 v5, v3, v5, v4
330; GFX9-NEXT:    v_mad_u64_u32 v[3:4], s[4:5], v6, v5, 0
331; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v12, v3
332; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v11, v2, 0
333; GFX9-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v4, vcc
334; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v11, v5, 0
335; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v12, v2
336; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v13, v3, vcc
337; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
338; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
339; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
340; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v6, v2
341; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v11, v3, vcc
342; GFX9-NEXT:    v_mul_lo_u32 v4, v7, v11
343; GFX9-NEXT:    v_mul_lo_u32 v5, v8, v12
344; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v7, v12, 0
345; GFX9-NEXT:    v_add3_u32 v5, v3, v4, v5
346; GFX9-NEXT:    v_mad_u64_u32 v[3:4], s[4:5], v11, v5, 0
347; GFX9-NEXT:    v_mad_u64_u32 v[5:6], s[4:5], v12, v5, 0
348; GFX9-NEXT:    v_mul_hi_u32 v13, v12, v2
349; GFX9-NEXT:    v_mad_u64_u32 v[7:8], s[4:5], v11, v2, 0
350; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v13, v5
351; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
352; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v7
353; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v5, v8, vcc
354; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
355; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
356; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
357; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v12, v2
358; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v11, v3, vcc
359; GFX9-NEXT:    v_ashrrev_i32_e32 v5, 31, v1
360; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v5
361; GFX9-NEXT:    v_xor_b32_e32 v6, v0, v5
362; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v1, v5, vcc
363; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v6, v3, 0
364; GFX9-NEXT:    v_mul_hi_u32 v7, v6, v2
365; GFX9-NEXT:    v_xor_b32_e32 v4, v4, v5
366; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v0
367; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v1, vcc
368; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v4, v2, 0
369; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v4, v3, 0
370; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v7, v0
371; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v8, v1, vcc
372; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
373; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
374; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
375; GFX9-NEXT:    v_mul_lo_u32 v2, v9, v0
376; GFX9-NEXT:    v_mul_lo_u32 v3, v10, v1
377; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v10, v0, 0
378; GFX9-NEXT:    v_add3_u32 v1, v1, v3, v2
379; GFX9-NEXT:    v_sub_u32_e32 v2, v4, v1
380; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, v6, v0
381; GFX9-NEXT:    v_subb_co_u32_e64 v2, s[4:5], v2, v9, vcc
382; GFX9-NEXT:    v_sub_co_u32_e64 v3, s[4:5], v0, v10
383; GFX9-NEXT:    v_subbrev_co_u32_e64 v6, s[6:7], 0, v2, s[4:5]
384; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v9
385; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
386; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v3, v10
387; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
388; GFX9-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v9
389; GFX9-NEXT:    v_subb_co_u32_e64 v2, s[4:5], v2, v9, s[4:5]
390; GFX9-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
391; GFX9-NEXT:    v_sub_co_u32_e64 v8, s[4:5], v3, v10
392; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v4, v1, vcc
393; GFX9-NEXT:    v_subbrev_co_u32_e64 v2, s[4:5], 0, v2, s[4:5]
394; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v9
395; GFX9-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
396; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
397; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v10
398; GFX9-NEXT:    v_cndmask_b32_e64 v2, v6, v2, s[4:5]
399; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
400; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v9
401; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
402; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
403; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
404; GFX9-NEXT:    v_cndmask_b32_e64 v2, v3, v8, s[4:5]
405; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
406; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v5
407; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v5
408; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, v0, v5
409; GFX9-NEXT:    v_subb_co_u32_e32 v5, vcc, v1, v5, vcc
410; GFX9-NEXT:    ; implicit-def: $vgpr2_vgpr3
411; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1
412; GFX9-NEXT:  .LBB2_2: ; %Flow
413; GFX9-NEXT:    s_or_saveexec_b64 s[4:5], s[8:9]
414; GFX9-NEXT:    s_xor_b64 exec, exec, s[4:5]
415; GFX9-NEXT:    s_cbranch_execz .LBB2_4
416; GFX9-NEXT:  ; %bb.3:
417; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
418; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v2
419; GFX9-NEXT:    v_mov_b32_e32 v5, 0
420; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
421; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
422; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
423; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v1
424; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
425; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
426; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
427; GFX9-NEXT:    v_mul_lo_u32 v1, v1, v2
428; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v1
429; GFX9-NEXT:    v_sub_u32_e32 v1, v0, v2
430; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
431; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
432; GFX9-NEXT:    v_sub_u32_e32 v1, v0, v2
433; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
434; GFX9-NEXT:    v_cndmask_b32_e32 v4, v0, v1, vcc
435; GFX9-NEXT:  .LBB2_4:
436; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
437; GFX9-NEXT:    v_mov_b32_e32 v0, v4
438; GFX9-NEXT:    v_mov_b32_e32 v1, v5
439; GFX9-NEXT:    s_setpc_b64 s[30:31]
440  %d = srem i64 %a, %b
441  ret i64 %d
442}
443
444define i64 @urem64(i64 %a, i64 %b) {
445; GFX9-LABEL: urem64:
446; GFX9:       ; %bb.0:
447; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
448; GFX9-NEXT:    v_or_b32_e32 v5, v1, v3
449; GFX9-NEXT:    v_mov_b32_e32 v4, 0
450; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[4:5]
451; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5
452; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
453; GFX9-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
454; GFX9-NEXT:    s_cbranch_execz .LBB3_2
455; GFX9-NEXT:  ; %bb.1:
456; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, v2
457; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v3
458; GFX9-NEXT:    v_sub_co_u32_e32 v10, vcc, 0, v2
459; GFX9-NEXT:    v_subb_co_u32_e32 v11, vcc, 0, v3, vcc
460; GFX9-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
461; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
462; GFX9-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
463; GFX9-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
464; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
465; GFX9-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
466; GFX9-NEXT:    v_cvt_u32_f32_e32 v8, v5
467; GFX9-NEXT:    v_cvt_u32_f32_e32 v9, v4
468; GFX9-NEXT:    v_mul_lo_u32 v6, v10, v8
469; GFX9-NEXT:    v_mul_lo_u32 v7, v11, v9
470; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v10, v9, 0
471; GFX9-NEXT:    v_add3_u32 v7, v5, v6, v7
472; GFX9-NEXT:    v_mul_hi_u32 v12, v9, v4
473; GFX9-NEXT:    v_mad_u64_u32 v[5:6], s[4:5], v9, v7, 0
474; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v12, v5
475; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v8, v4, 0
476; GFX9-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v6, vcc
477; GFX9-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], v8, v7, 0
478; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v12, v4
479; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v13, v5, vcc
480; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
481; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
482; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
483; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v9, v4
484; GFX9-NEXT:    v_addc_co_u32_e32 v13, vcc, v8, v5, vcc
485; GFX9-NEXT:    v_mul_lo_u32 v6, v10, v13
486; GFX9-NEXT:    v_mul_lo_u32 v7, v11, v12
487; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v10, v12, 0
488; GFX9-NEXT:    v_add3_u32 v7, v5, v6, v7
489; GFX9-NEXT:    v_mad_u64_u32 v[5:6], s[4:5], v13, v7, 0
490; GFX9-NEXT:    v_mad_u64_u32 v[7:8], s[4:5], v12, v7, 0
491; GFX9-NEXT:    v_mul_hi_u32 v11, v12, v4
492; GFX9-NEXT:    v_mad_u64_u32 v[9:10], s[4:5], v13, v4, 0
493; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v11, v7
494; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
495; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v9
496; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v10, vcc
497; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
498; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v5
499; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
500; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v12, v4
501; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v5, vcc
502; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v0, v7, 0
503; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v6
504; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v8, v4
505; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v5, vcc
506; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v1, v6, 0
507; GFX9-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], v1, v7, 0
508; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v8, v4
509; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
510; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
511; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
512; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
513; GFX9-NEXT:    v_mul_lo_u32 v6, v3, v4
514; GFX9-NEXT:    v_mul_lo_u32 v7, v2, v5
515; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v2, v4, 0
516; GFX9-NEXT:    v_add3_u32 v5, v5, v7, v6
517; GFX9-NEXT:    v_sub_u32_e32 v6, v1, v5
518; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, v0, v4
519; GFX9-NEXT:    v_subb_co_u32_e64 v4, s[4:5], v6, v3, vcc
520; GFX9-NEXT:    v_sub_co_u32_e64 v6, s[4:5], v0, v2
521; GFX9-NEXT:    v_subbrev_co_u32_e64 v7, s[6:7], 0, v4, s[4:5]
522; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v7, v3
523; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
524; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v2
525; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v5, vcc
526; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[6:7]
527; GFX9-NEXT:    v_cmp_eq_u32_e64 s[6:7], v7, v3
528; GFX9-NEXT:    v_subb_co_u32_e64 v4, s[4:5], v4, v3, s[4:5]
529; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
530; GFX9-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[6:7]
531; GFX9-NEXT:    v_sub_co_u32_e64 v9, s[4:5], v6, v2
532; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
533; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
534; GFX9-NEXT:    v_subbrev_co_u32_e64 v4, s[4:5], 0, v4, s[4:5]
535; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
536; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
537; GFX9-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v8
538; GFX9-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
539; GFX9-NEXT:    v_cndmask_b32_e64 v4, v7, v4, s[4:5]
540; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
541; GFX9-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc
542; GFX9-NEXT:    v_cndmask_b32_e64 v1, v6, v9, s[4:5]
543; GFX9-NEXT:    v_cndmask_b32_e32 v4, v0, v1, vcc
544; GFX9-NEXT:    ; implicit-def: $vgpr2_vgpr3
545; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1
546; GFX9-NEXT:  .LBB3_2: ; %Flow
547; GFX9-NEXT:    s_or_saveexec_b64 s[4:5], s[8:9]
548; GFX9-NEXT:    s_xor_b64 exec, exec, s[4:5]
549; GFX9-NEXT:    s_cbranch_execz .LBB3_4
550; GFX9-NEXT:  ; %bb.3:
551; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
552; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v2
553; GFX9-NEXT:    v_mov_b32_e32 v5, 0
554; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
555; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
556; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
557; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v1
558; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
559; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
560; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
561; GFX9-NEXT:    v_mul_lo_u32 v1, v1, v2
562; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v1
563; GFX9-NEXT:    v_sub_u32_e32 v1, v0, v2
564; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
565; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
566; GFX9-NEXT:    v_sub_u32_e32 v1, v0, v2
567; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
568; GFX9-NEXT:    v_cndmask_b32_e32 v4, v0, v1, vcc
569; GFX9-NEXT:  .LBB3_4:
570; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
571; GFX9-NEXT:    v_mov_b32_e32 v0, v4
572; GFX9-NEXT:    v_mov_b32_e32 v1, v5
573; GFX9-NEXT:    s_setpc_b64 s[30:31]
574  %d = urem i64 %a, %b
575  ret i64 %d
576}
577
578define i32 @sdiv32(i32 %a, i32 %b) {
579; GFX9-LABEL: sdiv32:
580; GFX9:       ; %bb.0:
581; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
582; GFX9-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
583; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
584; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v2
585; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, v1
586; GFX9-NEXT:    v_sub_u32_e32 v4, 0, v1
587; GFX9-NEXT:    v_ashrrev_i32_e32 v5, 31, v0
588; GFX9-NEXT:    v_add_u32_e32 v0, v0, v5
589; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v3
590; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v5
591; GFX9-NEXT:    v_xor_b32_e32 v2, v5, v2
592; GFX9-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
593; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
594; GFX9-NEXT:    v_mul_lo_u32 v4, v4, v3
595; GFX9-NEXT:    v_mul_hi_u32 v4, v3, v4
596; GFX9-NEXT:    v_add_u32_e32 v3, v3, v4
597; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v3
598; GFX9-NEXT:    v_mul_lo_u32 v4, v3, v1
599; GFX9-NEXT:    v_add_u32_e32 v5, 1, v3
600; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v4
601; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
602; GFX9-NEXT:    v_sub_u32_e32 v4, v0, v1
603; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
604; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
605; GFX9-NEXT:    v_add_u32_e32 v4, 1, v3
606; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
607; GFX9-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc
608; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v2
609; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v2
610; GFX9-NEXT:    s_setpc_b64 s[30:31]
611  %d = sdiv i32 %a, %b
612  ret i32 %d
613}
614
615define i32 @udiv32(i32 %a, i32 %b) {
616; GFX9-LABEL: udiv32:
617; GFX9:       ; %bb.0:
618; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
619; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, v1
620; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v1
621; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v2
622; GFX9-NEXT:    v_mul_f32_e32 v2, 0x4f7ffffe, v2
623; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
624; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v2
625; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v3
626; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
627; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
628; GFX9-NEXT:    v_mul_lo_u32 v3, v2, v1
629; GFX9-NEXT:    v_add_u32_e32 v4, 1, v2
630; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v3
631; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
632; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v1
633; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
634; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
635; GFX9-NEXT:    v_add_u32_e32 v3, 1, v2
636; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
637; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc
638; GFX9-NEXT:    s_setpc_b64 s[30:31]
639  %d = udiv i32 %a, %b
640  ret i32 %d
641}
642
643define i32 @srem32(i32 %a, i32 %b) {
644; GFX9-LABEL: srem32:
645; GFX9:       ; %bb.0:
646; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
647; GFX9-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
648; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
649; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v2
650; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, v1
651; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v1
652; GFX9-NEXT:    v_ashrrev_i32_e32 v4, 31, v0
653; GFX9-NEXT:    v_add_u32_e32 v0, v0, v4
654; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v2
655; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
656; GFX9-NEXT:    v_mul_f32_e32 v2, 0x4f7ffffe, v2
657; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
658; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v2
659; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v3
660; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
661; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
662; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v1
663; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v2
664; GFX9-NEXT:    v_sub_u32_e32 v2, v0, v1
665; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
666; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
667; GFX9-NEXT:    v_sub_u32_e32 v2, v0, v1
668; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
669; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
670; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
671; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v4
672; GFX9-NEXT:    s_setpc_b64 s[30:31]
673  %d = srem i32 %a, %b
674  ret i32 %d
675}
676
677define i32 @urem32(i32 %a, i32 %b) {
678; GFX9-LABEL: urem32:
679; GFX9:       ; %bb.0:
680; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
681; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, v1
682; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v1
683; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v2
684; GFX9-NEXT:    v_mul_f32_e32 v2, 0x4f7ffffe, v2
685; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
686; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v2
687; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v3
688; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
689; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
690; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v1
691; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v2
692; GFX9-NEXT:    v_sub_u32_e32 v2, v0, v1
693; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
694; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
695; GFX9-NEXT:    v_sub_u32_e32 v2, v0, v1
696; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
697; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
698; GFX9-NEXT:    s_setpc_b64 s[30:31]
699  %d = urem i32 %a, %b
700  ret i32 %d
701}
702
703define <2 x i64> @sdivrem64(i64 %a, i64 %b) {
704; GFX9-LABEL: sdivrem64:
705; GFX9:       ; %bb.0:
706; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
707; GFX9-NEXT:    v_or_b32_e32 v5, v1, v3
708; GFX9-NEXT:    v_mov_b32_e32 v4, 0
709; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[4:5]
710; GFX9-NEXT:    ; implicit-def: $vgpr6_vgpr7
711; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5
712; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
713; GFX9-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
714; GFX9-NEXT:    s_cbranch_execz .LBB8_2
715; GFX9-NEXT:  ; %bb.1:
716; GFX9-NEXT:    v_ashrrev_i32_e32 v9, 31, v3
717; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v9
718; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v9, vcc
719; GFX9-NEXT:    v_xor_b32_e32 v10, v3, v9
720; GFX9-NEXT:    v_xor_b32_e32 v11, v2, v9
721; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, v11
722; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, v10
723; GFX9-NEXT:    v_sub_co_u32_e32 v7, vcc, 0, v11
724; GFX9-NEXT:    v_subb_co_u32_e32 v8, vcc, 0, v10, vcc
725; GFX9-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
726; GFX9-NEXT:    v_rcp_f32_e32 v2, v2
727; GFX9-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
728; GFX9-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
729; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
730; GFX9-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
731; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v2
732; GFX9-NEXT:    v_cvt_u32_f32_e32 v12, v3
733; GFX9-NEXT:    v_mul_lo_u32 v4, v8, v6
734; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v7, v6, 0
735; GFX9-NEXT:    v_mul_lo_u32 v5, v7, v12
736; GFX9-NEXT:    v_mul_hi_u32 v13, v6, v2
737; GFX9-NEXT:    v_add3_u32 v5, v3, v5, v4
738; GFX9-NEXT:    v_mad_u64_u32 v[3:4], s[4:5], v6, v5, 0
739; GFX9-NEXT:    v_add_co_u32_e32 v13, vcc, v13, v3
740; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v12, v2, 0
741; GFX9-NEXT:    v_addc_co_u32_e32 v14, vcc, 0, v4, vcc
742; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v12, v5, 0
743; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v13, v2
744; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v14, v3, vcc
745; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
746; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
747; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
748; GFX9-NEXT:    v_add_co_u32_e32 v13, vcc, v6, v2
749; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v12, v3, vcc
750; GFX9-NEXT:    v_mul_lo_u32 v4, v7, v12
751; GFX9-NEXT:    v_mul_lo_u32 v5, v8, v13
752; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v7, v13, 0
753; GFX9-NEXT:    v_add3_u32 v5, v3, v4, v5
754; GFX9-NEXT:    v_mad_u64_u32 v[3:4], s[4:5], v12, v5, 0
755; GFX9-NEXT:    v_mad_u64_u32 v[5:6], s[4:5], v13, v5, 0
756; GFX9-NEXT:    v_mul_hi_u32 v14, v13, v2
757; GFX9-NEXT:    v_mad_u64_u32 v[7:8], s[4:5], v12, v2, 0
758; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v14, v5
759; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
760; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v7
761; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v5, v8, vcc
762; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
763; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
764; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
765; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v13, v2
766; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v12, v3, vcc
767; GFX9-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
768; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v7
769; GFX9-NEXT:    v_xor_b32_e32 v5, v0, v7
770; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v1, v7, vcc
771; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v5, v3, 0
772; GFX9-NEXT:    v_mul_hi_u32 v6, v5, v2
773; GFX9-NEXT:    v_xor_b32_e32 v4, v4, v7
774; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v0
775; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v1, vcc
776; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v4, v2, 0
777; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v4, v3, 0
778; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v6, v0
779; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v8, v1, vcc
780; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
781; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v0, v2
782; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
783; GFX9-NEXT:    v_mul_lo_u32 v6, v10, v2
784; GFX9-NEXT:    v_mul_lo_u32 v8, v11, v3
785; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v11, v2, 0
786; GFX9-NEXT:    v_add3_u32 v1, v1, v8, v6
787; GFX9-NEXT:    v_sub_u32_e32 v6, v4, v1
788; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, v5, v0
789; GFX9-NEXT:    v_subb_co_u32_e64 v6, s[4:5], v6, v10, vcc
790; GFX9-NEXT:    v_sub_co_u32_e64 v8, s[4:5], v0, v11
791; GFX9-NEXT:    v_subbrev_co_u32_e64 v12, s[6:7], 0, v6, s[4:5]
792; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v12, v10
793; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[6:7]
794; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v8, v11
795; GFX9-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[6:7]
796; GFX9-NEXT:    v_cmp_eq_u32_e64 s[6:7], v12, v10
797; GFX9-NEXT:    v_cndmask_b32_e64 v5, v5, v13, s[6:7]
798; GFX9-NEXT:    v_add_co_u32_e64 v13, s[6:7], 2, v2
799; GFX9-NEXT:    v_addc_co_u32_e64 v14, s[6:7], 0, v3, s[6:7]
800; GFX9-NEXT:    v_add_co_u32_e64 v15, s[6:7], 1, v2
801; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v4, v1, vcc
802; GFX9-NEXT:    v_addc_co_u32_e64 v16, s[6:7], 0, v3, s[6:7]
803; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v10
804; GFX9-NEXT:    v_cmp_ne_u32_e64 s[6:7], 0, v5
805; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
806; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v11
807; GFX9-NEXT:    v_cndmask_b32_e64 v5, v16, v14, s[6:7]
808; GFX9-NEXT:    v_cndmask_b32_e64 v14, 0, -1, vcc
809; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v10
810; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v14, vcc
811; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
812; GFX9-NEXT:    v_cndmask_b32_e64 v4, v15, v13, s[6:7]
813; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
814; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
815; GFX9-NEXT:    v_xor_b32_e32 v5, v7, v9
816; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v5
817; GFX9-NEXT:    v_xor_b32_e32 v3, v3, v5
818; GFX9-NEXT:    v_sub_co_u32_e64 v4, s[8:9], v2, v5
819; GFX9-NEXT:    v_subb_co_u32_e64 v2, s[4:5], v6, v10, s[4:5]
820; GFX9-NEXT:    v_subb_co_u32_e64 v5, s[8:9], v3, v5, s[8:9]
821; GFX9-NEXT:    v_sub_co_u32_e64 v3, s[4:5], v8, v11
822; GFX9-NEXT:    v_subbrev_co_u32_e64 v2, s[4:5], 0, v2, s[4:5]
823; GFX9-NEXT:    v_cndmask_b32_e64 v2, v12, v2, s[6:7]
824; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
825; GFX9-NEXT:    v_cndmask_b32_e64 v2, v8, v3, s[6:7]
826; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
827; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v7
828; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v7
829; GFX9-NEXT:    v_sub_co_u32_e32 v6, vcc, v0, v7
830; GFX9-NEXT:    v_subb_co_u32_e32 v7, vcc, v1, v7, vcc
831; GFX9-NEXT:    ; implicit-def: $vgpr2_vgpr3
832; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1
833; GFX9-NEXT:  .LBB8_2: ; %Flow
834; GFX9-NEXT:    s_or_saveexec_b64 s[4:5], s[10:11]
835; GFX9-NEXT:    s_xor_b64 exec, exec, s[4:5]
836; GFX9-NEXT:    s_cbranch_execz .LBB8_4
837; GFX9-NEXT:  ; %bb.3:
838; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
839; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v2
840; GFX9-NEXT:    v_mov_b32_e32 v5, 0
841; GFX9-NEXT:    v_mov_b32_e32 v7, v5
842; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
843; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
844; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
845; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v1
846; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
847; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
848; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
849; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v2
850; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
851; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v3
852; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v2
853; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
854; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
855; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
856; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v2
857; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
858; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
859; GFX9-NEXT:    v_cndmask_b32_e32 v6, v0, v3, vcc
860; GFX9-NEXT:    v_cndmask_b32_e32 v4, v1, v4, vcc
861; GFX9-NEXT:  .LBB8_4:
862; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
863; GFX9-NEXT:    v_mov_b32_e32 v0, v4
864; GFX9-NEXT:    v_mov_b32_e32 v1, v5
865; GFX9-NEXT:    v_mov_b32_e32 v2, v6
866; GFX9-NEXT:    v_mov_b32_e32 v3, v7
867; GFX9-NEXT:    s_setpc_b64 s[30:31]
868  %d = sdiv i64 %a, %b
869  %r = srem i64 %a, %b
870  %ins.0 = insertelement <2 x i64> undef, i64 %d, i32 0
871  %ins.1 = insertelement <2 x i64> %ins.0, i64 %r, i32 1
872  ret <2 x i64> %ins.1
873}
874
875define <2 x i64> @udivrem64(i64 %a, i64 %b) {
876; GFX9-LABEL: udivrem64:
877; GFX9:       ; %bb.0:
878; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
879; GFX9-NEXT:    v_or_b32_e32 v5, v1, v3
880; GFX9-NEXT:    v_mov_b32_e32 v4, 0
881; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[4:5]
882; GFX9-NEXT:    ; implicit-def: $vgpr6_vgpr7
883; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5
884; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
885; GFX9-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
886; GFX9-NEXT:    s_cbranch_execz .LBB9_2
887; GFX9-NEXT:  ; %bb.1:
888; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, v2
889; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v3
890; GFX9-NEXT:    v_sub_co_u32_e32 v10, vcc, 0, v2
891; GFX9-NEXT:    v_subb_co_u32_e32 v11, vcc, 0, v3, vcc
892; GFX9-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
893; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
894; GFX9-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
895; GFX9-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
896; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
897; GFX9-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
898; GFX9-NEXT:    v_cvt_u32_f32_e32 v8, v5
899; GFX9-NEXT:    v_cvt_u32_f32_e32 v9, v4
900; GFX9-NEXT:    v_mul_lo_u32 v6, v10, v8
901; GFX9-NEXT:    v_mul_lo_u32 v7, v11, v9
902; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v10, v9, 0
903; GFX9-NEXT:    v_add3_u32 v7, v5, v6, v7
904; GFX9-NEXT:    v_mul_hi_u32 v12, v9, v4
905; GFX9-NEXT:    v_mad_u64_u32 v[5:6], s[4:5], v9, v7, 0
906; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v12, v5
907; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v8, v4, 0
908; GFX9-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v6, vcc
909; GFX9-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], v8, v7, 0
910; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v12, v4
911; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v13, v5, vcc
912; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
913; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
914; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
915; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v9, v4
916; GFX9-NEXT:    v_addc_co_u32_e32 v13, vcc, v8, v5, vcc
917; GFX9-NEXT:    v_mul_lo_u32 v6, v10, v13
918; GFX9-NEXT:    v_mul_lo_u32 v7, v11, v12
919; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v10, v12, 0
920; GFX9-NEXT:    v_add3_u32 v7, v5, v6, v7
921; GFX9-NEXT:    v_mad_u64_u32 v[5:6], s[4:5], v13, v7, 0
922; GFX9-NEXT:    v_mad_u64_u32 v[7:8], s[4:5], v12, v7, 0
923; GFX9-NEXT:    v_mul_hi_u32 v11, v12, v4
924; GFX9-NEXT:    v_mad_u64_u32 v[9:10], s[4:5], v13, v4, 0
925; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v11, v7
926; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
927; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v9
928; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v10, vcc
929; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
930; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v5
931; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
932; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v12, v4
933; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v5, vcc
934; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v0, v7, 0
935; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v6
936; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v8, v4
937; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v5, vcc
938; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v1, v6, 0
939; GFX9-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], v1, v7, 0
940; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v8, v4
941; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
942; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
943; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v4, v6
944; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v5, vcc
945; GFX9-NEXT:    v_mul_lo_u32 v8, v3, v6
946; GFX9-NEXT:    v_mul_lo_u32 v9, v2, v7
947; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v2, v6, 0
948; GFX9-NEXT:    v_add3_u32 v5, v5, v9, v8
949; GFX9-NEXT:    v_sub_u32_e32 v8, v1, v5
950; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, v0, v4
951; GFX9-NEXT:    v_subb_co_u32_e64 v8, s[4:5], v8, v3, vcc
952; GFX9-NEXT:    v_sub_co_u32_e64 v9, s[4:5], v0, v2
953; GFX9-NEXT:    v_subbrev_co_u32_e64 v10, s[6:7], 0, v8, s[4:5]
954; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v10, v3
955; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[6:7]
956; GFX9-NEXT:    v_cmp_ge_u32_e64 s[6:7], v9, v2
957; GFX9-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[6:7]
958; GFX9-NEXT:    v_cmp_eq_u32_e64 s[6:7], v10, v3
959; GFX9-NEXT:    v_cndmask_b32_e64 v4, v4, v11, s[6:7]
960; GFX9-NEXT:    v_add_co_u32_e64 v11, s[6:7], 2, v6
961; GFX9-NEXT:    v_addc_co_u32_e64 v12, s[6:7], 0, v7, s[6:7]
962; GFX9-NEXT:    v_add_co_u32_e64 v13, s[6:7], 1, v6
963; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v5, vcc
964; GFX9-NEXT:    v_addc_co_u32_e64 v14, s[6:7], 0, v7, s[6:7]
965; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
966; GFX9-NEXT:    v_cmp_ne_u32_e64 s[6:7], 0, v4
967; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
968; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
969; GFX9-NEXT:    v_cndmask_b32_e64 v4, v14, v12, s[6:7]
970; GFX9-NEXT:    v_cndmask_b32_e64 v12, 0, -1, vcc
971; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
972; GFX9-NEXT:    v_subb_co_u32_e64 v3, s[4:5], v8, v3, s[4:5]
973; GFX9-NEXT:    v_sub_co_u32_e64 v2, s[4:5], v9, v2
974; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v12, vcc
975; GFX9-NEXT:    v_subbrev_co_u32_e64 v3, s[4:5], 0, v3, s[4:5]
976; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
977; GFX9-NEXT:    v_cndmask_b32_e64 v3, v10, v3, s[6:7]
978; GFX9-NEXT:    v_cndmask_b32_e32 v5, v7, v4, vcc
979; GFX9-NEXT:    v_cndmask_b32_e64 v4, v13, v11, s[6:7]
980; GFX9-NEXT:    v_cndmask_b32_e32 v7, v1, v3, vcc
981; GFX9-NEXT:    v_cndmask_b32_e64 v1, v9, v2, s[6:7]
982; GFX9-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
983; GFX9-NEXT:    v_cndmask_b32_e32 v6, v0, v1, vcc
984; GFX9-NEXT:    ; implicit-def: $vgpr2_vgpr3
985; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1
986; GFX9-NEXT:  .LBB9_2: ; %Flow
987; GFX9-NEXT:    s_or_saveexec_b64 s[4:5], s[8:9]
988; GFX9-NEXT:    s_xor_b64 exec, exec, s[4:5]
989; GFX9-NEXT:    s_cbranch_execz .LBB9_4
990; GFX9-NEXT:  ; %bb.3:
991; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
992; GFX9-NEXT:    v_sub_u32_e32 v3, 0, v2
993; GFX9-NEXT:    v_mov_b32_e32 v5, 0
994; GFX9-NEXT:    v_mov_b32_e32 v7, v5
995; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
996; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
997; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
998; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v1
999; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
1000; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
1001; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
1002; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v2
1003; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
1004; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v3
1005; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v2
1006; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
1007; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1008; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
1009; GFX9-NEXT:    v_sub_u32_e32 v3, v0, v2
1010; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
1011; GFX9-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
1012; GFX9-NEXT:    v_cndmask_b32_e32 v6, v0, v3, vcc
1013; GFX9-NEXT:    v_cndmask_b32_e32 v4, v1, v4, vcc
1014; GFX9-NEXT:  .LBB9_4:
1015; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
1016; GFX9-NEXT:    v_mov_b32_e32 v0, v4
1017; GFX9-NEXT:    v_mov_b32_e32 v1, v5
1018; GFX9-NEXT:    v_mov_b32_e32 v2, v6
1019; GFX9-NEXT:    v_mov_b32_e32 v3, v7
1020; GFX9-NEXT:    s_setpc_b64 s[30:31]
1021  %d = udiv i64 %a, %b
1022  %r = urem i64 %a, %b
1023  %ins.0 = insertelement <2 x i64> undef, i64 %d, i32 0
1024  %ins.1 = insertelement <2 x i64> %ins.0, i64 %r, i32 1
1025  ret <2 x i64> %ins.1
1026}
1027
1028define i64 @sdiv64_known32(i64 %a, i64 %b) {
1029; GFX9-LABEL: sdiv64_known32:
1030; GFX9:       ; %bb.0:
1031; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1032; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, v3
1033; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v1
1034; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
1035; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
1036; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
1037; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v2
1038; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
1039; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1040; GFX9-NEXT:    v_mov_b32_e32 v1, 0
1041; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
1042; GFX9-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
1043; GFX9-NEXT:    s_setpc_b64 s[30:31]
1044  %a.ext = ashr i64 %a, 32
1045  %b.ext = ashr i64 %b, 32
1046  %d = udiv i64 %a.ext, %b.ext
1047  ret i64 %d
1048}
1049
1050define i64 @udiv64_known32(i64 %a, i64 %b) {
1051; GFX9-LABEL: udiv64_known32:
1052; GFX9:       ; %bb.0:
1053; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1054; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, v2
1055; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, v0
1056; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1057; GFX9-NEXT:    v_mul_f32_e32 v2, v0, v2
1058; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
1059; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v2
1060; GFX9-NEXT:    v_mad_f32 v0, -v2, v1, v0
1061; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, v1
1062; GFX9-NEXT:    v_mov_b32_e32 v1, 0
1063; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
1064; GFX9-NEXT:    s_setpc_b64 s[30:31]
1065  %a.mask = and i64 %a, 4294967295
1066  %b.mask = and i64 %b, 4294967295
1067  %d = udiv i64 %a.mask, %b.mask
1068  ret i64 %d
1069}
1070