1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=amdgcn-- -verify-machineinstrs | FileCheck %s --check-prefixes=FUNC,GCN,SI
3; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s -check-prefixes=FUNC,GCN,VI
4
5declare i16 @llvm.bswap.i16(i16) nounwind readnone
6declare i32 @llvm.bswap.i32(i32) nounwind readnone
7declare <2 x i32> @llvm.bswap.v2i32(<2 x i32>) nounwind readnone
8declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone
9declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>) nounwind readnone
10declare i64 @llvm.bswap.i64(i64) nounwind readnone
11declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>) nounwind readnone
12declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>) nounwind readnone
13
14define amdgpu_kernel void @test_bswap_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
15; SI-LABEL: test_bswap_i32:
16; SI:       ; %bb.0:
17; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
18; SI-NEXT:    s_waitcnt lgkmcnt(0)
19; SI-NEXT:    s_load_dword s4, s[2:3], 0x0
20; SI-NEXT:    s_mov_b32 s3, 0xf000
21; SI-NEXT:    s_mov_b32 s2, -1
22; SI-NEXT:    s_waitcnt lgkmcnt(0)
23; SI-NEXT:    v_alignbit_b32 v0, s4, s4, 8
24; SI-NEXT:    v_alignbit_b32 v1, s4, s4, 24
25; SI-NEXT:    s_mov_b32 s4, 0xff00ff
26; SI-NEXT:    v_bfi_b32 v0, s4, v1, v0
27; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
28; SI-NEXT:    s_endpgm
29;
30; VI-LABEL: test_bswap_i32:
31; VI:       ; %bb.0:
32; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
33; VI-NEXT:    v_mov_b32_e32 v0, 0x10203
34; VI-NEXT:    s_mov_b32 s3, 0xf000
35; VI-NEXT:    s_mov_b32 s2, -1
36; VI-NEXT:    s_waitcnt lgkmcnt(0)
37; VI-NEXT:    s_mov_b32 s0, s4
38; VI-NEXT:    s_load_dword s4, s[6:7], 0x0
39; VI-NEXT:    s_mov_b32 s1, s5
40; VI-NEXT:    s_waitcnt lgkmcnt(0)
41; VI-NEXT:    v_perm_b32 v0, 0, s4, v0
42; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
43; VI-NEXT:    s_endpgm
44  %val = load i32, i32 addrspace(1)* %in, align 4
45  %bswap = call i32 @llvm.bswap.i32(i32 %val) nounwind readnone
46  store i32 %bswap, i32 addrspace(1)* %out, align 4
47  ret void
48}
49
50define amdgpu_kernel void @test_bswap_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) nounwind {
51; SI-LABEL: test_bswap_v2i32:
52; SI:       ; %bb.0:
53; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
54; SI-NEXT:    s_waitcnt lgkmcnt(0)
55; SI-NEXT:    s_load_dwordx2 s[4:5], s[2:3], 0x0
56; SI-NEXT:    s_mov_b32 s3, 0xf000
57; SI-NEXT:    s_mov_b32 s2, -1
58; SI-NEXT:    s_mov_b32 s6, 0xff00ff
59; SI-NEXT:    s_waitcnt lgkmcnt(0)
60; SI-NEXT:    v_alignbit_b32 v0, s5, s5, 8
61; SI-NEXT:    v_alignbit_b32 v1, s5, s5, 24
62; SI-NEXT:    v_alignbit_b32 v2, s4, s4, 8
63; SI-NEXT:    v_alignbit_b32 v3, s4, s4, 24
64; SI-NEXT:    v_bfi_b32 v1, s6, v1, v0
65; SI-NEXT:    v_bfi_b32 v0, s6, v3, v2
66; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
67; SI-NEXT:    s_endpgm
68;
69; VI-LABEL: test_bswap_v2i32:
70; VI:       ; %bb.0:
71; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
72; VI-NEXT:    v_mov_b32_e32 v0, 0x10203
73; VI-NEXT:    s_mov_b32 s3, 0xf000
74; VI-NEXT:    s_mov_b32 s2, -1
75; VI-NEXT:    s_waitcnt lgkmcnt(0)
76; VI-NEXT:    s_mov_b32 s0, s4
77; VI-NEXT:    s_mov_b32 s1, s5
78; VI-NEXT:    s_load_dwordx2 s[4:5], s[6:7], 0x0
79; VI-NEXT:    s_waitcnt lgkmcnt(0)
80; VI-NEXT:    v_perm_b32 v1, 0, s5, v0
81; VI-NEXT:    v_perm_b32 v0, 0, s4, v0
82; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
83; VI-NEXT:    s_endpgm
84  %val = load <2 x i32>, <2 x i32> addrspace(1)* %in, align 8
85  %bswap = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %val) nounwind readnone
86  store <2 x i32> %bswap, <2 x i32> addrspace(1)* %out, align 8
87  ret void
88}
89
90define amdgpu_kernel void @test_bswap_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) nounwind {
91; SI-LABEL: test_bswap_v4i32:
92; SI:       ; %bb.0:
93; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
94; SI-NEXT:    s_waitcnt lgkmcnt(0)
95; SI-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
96; SI-NEXT:    s_mov_b32 s3, 0xf000
97; SI-NEXT:    s_mov_b32 s2, -1
98; SI-NEXT:    s_mov_b32 s8, 0xff00ff
99; SI-NEXT:    s_waitcnt lgkmcnt(0)
100; SI-NEXT:    v_alignbit_b32 v0, s7, s7, 8
101; SI-NEXT:    v_alignbit_b32 v1, s7, s7, 24
102; SI-NEXT:    v_alignbit_b32 v2, s6, s6, 8
103; SI-NEXT:    v_alignbit_b32 v4, s6, s6, 24
104; SI-NEXT:    v_alignbit_b32 v5, s5, s5, 8
105; SI-NEXT:    v_alignbit_b32 v6, s5, s5, 24
106; SI-NEXT:    v_alignbit_b32 v7, s4, s4, 8
107; SI-NEXT:    v_alignbit_b32 v8, s4, s4, 24
108; SI-NEXT:    v_bfi_b32 v3, s8, v1, v0
109; SI-NEXT:    v_bfi_b32 v2, s8, v4, v2
110; SI-NEXT:    v_bfi_b32 v1, s8, v6, v5
111; SI-NEXT:    v_bfi_b32 v0, s8, v8, v7
112; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
113; SI-NEXT:    s_endpgm
114;
115; VI-LABEL: test_bswap_v4i32:
116; VI:       ; %bb.0:
117; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
118; VI-NEXT:    v_mov_b32_e32 v0, 0x10203
119; VI-NEXT:    s_mov_b32 s3, 0xf000
120; VI-NEXT:    s_mov_b32 s2, -1
121; VI-NEXT:    s_waitcnt lgkmcnt(0)
122; VI-NEXT:    s_mov_b32 s0, s4
123; VI-NEXT:    s_mov_b32 s1, s5
124; VI-NEXT:    s_load_dwordx4 s[4:7], s[6:7], 0x0
125; VI-NEXT:    s_waitcnt lgkmcnt(0)
126; VI-NEXT:    v_perm_b32 v3, 0, s7, v0
127; VI-NEXT:    v_perm_b32 v2, 0, s6, v0
128; VI-NEXT:    v_perm_b32 v1, 0, s5, v0
129; VI-NEXT:    v_perm_b32 v0, 0, s4, v0
130; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
131; VI-NEXT:    s_endpgm
132  %val = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16
133  %bswap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val) nounwind readnone
134  store <4 x i32> %bswap, <4 x i32> addrspace(1)* %out, align 16
135  ret void
136}
137
138define amdgpu_kernel void @test_bswap_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) nounwind {
139; SI-LABEL: test_bswap_v8i32:
140; SI:       ; %bb.0:
141; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
142; SI-NEXT:    s_waitcnt lgkmcnt(0)
143; SI-NEXT:    s_load_dwordx8 s[0:7], s[10:11], 0x0
144; SI-NEXT:    s_mov_b32 s11, 0xf000
145; SI-NEXT:    s_mov_b32 s10, -1
146; SI-NEXT:    s_mov_b32 s12, 0xff00ff
147; SI-NEXT:    s_waitcnt lgkmcnt(0)
148; SI-NEXT:    v_alignbit_b32 v0, s3, s3, 8
149; SI-NEXT:    v_alignbit_b32 v1, s3, s3, 24
150; SI-NEXT:    v_alignbit_b32 v2, s2, s2, 8
151; SI-NEXT:    v_alignbit_b32 v4, s2, s2, 24
152; SI-NEXT:    v_alignbit_b32 v5, s1, s1, 8
153; SI-NEXT:    v_alignbit_b32 v6, s1, s1, 24
154; SI-NEXT:    v_alignbit_b32 v7, s0, s0, 8
155; SI-NEXT:    v_alignbit_b32 v8, s0, s0, 24
156; SI-NEXT:    v_alignbit_b32 v9, s7, s7, 8
157; SI-NEXT:    v_alignbit_b32 v10, s7, s7, 24
158; SI-NEXT:    v_alignbit_b32 v11, s6, s6, 8
159; SI-NEXT:    v_alignbit_b32 v12, s6, s6, 24
160; SI-NEXT:    v_alignbit_b32 v13, s5, s5, 8
161; SI-NEXT:    v_alignbit_b32 v14, s5, s5, 24
162; SI-NEXT:    v_alignbit_b32 v15, s4, s4, 8
163; SI-NEXT:    v_alignbit_b32 v16, s4, s4, 24
164; SI-NEXT:    v_bfi_b32 v3, s12, v1, v0
165; SI-NEXT:    v_bfi_b32 v2, s12, v4, v2
166; SI-NEXT:    v_bfi_b32 v1, s12, v6, v5
167; SI-NEXT:    v_bfi_b32 v0, s12, v8, v7
168; SI-NEXT:    v_bfi_b32 v7, s12, v10, v9
169; SI-NEXT:    v_bfi_b32 v6, s12, v12, v11
170; SI-NEXT:    v_bfi_b32 v5, s12, v14, v13
171; SI-NEXT:    v_bfi_b32 v4, s12, v16, v15
172; SI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:16
173; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
174; SI-NEXT:    s_endpgm
175;
176; VI-LABEL: test_bswap_v8i32:
177; VI:       ; %bb.0:
178; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
179; VI-NEXT:    v_mov_b32_e32 v4, 0x10203
180; VI-NEXT:    s_mov_b32 s11, 0xf000
181; VI-NEXT:    s_mov_b32 s10, -1
182; VI-NEXT:    s_waitcnt lgkmcnt(0)
183; VI-NEXT:    s_mov_b32 s8, s0
184; VI-NEXT:    s_mov_b32 s9, s1
185; VI-NEXT:    s_load_dwordx8 s[0:7], s[2:3], 0x0
186; VI-NEXT:    s_waitcnt lgkmcnt(0)
187; VI-NEXT:    v_perm_b32 v3, 0, s3, v4
188; VI-NEXT:    v_perm_b32 v2, 0, s2, v4
189; VI-NEXT:    v_perm_b32 v1, 0, s1, v4
190; VI-NEXT:    v_perm_b32 v0, 0, s0, v4
191; VI-NEXT:    v_perm_b32 v7, 0, s7, v4
192; VI-NEXT:    v_perm_b32 v6, 0, s6, v4
193; VI-NEXT:    v_perm_b32 v5, 0, s5, v4
194; VI-NEXT:    v_perm_b32 v4, 0, s4, v4
195; VI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:16
196; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
197; VI-NEXT:    s_endpgm
198  %val = load <8 x i32>, <8 x i32> addrspace(1)* %in, align 32
199  %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %val) nounwind readnone
200  store <8 x i32> %bswap, <8 x i32> addrspace(1)* %out, align 32
201  ret void
202}
203
204define amdgpu_kernel void @test_bswap_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
205; SI-LABEL: test_bswap_i64:
206; SI:       ; %bb.0:
207; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
208; SI-NEXT:    s_waitcnt lgkmcnt(0)
209; SI-NEXT:    s_load_dwordx2 s[4:5], s[2:3], 0x0
210; SI-NEXT:    s_mov_b32 s3, 0xf000
211; SI-NEXT:    s_mov_b32 s2, -1
212; SI-NEXT:    s_mov_b32 s6, 0xff00ff
213; SI-NEXT:    s_waitcnt lgkmcnt(0)
214; SI-NEXT:    v_alignbit_b32 v0, s4, s4, 8
215; SI-NEXT:    v_alignbit_b32 v1, s4, s4, 24
216; SI-NEXT:    v_alignbit_b32 v2, s5, s5, 8
217; SI-NEXT:    v_alignbit_b32 v3, s5, s5, 24
218; SI-NEXT:    v_bfi_b32 v1, s6, v1, v0
219; SI-NEXT:    v_bfi_b32 v0, s6, v3, v2
220; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
221; SI-NEXT:    s_endpgm
222;
223; VI-LABEL: test_bswap_i64:
224; VI:       ; %bb.0:
225; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
226; VI-NEXT:    v_mov_b32_e32 v0, 0x10203
227; VI-NEXT:    s_mov_b32 s3, 0xf000
228; VI-NEXT:    s_mov_b32 s2, -1
229; VI-NEXT:    s_waitcnt lgkmcnt(0)
230; VI-NEXT:    s_mov_b32 s0, s4
231; VI-NEXT:    s_mov_b32 s1, s5
232; VI-NEXT:    s_load_dwordx2 s[4:5], s[6:7], 0x0
233; VI-NEXT:    s_waitcnt lgkmcnt(0)
234; VI-NEXT:    v_perm_b32 v1, 0, s4, v0
235; VI-NEXT:    v_perm_b32 v0, 0, s5, v0
236; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
237; VI-NEXT:    s_endpgm
238  %val = load i64, i64 addrspace(1)* %in, align 8
239  %bswap = call i64 @llvm.bswap.i64(i64 %val) nounwind readnone
240  store i64 %bswap, i64 addrspace(1)* %out, align 8
241  ret void
242}
243
244define amdgpu_kernel void @test_bswap_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) nounwind {
245; SI-LABEL: test_bswap_v2i64:
246; SI:       ; %bb.0:
247; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
248; SI-NEXT:    s_waitcnt lgkmcnt(0)
249; SI-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
250; SI-NEXT:    s_mov_b32 s3, 0xf000
251; SI-NEXT:    s_mov_b32 s2, -1
252; SI-NEXT:    s_mov_b32 s8, 0xff00ff
253; SI-NEXT:    s_waitcnt lgkmcnt(0)
254; SI-NEXT:    v_alignbit_b32 v0, s6, s6, 8
255; SI-NEXT:    v_alignbit_b32 v1, s6, s6, 24
256; SI-NEXT:    v_alignbit_b32 v2, s7, s7, 8
257; SI-NEXT:    v_alignbit_b32 v4, s7, s7, 24
258; SI-NEXT:    v_alignbit_b32 v5, s4, s4, 8
259; SI-NEXT:    v_alignbit_b32 v6, s4, s4, 24
260; SI-NEXT:    v_alignbit_b32 v7, s5, s5, 8
261; SI-NEXT:    v_alignbit_b32 v8, s5, s5, 24
262; SI-NEXT:    v_bfi_b32 v3, s8, v1, v0
263; SI-NEXT:    v_bfi_b32 v2, s8, v4, v2
264; SI-NEXT:    v_bfi_b32 v1, s8, v6, v5
265; SI-NEXT:    v_bfi_b32 v0, s8, v8, v7
266; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
267; SI-NEXT:    s_endpgm
268;
269; VI-LABEL: test_bswap_v2i64:
270; VI:       ; %bb.0:
271; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
272; VI-NEXT:    v_mov_b32_e32 v0, 0x10203
273; VI-NEXT:    s_mov_b32 s3, 0xf000
274; VI-NEXT:    s_mov_b32 s2, -1
275; VI-NEXT:    s_waitcnt lgkmcnt(0)
276; VI-NEXT:    s_mov_b32 s0, s4
277; VI-NEXT:    s_mov_b32 s1, s5
278; VI-NEXT:    s_load_dwordx4 s[4:7], s[6:7], 0x0
279; VI-NEXT:    s_waitcnt lgkmcnt(0)
280; VI-NEXT:    v_perm_b32 v3, 0, s6, v0
281; VI-NEXT:    v_perm_b32 v2, 0, s7, v0
282; VI-NEXT:    v_perm_b32 v1, 0, s4, v0
283; VI-NEXT:    v_perm_b32 v0, 0, s5, v0
284; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
285; VI-NEXT:    s_endpgm
286  %val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16
287  %bswap = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %val) nounwind readnone
288  store <2 x i64> %bswap, <2 x i64> addrspace(1)* %out, align 16
289  ret void
290}
291
292define amdgpu_kernel void @test_bswap_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) nounwind {
293; SI-LABEL: test_bswap_v4i64:
294; SI:       ; %bb.0:
295; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
296; SI-NEXT:    s_waitcnt lgkmcnt(0)
297; SI-NEXT:    s_load_dwordx8 s[0:7], s[10:11], 0x0
298; SI-NEXT:    s_mov_b32 s11, 0xf000
299; SI-NEXT:    s_mov_b32 s10, -1
300; SI-NEXT:    s_mov_b32 s12, 0xff00ff
301; SI-NEXT:    s_waitcnt lgkmcnt(0)
302; SI-NEXT:    v_alignbit_b32 v0, s2, s2, 8
303; SI-NEXT:    v_alignbit_b32 v1, s2, s2, 24
304; SI-NEXT:    v_alignbit_b32 v2, s3, s3, 8
305; SI-NEXT:    v_alignbit_b32 v4, s3, s3, 24
306; SI-NEXT:    v_alignbit_b32 v5, s0, s0, 8
307; SI-NEXT:    v_alignbit_b32 v6, s0, s0, 24
308; SI-NEXT:    v_alignbit_b32 v7, s1, s1, 8
309; SI-NEXT:    v_alignbit_b32 v8, s1, s1, 24
310; SI-NEXT:    v_alignbit_b32 v9, s6, s6, 8
311; SI-NEXT:    v_alignbit_b32 v10, s6, s6, 24
312; SI-NEXT:    v_alignbit_b32 v11, s7, s7, 8
313; SI-NEXT:    v_alignbit_b32 v12, s7, s7, 24
314; SI-NEXT:    v_alignbit_b32 v13, s4, s4, 8
315; SI-NEXT:    v_alignbit_b32 v14, s4, s4, 24
316; SI-NEXT:    v_alignbit_b32 v15, s5, s5, 8
317; SI-NEXT:    v_alignbit_b32 v16, s5, s5, 24
318; SI-NEXT:    v_bfi_b32 v3, s12, v1, v0
319; SI-NEXT:    v_bfi_b32 v2, s12, v4, v2
320; SI-NEXT:    v_bfi_b32 v1, s12, v6, v5
321; SI-NEXT:    v_bfi_b32 v0, s12, v8, v7
322; SI-NEXT:    v_bfi_b32 v7, s12, v10, v9
323; SI-NEXT:    v_bfi_b32 v6, s12, v12, v11
324; SI-NEXT:    v_bfi_b32 v5, s12, v14, v13
325; SI-NEXT:    v_bfi_b32 v4, s12, v16, v15
326; SI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:16
327; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
328; SI-NEXT:    s_endpgm
329;
330; VI-LABEL: test_bswap_v4i64:
331; VI:       ; %bb.0:
332; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
333; VI-NEXT:    v_mov_b32_e32 v4, 0x10203
334; VI-NEXT:    s_mov_b32 s11, 0xf000
335; VI-NEXT:    s_mov_b32 s10, -1
336; VI-NEXT:    s_waitcnt lgkmcnt(0)
337; VI-NEXT:    s_mov_b32 s8, s0
338; VI-NEXT:    s_mov_b32 s9, s1
339; VI-NEXT:    s_load_dwordx8 s[0:7], s[2:3], 0x0
340; VI-NEXT:    s_waitcnt lgkmcnt(0)
341; VI-NEXT:    v_perm_b32 v3, 0, s2, v4
342; VI-NEXT:    v_perm_b32 v2, 0, s3, v4
343; VI-NEXT:    v_perm_b32 v1, 0, s0, v4
344; VI-NEXT:    v_perm_b32 v0, 0, s1, v4
345; VI-NEXT:    v_perm_b32 v7, 0, s6, v4
346; VI-NEXT:    v_perm_b32 v6, 0, s7, v4
347; VI-NEXT:    v_perm_b32 v5, 0, s4, v4
348; VI-NEXT:    v_perm_b32 v4, 0, s5, v4
349; VI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:16
350; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
351; VI-NEXT:    s_endpgm
352  %val = load <4 x i64>, <4 x i64> addrspace(1)* %in, align 32
353  %bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %val) nounwind readnone
354  store <4 x i64> %bswap, <4 x i64> addrspace(1)* %out, align 32
355  ret void
356}
357
358define float @missing_truncate_promote_bswap(i32 %arg) {
359; SI-LABEL: missing_truncate_promote_bswap:
360; SI:       ; %bb.0: ; %bb
361; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
362; SI-NEXT:    v_alignbit_b32 v1, v0, v0, 8
363; SI-NEXT:    v_alignbit_b32 v0, v0, v0, 24
364; SI-NEXT:    s_mov_b32 s4, 0xff00ff
365; SI-NEXT:    v_bfi_b32 v0, s4, v0, v1
366; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
367; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
368; SI-NEXT:    s_setpc_b64 s[30:31]
369;
370; VI-LABEL: missing_truncate_promote_bswap:
371; VI:       ; %bb.0: ; %bb
372; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
373; VI-NEXT:    s_mov_b32 s4, 0x10203
374; VI-NEXT:    v_perm_b32 v0, 0, v0, s4
375; VI-NEXT:    v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
376; VI-NEXT:    s_setpc_b64 s[30:31]
377bb:
378  %tmp = trunc i32 %arg to i16
379  %tmp1 = call i16 @llvm.bswap.i16(i16 %tmp)
380  %tmp2 = bitcast i16 %tmp1 to half
381  %tmp3 = fpext half %tmp2 to float
382  ret float %tmp3
383}
384