1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s
2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s
3
4declare i16 @llvm.bswap.i16(i16) nounwind readnone
5declare i32 @llvm.bswap.i32(i32) nounwind readnone
6declare <2 x i32> @llvm.bswap.v2i32(<2 x i32>) nounwind readnone
7declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone
8declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>) nounwind readnone
9declare i64 @llvm.bswap.i64(i64) nounwind readnone
10declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>) nounwind readnone
11declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>) nounwind readnone
12
13; FUNC-LABEL: @test_bswap_i32
14; GCN: s_load_dword [[VAL:s[0-9]+]]
15; GCN-DAG: v_alignbit_b32 [[TMP0:v[0-9]+]], [[VAL]], [[VAL]], 8
16; GCN-DAG: v_alignbit_b32 [[TMP1:v[0-9]+]], [[VAL]], [[VAL]], 24
17; GCN-DAG: s_mov_b32 [[K:s[0-9]+]], 0xff00ff
18; GCN: v_bfi_b32 [[RESULT:v[0-9]+]], [[K]], [[TMP1]], [[TMP0]]
19; GCN: buffer_store_dword [[RESULT]]
20; GCN: s_endpgm
21define amdgpu_kernel void @test_bswap_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
22  %val = load i32, i32 addrspace(1)* %in, align 4
23  %bswap = call i32 @llvm.bswap.i32(i32 %val) nounwind readnone
24  store i32 %bswap, i32 addrspace(1)* %out, align 4
25  ret void
26}
27
28; FUNC-LABEL: @test_bswap_v2i32
29; GCN-DAG: v_alignbit_b32
30; GCN-DAG: v_alignbit_b32
31; GCN-DAG: v_bfi_b32
32; GCN-DAG: v_alignbit_b32
33; GCN-DAG: v_alignbit_b32
34; GCN-DAG: v_bfi_b32
35; GCN: s_endpgm
36define amdgpu_kernel void @test_bswap_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) nounwind {
37  %val = load <2 x i32>, <2 x i32> addrspace(1)* %in, align 8
38  %bswap = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %val) nounwind readnone
39  store <2 x i32> %bswap, <2 x i32> addrspace(1)* %out, align 8
40  ret void
41}
42
43; FUNC-LABEL: @test_bswap_v4i32
44; GCN-DAG: v_alignbit_b32
45; GCN-DAG: v_alignbit_b32
46; GCN-DAG: v_bfi_b32
47; GCN-DAG: v_alignbit_b32
48; GCN-DAG: v_alignbit_b32
49; GCN-DAG: v_bfi_b32
50; GCN-DAG: v_alignbit_b32
51; GCN-DAG: v_alignbit_b32
52; GCN-DAG: v_bfi_b32
53; GCN-DAG: v_alignbit_b32
54; GCN-DAG: v_alignbit_b32
55; GCN-DAG: v_bfi_b32
56; GCN: s_endpgm
57define amdgpu_kernel void @test_bswap_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) nounwind {
58  %val = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16
59  %bswap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val) nounwind readnone
60  store <4 x i32> %bswap, <4 x i32> addrspace(1)* %out, align 16
61  ret void
62}
63
64; FUNC-LABEL: @test_bswap_v8i32
65; GCN-DAG: v_alignbit_b32
66; GCN-DAG: v_alignbit_b32
67; GCN-DAG: v_bfi_b32
68; GCN-DAG: v_alignbit_b32
69; GCN-DAG: v_alignbit_b32
70; GCN-DAG: v_bfi_b32
71; GCN-DAG: v_alignbit_b32
72; GCN-DAG: v_alignbit_b32
73; GCN-DAG: v_bfi_b32
74; GCN-DAG: v_alignbit_b32
75; GCN-DAG: v_alignbit_b32
76; GCN-DAG: v_bfi_b32
77; GCN-DAG: v_alignbit_b32
78; GCN-DAG: v_alignbit_b32
79; GCN-DAG: v_bfi_b32
80; GCN-DAG: v_alignbit_b32
81; GCN-DAG: v_alignbit_b32
82; GCN-DAG: v_bfi_b32
83; GCN-DAG: v_alignbit_b32
84; GCN-DAG: v_alignbit_b32
85; GCN-DAG: v_bfi_b32
86; GCN-DAG: v_alignbit_b32
87; GCN-DAG: v_alignbit_b32
88; GCN-DAG: v_bfi_b32
89; GCN: s_endpgm
90define amdgpu_kernel void @test_bswap_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) nounwind {
91  %val = load <8 x i32>, <8 x i32> addrspace(1)* %in, align 32
92  %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %val) nounwind readnone
93  store <8 x i32> %bswap, <8 x i32> addrspace(1)* %out, align 32
94  ret void
95}
96
97; FUNC-LABEL: {{^}}test_bswap_i64:
98; GCN-NOT: v_or_b32_e64 v{{[0-9]+}}, 0, 0
99define amdgpu_kernel void @test_bswap_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
100  %val = load i64, i64 addrspace(1)* %in, align 8
101  %bswap = call i64 @llvm.bswap.i64(i64 %val) nounwind readnone
102  store i64 %bswap, i64 addrspace(1)* %out, align 8
103  ret void
104}
105
106define amdgpu_kernel void @test_bswap_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) nounwind {
107  %val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16
108  %bswap = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %val) nounwind readnone
109  store <2 x i64> %bswap, <2 x i64> addrspace(1)* %out, align 16
110  ret void
111}
112
113define amdgpu_kernel void @test_bswap_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) nounwind {
114  %val = load <4 x i64>, <4 x i64> addrspace(1)* %in, align 32
115  %bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %val) nounwind readnone
116  store <4 x i64> %bswap, <4 x i64> addrspace(1)* %out, align 32
117  ret void
118}
119
120; GCN-LABEL: {{^}}missing_truncate_promote_bswap:
121; VI: v_and_b32
122; VI: v_alignbit_b32
123; VI: v_alignbit_b32
124; VI: v_bfi_b32
125define float @missing_truncate_promote_bswap(i32 %arg) {
126bb:
127  %tmp = trunc i32 %arg to i16
128  %tmp1 = call i16 @llvm.bswap.i16(i16 %tmp)
129  %tmp2 = bitcast i16 %tmp1 to half
130  %tmp3 = fpext half %tmp2 to float
131  ret float %tmp3
132}
133