1; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
2
3
4; FIXME: We should use llvm-mc for this, but we can't even parse our own output.
5;        See PR33579.
6; RUN: llc -march=amdgcn -verify-machineinstrs -amdgpu-s-branch-bits=4 -o %t.o -filetype=obj %s
7; RUN: llvm-readobj -r %t.o | FileCheck --check-prefix=OBJ %s
8
9; OBJ:       Relocations [
10; OBJ-NEXT: ]
11
12; Restrict maximum branch to between +7 and -8 dwords
13
14; Used to emit an always 4 byte instruction. Inline asm always assumes
15; each instruction is the maximum size.
16declare void @llvm.amdgcn.s.sleep(i32) #0
17
18declare i32 @llvm.amdgcn.workitem.id.x() #1
19
20
21; GCN-LABEL: {{^}}uniform_conditional_max_short_forward_branch:
22; GCN: s_load_dword [[CND:s[0-9]+]]
23; GCN: s_cmp_eq_u32 [[CND]], 0
24; GCN-NEXT: s_cbranch_scc1 [[BB3:BB[0-9]+_[0-9]+]]
25
26
27; GCN-NEXT: ; %bb.1: ; %bb2
28; GCN-NEXT: ;;#ASMSTART
29; GCN-NEXT: v_nop_e64
30; GCN-NEXT: v_nop_e64
31; GCN-NEXT: v_nop_e64
32; GCN-NEXT: ;;#ASMEND
33; GCN-NEXT: s_sleep 0
34
35; GCN-NEXT: [[BB3]]: ; %bb3
36; GCN: v_mov_b32_e32 [[V_CND:v[0-9]+]], [[CND]]
37; GCN: buffer_store_dword [[V_CND]]
38; GCN: s_endpgm
39define amdgpu_kernel void @uniform_conditional_max_short_forward_branch(i32 addrspace(1)* %arg, i32 %cnd) #0 {
40bb:
41  %cmp = icmp eq i32 %cnd, 0
42  br i1 %cmp, label %bb3, label %bb2 ; +8 dword branch
43
44bb2:
45; 24 bytes
46  call void asm sideeffect
47   "v_nop_e64
48    v_nop_e64
49    v_nop_e64", ""() #0
50  call void @llvm.amdgcn.s.sleep(i32 0)
51  br label %bb3
52
53bb3:
54  store volatile i32 %cnd, i32 addrspace(1)* %arg
55  ret void
56}
57
58; GCN-LABEL: {{^}}uniform_conditional_min_long_forward_branch:
59; GCN: s_load_dword [[CND:s[0-9]+]]
60; GCN: s_cmp_eq_u32 [[CND]], 0
61; GCN-NEXT: s_cbranch_scc0 [[LONGBB:BB[0-9]+_[0-9]+]]
62
63; GCN-NEXT: [[LONG_JUMP:BB[0-9]+_[0-9]+]]: ; %bb0
64; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
65; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], [[ENDBB:BB[0-9]+_[0-9]+]]-([[LONG_JUMP]]+4)
66; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], 0
67; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
68
69; GCN-NEXT: [[LONGBB]]:
70; GCN-NEXT: ;;#ASMSTART
71; GCN: v_nop_e64
72; GCN: v_nop_e64
73; GCN: v_nop_e64
74; GCN: v_nop_e64
75; GCN-NEXT: ;;#ASMEND
76
77; GCN-NEXT: [[ENDBB]]:
78; GCN: v_mov_b32_e32 [[V_CND:v[0-9]+]], [[CND]]
79; GCN: buffer_store_dword [[V_CND]]
80; GCN: s_endpgm
81define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(i32 addrspace(1)* %arg, i32 %cnd) #0 {
82bb0:
83  %cmp = icmp eq i32 %cnd, 0
84  br i1 %cmp, label %bb3, label %bb2 ; +9 dword branch
85
86bb2:
87; 32 bytes
88  call void asm sideeffect
89   "v_nop_e64
90    v_nop_e64
91    v_nop_e64
92    v_nop_e64", ""() #0
93  br label %bb3
94
95bb3:
96  store volatile i32 %cnd, i32 addrspace(1)* %arg
97  ret void
98}
99
100; GCN-LABEL: {{^}}uniform_conditional_min_long_forward_vcnd_branch:
101; GCN: s_load_dword [[CND:s[0-9]+]]
102
103; GCN-DAG: v_cmp_eq_f32_e64 [[UNMASKED:s\[[0-9]+:[0-9]+\]]], [[CND]], 0
104; GCN-DAG: s_and_b64 vcc, exec, [[UNMASKED]]
105; GCN: s_cbranch_vccz [[LONGBB:BB[0-9]+_[0-9]+]]
106
107; GCN-NEXT: [[LONG_JUMP:BB[0-9]+_[0-9]+]]: ; %bb0
108; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
109; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], [[ENDBB:BB[0-9]+_[0-9]+]]-([[LONG_JUMP]]+4)
110; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], 0
111; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
112
113; GCN-NEXT: [[LONGBB]]:
114; GCN: v_nop_e64
115; GCN: v_nop_e64
116; GCN: v_nop_e64
117; GCN: v_nop_e64
118
119; GCN: [[ENDBB]]:
120; GCN: v_mov_b32_e32 [[V_CND:v[0-9]+]], [[CND]]
121; GCN: buffer_store_dword [[V_CND]]
122; GCN: s_endpgm
123define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(float addrspace(1)* %arg, float %cnd) #0 {
124bb0:
125  %cmp = fcmp oeq float %cnd, 0.0
126  br i1 %cmp, label %bb3, label %bb2 ; + 8 dword branch
127
128bb2:
129  call void asm sideeffect " ; 32 bytes
130    v_nop_e64
131    v_nop_e64
132    v_nop_e64
133    v_nop_e64", ""() #0
134  br label %bb3
135
136bb3:
137  store volatile float %cnd, float addrspace(1)* %arg
138  ret void
139}
140
141; GCN-LABEL: {{^}}min_long_forward_vbranch:
142
143; GCN: buffer_load_dword
144; GCN: v_cmp_ne_u32_e32 vcc, 0, v{{[0-9]+}}
145; GCN: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], vcc
146
147; GCN: v_nop_e64
148; GCN: v_nop_e64
149; GCN: v_nop_e64
150; GCN: v_nop_e64
151
152; GCN: s_or_b64 exec, exec, [[SAVE]]
153; GCN: buffer_store_dword
154; GCN: s_endpgm
155define amdgpu_kernel void @min_long_forward_vbranch(i32 addrspace(1)* %arg) #0 {
156bb:
157  %tid = call i32 @llvm.amdgcn.workitem.id.x()
158  %tid.ext = zext i32 %tid to i64
159  %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tid.ext
160  %load = load volatile i32, i32 addrspace(1)* %gep
161  %cmp = icmp eq i32 %load, 0
162  br i1 %cmp, label %bb3, label %bb2 ; + 8 dword branch
163
164bb2:
165  call void asm sideeffect " ; 32 bytes
166    v_nop_e64
167    v_nop_e64
168    v_nop_e64
169    v_nop_e64", ""() #0
170  br label %bb3
171
172bb3:
173  store volatile i32 %load, i32 addrspace(1)* %gep
174  ret void
175}
176
177; GCN-LABEL: {{^}}long_backward_sbranch:
178; GCN: s_mov_b32 [[LOOPIDX:s[0-9]+]], 0{{$}}
179
180; GCN: [[LOOPBB:BB[0-9]+_[0-9]+]]: ; %bb2
181; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
182; GCN-NEXT: s_add_i32 [[INC:s[0-9]+]], [[LOOPIDX]], 1
183; GCN-NEXT: s_cmp_lt_i32 [[INC]], 10
184
185; GCN-NEXT: ;;#ASMSTART
186; GCN-NEXT: v_nop_e64
187; GCN-NEXT: v_nop_e64
188; GCN-NEXT: v_nop_e64
189; GCN-NEXT: ;;#ASMEND
190
191; GCN-NEXT: s_cbranch_scc0 [[ENDBB:BB[0-9]+_[0-9]+]]
192
193; GCN-NEXT: [[LONG_JUMP:BB[0-9]+_[0-9]+]]: ; %bb2
194; GCN-NEXT: ; in Loop: Header=[[LOOPBB]] Depth=1
195
196; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
197; GCN-NEXT: s_sub_u32 s[[PC_LO]], s[[PC_LO]], ([[LONG_JUMP]]+4)-[[LOOPBB]]
198; GCN-NEXT: s_subb_u32 s[[PC_HI]], s[[PC_HI]], 0
199; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
200
201; GCN-NEXT: [[ENDBB]]:
202; GCN-NEXT: s_endpgm
203define amdgpu_kernel void @long_backward_sbranch(i32 addrspace(1)* %arg) #0 {
204bb:
205  br label %bb2
206
207bb2:
208  %loop.idx = phi i32 [ 0, %bb ], [ %inc, %bb2 ]
209   ; 24 bytes
210  call void asm sideeffect
211   "v_nop_e64
212    v_nop_e64
213    v_nop_e64", ""() #0
214  %inc = add nsw i32 %loop.idx, 1 ; add cost 4
215  %cmp = icmp slt i32 %inc, 10 ; condition cost = 8
216  br i1 %cmp, label %bb2, label %bb3 ; -
217
218bb3:
219  ret void
220}
221
222; Requires expansion of unconditional branch from %bb2 to %bb4 (and
223; expansion of conditional branch from %bb to %bb3.
224
225; GCN-LABEL: {{^}}uniform_unconditional_min_long_forward_branch:
226; GCN: s_cmp_eq_u32
227; GCN-NEXT: s_cbranch_scc0 [[BB2:BB[0-9]+_[0-9]+]]
228
229; GCN-NEXT: [[LONG_JUMP0:BB[0-9]+_[0-9]+]]: ; %bb0
230; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
231; GCN-NEXT: s_add_u32 s[[PC0_LO]], s[[PC0_LO]], [[BB3:BB[0-9]_[0-9]+]]-([[LONG_JUMP0]]+4)
232; GCN-NEXT: s_addc_u32 s[[PC0_HI]], s[[PC0_HI]], 0{{$}}
233; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC0_LO]]:[[PC0_HI]]{{\]}}
234
235; GCN-NEXT: [[BB2]]: ; %bb2
236; GCN: v_mov_b32_e32 [[BB2_K:v[0-9]+]], 17
237; GCN: buffer_store_dword [[BB2_K]]
238
239; GCN-NEXT: [[LONG_JUMP1:BB[0-9]+_[0-9]+]]: ; %bb2
240; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}}
241; GCN-NEXT: s_add_u32 s[[PC1_LO]], s[[PC1_LO]], [[BB4:BB[0-9]_[0-9]+]]-([[LONG_JUMP1]]+4)
242; GCN-NEXT: s_addc_u32 s[[PC1_HI]], s[[PC1_HI]], 0{{$}}
243; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC1_LO]]:[[PC1_HI]]{{\]}}
244
245; GCN: [[BB3]]: ; %bb3
246; GCN: v_nop_e64
247; GCN: v_nop_e64
248; GCN: v_nop_e64
249; GCN: v_nop_e64
250; GCN: ;;#ASMEND
251
252; GCN-NEXT: [[BB4]]: ; %bb4
253; GCN: v_mov_b32_e32 [[BB4_K:v[0-9]+]], 63
254; GCN: buffer_store_dword [[BB4_K]]
255; GCN-NEXT: s_endpgm
256; GCN-NEXT: .Lfunc_end{{[0-9]+}}:
257define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(i32 addrspace(1)* %arg, i32 %arg1) {
258bb0:
259  %tmp = icmp ne i32 %arg1, 0
260  br i1 %tmp, label %bb2, label %bb3
261
262bb2:
263  store volatile i32 17, i32 addrspace(1)* undef
264  br label %bb4
265
266bb3:
267  ; 32 byte asm
268  call void asm sideeffect
269   "v_nop_e64
270    v_nop_e64
271    v_nop_e64
272    v_nop_e64", ""() #0
273  br label %bb4
274
275bb4:
276  store volatile i32 63, i32 addrspace(1)* %arg
277  ret void
278}
279
280; GCN-LABEL: {{^}}uniform_unconditional_min_long_backward_branch:
281; GCN-NEXT: ; %bb.0: ; %entry
282
283; GCN-NEXT: [[LOOP:BB[0-9]_[0-9]+]]: ; %loop
284; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
285; GCN-NEXT: ;;#ASMSTART
286; GCN-NEXT: v_nop_e64
287; GCN-NEXT: v_nop_e64
288; GCN-NEXT: v_nop_e64
289; GCN-NEXT: v_nop_e64
290; GCN-NEXT: ;;#ASMEND
291
292; GCN-NEXT: [[LONGBB:BB[0-9]+_[0-9]+]]: ; %loop
293; GCN-NEXT: ; in Loop: Header=[[LOOP]] Depth=1
294
295; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
296; GCN-NEXT: s_sub_u32 s[[PC_LO]], s[[PC_LO]], ([[LONGBB]]+4)-[[LOOP]]
297; GCN-NEXT: s_subb_u32 s[[PC_HI]], s[[PC_HI]], 0{{$}}
298; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
299; GCN-NEXT: .Lfunc_end{{[0-9]+}}:
300define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(i32 addrspace(1)* %arg, i32 %arg1) {
301entry:
302  br label %loop
303
304loop:
305  ; 32 byte asm
306  call void asm sideeffect
307   "v_nop_e64
308    v_nop_e64
309    v_nop_e64
310    v_nop_e64", ""() #0
311  br label %loop
312}
313
314; Expansion of branch from %bb1 to %bb3 introduces need to expand
315; branch from %bb0 to %bb2
316
317; GCN-LABEL: {{^}}expand_requires_expand:
318; GCN-NEXT: ; %bb.0: ; %bb0
319; GCN: s_load_dword
320; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 0{{$}}
321; GCN-NEXT: s_cbranch_scc0 [[BB1:BB[0-9]+_[0-9]+]]
322
323; GCN-NEXT: [[LONGBB0:BB[0-9]+_[0-9]+]]: ; %bb0
324
325; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
326; GCN-NEXT: s_add_u32 s[[PC0_LO]], s[[PC0_LO]], [[BB2:BB[0-9]_[0-9]+]]-([[LONGBB0]]+4)
327; GCN-NEXT: s_addc_u32 s[[PC0_HI]], s[[PC0_HI]], 0{{$}}
328; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC0_LO]]:[[PC0_HI]]{{\]}}
329
330; GCN-NEXT: [[BB1]]: ; %bb1
331; GCN-NEXT: s_load_dword
332; GCN-NEXT: s_waitcnt lgkmcnt(0)
333; GCN-NEXT: s_cmp_eq_u32 s{{[0-9]+}}, 3{{$}}
334; GCN-NEXT: s_cbranch_scc0 [[BB2:BB[0-9]_[0-9]+]]
335
336; GCN-NEXT: [[LONGBB1:BB[0-9]+_[0-9]+]]: ; %bb1
337; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}}
338; GCN-NEXT: s_add_u32 s[[PC1_LO]], s[[PC1_LO]], [[BB3:BB[0-9]+_[0-9]+]]-([[LONGBB1]]+4)
339; GCN-NEXT: s_addc_u32 s[[PC1_HI]], s[[PC1_HI]], 0{{$}}
340; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC1_LO]]:[[PC1_HI]]{{\]}}
341
342; GCN-NEXT: [[BB2]]: ; %bb2
343; GCN-NEXT: ;;#ASMSTART
344; GCN-NEXT: v_nop_e64
345; GCN-NEXT: v_nop_e64
346; GCN-NEXT: v_nop_e64
347; GCN-NEXT: v_nop_e64
348; GCN-NEXT: ;;#ASMEND
349
350; GCN-NEXT: [[BB3]]: ; %bb3
351; GCN-NEXT: ;;#ASMSTART
352; GCN-NEXT: v_nop_e64
353; GCN-NEXT: ;;#ASMEND
354; GCN-NEXT: ;;#ASMSTART
355; GCN-NEXT: v_nop_e64
356; GCN-NEXT: ;;#ASMEND
357; GCN-NEXT: s_endpgm
358define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 {
359bb0:
360  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
361  %cmp0 = icmp slt i32 %cond0, 0
362  br i1 %cmp0, label %bb2, label %bb1
363
364bb1:
365  %val = load volatile i32, i32 addrspace(4)* undef
366  %cmp1 = icmp eq i32 %val, 3
367  br i1 %cmp1, label %bb3, label %bb2
368
369bb2:
370  call void asm sideeffect
371   "v_nop_e64
372    v_nop_e64
373    v_nop_e64
374    v_nop_e64", ""() #0
375  br label %bb3
376
377bb3:
378; These NOPs prevent tail-duplication-based outlining
379; from firing, which defeats the need to expand the branches and this test.
380  call void asm sideeffect
381   "v_nop_e64", ""() #0
382  call void asm sideeffect
383   "v_nop_e64", ""() #0
384  ret void
385}
386
387; Requires expanding of required skip branch.
388
389; GCN-LABEL: {{^}}uniform_inside_divergent:
390; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}}
391; GCN-NEXT: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
392; GCN-NEXT: s_cbranch_execnz [[IF:BB[0-9]+_[0-9]+]]
393
394; GCN-NEXT: [[LONGBB:BB[0-9]+_[0-9]+]]: ; %entry
395; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
396; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], [[BB2:BB[0-9]_[0-9]+]]-([[LONGBB]]+4)
397; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], 0{{$}}
398; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
399
400; GCN-NEXT: [[IF]]: ; %if
401; GCN: buffer_store_dword
402; GCN: s_cmp_lg_u32
403; GCN: s_cbranch_scc1 [[ENDIF:BB[0-9]+_[0-9]+]]
404
405; GCN-NEXT: ; %bb.2: ; %if_uniform
406; GCN: buffer_store_dword
407
408; GCN-NEXT: [[ENDIF]]: ; %endif
409; GCN-NEXT: s_or_b64 exec, exec, [[MASK]]
410; GCN-NEXT: s_sleep 5
411; GCN-NEXT: s_endpgm
412define amdgpu_kernel void @uniform_inside_divergent(i32 addrspace(1)* %out, i32 %cond) #0 {
413entry:
414  %tid = call i32 @llvm.amdgcn.workitem.id.x()
415  %d_cmp = icmp ult i32 %tid, 16
416  br i1 %d_cmp, label %if, label %endif
417
418if:
419  store i32 0, i32 addrspace(1)* %out
420  %u_cmp = icmp eq i32 %cond, 0
421  br i1 %u_cmp, label %if_uniform, label %endif
422
423if_uniform:
424  store i32 1, i32 addrspace(1)* %out
425  br label %endif
426
427endif:
428  ; layout can remove the split branch if it can copy the return block.
429  ; This call makes the return block long enough that it doesn't get copied.
430  call void @llvm.amdgcn.s.sleep(i32 5);
431  ret void
432}
433
434; si_mask_branch
435
436; GCN-LABEL: {{^}}analyze_mask_branch:
437; GCN: v_cmp_nlt_f32_e32 vcc
438; GCN-NEXT: s_and_saveexec_b64 [[TEMP_MASK:s\[[0-9]+:[0-9]+\]]], vcc
439; GCN-NEXT: s_xor_b64  [[MASK:s\[[0-9]+:[0-9]+\]]], exec, [[TEMP_MASK]]
440
441; GCN: BB{{[0-9]+_[0-9]+}}: ; %Flow
442; GCN-NEXT: s_or_saveexec_b64 [[TEMP_MASK1:s\[[0-9]+:[0-9]+\]]], [[MASK]]
443; GCN-NEXT: s_xor_b64 exec, exec, [[TEMP_MASK1]]
444
445; GCN: [[LOOP_BODY:BB[0-9]+_[0-9]+]]: ; %loop{{$}}
446; GCN: ;;#ASMSTART
447; GCN: v_nop_e64
448; GCN: v_nop_e64
449; GCN: v_nop_e64
450; GCN: v_nop_e64
451; GCN: v_nop_e64
452; GCN: v_nop_e64
453; GCN: ;;#ASMEND
454; GCN: s_cbranch_vccz [[RET:BB[0-9]+_[0-9]+]]
455
456; GCN-NEXT: [[LONGBB:BB[0-9]+_[0-9]+]]: ; %loop
457; GCN-NEXT: ; in Loop: Header=[[LOOP_BODY]] Depth=1
458; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
459; GCN-NEXT: s_sub_u32 s[[PC_LO]], s[[PC_LO]], ([[LONGBB]]+4)-[[LOOP_BODY]]
460; GCN-NEXT: s_subb_u32 s[[PC_HI]], s[[PC_HI]], 0
461; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
462
463; GCN-NEXT: [[RET]]: ; %UnifiedReturnBlock
464; GCN-NEXT: s_endpgm
465define amdgpu_kernel void @analyze_mask_branch() #0 {
466entry:
467  %reg = call float asm sideeffect "v_mov_b32_e64 $0, 0", "=v"()
468  %cmp0 = fcmp ogt float %reg, 0.000000e+00
469  br i1 %cmp0, label %loop, label %ret
470
471loop:
472  %phi = phi float [ 0.000000e+00, %loop_body ], [ 1.000000e+00, %entry ]
473  call void asm sideeffect
474    "v_nop_e64
475     v_nop_e64", ""() #0
476  %cmp1 = fcmp olt float %phi, 8.0
477  br i1 %cmp1, label %loop_body, label %ret
478
479loop_body:
480  call void asm sideeffect
481  "v_nop_e64
482   v_nop_e64
483   v_nop_e64
484   v_nop_e64", ""() #0
485  br label %loop
486
487ret:
488  store volatile i32 7, i32 addrspace(1)* undef
489  ret void
490}
491
492; GCN-LABEL: {{^}}long_branch_hang:
493; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 6
494; GCN: s_cbranch_scc0 [[LONG_BR_0:BB[0-9]+_[0-9]+]]
495; GCN-NEXT: BB{{[0-9]+_[0-9]+}}:
496
497; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, [[LONG_BR_DEST0:BB[0-9]+_[0-9]+]]-(
498; GCN-NEXT: s_addc_u32
499; GCN-NEXT: s_setpc_b64
500
501; GCN-NEXT: [[LONG_BR_0]]:
502; GCN-DAG: v_cmp_lt_i32
503; GCN-DAG: v_cmp_gt_i32
504; GCN: s_cbranch_vccnz
505
506; GCN: s_setpc_b64
507; GCN: s_setpc_b64
508
509; GCN: [[LONG_BR_DEST0]]
510; GCN: s_cbranch_vccz
511; GCN: s_setpc_b64
512
513; GCN: s_endpgm
514define amdgpu_kernel void @long_branch_hang(i32 addrspace(1)* nocapture %arg, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i64 %arg5) #0 {
515bb:
516  %tmp = icmp slt i32 %arg2, 9
517  %tmp6 = icmp eq i32 %arg1, 0
518  %tmp7 = icmp sgt i32 %arg4, 0
519  %tmp8 = icmp sgt i32 %arg4, 5
520  br i1 %tmp8, label %bb9, label %bb13
521
522bb9:                                              ; preds = %bb
523  %tmp10 = and i1 %tmp7, %tmp
524  %tmp11 = icmp slt i32 %arg3, %arg4
525  %tmp12 = or i1 %tmp11, %tmp7
526  br i1 %tmp12, label %bb19, label %bb14
527
528bb13:                                             ; preds = %bb
529  call void asm sideeffect
530  "v_nop_e64
531   v_nop_e64
532   v_nop_e64
533   v_nop_e64", ""() #0
534  br i1 %tmp6, label %bb19, label %bb14
535
536bb14:                                             ; preds = %bb13, %bb9
537  %tmp15 = icmp slt i32 %arg3, %arg4
538  %tmp16 = or i1 %tmp15, %tmp
539  %tmp17 = and i1 %tmp6, %tmp16
540  %tmp18 = zext i1 %tmp17 to i32
541  br label %bb19
542
543bb19:                                             ; preds = %bb14, %bb13, %bb9
544  %tmp20 = phi i32 [ undef, %bb9 ], [ undef, %bb13 ], [ %tmp18, %bb14 ]
545  %tmp21 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %arg5
546  store i32 %tmp20, i32 addrspace(1)* %tmp21, align 4
547  ret void
548}
549
550attributes #0 = { nounwind }
551attributes #1 = { nounwind readnone }
552