1; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=4 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
2
3
4; FIXME: We should use llvm-mc for this, but we can't even parse our own output.
5;        See PR33579.
6; RUN: llc -march=amdgcn -verify-machineinstrs -amdgpu-s-branch-bits=4 -o %t.o -filetype=obj -simplifycfg-require-and-preserve-domtree=1 %s
7; RUN: llvm-readobj -r %t.o | FileCheck --check-prefix=OBJ %s
8
9; OBJ:       Relocations [
10; OBJ-NEXT: ]
11
12; Restrict maximum branch to between +7 and -8 dwords
13
14; Used to emit an always 4 byte instruction. Inline asm always assumes
15; each instruction is the maximum size.
16declare void @llvm.amdgcn.s.sleep(i32) #0
17
18declare i32 @llvm.amdgcn.workitem.id.x() #1
19
20
21; GCN-LABEL: {{^}}uniform_conditional_max_short_forward_branch:
22; GCN: s_load_dword [[CND:s[0-9]+]]
23; GCN: s_cmp_eq_u32 [[CND]], 0
24; GCN-NEXT: s_cbranch_scc1 [[BB3:.LBB[0-9]+_[0-9]+]]
25
26
27; GCN-NEXT: ; %bb.1: ; %bb2
28; GCN-NEXT: ;;#ASMSTART
29; GCN-NEXT: v_nop_e64
30; GCN-NEXT: v_nop_e64
31; GCN-NEXT: v_nop_e64
32; GCN-NEXT: ;;#ASMEND
33; GCN-NEXT: s_sleep 0
34
35; GCN-NEXT: [[BB3]]: ; %bb3
36; GCN: v_mov_b32_e32 [[V_CND:v[0-9]+]], [[CND]]
37; GCN: buffer_store_dword [[V_CND]]
38; GCN: s_endpgm
39define amdgpu_kernel void @uniform_conditional_max_short_forward_branch(i32 addrspace(1)* %arg, i32 %cnd) #0 {
40bb:
41  %cmp = icmp eq i32 %cnd, 0
42  br i1 %cmp, label %bb3, label %bb2 ; +8 dword branch
43
44bb2:
45; 24 bytes
46  call void asm sideeffect
47   "v_nop_e64
48    v_nop_e64
49    v_nop_e64", ""() #0
50  call void @llvm.amdgcn.s.sleep(i32 0)
51  br label %bb3
52
53bb3:
54  store volatile i32 %cnd, i32 addrspace(1)* %arg
55  ret void
56}
57
58; GCN-LABEL: {{^}}uniform_conditional_min_long_forward_branch:
59; GCN: s_load_dword [[CND:s[0-9]+]]
60; GCN: s_cmp_eq_u32 [[CND]], 0
61; GCN-NEXT: s_cbranch_scc0 [[LONGBB:.LBB[0-9]+_[0-9]+]]
62
63; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %bb0
64; GCN-NEXT: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
65; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
66; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[ENDBB:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295
67; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[ENDBB]]-[[POST_GETPC]])>>32
68; GCN-NEXT: s_setpc_b64 s[[[PC_LO]]:[[PC_HI]]]
69
70; GCN-NEXT: [[LONGBB]]:
71; GCN-NEXT: ;;#ASMSTART
72; GCN: v_nop_e64
73; GCN: v_nop_e64
74; GCN: v_nop_e64
75; GCN: v_nop_e64
76; GCN-NEXT: ;;#ASMEND
77
78; GCN-NEXT: [[ENDBB]]:
79; GCN: v_mov_b32_e32 [[V_CND:v[0-9]+]], [[CND]]
80; GCN: buffer_store_dword [[V_CND]]
81; GCN: s_endpgm
82define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(i32 addrspace(1)* %arg, i32 %cnd) #0 {
83bb0:
84  %cmp = icmp eq i32 %cnd, 0
85  br i1 %cmp, label %bb3, label %bb2 ; +9 dword branch
86
87bb2:
88; 32 bytes
89  call void asm sideeffect
90   "v_nop_e64
91    v_nop_e64
92    v_nop_e64
93    v_nop_e64", ""() #0
94  br label %bb3
95
96bb3:
97  store volatile i32 %cnd, i32 addrspace(1)* %arg
98  ret void
99}
100
101; GCN-LABEL: {{^}}uniform_conditional_min_long_forward_vcnd_branch:
102; GCN: s_load_dword [[CND:s[0-9]+]]
103
104; GCN-DAG: v_cmp_eq_f32_e64 [[UNMASKED:s\[[0-9]+:[0-9]+\]]], [[CND]], 0
105; GCN-DAG: s_and_b64 vcc, exec, [[UNMASKED]]
106; GCN: s_cbranch_vccz [[LONGBB:.LBB[0-9]+_[0-9]+]]
107
108; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %bb0
109; GCN-NEXT: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
110; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
111; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[ENDBB:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295
112; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[ENDBB]]-[[POST_GETPC]])>>32
113; GCN-NEXT: s_setpc_b64 s[[[PC_LO]]:[[PC_HI]]]
114
115; GCN-NEXT: [[LONGBB]]:
116; GCN: v_nop_e64
117; GCN: v_nop_e64
118; GCN: v_nop_e64
119; GCN: v_nop_e64
120
121; GCN: [[ENDBB]]:
122; GCN: v_mov_b32_e32 [[V_CND:v[0-9]+]], [[CND]]
123; GCN: buffer_store_dword [[V_CND]]
124; GCN: s_endpgm
125define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(float addrspace(1)* %arg, float %cnd) #0 {
126bb0:
127  %cmp = fcmp oeq float %cnd, 0.0
128  br i1 %cmp, label %bb3, label %bb2 ; + 8 dword branch
129
130bb2:
131  call void asm sideeffect " ; 32 bytes
132    v_nop_e64
133    v_nop_e64
134    v_nop_e64
135    v_nop_e64", ""() #0
136  br label %bb3
137
138bb3:
139  store volatile float %cnd, float addrspace(1)* %arg
140  ret void
141}
142
143; GCN-LABEL: {{^}}min_long_forward_vbranch:
144
145; GCN: buffer_load_dword
146; GCN: v_cmp_ne_u32_e32 vcc, 0, v{{[0-9]+}}
147; GCN: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], vcc
148
149; GCN: v_nop_e64
150; GCN: v_nop_e64
151; GCN: v_nop_e64
152; GCN: v_nop_e64
153
154; GCN: s_or_b64 exec, exec, [[SAVE]]
155; GCN: buffer_store_dword
156; GCN: s_endpgm
157define amdgpu_kernel void @min_long_forward_vbranch(i32 addrspace(1)* %arg) #0 {
158bb:
159  %tid = call i32 @llvm.amdgcn.workitem.id.x()
160  %tid.ext = zext i32 %tid to i64
161  %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tid.ext
162  %load = load volatile i32, i32 addrspace(1)* %gep
163  %cmp = icmp eq i32 %load, 0
164  br i1 %cmp, label %bb3, label %bb2 ; + 8 dword branch
165
166bb2:
167  call void asm sideeffect " ; 32 bytes
168    v_nop_e64
169    v_nop_e64
170    v_nop_e64
171    v_nop_e64", ""() #0
172  br label %bb3
173
174bb3:
175  store volatile i32 %load, i32 addrspace(1)* %gep
176  ret void
177}
178
179; GCN-LABEL: {{^}}long_backward_sbranch:
180; GCN: s_mov_b32 [[LOOPIDX:s[0-9]+]], 0{{$}}
181
182; GCN: .L[[LOOPBB:BB[0-9]+_[0-9]+]]: ; %bb2
183; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
184; GCN-NEXT: s_add_i32 [[INC:s[0-9]+]], [[LOOPIDX]], 1
185; GCN-NEXT: s_cmp_lt_i32 [[INC]], 10
186
187; GCN-NEXT: ;;#ASMSTART
188; GCN-NEXT: v_nop_e64
189; GCN-NEXT: v_nop_e64
190; GCN-NEXT: v_nop_e64
191; GCN-NEXT: ;;#ASMEND
192
193; GCN-NEXT: s_cbranch_scc0 [[ENDBB:.LBB[0-9]+_[0-9]+]]
194
195; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %bb2
196; GCN-NEXT: ; in Loop: Header=[[LOOPBB]] Depth=1
197
198; GCN-NEXT: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
199; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
200; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], (.L[[LOOPBB]]-[[POST_GETPC]])&4294967295
201; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], (.L[[LOOPBB]]-[[POST_GETPC]])>>32
202; GCN-NEXT: s_setpc_b64 s[[[PC_LO]]:[[PC_HI]]]
203
204; GCN-NEXT: [[ENDBB]]:
205; GCN-NEXT: s_endpgm
206define amdgpu_kernel void @long_backward_sbranch(i32 addrspace(1)* %arg) #0 {
207bb:
208  br label %bb2
209
210bb2:
211  %loop.idx = phi i32 [ 0, %bb ], [ %inc, %bb2 ]
212   ; 24 bytes
213  call void asm sideeffect
214   "v_nop_e64
215    v_nop_e64
216    v_nop_e64", ""() #0
217  %inc = add nsw i32 %loop.idx, 1 ; add cost 4
218  %cmp = icmp slt i32 %inc, 10 ; condition cost = 8
219  br i1 %cmp, label %bb2, label %bb3 ; -
220
221bb3:
222  ret void
223}
224
225; Requires expansion of unconditional branch from %bb2 to %bb4 (and
226; expansion of conditional branch from %bb to %bb3.
227
228; GCN-LABEL: {{^}}uniform_unconditional_min_long_forward_branch:
229; GCN: s_cmp_eq_u32
230; GCN: s_cbranch_scc{{[0-1]}} [[BB1:.LBB[0-9]+_[0-9]+]]
231
232; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %bb0
233; GCN-NEXT: s_getpc_b64 s[[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]]
234; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
235; GCN-NEXT: s_add_u32 s[[PC0_LO]], s[[PC0_LO]], ([[BB4:.LBB[0-9]_[0-9]+]]-[[POST_GETPC]])&4294967295
236; GCN-NEXT: s_addc_u32 s[[PC0_HI]], s[[PC0_HI]], ([[BB4]]-[[POST_GETPC]])>>32
237; GCN-NEXT: s_setpc_b64 s[[[PC0_LO]]:[[PC0_HI]]]
238
239; GCN: [[BB1]]:
240; GCN: v_mov_b32_e32 [[BB2_K:v[0-9]+]], 17
241; GCN: buffer_store_dword [[BB2_K]]
242
243; GCN: v_mov_b32_e32 [[BB4_K:v[0-9]+]], 63
244; GCN: buffer_store_dword [[BB4_K]]
245; GCN: s_endpgm
246
247; GCN: [[BB4]]: ; %bb3
248; GCN: v_nop_e64
249; GCN: v_nop_e64
250; GCN: v_nop_e64
251; GCN: v_nop_e64
252; GCN: ;;#ASMEND
253
254; GCN: .Lfunc_end{{[0-9]+}}:
255define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(i32 addrspace(1)* %arg, i32 %arg1) {
256bb0:
257  %tmp = icmp ne i32 %arg1, 0
258  br i1 %tmp, label %bb2, label %bb3
259
260bb2:
261  store volatile i32 17, i32 addrspace(1)* undef
262  br label %bb4
263
264bb3:
265  ; 32 byte asm
266  call void asm sideeffect
267   "v_nop_e64
268    v_nop_e64
269    v_nop_e64
270    v_nop_e64", ""() #0
271  br label %bb4
272
273bb4:
274  store volatile i32 63, i32 addrspace(1)* %arg
275  ret void
276}
277
278; GCN-LABEL: {{^}}uniform_unconditional_min_long_backward_branch:
279; GCN-NEXT: ; %bb.0: ; %entry
280
281; GCN-NEXT: .L[[LOOP:BB[0-9]_[0-9]+]]: ; %loop
282; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
283; GCN-NEXT: ;;#ASMSTART
284; GCN-NEXT: v_nop_e64
285; GCN-NEXT: v_nop_e64
286; GCN-NEXT: v_nop_e64
287; GCN-NEXT: v_nop_e64
288; GCN-NEXT: ;;#ASMEND
289
290; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %loop
291; GCN-NEXT: ; in Loop: Header=[[LOOP]] Depth=1
292
293; GCN-NEXT: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
294; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
295; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], (.L[[LOOP]]-[[POST_GETPC]])&4294967295
296; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], (.L[[LOOP]]-[[POST_GETPC]])>>32
297; GCN-NEXT: s_setpc_b64 s[[[PC_LO]]:[[PC_HI]]]
298; GCN-NEXT: .Lfunc_end{{[0-9]+}}:
299define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(i32 addrspace(1)* %arg, i32 %arg1) {
300entry:
301  br label %loop
302
303loop:
304  ; 32 byte asm
305  call void asm sideeffect
306   "v_nop_e64
307    v_nop_e64
308    v_nop_e64
309    v_nop_e64", ""() #0
310  br label %loop
311}
312
313; Expansion of branch from %bb1 to %bb3 introduces need to expand
314; branch from %bb0 to %bb2
315
316; GCN-LABEL: {{^}}expand_requires_expand:
317; GCN-NEXT: ; %bb.0: ; %bb0
318; GCN: s_load_dword
319; GCN: {{s|v}}_cmp_lt_i32
320; GCN: s_cbranch
321
322; GCN: s_load_dword
323; GCN-NEXT: s_waitcnt lgkmcnt(0)
324; GCN-NEXT: s_cmp_lg_u32
325; GCN-NEXT: s_cselect_b64
326; GCN: s_cbranch_vccz [[BB2:.LBB[0-9]_[0-9]+]]
327
328; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}:
329; GCN-NEXT: s_getpc_b64 s[[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]]
330; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
331; GCN-NEXT: s_add_u32 s[[PC1_LO]], s[[PC1_LO]], ([[BB3:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295
332; GCN-NEXT: s_addc_u32 s[[PC1_HI]], s[[PC1_HI]], ([[BB3:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])>>32
333; GCN-NEXT: s_setpc_b64 s[[[PC1_LO]]:[[PC1_HI]]]
334
335; GCN-NEXT: [[BB2]]: ; %bb2
336; GCN-NEXT: ;;#ASMSTART
337; GCN-NEXT: v_nop_e64
338; GCN-NEXT: v_nop_e64
339; GCN-NEXT: v_nop_e64
340; GCN-NEXT: v_nop_e64
341; GCN-NEXT: ;;#ASMEND
342
343; GCN-NEXT: [[BB3]]: ; %bb3
344; GCN-NEXT: ;;#ASMSTART
345; GCN-NEXT: v_nop_e64
346; GCN-NEXT: ;;#ASMEND
347; GCN-NEXT: ;;#ASMSTART
348; GCN-NEXT: v_nop_e64
349; GCN-NEXT: ;;#ASMEND
350; GCN-NEXT: s_endpgm
351define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 {
352bb0:
353  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
354  %cmp0 = icmp slt i32 %cond0, 0
355  br i1 %cmp0, label %bb2, label %bb1
356
357bb1:
358  %val = load volatile i32, i32 addrspace(4)* undef
359  %cmp1 = icmp eq i32 %val, 3
360  br i1 %cmp1, label %bb3, label %bb2
361
362bb2:
363  call void asm sideeffect
364   "v_nop_e64
365    v_nop_e64
366    v_nop_e64
367    v_nop_e64", ""() #0
368  br label %bb3
369
370bb3:
371; These NOPs prevent tail-duplication-based outlining
372; from firing, which defeats the need to expand the branches and this test.
373  call void asm sideeffect
374   "v_nop_e64", ""() #0
375  call void asm sideeffect
376   "v_nop_e64", ""() #0
377  ret void
378}
379
380; Requires expanding of required skip branch.
381
382; GCN-LABEL: {{^}}uniform_inside_divergent:
383; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}}
384; GCN-NEXT: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
385; GCN-NEXT: s_cbranch_execnz [[IF:.LBB[0-9]+_[0-9]+]]
386
387; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %entry
388; GCN-NEXT: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
389; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
390; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[BB2:.LBB[0-9]_[0-9]+]]-[[POST_GETPC]])&4294967295
391; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[BB2:.LBB[0-9]_[0-9]+]]-[[POST_GETPC]])>>32
392; GCN-NEXT: s_setpc_b64 s[[[PC_LO]]:[[PC_HI]]]
393
394; GCN-NEXT: [[IF]]: ; %if
395; GCN: s_cmp_lg_u32
396; GCN: s_cbranch_scc1 [[ENDIF:.LBB[0-9]+_[0-9]+]]
397
398; GCN-NEXT: ; %bb.2: ; %if_uniform
399; GCN: buffer_store_dword
400
401; GCN-NEXT: [[ENDIF]]: ; %endif
402; GCN-NEXT: s_or_b64 exec, exec, [[MASK]]
403; GCN-NEXT: s_sleep 5
404; GCN-NEXT: s_endpgm
405define amdgpu_kernel void @uniform_inside_divergent(i32 addrspace(1)* %out, i32 %cond) #0 {
406entry:
407  %tid = call i32 @llvm.amdgcn.workitem.id.x()
408  %d_cmp = icmp ult i32 %tid, 16
409  br i1 %d_cmp, label %if, label %endif
410
411if:
412  store i32 0, i32 addrspace(1)* %out
413  %u_cmp = icmp eq i32 %cond, 0
414  br i1 %u_cmp, label %if_uniform, label %endif
415
416if_uniform:
417  store i32 1, i32 addrspace(1)* %out
418  br label %endif
419
420endif:
421  ; layout can remove the split branch if it can copy the return block.
422  ; This call makes the return block long enough that it doesn't get copied.
423  call void @llvm.amdgcn.s.sleep(i32 5);
424  ret void
425}
426
427; si_mask_branch
428
429; GCN-LABEL: {{^}}analyze_mask_branch:
430; GCN: v_cmp_nlt_f32_e32 vcc
431; GCN-NEXT: s_and_saveexec_b64 [[TEMP_MASK:s\[[0-9]+:[0-9]+\]]], vcc
432; GCN-NEXT: s_xor_b64  [[MASK:s\[[0-9]+:[0-9]+\]]], exec, [[TEMP_MASK]]
433
434; GCN: .LBB{{[0-9]+_[0-9]+}}: ; %Flow1
435; GCN-NEXT: s_andn2_saveexec_b64 [[MASK]], [[MASK]]
436; GCN-NEXT: s_cbranch_execnz
437
438; GCN: .L[[LOOP_BODY:BB[0-9]+_[0-9]+]]: ; %loop{{$}}
439; GCN: ;;#ASMSTART
440; GCN: v_nop_e64
441; GCN: v_nop_e64
442; GCN: v_nop_e64
443; GCN: v_nop_e64
444; GCN: v_nop_e64
445; GCN: v_nop_e64
446; GCN: ;;#ASMEND
447; GCN: s_cbranch_{{vccz|vccnz}} [[RET:.LBB[0-9]+_[0-9]+]]
448
449; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %loop
450; GCN-NEXT: ; in Loop: Header=[[LOOP_BODY]] Depth=1
451; GCN-NEXT: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
452; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
453; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], (.L[[LOOP_BODY]]-[[POST_GETPC]])&4294967295
454; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], (.L[[LOOP_BODY]]-[[POST_GETPC]])>>32
455; GCN-NEXT: s_setpc_b64 s[[[PC_LO]]:[[PC_HI]]]
456
457; GCN-NEXT: [[RET]]: ; %UnifiedReturnBlock
458; GCN-NEXT: s_endpgm
459define amdgpu_kernel void @analyze_mask_branch() #0 {
460entry:
461  %reg = call float asm sideeffect "v_mov_b32_e64 $0, 0", "=v"()
462  %cmp0 = fcmp ogt float %reg, 0.000000e+00
463  br i1 %cmp0, label %loop, label %ret
464
465loop:
466  %phi = phi float [ 0.000000e+00, %loop_body ], [ 1.000000e+00, %entry ]
467  call void asm sideeffect
468    "v_nop_e64
469     v_nop_e64", ""() #0
470  %cmp1 = fcmp olt float %phi, 8.0
471  br i1 %cmp1, label %loop_body, label %ret
472
473loop_body:
474  call void asm sideeffect
475  "v_nop_e64
476   v_nop_e64
477   v_nop_e64
478   v_nop_e64", ""() #0
479  br label %loop
480
481ret:
482  store volatile i32 7, i32 addrspace(1)* undef
483  ret void
484}
485
486; GCN-LABEL: {{^}}long_branch_hang:
487; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 6
488; GCN: s_cbranch_scc{{[0-1]}} [[LONG_BR_0:.LBB[0-9]+_[0-9]+]]
489; GCN-NEXT: BB{{[0-9]+_[0-9]+}}:
490
491; GCN: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
492; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
493; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[LONG_BR_DEST0:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295
494; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[LONG_BR_DEST0]]-[[POST_GETPC]])>>32
495; GCN-NEXT: s_setpc_b64 s[[[PC_LO]]:[[PC_HI]]]
496; GCN-NEXT: [[LONG_BR_0]]:
497
498; GCN: [[LONG_BR_DEST0]]:
499
500; GCN-DAG: s_cmp_lt_i32
501; GCN-DAG: s_cmp_ge_i32
502
503; GCN: s_cbranch_vccz
504; GCN: s_setpc_b64
505
506; GCN: s_endpgm
507define amdgpu_kernel void @long_branch_hang(i32 addrspace(1)* nocapture %arg, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i64 %arg5) #0 {
508bb:
509  %tmp = icmp slt i32 %arg2, 9
510  %tmp6 = icmp eq i32 %arg1, 0
511  %tmp8 = icmp sgt i32 %arg4, 5
512  br i1 %tmp8, label %bb9, label %bb13
513
514bb9:                                              ; preds = %bb
515  %tmp7 = icmp sgt i32 %arg4, 0
516  %tmp10 = and i1 %tmp7, %tmp
517  %tmp11 = icmp slt i32 %arg3, %arg4
518  %tmp12 = or i1 %tmp11, %tmp7
519  br i1 %tmp12, label %bb19, label %bb14
520
521bb13:                                             ; preds = %bb
522  call void asm sideeffect
523  "v_nop_e64
524   v_nop_e64
525   v_nop_e64
526   v_nop_e64", ""() #0
527  br i1 %tmp6, label %bb19, label %bb14
528
529bb14:                                             ; preds = %bb13, %bb9
530  %tmp15 = icmp slt i32 %arg3, %arg4
531  %tmp16 = or i1 %tmp15, %tmp
532  %tmp17 = and i1 %tmp6, %tmp16
533  %tmp18 = zext i1 %tmp17 to i32
534  br label %bb19
535
536bb19:                                             ; preds = %bb14, %bb13, %bb9
537  %tmp20 = phi i32 [ undef, %bb9 ], [ undef, %bb13 ], [ %tmp18, %bb14 ]
538  %tmp21 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %arg5
539  store i32 %tmp20, i32 addrspace(1)* %tmp21, align 4
540  ret void
541}
542
543attributes #0 = { nounwind }
544attributes #1 = { nounwind readnone }
545