1; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
2; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
3
4; GCN-LABEL: {{^}}br_cc_f16:
5; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
6; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
7
8; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
9; SI:  v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
10; SI:  v_cmp_nlt_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
11; VI:  v_cmp_nlt_f16_e32 vcc, v[[A_F16]], v[[B_F16]]
12; GCN: s_cbranch_vccnz
13
14; GCN: one{{$}}
15; SI: v_cvt_f16_f32_e32 v[[A_F16:[0-9]+]], v[[A_F32]]
16; GCN: buffer_store_short
17; GCN: s_endpgm
18
19; GCN: two{{$}}
20; SI:  v_cvt_f16_f32_e32 v[[B_F16:[0-9]+]], v[[B_F32]]
21; GCN: buffer_store_short v[[B_F16]]
22; GCN: s_endpgm
23define amdgpu_kernel void @br_cc_f16(
24    half addrspace(1)* %r,
25    half addrspace(1)* %a,
26    half addrspace(1)* %b) {
27entry:
28  %a.val = load half, half addrspace(1)* %a
29  %b.val = load half, half addrspace(1)* %b
30  %fcmp = fcmp olt half %a.val, %b.val
31  br i1 %fcmp, label %one, label %two
32
33one:
34  store half %a.val, half addrspace(1)* %r
35  ret void
36
37two:
38  store half %b.val, half addrspace(1)* %r
39  ret void
40}
41
42; GCN-LABEL: {{^}}br_cc_f16_imm_a:
43; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
44
45; SI:  v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
46; SI:  v_cmp_nlt_f32_e32 vcc, 0.5, v[[B_F32]]
47; SI: s_cbranch_vccnz
48
49; VI:  v_cmp_nlt_f16_e32 vcc, 0.5, v[[B_F16]]
50; VI: s_cbranch_vccnz
51
52; GCN: one{{$}}
53; VI: v_mov_b32_e32 v[[A_F16:[0-9]+]], 0x380{{0|1}}{{$}}
54
55; SI: buffer_store_short v[[A_F16]]
56; SI: s_endpgm
57
58
59; GCN: two{{$}}
60; SI:  v_cvt_f16_f32_e32 v[[B_F16:[0-9]+]], v[[B_F32]]
61
62define amdgpu_kernel void @br_cc_f16_imm_a(
63    half addrspace(1)* %r,
64    half addrspace(1)* %b) {
65entry:
66  %b.val = load half, half addrspace(1)* %b
67  %fcmp = fcmp olt half 0xH3800, %b.val
68  br i1 %fcmp, label %one, label %two
69
70one:
71  store half 0xH3800, half addrspace(1)* %r
72  ret void
73
74two:
75  store half %b.val, half addrspace(1)* %r
76  ret void
77}
78
79; GCN-LABEL: {{^}}br_cc_f16_imm_b:
80; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
81
82; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
83; SI:  v_cmp_ngt_f32_e32 vcc, 0.5, v[[A_F32]]
84
85; VI:  v_cmp_ngt_f16_e32 vcc, 0.5, v[[A_F16]]
86; GCN: s_cbranch_vccnz
87
88; GCN: one{{$}}
89; SI:  v_cvt_f16_f32_e32 v[[A_F16:[0-9]+]], v[[A_F32]]
90
91; GCN: two{{$}}
92; VI:  v_mov_b32_e32 v[[B_F16:[0-9]+]], 0x3800{{$}}
93; GCN: buffer_store_short v[[B_F16]]
94; GCN: s_endpgm
95define amdgpu_kernel void @br_cc_f16_imm_b(
96    half addrspace(1)* %r,
97    half addrspace(1)* %a) {
98entry:
99  %a.val = load half, half addrspace(1)* %a
100  %fcmp = fcmp olt half %a.val, 0xH3800
101  br i1 %fcmp, label %one, label %two
102
103one:
104  store half %a.val, half addrspace(1)* %r
105  ret void
106
107two:
108  store half 0xH3800, half addrspace(1)* %r
109  ret void
110}
111