1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
2; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
3
4; GCN-LABEL: {{^}}br_cc_f16
5; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
6; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
7
8; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
9; SI:  v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
10; SI:  v_cmp_nlt_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
11; VI:  v_cmp_nlt_f16_e32 vcc, v[[A_F16]], v[[B_F16]]
12; GCN: s_cbranch_vccnz
13
14; GCN: one{{$}}
15; SI: v_cvt_f16_f32_e32 v[[A_F16:[0-9]+]], v[[A_F32]]
16; SI: s_branch
17; VI: buffer_store_short
18; VI: s_endpgm
19
20; GCN: two{{$}}
21; SI:  v_cvt_f16_f32_e32 v[[B_F16:[0-9]+]], v[[B_F32]]
22; GCN: buffer_store_short v[[B_F16]]
23; GCN: s_endpgm
24define void @br_cc_f16(
25    half addrspace(1)* %r,
26    half addrspace(1)* %a,
27    half addrspace(1)* %b) {
28entry:
29  %a.val = load half, half addrspace(1)* %a
30  %b.val = load half, half addrspace(1)* %b
31  %fcmp = fcmp olt half %a.val, %b.val
32  br i1 %fcmp, label %one, label %two
33
34one:
35  store half %a.val, half addrspace(1)* %r
36  ret void
37
38two:
39  store half %b.val, half addrspace(1)* %r
40  ret void
41}
42
43; GCN-LABEL: {{^}}br_cc_f16_imm_a
44; SI: v_mov_b32_e32 v[[A_F16:[0-9]+]], 0x3800{{$}}
45; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
46; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
47
48; SI:  v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
49; SI:  v_cmp_ngt_f32_e32 vcc, v[[B_F32]], v[[A_F32]]
50; SI: s_cbranch_vccz
51
52; VI:  v_cmp_nlt_f16_e32 vcc, 0.5, v[[B_F16]]
53; VI: s_cbranch_vccnz
54
55; VI: one{{$}}
56; VI: v_mov_b32_e32 v[[A_F16:[0-9]+]], 0x380{{0|1}}{{$}}
57
58; GCN: two{{$}}
59; SI:  v_cvt_f16_f32_e32 v[[B_F16:[0-9]+]], v[[B_F32]]
60
61; SI: one{{$}}
62; SI: buffer_store_short v[[A_F16]]
63; SI: s_endpgm
64
65define void @br_cc_f16_imm_a(
66    half addrspace(1)* %r,
67    half addrspace(1)* %b) {
68entry:
69  %b.val = load half, half addrspace(1)* %b
70  %fcmp = fcmp olt half 0xH3800, %b.val
71  br i1 %fcmp, label %one, label %two
72
73one:
74  store half 0xH3800, half addrspace(1)* %r
75  ret void
76
77two:
78  store half %b.val, half addrspace(1)* %r
79  ret void
80}
81
82; GCN-LABEL: {{^}}br_cc_f16_imm_b
83; SI: v_mov_b32_e32 v[[B_F16:[0-9]+]], 0x3800{{$}}
84; SI:  v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
85; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
86
87; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
88; SI:  v_cmp_nlt_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
89; VI:  v_cmp_ngt_f16_e32 vcc, 0.5, v[[A_F16]]
90; GCN: s_cbranch_vccnz
91
92; GCN: one{{$}}
93; SI:  v_cvt_f16_f32_e32 v[[A_F16:[0-9]+]], v[[A_F32]]
94
95; GCN: two{{$}}
96; VI:  v_mov_b32_e32 v[[B_F16:[0-9]+]], 0x3800{{$}}
97; GCN: buffer_store_short v[[B_F16]]
98; GCN: s_endpgm
99define void @br_cc_f16_imm_b(
100    half addrspace(1)* %r,
101    half addrspace(1)* %a) {
102entry:
103  %a.val = load half, half addrspace(1)* %a
104  %fcmp = fcmp olt half %a.val, 0xH3800
105  br i1 %fcmp, label %one, label %two
106
107one:
108  store half %a.val, half addrspace(1)* %r
109  ret void
110
111two:
112  store half 0xH3800, half addrspace(1)* %r
113  ret void
114}
115