1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=amdgcn-- -verify-machineinstrs | FileCheck %s --check-prefixes=FUNC,SI
3; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=FUNC,FLAT,TONGA
4; RUN: llc < %s -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=FUNC,FLAT,VI
5
6declare i32 @llvm.amdgcn.workitem.id.x() #1
7
8declare i16 @llvm.bitreverse.i16(i16) #1
9declare i32 @llvm.bitreverse.i32(i32) #1
10declare i64 @llvm.bitreverse.i64(i64) #1
11
12declare <2 x i32> @llvm.bitreverse.v2i32(<2 x i32>) #1
13declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>) #1
14
15declare <2 x i64> @llvm.bitreverse.v2i64(<2 x i64>) #1
16declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>) #1
17
18define amdgpu_kernel void @s_brev_i16(i16 addrspace(1)* noalias %out, i16 %val) #0 {
19; SI-LABEL: s_brev_i16:
20; SI:       ; %bb.0:
21; SI-NEXT:    s_load_dword s2, s[0:1], 0xb
22; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
23; SI-NEXT:    s_mov_b32 s3, 0xf000
24; SI-NEXT:    s_waitcnt lgkmcnt(0)
25; SI-NEXT:    s_brev_b32 s2, s2
26; SI-NEXT:    s_lshr_b32 s4, s2, 16
27; SI-NEXT:    s_mov_b32 s2, -1
28; SI-NEXT:    v_mov_b32_e32 v0, s4
29; SI-NEXT:    buffer_store_short v0, off, s[0:3], 0
30; SI-NEXT:    s_endpgm
31;
32; FLAT-LABEL: s_brev_i16:
33; FLAT:       ; %bb.0:
34; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
35; FLAT-NEXT:    s_load_dword s0, s[0:1], 0x2c
36; FLAT-NEXT:    s_mov_b32 s7, 0xf000
37; FLAT-NEXT:    s_mov_b32 s6, -1
38; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
39; FLAT-NEXT:    s_and_b32 s0, s0, 0xffff
40; FLAT-NEXT:    s_brev_b32 s0, s0
41; FLAT-NEXT:    s_lshr_b32 s0, s0, 16
42; FLAT-NEXT:    v_mov_b32_e32 v0, s0
43; FLAT-NEXT:    buffer_store_short v0, off, s[4:7], 0
44; FLAT-NEXT:    s_endpgm
45  %brev = call i16 @llvm.bitreverse.i16(i16 %val) #1
46  store i16 %brev, i16 addrspace(1)* %out
47  ret void
48}
49
50define amdgpu_kernel void @v_brev_i16(i16 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %valptr) #0 {
51; SI-LABEL: v_brev_i16:
52; SI:       ; %bb.0:
53; SI-NEXT:    s_mov_b32 s3, 0xf000
54; SI-NEXT:    s_mov_b32 s2, -1
55; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
56; SI-NEXT:    s_mov_b32 s6, s2
57; SI-NEXT:    s_mov_b32 s7, s3
58; SI-NEXT:    s_waitcnt lgkmcnt(0)
59; SI-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
60; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
61; SI-NEXT:    s_waitcnt vmcnt(0)
62; SI-NEXT:    v_bfrev_b32_e32 v0, v0
63; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
64; SI-NEXT:    s_waitcnt lgkmcnt(0)
65; SI-NEXT:    buffer_store_short v0, off, s[0:3], 0
66; SI-NEXT:    s_endpgm
67;
68; FLAT-LABEL: v_brev_i16:
69; FLAT:       ; %bb.0:
70; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
71; FLAT-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
72; FLAT-NEXT:    s_mov_b32 s7, 0xf000
73; FLAT-NEXT:    s_mov_b32 s6, -1
74; FLAT-NEXT:    s_mov_b32 s2, s6
75; FLAT-NEXT:    s_mov_b32 s3, s7
76; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
77; FLAT-NEXT:    buffer_load_ushort v0, off, s[0:3], 0
78; FLAT-NEXT:    s_waitcnt vmcnt(0)
79; FLAT-NEXT:    v_bfrev_b32_e32 v0, v0
80; FLAT-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
81; FLAT-NEXT:    buffer_store_short v0, off, s[4:7], 0
82; FLAT-NEXT:    s_endpgm
83  %val = load i16, i16 addrspace(1)* %valptr
84  %brev = call i16 @llvm.bitreverse.i16(i16 %val) #1
85  store i16 %brev, i16 addrspace(1)* %out
86  ret void
87}
88
89define amdgpu_kernel void @s_brev_i32(i32 addrspace(1)* noalias %out, i32 %val) #0 {
90; SI-LABEL: s_brev_i32:
91; SI:       ; %bb.0:
92; SI-NEXT:    s_load_dword s2, s[0:1], 0xb
93; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
94; SI-NEXT:    s_mov_b32 s3, 0xf000
95; SI-NEXT:    s_waitcnt lgkmcnt(0)
96; SI-NEXT:    s_brev_b32 s4, s2
97; SI-NEXT:    s_mov_b32 s2, -1
98; SI-NEXT:    v_mov_b32_e32 v0, s4
99; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
100; SI-NEXT:    s_endpgm
101;
102; FLAT-LABEL: s_brev_i32:
103; FLAT:       ; %bb.0:
104; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
105; FLAT-NEXT:    s_load_dword s0, s[0:1], 0x2c
106; FLAT-NEXT:    s_mov_b32 s7, 0xf000
107; FLAT-NEXT:    s_mov_b32 s6, -1
108; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
109; FLAT-NEXT:    s_brev_b32 s0, s0
110; FLAT-NEXT:    v_mov_b32_e32 v0, s0
111; FLAT-NEXT:    buffer_store_dword v0, off, s[4:7], 0
112; FLAT-NEXT:    s_endpgm
113  %brev = call i32 @llvm.bitreverse.i32(i32 %val) #1
114  store i32 %brev, i32 addrspace(1)* %out
115  ret void
116}
117
118define amdgpu_kernel void @v_brev_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) #0 {
119; SI-LABEL: v_brev_i32:
120; SI:       ; %bb.0:
121; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
122; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
123; SI-NEXT:    s_mov_b32 s7, 0xf000
124; SI-NEXT:    s_mov_b32 s2, 0
125; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
126; SI-NEXT:    v_mov_b32_e32 v1, 0
127; SI-NEXT:    s_mov_b32 s3, s7
128; SI-NEXT:    s_waitcnt lgkmcnt(0)
129; SI-NEXT:    buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
130; SI-NEXT:    s_mov_b32 s6, -1
131; SI-NEXT:    s_waitcnt vmcnt(0)
132; SI-NEXT:    v_bfrev_b32_e32 v0, v0
133; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
134; SI-NEXT:    s_endpgm
135;
136; FLAT-LABEL: v_brev_i32:
137; FLAT:       ; %bb.0:
138; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
139; FLAT-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
140; FLAT-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
141; FLAT-NEXT:    s_mov_b32 s7, 0xf000
142; FLAT-NEXT:    s_mov_b32 s6, -1
143; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
144; FLAT-NEXT:    v_mov_b32_e32 v1, s1
145; FLAT-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
146; FLAT-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
147; FLAT-NEXT:    flat_load_dword v0, v[0:1]
148; FLAT-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
149; FLAT-NEXT:    v_bfrev_b32_e32 v0, v0
150; FLAT-NEXT:    buffer_store_dword v0, off, s[4:7], 0
151; FLAT-NEXT:    s_endpgm
152  %tid = call i32 @llvm.amdgcn.workitem.id.x()
153  %gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
154  %val = load i32, i32 addrspace(1)* %gep
155  %brev = call i32 @llvm.bitreverse.i32(i32 %val) #1
156  store i32 %brev, i32 addrspace(1)* %out
157  ret void
158}
159
160define amdgpu_kernel void @s_brev_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> %val) #0 {
161; SI-LABEL: s_brev_v2i32:
162; SI:       ; %bb.0:
163; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
164; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
165; SI-NEXT:    s_mov_b32 s3, 0xf000
166; SI-NEXT:    s_waitcnt lgkmcnt(0)
167; SI-NEXT:    s_brev_b32 s5, s5
168; SI-NEXT:    s_brev_b32 s4, s4
169; SI-NEXT:    s_mov_b32 s2, -1
170; SI-NEXT:    v_mov_b32_e32 v0, s4
171; SI-NEXT:    v_mov_b32_e32 v1, s5
172; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
173; SI-NEXT:    s_endpgm
174;
175; FLAT-LABEL: s_brev_v2i32:
176; FLAT:       ; %bb.0:
177; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
178; FLAT-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
179; FLAT-NEXT:    s_mov_b32 s7, 0xf000
180; FLAT-NEXT:    s_mov_b32 s6, -1
181; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
182; FLAT-NEXT:    s_brev_b32 s1, s1
183; FLAT-NEXT:    s_brev_b32 s0, s0
184; FLAT-NEXT:    v_mov_b32_e32 v0, s0
185; FLAT-NEXT:    v_mov_b32_e32 v1, s1
186; FLAT-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
187; FLAT-NEXT:    s_endpgm
188  %brev = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %val) #1
189  store <2 x i32> %brev, <2 x i32> addrspace(1)* %out
190  ret void
191}
192
193define amdgpu_kernel void @v_brev_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) #0 {
194; SI-LABEL: v_brev_v2i32:
195; SI:       ; %bb.0:
196; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
197; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
198; SI-NEXT:    s_mov_b32 s7, 0xf000
199; SI-NEXT:    s_mov_b32 s2, 0
200; SI-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
201; SI-NEXT:    v_mov_b32_e32 v1, 0
202; SI-NEXT:    s_mov_b32 s3, s7
203; SI-NEXT:    s_waitcnt lgkmcnt(0)
204; SI-NEXT:    buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 addr64
205; SI-NEXT:    s_mov_b32 s6, -1
206; SI-NEXT:    s_waitcnt vmcnt(0)
207; SI-NEXT:    v_bfrev_b32_e32 v1, v1
208; SI-NEXT:    v_bfrev_b32_e32 v0, v0
209; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
210; SI-NEXT:    s_endpgm
211;
212; FLAT-LABEL: v_brev_v2i32:
213; FLAT:       ; %bb.0:
214; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
215; FLAT-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
216; FLAT-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
217; FLAT-NEXT:    s_mov_b32 s7, 0xf000
218; FLAT-NEXT:    s_mov_b32 s6, -1
219; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
220; FLAT-NEXT:    v_mov_b32_e32 v1, s1
221; FLAT-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
222; FLAT-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
223; FLAT-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
224; FLAT-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
225; FLAT-NEXT:    v_bfrev_b32_e32 v1, v1
226; FLAT-NEXT:    v_bfrev_b32_e32 v0, v0
227; FLAT-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
228; FLAT-NEXT:    s_endpgm
229  %tid = call i32 @llvm.amdgcn.workitem.id.x()
230  %gep = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %valptr, i32 %tid
231  %val = load <2 x i32>, <2 x i32> addrspace(1)* %gep
232  %brev = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %val) #1
233  store <2 x i32> %brev, <2 x i32> addrspace(1)* %out
234  ret void
235}
236
237define amdgpu_kernel void @s_brev_i64(i64 addrspace(1)* noalias %out, i64 %val) #0 {
238; SI-LABEL: s_brev_i64:
239; SI:       ; %bb.0:
240; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
241; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
242; SI-NEXT:    s_mov_b32 s7, 0xf000
243; SI-NEXT:    s_mov_b32 s6, -1
244; SI-NEXT:    s_mov_b32 s17, 0xff0000
245; SI-NEXT:    s_mov_b32 s3, 0
246; SI-NEXT:    s_mov_b32 s13, 0xff00
247; SI-NEXT:    s_mov_b32 s22, 0xf0f0f0f
248; SI-NEXT:    s_mov_b32 s23, 0xf0f0f0f0
249; SI-NEXT:    s_mov_b32 s24, 0x33333333
250; SI-NEXT:    s_mov_b32 s25, 0xcccccccc
251; SI-NEXT:    s_mov_b32 s26, 0x55555555
252; SI-NEXT:    s_mov_b32 s27, 0xaaaaaaaa
253; SI-NEXT:    s_mov_b32 s9, s3
254; SI-NEXT:    s_mov_b32 s10, s3
255; SI-NEXT:    s_mov_b32 s12, s3
256; SI-NEXT:    s_mov_b32 s14, s3
257; SI-NEXT:    s_mov_b32 s16, s3
258; SI-NEXT:    s_waitcnt lgkmcnt(0)
259; SI-NEXT:    v_mov_b32_e32 v0, s0
260; SI-NEXT:    v_alignbit_b32 v1, s1, v0, 24
261; SI-NEXT:    v_alignbit_b32 v0, s1, v0, 8
262; SI-NEXT:    s_lshr_b32 s2, s1, 24
263; SI-NEXT:    s_lshr_b32 s8, s1, 8
264; SI-NEXT:    s_lshl_b64 s[18:19], s[0:1], 8
265; SI-NEXT:    s_lshl_b64 s[20:21], s[0:1], 24
266; SI-NEXT:    s_lshl_b32 s15, s0, 24
267; SI-NEXT:    s_lshl_b32 s0, s0, 8
268; SI-NEXT:    v_and_b32_e32 v1, s17, v1
269; SI-NEXT:    v_and_b32_e32 v0, 0xff000000, v0
270; SI-NEXT:    s_and_b32 s8, s8, s13
271; SI-NEXT:    s_and_b32 s11, s19, 0xff
272; SI-NEXT:    s_and_b32 s13, s21, s13
273; SI-NEXT:    s_and_b32 s17, s0, s17
274; SI-NEXT:    v_or_b32_e32 v0, v0, v1
275; SI-NEXT:    s_or_b64 s[0:1], s[8:9], s[2:3]
276; SI-NEXT:    s_or_b64 s[2:3], s[12:13], s[10:11]
277; SI-NEXT:    s_or_b64 s[8:9], s[14:15], s[16:17]
278; SI-NEXT:    v_or_b32_e32 v0, s0, v0
279; SI-NEXT:    v_mov_b32_e32 v1, s1
280; SI-NEXT:    s_or_b64 s[0:1], s[8:9], s[2:3]
281; SI-NEXT:    v_or_b32_e32 v2, s0, v0
282; SI-NEXT:    v_or_b32_e32 v3, s1, v1
283; SI-NEXT:    v_and_b32_e32 v1, s22, v3
284; SI-NEXT:    v_and_b32_e32 v0, s22, v2
285; SI-NEXT:    v_and_b32_e32 v3, s23, v3
286; SI-NEXT:    v_and_b32_e32 v2, s23, v2
287; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 4
288; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 4
289; SI-NEXT:    v_or_b32_e32 v2, v2, v0
290; SI-NEXT:    v_or_b32_e32 v3, v3, v1
291; SI-NEXT:    v_and_b32_e32 v1, s24, v3
292; SI-NEXT:    v_and_b32_e32 v0, s24, v2
293; SI-NEXT:    v_and_b32_e32 v3, s25, v3
294; SI-NEXT:    v_and_b32_e32 v2, s25, v2
295; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 2
296; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 2
297; SI-NEXT:    v_or_b32_e32 v2, v2, v0
298; SI-NEXT:    v_or_b32_e32 v3, v3, v1
299; SI-NEXT:    v_and_b32_e32 v1, s26, v3
300; SI-NEXT:    v_and_b32_e32 v0, s26, v2
301; SI-NEXT:    v_and_b32_e32 v3, s27, v3
302; SI-NEXT:    v_and_b32_e32 v2, s27, v2
303; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
304; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 1
305; SI-NEXT:    v_or_b32_e32 v0, v2, v0
306; SI-NEXT:    v_or_b32_e32 v1, v3, v1
307; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
308; SI-NEXT:    s_endpgm
309;
310; FLAT-LABEL: s_brev_i64:
311; FLAT:       ; %bb.0:
312; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
313; FLAT-NEXT:    s_mov_b32 s3, 0
314; FLAT-NEXT:    s_mov_b32 s10, 0xff0000
315; FLAT-NEXT:    s_mov_b32 s7, s3
316; FLAT-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
317; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
318; FLAT-NEXT:    v_mov_b32_e32 v0, s4
319; FLAT-NEXT:    v_alignbit_b32 v1, s5, v0, 24
320; FLAT-NEXT:    v_alignbit_b32 v0, s5, v0, 8
321; FLAT-NEXT:    s_bfe_u32 s6, s5, 0x80010
322; FLAT-NEXT:    v_and_b32_e32 v1, s10, v1
323; FLAT-NEXT:    v_and_b32_e32 v0, 0xff000000, v0
324; FLAT-NEXT:    s_lshr_b32 s2, s5, 24
325; FLAT-NEXT:    s_lshl_b32 s6, s6, 8
326; FLAT-NEXT:    s_or_b64 s[6:7], s[6:7], s[2:3]
327; FLAT-NEXT:    v_or_b32_e32 v0, v0, v1
328; FLAT-NEXT:    s_lshl_b64 s[8:9], s[4:5], 24
329; FLAT-NEXT:    v_or_b32_e32 v0, s6, v0
330; FLAT-NEXT:    v_mov_b32_e32 v1, s7
331; FLAT-NEXT:    s_lshl_b64 s[6:7], s[4:5], 8
332; FLAT-NEXT:    s_lshl_b32 s2, s4, 8
333; FLAT-NEXT:    s_and_b32 s7, s7, 0xff
334; FLAT-NEXT:    s_mov_b32 s6, s3
335; FLAT-NEXT:    s_and_b32 s9, s9, 0xff00
336; FLAT-NEXT:    s_mov_b32 s8, s3
337; FLAT-NEXT:    s_or_b64 s[6:7], s[8:9], s[6:7]
338; FLAT-NEXT:    s_lshl_b32 s9, s4, 24
339; FLAT-NEXT:    s_and_b32 s5, s2, s10
340; FLAT-NEXT:    s_mov_b32 s4, s3
341; FLAT-NEXT:    s_or_b64 s[2:3], s[8:9], s[4:5]
342; FLAT-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
343; FLAT-NEXT:    v_or_b32_e32 v2, s2, v0
344; FLAT-NEXT:    v_or_b32_e32 v3, s3, v1
345; FLAT-NEXT:    s_mov_b32 s2, 0xf0f0f0f
346; FLAT-NEXT:    v_and_b32_e32 v1, s2, v3
347; FLAT-NEXT:    v_and_b32_e32 v0, s2, v2
348; FLAT-NEXT:    s_mov_b32 s2, 0xf0f0f0f0
349; FLAT-NEXT:    v_and_b32_e32 v3, s2, v3
350; FLAT-NEXT:    v_and_b32_e32 v2, s2, v2
351; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 4, v[0:1]
352; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 4, v[2:3]
353; FLAT-NEXT:    s_mov_b32 s2, 0x33333333
354; FLAT-NEXT:    v_or_b32_e32 v2, v2, v0
355; FLAT-NEXT:    v_or_b32_e32 v3, v3, v1
356; FLAT-NEXT:    v_and_b32_e32 v1, s2, v3
357; FLAT-NEXT:    v_and_b32_e32 v0, s2, v2
358; FLAT-NEXT:    s_mov_b32 s2, 0xcccccccc
359; FLAT-NEXT:    v_and_b32_e32 v3, s2, v3
360; FLAT-NEXT:    v_and_b32_e32 v2, s2, v2
361; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 2, v[0:1]
362; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 2, v[2:3]
363; FLAT-NEXT:    s_mov_b32 s2, 0x55555555
364; FLAT-NEXT:    v_or_b32_e32 v2, v2, v0
365; FLAT-NEXT:    v_or_b32_e32 v3, v3, v1
366; FLAT-NEXT:    v_and_b32_e32 v1, s2, v3
367; FLAT-NEXT:    v_and_b32_e32 v0, s2, v2
368; FLAT-NEXT:    s_mov_b32 s2, 0xaaaaaaaa
369; FLAT-NEXT:    v_and_b32_e32 v3, s2, v3
370; FLAT-NEXT:    v_and_b32_e32 v2, s2, v2
371; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
372; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 1, v[2:3]
373; FLAT-NEXT:    s_mov_b32 s3, 0xf000
374; FLAT-NEXT:    s_mov_b32 s2, -1
375; FLAT-NEXT:    v_or_b32_e32 v0, v2, v0
376; FLAT-NEXT:    v_or_b32_e32 v1, v3, v1
377; FLAT-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
378; FLAT-NEXT:    s_endpgm
379  %brev = call i64 @llvm.bitreverse.i64(i64 %val) #1
380  store i64 %brev, i64 addrspace(1)* %out
381  ret void
382}
383
384define amdgpu_kernel void @v_brev_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %valptr) #0 {
385; SI-LABEL: v_brev_i64:
386; SI:       ; %bb.0:
387; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
388; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
389; SI-NEXT:    s_mov_b32 s7, 0xf000
390; SI-NEXT:    s_mov_b32 s2, 0
391; SI-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
392; SI-NEXT:    v_mov_b32_e32 v1, 0
393; SI-NEXT:    s_mov_b32 s3, s7
394; SI-NEXT:    s_waitcnt lgkmcnt(0)
395; SI-NEXT:    buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 addr64
396; SI-NEXT:    s_mov_b32 s0, 0xff0000
397; SI-NEXT:    s_mov_b32 s1, 0xff00
398; SI-NEXT:    s_mov_b32 s2, 0xf0f0f0f
399; SI-NEXT:    s_mov_b32 s3, 0xf0f0f0f0
400; SI-NEXT:    s_mov_b32 s8, 0x33333333
401; SI-NEXT:    s_mov_b32 s9, 0xcccccccc
402; SI-NEXT:    s_mov_b32 s10, 0x55555555
403; SI-NEXT:    s_mov_b32 s6, -1
404; SI-NEXT:    s_mov_b32 s11, 0xaaaaaaaa
405; SI-NEXT:    s_waitcnt vmcnt(0)
406; SI-NEXT:    v_alignbit_b32 v4, v1, v0, 24
407; SI-NEXT:    v_alignbit_b32 v5, v1, v0, 8
408; SI-NEXT:    v_lshrrev_b32_e32 v6, 24, v1
409; SI-NEXT:    v_lshrrev_b32_e32 v7, 8, v1
410; SI-NEXT:    v_lshl_b64 v[2:3], v[0:1], 8
411; SI-NEXT:    v_lshl_b64 v[1:2], v[0:1], 24
412; SI-NEXT:    v_lshlrev_b32_e32 v1, 24, v0
413; SI-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
414; SI-NEXT:    v_and_b32_e32 v4, s0, v4
415; SI-NEXT:    v_and_b32_e32 v5, 0xff000000, v5
416; SI-NEXT:    v_and_b32_e32 v7, s1, v7
417; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
418; SI-NEXT:    v_and_b32_e32 v2, s1, v2
419; SI-NEXT:    v_and_b32_e32 v0, s0, v0
420; SI-NEXT:    v_or_b32_e32 v4, v5, v4
421; SI-NEXT:    v_or_b32_e32 v5, v7, v6
422; SI-NEXT:    v_or_b32_e32 v2, v2, v3
423; SI-NEXT:    v_or_b32_e32 v0, v1, v0
424; SI-NEXT:    v_or_b32_e32 v4, v4, v5
425; SI-NEXT:    v_or_b32_e32 v2, v0, v2
426; SI-NEXT:    v_and_b32_e32 v1, s2, v2
427; SI-NEXT:    v_and_b32_e32 v0, s2, v4
428; SI-NEXT:    v_and_b32_e32 v3, s3, v2
429; SI-NEXT:    v_and_b32_e32 v2, s3, v4
430; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 4
431; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 4
432; SI-NEXT:    v_or_b32_e32 v3, v3, v1
433; SI-NEXT:    v_or_b32_e32 v2, v2, v0
434; SI-NEXT:    v_and_b32_e32 v1, s8, v3
435; SI-NEXT:    v_and_b32_e32 v0, s8, v2
436; SI-NEXT:    v_and_b32_e32 v3, s9, v3
437; SI-NEXT:    v_and_b32_e32 v2, s9, v2
438; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 2
439; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 2
440; SI-NEXT:    v_or_b32_e32 v3, v3, v1
441; SI-NEXT:    v_or_b32_e32 v2, v2, v0
442; SI-NEXT:    v_and_b32_e32 v1, s10, v3
443; SI-NEXT:    v_and_b32_e32 v0, s10, v2
444; SI-NEXT:    v_and_b32_e32 v3, s11, v3
445; SI-NEXT:    v_and_b32_e32 v2, s11, v2
446; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
447; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 1
448; SI-NEXT:    v_or_b32_e32 v1, v3, v1
449; SI-NEXT:    v_or_b32_e32 v0, v2, v0
450; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
451; SI-NEXT:    s_endpgm
452;
453; FLAT-LABEL: v_brev_i64:
454; FLAT:       ; %bb.0:
455; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
456; FLAT-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
457; FLAT-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
458; FLAT-NEXT:    v_mov_b32_e32 v4, 8
459; FLAT-NEXT:    s_mov_b32 s2, 0xff0000
460; FLAT-NEXT:    s_mov_b32 s3, 0xf0f0f0f
461; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
462; FLAT-NEXT:    v_mov_b32_e32 v1, s1
463; FLAT-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
464; FLAT-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
465; FLAT-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
466; FLAT-NEXT:    s_mov_b32 s0, 0xf0f0f0f0
467; FLAT-NEXT:    s_mov_b32 s1, 0x33333333
468; FLAT-NEXT:    s_mov_b32 s6, 0xcccccccc
469; FLAT-NEXT:    s_mov_b32 s8, 0x55555555
470; FLAT-NEXT:    s_mov_b32 s9, 0xaaaaaaaa
471; FLAT-NEXT:    s_mov_b32 s7, 0xf000
472; FLAT-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
473; FLAT-NEXT:    v_lshlrev_b64 v[2:3], 24, v[0:1]
474; FLAT-NEXT:    v_alignbit_b32 v2, v1, v0, 24
475; FLAT-NEXT:    v_alignbit_b32 v6, v1, v0, 8
476; FLAT-NEXT:    v_lshlrev_b32_sdwa v7, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
477; FLAT-NEXT:    v_lshlrev_b64 v[4:5], 8, v[0:1]
478; FLAT-NEXT:    v_lshlrev_b32_e32 v4, 24, v0
479; FLAT-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
480; FLAT-NEXT:    v_and_b32_e32 v2, s2, v2
481; FLAT-NEXT:    v_and_b32_e32 v6, 0xff000000, v6
482; FLAT-NEXT:    v_and_b32_e32 v0, s2, v0
483; FLAT-NEXT:    v_or_b32_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
484; FLAT-NEXT:    v_or_b32_e32 v2, v6, v2
485; FLAT-NEXT:    v_and_b32_e32 v3, 0xff00, v3
486; FLAT-NEXT:    v_or_b32_e32 v1, v2, v1
487; FLAT-NEXT:    v_or_b32_e32 v0, v4, v0
488; FLAT-NEXT:    v_or_b32_sdwa v2, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
489; FLAT-NEXT:    v_or_b32_e32 v3, v0, v2
490; FLAT-NEXT:    v_and_b32_e32 v0, s3, v1
491; FLAT-NEXT:    v_and_b32_e32 v2, s0, v1
492; FLAT-NEXT:    v_and_b32_e32 v1, s3, v3
493; FLAT-NEXT:    v_and_b32_e32 v3, s0, v3
494; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 4, v[0:1]
495; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 4, v[2:3]
496; FLAT-NEXT:    v_or_b32_e32 v3, v3, v1
497; FLAT-NEXT:    v_or_b32_e32 v2, v2, v0
498; FLAT-NEXT:    v_and_b32_e32 v1, s1, v3
499; FLAT-NEXT:    v_and_b32_e32 v0, s1, v2
500; FLAT-NEXT:    v_and_b32_e32 v3, s6, v3
501; FLAT-NEXT:    v_and_b32_e32 v2, s6, v2
502; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 2, v[0:1]
503; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 2, v[2:3]
504; FLAT-NEXT:    s_mov_b32 s6, -1
505; FLAT-NEXT:    v_or_b32_e32 v3, v3, v1
506; FLAT-NEXT:    v_or_b32_e32 v2, v2, v0
507; FLAT-NEXT:    v_and_b32_e32 v1, s8, v3
508; FLAT-NEXT:    v_and_b32_e32 v0, s8, v2
509; FLAT-NEXT:    v_and_b32_e32 v3, s9, v3
510; FLAT-NEXT:    v_and_b32_e32 v2, s9, v2
511; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
512; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 1, v[2:3]
513; FLAT-NEXT:    v_or_b32_e32 v1, v3, v1
514; FLAT-NEXT:    v_or_b32_e32 v0, v2, v0
515; FLAT-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
516; FLAT-NEXT:    s_endpgm
517  %tid = call i32 @llvm.amdgcn.workitem.id.x()
518  %gep = getelementptr i64, i64 addrspace(1)* %valptr, i32 %tid
519  %val = load i64, i64 addrspace(1)* %gep
520  %brev = call i64 @llvm.bitreverse.i64(i64 %val) #1
521  store i64 %brev, i64 addrspace(1)* %out
522  ret void
523}
524
525define amdgpu_kernel void @s_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %val) #0 {
526; SI-LABEL: s_brev_v2i64:
527; SI:       ; %bb.0:
528; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
529; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
530; SI-NEXT:    s_mov_b32 s7, 0xf000
531; SI-NEXT:    s_mov_b32 s6, -1
532; SI-NEXT:    s_mov_b32 s25, 0xff0000
533; SI-NEXT:    s_mov_b32 s9, 0
534; SI-NEXT:    s_mov_b32 s20, 0xff000000
535; SI-NEXT:    s_mov_b32 s29, 0xff00
536; SI-NEXT:    s_movk_i32 s27, 0xff
537; SI-NEXT:    s_mov_b32 s32, 0xf0f0f0f
538; SI-NEXT:    s_mov_b32 s33, 0xf0f0f0f0
539; SI-NEXT:    s_mov_b32 s34, 0x33333333
540; SI-NEXT:    s_mov_b32 s35, 0xcccccccc
541; SI-NEXT:    s_mov_b32 s36, 0x55555555
542; SI-NEXT:    s_mov_b32 s37, 0xaaaaaaaa
543; SI-NEXT:    s_mov_b32 s11, s9
544; SI-NEXT:    s_mov_b32 s12, s9
545; SI-NEXT:    s_mov_b32 s14, s9
546; SI-NEXT:    s_mov_b32 s16, s9
547; SI-NEXT:    s_mov_b32 s18, s9
548; SI-NEXT:    s_mov_b32 s21, s9
549; SI-NEXT:    s_mov_b32 s22, s9
550; SI-NEXT:    s_mov_b32 s24, s9
551; SI-NEXT:    s_mov_b32 s26, s9
552; SI-NEXT:    s_mov_b32 s28, s9
553; SI-NEXT:    s_waitcnt lgkmcnt(0)
554; SI-NEXT:    v_mov_b32_e32 v0, s2
555; SI-NEXT:    v_alignbit_b32 v1, s3, v0, 24
556; SI-NEXT:    v_alignbit_b32 v0, s3, v0, 8
557; SI-NEXT:    s_lshr_b32 s8, s3, 24
558; SI-NEXT:    s_lshr_b32 s10, s3, 8
559; SI-NEXT:    s_lshl_b32 s13, s2, 24
560; SI-NEXT:    s_lshl_b32 s15, s2, 8
561; SI-NEXT:    s_lshl_b64 s[30:31], s[2:3], 8
562; SI-NEXT:    s_and_b32 s17, s31, s27
563; SI-NEXT:    s_lshl_b64 s[2:3], s[2:3], 24
564; SI-NEXT:    v_mov_b32_e32 v2, s0
565; SI-NEXT:    v_alignbit_b32 v3, s1, v2, 24
566; SI-NEXT:    v_alignbit_b32 v2, s1, v2, 8
567; SI-NEXT:    s_and_b32 s10, s10, s29
568; SI-NEXT:    s_lshr_b32 s30, s1, 8
569; SI-NEXT:    s_lshl_b32 s23, s0, 24
570; SI-NEXT:    s_and_b32 s15, s15, s25
571; SI-NEXT:    s_lshl_b32 s38, s0, 8
572; SI-NEXT:    s_and_b32 s19, s3, s29
573; SI-NEXT:    s_lshl_b64 s[2:3], s[0:1], 8
574; SI-NEXT:    v_and_b32_e32 v0, s20, v0
575; SI-NEXT:    v_and_b32_e32 v2, s20, v2
576; SI-NEXT:    s_and_b32 s20, s30, s29
577; SI-NEXT:    s_lshl_b64 s[30:31], s[0:1], 24
578; SI-NEXT:    v_and_b32_e32 v1, s25, v1
579; SI-NEXT:    v_and_b32_e32 v3, s25, v3
580; SI-NEXT:    s_and_b32 s25, s38, s25
581; SI-NEXT:    s_and_b32 s27, s3, s27
582; SI-NEXT:    s_and_b32 s29, s31, s29
583; SI-NEXT:    v_or_b32_e32 v0, v0, v1
584; SI-NEXT:    s_or_b64 s[2:3], s[10:11], s[8:9]
585; SI-NEXT:    s_or_b64 s[10:11], s[12:13], s[14:15]
586; SI-NEXT:    s_or_b64 s[12:13], s[18:19], s[16:17]
587; SI-NEXT:    v_or_b32_e32 v1, v2, v3
588; SI-NEXT:    s_lshr_b32 s8, s1, 24
589; SI-NEXT:    s_or_b64 s[0:1], s[22:23], s[24:25]
590; SI-NEXT:    s_or_b64 s[14:15], s[28:29], s[26:27]
591; SI-NEXT:    v_or_b32_e32 v0, s2, v0
592; SI-NEXT:    v_mov_b32_e32 v2, s3
593; SI-NEXT:    s_or_b64 s[2:3], s[10:11], s[12:13]
594; SI-NEXT:    s_or_b64 s[8:9], s[20:21], s[8:9]
595; SI-NEXT:    s_or_b64 s[0:1], s[0:1], s[14:15]
596; SI-NEXT:    v_or_b32_e32 v3, s2, v0
597; SI-NEXT:    v_or_b32_e32 v4, s3, v2
598; SI-NEXT:    v_or_b32_e32 v5, s8, v1
599; SI-NEXT:    v_mov_b32_e32 v0, s9
600; SI-NEXT:    v_or_b32_e32 v6, s1, v0
601; SI-NEXT:    v_and_b32_e32 v0, s32, v3
602; SI-NEXT:    v_and_b32_e32 v1, s32, v4
603; SI-NEXT:    v_and_b32_e32 v2, s33, v3
604; SI-NEXT:    v_and_b32_e32 v3, s33, v4
605; SI-NEXT:    v_or_b32_e32 v5, s0, v5
606; SI-NEXT:    v_and_b32_e32 v4, s32, v6
607; SI-NEXT:    v_and_b32_e32 v6, s33, v6
608; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 4
609; SI-NEXT:    v_lshr_b64 v[7:8], v[2:3], 4
610; SI-NEXT:    v_and_b32_e32 v3, s32, v5
611; SI-NEXT:    v_and_b32_e32 v5, s33, v5
612; SI-NEXT:    v_or_b32_e32 v7, v7, v0
613; SI-NEXT:    v_or_b32_e32 v8, v8, v1
614; SI-NEXT:    v_lshl_b64 v[0:1], v[3:4], 4
615; SI-NEXT:    v_lshr_b64 v[2:3], v[5:6], 4
616; SI-NEXT:    v_and_b32_e32 v4, s34, v7
617; SI-NEXT:    v_and_b32_e32 v5, s34, v8
618; SI-NEXT:    v_and_b32_e32 v6, s35, v7
619; SI-NEXT:    v_and_b32_e32 v7, s35, v8
620; SI-NEXT:    v_or_b32_e32 v8, v2, v0
621; SI-NEXT:    v_or_b32_e32 v9, v3, v1
622; SI-NEXT:    v_lshl_b64 v[0:1], v[4:5], 2
623; SI-NEXT:    v_lshr_b64 v[2:3], v[6:7], 2
624; SI-NEXT:    v_and_b32_e32 v4, s34, v8
625; SI-NEXT:    v_and_b32_e32 v5, s34, v9
626; SI-NEXT:    v_and_b32_e32 v6, s35, v8
627; SI-NEXT:    v_and_b32_e32 v7, s35, v9
628; SI-NEXT:    v_or_b32_e32 v8, v2, v0
629; SI-NEXT:    v_or_b32_e32 v9, v3, v1
630; SI-NEXT:    v_lshl_b64 v[0:1], v[4:5], 2
631; SI-NEXT:    v_lshr_b64 v[2:3], v[6:7], 2
632; SI-NEXT:    v_and_b32_e32 v4, s36, v8
633; SI-NEXT:    v_and_b32_e32 v5, s36, v9
634; SI-NEXT:    v_and_b32_e32 v6, s37, v8
635; SI-NEXT:    v_and_b32_e32 v7, s37, v9
636; SI-NEXT:    v_or_b32_e32 v8, v2, v0
637; SI-NEXT:    v_or_b32_e32 v9, v3, v1
638; SI-NEXT:    v_lshl_b64 v[0:1], v[4:5], 1
639; SI-NEXT:    v_lshr_b64 v[2:3], v[6:7], 1
640; SI-NEXT:    v_and_b32_e32 v4, s36, v8
641; SI-NEXT:    v_and_b32_e32 v5, s36, v9
642; SI-NEXT:    v_and_b32_e32 v6, s37, v8
643; SI-NEXT:    v_and_b32_e32 v7, s37, v9
644; SI-NEXT:    v_or_b32_e32 v2, v2, v0
645; SI-NEXT:    v_or_b32_e32 v3, v3, v1
646; SI-NEXT:    v_lshl_b64 v[0:1], v[4:5], 1
647; SI-NEXT:    v_lshr_b64 v[4:5], v[6:7], 1
648; SI-NEXT:    v_or_b32_e32 v0, v4, v0
649; SI-NEXT:    v_or_b32_e32 v1, v5, v1
650; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
651; SI-NEXT:    s_endpgm
652;
653; FLAT-LABEL: s_brev_v2i64:
654; FLAT:       ; %bb.0:
655; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
656; FLAT-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
657; FLAT-NEXT:    s_mov_b32 s9, 0
658; FLAT-NEXT:    s_mov_b32 s12, 0xff0000
659; FLAT-NEXT:    s_mov_b32 s13, 0xff000000
660; FLAT-NEXT:    s_mov_b32 s7, s9
661; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
662; FLAT-NEXT:    v_mov_b32_e32 v0, s2
663; FLAT-NEXT:    v_alignbit_b32 v1, s3, v0, 24
664; FLAT-NEXT:    v_alignbit_b32 v0, s3, v0, 8
665; FLAT-NEXT:    s_bfe_u32 s6, s3, 0x80010
666; FLAT-NEXT:    v_and_b32_e32 v1, s12, v1
667; FLAT-NEXT:    v_and_b32_e32 v0, s13, v0
668; FLAT-NEXT:    s_lshr_b32 s8, s3, 24
669; FLAT-NEXT:    s_lshl_b32 s6, s6, 8
670; FLAT-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
671; FLAT-NEXT:    v_or_b32_e32 v0, v0, v1
672; FLAT-NEXT:    s_lshl_b32 s8, s2, 8
673; FLAT-NEXT:    v_or_b32_e32 v0, s6, v0
674; FLAT-NEXT:    v_mov_b32_e32 v1, s7
675; FLAT-NEXT:    s_and_b32 s11, s8, s12
676; FLAT-NEXT:    s_lshl_b32 s7, s2, 24
677; FLAT-NEXT:    s_mov_b32 s6, s9
678; FLAT-NEXT:    s_mov_b32 s10, s9
679; FLAT-NEXT:    s_or_b64 s[6:7], s[6:7], s[10:11]
680; FLAT-NEXT:    s_lshl_b64 s[10:11], s[2:3], 8
681; FLAT-NEXT:    s_movk_i32 s14, 0xff
682; FLAT-NEXT:    s_lshl_b64 s[2:3], s[2:3], 24
683; FLAT-NEXT:    s_mov_b32 s15, 0xff00
684; FLAT-NEXT:    s_and_b32 s11, s11, s14
685; FLAT-NEXT:    s_mov_b32 s10, s9
686; FLAT-NEXT:    s_and_b32 s3, s3, s15
687; FLAT-NEXT:    s_mov_b32 s2, s9
688; FLAT-NEXT:    s_or_b64 s[2:3], s[2:3], s[10:11]
689; FLAT-NEXT:    s_or_b64 s[2:3], s[6:7], s[2:3]
690; FLAT-NEXT:    v_mov_b32_e32 v4, s0
691; FLAT-NEXT:    v_alignbit_b32 v5, s1, v4, 24
692; FLAT-NEXT:    v_alignbit_b32 v4, s1, v4, 8
693; FLAT-NEXT:    v_or_b32_e32 v2, s2, v0
694; FLAT-NEXT:    s_bfe_u32 s2, s1, 0x80010
695; FLAT-NEXT:    v_or_b32_e32 v3, s3, v1
696; FLAT-NEXT:    v_and_b32_e32 v5, s12, v5
697; FLAT-NEXT:    v_and_b32_e32 v4, s13, v4
698; FLAT-NEXT:    s_lshr_b32 s8, s1, 24
699; FLAT-NEXT:    s_lshl_b32 s2, s2, 8
700; FLAT-NEXT:    s_mov_b32 s3, s9
701; FLAT-NEXT:    s_or_b64 s[2:3], s[2:3], s[8:9]
702; FLAT-NEXT:    v_or_b32_e32 v4, v4, v5
703; FLAT-NEXT:    s_lshl_b32 s8, s0, 8
704; FLAT-NEXT:    v_or_b32_e32 v4, s2, v4
705; FLAT-NEXT:    v_mov_b32_e32 v5, s3
706; FLAT-NEXT:    s_lshl_b32 s3, s0, 24
707; FLAT-NEXT:    s_mov_b32 s2, s9
708; FLAT-NEXT:    s_and_b32 s11, s8, s12
709; FLAT-NEXT:    s_mov_b32 s16, 0xf0f0f0f
710; FLAT-NEXT:    s_or_b64 s[2:3], s[2:3], s[10:11]
711; FLAT-NEXT:    s_lshl_b64 s[10:11], s[0:1], 8
712; FLAT-NEXT:    s_lshl_b64 s[0:1], s[0:1], 24
713; FLAT-NEXT:    s_mov_b32 s17, 0xf0f0f0f0
714; FLAT-NEXT:    v_and_b32_e32 v0, s16, v2
715; FLAT-NEXT:    v_and_b32_e32 v1, s16, v3
716; FLAT-NEXT:    v_and_b32_e32 v2, s17, v2
717; FLAT-NEXT:    v_and_b32_e32 v3, s17, v3
718; FLAT-NEXT:    s_and_b32 s11, s11, s14
719; FLAT-NEXT:    s_mov_b32 s10, s9
720; FLAT-NEXT:    s_and_b32 s1, s1, s15
721; FLAT-NEXT:    s_mov_b32 s0, s9
722; FLAT-NEXT:    s_or_b64 s[0:1], s[0:1], s[10:11]
723; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 4, v[0:1]
724; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 4, v[2:3]
725; FLAT-NEXT:    s_or_b64 s[0:1], s[2:3], s[0:1]
726; FLAT-NEXT:    v_or_b32_e32 v6, s0, v4
727; FLAT-NEXT:    v_or_b32_e32 v7, s1, v5
728; FLAT-NEXT:    v_or_b32_e32 v2, v2, v0
729; FLAT-NEXT:    s_mov_b32 s18, 0x33333333
730; FLAT-NEXT:    v_or_b32_e32 v3, v3, v1
731; FLAT-NEXT:    s_mov_b32 s19, 0xcccccccc
732; FLAT-NEXT:    v_and_b32_e32 v0, s18, v2
733; FLAT-NEXT:    v_and_b32_e32 v1, s18, v3
734; FLAT-NEXT:    v_and_b32_e32 v4, s16, v6
735; FLAT-NEXT:    v_and_b32_e32 v5, s16, v7
736; FLAT-NEXT:    v_and_b32_e32 v2, s19, v2
737; FLAT-NEXT:    v_and_b32_e32 v3, s19, v3
738; FLAT-NEXT:    v_and_b32_e32 v6, s17, v6
739; FLAT-NEXT:    v_and_b32_e32 v7, s17, v7
740; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 2, v[0:1]
741; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 2, v[2:3]
742; FLAT-NEXT:    v_lshlrev_b64 v[4:5], 4, v[4:5]
743; FLAT-NEXT:    v_lshrrev_b64 v[6:7], 4, v[6:7]
744; FLAT-NEXT:    v_or_b32_e32 v2, v2, v0
745; FLAT-NEXT:    v_or_b32_e32 v6, v6, v4
746; FLAT-NEXT:    v_or_b32_e32 v7, v7, v5
747; FLAT-NEXT:    s_mov_b32 s20, 0x55555555
748; FLAT-NEXT:    v_or_b32_e32 v3, v3, v1
749; FLAT-NEXT:    s_mov_b32 s21, 0xaaaaaaaa
750; FLAT-NEXT:    v_and_b32_e32 v0, s20, v2
751; FLAT-NEXT:    v_and_b32_e32 v1, s20, v3
752; FLAT-NEXT:    v_and_b32_e32 v4, s18, v6
753; FLAT-NEXT:    v_and_b32_e32 v5, s18, v7
754; FLAT-NEXT:    v_and_b32_e32 v2, s21, v2
755; FLAT-NEXT:    v_and_b32_e32 v3, s21, v3
756; FLAT-NEXT:    v_and_b32_e32 v6, s19, v6
757; FLAT-NEXT:    v_and_b32_e32 v7, s19, v7
758; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
759; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 1, v[2:3]
760; FLAT-NEXT:    v_lshlrev_b64 v[4:5], 2, v[4:5]
761; FLAT-NEXT:    v_lshrrev_b64 v[6:7], 2, v[6:7]
762; FLAT-NEXT:    v_or_b32_e32 v2, v2, v0
763; FLAT-NEXT:    v_or_b32_e32 v0, v6, v4
764; FLAT-NEXT:    v_or_b32_e32 v7, v7, v5
765; FLAT-NEXT:    v_and_b32_e32 v5, s20, v7
766; FLAT-NEXT:    v_and_b32_e32 v4, s20, v0
767; FLAT-NEXT:    v_and_b32_e32 v6, s21, v0
768; FLAT-NEXT:    v_and_b32_e32 v7, s21, v7
769; FLAT-NEXT:    v_lshlrev_b64 v[4:5], 1, v[4:5]
770; FLAT-NEXT:    v_lshrrev_b64 v[6:7], 1, v[6:7]
771; FLAT-NEXT:    v_or_b32_e32 v3, v3, v1
772; FLAT-NEXT:    s_mov_b32 s7, 0xf000
773; FLAT-NEXT:    s_mov_b32 s6, -1
774; FLAT-NEXT:    v_or_b32_e32 v0, v6, v4
775; FLAT-NEXT:    v_or_b32_e32 v1, v7, v5
776; FLAT-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
777; FLAT-NEXT:    s_endpgm
778  %brev = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %val) #1
779  store <2 x i64> %brev, <2 x i64> addrspace(1)* %out
780  ret void
781}
782
783define amdgpu_kernel void @v_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %valptr) #0 {
784; SI-LABEL: v_brev_v2i64:
785; SI:       ; %bb.0:
786; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
787; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
788; SI-NEXT:    s_mov_b32 s7, 0xf000
789; SI-NEXT:    s_mov_b32 s2, 0
790; SI-NEXT:    v_lshlrev_b32_e32 v0, 4, v0
791; SI-NEXT:    v_mov_b32_e32 v1, 0
792; SI-NEXT:    s_mov_b32 s3, s7
793; SI-NEXT:    s_waitcnt lgkmcnt(0)
794; SI-NEXT:    buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 addr64
795; SI-NEXT:    s_mov_b32 s0, 0xff0000
796; SI-NEXT:    s_mov_b32 s1, 0xff000000
797; SI-NEXT:    s_mov_b32 s6, -1
798; SI-NEXT:    s_waitcnt vmcnt(0)
799; SI-NEXT:    v_alignbit_b32 v8, v3, v2, 24
800; SI-NEXT:    v_alignbit_b32 v9, v3, v2, 8
801; SI-NEXT:    v_lshrrev_b32_e32 v10, 8, v3
802; SI-NEXT:    v_lshl_b64 v[4:5], v[2:3], 8
803; SI-NEXT:    v_lshl_b64 v[6:7], v[2:3], 24
804; SI-NEXT:    v_lshlrev_b32_e32 v4, 8, v2
805; SI-NEXT:    v_alignbit_b32 v6, v1, v0, 24
806; SI-NEXT:    v_alignbit_b32 v11, v1, v0, 8
807; SI-NEXT:    v_lshrrev_b32_e32 v12, 8, v1
808; SI-NEXT:    v_lshrrev_b32_e32 v13, 24, v3
809; SI-NEXT:    v_lshlrev_b32_e32 v14, 24, v2
810; SI-NEXT:    v_lshrrev_b32_e32 v15, 24, v1
811; SI-NEXT:    v_lshlrev_b32_e32 v16, 24, v0
812; SI-NEXT:    v_lshlrev_b32_e32 v17, 8, v0
813; SI-NEXT:    v_lshl_b64 v[2:3], v[0:1], 8
814; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 24
815; SI-NEXT:    s_mov_b32 s2, 0xff00
816; SI-NEXT:    s_movk_i32 s3, 0xff
817; SI-NEXT:    s_mov_b32 s8, 0xf0f0f0f
818; SI-NEXT:    s_mov_b32 s9, 0xf0f0f0f0
819; SI-NEXT:    s_mov_b32 s10, 0x33333333
820; SI-NEXT:    s_mov_b32 s11, 0xcccccccc
821; SI-NEXT:    s_mov_b32 s12, 0x55555555
822; SI-NEXT:    s_mov_b32 s13, 0xaaaaaaaa
823; SI-NEXT:    v_and_b32_e32 v0, s0, v8
824; SI-NEXT:    v_and_b32_e32 v2, s1, v9
825; SI-NEXT:    v_and_b32_e32 v8, s2, v10
826; SI-NEXT:    v_and_b32_e32 v5, s3, v5
827; SI-NEXT:    v_and_b32_e32 v7, s2, v7
828; SI-NEXT:    v_and_b32_e32 v4, s0, v4
829; SI-NEXT:    v_and_b32_e32 v6, s0, v6
830; SI-NEXT:    v_and_b32_e32 v9, s1, v11
831; SI-NEXT:    v_and_b32_e32 v10, s2, v12
832; SI-NEXT:    v_and_b32_e32 v3, s3, v3
833; SI-NEXT:    v_and_b32_e32 v1, s2, v1
834; SI-NEXT:    v_and_b32_e32 v11, s0, v17
835; SI-NEXT:    v_or_b32_e32 v0, v2, v0
836; SI-NEXT:    v_or_b32_e32 v2, v8, v13
837; SI-NEXT:    v_or_b32_e32 v5, v7, v5
838; SI-NEXT:    v_or_b32_e32 v4, v14, v4
839; SI-NEXT:    v_or_b32_e32 v6, v9, v6
840; SI-NEXT:    v_or_b32_e32 v7, v10, v15
841; SI-NEXT:    v_or_b32_e32 v1, v1, v3
842; SI-NEXT:    v_or_b32_e32 v3, v16, v11
843; SI-NEXT:    v_or_b32_e32 v2, v0, v2
844; SI-NEXT:    v_or_b32_e32 v4, v4, v5
845; SI-NEXT:    v_or_b32_e32 v6, v6, v7
846; SI-NEXT:    v_or_b32_e32 v7, v3, v1
847; SI-NEXT:    v_and_b32_e32 v1, s8, v4
848; SI-NEXT:    v_and_b32_e32 v0, s8, v2
849; SI-NEXT:    v_and_b32_e32 v3, s9, v4
850; SI-NEXT:    v_and_b32_e32 v2, s9, v2
851; SI-NEXT:    v_and_b32_e32 v5, s8, v7
852; SI-NEXT:    v_and_b32_e32 v4, s8, v6
853; SI-NEXT:    v_and_b32_e32 v7, s9, v7
854; SI-NEXT:    v_and_b32_e32 v6, s9, v6
855; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 4
856; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 4
857; SI-NEXT:    v_lshl_b64 v[4:5], v[4:5], 4
858; SI-NEXT:    v_lshr_b64 v[6:7], v[6:7], 4
859; SI-NEXT:    v_or_b32_e32 v3, v3, v1
860; SI-NEXT:    v_or_b32_e32 v2, v2, v0
861; SI-NEXT:    v_or_b32_e32 v7, v7, v5
862; SI-NEXT:    v_or_b32_e32 v6, v6, v4
863; SI-NEXT:    v_and_b32_e32 v1, s10, v3
864; SI-NEXT:    v_and_b32_e32 v0, s10, v2
865; SI-NEXT:    v_and_b32_e32 v3, s11, v3
866; SI-NEXT:    v_and_b32_e32 v2, s11, v2
867; SI-NEXT:    v_and_b32_e32 v5, s10, v7
868; SI-NEXT:    v_and_b32_e32 v4, s10, v6
869; SI-NEXT:    v_and_b32_e32 v7, s11, v7
870; SI-NEXT:    v_and_b32_e32 v6, s11, v6
871; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 2
872; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 2
873; SI-NEXT:    v_lshl_b64 v[4:5], v[4:5], 2
874; SI-NEXT:    v_lshr_b64 v[6:7], v[6:7], 2
875; SI-NEXT:    v_or_b32_e32 v3, v3, v1
876; SI-NEXT:    v_or_b32_e32 v2, v2, v0
877; SI-NEXT:    v_or_b32_e32 v7, v7, v5
878; SI-NEXT:    v_or_b32_e32 v6, v6, v4
879; SI-NEXT:    v_and_b32_e32 v1, s12, v3
880; SI-NEXT:    v_and_b32_e32 v0, s12, v2
881; SI-NEXT:    v_and_b32_e32 v3, s13, v3
882; SI-NEXT:    v_and_b32_e32 v2, s13, v2
883; SI-NEXT:    v_and_b32_e32 v5, s12, v7
884; SI-NEXT:    v_and_b32_e32 v4, s12, v6
885; SI-NEXT:    v_and_b32_e32 v7, s13, v7
886; SI-NEXT:    v_and_b32_e32 v6, s13, v6
887; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
888; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 1
889; SI-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
890; SI-NEXT:    v_lshr_b64 v[6:7], v[6:7], 1
891; SI-NEXT:    v_or_b32_e32 v3, v3, v1
892; SI-NEXT:    v_or_b32_e32 v2, v2, v0
893; SI-NEXT:    v_or_b32_e32 v1, v7, v5
894; SI-NEXT:    v_or_b32_e32 v0, v6, v4
895; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
896; SI-NEXT:    s_endpgm
897;
898; FLAT-LABEL: v_brev_v2i64:
899; FLAT:       ; %bb.0:
900; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
901; FLAT-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
902; FLAT-NEXT:    v_lshlrev_b32_e32 v0, 4, v0
903; FLAT-NEXT:    v_mov_b32_e32 v8, 8
904; FLAT-NEXT:    s_mov_b32 s2, 0xff0000
905; FLAT-NEXT:    s_mov_b32 s3, 0xff000000
906; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
907; FLAT-NEXT:    v_mov_b32_e32 v1, s1
908; FLAT-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
909; FLAT-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
910; FLAT-NEXT:    flat_load_dwordx4 v[0:3], v[0:1]
911; FLAT-NEXT:    s_mov_b32 s0, 0xff00
912; FLAT-NEXT:    s_mov_b32 s1, 0xf0f0f0f
913; FLAT-NEXT:    s_mov_b32 s8, 0xf0f0f0f0
914; FLAT-NEXT:    s_mov_b32 s9, 0x33333333
915; FLAT-NEXT:    s_mov_b32 s10, 0xcccccccc
916; FLAT-NEXT:    s_mov_b32 s11, 0x55555555
917; FLAT-NEXT:    s_mov_b32 s12, 0xaaaaaaaa
918; FLAT-NEXT:    s_mov_b32 s7, 0xf000
919; FLAT-NEXT:    s_mov_b32 s6, -1
920; FLAT-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
921; FLAT-NEXT:    v_lshlrev_b64 v[4:5], 24, v[2:3]
922; FLAT-NEXT:    v_lshlrev_b32_sdwa v11, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
923; FLAT-NEXT:    v_lshlrev_b32_sdwa v14, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
924; FLAT-NEXT:    v_lshlrev_b64 v[8:9], 8, v[0:1]
925; FLAT-NEXT:    v_lshlrev_b64 v[6:7], 8, v[2:3]
926; FLAT-NEXT:    v_alignbit_b32 v4, v3, v2, 24
927; FLAT-NEXT:    v_alignbit_b32 v10, v3, v2, 8
928; FLAT-NEXT:    v_or_b32_sdwa v3, v11, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
929; FLAT-NEXT:    v_alignbit_b32 v12, v1, v0, 24
930; FLAT-NEXT:    v_alignbit_b32 v13, v1, v0, 8
931; FLAT-NEXT:    v_lshlrev_b32_e32 v8, 24, v0
932; FLAT-NEXT:    v_lshlrev_b32_e32 v15, 8, v0
933; FLAT-NEXT:    v_or_b32_sdwa v11, v14, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
934; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 24, v[0:1]
935; FLAT-NEXT:    v_lshlrev_b32_e32 v6, 24, v2
936; FLAT-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
937; FLAT-NEXT:    v_and_b32_e32 v0, s2, v4
938; FLAT-NEXT:    v_and_b32_e32 v4, s3, v10
939; FLAT-NEXT:    v_and_b32_e32 v2, s2, v2
940; FLAT-NEXT:    v_or_b32_e32 v0, v4, v0
941; FLAT-NEXT:    v_and_b32_e32 v1, s0, v1
942; FLAT-NEXT:    v_and_b32_e32 v10, s2, v12
943; FLAT-NEXT:    v_and_b32_e32 v12, s3, v13
944; FLAT-NEXT:    v_and_b32_e32 v4, s0, v5
945; FLAT-NEXT:    v_and_b32_e32 v13, s2, v15
946; FLAT-NEXT:    v_or_b32_e32 v5, v12, v10
947; FLAT-NEXT:    v_or_b32_e32 v2, v6, v2
948; FLAT-NEXT:    v_or_b32_e32 v3, v0, v3
949; FLAT-NEXT:    v_or_b32_sdwa v0, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
950; FLAT-NEXT:    v_or_b32_e32 v6, v8, v13
951; FLAT-NEXT:    v_or_b32_sdwa v1, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
952; FLAT-NEXT:    v_or_b32_e32 v7, v2, v0
953; FLAT-NEXT:    v_or_b32_e32 v5, v5, v11
954; FLAT-NEXT:    v_or_b32_e32 v8, v6, v1
955; FLAT-NEXT:    v_and_b32_e32 v0, s1, v3
956; FLAT-NEXT:    v_and_b32_e32 v1, s1, v7
957; FLAT-NEXT:    v_and_b32_e32 v2, s8, v3
958; FLAT-NEXT:    v_and_b32_e32 v3, s8, v7
959; FLAT-NEXT:    v_and_b32_e32 v4, s1, v5
960; FLAT-NEXT:    v_and_b32_e32 v6, s8, v5
961; FLAT-NEXT:    v_and_b32_e32 v5, s1, v8
962; FLAT-NEXT:    v_and_b32_e32 v7, s8, v8
963; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 4, v[0:1]
964; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 4, v[2:3]
965; FLAT-NEXT:    v_lshlrev_b64 v[4:5], 4, v[4:5]
966; FLAT-NEXT:    v_lshrrev_b64 v[6:7], 4, v[6:7]
967; FLAT-NEXT:    v_or_b32_e32 v3, v3, v1
968; FLAT-NEXT:    v_or_b32_e32 v2, v2, v0
969; FLAT-NEXT:    v_or_b32_e32 v7, v7, v5
970; FLAT-NEXT:    v_or_b32_e32 v6, v6, v4
971; FLAT-NEXT:    v_and_b32_e32 v1, s9, v3
972; FLAT-NEXT:    v_and_b32_e32 v0, s9, v2
973; FLAT-NEXT:    v_and_b32_e32 v5, s9, v7
974; FLAT-NEXT:    v_and_b32_e32 v4, s9, v6
975; FLAT-NEXT:    v_and_b32_e32 v3, s10, v3
976; FLAT-NEXT:    v_and_b32_e32 v2, s10, v2
977; FLAT-NEXT:    v_and_b32_e32 v7, s10, v7
978; FLAT-NEXT:    v_and_b32_e32 v6, s10, v6
979; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 2, v[0:1]
980; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 2, v[2:3]
981; FLAT-NEXT:    v_lshlrev_b64 v[4:5], 2, v[4:5]
982; FLAT-NEXT:    v_lshrrev_b64 v[6:7], 2, v[6:7]
983; FLAT-NEXT:    v_or_b32_e32 v3, v3, v1
984; FLAT-NEXT:    v_or_b32_e32 v2, v2, v0
985; FLAT-NEXT:    v_or_b32_e32 v7, v7, v5
986; FLAT-NEXT:    v_or_b32_e32 v6, v6, v4
987; FLAT-NEXT:    v_and_b32_e32 v1, s11, v3
988; FLAT-NEXT:    v_and_b32_e32 v0, s11, v2
989; FLAT-NEXT:    v_and_b32_e32 v5, s11, v7
990; FLAT-NEXT:    v_and_b32_e32 v4, s11, v6
991; FLAT-NEXT:    v_and_b32_e32 v3, s12, v3
992; FLAT-NEXT:    v_and_b32_e32 v2, s12, v2
993; FLAT-NEXT:    v_and_b32_e32 v7, s12, v7
994; FLAT-NEXT:    v_and_b32_e32 v6, s12, v6
995; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
996; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 1, v[2:3]
997; FLAT-NEXT:    v_lshlrev_b64 v[4:5], 1, v[4:5]
998; FLAT-NEXT:    v_lshrrev_b64 v[6:7], 1, v[6:7]
999; FLAT-NEXT:    v_or_b32_e32 v3, v3, v1
1000; FLAT-NEXT:    v_or_b32_e32 v2, v2, v0
1001; FLAT-NEXT:    v_or_b32_e32 v1, v7, v5
1002; FLAT-NEXT:    v_or_b32_e32 v0, v6, v4
1003; FLAT-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
1004; FLAT-NEXT:    s_endpgm
1005  %tid = call i32 @llvm.amdgcn.workitem.id.x()
1006  %gep = getelementptr <2 x i64> , <2 x i64> addrspace(1)* %valptr, i32 %tid
1007  %val = load <2 x i64>, <2 x i64> addrspace(1)* %gep
1008  %brev = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %val) #1
1009  store <2 x i64> %brev, <2 x i64> addrspace(1)* %out
1010  ret void
1011}
1012
1013define float @missing_truncate_promote_bitreverse(i32 %arg) {
1014; SI-LABEL: missing_truncate_promote_bitreverse:
1015; SI:       ; %bb.0: ; %bb
1016; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1017; SI-NEXT:    v_bfrev_b32_e32 v0, v0
1018; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
1019; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
1020; SI-NEXT:    s_setpc_b64 s[30:31]
1021;
1022; FLAT-LABEL: missing_truncate_promote_bitreverse:
1023; FLAT:       ; %bb.0: ; %bb
1024; FLAT-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1025; FLAT-NEXT:    v_bfrev_b32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
1026; FLAT-NEXT:    v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
1027; FLAT-NEXT:    s_setpc_b64 s[30:31]
1028bb:
1029  %tmp = trunc i32 %arg to i16
1030  %tmp1 = call i16 @llvm.bitreverse.i16(i16 %tmp)
1031  %tmp2 = bitcast i16 %tmp1 to half
1032  %tmp3 = fpext half %tmp2 to float
1033  ret float %tmp3
1034}
1035
1036attributes #0 = { nounwind }
1037attributes #1 = { nounwind readnone }
1038