1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs | FileCheck %s --check-prefixes=FUNC,SI
3; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=FUNC,FLAT,TONGA
4; RUN: llc < %s -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=FUNC,FLAT,VI
5
6declare i32 @llvm.amdgcn.workitem.id.x() #1
7
8declare i16 @llvm.bitreverse.i16(i16) #1
9declare i32 @llvm.bitreverse.i32(i32) #1
10declare i64 @llvm.bitreverse.i64(i64) #1
11
12declare <2 x i32> @llvm.bitreverse.v2i32(<2 x i32>) #1
13declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>) #1
14
15declare <2 x i64> @llvm.bitreverse.v2i64(<2 x i64>) #1
16declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>) #1
17
18define amdgpu_kernel void @s_brev_i16(i16 addrspace(1)* noalias %out, i16 %val) #0 {
19; SI-LABEL: s_brev_i16:
20; SI:       ; %bb.0:
21; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
22; SI-NEXT:    s_load_dword s0, s[0:1], 0xb
23; SI-NEXT:    s_mov_b32 s7, 0xf000
24; SI-NEXT:    s_mov_b32 s6, -1
25; SI-NEXT:    s_waitcnt lgkmcnt(0)
26; SI-NEXT:    s_brev_b32 s0, s0
27; SI-NEXT:    s_lshr_b32 s0, s0, 16
28; SI-NEXT:    v_mov_b32_e32 v0, s0
29; SI-NEXT:    buffer_store_short v0, off, s[4:7], 0
30; SI-NEXT:    s_endpgm
31;
32; FLAT-LABEL: s_brev_i16:
33; FLAT:       ; %bb.0:
34; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
35; FLAT-NEXT:    s_load_dword s0, s[0:1], 0x2c
36; FLAT-NEXT:    s_mov_b32 s7, 0xf000
37; FLAT-NEXT:    s_mov_b32 s6, -1
38; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
39; FLAT-NEXT:    s_and_b32 s0, s0, 0xffff
40; FLAT-NEXT:    s_brev_b32 s0, s0
41; FLAT-NEXT:    s_lshr_b32 s0, s0, 16
42; FLAT-NEXT:    v_mov_b32_e32 v0, s0
43; FLAT-NEXT:    buffer_store_short v0, off, s[4:7], 0
44; FLAT-NEXT:    s_endpgm
45  %brev = call i16 @llvm.bitreverse.i16(i16 %val) #1
46  store i16 %brev, i16 addrspace(1)* %out
47  ret void
48}
49
50define amdgpu_kernel void @v_brev_i16(i16 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %valptr) #0 {
51; SI-LABEL: v_brev_i16:
52; SI:       ; %bb.0:
53; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
54; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
55; SI-NEXT:    s_mov_b32 s7, 0xf000
56; SI-NEXT:    s_mov_b32 s6, -1
57; SI-NEXT:    s_mov_b32 s2, s6
58; SI-NEXT:    s_mov_b32 s3, s7
59; SI-NEXT:    s_waitcnt lgkmcnt(0)
60; SI-NEXT:    buffer_load_ushort v0, off, s[0:3], 0
61; SI-NEXT:    s_waitcnt vmcnt(0)
62; SI-NEXT:    v_bfrev_b32_e32 v0, v0
63; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
64; SI-NEXT:    buffer_store_short v0, off, s[4:7], 0
65; SI-NEXT:    s_endpgm
66;
67; FLAT-LABEL: v_brev_i16:
68; FLAT:       ; %bb.0:
69; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
70; FLAT-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
71; FLAT-NEXT:    s_mov_b32 s7, 0xf000
72; FLAT-NEXT:    s_mov_b32 s6, -1
73; FLAT-NEXT:    s_mov_b32 s2, s6
74; FLAT-NEXT:    s_mov_b32 s3, s7
75; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
76; FLAT-NEXT:    buffer_load_ushort v0, off, s[0:3], 0
77; FLAT-NEXT:    s_waitcnt vmcnt(0)
78; FLAT-NEXT:    v_bfrev_b32_e32 v0, v0
79; FLAT-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
80; FLAT-NEXT:    buffer_store_short v0, off, s[4:7], 0
81; FLAT-NEXT:    s_endpgm
82  %val = load i16, i16 addrspace(1)* %valptr
83  %brev = call i16 @llvm.bitreverse.i16(i16 %val) #1
84  store i16 %brev, i16 addrspace(1)* %out
85  ret void
86}
87
88define amdgpu_kernel void @s_brev_i32(i32 addrspace(1)* noalias %out, i32 %val) #0 {
89; SI-LABEL: s_brev_i32:
90; SI:       ; %bb.0:
91; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
92; SI-NEXT:    s_load_dword s0, s[0:1], 0xb
93; SI-NEXT:    s_mov_b32 s7, 0xf000
94; SI-NEXT:    s_mov_b32 s6, -1
95; SI-NEXT:    s_waitcnt lgkmcnt(0)
96; SI-NEXT:    s_brev_b32 s0, s0
97; SI-NEXT:    v_mov_b32_e32 v0, s0
98; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
99; SI-NEXT:    s_endpgm
100;
101; FLAT-LABEL: s_brev_i32:
102; FLAT:       ; %bb.0:
103; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
104; FLAT-NEXT:    s_load_dword s0, s[0:1], 0x2c
105; FLAT-NEXT:    s_mov_b32 s7, 0xf000
106; FLAT-NEXT:    s_mov_b32 s6, -1
107; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
108; FLAT-NEXT:    s_brev_b32 s0, s0
109; FLAT-NEXT:    v_mov_b32_e32 v0, s0
110; FLAT-NEXT:    buffer_store_dword v0, off, s[4:7], 0
111; FLAT-NEXT:    s_endpgm
112  %brev = call i32 @llvm.bitreverse.i32(i32 %val) #1
113  store i32 %brev, i32 addrspace(1)* %out
114  ret void
115}
116
117define amdgpu_kernel void @v_brev_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) #0 {
118; SI-LABEL: v_brev_i32:
119; SI:       ; %bb.0:
120; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
121; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
122; SI-NEXT:    s_mov_b32 s7, 0xf000
123; SI-NEXT:    s_mov_b32 s2, 0
124; SI-NEXT:    s_mov_b32 s3, s7
125; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
126; SI-NEXT:    v_mov_b32_e32 v1, 0
127; SI-NEXT:    s_waitcnt lgkmcnt(0)
128; SI-NEXT:    buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
129; SI-NEXT:    s_mov_b32 s6, -1
130; SI-NEXT:    s_waitcnt vmcnt(0)
131; SI-NEXT:    v_bfrev_b32_e32 v0, v0
132; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
133; SI-NEXT:    s_endpgm
134;
135; FLAT-LABEL: v_brev_i32:
136; FLAT:       ; %bb.0:
137; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
138; FLAT-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
139; FLAT-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
140; FLAT-NEXT:    s_mov_b32 s7, 0xf000
141; FLAT-NEXT:    s_mov_b32 s6, -1
142; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
143; FLAT-NEXT:    v_mov_b32_e32 v1, s1
144; FLAT-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
145; FLAT-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
146; FLAT-NEXT:    flat_load_dword v0, v[0:1]
147; FLAT-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
148; FLAT-NEXT:    v_bfrev_b32_e32 v0, v0
149; FLAT-NEXT:    buffer_store_dword v0, off, s[4:7], 0
150; FLAT-NEXT:    s_endpgm
151  %tid = call i32 @llvm.amdgcn.workitem.id.x()
152  %gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
153  %val = load i32, i32 addrspace(1)* %gep
154  %brev = call i32 @llvm.bitreverse.i32(i32 %val) #1
155  store i32 %brev, i32 addrspace(1)* %out
156  ret void
157}
158
159define amdgpu_kernel void @s_brev_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> %val) #0 {
160; SI-LABEL: s_brev_v2i32:
161; SI:       ; %bb.0:
162; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
163; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
164; SI-NEXT:    s_mov_b32 s7, 0xf000
165; SI-NEXT:    s_mov_b32 s6, -1
166; SI-NEXT:    s_waitcnt lgkmcnt(0)
167; SI-NEXT:    s_brev_b32 s1, s1
168; SI-NEXT:    s_brev_b32 s0, s0
169; SI-NEXT:    v_mov_b32_e32 v0, s0
170; SI-NEXT:    v_mov_b32_e32 v1, s1
171; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
172; SI-NEXT:    s_endpgm
173;
174; FLAT-LABEL: s_brev_v2i32:
175; FLAT:       ; %bb.0:
176; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
177; FLAT-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
178; FLAT-NEXT:    s_mov_b32 s7, 0xf000
179; FLAT-NEXT:    s_mov_b32 s6, -1
180; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
181; FLAT-NEXT:    s_brev_b32 s1, s1
182; FLAT-NEXT:    s_brev_b32 s0, s0
183; FLAT-NEXT:    v_mov_b32_e32 v0, s0
184; FLAT-NEXT:    v_mov_b32_e32 v1, s1
185; FLAT-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
186; FLAT-NEXT:    s_endpgm
187  %brev = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %val) #1
188  store <2 x i32> %brev, <2 x i32> addrspace(1)* %out
189  ret void
190}
191
192define amdgpu_kernel void @v_brev_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) #0 {
193; SI-LABEL: v_brev_v2i32:
194; SI:       ; %bb.0:
195; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
196; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
197; SI-NEXT:    s_mov_b32 s7, 0xf000
198; SI-NEXT:    s_mov_b32 s2, 0
199; SI-NEXT:    s_mov_b32 s3, s7
200; SI-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
201; SI-NEXT:    v_mov_b32_e32 v1, 0
202; SI-NEXT:    s_waitcnt lgkmcnt(0)
203; SI-NEXT:    buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 addr64
204; SI-NEXT:    s_mov_b32 s6, -1
205; SI-NEXT:    s_waitcnt vmcnt(0)
206; SI-NEXT:    v_bfrev_b32_e32 v1, v1
207; SI-NEXT:    v_bfrev_b32_e32 v0, v0
208; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
209; SI-NEXT:    s_endpgm
210;
211; FLAT-LABEL: v_brev_v2i32:
212; FLAT:       ; %bb.0:
213; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
214; FLAT-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
215; FLAT-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
216; FLAT-NEXT:    s_mov_b32 s7, 0xf000
217; FLAT-NEXT:    s_mov_b32 s6, -1
218; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
219; FLAT-NEXT:    v_mov_b32_e32 v1, s1
220; FLAT-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
221; FLAT-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
222; FLAT-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
223; FLAT-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
224; FLAT-NEXT:    v_bfrev_b32_e32 v1, v1
225; FLAT-NEXT:    v_bfrev_b32_e32 v0, v0
226; FLAT-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
227; FLAT-NEXT:    s_endpgm
228  %tid = call i32 @llvm.amdgcn.workitem.id.x()
229  %gep = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %valptr, i32 %tid
230  %val = load <2 x i32>, <2 x i32> addrspace(1)* %gep
231  %brev = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %val) #1
232  store <2 x i32> %brev, <2 x i32> addrspace(1)* %out
233  ret void
234}
235
236define amdgpu_kernel void @s_brev_i64(i64 addrspace(1)* noalias %out, i64 %val) #0 {
237; SI-LABEL: s_brev_i64:
238; SI:       ; %bb.0:
239; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
240; SI-NEXT:    s_mov_b32 s3, 0
241; SI-NEXT:    s_mov_b32 s10, 0xff0000
242; SI-NEXT:    s_mov_b32 s11, 0xff00
243; SI-NEXT:    s_mov_b32 s7, s3
244; SI-NEXT:    s_waitcnt lgkmcnt(0)
245; SI-NEXT:    v_mov_b32_e32 v0, s4
246; SI-NEXT:    v_alignbit_b32 v1, s5, v0, 24
247; SI-NEXT:    v_alignbit_b32 v0, s5, v0, 8
248; SI-NEXT:    s_lshr_b32 s6, s5, 8
249; SI-NEXT:    v_and_b32_e32 v1, s10, v1
250; SI-NEXT:    v_and_b32_e32 v0, 0xff000000, v0
251; SI-NEXT:    s_lshr_b32 s2, s5, 24
252; SI-NEXT:    s_and_b32 s6, s6, s11
253; SI-NEXT:    s_or_b64 s[6:7], s[6:7], s[2:3]
254; SI-NEXT:    v_or_b32_e32 v0, v0, v1
255; SI-NEXT:    s_lshl_b64 s[8:9], s[4:5], 24
256; SI-NEXT:    v_or_b32_e32 v0, s6, v0
257; SI-NEXT:    v_mov_b32_e32 v1, s7
258; SI-NEXT:    s_lshl_b64 s[6:7], s[4:5], 8
259; SI-NEXT:    s_lshl_b32 s2, s4, 8
260; SI-NEXT:    s_and_b32 s7, s7, 0xff
261; SI-NEXT:    s_mov_b32 s6, s3
262; SI-NEXT:    s_and_b32 s9, s9, s11
263; SI-NEXT:    s_mov_b32 s8, s3
264; SI-NEXT:    s_or_b64 s[6:7], s[8:9], s[6:7]
265; SI-NEXT:    s_lshl_b32 s9, s4, 24
266; SI-NEXT:    s_and_b32 s5, s2, s10
267; SI-NEXT:    s_mov_b32 s4, s3
268; SI-NEXT:    s_or_b64 s[2:3], s[8:9], s[4:5]
269; SI-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
270; SI-NEXT:    v_or_b32_e32 v2, s2, v0
271; SI-NEXT:    v_or_b32_e32 v3, s3, v1
272; SI-NEXT:    s_mov_b32 s2, 0xf0f0f0f
273; SI-NEXT:    v_and_b32_e32 v1, s2, v3
274; SI-NEXT:    v_and_b32_e32 v0, s2, v2
275; SI-NEXT:    s_mov_b32 s2, 0xf0f0f0f0
276; SI-NEXT:    v_and_b32_e32 v3, s2, v3
277; SI-NEXT:    v_and_b32_e32 v2, s2, v2
278; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 4
279; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 4
280; SI-NEXT:    s_mov_b32 s2, 0x33333333
281; SI-NEXT:    v_or_b32_e32 v2, v2, v0
282; SI-NEXT:    v_or_b32_e32 v3, v3, v1
283; SI-NEXT:    v_and_b32_e32 v1, s2, v3
284; SI-NEXT:    v_and_b32_e32 v0, s2, v2
285; SI-NEXT:    s_mov_b32 s2, 0xcccccccc
286; SI-NEXT:    v_and_b32_e32 v3, s2, v3
287; SI-NEXT:    v_and_b32_e32 v2, s2, v2
288; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 2
289; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 2
290; SI-NEXT:    s_mov_b32 s2, 0x55555555
291; SI-NEXT:    v_or_b32_e32 v2, v2, v0
292; SI-NEXT:    v_or_b32_e32 v3, v3, v1
293; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
294; SI-NEXT:    v_and_b32_e32 v1, s2, v3
295; SI-NEXT:    v_and_b32_e32 v0, s2, v2
296; SI-NEXT:    s_mov_b32 s2, 0xaaaaaaaa
297; SI-NEXT:    v_and_b32_e32 v3, s2, v3
298; SI-NEXT:    v_and_b32_e32 v2, s2, v2
299; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
300; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 1
301; SI-NEXT:    s_mov_b32 s3, 0xf000
302; SI-NEXT:    s_mov_b32 s2, -1
303; SI-NEXT:    v_or_b32_e32 v0, v2, v0
304; SI-NEXT:    v_or_b32_e32 v1, v3, v1
305; SI-NEXT:    s_waitcnt lgkmcnt(0)
306; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
307; SI-NEXT:    s_endpgm
308;
309; FLAT-LABEL: s_brev_i64:
310; FLAT:       ; %bb.0:
311; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
312; FLAT-NEXT:    s_mov_b32 s3, 0
313; FLAT-NEXT:    s_mov_b32 s10, 0xff0000
314; FLAT-NEXT:    s_mov_b32 s7, s3
315; FLAT-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
316; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
317; FLAT-NEXT:    v_mov_b32_e32 v0, s4
318; FLAT-NEXT:    v_alignbit_b32 v1, s5, v0, 24
319; FLAT-NEXT:    v_alignbit_b32 v0, s5, v0, 8
320; FLAT-NEXT:    s_bfe_u32 s6, s5, 0x80010
321; FLAT-NEXT:    v_and_b32_e32 v1, s10, v1
322; FLAT-NEXT:    v_and_b32_e32 v0, 0xff000000, v0
323; FLAT-NEXT:    s_lshr_b32 s2, s5, 24
324; FLAT-NEXT:    s_lshl_b32 s6, s6, 8
325; FLAT-NEXT:    s_or_b64 s[6:7], s[6:7], s[2:3]
326; FLAT-NEXT:    v_or_b32_e32 v0, v0, v1
327; FLAT-NEXT:    s_lshl_b64 s[8:9], s[4:5], 24
328; FLAT-NEXT:    v_or_b32_e32 v0, s6, v0
329; FLAT-NEXT:    v_mov_b32_e32 v1, s7
330; FLAT-NEXT:    s_lshl_b64 s[6:7], s[4:5], 8
331; FLAT-NEXT:    s_lshl_b32 s2, s4, 8
332; FLAT-NEXT:    s_and_b32 s7, s7, 0xff
333; FLAT-NEXT:    s_mov_b32 s6, s3
334; FLAT-NEXT:    s_and_b32 s9, s9, 0xff00
335; FLAT-NEXT:    s_mov_b32 s8, s3
336; FLAT-NEXT:    s_or_b64 s[6:7], s[8:9], s[6:7]
337; FLAT-NEXT:    s_lshl_b32 s9, s4, 24
338; FLAT-NEXT:    s_and_b32 s5, s2, s10
339; FLAT-NEXT:    s_mov_b32 s4, s3
340; FLAT-NEXT:    s_or_b64 s[2:3], s[8:9], s[4:5]
341; FLAT-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
342; FLAT-NEXT:    v_or_b32_e32 v2, s2, v0
343; FLAT-NEXT:    v_or_b32_e32 v3, s3, v1
344; FLAT-NEXT:    s_mov_b32 s2, 0xf0f0f0f
345; FLAT-NEXT:    v_and_b32_e32 v1, s2, v3
346; FLAT-NEXT:    v_and_b32_e32 v0, s2, v2
347; FLAT-NEXT:    s_mov_b32 s2, 0xf0f0f0f0
348; FLAT-NEXT:    v_and_b32_e32 v3, s2, v3
349; FLAT-NEXT:    v_and_b32_e32 v2, s2, v2
350; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 4, v[0:1]
351; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 4, v[2:3]
352; FLAT-NEXT:    s_mov_b32 s2, 0x33333333
353; FLAT-NEXT:    v_or_b32_e32 v2, v2, v0
354; FLAT-NEXT:    v_or_b32_e32 v3, v3, v1
355; FLAT-NEXT:    v_and_b32_e32 v1, s2, v3
356; FLAT-NEXT:    v_and_b32_e32 v0, s2, v2
357; FLAT-NEXT:    s_mov_b32 s2, 0xcccccccc
358; FLAT-NEXT:    v_and_b32_e32 v3, s2, v3
359; FLAT-NEXT:    v_and_b32_e32 v2, s2, v2
360; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 2, v[0:1]
361; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 2, v[2:3]
362; FLAT-NEXT:    s_mov_b32 s2, 0x55555555
363; FLAT-NEXT:    v_or_b32_e32 v2, v2, v0
364; FLAT-NEXT:    v_or_b32_e32 v3, v3, v1
365; FLAT-NEXT:    v_and_b32_e32 v1, s2, v3
366; FLAT-NEXT:    v_and_b32_e32 v0, s2, v2
367; FLAT-NEXT:    s_mov_b32 s2, 0xaaaaaaaa
368; FLAT-NEXT:    v_and_b32_e32 v3, s2, v3
369; FLAT-NEXT:    v_and_b32_e32 v2, s2, v2
370; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
371; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 1, v[2:3]
372; FLAT-NEXT:    s_mov_b32 s3, 0xf000
373; FLAT-NEXT:    s_mov_b32 s2, -1
374; FLAT-NEXT:    v_or_b32_e32 v0, v2, v0
375; FLAT-NEXT:    v_or_b32_e32 v1, v3, v1
376; FLAT-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
377; FLAT-NEXT:    s_endpgm
378  %brev = call i64 @llvm.bitreverse.i64(i64 %val) #1
379  store i64 %brev, i64 addrspace(1)* %out
380  ret void
381}
382
383define amdgpu_kernel void @v_brev_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %valptr) #0 {
384; SI-LABEL: v_brev_i64:
385; SI:       ; %bb.0:
386; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
387; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
388; SI-NEXT:    s_mov_b32 s7, 0xf000
389; SI-NEXT:    s_mov_b32 s2, 0
390; SI-NEXT:    s_mov_b32 s3, s7
391; SI-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
392; SI-NEXT:    v_mov_b32_e32 v1, 0
393; SI-NEXT:    s_waitcnt lgkmcnt(0)
394; SI-NEXT:    buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 addr64
395; SI-NEXT:    s_mov_b32 s0, 0xff0000
396; SI-NEXT:    s_mov_b32 s1, 0xff00
397; SI-NEXT:    s_mov_b32 s2, 0xf0f0f0f
398; SI-NEXT:    s_mov_b32 s3, 0xf0f0f0f0
399; SI-NEXT:    s_mov_b32 s6, 0x33333333
400; SI-NEXT:    s_mov_b32 s8, 0xcccccccc
401; SI-NEXT:    s_mov_b32 s9, 0x55555555
402; SI-NEXT:    s_mov_b32 s10, 0xaaaaaaaa
403; SI-NEXT:    s_waitcnt vmcnt(0)
404; SI-NEXT:    v_lshl_b64 v[2:3], v[0:1], 8
405; SI-NEXT:    v_alignbit_b32 v4, v1, v0, 24
406; SI-NEXT:    v_alignbit_b32 v5, v1, v0, 8
407; SI-NEXT:    v_lshrrev_b32_e32 v7, 8, v1
408; SI-NEXT:    v_lshrrev_b32_e32 v6, 24, v1
409; SI-NEXT:    v_lshl_b64 v[1:2], v[0:1], 24
410; SI-NEXT:    v_lshlrev_b32_e32 v1, 24, v0
411; SI-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
412; SI-NEXT:    v_and_b32_e32 v0, s0, v0
413; SI-NEXT:    v_and_b32_e32 v4, s0, v4
414; SI-NEXT:    v_and_b32_e32 v5, 0xff000000, v5
415; SI-NEXT:    v_and_b32_e32 v7, s1, v7
416; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
417; SI-NEXT:    v_and_b32_e32 v2, s1, v2
418; SI-NEXT:    v_or_b32_e32 v4, v5, v4
419; SI-NEXT:    v_or_b32_e32 v5, v7, v6
420; SI-NEXT:    v_or_b32_e32 v0, v1, v0
421; SI-NEXT:    v_or_b32_e32 v2, v2, v3
422; SI-NEXT:    v_or_b32_e32 v1, v4, v5
423; SI-NEXT:    v_or_b32_e32 v3, v0, v2
424; SI-NEXT:    v_and_b32_e32 v0, s2, v1
425; SI-NEXT:    v_and_b32_e32 v2, s3, v1
426; SI-NEXT:    v_and_b32_e32 v1, s2, v3
427; SI-NEXT:    v_and_b32_e32 v3, s3, v3
428; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 4
429; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 4
430; SI-NEXT:    v_or_b32_e32 v3, v3, v1
431; SI-NEXT:    v_or_b32_e32 v2, v2, v0
432; SI-NEXT:    v_and_b32_e32 v1, s6, v3
433; SI-NEXT:    v_and_b32_e32 v0, s6, v2
434; SI-NEXT:    v_and_b32_e32 v3, s8, v3
435; SI-NEXT:    v_and_b32_e32 v2, s8, v2
436; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 2
437; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 2
438; SI-NEXT:    s_mov_b32 s6, -1
439; SI-NEXT:    v_or_b32_e32 v3, v3, v1
440; SI-NEXT:    v_or_b32_e32 v2, v2, v0
441; SI-NEXT:    v_and_b32_e32 v1, s9, v3
442; SI-NEXT:    v_and_b32_e32 v0, s9, v2
443; SI-NEXT:    v_and_b32_e32 v3, s10, v3
444; SI-NEXT:    v_and_b32_e32 v2, s10, v2
445; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
446; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 1
447; SI-NEXT:    v_or_b32_e32 v1, v3, v1
448; SI-NEXT:    v_or_b32_e32 v0, v2, v0
449; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
450; SI-NEXT:    s_endpgm
451;
452; FLAT-LABEL: v_brev_i64:
453; FLAT:       ; %bb.0:
454; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
455; FLAT-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
456; FLAT-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
457; FLAT-NEXT:    v_mov_b32_e32 v4, 8
458; FLAT-NEXT:    s_mov_b32 s2, 0xff0000
459; FLAT-NEXT:    s_mov_b32 s3, 0xf0f0f0f
460; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
461; FLAT-NEXT:    v_mov_b32_e32 v1, s1
462; FLAT-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
463; FLAT-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
464; FLAT-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
465; FLAT-NEXT:    s_mov_b32 s0, 0xf0f0f0f0
466; FLAT-NEXT:    s_mov_b32 s1, 0x33333333
467; FLAT-NEXT:    s_mov_b32 s6, 0xcccccccc
468; FLAT-NEXT:    s_mov_b32 s8, 0x55555555
469; FLAT-NEXT:    s_mov_b32 s9, 0xaaaaaaaa
470; FLAT-NEXT:    s_mov_b32 s7, 0xf000
471; FLAT-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
472; FLAT-NEXT:    v_lshlrev_b64 v[2:3], 24, v[0:1]
473; FLAT-NEXT:    v_alignbit_b32 v2, v1, v0, 24
474; FLAT-NEXT:    v_alignbit_b32 v6, v1, v0, 8
475; FLAT-NEXT:    v_lshlrev_b32_sdwa v7, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
476; FLAT-NEXT:    v_lshlrev_b64 v[4:5], 8, v[0:1]
477; FLAT-NEXT:    v_lshlrev_b32_e32 v4, 24, v0
478; FLAT-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
479; FLAT-NEXT:    v_and_b32_e32 v2, s2, v2
480; FLAT-NEXT:    v_and_b32_e32 v6, 0xff000000, v6
481; FLAT-NEXT:    v_and_b32_e32 v0, s2, v0
482; FLAT-NEXT:    v_or_b32_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
483; FLAT-NEXT:    v_or_b32_e32 v2, v6, v2
484; FLAT-NEXT:    v_and_b32_e32 v3, 0xff00, v3
485; FLAT-NEXT:    v_or_b32_e32 v1, v2, v1
486; FLAT-NEXT:    v_or_b32_e32 v0, v4, v0
487; FLAT-NEXT:    v_or_b32_sdwa v2, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
488; FLAT-NEXT:    v_or_b32_e32 v3, v0, v2
489; FLAT-NEXT:    v_and_b32_e32 v0, s3, v1
490; FLAT-NEXT:    v_and_b32_e32 v2, s0, v1
491; FLAT-NEXT:    v_and_b32_e32 v1, s3, v3
492; FLAT-NEXT:    v_and_b32_e32 v3, s0, v3
493; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 4, v[0:1]
494; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 4, v[2:3]
495; FLAT-NEXT:    v_or_b32_e32 v3, v3, v1
496; FLAT-NEXT:    v_or_b32_e32 v2, v2, v0
497; FLAT-NEXT:    v_and_b32_e32 v1, s1, v3
498; FLAT-NEXT:    v_and_b32_e32 v0, s1, v2
499; FLAT-NEXT:    v_and_b32_e32 v3, s6, v3
500; FLAT-NEXT:    v_and_b32_e32 v2, s6, v2
501; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 2, v[0:1]
502; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 2, v[2:3]
503; FLAT-NEXT:    s_mov_b32 s6, -1
504; FLAT-NEXT:    v_or_b32_e32 v3, v3, v1
505; FLAT-NEXT:    v_or_b32_e32 v2, v2, v0
506; FLAT-NEXT:    v_and_b32_e32 v1, s8, v3
507; FLAT-NEXT:    v_and_b32_e32 v0, s8, v2
508; FLAT-NEXT:    v_and_b32_e32 v3, s9, v3
509; FLAT-NEXT:    v_and_b32_e32 v2, s9, v2
510; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
511; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 1, v[2:3]
512; FLAT-NEXT:    v_or_b32_e32 v1, v3, v1
513; FLAT-NEXT:    v_or_b32_e32 v0, v2, v0
514; FLAT-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
515; FLAT-NEXT:    s_endpgm
516  %tid = call i32 @llvm.amdgcn.workitem.id.x()
517  %gep = getelementptr i64, i64 addrspace(1)* %valptr, i32 %tid
518  %val = load i64, i64 addrspace(1)* %gep
519  %brev = call i64 @llvm.bitreverse.i64(i64 %val) #1
520  store i64 %brev, i64 addrspace(1)* %out
521  ret void
522}
523
524define amdgpu_kernel void @s_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %val) #0 {
525; SI-LABEL: s_brev_v2i64:
526; SI:       ; %bb.0:
527; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
528; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
529; SI-NEXT:    s_mov_b32 s9, 0
530; SI-NEXT:    s_mov_b32 s12, 0xff0000
531; SI-NEXT:    s_mov_b32 s13, 0xff000000
532; SI-NEXT:    s_mov_b32 s14, 0xff00
533; SI-NEXT:    s_waitcnt lgkmcnt(0)
534; SI-NEXT:    v_mov_b32_e32 v0, s2
535; SI-NEXT:    v_alignbit_b32 v1, s3, v0, 24
536; SI-NEXT:    v_alignbit_b32 v0, s3, v0, 8
537; SI-NEXT:    s_lshr_b32 s6, s3, 8
538; SI-NEXT:    v_and_b32_e32 v1, s12, v1
539; SI-NEXT:    v_and_b32_e32 v0, s13, v0
540; SI-NEXT:    s_lshr_b32 s8, s3, 24
541; SI-NEXT:    s_and_b32 s6, s6, s14
542; SI-NEXT:    s_mov_b32 s7, s9
543; SI-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
544; SI-NEXT:    v_or_b32_e32 v0, v0, v1
545; SI-NEXT:    s_lshl_b32 s8, s2, 8
546; SI-NEXT:    v_or_b32_e32 v0, s6, v0
547; SI-NEXT:    v_mov_b32_e32 v1, s7
548; SI-NEXT:    s_and_b32 s11, s8, s12
549; SI-NEXT:    s_lshl_b32 s7, s2, 24
550; SI-NEXT:    s_mov_b32 s6, s9
551; SI-NEXT:    s_mov_b32 s10, s9
552; SI-NEXT:    s_or_b64 s[6:7], s[6:7], s[10:11]
553; SI-NEXT:    s_lshl_b64 s[10:11], s[2:3], 8
554; SI-NEXT:    s_lshl_b64 s[2:3], s[2:3], 24
555; SI-NEXT:    s_movk_i32 s15, 0xff
556; SI-NEXT:    s_and_b32 s11, s11, s15
557; SI-NEXT:    s_mov_b32 s10, s9
558; SI-NEXT:    s_and_b32 s3, s3, s14
559; SI-NEXT:    s_mov_b32 s2, s9
560; SI-NEXT:    s_or_b64 s[2:3], s[2:3], s[10:11]
561; SI-NEXT:    s_or_b64 s[2:3], s[6:7], s[2:3]
562; SI-NEXT:    v_mov_b32_e32 v4, s0
563; SI-NEXT:    v_alignbit_b32 v5, s1, v4, 24
564; SI-NEXT:    v_alignbit_b32 v4, s1, v4, 8
565; SI-NEXT:    v_or_b32_e32 v2, s2, v0
566; SI-NEXT:    s_lshr_b32 s2, s1, 8
567; SI-NEXT:    v_or_b32_e32 v3, s3, v1
568; SI-NEXT:    v_and_b32_e32 v5, s12, v5
569; SI-NEXT:    v_and_b32_e32 v4, s13, v4
570; SI-NEXT:    s_lshr_b32 s8, s1, 24
571; SI-NEXT:    s_and_b32 s2, s2, s14
572; SI-NEXT:    s_mov_b32 s3, s9
573; SI-NEXT:    s_or_b64 s[2:3], s[2:3], s[8:9]
574; SI-NEXT:    v_or_b32_e32 v4, v4, v5
575; SI-NEXT:    s_lshl_b32 s8, s0, 8
576; SI-NEXT:    v_or_b32_e32 v4, s2, v4
577; SI-NEXT:    v_mov_b32_e32 v5, s3
578; SI-NEXT:    s_lshl_b32 s3, s0, 24
579; SI-NEXT:    s_mov_b32 s2, s9
580; SI-NEXT:    s_and_b32 s11, s8, s12
581; SI-NEXT:    s_mov_b32 s16, 0xf0f0f0f
582; SI-NEXT:    s_or_b64 s[2:3], s[2:3], s[10:11]
583; SI-NEXT:    s_lshl_b64 s[10:11], s[0:1], 8
584; SI-NEXT:    s_lshl_b64 s[0:1], s[0:1], 24
585; SI-NEXT:    s_mov_b32 s17, 0xf0f0f0f0
586; SI-NEXT:    v_and_b32_e32 v0, s16, v2
587; SI-NEXT:    v_and_b32_e32 v1, s16, v3
588; SI-NEXT:    v_and_b32_e32 v2, s17, v2
589; SI-NEXT:    v_and_b32_e32 v3, s17, v3
590; SI-NEXT:    s_and_b32 s11, s11, s15
591; SI-NEXT:    s_mov_b32 s10, s9
592; SI-NEXT:    s_and_b32 s1, s1, s14
593; SI-NEXT:    s_mov_b32 s0, s9
594; SI-NEXT:    s_or_b64 s[0:1], s[0:1], s[10:11]
595; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 4
596; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 4
597; SI-NEXT:    s_or_b64 s[0:1], s[2:3], s[0:1]
598; SI-NEXT:    v_or_b32_e32 v6, s0, v4
599; SI-NEXT:    v_or_b32_e32 v7, s1, v5
600; SI-NEXT:    v_or_b32_e32 v2, v2, v0
601; SI-NEXT:    s_mov_b32 s18, 0x33333333
602; SI-NEXT:    v_or_b32_e32 v3, v3, v1
603; SI-NEXT:    s_mov_b32 s19, 0xcccccccc
604; SI-NEXT:    v_and_b32_e32 v0, s18, v2
605; SI-NEXT:    v_and_b32_e32 v1, s18, v3
606; SI-NEXT:    v_and_b32_e32 v4, s16, v6
607; SI-NEXT:    v_and_b32_e32 v5, s16, v7
608; SI-NEXT:    v_and_b32_e32 v2, s19, v2
609; SI-NEXT:    v_and_b32_e32 v3, s19, v3
610; SI-NEXT:    v_and_b32_e32 v6, s17, v6
611; SI-NEXT:    v_and_b32_e32 v7, s17, v7
612; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 2
613; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 2
614; SI-NEXT:    v_lshl_b64 v[4:5], v[4:5], 4
615; SI-NEXT:    v_lshr_b64 v[6:7], v[6:7], 4
616; SI-NEXT:    v_or_b32_e32 v2, v2, v0
617; SI-NEXT:    v_or_b32_e32 v6, v6, v4
618; SI-NEXT:    v_or_b32_e32 v7, v7, v5
619; SI-NEXT:    s_mov_b32 s20, 0x55555555
620; SI-NEXT:    v_or_b32_e32 v3, v3, v1
621; SI-NEXT:    s_mov_b32 s21, 0xaaaaaaaa
622; SI-NEXT:    v_and_b32_e32 v0, s20, v2
623; SI-NEXT:    v_and_b32_e32 v1, s20, v3
624; SI-NEXT:    v_and_b32_e32 v4, s18, v6
625; SI-NEXT:    v_and_b32_e32 v5, s18, v7
626; SI-NEXT:    v_and_b32_e32 v2, s21, v2
627; SI-NEXT:    v_and_b32_e32 v3, s21, v3
628; SI-NEXT:    v_and_b32_e32 v6, s19, v6
629; SI-NEXT:    v_and_b32_e32 v7, s19, v7
630; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
631; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 1
632; SI-NEXT:    v_lshl_b64 v[4:5], v[4:5], 2
633; SI-NEXT:    v_lshr_b64 v[6:7], v[6:7], 2
634; SI-NEXT:    v_or_b32_e32 v2, v2, v0
635; SI-NEXT:    v_or_b32_e32 v0, v6, v4
636; SI-NEXT:    v_or_b32_e32 v7, v7, v5
637; SI-NEXT:    v_and_b32_e32 v5, s20, v7
638; SI-NEXT:    v_and_b32_e32 v4, s20, v0
639; SI-NEXT:    v_and_b32_e32 v6, s21, v0
640; SI-NEXT:    v_and_b32_e32 v7, s21, v7
641; SI-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
642; SI-NEXT:    v_lshr_b64 v[6:7], v[6:7], 1
643; SI-NEXT:    v_or_b32_e32 v3, v3, v1
644; SI-NEXT:    s_mov_b32 s7, 0xf000
645; SI-NEXT:    s_mov_b32 s6, -1
646; SI-NEXT:    v_or_b32_e32 v0, v6, v4
647; SI-NEXT:    v_or_b32_e32 v1, v7, v5
648; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
649; SI-NEXT:    s_endpgm
650;
651; FLAT-LABEL: s_brev_v2i64:
652; FLAT:       ; %bb.0:
653; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
654; FLAT-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
655; FLAT-NEXT:    s_mov_b32 s9, 0
656; FLAT-NEXT:    s_mov_b32 s12, 0xff0000
657; FLAT-NEXT:    s_mov_b32 s13, 0xff000000
658; FLAT-NEXT:    s_mov_b32 s7, s9
659; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
660; FLAT-NEXT:    v_mov_b32_e32 v0, s2
661; FLAT-NEXT:    v_alignbit_b32 v1, s3, v0, 24
662; FLAT-NEXT:    v_alignbit_b32 v0, s3, v0, 8
663; FLAT-NEXT:    s_bfe_u32 s6, s3, 0x80010
664; FLAT-NEXT:    v_and_b32_e32 v1, s12, v1
665; FLAT-NEXT:    v_and_b32_e32 v0, s13, v0
666; FLAT-NEXT:    s_lshr_b32 s8, s3, 24
667; FLAT-NEXT:    s_lshl_b32 s6, s6, 8
668; FLAT-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
669; FLAT-NEXT:    v_or_b32_e32 v0, v0, v1
670; FLAT-NEXT:    s_lshl_b32 s8, s2, 8
671; FLAT-NEXT:    v_or_b32_e32 v0, s6, v0
672; FLAT-NEXT:    v_mov_b32_e32 v1, s7
673; FLAT-NEXT:    s_and_b32 s11, s8, s12
674; FLAT-NEXT:    s_lshl_b32 s7, s2, 24
675; FLAT-NEXT:    s_mov_b32 s6, s9
676; FLAT-NEXT:    s_mov_b32 s10, s9
677; FLAT-NEXT:    s_or_b64 s[6:7], s[6:7], s[10:11]
678; FLAT-NEXT:    s_lshl_b64 s[10:11], s[2:3], 8
679; FLAT-NEXT:    s_movk_i32 s14, 0xff
680; FLAT-NEXT:    s_lshl_b64 s[2:3], s[2:3], 24
681; FLAT-NEXT:    s_mov_b32 s15, 0xff00
682; FLAT-NEXT:    s_and_b32 s11, s11, s14
683; FLAT-NEXT:    s_mov_b32 s10, s9
684; FLAT-NEXT:    s_and_b32 s3, s3, s15
685; FLAT-NEXT:    s_mov_b32 s2, s9
686; FLAT-NEXT:    s_or_b64 s[2:3], s[2:3], s[10:11]
687; FLAT-NEXT:    s_or_b64 s[2:3], s[6:7], s[2:3]
688; FLAT-NEXT:    v_mov_b32_e32 v4, s0
689; FLAT-NEXT:    v_alignbit_b32 v5, s1, v4, 24
690; FLAT-NEXT:    v_alignbit_b32 v4, s1, v4, 8
691; FLAT-NEXT:    v_or_b32_e32 v2, s2, v0
692; FLAT-NEXT:    s_bfe_u32 s2, s1, 0x80010
693; FLAT-NEXT:    v_or_b32_e32 v3, s3, v1
694; FLAT-NEXT:    v_and_b32_e32 v5, s12, v5
695; FLAT-NEXT:    v_and_b32_e32 v4, s13, v4
696; FLAT-NEXT:    s_lshr_b32 s8, s1, 24
697; FLAT-NEXT:    s_lshl_b32 s2, s2, 8
698; FLAT-NEXT:    s_mov_b32 s3, s9
699; FLAT-NEXT:    s_or_b64 s[2:3], s[2:3], s[8:9]
700; FLAT-NEXT:    v_or_b32_e32 v4, v4, v5
701; FLAT-NEXT:    s_lshl_b32 s8, s0, 8
702; FLAT-NEXT:    v_or_b32_e32 v4, s2, v4
703; FLAT-NEXT:    v_mov_b32_e32 v5, s3
704; FLAT-NEXT:    s_lshl_b32 s3, s0, 24
705; FLAT-NEXT:    s_mov_b32 s2, s9
706; FLAT-NEXT:    s_and_b32 s11, s8, s12
707; FLAT-NEXT:    s_mov_b32 s16, 0xf0f0f0f
708; FLAT-NEXT:    s_or_b64 s[2:3], s[2:3], s[10:11]
709; FLAT-NEXT:    s_lshl_b64 s[10:11], s[0:1], 8
710; FLAT-NEXT:    s_lshl_b64 s[0:1], s[0:1], 24
711; FLAT-NEXT:    s_mov_b32 s17, 0xf0f0f0f0
712; FLAT-NEXT:    v_and_b32_e32 v0, s16, v2
713; FLAT-NEXT:    v_and_b32_e32 v1, s16, v3
714; FLAT-NEXT:    v_and_b32_e32 v2, s17, v2
715; FLAT-NEXT:    v_and_b32_e32 v3, s17, v3
716; FLAT-NEXT:    s_and_b32 s11, s11, s14
717; FLAT-NEXT:    s_mov_b32 s10, s9
718; FLAT-NEXT:    s_and_b32 s1, s1, s15
719; FLAT-NEXT:    s_mov_b32 s0, s9
720; FLAT-NEXT:    s_or_b64 s[0:1], s[0:1], s[10:11]
721; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 4, v[0:1]
722; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 4, v[2:3]
723; FLAT-NEXT:    s_or_b64 s[0:1], s[2:3], s[0:1]
724; FLAT-NEXT:    v_or_b32_e32 v6, s0, v4
725; FLAT-NEXT:    v_or_b32_e32 v7, s1, v5
726; FLAT-NEXT:    v_or_b32_e32 v2, v2, v0
727; FLAT-NEXT:    s_mov_b32 s18, 0x33333333
728; FLAT-NEXT:    v_or_b32_e32 v3, v3, v1
729; FLAT-NEXT:    s_mov_b32 s19, 0xcccccccc
730; FLAT-NEXT:    v_and_b32_e32 v0, s18, v2
731; FLAT-NEXT:    v_and_b32_e32 v1, s18, v3
732; FLAT-NEXT:    v_and_b32_e32 v4, s16, v6
733; FLAT-NEXT:    v_and_b32_e32 v5, s16, v7
734; FLAT-NEXT:    v_and_b32_e32 v2, s19, v2
735; FLAT-NEXT:    v_and_b32_e32 v3, s19, v3
736; FLAT-NEXT:    v_and_b32_e32 v6, s17, v6
737; FLAT-NEXT:    v_and_b32_e32 v7, s17, v7
738; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 2, v[0:1]
739; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 2, v[2:3]
740; FLAT-NEXT:    v_lshlrev_b64 v[4:5], 4, v[4:5]
741; FLAT-NEXT:    v_lshrrev_b64 v[6:7], 4, v[6:7]
742; FLAT-NEXT:    v_or_b32_e32 v2, v2, v0
743; FLAT-NEXT:    v_or_b32_e32 v6, v6, v4
744; FLAT-NEXT:    v_or_b32_e32 v7, v7, v5
745; FLAT-NEXT:    s_mov_b32 s20, 0x55555555
746; FLAT-NEXT:    v_or_b32_e32 v3, v3, v1
747; FLAT-NEXT:    s_mov_b32 s21, 0xaaaaaaaa
748; FLAT-NEXT:    v_and_b32_e32 v0, s20, v2
749; FLAT-NEXT:    v_and_b32_e32 v1, s20, v3
750; FLAT-NEXT:    v_and_b32_e32 v4, s18, v6
751; FLAT-NEXT:    v_and_b32_e32 v5, s18, v7
752; FLAT-NEXT:    v_and_b32_e32 v2, s21, v2
753; FLAT-NEXT:    v_and_b32_e32 v3, s21, v3
754; FLAT-NEXT:    v_and_b32_e32 v6, s19, v6
755; FLAT-NEXT:    v_and_b32_e32 v7, s19, v7
756; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
757; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 1, v[2:3]
758; FLAT-NEXT:    v_lshlrev_b64 v[4:5], 2, v[4:5]
759; FLAT-NEXT:    v_lshrrev_b64 v[6:7], 2, v[6:7]
760; FLAT-NEXT:    v_or_b32_e32 v2, v2, v0
761; FLAT-NEXT:    v_or_b32_e32 v0, v6, v4
762; FLAT-NEXT:    v_or_b32_e32 v7, v7, v5
763; FLAT-NEXT:    v_and_b32_e32 v5, s20, v7
764; FLAT-NEXT:    v_and_b32_e32 v4, s20, v0
765; FLAT-NEXT:    v_and_b32_e32 v6, s21, v0
766; FLAT-NEXT:    v_and_b32_e32 v7, s21, v7
767; FLAT-NEXT:    v_lshlrev_b64 v[4:5], 1, v[4:5]
768; FLAT-NEXT:    v_lshrrev_b64 v[6:7], 1, v[6:7]
769; FLAT-NEXT:    v_or_b32_e32 v3, v3, v1
770; FLAT-NEXT:    s_mov_b32 s7, 0xf000
771; FLAT-NEXT:    s_mov_b32 s6, -1
772; FLAT-NEXT:    v_or_b32_e32 v0, v6, v4
773; FLAT-NEXT:    v_or_b32_e32 v1, v7, v5
774; FLAT-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
775; FLAT-NEXT:    s_endpgm
776  %brev = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %val) #1
777  store <2 x i64> %brev, <2 x i64> addrspace(1)* %out
778  ret void
779}
780
781define amdgpu_kernel void @v_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %valptr) #0 {
782; SI-LABEL: v_brev_v2i64:
783; SI:       ; %bb.0:
784; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
785; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
786; SI-NEXT:    s_mov_b32 s7, 0xf000
787; SI-NEXT:    s_mov_b32 s2, 0
788; SI-NEXT:    s_mov_b32 s3, s7
789; SI-NEXT:    v_lshlrev_b32_e32 v0, 4, v0
790; SI-NEXT:    v_mov_b32_e32 v1, 0
791; SI-NEXT:    s_waitcnt lgkmcnt(0)
792; SI-NEXT:    buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 addr64
793; SI-NEXT:    s_mov_b32 s0, 0xff0000
794; SI-NEXT:    s_mov_b32 s1, 0xff000000
795; SI-NEXT:    s_mov_b32 s2, 0xff00
796; SI-NEXT:    s_movk_i32 s3, 0xff
797; SI-NEXT:    s_mov_b32 s8, 0xf0f0f0f
798; SI-NEXT:    s_mov_b32 s9, 0xf0f0f0f0
799; SI-NEXT:    s_mov_b32 s10, 0x33333333
800; SI-NEXT:    s_mov_b32 s11, 0xcccccccc
801; SI-NEXT:    s_mov_b32 s12, 0x55555555
802; SI-NEXT:    s_mov_b32 s13, 0xaaaaaaaa
803; SI-NEXT:    s_mov_b32 s6, -1
804; SI-NEXT:    s_waitcnt vmcnt(0)
805; SI-NEXT:    v_lshl_b64 v[4:5], v[2:3], 8
806; SI-NEXT:    v_alignbit_b32 v6, v3, v2, 24
807; SI-NEXT:    v_alignbit_b32 v7, v3, v2, 8
808; SI-NEXT:    v_lshrrev_b32_e32 v8, 24, v3
809; SI-NEXT:    v_lshrrev_b32_e32 v9, 8, v3
810; SI-NEXT:    v_lshl_b64 v[3:4], v[2:3], 24
811; SI-NEXT:    v_lshlrev_b32_e32 v10, 24, v2
812; SI-NEXT:    v_lshlrev_b32_e32 v11, 8, v2
813; SI-NEXT:    v_lshl_b64 v[2:3], v[0:1], 8
814; SI-NEXT:    v_alignbit_b32 v12, v1, v0, 24
815; SI-NEXT:    v_alignbit_b32 v13, v1, v0, 8
816; SI-NEXT:    v_lshrrev_b32_e32 v14, 24, v1
817; SI-NEXT:    v_lshrrev_b32_e32 v15, 8, v1
818; SI-NEXT:    v_lshlrev_b32_e32 v16, 24, v0
819; SI-NEXT:    v_lshlrev_b32_e32 v17, 8, v0
820; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 24
821; SI-NEXT:    v_and_b32_e32 v0, s0, v6
822; SI-NEXT:    v_and_b32_e32 v2, s1, v7
823; SI-NEXT:    v_and_b32_e32 v6, s2, v9
824; SI-NEXT:    v_and_b32_e32 v7, s0, v11
825; SI-NEXT:    v_and_b32_e32 v9, s0, v12
826; SI-NEXT:    v_and_b32_e32 v11, s1, v13
827; SI-NEXT:    v_or_b32_e32 v0, v2, v0
828; SI-NEXT:    v_or_b32_e32 v2, v6, v8
829; SI-NEXT:    v_and_b32_e32 v12, s2, v15
830; SI-NEXT:    v_and_b32_e32 v13, s0, v17
831; SI-NEXT:    v_and_b32_e32 v5, s3, v5
832; SI-NEXT:    v_and_b32_e32 v4, s2, v4
833; SI-NEXT:    v_and_b32_e32 v3, s3, v3
834; SI-NEXT:    v_and_b32_e32 v1, s2, v1
835; SI-NEXT:    v_or_b32_e32 v6, v10, v7
836; SI-NEXT:    v_or_b32_e32 v7, v11, v9
837; SI-NEXT:    v_or_b32_e32 v2, v0, v2
838; SI-NEXT:    v_or_b32_e32 v8, v12, v14
839; SI-NEXT:    v_or_b32_e32 v0, v4, v5
840; SI-NEXT:    v_or_b32_e32 v1, v1, v3
841; SI-NEXT:    v_or_b32_e32 v9, v16, v13
842; SI-NEXT:    v_or_b32_e32 v5, v7, v8
843; SI-NEXT:    v_or_b32_e32 v3, v6, v0
844; SI-NEXT:    v_or_b32_e32 v7, v9, v1
845; SI-NEXT:    v_and_b32_e32 v0, s8, v2
846; SI-NEXT:    v_and_b32_e32 v1, s8, v3
847; SI-NEXT:    v_and_b32_e32 v2, s9, v2
848; SI-NEXT:    v_and_b32_e32 v3, s9, v3
849; SI-NEXT:    v_and_b32_e32 v4, s8, v5
850; SI-NEXT:    v_and_b32_e32 v6, s9, v5
851; SI-NEXT:    v_and_b32_e32 v5, s8, v7
852; SI-NEXT:    v_and_b32_e32 v7, s9, v7
853; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 4
854; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 4
855; SI-NEXT:    v_lshl_b64 v[4:5], v[4:5], 4
856; SI-NEXT:    v_lshr_b64 v[6:7], v[6:7], 4
857; SI-NEXT:    v_or_b32_e32 v3, v3, v1
858; SI-NEXT:    v_or_b32_e32 v2, v2, v0
859; SI-NEXT:    v_or_b32_e32 v7, v7, v5
860; SI-NEXT:    v_or_b32_e32 v6, v6, v4
861; SI-NEXT:    v_and_b32_e32 v1, s10, v3
862; SI-NEXT:    v_and_b32_e32 v0, s10, v2
863; SI-NEXT:    v_and_b32_e32 v5, s10, v7
864; SI-NEXT:    v_and_b32_e32 v4, s10, v6
865; SI-NEXT:    v_and_b32_e32 v3, s11, v3
866; SI-NEXT:    v_and_b32_e32 v2, s11, v2
867; SI-NEXT:    v_and_b32_e32 v7, s11, v7
868; SI-NEXT:    v_and_b32_e32 v6, s11, v6
869; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 2
870; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 2
871; SI-NEXT:    v_lshl_b64 v[4:5], v[4:5], 2
872; SI-NEXT:    v_lshr_b64 v[6:7], v[6:7], 2
873; SI-NEXT:    v_or_b32_e32 v3, v3, v1
874; SI-NEXT:    v_or_b32_e32 v2, v2, v0
875; SI-NEXT:    v_or_b32_e32 v7, v7, v5
876; SI-NEXT:    v_or_b32_e32 v6, v6, v4
877; SI-NEXT:    v_and_b32_e32 v1, s12, v3
878; SI-NEXT:    v_and_b32_e32 v0, s12, v2
879; SI-NEXT:    v_and_b32_e32 v5, s12, v7
880; SI-NEXT:    v_and_b32_e32 v4, s12, v6
881; SI-NEXT:    v_and_b32_e32 v3, s13, v3
882; SI-NEXT:    v_and_b32_e32 v2, s13, v2
883; SI-NEXT:    v_and_b32_e32 v7, s13, v7
884; SI-NEXT:    v_and_b32_e32 v6, s13, v6
885; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
886; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], 1
887; SI-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
888; SI-NEXT:    v_lshr_b64 v[6:7], v[6:7], 1
889; SI-NEXT:    v_or_b32_e32 v3, v3, v1
890; SI-NEXT:    v_or_b32_e32 v2, v2, v0
891; SI-NEXT:    v_or_b32_e32 v1, v7, v5
892; SI-NEXT:    v_or_b32_e32 v0, v6, v4
893; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
894; SI-NEXT:    s_endpgm
895;
896; FLAT-LABEL: v_brev_v2i64:
897; FLAT:       ; %bb.0:
898; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
899; FLAT-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
900; FLAT-NEXT:    v_lshlrev_b32_e32 v0, 4, v0
901; FLAT-NEXT:    v_mov_b32_e32 v8, 8
902; FLAT-NEXT:    s_mov_b32 s2, 0xff0000
903; FLAT-NEXT:    s_mov_b32 s3, 0xff000000
904; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
905; FLAT-NEXT:    v_mov_b32_e32 v1, s1
906; FLAT-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
907; FLAT-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
908; FLAT-NEXT:    flat_load_dwordx4 v[0:3], v[0:1]
909; FLAT-NEXT:    s_mov_b32 s0, 0xff00
910; FLAT-NEXT:    s_mov_b32 s1, 0xf0f0f0f
911; FLAT-NEXT:    s_mov_b32 s8, 0xf0f0f0f0
912; FLAT-NEXT:    s_mov_b32 s9, 0x33333333
913; FLAT-NEXT:    s_mov_b32 s10, 0xcccccccc
914; FLAT-NEXT:    s_mov_b32 s11, 0x55555555
915; FLAT-NEXT:    s_mov_b32 s12, 0xaaaaaaaa
916; FLAT-NEXT:    s_mov_b32 s7, 0xf000
917; FLAT-NEXT:    s_mov_b32 s6, -1
918; FLAT-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
919; FLAT-NEXT:    v_lshlrev_b64 v[4:5], 24, v[2:3]
920; FLAT-NEXT:    v_lshlrev_b32_sdwa v11, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
921; FLAT-NEXT:    v_lshlrev_b32_sdwa v14, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
922; FLAT-NEXT:    v_lshlrev_b64 v[8:9], 8, v[0:1]
923; FLAT-NEXT:    v_lshlrev_b64 v[6:7], 8, v[2:3]
924; FLAT-NEXT:    v_alignbit_b32 v4, v3, v2, 24
925; FLAT-NEXT:    v_alignbit_b32 v10, v3, v2, 8
926; FLAT-NEXT:    v_or_b32_sdwa v3, v11, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
927; FLAT-NEXT:    v_alignbit_b32 v12, v1, v0, 24
928; FLAT-NEXT:    v_alignbit_b32 v13, v1, v0, 8
929; FLAT-NEXT:    v_lshlrev_b32_e32 v8, 24, v0
930; FLAT-NEXT:    v_lshlrev_b32_e32 v15, 8, v0
931; FLAT-NEXT:    v_or_b32_sdwa v11, v14, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
932; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 24, v[0:1]
933; FLAT-NEXT:    v_lshlrev_b32_e32 v6, 24, v2
934; FLAT-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
935; FLAT-NEXT:    v_and_b32_e32 v0, s2, v4
936; FLAT-NEXT:    v_and_b32_e32 v4, s3, v10
937; FLAT-NEXT:    v_and_b32_e32 v2, s2, v2
938; FLAT-NEXT:    v_or_b32_e32 v0, v4, v0
939; FLAT-NEXT:    v_and_b32_e32 v1, s0, v1
940; FLAT-NEXT:    v_and_b32_e32 v10, s2, v12
941; FLAT-NEXT:    v_and_b32_e32 v12, s3, v13
942; FLAT-NEXT:    v_and_b32_e32 v4, s0, v5
943; FLAT-NEXT:    v_and_b32_e32 v13, s2, v15
944; FLAT-NEXT:    v_or_b32_e32 v5, v12, v10
945; FLAT-NEXT:    v_or_b32_e32 v2, v6, v2
946; FLAT-NEXT:    v_or_b32_e32 v3, v0, v3
947; FLAT-NEXT:    v_or_b32_sdwa v0, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
948; FLAT-NEXT:    v_or_b32_e32 v6, v8, v13
949; FLAT-NEXT:    v_or_b32_sdwa v1, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
950; FLAT-NEXT:    v_or_b32_e32 v7, v2, v0
951; FLAT-NEXT:    v_or_b32_e32 v5, v5, v11
952; FLAT-NEXT:    v_or_b32_e32 v8, v6, v1
953; FLAT-NEXT:    v_and_b32_e32 v0, s1, v3
954; FLAT-NEXT:    v_and_b32_e32 v1, s1, v7
955; FLAT-NEXT:    v_and_b32_e32 v2, s8, v3
956; FLAT-NEXT:    v_and_b32_e32 v3, s8, v7
957; FLAT-NEXT:    v_and_b32_e32 v4, s1, v5
958; FLAT-NEXT:    v_and_b32_e32 v6, s8, v5
959; FLAT-NEXT:    v_and_b32_e32 v5, s1, v8
960; FLAT-NEXT:    v_and_b32_e32 v7, s8, v8
961; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 4, v[0:1]
962; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 4, v[2:3]
963; FLAT-NEXT:    v_lshlrev_b64 v[4:5], 4, v[4:5]
964; FLAT-NEXT:    v_lshrrev_b64 v[6:7], 4, v[6:7]
965; FLAT-NEXT:    v_or_b32_e32 v3, v3, v1
966; FLAT-NEXT:    v_or_b32_e32 v2, v2, v0
967; FLAT-NEXT:    v_or_b32_e32 v7, v7, v5
968; FLAT-NEXT:    v_or_b32_e32 v6, v6, v4
969; FLAT-NEXT:    v_and_b32_e32 v1, s9, v3
970; FLAT-NEXT:    v_and_b32_e32 v0, s9, v2
971; FLAT-NEXT:    v_and_b32_e32 v5, s9, v7
972; FLAT-NEXT:    v_and_b32_e32 v4, s9, v6
973; FLAT-NEXT:    v_and_b32_e32 v3, s10, v3
974; FLAT-NEXT:    v_and_b32_e32 v2, s10, v2
975; FLAT-NEXT:    v_and_b32_e32 v7, s10, v7
976; FLAT-NEXT:    v_and_b32_e32 v6, s10, v6
977; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 2, v[0:1]
978; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 2, v[2:3]
979; FLAT-NEXT:    v_lshlrev_b64 v[4:5], 2, v[4:5]
980; FLAT-NEXT:    v_lshrrev_b64 v[6:7], 2, v[6:7]
981; FLAT-NEXT:    v_or_b32_e32 v3, v3, v1
982; FLAT-NEXT:    v_or_b32_e32 v2, v2, v0
983; FLAT-NEXT:    v_or_b32_e32 v7, v7, v5
984; FLAT-NEXT:    v_or_b32_e32 v6, v6, v4
985; FLAT-NEXT:    v_and_b32_e32 v1, s11, v3
986; FLAT-NEXT:    v_and_b32_e32 v0, s11, v2
987; FLAT-NEXT:    v_and_b32_e32 v5, s11, v7
988; FLAT-NEXT:    v_and_b32_e32 v4, s11, v6
989; FLAT-NEXT:    v_and_b32_e32 v3, s12, v3
990; FLAT-NEXT:    v_and_b32_e32 v2, s12, v2
991; FLAT-NEXT:    v_and_b32_e32 v7, s12, v7
992; FLAT-NEXT:    v_and_b32_e32 v6, s12, v6
993; FLAT-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
994; FLAT-NEXT:    v_lshrrev_b64 v[2:3], 1, v[2:3]
995; FLAT-NEXT:    v_lshlrev_b64 v[4:5], 1, v[4:5]
996; FLAT-NEXT:    v_lshrrev_b64 v[6:7], 1, v[6:7]
997; FLAT-NEXT:    v_or_b32_e32 v3, v3, v1
998; FLAT-NEXT:    v_or_b32_e32 v2, v2, v0
999; FLAT-NEXT:    v_or_b32_e32 v1, v7, v5
1000; FLAT-NEXT:    v_or_b32_e32 v0, v6, v4
1001; FLAT-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
1002; FLAT-NEXT:    s_endpgm
1003  %tid = call i32 @llvm.amdgcn.workitem.id.x()
1004  %gep = getelementptr <2 x i64> , <2 x i64> addrspace(1)* %valptr, i32 %tid
1005  %val = load <2 x i64>, <2 x i64> addrspace(1)* %gep
1006  %brev = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %val) #1
1007  store <2 x i64> %brev, <2 x i64> addrspace(1)* %out
1008  ret void
1009}
1010
1011define float @missing_truncate_promote_bitreverse(i32 %arg) {
1012; SI-LABEL: missing_truncate_promote_bitreverse:
1013; SI:       ; %bb.0: ; %bb
1014; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1015; SI-NEXT:    v_bfrev_b32_e32 v0, v0
1016; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
1017; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
1018; SI-NEXT:    s_setpc_b64 s[30:31]
1019;
1020; FLAT-LABEL: missing_truncate_promote_bitreverse:
1021; FLAT:       ; %bb.0: ; %bb
1022; FLAT-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1023; FLAT-NEXT:    v_bfrev_b32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
1024; FLAT-NEXT:    v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
1025; FLAT-NEXT:    s_setpc_b64 s[30:31]
1026bb:
1027  %tmp = trunc i32 %arg to i16
1028  %tmp1 = call i16 @llvm.bitreverse.i16(i16 %tmp)
1029  %tmp2 = bitcast i16 %tmp1 to half
1030  %tmp3 = fpext half %tmp2 to float
1031  ret float %tmp3
1032}
1033
1034attributes #0 = { nounwind }
1035attributes #1 = { nounwind readnone }
1036