1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3
4define i32 @atomic_nand_i32_lds(i32 addrspace(3)* %ptr) nounwind {
5; GCN-LABEL: atomic_nand_i32_lds:
6; GCN:       ; %bb.0:
7; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8; GCN-NEXT:    ds_read_b32 v1, v0
9; GCN-NEXT:    s_mov_b64 s[4:5], 0
10; GCN-NEXT:  BB0_1: ; %atomicrmw.start
11; GCN-NEXT:    ; =>This Inner Loop Header: Depth=1
12; GCN-NEXT:    s_waitcnt lgkmcnt(0)
13; GCN-NEXT:    v_mov_b32_e32 v2, v1
14; GCN-NEXT:    v_not_b32_e32 v1, v2
15; GCN-NEXT:    v_or_b32_e32 v1, -5, v1
16; GCN-NEXT:    s_waitcnt lgkmcnt(0)
17; GCN-NEXT:    ds_cmpst_rtn_b32 v1, v0, v2, v1
18; GCN-NEXT:    s_waitcnt lgkmcnt(0)
19; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v2
20; GCN-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
21; GCN-NEXT:    s_andn2_b64 exec, exec, s[4:5]
22; GCN-NEXT:    s_cbranch_execnz BB0_1
23; GCN-NEXT:  ; %bb.2: ; %atomicrmw.end
24; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
25; GCN-NEXT:    v_mov_b32_e32 v0, v1
26; GCN-NEXT:    s_setpc_b64 s[30:31]
27  %result = atomicrmw nand i32 addrspace(3)* %ptr, i32 4 seq_cst
28  ret i32 %result
29}
30
31define i32 @atomic_nand_i32_global(i32 addrspace(1)* %ptr) nounwind {
32; GCN-LABEL: atomic_nand_i32_global:
33; GCN:       ; %bb.0:
34; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
35; GCN-NEXT:    global_load_dword v2, v[0:1], off
36; GCN-NEXT:    s_mov_b64 s[4:5], 0
37; GCN-NEXT:  BB1_1: ; %atomicrmw.start
38; GCN-NEXT:    ; =>This Inner Loop Header: Depth=1
39; GCN-NEXT:    s_waitcnt vmcnt(0)
40; GCN-NEXT:    v_mov_b32_e32 v3, v2
41; GCN-NEXT:    v_not_b32_e32 v2, v3
42; GCN-NEXT:    v_or_b32_e32 v2, -5, v2
43; GCN-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
44; GCN-NEXT:    global_atomic_cmpswap v2, v[0:1], v[2:3], off glc
45; GCN-NEXT:    s_waitcnt vmcnt(0)
46; GCN-NEXT:    buffer_wbinvl1_vol
47; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v3
48; GCN-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
49; GCN-NEXT:    s_andn2_b64 exec, exec, s[4:5]
50; GCN-NEXT:    s_cbranch_execnz BB1_1
51; GCN-NEXT:  ; %bb.2: ; %atomicrmw.end
52; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
53; GCN-NEXT:    v_mov_b32_e32 v0, v2
54; GCN-NEXT:    s_setpc_b64 s[30:31]
55  %result = atomicrmw nand i32 addrspace(1)* %ptr, i32 4 seq_cst
56  ret i32 %result
57}
58
59define i32 @atomic_nand_i32_flat(i32* %ptr) nounwind {
60; GCN-LABEL: atomic_nand_i32_flat:
61; GCN:       ; %bb.0:
62; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
63; GCN-NEXT:    flat_load_dword v2, v[0:1]
64; GCN-NEXT:    s_mov_b64 s[4:5], 0
65; GCN-NEXT:  BB2_1: ; %atomicrmw.start
66; GCN-NEXT:    ; =>This Inner Loop Header: Depth=1
67; GCN-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
68; GCN-NEXT:    v_mov_b32_e32 v3, v2
69; GCN-NEXT:    v_not_b32_e32 v2, v3
70; GCN-NEXT:    v_or_b32_e32 v2, -5, v2
71; GCN-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
72; GCN-NEXT:    flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
73; GCN-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
74; GCN-NEXT:    buffer_wbinvl1_vol
75; GCN-NEXT:    s_waitcnt lgkmcnt(0)
76; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v3
77; GCN-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
78; GCN-NEXT:    s_andn2_b64 exec, exec, s[4:5]
79; GCN-NEXT:    s_cbranch_execnz BB2_1
80; GCN-NEXT:  ; %bb.2: ; %atomicrmw.end
81; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
82; GCN-NEXT:    v_mov_b32_e32 v0, v2
83; GCN-NEXT:    s_setpc_b64 s[30:31]
84  %result = atomicrmw nand i32* %ptr, i32 4 seq_cst
85  ret i32 %result
86}
87