1; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX7LESS %s
2; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX8MORE %s
3; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX8MORE %s
4
5declare i32 @llvm.amdgcn.workitem.id.x()
6declare i32 @llvm.amdgcn.struct.buffer.atomic.add(i32, <4 x i32>, i32, i32, i32, i32)
7declare i32 @llvm.amdgcn.struct.buffer.atomic.sub(i32, <4 x i32>, i32, i32, i32, i32)
8
9; Show that what the atomic optimization pass will do for struct buffers.
10
11; GCN-LABEL: add_i32_constant:
12; GCN: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0
13; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt_lo:[0-9]+]], s[[exec_lo]], 0
14; GCN: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt_hi:[0-9]+]], s[[exec_hi]], v[[mbcnt_lo]]
15; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc, 0, v[[mbcnt_hi]]
16; GCN: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
17; GCN: v_mul_u32_u24{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[popcount]], 5
18; GCN: buffer_atomic_add v[[value]]
19define amdgpu_kernel void @add_i32_constant(i32 addrspace(1)* %out, <4 x i32> %inout) {
20entry:
21  %old = call i32 @llvm.amdgcn.struct.buffer.atomic.add(i32 5, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 0)
22  store i32 %old, i32 addrspace(1)* %out
23  ret void
24}
25
26; GCN-LABEL: add_i32_uniform:
27; GCN: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0
28; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt_lo:[0-9]+]], s[[exec_lo]], 0
29; GCN: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt_hi:[0-9]+]], s[[exec_hi]], v[[mbcnt_lo]]
30; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc, 0, v[[mbcnt_hi]]
31; GCN: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
32; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]]
33; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
34; GCN: buffer_atomic_add v[[value]]
35define amdgpu_kernel void @add_i32_uniform(i32 addrspace(1)* %out, <4 x i32> %inout, i32 %additive) {
36entry:
37  %old = call i32 @llvm.amdgcn.struct.buffer.atomic.add(i32 %additive, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 0)
38  store i32 %old, i32 addrspace(1)* %out
39  ret void
40}
41
42; GCN-LABEL: add_i32_varying_vdata:
43; GFX7LESS-NOT: v_mbcnt_lo_u32_b32
44; GFX7LESS-NOT: v_mbcnt_hi_u32_b32
45; GFX7LESS-NOT: s_bcnt1_i32_b64
46; GFX7LESS: buffer_atomic_add v{{[0-9]+}}
47; GFX8MORE: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63
48; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
49; GFX8MORE: buffer_atomic_add v[[value]]
50define amdgpu_kernel void @add_i32_varying_vdata(i32 addrspace(1)* %out, <4 x i32> %inout) {
51entry:
52  %lane = call i32 @llvm.amdgcn.workitem.id.x()
53  %old = call i32 @llvm.amdgcn.struct.buffer.atomic.add(i32 %lane, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 0)
54  store i32 %old, i32 addrspace(1)* %out
55  ret void
56}
57
58; GCN-LABEL: add_i32_varying_vindex:
59; GCN-NOT: v_mbcnt_lo_u32_b32
60; GCN-NOT: v_mbcnt_hi_u32_b32
61; GCN-NOT: s_bcnt1_i32_b64
62; GCN: buffer_atomic_add v{{[0-9]+}}
63define amdgpu_kernel void @add_i32_varying_vindex(i32 addrspace(1)* %out, <4 x i32> %inout) {
64entry:
65  %lane = call i32 @llvm.amdgcn.workitem.id.x()
66  %old = call i32 @llvm.amdgcn.struct.buffer.atomic.add(i32 1, <4 x i32> %inout, i32 %lane, i32 0, i32 0, i32 0)
67  store i32 %old, i32 addrspace(1)* %out
68  ret void
69}
70
71; GCN-LABEL: add_i32_varying_offset:
72; GCN-NOT: v_mbcnt_lo_u32_b32
73; GCN-NOT: v_mbcnt_hi_u32_b32
74; GCN-NOT: s_bcnt1_i32_b64
75; GCN: buffer_atomic_add v{{[0-9]+}}
76define amdgpu_kernel void @add_i32_varying_offset(i32 addrspace(1)* %out, <4 x i32> %inout) {
77entry:
78  %lane = call i32 @llvm.amdgcn.workitem.id.x()
79  %old = call i32 @llvm.amdgcn.struct.buffer.atomic.add(i32 1, <4 x i32> %inout, i32 0, i32 %lane, i32 0, i32 0)
80  store i32 %old, i32 addrspace(1)* %out
81  ret void
82}
83
84; GCN-LABEL: sub_i32_constant:
85; GCN: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0
86; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt_lo:[0-9]+]], s[[exec_lo]], 0
87; GCN: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt_hi:[0-9]+]], s[[exec_hi]], v[[mbcnt_lo]]
88; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc, 0, v[[mbcnt_hi]]
89; GCN: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
90; GCN: v_mul_u32_u24{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[popcount]], 5
91; GCN: buffer_atomic_sub v[[value]]
92define amdgpu_kernel void @sub_i32_constant(i32 addrspace(1)* %out, <4 x i32> %inout) {
93entry:
94  %old = call i32 @llvm.amdgcn.struct.buffer.atomic.sub(i32 5, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 0)
95  store i32 %old, i32 addrspace(1)* %out
96  ret void
97}
98
99; GCN-LABEL: sub_i32_uniform:
100; GCN: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0
101; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt_lo:[0-9]+]], s[[exec_lo]], 0
102; GCN: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt_hi:[0-9]+]], s[[exec_hi]], v[[mbcnt_lo]]
103; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc, 0, v[[mbcnt_hi]]
104; GCN: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
105; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]]
106; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
107; GCN: buffer_atomic_sub v[[value]]
108define amdgpu_kernel void @sub_i32_uniform(i32 addrspace(1)* %out, <4 x i32> %inout, i32 %subitive) {
109entry:
110  %old = call i32 @llvm.amdgcn.struct.buffer.atomic.sub(i32 %subitive, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 0)
111  store i32 %old, i32 addrspace(1)* %out
112  ret void
113}
114
115; GCN-LABEL: sub_i32_varying_vdata:
116; GFX7LESS-NOT: v_mbcnt_lo_u32_b32
117; GFX7LESS-NOT: v_mbcnt_hi_u32_b32
118; GFX7LESS-NOT: s_bcnt1_i32_b64
119; GFX7LESS: buffer_atomic_sub v{{[0-9]+}}
120; GFX8MORE: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63
121; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
122; GFX8MORE: buffer_atomic_sub v[[value]]
123define amdgpu_kernel void @sub_i32_varying_vdata(i32 addrspace(1)* %out, <4 x i32> %inout) {
124entry:
125  %lane = call i32 @llvm.amdgcn.workitem.id.x()
126  %old = call i32 @llvm.amdgcn.struct.buffer.atomic.sub(i32 %lane, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 0)
127  store i32 %old, i32 addrspace(1)* %out
128  ret void
129}
130
131; GCN-LABEL: sub_i32_varying_vindex:
132; GCN-NOT: v_mbcnt_lo_u32_b32
133; GCN-NOT: v_mbcnt_hi_u32_b32
134; GCN-NOT: s_bcnt1_i32_b64
135; GCN: buffer_atomic_sub v{{[0-9]+}}
136define amdgpu_kernel void @sub_i32_varying_vindex(i32 addrspace(1)* %out, <4 x i32> %inout) {
137entry:
138  %lane = call i32 @llvm.amdgcn.workitem.id.x()
139  %old = call i32 @llvm.amdgcn.struct.buffer.atomic.sub(i32 1, <4 x i32> %inout, i32 %lane, i32 0, i32 0, i32 0)
140  store i32 %old, i32 addrspace(1)* %out
141  ret void
142}
143
144; GCN-LABEL: sub_i32_varying_offset:
145; GCN-NOT: v_mbcnt_lo_u32_b32
146; GCN-NOT: v_mbcnt_hi_u32_b32
147; GCN-NOT: s_bcnt1_i32_b64
148; GCN: buffer_atomic_sub v{{[0-9]+}}
149define amdgpu_kernel void @sub_i32_varying_offset(i32 addrspace(1)* %out, <4 x i32> %inout) {
150entry:
151  %lane = call i32 @llvm.amdgcn.workitem.id.x()
152  %old = call i32 @llvm.amdgcn.struct.buffer.atomic.sub(i32 1, <4 x i32> %inout, i32 0, i32 %lane, i32 0, i32 0)
153  store i32 %old, i32 addrspace(1)* %out
154  ret void
155}
156