1; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX7LESS %s
2; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX8MORE %s
3; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX8MORE %s
4
5declare i32 @llvm.amdgcn.workitem.id.x()
6declare i32 @llvm.amdgcn.struct.buffer.atomic.add(i32, <4 x i32>, i32, i32, i32, i32)
7declare i32 @llvm.amdgcn.struct.buffer.atomic.sub(i32, <4 x i32>, i32, i32, i32, i32)
8
9; Show that what the atomic optimization pass will do for struct buffers.
10
11; GCN-LABEL: add_i32_constant:
12; GCN: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0
13; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt_lo:[0-9]+]], s[[exec_lo]], 0
14; GCN: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt_hi:[0-9]+]], s[[exec_hi]], v[[mbcnt_lo]]
15; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc, 0, v[[mbcnt_hi]]
16; GCN: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
17; GCN: v_mul_u32_u24{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[popcount]], 5
18; GCN: buffer_atomic_add v[[value]]
19define amdgpu_kernel void @add_i32_constant(i32 addrspace(1)* %out, <4 x i32> %inout) {
20entry:
21  %old = call i32 @llvm.amdgcn.struct.buffer.atomic.add(i32 5, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 0)
22  store i32 %old, i32 addrspace(1)* %out
23  ret void
24}
25
26; GCN-LABEL: add_i32_uniform:
27; GCN: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0
28; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt_lo:[0-9]+]], s[[exec_lo]], 0
29; GCN: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt_hi:[0-9]+]], s[[exec_hi]], v[[mbcnt_lo]]
30; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc, 0, v[[mbcnt_hi]]
31; GCN: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
32; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]]
33; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
34; GCN: buffer_atomic_add v[[value]]
35define amdgpu_kernel void @add_i32_uniform(i32 addrspace(1)* %out, <4 x i32> %inout, i32 %additive) {
36entry:
37  %old = call i32 @llvm.amdgcn.struct.buffer.atomic.add(i32 %additive, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 0)
38  store i32 %old, i32 addrspace(1)* %out
39  ret void
40}
41
42; GCN-LABEL: add_i32_varying_vdata:
43; GFX7LESS-NOT: v_mbcnt_lo_u32_b32
44; GFX7LESS-NOT: v_mbcnt_hi_u32_b32
45; GFX7LESS-NOT: s_bcnt1_i32_b64
46; GFX7LESS: buffer_atomic_add v{{[0-9]+}}
47; GFX8MORE: v_add_u32_dpp
48; GFX8MORE: v_add_u32_dpp
49; GFX8MORE: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63
50; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
51; GFX8MORE: buffer_atomic_add v[[value]]
52define amdgpu_kernel void @add_i32_varying_vdata(i32 addrspace(1)* %out, <4 x i32> %inout) {
53entry:
54  %lane = call i32 @llvm.amdgcn.workitem.id.x()
55  %old = call i32 @llvm.amdgcn.struct.buffer.atomic.add(i32 %lane, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 0)
56  store i32 %old, i32 addrspace(1)* %out
57  ret void
58}
59
60; GCN-LABEL: add_i32_varying_vindex:
61; GCN-NOT: v_mbcnt_lo_u32_b32
62; GCN-NOT: v_mbcnt_hi_u32_b32
63; GCN-NOT: s_bcnt1_i32_b64
64; GCN: buffer_atomic_add v{{[0-9]+}}
65define amdgpu_kernel void @add_i32_varying_vindex(i32 addrspace(1)* %out, <4 x i32> %inout) {
66entry:
67  %lane = call i32 @llvm.amdgcn.workitem.id.x()
68  %old = call i32 @llvm.amdgcn.struct.buffer.atomic.add(i32 1, <4 x i32> %inout, i32 %lane, i32 0, i32 0, i32 0)
69  store i32 %old, i32 addrspace(1)* %out
70  ret void
71}
72
73; GCN-LABEL: add_i32_varying_offset:
74; GCN-NOT: v_mbcnt_lo_u32_b32
75; GCN-NOT: v_mbcnt_hi_u32_b32
76; GCN-NOT: s_bcnt1_i32_b64
77; GCN: buffer_atomic_add v{{[0-9]+}}
78define amdgpu_kernel void @add_i32_varying_offset(i32 addrspace(1)* %out, <4 x i32> %inout) {
79entry:
80  %lane = call i32 @llvm.amdgcn.workitem.id.x()
81  %old = call i32 @llvm.amdgcn.struct.buffer.atomic.add(i32 1, <4 x i32> %inout, i32 0, i32 %lane, i32 0, i32 0)
82  store i32 %old, i32 addrspace(1)* %out
83  ret void
84}
85
86; GCN-LABEL: sub_i32_constant:
87; GCN: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0
88; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt_lo:[0-9]+]], s[[exec_lo]], 0
89; GCN: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt_hi:[0-9]+]], s[[exec_hi]], v[[mbcnt_lo]]
90; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc, 0, v[[mbcnt_hi]]
91; GCN: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
92; GCN: v_mul_u32_u24{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[popcount]], 5
93; GCN: buffer_atomic_sub v[[value]]
94define amdgpu_kernel void @sub_i32_constant(i32 addrspace(1)* %out, <4 x i32> %inout) {
95entry:
96  %old = call i32 @llvm.amdgcn.struct.buffer.atomic.sub(i32 5, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 0)
97  store i32 %old, i32 addrspace(1)* %out
98  ret void
99}
100
101; GCN-LABEL: sub_i32_uniform:
102; GCN: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0
103; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt_lo:[0-9]+]], s[[exec_lo]], 0
104; GCN: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt_hi:[0-9]+]], s[[exec_hi]], v[[mbcnt_lo]]
105; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc, 0, v[[mbcnt_hi]]
106; GCN: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
107; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]]
108; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
109; GCN: buffer_atomic_sub v[[value]]
110define amdgpu_kernel void @sub_i32_uniform(i32 addrspace(1)* %out, <4 x i32> %inout, i32 %subitive) {
111entry:
112  %old = call i32 @llvm.amdgcn.struct.buffer.atomic.sub(i32 %subitive, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 0)
113  store i32 %old, i32 addrspace(1)* %out
114  ret void
115}
116
117; GCN-LABEL: sub_i32_varying_vdata:
118; GFX7LESS-NOT: v_mbcnt_lo_u32_b32
119; GFX7LESS-NOT: v_mbcnt_hi_u32_b32
120; GFX7LESS-NOT: s_bcnt1_i32_b64
121; GFX7LESS: buffer_atomic_sub v{{[0-9]+}}
122; GFX8MORE: v_sub{{(rev)?}}_u32_dpp
123; GFX8MORE: v_sub{{(rev)?}}_u32_dpp
124; GFX8MORE: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63
125; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
126; GFX8MORE: buffer_atomic_sub v[[value]]
127define amdgpu_kernel void @sub_i32_varying_vdata(i32 addrspace(1)* %out, <4 x i32> %inout) {
128entry:
129  %lane = call i32 @llvm.amdgcn.workitem.id.x()
130  %old = call i32 @llvm.amdgcn.struct.buffer.atomic.sub(i32 %lane, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 0)
131  store i32 %old, i32 addrspace(1)* %out
132  ret void
133}
134
135; GCN-LABEL: sub_i32_varying_vindex:
136; GCN-NOT: v_mbcnt_lo_u32_b32
137; GCN-NOT: v_mbcnt_hi_u32_b32
138; GCN-NOT: s_bcnt1_i32_b64
139; GCN: buffer_atomic_sub v{{[0-9]+}}
140define amdgpu_kernel void @sub_i32_varying_vindex(i32 addrspace(1)* %out, <4 x i32> %inout) {
141entry:
142  %lane = call i32 @llvm.amdgcn.workitem.id.x()
143  %old = call i32 @llvm.amdgcn.struct.buffer.atomic.sub(i32 1, <4 x i32> %inout, i32 %lane, i32 0, i32 0, i32 0)
144  store i32 %old, i32 addrspace(1)* %out
145  ret void
146}
147
148; GCN-LABEL: sub_i32_varying_offset:
149; GCN-NOT: v_mbcnt_lo_u32_b32
150; GCN-NOT: v_mbcnt_hi_u32_b32
151; GCN-NOT: s_bcnt1_i32_b64
152; GCN: buffer_atomic_sub v{{[0-9]+}}
153define amdgpu_kernel void @sub_i32_varying_offset(i32 addrspace(1)* %out, <4 x i32> %inout) {
154entry:
155  %lane = call i32 @llvm.amdgcn.workitem.id.x()
156  %old = call i32 @llvm.amdgcn.struct.buffer.atomic.sub(i32 1, <4 x i32> %inout, i32 0, i32 %lane, i32 0, i32 0)
157  store i32 %old, i32 addrspace(1)* %out
158  ret void
159}
160