1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX7LESS %s 3; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,DPPCOMB %s 4; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,DPPCOMB %s 5; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX1064 %s 6; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN32,GFX8MORE,GFX8MORE32,GFX1032 %s 7 8declare i32 @llvm.amdgcn.workitem.id.x() 9 10@local_var32 = addrspace(3) global i32 undef, align 4 11@local_var64 = addrspace(3) global i64 undef, align 8 12 13; Show that what the atomic optimization pass will do for local pointers. 14 15; GCN-LABEL: add_i32_constant: 16; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 17; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 18; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 19; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] 20; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] 21; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] 22; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} 23; GCN: v_mul_u32_u24{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[popcount]], 5 24; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] 25define amdgpu_kernel void @add_i32_constant(i32 addrspace(1)* %out) { 26entry: 27 %old = atomicrmw add i32 addrspace(3)* @local_var32, i32 5 acq_rel 28 store i32 %old, i32 addrspace(1)* %out 29 ret void 30} 31 32; GCN-LABEL: add_i32_uniform: 33; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 34; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 35; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 36; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] 37; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] 38; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] 39; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} 40; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]] 41; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] 42; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] 43define amdgpu_kernel void @add_i32_uniform(i32 addrspace(1)* %out, i32 %additive) { 44entry: 45 %old = atomicrmw add i32 addrspace(3)* @local_var32, i32 %additive acq_rel 46 store i32 %old, i32 addrspace(1)* %out 47 ret void 48} 49 50; GCN-LABEL: add_i32_varying: 51; GFX7LESS-NOT: v_mbcnt_lo_u32_b32 52; GFX7LESS-NOT: v_mbcnt_hi_u32_b32 53; GFX7LESS-NOT: s_bcnt1_i32_b64 54; GFX7LESS: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 55; DPPCOMB: v_add_u32_dpp 56; DPPCOMB: v_add_u32_dpp 57; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31 58; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63 59; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] 60; GFX8MORE: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] 61define amdgpu_kernel void @add_i32_varying(i32 addrspace(1)* %out) { 62entry: 63 %lane = call i32 @llvm.amdgcn.workitem.id.x() 64 %old = atomicrmw add i32 addrspace(3)* @local_var32, i32 %lane acq_rel 65 store i32 %old, i32 addrspace(1)* %out 66 ret void 67} 68 69define amdgpu_kernel void @add_i32_varying_gfx1032(i32 addrspace(1)* %out) { 70; GFX1032-LABEL: add_i32_varying_gfx1032: 71; GFX1032: v_mov_b32_e32 v2, v0 72; GFX1032: s_or_saveexec_b32 s2, -1 73; GFX1032: s_load_dwordx2 s[0:1], s[0:1], 0x24 74; GFX1032: v_mov_b32_e32 v1, 0 75; GFX1032: s_mov_b32 exec_lo, s2 76; GFX1032: v_cmp_ne_u32_e64 s2, 1, 0 77; GFX1032: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 78; GFX1032: s_not_b32 exec_lo, exec_lo 79; GFX1032: v_mov_b32_e32 v2, 0 80; GFX1032: s_not_b32 exec_lo, exec_lo 81; GFX1032: s_or_saveexec_b32 s4, -1 82; GFX1032: v_mov_b32_e32 v3, v1 83; GFX1032: v_mov_b32_e32 v4, v1 84; GFX1032: s_mov_b32 s2, -1 85; GFX1032: v_mov_b32_dpp v3, v2 row_shr:1 row_mask:0xf bank_mask:0xf 86; GFX1032: v_add_nc_u32_e32 v2, v2, v3 87; GFX1032: v_mov_b32_e32 v3, v1 88; GFX1032: v_mov_b32_dpp v3, v2 row_shr:2 row_mask:0xf bank_mask:0xf 89; GFX1032: v_add_nc_u32_e32 v2, v2, v3 90; GFX1032: v_mov_b32_e32 v3, v1 91; GFX1032: v_mov_b32_dpp v3, v2 row_shr:4 row_mask:0xf bank_mask:0xf 92; GFX1032: v_add_nc_u32_e32 v2, v2, v3 93; GFX1032: v_mov_b32_e32 v3, v1 94; GFX1032: v_mov_b32_dpp v3, v2 row_shr:8 row_mask:0xf bank_mask:0xf 95; GFX1032: v_add_nc_u32_e32 v2, v2, v3 96; GFX1032: v_mov_b32_e32 v3, v2 97; GFX1032: v_permlanex16_b32 v3, v3, -1, -1 98; GFX1032: v_mov_b32_dpp v4, v3 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf 99; GFX1032: v_add_nc_u32_e32 v2, v2, v4 100; GFX1032: v_readlane_b32 s3, v2, 31 101; GFX1032: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf 102; GFX1032: v_readlane_b32 s5, v2, 15 103; GFX1032: v_writelane_b32 v1, s5, 16 104; GFX1032: s_mov_b32 exec_lo, s4 105; GFX1032: v_cmp_eq_u32_e32 vcc_lo, 0, v0 106; GFX1032: s_and_saveexec_b32 s4, vcc_lo 107; GFX1032: s_cbranch_execz BB3_2 108; GFX1032: BB3_1: 109; GFX1032: v_mov_b32_e32 v0, local_var32@abs32@lo 110; GFX1032: v_mov_b32_e32 v5, s3 111; GFX1032: s_waitcnt vmcnt(0) lgkmcnt(0) 112; GFX1032: s_waitcnt_vscnt null, 0x0 113; GFX1032: ds_add_rtn_u32 v0, v0, v5 114; GFX1032: s_waitcnt vmcnt(0) lgkmcnt(0) 115; GFX1032: buffer_gl0_inv 116; GFX1032: buffer_gl1_inv 117; GFX1032: BB3_2: 118; GFX1032: v_nop 119; GFX1032: s_or_b32 exec_lo, exec_lo, s4 120; GFX1032: v_readfirstlane_b32 s3, v0 121; GFX1032: v_mov_b32_e32 v0, v1 122; GFX1032: v_add_nc_u32_e32 v0, s3, v0 123; GFX1032: s_mov_b32 s3, 0x31016000 124; GFX1032: s_nop 1 125; GFX1032: s_waitcnt lgkmcnt(0) 126; GFX1032: buffer_store_dword v0, off, s[0:3], 0 127; GFX1032: s_endpgm 128entry: 129 %lane = call i32 @llvm.amdgcn.workitem.id.x() 130 %old = atomicrmw add i32 addrspace(3)* @local_var32, i32 %lane acq_rel 131 store i32 %old, i32 addrspace(1)* %out 132 ret void 133} 134 135define amdgpu_kernel void @add_i32_varying_gfx1064(i32 addrspace(1)* %out) { 136; GFX1064-LABEL: add_i32_varying_gfx1064: 137; GFX1064: v_mov_b32_e32 v2, v0 138; GFX1064: s_or_saveexec_b64 s[2:3], -1 139; GFX1064: s_load_dwordx2 s[0:1], s[0:1], 0x24 140; GFX1064: v_mov_b32_e32 v1, 0 141; GFX1064: s_mov_b64 exec, s[2:3] 142; GFX1064: v_cmp_ne_u32_e64 s[2:3], 1, 0 143; GFX1064: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 144; GFX1064: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 145; GFX1064: s_not_b64 exec, exec 146; GFX1064: v_mov_b32_e32 v2, 0 147; GFX1064: s_not_b64 exec, exec 148; GFX1064: s_or_saveexec_b64 s[4:5], -1 149; GFX1064: v_mov_b32_e32 v3, v1 150; GFX1064: v_mov_b32_e32 v4, v1 151; GFX1064: s_mov_b32 s2, -1 152; GFX1064: v_mov_b32_dpp v3, v2 row_shr:1 row_mask:0xf bank_mask:0xf 153; GFX1064: v_add_nc_u32_e32 v2, v2, v3 154; GFX1064: v_mov_b32_e32 v3, v1 155; GFX1064: v_mov_b32_dpp v3, v2 row_shr:2 row_mask:0xf bank_mask:0xf 156; GFX1064: v_add_nc_u32_e32 v2, v2, v3 157; GFX1064: v_mov_b32_e32 v3, v1 158; GFX1064: v_mov_b32_dpp v3, v2 row_shr:4 row_mask:0xf bank_mask:0xf 159; GFX1064: v_add_nc_u32_e32 v2, v2, v3 160; GFX1064: v_mov_b32_e32 v3, v1 161; GFX1064: v_mov_b32_dpp v3, v2 row_shr:8 row_mask:0xf bank_mask:0xf 162; GFX1064: v_add_nc_u32_e32 v2, v2, v3 163; GFX1064: v_mov_b32_e32 v3, v2 164; GFX1064: v_permlanex16_b32 v3, v3, -1, -1 165; GFX1064: v_mov_b32_dpp v4, v3 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf 166; GFX1064: v_add_nc_u32_e32 v2, v2, v4 167; GFX1064: v_mov_b32_e32 v4, v1 168; GFX1064: v_readlane_b32 s3, v2, 31 169; GFX1064: v_mov_b32_e32 v3, s3 170; GFX1064: v_mov_b32_dpp v4, v3 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf 171; GFX1064: v_add_nc_u32_e32 v2, v2, v4 172; GFX1064: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf 173; GFX1064: v_readlane_b32 s3, v2, 15 174; GFX1064: v_readlane_b32 s6, v2, 31 175; GFX1064: v_writelane_b32 v1, s3, 16 176; GFX1064: v_readlane_b32 s3, v2, 63 177; GFX1064: v_writelane_b32 v1, s6, 32 178; GFX1064: v_readlane_b32 s6, v2, 47 179; GFX1064: v_writelane_b32 v1, s6, 48 180; GFX1064: s_mov_b64 exec, s[4:5] 181; GFX1064: v_cmp_eq_u32_e32 vcc, 0, v0 182; GFX1064: s_and_saveexec_b64 s[4:5], vcc 183; GFX1064: s_cbranch_execz BB4_2 184; GFX1064: BB4_1: 185; GFX1064: v_mov_b32_e32 v0, local_var32@abs32@lo 186; GFX1064: v_mov_b32_e32 v5, s3 187; GFX1064: s_waitcnt vmcnt(0) lgkmcnt(0) 188; GFX1064: s_waitcnt_vscnt null, 0x0 189; GFX1064: ds_add_rtn_u32 v0, v0, v5 190; GFX1064: s_waitcnt vmcnt(0) lgkmcnt(0) 191; GFX1064: buffer_gl0_inv 192; GFX1064: buffer_gl1_inv 193; GFX1064: BB4_2: 194; GFX1064: v_nop 195; GFX1064: s_or_b64 exec, exec, s[4:5] 196; GFX1064: v_readfirstlane_b32 s3, v0 197; GFX1064: v_mov_b32_e32 v0, v1 198; GFX1064: v_add_nc_u32_e32 v0, s3, v0 199; GFX1064: s_mov_b32 s3, 0x31016000 200; GFX1064: s_nop 1 201; GFX1064: s_waitcnt lgkmcnt(0) 202; GFX1064: buffer_store_dword v0, off, s[0:3], 0 203; GFX1064: s_endpgm 204entry: 205 %lane = call i32 @llvm.amdgcn.workitem.id.x() 206 %old = atomicrmw add i32 addrspace(3)* @local_var32, i32 %lane acq_rel 207 store i32 %old, i32 addrspace(1)* %out 208 ret void 209} 210 211; GCN-LABEL: add_i64_constant: 212; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 213; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 214; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 215; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] 216; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] 217; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] 218; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} 219; GCN: v_mul_hi_u32_u24{{(_e[0-9]+)?}} v[[value_hi:[0-9]+]], s[[popcount]], 5 220; GCN: v_mul_u32_u24{{(_e[0-9]+)?}} v[[value_lo:[0-9]+]], s[[popcount]], 5 221; GCN: ds_add_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}[[value_lo]]:[[value_hi]]{{\]}} 222define amdgpu_kernel void @add_i64_constant(i64 addrspace(1)* %out) { 223entry: 224 %old = atomicrmw add i64 addrspace(3)* @local_var64, i64 5 acq_rel 225 store i64 %old, i64 addrspace(1)* %out 226 ret void 227} 228 229; GCN-LABEL: add_i64_uniform: 230; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 231; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 232; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 233; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] 234; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] 235; GCN32: s_bcnt1_i32_b32 s{{[0-9]+}}, s[[exec_lo]] 236; GCN64: s_bcnt1_i32_b64 s{{[0-9]+}}, s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} 237; GCN: ds_add_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}} 238define amdgpu_kernel void @add_i64_uniform(i64 addrspace(1)* %out, i64 %additive) { 239entry: 240 %old = atomicrmw add i64 addrspace(3)* @local_var64, i64 %additive acq_rel 241 store i64 %old, i64 addrspace(1)* %out 242 ret void 243} 244 245; GCN-LABEL: add_i64_varying: 246; GCN-NOT: v_mbcnt_lo_u32_b32 247; GCN-NOT: v_mbcnt_hi_u32_b32 248; GCN-NOT: s_bcnt1_i32_b64 249; GCN: ds_add_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}} 250define amdgpu_kernel void @add_i64_varying(i64 addrspace(1)* %out) { 251entry: 252 %lane = call i32 @llvm.amdgcn.workitem.id.x() 253 %zext = zext i32 %lane to i64 254 %old = atomicrmw add i64 addrspace(3)* @local_var64, i64 %zext acq_rel 255 store i64 %old, i64 addrspace(1)* %out 256 ret void 257} 258 259; GCN-LABEL: sub_i32_constant: 260; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 261; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 262; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 263; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] 264; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] 265; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] 266; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} 267; GCN: v_mul_u32_u24{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[popcount]], 5 268; GCN: ds_sub_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] 269define amdgpu_kernel void @sub_i32_constant(i32 addrspace(1)* %out) { 270entry: 271 %old = atomicrmw sub i32 addrspace(3)* @local_var32, i32 5 acq_rel 272 store i32 %old, i32 addrspace(1)* %out 273 ret void 274} 275 276; GCN-LABEL: sub_i32_uniform: 277; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 278; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 279; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 280; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] 281; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] 282; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] 283; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} 284; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]] 285; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] 286; GCN: ds_sub_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] 287define amdgpu_kernel void @sub_i32_uniform(i32 addrspace(1)* %out, i32 %subitive) { 288entry: 289 %old = atomicrmw sub i32 addrspace(3)* @local_var32, i32 %subitive acq_rel 290 store i32 %old, i32 addrspace(1)* %out 291 ret void 292} 293 294; GCN-LABEL: sub_i32_varying: 295; GFX7LESS-NOT: v_mbcnt_lo_u32_b32 296; GFX7LESS-NOT: v_mbcnt_hi_u32_b32 297; GFX7LESS-NOT: s_bcnt1_i32_b64 298; GFX7LESS: ds_sub_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 299; DPPCOMB: v_add_u32_dpp 300; DPPCOMB: v_add_u32_dpp 301; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31 302; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63 303; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] 304; GFX8MORE: ds_sub_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] 305define amdgpu_kernel void @sub_i32_varying(i32 addrspace(1)* %out) { 306entry: 307 %lane = call i32 @llvm.amdgcn.workitem.id.x() 308 %old = atomicrmw sub i32 addrspace(3)* @local_var32, i32 %lane acq_rel 309 store i32 %old, i32 addrspace(1)* %out 310 ret void 311} 312 313; GCN-LABEL: sub_i64_constant: 314; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 315; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 316; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 317; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] 318; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] 319; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] 320; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} 321; GCN: v_mul_hi_u32_u24{{(_e[0-9]+)?}} v[[value_hi:[0-9]+]], s[[popcount]], 5 322; GCN: v_mul_u32_u24{{(_e[0-9]+)?}} v[[value_lo:[0-9]+]], s[[popcount]], 5 323; GCN: ds_sub_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}[[value_lo]]:[[value_hi]]{{\]}} 324define amdgpu_kernel void @sub_i64_constant(i64 addrspace(1)* %out) { 325entry: 326 %old = atomicrmw sub i64 addrspace(3)* @local_var64, i64 5 acq_rel 327 store i64 %old, i64 addrspace(1)* %out 328 ret void 329} 330 331; GCN-LABEL: sub_i64_uniform: 332; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 333; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 334; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 335; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] 336; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] 337; GCN32: s_bcnt1_i32_b32 s{{[0-9]+}}, s[[exec_lo]] 338; GCN64: s_bcnt1_i32_b64 s{{[0-9]+}}, s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} 339; GCN: ds_sub_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}} 340define amdgpu_kernel void @sub_i64_uniform(i64 addrspace(1)* %out, i64 %subitive) { 341entry: 342 %old = atomicrmw sub i64 addrspace(3)* @local_var64, i64 %subitive acq_rel 343 store i64 %old, i64 addrspace(1)* %out 344 ret void 345} 346 347; GCN-LABEL: sub_i64_varying: 348; GCN-NOT: v_mbcnt_lo_u32_b32 349; GCN-NOT: v_mbcnt_hi_u32_b32 350; GCN-NOT: s_bcnt1_i32_b64 351; GCN: ds_sub_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}} 352define amdgpu_kernel void @sub_i64_varying(i64 addrspace(1)* %out) { 353entry: 354 %lane = call i32 @llvm.amdgcn.workitem.id.x() 355 %zext = zext i32 %lane to i64 356 %old = atomicrmw sub i64 addrspace(3)* @local_var64, i64 %zext acq_rel 357 store i64 %old, i64 addrspace(1)* %out 358 ret void 359} 360 361; GCN-LABEL: and_i32_varying: 362; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31 363; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63 364; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] 365; GFX8MORE: ds_and_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] 366define amdgpu_kernel void @and_i32_varying(i32 addrspace(1)* %out) { 367entry: 368 %lane = call i32 @llvm.amdgcn.workitem.id.x() 369 %old = atomicrmw and i32 addrspace(3)* @local_var32, i32 %lane acq_rel 370 store i32 %old, i32 addrspace(1)* %out 371 ret void 372} 373 374; GCN-LABEL: or_i32_varying: 375; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31 376; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63 377; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] 378; GFX8MORE: ds_or_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] 379define amdgpu_kernel void @or_i32_varying(i32 addrspace(1)* %out) { 380entry: 381 %lane = call i32 @llvm.amdgcn.workitem.id.x() 382 %old = atomicrmw or i32 addrspace(3)* @local_var32, i32 %lane acq_rel 383 store i32 %old, i32 addrspace(1)* %out 384 ret void 385} 386 387; GCN-LABEL: xor_i32_varying: 388; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31 389; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63 390; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] 391; GFX8MORE: ds_xor_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] 392define amdgpu_kernel void @xor_i32_varying(i32 addrspace(1)* %out) { 393entry: 394 %lane = call i32 @llvm.amdgcn.workitem.id.x() 395 %old = atomicrmw xor i32 addrspace(3)* @local_var32, i32 %lane acq_rel 396 store i32 %old, i32 addrspace(1)* %out 397 ret void 398} 399 400; GCN-LABEL: max_i32_varying: 401; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31 402; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63 403; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] 404; GFX8MORE: ds_max_rtn_i32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] 405define amdgpu_kernel void @max_i32_varying(i32 addrspace(1)* %out) { 406entry: 407 %lane = call i32 @llvm.amdgcn.workitem.id.x() 408 %old = atomicrmw max i32 addrspace(3)* @local_var32, i32 %lane acq_rel 409 store i32 %old, i32 addrspace(1)* %out 410 ret void 411} 412 413; GCN-LABEL: max_i64_constant: 414; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 415; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 416; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 417; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] 418; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] 419; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value_lo:[0-9]+]], 5 420; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value_hi:[0-9]+]], 0 421; GCN: ds_max_rtn_i64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}[[value_lo]]:[[value_hi]]{{\]}} 422define amdgpu_kernel void @max_i64_constant(i64 addrspace(1)* %out) { 423entry: 424 %old = atomicrmw max i64 addrspace(3)* @local_var64, i64 5 acq_rel 425 store i64 %old, i64 addrspace(1)* %out 426 ret void 427} 428 429; GCN-LABEL: min_i32_varying: 430; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31 431; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63 432; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] 433; GFX8MORE: ds_min_rtn_i32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] 434define amdgpu_kernel void @min_i32_varying(i32 addrspace(1)* %out) { 435entry: 436 %lane = call i32 @llvm.amdgcn.workitem.id.x() 437 %old = atomicrmw min i32 addrspace(3)* @local_var32, i32 %lane acq_rel 438 store i32 %old, i32 addrspace(1)* %out 439 ret void 440} 441 442; GCN-LABEL: min_i64_constant: 443; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 444; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 445; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 446; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] 447; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] 448; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value_lo:[0-9]+]], 5 449; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value_hi:[0-9]+]], 0 450; GCN: ds_min_rtn_i64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}[[value_lo]]:[[value_hi]]{{\]}} 451define amdgpu_kernel void @min_i64_constant(i64 addrspace(1)* %out) { 452entry: 453 %old = atomicrmw min i64 addrspace(3)* @local_var64, i64 5 acq_rel 454 store i64 %old, i64 addrspace(1)* %out 455 ret void 456} 457 458; GCN-LABEL: umax_i32_varying: 459; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31 460; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63 461; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] 462; GFX8MORE: ds_max_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] 463define amdgpu_kernel void @umax_i32_varying(i32 addrspace(1)* %out) { 464entry: 465 %lane = call i32 @llvm.amdgcn.workitem.id.x() 466 %old = atomicrmw umax i32 addrspace(3)* @local_var32, i32 %lane acq_rel 467 store i32 %old, i32 addrspace(1)* %out 468 ret void 469} 470 471; GCN-LABEL: umax_i64_constant: 472; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 473; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 474; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 475; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] 476; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] 477; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value_lo:[0-9]+]], 5 478; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value_hi:[0-9]+]], 0 479; GCN: ds_max_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}[[value_lo]]:[[value_hi]]{{\]}} 480define amdgpu_kernel void @umax_i64_constant(i64 addrspace(1)* %out) { 481entry: 482 %old = atomicrmw umax i64 addrspace(3)* @local_var64, i64 5 acq_rel 483 store i64 %old, i64 addrspace(1)* %out 484 ret void 485} 486 487; GCN-LABEL: umin_i32_varying: 488; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31 489; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63 490; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] 491; GFX8MORE: ds_min_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] 492define amdgpu_kernel void @umin_i32_varying(i32 addrspace(1)* %out) { 493entry: 494 %lane = call i32 @llvm.amdgcn.workitem.id.x() 495 %old = atomicrmw umin i32 addrspace(3)* @local_var32, i32 %lane acq_rel 496 store i32 %old, i32 addrspace(1)* %out 497 ret void 498} 499 500; GCN-LABEL: umin_i64_constant: 501; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 502; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 503; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 504; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] 505; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] 506; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value_lo:[0-9]+]], 5 507; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value_hi:[0-9]+]], 0 508; GCN: ds_min_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}[[value_lo]]:[[value_hi]]{{\]}} 509define amdgpu_kernel void @umin_i64_constant(i64 addrspace(1)* %out) { 510entry: 511 %old = atomicrmw umin i64 addrspace(3)* @local_var64, i64 5 acq_rel 512 store i64 %old, i64 addrspace(1)* %out 513 ret void 514} 515