1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -S -mtriple=amdgcn-unknown-unknown -amdgpu-annotate-kernel-features < %s | FileCheck %s
3
4declare i32 @llvm.r600.read.tgid.x() #0
5declare i32 @llvm.r600.read.tgid.y() #0
6declare i32 @llvm.r600.read.tgid.z() #0
7
8declare i32 @llvm.r600.read.tidig.x() #0
9declare i32 @llvm.r600.read.tidig.y() #0
10declare i32 @llvm.r600.read.tidig.z() #0
11
12declare i32 @llvm.r600.read.local.size.x() #0
13declare i32 @llvm.r600.read.local.size.y() #0
14declare i32 @llvm.r600.read.local.size.z() #0
15
16define amdgpu_kernel void @use_tgid_x(i32 addrspace(1)* %ptr) #1 {
17; CHECK-LABEL: @use_tgid_x(
18; CHECK-NEXT:    [[VAL:%.*]] = call i32 @llvm.r600.read.tgid.x()
19; CHECK-NEXT:    store i32 [[VAL]], i32 addrspace(1)* [[PTR:%.*]], align 4
20; CHECK-NEXT:    ret void
21;
22  %val = call i32 @llvm.r600.read.tgid.x()
23  store i32 %val, i32 addrspace(1)* %ptr
24  ret void
25}
26
27define amdgpu_kernel void @use_tgid_y(i32 addrspace(1)* %ptr) #1 {
28; CHECK-LABEL: @use_tgid_y(
29; CHECK-NEXT:    [[VAL:%.*]] = call i32 @llvm.r600.read.tgid.y()
30; CHECK-NEXT:    store i32 [[VAL]], i32 addrspace(1)* [[PTR:%.*]], align 4
31; CHECK-NEXT:    ret void
32;
33  %val = call i32 @llvm.r600.read.tgid.y()
34  store i32 %val, i32 addrspace(1)* %ptr
35  ret void
36}
37
38define amdgpu_kernel void @multi_use_tgid_y(i32 addrspace(1)* %ptr) #1 {
39; CHECK-LABEL: @multi_use_tgid_y(
40; CHECK-NEXT:    [[VAL0:%.*]] = call i32 @llvm.r600.read.tgid.y()
41; CHECK-NEXT:    store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR:%.*]], align 4
42; CHECK-NEXT:    [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y()
43; CHECK-NEXT:    store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4
44; CHECK-NEXT:    ret void
45;
46  %val0 = call i32 @llvm.r600.read.tgid.y()
47  store volatile i32 %val0, i32 addrspace(1)* %ptr
48  %val1 = call i32 @llvm.r600.read.tgid.y()
49  store volatile i32 %val1, i32 addrspace(1)* %ptr
50  ret void
51}
52
53define amdgpu_kernel void @use_tgid_x_y(i32 addrspace(1)* %ptr) #1 {
54; CHECK-LABEL: @use_tgid_x_y(
55; CHECK-NEXT:    [[VAL0:%.*]] = call i32 @llvm.r600.read.tgid.x()
56; CHECK-NEXT:    [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y()
57; CHECK-NEXT:    store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR:%.*]], align 4
58; CHECK-NEXT:    store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4
59; CHECK-NEXT:    ret void
60;
61  %val0 = call i32 @llvm.r600.read.tgid.x()
62  %val1 = call i32 @llvm.r600.read.tgid.y()
63  store volatile i32 %val0, i32 addrspace(1)* %ptr
64  store volatile i32 %val1, i32 addrspace(1)* %ptr
65  ret void
66}
67
68define amdgpu_kernel void @use_tgid_z(i32 addrspace(1)* %ptr) #1 {
69; CHECK-LABEL: @use_tgid_z(
70; CHECK-NEXT:    [[VAL:%.*]] = call i32 @llvm.r600.read.tgid.z()
71; CHECK-NEXT:    store i32 [[VAL]], i32 addrspace(1)* [[PTR:%.*]], align 4
72; CHECK-NEXT:    ret void
73;
74  %val = call i32 @llvm.r600.read.tgid.z()
75  store i32 %val, i32 addrspace(1)* %ptr
76  ret void
77}
78
79define amdgpu_kernel void @use_tgid_x_z(i32 addrspace(1)* %ptr) #1 {
80; CHECK-LABEL: @use_tgid_x_z(
81; CHECK-NEXT:    [[VAL0:%.*]] = call i32 @llvm.r600.read.tgid.x()
82; CHECK-NEXT:    [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.z()
83; CHECK-NEXT:    store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR:%.*]], align 4
84; CHECK-NEXT:    store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4
85; CHECK-NEXT:    ret void
86;
87  %val0 = call i32 @llvm.r600.read.tgid.x()
88  %val1 = call i32 @llvm.r600.read.tgid.z()
89  store volatile i32 %val0, i32 addrspace(1)* %ptr
90  store volatile i32 %val1, i32 addrspace(1)* %ptr
91  ret void
92}
93
94define amdgpu_kernel void @use_tgid_y_z(i32 addrspace(1)* %ptr) #1 {
95; CHECK-LABEL: @use_tgid_y_z(
96; CHECK-NEXT:    [[VAL0:%.*]] = call i32 @llvm.r600.read.tgid.y()
97; CHECK-NEXT:    [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.z()
98; CHECK-NEXT:    store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR:%.*]], align 4
99; CHECK-NEXT:    store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4
100; CHECK-NEXT:    ret void
101;
102  %val0 = call i32 @llvm.r600.read.tgid.y()
103  %val1 = call i32 @llvm.r600.read.tgid.z()
104  store volatile i32 %val0, i32 addrspace(1)* %ptr
105  store volatile i32 %val1, i32 addrspace(1)* %ptr
106  ret void
107}
108
109define amdgpu_kernel void @use_tgid_x_y_z(i32 addrspace(1)* %ptr) #1 {
110; CHECK-LABEL: @use_tgid_x_y_z(
111; CHECK-NEXT:    [[VAL0:%.*]] = call i32 @llvm.r600.read.tgid.x()
112; CHECK-NEXT:    [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y()
113; CHECK-NEXT:    [[VAL2:%.*]] = call i32 @llvm.r600.read.tgid.z()
114; CHECK-NEXT:    store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR:%.*]], align 4
115; CHECK-NEXT:    store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4
116; CHECK-NEXT:    store volatile i32 [[VAL2]], i32 addrspace(1)* [[PTR]], align 4
117; CHECK-NEXT:    ret void
118;
119  %val0 = call i32 @llvm.r600.read.tgid.x()
120  %val1 = call i32 @llvm.r600.read.tgid.y()
121  %val2 = call i32 @llvm.r600.read.tgid.z()
122  store volatile i32 %val0, i32 addrspace(1)* %ptr
123  store volatile i32 %val1, i32 addrspace(1)* %ptr
124  store volatile i32 %val2, i32 addrspace(1)* %ptr
125  ret void
126}
127
128define amdgpu_kernel void @use_tidig_x(i32 addrspace(1)* %ptr) #1 {
129; CHECK-LABEL: @use_tidig_x(
130; CHECK-NEXT:    [[VAL:%.*]] = call i32 @llvm.r600.read.tidig.x()
131; CHECK-NEXT:    store i32 [[VAL]], i32 addrspace(1)* [[PTR:%.*]], align 4
132; CHECK-NEXT:    ret void
133;
134  %val = call i32 @llvm.r600.read.tidig.x()
135  store i32 %val, i32 addrspace(1)* %ptr
136  ret void
137}
138
139define amdgpu_kernel void @use_tidig_y(i32 addrspace(1)* %ptr) #1 {
140; CHECK-LABEL: @use_tidig_y(
141; CHECK-NEXT:    [[VAL:%.*]] = call i32 @llvm.r600.read.tidig.y()
142; CHECK-NEXT:    store i32 [[VAL]], i32 addrspace(1)* [[PTR:%.*]], align 4
143; CHECK-NEXT:    ret void
144;
145  %val = call i32 @llvm.r600.read.tidig.y()
146  store i32 %val, i32 addrspace(1)* %ptr
147  ret void
148}
149
150define amdgpu_kernel void @use_tidig_z(i32 addrspace(1)* %ptr) #1 {
151; CHECK-LABEL: @use_tidig_z(
152; CHECK-NEXT:    [[VAL:%.*]] = call i32 @llvm.r600.read.tidig.z()
153; CHECK-NEXT:    store i32 [[VAL]], i32 addrspace(1)* [[PTR:%.*]], align 4
154; CHECK-NEXT:    ret void
155;
156  %val = call i32 @llvm.r600.read.tidig.z()
157  store i32 %val, i32 addrspace(1)* %ptr
158  ret void
159}
160
161define amdgpu_kernel void @use_tidig_x_tgid_x(i32 addrspace(1)* %ptr) #1 {
162; CHECK-LABEL: @use_tidig_x_tgid_x(
163; CHECK-NEXT:    [[VAL0:%.*]] = call i32 @llvm.r600.read.tidig.x()
164; CHECK-NEXT:    [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.x()
165; CHECK-NEXT:    store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR:%.*]], align 4
166; CHECK-NEXT:    store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4
167; CHECK-NEXT:    ret void
168;
169  %val0 = call i32 @llvm.r600.read.tidig.x()
170  %val1 = call i32 @llvm.r600.read.tgid.x()
171  store volatile i32 %val0, i32 addrspace(1)* %ptr
172  store volatile i32 %val1, i32 addrspace(1)* %ptr
173  ret void
174}
175
176define amdgpu_kernel void @use_tidig_y_tgid_y(i32 addrspace(1)* %ptr) #1 {
177; CHECK-LABEL: @use_tidig_y_tgid_y(
178; CHECK-NEXT:    [[VAL0:%.*]] = call i32 @llvm.r600.read.tidig.y()
179; CHECK-NEXT:    [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y()
180; CHECK-NEXT:    store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR:%.*]], align 4
181; CHECK-NEXT:    store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4
182; CHECK-NEXT:    ret void
183;
184  %val0 = call i32 @llvm.r600.read.tidig.y()
185  %val1 = call i32 @llvm.r600.read.tgid.y()
186  store volatile i32 %val0, i32 addrspace(1)* %ptr
187  store volatile i32 %val1, i32 addrspace(1)* %ptr
188  ret void
189}
190
191define amdgpu_kernel void @use_tidig_x_y_z(i32 addrspace(1)* %ptr) #1 {
192; CHECK-LABEL: @use_tidig_x_y_z(
193; CHECK-NEXT:    [[VAL0:%.*]] = call i32 @llvm.r600.read.tidig.x()
194; CHECK-NEXT:    [[VAL1:%.*]] = call i32 @llvm.r600.read.tidig.y()
195; CHECK-NEXT:    [[VAL2:%.*]] = call i32 @llvm.r600.read.tidig.z()
196; CHECK-NEXT:    store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR:%.*]], align 4
197; CHECK-NEXT:    store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4
198; CHECK-NEXT:    store volatile i32 [[VAL2]], i32 addrspace(1)* [[PTR]], align 4
199; CHECK-NEXT:    ret void
200;
201  %val0 = call i32 @llvm.r600.read.tidig.x()
202  %val1 = call i32 @llvm.r600.read.tidig.y()
203  %val2 = call i32 @llvm.r600.read.tidig.z()
204  store volatile i32 %val0, i32 addrspace(1)* %ptr
205  store volatile i32 %val1, i32 addrspace(1)* %ptr
206  store volatile i32 %val2, i32 addrspace(1)* %ptr
207  ret void
208}
209
210define amdgpu_kernel void @use_all_workitems(i32 addrspace(1)* %ptr) #1 {
211; CHECK-LABEL: @use_all_workitems(
212; CHECK-NEXT:    [[VAL0:%.*]] = call i32 @llvm.r600.read.tidig.x()
213; CHECK-NEXT:    [[VAL1:%.*]] = call i32 @llvm.r600.read.tidig.y()
214; CHECK-NEXT:    [[VAL2:%.*]] = call i32 @llvm.r600.read.tidig.z()
215; CHECK-NEXT:    [[VAL3:%.*]] = call i32 @llvm.r600.read.tgid.x()
216; CHECK-NEXT:    [[VAL4:%.*]] = call i32 @llvm.r600.read.tgid.y()
217; CHECK-NEXT:    [[VAL5:%.*]] = call i32 @llvm.r600.read.tgid.z()
218; CHECK-NEXT:    store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR:%.*]], align 4
219; CHECK-NEXT:    store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4
220; CHECK-NEXT:    store volatile i32 [[VAL2]], i32 addrspace(1)* [[PTR]], align 4
221; CHECK-NEXT:    store volatile i32 [[VAL3]], i32 addrspace(1)* [[PTR]], align 4
222; CHECK-NEXT:    store volatile i32 [[VAL4]], i32 addrspace(1)* [[PTR]], align 4
223; CHECK-NEXT:    store volatile i32 [[VAL5]], i32 addrspace(1)* [[PTR]], align 4
224; CHECK-NEXT:    ret void
225;
226  %val0 = call i32 @llvm.r600.read.tidig.x()
227  %val1 = call i32 @llvm.r600.read.tidig.y()
228  %val2 = call i32 @llvm.r600.read.tidig.z()
229  %val3 = call i32 @llvm.r600.read.tgid.x()
230  %val4 = call i32 @llvm.r600.read.tgid.y()
231  %val5 = call i32 @llvm.r600.read.tgid.z()
232  store volatile i32 %val0, i32 addrspace(1)* %ptr
233  store volatile i32 %val1, i32 addrspace(1)* %ptr
234  store volatile i32 %val2, i32 addrspace(1)* %ptr
235  store volatile i32 %val3, i32 addrspace(1)* %ptr
236  store volatile i32 %val4, i32 addrspace(1)* %ptr
237  store volatile i32 %val5, i32 addrspace(1)* %ptr
238  ret void
239}
240
241define amdgpu_kernel void @use_get_local_size_x(i32 addrspace(1)* %ptr) #1 {
242; CHECK-LABEL: @use_get_local_size_x(
243; CHECK-NEXT:    [[VAL:%.*]] = call i32 @llvm.r600.read.local.size.x()
244; CHECK-NEXT:    store i32 [[VAL]], i32 addrspace(1)* [[PTR:%.*]], align 4
245; CHECK-NEXT:    ret void
246;
247  %val = call i32 @llvm.r600.read.local.size.x()
248  store i32 %val, i32 addrspace(1)* %ptr
249  ret void
250}
251
252define amdgpu_kernel void @use_get_local_size_y(i32 addrspace(1)* %ptr) #1 {
253; CHECK-LABEL: @use_get_local_size_y(
254; CHECK-NEXT:    [[VAL:%.*]] = call i32 @llvm.r600.read.local.size.y()
255; CHECK-NEXT:    store i32 [[VAL]], i32 addrspace(1)* [[PTR:%.*]], align 4
256; CHECK-NEXT:    ret void
257;
258  %val = call i32 @llvm.r600.read.local.size.y()
259  store i32 %val, i32 addrspace(1)* %ptr
260  ret void
261}
262
263define amdgpu_kernel void @use_get_local_size_z(i32 addrspace(1)* %ptr) #1 {
264; CHECK-LABEL: @use_get_local_size_z(
265; CHECK-NEXT:    [[VAL:%.*]] = call i32 @llvm.r600.read.local.size.z()
266; CHECK-NEXT:    store i32 [[VAL]], i32 addrspace(1)* [[PTR:%.*]], align 4
267; CHECK-NEXT:    ret void
268;
269  %val = call i32 @llvm.r600.read.local.size.z()
270  store i32 %val, i32 addrspace(1)* %ptr
271  ret void
272}
273
274attributes #0 = { nounwind readnone }
275attributes #1 = { nounwind }
276
277; HSA: attributes #0 = { nounwind readnone }
278; HSA: attributes #1 = { nounwind }
279; HSA: attributes #2 = { nounwind "amdgpu-work-group-id-y" }
280; HSA: attributes #3 = { nounwind "amdgpu-work-group-id-z" }
281; HSA: attributes #4 = { nounwind "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" }
282; HSA: attributes #5 = { nounwind "amdgpu-work-item-id-y" }
283; HSA: attributes #6 = { nounwind "amdgpu-work-item-id-z" }
284; HSA: attributes #7 = { nounwind "amdgpu-work-group-id-y" "amdgpu-work-item-id-y" }
285; HSA: attributes #8 = { nounwind "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" }
286; HSA: attributes #9 = { nounwind "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" }
287; HSA: attributes #10 = { nounwind "amdgpu-dispatch-ptr" }
288