1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals 2; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-annotate-kernel-features %s | FileCheck -check-prefix=HSA %s 3 4declare i32 @llvm.amdgcn.workgroup.id.x() #0 5declare i32 @llvm.amdgcn.workgroup.id.y() #0 6declare i32 @llvm.amdgcn.workgroup.id.z() #0 7 8declare i32 @llvm.amdgcn.workitem.id.x() #0 9declare i32 @llvm.amdgcn.workitem.id.y() #0 10declare i32 @llvm.amdgcn.workitem.id.z() #0 11 12declare i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0 13declare i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0 14declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0 15declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0 16declare i64 @llvm.amdgcn.dispatch.id() #0 17 18define void @use_workitem_id_x() #1 { 19; HSA-LABEL: define {{[^@]+}}@use_workitem_id_x 20; HSA-SAME: () #[[ATTR1:[0-9]+]] { 21; HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() 22; HSA-NEXT: store volatile i32 [[VAL]], i32 addrspace(1)* undef, align 4 23; HSA-NEXT: ret void 24; 25 %val = call i32 @llvm.amdgcn.workitem.id.x() 26 store volatile i32 %val, i32 addrspace(1)* undef 27 ret void 28} 29 30define void @use_workitem_id_y() #1 { 31; HSA-LABEL: define {{[^@]+}}@use_workitem_id_y 32; HSA-SAME: () #[[ATTR2:[0-9]+]] { 33; HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() 34; HSA-NEXT: store volatile i32 [[VAL]], i32 addrspace(1)* undef, align 4 35; HSA-NEXT: ret void 36; 37 %val = call i32 @llvm.amdgcn.workitem.id.y() 38 store volatile i32 %val, i32 addrspace(1)* undef 39 ret void 40} 41 42define void @use_workitem_id_z() #1 { 43; HSA-LABEL: define {{[^@]+}}@use_workitem_id_z 44; HSA-SAME: () #[[ATTR3:[0-9]+]] { 45; HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.z() 46; HSA-NEXT: store volatile i32 [[VAL]], i32 addrspace(1)* undef, align 4 47; HSA-NEXT: ret void 48; 49 %val = call i32 @llvm.amdgcn.workitem.id.z() 50 store volatile i32 %val, i32 addrspace(1)* undef 51 ret void 52} 53 54define void @use_workgroup_id_x() #1 { 55; HSA-LABEL: define {{[^@]+}}@use_workgroup_id_x 56; HSA-SAME: () #[[ATTR4:[0-9]+]] { 57; HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 58; HSA-NEXT: store volatile i32 [[VAL]], i32 addrspace(1)* undef, align 4 59; HSA-NEXT: ret void 60; 61 %val = call i32 @llvm.amdgcn.workgroup.id.x() 62 store volatile i32 %val, i32 addrspace(1)* undef 63 ret void 64} 65 66define void @use_workgroup_id_y() #1 { 67; HSA-LABEL: define {{[^@]+}}@use_workgroup_id_y 68; HSA-SAME: () #[[ATTR5:[0-9]+]] { 69; HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 70; HSA-NEXT: store volatile i32 [[VAL]], i32 addrspace(1)* undef, align 4 71; HSA-NEXT: ret void 72; 73 %val = call i32 @llvm.amdgcn.workgroup.id.y() 74 store volatile i32 %val, i32 addrspace(1)* undef 75 ret void 76} 77 78define void @use_workgroup_id_z() #1 { 79; HSA-LABEL: define {{[^@]+}}@use_workgroup_id_z 80; HSA-SAME: () #[[ATTR6:[0-9]+]] { 81; HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 82; HSA-NEXT: store volatile i32 [[VAL]], i32 addrspace(1)* undef, align 4 83; HSA-NEXT: ret void 84; 85 %val = call i32 @llvm.amdgcn.workgroup.id.z() 86 store volatile i32 %val, i32 addrspace(1)* undef 87 ret void 88} 89 90define void @use_dispatch_ptr() #1 { 91; HSA-LABEL: define {{[^@]+}}@use_dispatch_ptr 92; HSA-SAME: () #[[ATTR7:[0-9]+]] { 93; HSA-NEXT: [[DISPATCH_PTR:%.*]] = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 94; HSA-NEXT: store volatile i8 addrspace(4)* [[DISPATCH_PTR]], i8 addrspace(4)* addrspace(1)* undef, align 8 95; HSA-NEXT: ret void 96; 97 %dispatch.ptr = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 98 store volatile i8 addrspace(4)* %dispatch.ptr, i8 addrspace(4)* addrspace(1)* undef 99 ret void 100} 101 102define void @use_queue_ptr() #1 { 103; HSA-LABEL: define {{[^@]+}}@use_queue_ptr 104; HSA-SAME: () #[[ATTR8:[0-9]+]] { 105; HSA-NEXT: [[QUEUE_PTR:%.*]] = call i8 addrspace(4)* @llvm.amdgcn.queue.ptr() 106; HSA-NEXT: store volatile i8 addrspace(4)* [[QUEUE_PTR]], i8 addrspace(4)* addrspace(1)* undef, align 8 107; HSA-NEXT: ret void 108; 109 %queue.ptr = call i8 addrspace(4)* @llvm.amdgcn.queue.ptr() 110 store volatile i8 addrspace(4)* %queue.ptr, i8 addrspace(4)* addrspace(1)* undef 111 ret void 112} 113 114define void @use_dispatch_id() #1 { 115; HSA-LABEL: define {{[^@]+}}@use_dispatch_id 116; HSA-SAME: () #[[ATTR9:[0-9]+]] { 117; HSA-NEXT: [[VAL:%.*]] = call i64 @llvm.amdgcn.dispatch.id() 118; HSA-NEXT: store volatile i64 [[VAL]], i64 addrspace(1)* undef, align 4 119; HSA-NEXT: ret void 120; 121 %val = call i64 @llvm.amdgcn.dispatch.id() 122 store volatile i64 %val, i64 addrspace(1)* undef 123 ret void 124} 125 126define void @use_workgroup_id_y_workgroup_id_z() #1 { 127; HSA-LABEL: define {{[^@]+}}@use_workgroup_id_y_workgroup_id_z 128; HSA-SAME: () #[[ATTR10:[0-9]+]] { 129; HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 130; HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 131; HSA-NEXT: store volatile i32 [[VAL0]], i32 addrspace(1)* undef, align 4 132; HSA-NEXT: store volatile i32 [[VAL1]], i32 addrspace(1)* undef, align 4 133; HSA-NEXT: ret void 134; 135 %val0 = call i32 @llvm.amdgcn.workgroup.id.y() 136 %val1 = call i32 @llvm.amdgcn.workgroup.id.z() 137 store volatile i32 %val0, i32 addrspace(1)* undef 138 store volatile i32 %val1, i32 addrspace(1)* undef 139 ret void 140} 141 142define void @func_indirect_use_workitem_id_x() #1 { 143; HSA-LABEL: define {{[^@]+}}@func_indirect_use_workitem_id_x 144; HSA-SAME: () #[[ATTR1]] { 145; HSA-NEXT: call void @use_workitem_id_x() 146; HSA-NEXT: ret void 147; 148 call void @use_workitem_id_x() 149 ret void 150} 151 152define void @kernel_indirect_use_workitem_id_x() #1 { 153; HSA-LABEL: define {{[^@]+}}@kernel_indirect_use_workitem_id_x 154; HSA-SAME: () #[[ATTR1]] { 155; HSA-NEXT: call void @use_workitem_id_x() 156; HSA-NEXT: ret void 157; 158 call void @use_workitem_id_x() 159 ret void 160} 161 162define void @func_indirect_use_workitem_id_y() #1 { 163; HSA-LABEL: define {{[^@]+}}@func_indirect_use_workitem_id_y 164; HSA-SAME: () #[[ATTR2]] { 165; HSA-NEXT: call void @use_workitem_id_y() 166; HSA-NEXT: ret void 167; 168 call void @use_workitem_id_y() 169 ret void 170} 171 172define void @func_indirect_use_workitem_id_z() #1 { 173; HSA-LABEL: define {{[^@]+}}@func_indirect_use_workitem_id_z 174; HSA-SAME: () #[[ATTR3]] { 175; HSA-NEXT: call void @use_workitem_id_z() 176; HSA-NEXT: ret void 177; 178 call void @use_workitem_id_z() 179 ret void 180} 181 182define void @func_indirect_use_workgroup_id_x() #1 { 183; HSA-LABEL: define {{[^@]+}}@func_indirect_use_workgroup_id_x 184; HSA-SAME: () #[[ATTR4]] { 185; HSA-NEXT: call void @use_workgroup_id_x() 186; HSA-NEXT: ret void 187; 188 call void @use_workgroup_id_x() 189 ret void 190} 191 192define void @kernel_indirect_use_workgroup_id_x() #1 { 193; HSA-LABEL: define {{[^@]+}}@kernel_indirect_use_workgroup_id_x 194; HSA-SAME: () #[[ATTR4]] { 195; HSA-NEXT: call void @use_workgroup_id_x() 196; HSA-NEXT: ret void 197; 198 call void @use_workgroup_id_x() 199 ret void 200} 201 202define void @func_indirect_use_workgroup_id_y() #1 { 203; HSA-LABEL: define {{[^@]+}}@func_indirect_use_workgroup_id_y 204; HSA-SAME: () #[[ATTR5]] { 205; HSA-NEXT: call void @use_workgroup_id_y() 206; HSA-NEXT: ret void 207; 208 call void @use_workgroup_id_y() 209 ret void 210} 211 212define void @func_indirect_use_workgroup_id_z() #1 { 213; HSA-LABEL: define {{[^@]+}}@func_indirect_use_workgroup_id_z 214; HSA-SAME: () #[[ATTR6]] { 215; HSA-NEXT: call void @use_workgroup_id_z() 216; HSA-NEXT: ret void 217; 218 call void @use_workgroup_id_z() 219 ret void 220} 221 222define void @func_indirect_indirect_use_workgroup_id_y() #1 { 223; HSA-LABEL: define {{[^@]+}}@func_indirect_indirect_use_workgroup_id_y 224; HSA-SAME: () #[[ATTR5]] { 225; HSA-NEXT: call void @func_indirect_use_workgroup_id_y() 226; HSA-NEXT: ret void 227; 228 call void @func_indirect_use_workgroup_id_y() 229 ret void 230} 231 232define void @indirect_x2_use_workgroup_id_y() #1 { 233; HSA-LABEL: define {{[^@]+}}@indirect_x2_use_workgroup_id_y 234; HSA-SAME: () #[[ATTR5]] { 235; HSA-NEXT: call void @func_indirect_indirect_use_workgroup_id_y() 236; HSA-NEXT: ret void 237; 238 call void @func_indirect_indirect_use_workgroup_id_y() 239 ret void 240} 241 242define void @func_indirect_use_dispatch_ptr() #1 { 243; HSA-LABEL: define {{[^@]+}}@func_indirect_use_dispatch_ptr 244; HSA-SAME: () #[[ATTR7]] { 245; HSA-NEXT: call void @use_dispatch_ptr() 246; HSA-NEXT: ret void 247; 248 call void @use_dispatch_ptr() 249 ret void 250} 251 252define void @func_indirect_use_queue_ptr() #1 { 253; HSA-LABEL: define {{[^@]+}}@func_indirect_use_queue_ptr 254; HSA-SAME: () #[[ATTR8]] { 255; HSA-NEXT: call void @use_queue_ptr() 256; HSA-NEXT: ret void 257; 258 call void @use_queue_ptr() 259 ret void 260} 261 262define void @func_indirect_use_dispatch_id() #1 { 263; HSA-LABEL: define {{[^@]+}}@func_indirect_use_dispatch_id 264; HSA-SAME: () #[[ATTR9]] { 265; HSA-NEXT: call void @use_dispatch_id() 266; HSA-NEXT: ret void 267; 268 call void @use_dispatch_id() 269 ret void 270} 271 272define void @func_indirect_use_workgroup_id_y_workgroup_id_z() #1 { 273; HSA-LABEL: define {{[^@]+}}@func_indirect_use_workgroup_id_y_workgroup_id_z 274; HSA-SAME: () #[[ATTR11:[0-9]+]] { 275; HSA-NEXT: call void @func_indirect_use_workgroup_id_y_workgroup_id_z() 276; HSA-NEXT: ret void 277; 278 call void @func_indirect_use_workgroup_id_y_workgroup_id_z() 279 ret void 280} 281 282define void @recursive_use_workitem_id_y() #1 { 283; HSA-LABEL: define {{[^@]+}}@recursive_use_workitem_id_y 284; HSA-SAME: () #[[ATTR2]] { 285; HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() 286; HSA-NEXT: store volatile i32 [[VAL]], i32 addrspace(1)* undef, align 4 287; HSA-NEXT: call void @recursive_use_workitem_id_y() 288; HSA-NEXT: ret void 289; 290 %val = call i32 @llvm.amdgcn.workitem.id.y() 291 store volatile i32 %val, i32 addrspace(1)* undef 292 call void @recursive_use_workitem_id_y() 293 ret void 294} 295 296define void @call_recursive_use_workitem_id_y() #1 { 297; HSA-LABEL: define {{[^@]+}}@call_recursive_use_workitem_id_y 298; HSA-SAME: () #[[ATTR2]] { 299; HSA-NEXT: call void @recursive_use_workitem_id_y() 300; HSA-NEXT: ret void 301; 302 call void @recursive_use_workitem_id_y() 303 ret void 304} 305 306define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #1 { 307; HSA-LABEL: define {{[^@]+}}@use_group_to_flat_addrspacecast 308; HSA-SAME: (i32 addrspace(3)* [[PTR:%.*]]) #[[ATTR8]] { 309; HSA-NEXT: [[STOF:%.*]] = addrspacecast i32 addrspace(3)* [[PTR]] to i32 addrspace(4)* 310; HSA-NEXT: store volatile i32 0, i32 addrspace(4)* [[STOF]], align 4 311; HSA-NEXT: ret void 312; 313 %stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* 314 store volatile i32 0, i32 addrspace(4)* %stof 315 ret void 316} 317 318define void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* %ptr) #2 { 319; HSA-LABEL: define {{[^@]+}}@use_group_to_flat_addrspacecast_gfx9 320; HSA-SAME: (i32 addrspace(3)* [[PTR:%.*]]) #[[ATTR12:[0-9]+]] { 321; HSA-NEXT: [[STOF:%.*]] = addrspacecast i32 addrspace(3)* [[PTR]] to i32 addrspace(4)* 322; HSA-NEXT: store volatile i32 0, i32 addrspace(4)* [[STOF]], align 4 323; HSA-NEXT: ret void 324; 325 %stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* 326 store volatile i32 0, i32 addrspace(4)* %stof 327 ret void 328} 329 330define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* %ptr) #2 { 331; HSA-LABEL: define {{[^@]+}}@use_group_to_flat_addrspacecast_queue_ptr_gfx9 332; HSA-SAME: (i32 addrspace(3)* [[PTR:%.*]]) #[[ATTR13:[0-9]+]] { 333; HSA-NEXT: [[STOF:%.*]] = addrspacecast i32 addrspace(3)* [[PTR]] to i32 addrspace(4)* 334; HSA-NEXT: store volatile i32 0, i32 addrspace(4)* [[STOF]], align 4 335; HSA-NEXT: call void @func_indirect_use_queue_ptr() 336; HSA-NEXT: ret void 337; 338 %stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* 339 store volatile i32 0, i32 addrspace(4)* %stof 340 call void @func_indirect_use_queue_ptr() 341 ret void 342} 343 344define void @indirect_use_group_to_flat_addrspacecast() #1 { 345; HSA-LABEL: define {{[^@]+}}@indirect_use_group_to_flat_addrspacecast 346; HSA-SAME: () #[[ATTR8]] { 347; HSA-NEXT: call void @use_group_to_flat_addrspacecast(i32 addrspace(3)* null) 348; HSA-NEXT: ret void 349; 350 call void @use_group_to_flat_addrspacecast(i32 addrspace(3)* null) 351 ret void 352} 353 354define void @indirect_use_group_to_flat_addrspacecast_gfx9() #1 { 355; HSA-LABEL: define {{[^@]+}}@indirect_use_group_to_flat_addrspacecast_gfx9 356; HSA-SAME: () #[[ATTR11]] { 357; HSA-NEXT: call void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* null) 358; HSA-NEXT: ret void 359; 360 call void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* null) 361 ret void 362} 363 364define void @indirect_use_group_to_flat_addrspacecast_queue_ptr_gfx9() #1 { 365; HSA-LABEL: define {{[^@]+}}@indirect_use_group_to_flat_addrspacecast_queue_ptr_gfx9 366; HSA-SAME: () #[[ATTR8]] { 367; HSA-NEXT: call void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* null) 368; HSA-NEXT: ret void 369; 370 call void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* null) 371 ret void 372} 373 374define void @use_kernarg_segment_ptr() #1 { 375; HSA-LABEL: define {{[^@]+}}@use_kernarg_segment_ptr 376; HSA-SAME: () #[[ATTR14:[0-9]+]] { 377; HSA-NEXT: [[KERNARG_SEGMENT_PTR:%.*]] = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() 378; HSA-NEXT: store volatile i8 addrspace(4)* [[KERNARG_SEGMENT_PTR]], i8 addrspace(4)* addrspace(1)* undef, align 8 379; HSA-NEXT: ret void 380; 381 %kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() 382 store volatile i8 addrspace(4)* %kernarg.segment.ptr, i8 addrspace(4)* addrspace(1)* undef 383 ret void 384} 385 386define void @func_indirect_use_kernarg_segment_ptr() #1 { 387; HSA-LABEL: define {{[^@]+}}@func_indirect_use_kernarg_segment_ptr 388; HSA-SAME: () #[[ATTR11]] { 389; HSA-NEXT: call void @use_kernarg_segment_ptr() 390; HSA-NEXT: ret void 391; 392 call void @use_kernarg_segment_ptr() 393 ret void 394} 395 396define amdgpu_kernel void @kern_use_implicitarg_ptr() #1 { 397; HSA-LABEL: define {{[^@]+}}@kern_use_implicitarg_ptr 398; HSA-SAME: () #[[ATTR15:[0-9]+]] { 399; HSA-NEXT: [[IMPLICITARG_PTR:%.*]] = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() 400; HSA-NEXT: store volatile i8 addrspace(4)* [[IMPLICITARG_PTR]], i8 addrspace(4)* addrspace(1)* undef, align 8 401; HSA-NEXT: ret void 402; 403 %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() 404 store volatile i8 addrspace(4)* %implicitarg.ptr, i8 addrspace(4)* addrspace(1)* undef 405 ret void 406} 407 408define void @use_implicitarg_ptr() #1 { 409; HSA-LABEL: define {{[^@]+}}@use_implicitarg_ptr 410; HSA-SAME: () #[[ATTR16:[0-9]+]] { 411; HSA-NEXT: [[IMPLICITARG_PTR:%.*]] = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() 412; HSA-NEXT: store volatile i8 addrspace(4)* [[IMPLICITARG_PTR]], i8 addrspace(4)* addrspace(1)* undef, align 8 413; HSA-NEXT: ret void 414; 415 %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() 416 store volatile i8 addrspace(4)* %implicitarg.ptr, i8 addrspace(4)* addrspace(1)* undef 417 ret void 418} 419 420define void @func_indirect_use_implicitarg_ptr() #1 { 421; HSA-LABEL: define {{[^@]+}}@func_indirect_use_implicitarg_ptr 422; HSA-SAME: () #[[ATTR16]] { 423; HSA-NEXT: call void @use_implicitarg_ptr() 424; HSA-NEXT: ret void 425; 426 call void @use_implicitarg_ptr() 427 ret void 428} 429 430declare void @external.func() #3 431 432define internal void @defined.func() #3 { 433; HSA-LABEL: define {{[^@]+}}@defined.func 434; HSA-SAME: () #[[ATTR17:[0-9]+]] { 435; HSA-NEXT: ret void 436; 437 ret void 438} 439 440define void @func_call_external() #3 { 441; HSA-LABEL: define {{[^@]+}}@func_call_external 442; HSA-SAME: () #[[ATTR17]] { 443; HSA-NEXT: call void @external.func() 444; HSA-NEXT: ret void 445; 446 call void @external.func() 447 ret void 448} 449 450define void @func_call_defined() #3 { 451; HSA-LABEL: define {{[^@]+}}@func_call_defined 452; HSA-SAME: () #[[ATTR17]] { 453; HSA-NEXT: call void @defined.func() 454; HSA-NEXT: ret void 455; 456 call void @defined.func() 457 ret void 458} 459 460define void @func_call_asm() #3 { 461; HSA-LABEL: define {{[^@]+}}@func_call_asm 462; HSA-SAME: () #[[ATTR18:[0-9]+]] { 463; HSA-NEXT: call void asm sideeffect "", ""() #[[ATTR18]] 464; HSA-NEXT: ret void 465; 466 call void asm sideeffect "", ""() #3 467 ret void 468} 469 470define amdgpu_kernel void @kern_call_external() #3 { 471; HSA-LABEL: define {{[^@]+}}@kern_call_external 472; HSA-SAME: () #[[ATTR19:[0-9]+]] { 473; HSA-NEXT: call void @external.func() 474; HSA-NEXT: ret void 475; 476 call void @external.func() 477 ret void 478} 479 480define amdgpu_kernel void @func_kern_defined() #3 { 481; HSA-LABEL: define {{[^@]+}}@func_kern_defined 482; HSA-SAME: () #[[ATTR19]] { 483; HSA-NEXT: call void @defined.func() 484; HSA-NEXT: ret void 485; 486 call void @defined.func() 487 ret void 488} 489 490define i32 @use_dispatch_ptr_ret_type() #1 { 491; HSA-LABEL: define {{[^@]+}}@use_dispatch_ptr_ret_type 492; HSA-SAME: () #[[ATTR20:[0-9]+]] { 493; HSA-NEXT: [[DISPATCH_PTR:%.*]] = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 494; HSA-NEXT: store volatile i8 addrspace(4)* [[DISPATCH_PTR]], i8 addrspace(4)* addrspace(1)* undef, align 8 495; HSA-NEXT: ret i32 0 496; 497 %dispatch.ptr = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 498 store volatile i8 addrspace(4)* %dispatch.ptr, i8 addrspace(4)* addrspace(1)* undef 499 ret i32 0 500} 501 502define float @func_indirect_use_dispatch_ptr_constexpr_cast_func() #1 { 503; HSA-LABEL: define {{[^@]+}}@func_indirect_use_dispatch_ptr_constexpr_cast_func 504; HSA-SAME: () #[[ATTR20]] { 505; HSA-NEXT: [[F:%.*]] = call float bitcast (i32 ()* @use_dispatch_ptr_ret_type to float ()*)() 506; HSA-NEXT: [[FADD:%.*]] = fadd float [[F]], 1.000000e+00 507; HSA-NEXT: ret float [[FADD]] 508; 509 %f = call float bitcast (i32()* @use_dispatch_ptr_ret_type to float()*)() 510 %fadd = fadd float %f, 1.0 511 ret float %fadd 512} 513 514attributes #0 = { nounwind readnone speculatable } 515attributes #1 = { nounwind "target-cpu"="fiji" } 516attributes #2 = { nounwind "target-cpu"="gfx900" } 517attributes #3 = { nounwind } 518 519;. 520; HSA: attributes #[[ATTR0:[0-9]+]] = { nounwind readnone speculatable willreturn } 521; HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-work-item-id-x" "target-cpu"="fiji" "uniform-work-group-size"="false" } 522; HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-work-item-id-y" "target-cpu"="fiji" "uniform-work-group-size"="false" } 523; HSA: attributes #[[ATTR3]] = { nounwind "amdgpu-work-item-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } 524; HSA: attributes #[[ATTR4]] = { nounwind "amdgpu-work-group-id-x" "target-cpu"="fiji" "uniform-work-group-size"="false" } 525; HSA: attributes #[[ATTR5]] = { nounwind "amdgpu-work-group-id-y" "target-cpu"="fiji" "uniform-work-group-size"="false" } 526; HSA: attributes #[[ATTR6]] = { nounwind "amdgpu-work-group-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } 527; HSA: attributes #[[ATTR7]] = { nounwind "amdgpu-dispatch-ptr" "target-cpu"="fiji" "uniform-work-group-size"="false" } 528; HSA: attributes #[[ATTR8]] = { nounwind "amdgpu-queue-ptr" "target-cpu"="fiji" "uniform-work-group-size"="false" } 529; HSA: attributes #[[ATTR9]] = { nounwind "amdgpu-dispatch-id" "target-cpu"="fiji" "uniform-work-group-size"="false" } 530; HSA: attributes #[[ATTR10]] = { nounwind "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" "target-cpu"="fiji" } 531; HSA: attributes #[[ATTR11]] = { nounwind "target-cpu"="fiji" "uniform-work-group-size"="false" } 532; HSA: attributes #[[ATTR12]] = { nounwind "target-cpu"="gfx900" "uniform-work-group-size"="false" } 533; HSA: attributes #[[ATTR13]] = { nounwind "amdgpu-queue-ptr" "target-cpu"="gfx900" "uniform-work-group-size"="false" } 534; HSA: attributes #[[ATTR14]] = { nounwind "amdgpu-kernarg-segment-ptr" "target-cpu"="fiji" "uniform-work-group-size"="false" } 535; HSA: attributes #[[ATTR15]] = { nounwind "amdgpu-implicitarg-ptr" "target-cpu"="fiji" } 536; HSA: attributes #[[ATTR16]] = { nounwind "amdgpu-implicitarg-ptr" "target-cpu"="fiji" "uniform-work-group-size"="false" } 537; HSA: attributes #[[ATTR17]] = { nounwind "uniform-work-group-size"="false" } 538; HSA: attributes #[[ATTR18]] = { nounwind } 539; HSA: attributes #[[ATTR19]] = { nounwind "amdgpu-calls" "uniform-work-group-size"="false" } 540; HSA: attributes #[[ATTR20]] = { nounwind "amdgpu-dispatch-id" "amdgpu-dispatch-ptr" "amdgpu-implicitarg-ptr" "amdgpu-queue-ptr" "amdgpu-work-group-id-x" "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" "amdgpu-work-item-id-x" "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" "target-cpu"="fiji" } 541;. 542