1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
3;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
4
5; ===================================================================================
6; V_AND_OR_B32
7; ===================================================================================
8
9define amdgpu_ps float @and_or(i32 %a, i32 %b, i32 %c) {
10; VI-LABEL: and_or:
11; VI:       ; %bb.0:
12; VI-NEXT:    v_and_b32_e32 v0, v0, v1
13; VI-NEXT:    v_or_b32_e32 v0, v0, v2
14; VI-NEXT:    ; return to shader part epilog
15;
16; GFX9-LABEL: and_or:
17; GFX9:       ; %bb.0:
18; GFX9-NEXT:    v_and_or_b32 v0, v0, v1, v2
19; GFX9-NEXT:    ; return to shader part epilog
20  %x = and i32 %a, %b
21  %result = or i32 %x, %c
22  %bc = bitcast i32 %result to float
23  ret float %bc
24}
25
26; ThreeOp instruction variant not used due to Constant Bus Limitations
27define amdgpu_ps float @and_or_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {
28; VI-LABEL: and_or_vgpr_b:
29; VI:       ; %bb.0:
30; VI-NEXT:    v_and_b32_e32 v0, s2, v0
31; VI-NEXT:    v_or_b32_e32 v0, s3, v0
32; VI-NEXT:    ; return to shader part epilog
33;
34; GFX9-LABEL: and_or_vgpr_b:
35; GFX9:       ; %bb.0:
36; GFX9-NEXT:    v_and_b32_e32 v0, s2, v0
37; GFX9-NEXT:    v_or_b32_e32 v0, s3, v0
38; GFX9-NEXT:    ; return to shader part epilog
39  %x = and i32 %a, %b
40  %result = or i32 %x, %c
41  %bc = bitcast i32 %result to float
42  ret float %bc
43}
44
45define amdgpu_ps float @and_or_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) {
46; VI-LABEL: and_or_vgpr_ab:
47; VI:       ; %bb.0:
48; VI-NEXT:    v_and_b32_e32 v0, v0, v1
49; VI-NEXT:    v_or_b32_e32 v0, s2, v0
50; VI-NEXT:    ; return to shader part epilog
51;
52; GFX9-LABEL: and_or_vgpr_ab:
53; GFX9:       ; %bb.0:
54; GFX9-NEXT:    v_and_or_b32 v0, v0, v1, s2
55; GFX9-NEXT:    ; return to shader part epilog
56  %x = and i32 %a, %b
57  %result = or i32 %x, %c
58  %bc = bitcast i32 %result to float
59  ret float %bc
60}
61
62define amdgpu_ps float @and_or_vgpr_const(i32 %a, i32 %b) {
63; VI-LABEL: and_or_vgpr_const:
64; VI:       ; %bb.0:
65; VI-NEXT:    v_and_b32_e32 v0, 4, v0
66; VI-NEXT:    v_or_b32_e32 v0, v0, v1
67; VI-NEXT:    ; return to shader part epilog
68;
69; GFX9-LABEL: and_or_vgpr_const:
70; GFX9:       ; %bb.0:
71; GFX9-NEXT:    v_and_or_b32 v0, v0, 4, v1
72; GFX9-NEXT:    ; return to shader part epilog
73  %x = and i32 4, %a
74  %result = or i32 %x, %b
75  %bc = bitcast i32 %result to float
76  ret float %bc
77}
78
79define amdgpu_ps float @and_or_vgpr_const_inline_const(i32 %a) {
80; VI-LABEL: and_or_vgpr_const_inline_const:
81; VI:       ; %bb.0:
82; VI-NEXT:    v_and_b32_e32 v0, 20, v0
83; VI-NEXT:    v_or_b32_e32 v0, 0x808, v0
84; VI-NEXT:    ; return to shader part epilog
85;
86; GFX9-LABEL: and_or_vgpr_const_inline_const:
87; GFX9:       ; %bb.0:
88; GFX9-NEXT:    v_mov_b32_e32 v1, 0x808
89; GFX9-NEXT:    v_and_or_b32 v0, v0, 20, v1
90; GFX9-NEXT:    ; return to shader part epilog
91  %x = and i32 20, %a
92  %result = or i32 %x, 2056
93  %bc = bitcast i32 %result to float
94  ret float %bc
95}
96
97define amdgpu_ps float @and_or_vgpr_inline_const_x2(i32 %a) {
98; VI-LABEL: and_or_vgpr_inline_const_x2:
99; VI:       ; %bb.0:
100; VI-NEXT:    v_and_b32_e32 v0, 4, v0
101; VI-NEXT:    v_or_b32_e32 v0, 1, v0
102; VI-NEXT:    ; return to shader part epilog
103;
104; GFX9-LABEL: and_or_vgpr_inline_const_x2:
105; GFX9:       ; %bb.0:
106; GFX9-NEXT:    v_and_or_b32 v0, v0, 4, 1
107; GFX9-NEXT:    ; return to shader part epilog
108  %x = and i32 4, %a
109  %result = or i32 %x, 1
110  %bc = bitcast i32 %result to float
111  ret float %bc
112}
113