1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
3;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
4;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
5
6; ===================================================================================
7; V_AND_OR_B32
8; ===================================================================================
9
10define amdgpu_ps float @and_or(i32 %a, i32 %b, i32 %c) {
11; VI-LABEL: and_or:
12; VI:       ; %bb.0:
13; VI-NEXT:    v_and_b32_e32 v0, v0, v1
14; VI-NEXT:    v_or_b32_e32 v0, v0, v2
15; VI-NEXT:    ; return to shader part epilog
16;
17; GFX9-LABEL: and_or:
18; GFX9:       ; %bb.0:
19; GFX9-NEXT:    v_and_or_b32 v0, v0, v1, v2
20; GFX9-NEXT:    ; return to shader part epilog
21;
22; GFX10-LABEL: and_or:
23; GFX10:       ; %bb.0:
24; GFX10-NEXT:    v_and_or_b32 v0, v0, v1, v2
25; GFX10-NEXT:    ; return to shader part epilog
26  %x = and i32 %a, %b
27  %result = or i32 %x, %c
28  %bc = bitcast i32 %result to float
29  ret float %bc
30}
31
32; ThreeOp instruction variant not used due to Constant Bus Limitations
33define amdgpu_ps float @and_or_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {
34; VI-LABEL: and_or_vgpr_b:
35; VI:       ; %bb.0:
36; VI-NEXT:    v_and_b32_e32 v0, s2, v0
37; VI-NEXT:    v_or_b32_e32 v0, s3, v0
38; VI-NEXT:    ; return to shader part epilog
39;
40; GFX9-LABEL: and_or_vgpr_b:
41; GFX9:       ; %bb.0:
42; GFX9-NEXT:    v_and_b32_e32 v0, s2, v0
43; GFX9-NEXT:    v_or_b32_e32 v0, s3, v0
44; GFX9-NEXT:    ; return to shader part epilog
45;
46; GFX10-LABEL: and_or_vgpr_b:
47; GFX10:       ; %bb.0:
48; GFX10-NEXT:    v_and_or_b32 v0, s2, v0, s3
49; GFX10-NEXT:    ; return to shader part epilog
50  %x = and i32 %a, %b
51  %result = or i32 %x, %c
52  %bc = bitcast i32 %result to float
53  ret float %bc
54}
55
56define amdgpu_ps float @and_or_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) {
57; VI-LABEL: and_or_vgpr_ab:
58; VI:       ; %bb.0:
59; VI-NEXT:    v_and_b32_e32 v0, v0, v1
60; VI-NEXT:    v_or_b32_e32 v0, s2, v0
61; VI-NEXT:    ; return to shader part epilog
62;
63; GFX9-LABEL: and_or_vgpr_ab:
64; GFX9:       ; %bb.0:
65; GFX9-NEXT:    v_and_or_b32 v0, v0, v1, s2
66; GFX9-NEXT:    ; return to shader part epilog
67;
68; GFX10-LABEL: and_or_vgpr_ab:
69; GFX10:       ; %bb.0:
70; GFX10-NEXT:    v_and_or_b32 v0, v0, v1, s2
71; GFX10-NEXT:    ; return to shader part epilog
72  %x = and i32 %a, %b
73  %result = or i32 %x, %c
74  %bc = bitcast i32 %result to float
75  ret float %bc
76}
77
78define amdgpu_ps float @and_or_vgpr_const(i32 %a, i32 %b) {
79; VI-LABEL: and_or_vgpr_const:
80; VI:       ; %bb.0:
81; VI-NEXT:    v_and_b32_e32 v0, 4, v0
82; VI-NEXT:    v_or_b32_e32 v0, v0, v1
83; VI-NEXT:    ; return to shader part epilog
84;
85; GFX9-LABEL: and_or_vgpr_const:
86; GFX9:       ; %bb.0:
87; GFX9-NEXT:    v_and_or_b32 v0, v0, 4, v1
88; GFX9-NEXT:    ; return to shader part epilog
89;
90; GFX10-LABEL: and_or_vgpr_const:
91; GFX10:       ; %bb.0:
92; GFX10-NEXT:    v_and_or_b32 v0, v0, 4, v1
93; GFX10-NEXT:    ; return to shader part epilog
94  %x = and i32 4, %a
95  %result = or i32 %x, %b
96  %bc = bitcast i32 %result to float
97  ret float %bc
98}
99
100define amdgpu_ps float @and_or_vgpr_const_inline_const(i32 %a) {
101; VI-LABEL: and_or_vgpr_const_inline_const:
102; VI:       ; %bb.0:
103; VI-NEXT:    v_and_b32_e32 v0, 20, v0
104; VI-NEXT:    v_or_b32_e32 v0, 0x808, v0
105; VI-NEXT:    ; return to shader part epilog
106;
107; GFX9-LABEL: and_or_vgpr_const_inline_const:
108; GFX9:       ; %bb.0:
109; GFX9-NEXT:    v_mov_b32_e32 v1, 0x808
110; GFX9-NEXT:    v_and_or_b32 v0, v0, 20, v1
111; GFX9-NEXT:    ; return to shader part epilog
112;
113; GFX10-LABEL: and_or_vgpr_const_inline_const:
114; GFX10:       ; %bb.0:
115; GFX10-NEXT:    v_and_or_b32 v0, v0, 20, 0x808
116; GFX10-NEXT:    ; return to shader part epilog
117  %x = and i32 20, %a
118  %result = or i32 %x, 2056
119  %bc = bitcast i32 %result to float
120  ret float %bc
121}
122
123define amdgpu_ps float @and_or_vgpr_inline_const_x2(i32 %a) {
124; VI-LABEL: and_or_vgpr_inline_const_x2:
125; VI:       ; %bb.0:
126; VI-NEXT:    v_and_b32_e32 v0, 4, v0
127; VI-NEXT:    v_or_b32_e32 v0, 1, v0
128; VI-NEXT:    ; return to shader part epilog
129;
130; GFX9-LABEL: and_or_vgpr_inline_const_x2:
131; GFX9:       ; %bb.0:
132; GFX9-NEXT:    v_and_or_b32 v0, v0, 4, 1
133; GFX9-NEXT:    ; return to shader part epilog
134;
135; GFX10-LABEL: and_or_vgpr_inline_const_x2:
136; GFX10:       ; %bb.0:
137; GFX10-NEXT:    v_and_or_b32 v0, v0, 4, 1
138; GFX10-NEXT:    ; return to shader part epilog
139  %x = and i32 4, %a
140  %result = or i32 %x, 1
141  %bc = bitcast i32 %result to float
142  ret float %bc
143}
144