1; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=FUNC %s 2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=FUNC %s 3; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s 4 5declare i32 @llvm.r600.read.tidig.x() #0 6 7; FUNC-LABEL: {{^}}test2: 8; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 9; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 10 11; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}} 12; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}} 13 14define amdgpu_kernel void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { 15 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1 16 %a = load <2 x i32>, <2 x i32> addrspace(1) * %in 17 %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr 18 %result = and <2 x i32> %a, %b 19 store <2 x i32> %result, <2 x i32> addrspace(1)* %out 20 ret void 21} 22 23; FUNC-LABEL: {{^}}test4: 24; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 25; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 26; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 27; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 28 29 30; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}} 31; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}} 32; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}} 33; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}} 34 35define amdgpu_kernel void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { 36 %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1 37 %a = load <4 x i32>, <4 x i32> addrspace(1) * %in 38 %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr 39 %result = and <4 x i32> %a, %b 40 store <4 x i32> %result, <4 x i32> addrspace(1)* %out 41 ret void 42} 43 44; FUNC-LABEL: {{^}}s_and_i32: 45; SI: s_and_b32 46define amdgpu_kernel void @s_and_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) { 47 %and = and i32 %a, %b 48 store i32 %and, i32 addrspace(1)* %out, align 4 49 ret void 50} 51 52; FUNC-LABEL: {{^}}s_and_constant_i32: 53; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x12d687 54define amdgpu_kernel void @s_and_constant_i32(i32 addrspace(1)* %out, i32 %a) { 55 %and = and i32 %a, 1234567 56 store i32 %and, i32 addrspace(1)* %out, align 4 57 ret void 58} 59 60; FIXME: We should really duplicate the constant so that the SALU use 61; can fold into the s_and_b32 and the VALU one is materialized 62; directly without copying from the SGPR. 63 64; Second use is a VGPR use of the constant. 65; FUNC-LABEL: {{^}}s_and_multi_use_constant_i32_0: 66; SI: s_mov_b32 [[K:s[0-9]+]], 0x12d687 67; SI-DAG: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, [[K]] 68; SI-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], [[K]] 69; SI: buffer_store_dword [[VK]] 70define amdgpu_kernel void @s_and_multi_use_constant_i32_0(i32 addrspace(1)* %out, i32 %a, i32 %b) { 71 %and = and i32 %a, 1234567 72 73 ; Just to stop future replacement of copy to vgpr + store with VALU op. 74 %foo = add i32 %and, %b 75 store volatile i32 %foo, i32 addrspace(1)* %out 76 store volatile i32 1234567, i32 addrspace(1)* %out 77 ret void 78} 79 80; Second use is another SGPR use of the constant. 81; FUNC-LABEL: {{^}}s_and_multi_use_constant_i32_1: 82; SI: s_mov_b32 [[K:s[0-9]+]], 0x12d687 83; SI: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, [[K]] 84; SI: s_add_i32 85; SI: s_add_i32 [[ADD:s[0-9]+]], s{{[0-9]+}}, [[K]] 86; SI: v_mov_b32_e32 [[VADD:v[0-9]+]], [[ADD]] 87; SI: buffer_store_dword [[VADD]] 88define amdgpu_kernel void @s_and_multi_use_constant_i32_1(i32 addrspace(1)* %out, i32 %a, i32 %b) { 89 %and = and i32 %a, 1234567 90 %foo = add i32 %and, 1234567 91 %bar = add i32 %foo, %b 92 store volatile i32 %bar, i32 addrspace(1)* %out 93 ret void 94} 95 96; FUNC-LABEL: {{^}}v_and_i32_vgpr_vgpr: 97; SI: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 98define amdgpu_kernel void @v_and_i32_vgpr_vgpr(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) { 99 %tid = call i32 @llvm.r600.read.tidig.x() #0 100 %gep.a = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid 101 %gep.b = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid 102 %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid 103 %a = load i32, i32 addrspace(1)* %gep.a 104 %b = load i32, i32 addrspace(1)* %gep.b 105 %and = and i32 %a, %b 106 store i32 %and, i32 addrspace(1)* %gep.out 107 ret void 108} 109 110; FUNC-LABEL: {{^}}v_and_i32_sgpr_vgpr: 111; SI-DAG: s_load_dword [[SA:s[0-9]+]] 112; SI-DAG: {{buffer|flat}}_load_dword [[VB:v[0-9]+]] 113; SI: v_and_b32_e32 v{{[0-9]+}}, [[SA]], [[VB]] 114define amdgpu_kernel void @v_and_i32_sgpr_vgpr(i32 addrspace(1)* %out, i32 %a, i32 addrspace(1)* %bptr) { 115 %tid = call i32 @llvm.r600.read.tidig.x() #0 116 %gep.b = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid 117 %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid 118 %b = load i32, i32 addrspace(1)* %gep.b 119 %and = and i32 %a, %b 120 store i32 %and, i32 addrspace(1)* %gep.out 121 ret void 122} 123 124; FUNC-LABEL: {{^}}v_and_i32_vgpr_sgpr: 125; SI-DAG: s_load_dword [[SA:s[0-9]+]] 126; SI-DAG: {{buffer|flat}}_load_dword [[VB:v[0-9]+]] 127; SI: v_and_b32_e32 v{{[0-9]+}}, [[SA]], [[VB]] 128define amdgpu_kernel void @v_and_i32_vgpr_sgpr(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 %b) { 129 %tid = call i32 @llvm.r600.read.tidig.x() #0 130 %gep.a = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid 131 %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid 132 %a = load i32, i32 addrspace(1)* %gep.a 133 %and = and i32 %a, %b 134 store i32 %and, i32 addrspace(1)* %gep.out 135 ret void 136} 137 138; FUNC-LABEL: {{^}}v_and_constant_i32 139; SI: v_and_b32_e32 v{{[0-9]+}}, 0x12d687, v{{[0-9]+}} 140define amdgpu_kernel void @v_and_constant_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) { 141 %tid = call i32 @llvm.r600.read.tidig.x() #0 142 %gep = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid 143 %a = load i32, i32 addrspace(1)* %gep, align 4 144 %and = and i32 %a, 1234567 145 store i32 %and, i32 addrspace(1)* %out, align 4 146 ret void 147} 148 149; FUNC-LABEL: {{^}}v_and_inline_imm_64_i32 150; SI: v_and_b32_e32 v{{[0-9]+}}, 64, v{{[0-9]+}} 151define amdgpu_kernel void @v_and_inline_imm_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) { 152 %tid = call i32 @llvm.r600.read.tidig.x() #0 153 %gep = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid 154 %a = load i32, i32 addrspace(1)* %gep, align 4 155 %and = and i32 %a, 64 156 store i32 %and, i32 addrspace(1)* %out, align 4 157 ret void 158} 159 160; FUNC-LABEL: {{^}}v_and_inline_imm_neg_16_i32 161; SI: v_and_b32_e32 v{{[0-9]+}}, -16, v{{[0-9]+}} 162define amdgpu_kernel void @v_and_inline_imm_neg_16_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) { 163 %tid = call i32 @llvm.r600.read.tidig.x() #0 164 %gep = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid 165 %a = load i32, i32 addrspace(1)* %gep, align 4 166 %and = and i32 %a, -16 167 store i32 %and, i32 addrspace(1)* %out, align 4 168 ret void 169} 170 171; FUNC-LABEL: {{^}}s_and_i64 172; SI: s_and_b64 173define amdgpu_kernel void @s_and_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { 174 %and = and i64 %a, %b 175 store i64 %and, i64 addrspace(1)* %out, align 8 176 ret void 177} 178 179; FIXME: Should use SGPRs 180; FUNC-LABEL: {{^}}s_and_i1: 181; SI: v_and_b32 182define amdgpu_kernel void @s_and_i1(i1 addrspace(1)* %out, i1 %a, i1 %b) { 183 %and = and i1 %a, %b 184 store i1 %and, i1 addrspace(1)* %out 185 ret void 186} 187 188; FUNC-LABEL: {{^}}s_and_constant_i64: 189; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000{{$}} 190; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80{{$}} 191; SI: buffer_store_dwordx2 192define amdgpu_kernel void @s_and_constant_i64(i64 addrspace(1)* %out, i64 %a) { 193 %and = and i64 %a, 549756338176 194 store i64 %and, i64 addrspace(1)* %out, align 8 195 ret void 196} 197 198; FUNC-LABEL: {{^}}s_and_multi_use_constant_i64: 199; XSI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0x80000{{$}} 200; XSI-DAG: s_mov_b32 s[[KHI:[0-9]+]], 0x80{{$}} 201; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}} 202define amdgpu_kernel void @s_and_multi_use_constant_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { 203 %and0 = and i64 %a, 549756338176 204 %and1 = and i64 %b, 549756338176 205 store volatile i64 %and0, i64 addrspace(1)* %out 206 store volatile i64 %and1, i64 addrspace(1)* %out 207 ret void 208} 209 210; FUNC-LABEL: {{^}}s_and_32_bit_constant_i64: 211; SI: s_load_dwordx2 212; SI-NOT: and 213; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x12d687{{$}} 214; SI-NOT: and 215; SI: buffer_store_dwordx2 216define amdgpu_kernel void @s_and_32_bit_constant_i64(i64 addrspace(1)* %out, i64 %a) { 217 %and = and i64 %a, 1234567 218 store i64 %and, i64 addrspace(1)* %out, align 8 219 ret void 220} 221 222; FUNC-LABEL: {{^}}s_and_multi_use_inline_imm_i64: 223; SI: s_load_dwordx2 224; SI: s_load_dword [[A:s[0-9]+]] 225; SI: s_load_dword [[B:s[0-9]+]] 226; SI: s_load_dwordx2 227; SI-NOT: and 228; SI: s_lshl_b32 [[A]], [[A]], 1 229; SI: s_lshl_b32 [[B]], [[B]], 1 230; SI: s_and_b32 s{{[0-9]+}}, [[A]], 62 231; SI: s_and_b32 s{{[0-9]+}}, [[B]], 62 232; SI-NOT: and 233; SI: buffer_store_dwordx2 234define amdgpu_kernel void @s_and_multi_use_inline_imm_i64(i64 addrspace(1)* %out, i64 %a, i64 %b, i64 %c) { 235 %shl.a = shl i64 %a, 1 236 %shl.b = shl i64 %b, 1 237 %and0 = and i64 %shl.a, 62 238 %and1 = and i64 %shl.b, 62 239 %add0 = add i64 %and0, %c 240 %add1 = add i64 %and1, %c 241 store volatile i64 %add0, i64 addrspace(1)* %out 242 store volatile i64 %add1, i64 addrspace(1)* %out 243 ret void 244} 245 246; FUNC-LABEL: {{^}}v_and_i64: 247; SI: v_and_b32 248; SI: v_and_b32 249define amdgpu_kernel void @v_and_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) { 250 %tid = call i32 @llvm.r600.read.tidig.x() #0 251 %gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid 252 %a = load i64, i64 addrspace(1)* %gep.a, align 8 253 %gep.b = getelementptr i64, i64 addrspace(1)* %bptr, i32 %tid 254 %b = load i64, i64 addrspace(1)* %gep.b, align 8 255 %and = and i64 %a, %b 256 store i64 %and, i64 addrspace(1)* %out, align 8 257 ret void 258} 259 260; FUNC-LABEL: {{^}}v_and_constant_i64: 261; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, 0xab19b207, {{v[0-9]+}} 262; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, 0x11e, {{v[0-9]+}} 263; SI: buffer_store_dwordx2 264define amdgpu_kernel void @v_and_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 265 %tid = call i32 @llvm.r600.read.tidig.x() #0 266 %gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid 267 %a = load i64, i64 addrspace(1)* %gep.a, align 8 268 %and = and i64 %a, 1231231234567 269 store i64 %and, i64 addrspace(1)* %out, align 8 270 ret void 271} 272 273; FUNC-LABEL: {{^}}v_and_multi_use_constant_i64: 274; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO0:[0-9]+]]:[[HI0:[0-9]+]]{{\]}} 275; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO1:[0-9]+]]:[[HI1:[0-9]+]]{{\]}} 276; SI-DAG: s_movk_i32 [[KHI:s[0-9]+]], 0x11e{{$}} 277; SI-DAG: s_mov_b32 [[KLO:s[0-9]+]], 0xab19b207{{$}} 278; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], v[[LO0]] 279; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], v[[HI0]] 280; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], v[[LO1]] 281; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], v[[HI1]] 282; SI: buffer_store_dwordx2 283; SI: buffer_store_dwordx2 284define amdgpu_kernel void @v_and_multi_use_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 285 %a = load volatile i64, i64 addrspace(1)* %aptr 286 %b = load volatile i64, i64 addrspace(1)* %aptr 287 %and0 = and i64 %a, 1231231234567 288 %and1 = and i64 %b, 1231231234567 289 store volatile i64 %and0, i64 addrspace(1)* %out 290 store volatile i64 %and1, i64 addrspace(1)* %out 291 ret void 292} 293 294; FUNC-LABEL: {{^}}v_and_multi_use_inline_imm_i64: 295; SI: buffer_load_dwordx2 v{{\[}}[[LO0:[0-9]+]]:[[HI0:[0-9]+]]{{\]}} 296; SI-NOT: and 297; SI: buffer_load_dwordx2 v{{\[}}[[LO1:[0-9]+]]:[[HI1:[0-9]+]]{{\]}} 298; SI-NOT: and 299; SI: v_and_b32_e32 v[[RESLO0:[0-9]+]], 63, v[[LO0]] 300; SI: v_and_b32_e32 v[[RESLO1:[0-9]+]], 63, v[[LO1]] 301; SI-NOT: and 302; SI: buffer_store_dwordx2 v{{\[}}[[RESLO0]] 303; SI: buffer_store_dwordx2 v{{\[}}[[RESLO1]] 304define amdgpu_kernel void @v_and_multi_use_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 305 %a = load volatile i64, i64 addrspace(1)* %aptr 306 %b = load volatile i64, i64 addrspace(1)* %aptr 307 %and0 = and i64 %a, 63 308 %and1 = and i64 %b, 63 309 store volatile i64 %and0, i64 addrspace(1)* %out 310 store volatile i64 %and1, i64 addrspace(1)* %out 311 ret void 312} 313 314; FUNC-LABEL: {{^}}v_and_i64_32_bit_constant: 315; SI: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]] 316; SI-NOT: and 317; SI: v_and_b32_e32 {{v[0-9]+}}, 0x12d687, [[VAL]] 318; SI-NOT: and 319; SI: buffer_store_dwordx2 320define amdgpu_kernel void @v_and_i64_32_bit_constant(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 321 %tid = call i32 @llvm.r600.read.tidig.x() #0 322 %gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid 323 %a = load i64, i64 addrspace(1)* %gep.a, align 8 324 %and = and i64 %a, 1234567 325 store i64 %and, i64 addrspace(1)* %out, align 8 326 ret void 327} 328 329; FUNC-LABEL: {{^}}v_and_inline_imm_i64: 330; SI: {{buffer|flat}}_load_dword v{{[0-9]+}} 331; SI-NOT: and 332; SI: v_and_b32_e32 {{v[0-9]+}}, 64, {{v[0-9]+}} 333; SI-NOT: and 334; SI: buffer_store_dwordx2 335define amdgpu_kernel void @v_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 336 %tid = call i32 @llvm.r600.read.tidig.x() #0 337 %gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid 338 %a = load i64, i64 addrspace(1)* %gep.a, align 8 339 %and = and i64 %a, 64 340 store i64 %and, i64 addrspace(1)* %out, align 8 341 ret void 342} 343 344; FIXME: Should be able to reduce load width 345; FUNC-LABEL: {{^}}v_and_inline_neg_imm_i64: 346; SI: {{buffer|flat}}_load_dwordx2 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} 347; SI-NOT: and 348; SI: v_and_b32_e32 v[[VAL_LO]], -8, v[[VAL_LO]] 349; SI-NOT: and 350; SI: buffer_store_dwordx2 v{{\[}}[[VAL_LO]]:[[VAL_HI]]{{\]}} 351define amdgpu_kernel void @v_and_inline_neg_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 352 %tid = call i32 @llvm.r600.read.tidig.x() #0 353 %gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid 354 %a = load i64, i64 addrspace(1)* %gep.a, align 8 355 %and = and i64 %a, -8 356 store i64 %and, i64 addrspace(1)* %out, align 8 357 ret void 358} 359 360; FUNC-LABEL: {{^}}s_and_inline_imm_64_i64 361; SI: s_load_dword 362; SI-NOT: and 363; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 64 364; SI-NOT: and 365; SI: buffer_store_dword 366define amdgpu_kernel void @s_and_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 367 %and = and i64 %a, 64 368 store i64 %and, i64 addrspace(1)* %out, align 8 369 ret void 370} 371 372; FUNC-LABEL: {{^}}s_and_inline_imm_64_i64_noshrink: 373; SI: s_load_dword [[A:s[0-9]+]] 374; SI: s_lshl_b32 [[A]], [[A]], 1{{$}} 375; SI-NOT: and 376; SI: s_and_b32 s{{[0-9]+}}, [[A]], 64 377; SI-NOT: and 378; SI: s_add_u32 379; SI-NEXT: s_addc_u32 380define amdgpu_kernel void @s_and_inline_imm_64_i64_noshrink(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a, i64 %b) { 381 %shl = shl i64 %a, 1 382 %and = and i64 %shl, 64 383 %add = add i64 %and, %b 384 store i64 %add, i64 addrspace(1)* %out, align 8 385 ret void 386} 387 388; FUNC-LABEL: {{^}}s_and_inline_imm_1_i64 389; SI: s_load_dwordx2 390; SI-NOT: and 391; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1 392; SI-NOT: and 393; SI: buffer_store_dwordx2 394define amdgpu_kernel void @s_and_inline_imm_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 395 %and = and i64 %a, 1 396 store i64 %and, i64 addrspace(1)* %out, align 8 397 ret void 398} 399 400; FUNC-LABEL: {{^}}s_and_inline_imm_1.0_i64 401; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1.0 402 403; SI: s_load_dwordx2 404; SI: s_load_dwordx2 405; SI-NOT: and 406; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x3ff00000 407; SI-NOT: and 408; SI: buffer_store_dwordx2 409define amdgpu_kernel void @s_and_inline_imm_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 410 %and = and i64 %a, 4607182418800017408 411 store i64 %and, i64 addrspace(1)* %out, align 8 412 ret void 413} 414 415; FUNC-LABEL: {{^}}s_and_inline_imm_neg_1.0_i64 416; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -1.0 417 418; SI: s_load_dwordx2 419; SI: s_load_dwordx2 420; SI-NOT: and 421; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xbff00000 422; SI-NOT: and 423; SI: buffer_store_dwordx2 424define amdgpu_kernel void @s_and_inline_imm_neg_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 425 %and = and i64 %a, 13830554455654793216 426 store i64 %and, i64 addrspace(1)* %out, align 8 427 ret void 428} 429 430; FUNC-LABEL: {{^}}s_and_inline_imm_0.5_i64 431; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0.5 432 433; SI: s_load_dwordx2 434; SI: s_load_dwordx2 435; SI-NOT: and 436; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x3fe00000 437; SI-NOT: and 438; SI: buffer_store_dwordx2 439define amdgpu_kernel void @s_and_inline_imm_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 440 %and = and i64 %a, 4602678819172646912 441 store i64 %and, i64 addrspace(1)* %out, align 8 442 ret void 443} 444 445; FUNC-LABEL: {{^}}s_and_inline_imm_neg_0.5_i64: 446; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -0.5 447 448; SI: s_load_dwordx2 449; SI: s_load_dwordx2 450; SI-NOT: and 451; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xbfe00000 452; SI-NOT: and 453; SI: buffer_store_dwordx2 454define amdgpu_kernel void @s_and_inline_imm_neg_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 455 %and = and i64 %a, 13826050856027422720 456 store i64 %and, i64 addrspace(1)* %out, align 8 457 ret void 458} 459 460; FUNC-LABEL: {{^}}s_and_inline_imm_2.0_i64: 461; SI: s_load_dwordx2 462; SI: s_load_dwordx2 463; SI-NOT: and 464; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 2.0 465; SI-NOT: and 466; SI: buffer_store_dwordx2 467define amdgpu_kernel void @s_and_inline_imm_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 468 %and = and i64 %a, 4611686018427387904 469 store i64 %and, i64 addrspace(1)* %out, align 8 470 ret void 471} 472 473; FUNC-LABEL: {{^}}s_and_inline_imm_neg_2.0_i64: 474; SI: s_load_dwordx2 475; SI: s_load_dwordx2 476; SI-NOT: and 477; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, -2.0 478; SI-NOT: and 479; SI: buffer_store_dwordx2 480define amdgpu_kernel void @s_and_inline_imm_neg_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 481 %and = and i64 %a, 13835058055282163712 482 store i64 %and, i64 addrspace(1)* %out, align 8 483 ret void 484} 485 486; FUNC-LABEL: {{^}}s_and_inline_imm_4.0_i64: 487; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 4.0 488 489; SI: s_load_dwordx2 490; SI: s_load_dwordx2 491; SI-NOT: and 492; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x40100000 493; SI-NOT: and 494; SI: buffer_store_dwordx2 495define amdgpu_kernel void @s_and_inline_imm_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 496 %and = and i64 %a, 4616189618054758400 497 store i64 %and, i64 addrspace(1)* %out, align 8 498 ret void 499} 500 501; FUNC-LABEL: {{^}}s_and_inline_imm_neg_4.0_i64: 502; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -4.0 503 504; SI: s_load_dwordx2 505; SI: s_load_dwordx2 506; SI-NOT: and 507; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xc0100000 508; SI-NOT: and 509; SI: buffer_store_dwordx2 510define amdgpu_kernel void @s_and_inline_imm_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 511 %and = and i64 %a, 13839561654909534208 512 store i64 %and, i64 addrspace(1)* %out, align 8 513 ret void 514} 515 516 517; Test with the 64-bit integer bitpattern for a 32-bit float in the 518; low 32-bits, which is not a valid 64-bit inline immmediate. 519 520; FUNC-LABEL: {{^}}s_and_inline_imm_f32_4.0_i64: 521; SI: s_load_dwordx2 522; SI: s_load_dword s 523; SI-NOT: and 524; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, 4.0 525; SI-NOT: and 526; SI: buffer_store_dwordx2 527define amdgpu_kernel void @s_and_inline_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 528 %and = and i64 %a, 1082130432 529 store i64 %and, i64 addrspace(1)* %out, align 8 530 ret void 531} 532 533; FUNC-LABEL: {{^}}s_and_inline_imm_f32_neg_4.0_i64: 534; SI: s_load_dwordx2 535; SI: s_load_dwordx2 536; SI-NOT: and 537; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, -4.0 538; SI-NOT: and 539; SI: buffer_store_dwordx2 540define amdgpu_kernel void @s_and_inline_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 541 %and = and i64 %a, -1065353216 542 store i64 %and, i64 addrspace(1)* %out, align 8 543 ret void 544} 545 546; Shift into upper 32-bits 547; SI: s_load_dwordx2 548; SI: s_load_dwordx2 549; SI-NOT: and 550; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, 4.0 551; SI-NOT: and 552; SI: buffer_store_dwordx2 553define amdgpu_kernel void @s_and_inline_high_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 554 %and = and i64 %a, 4647714815446351872 555 store i64 %and, i64 addrspace(1)* %out, align 8 556 ret void 557} 558 559; FUNC-LABEL: {{^}}s_and_inline_high_imm_f32_neg_4.0_i64: 560; SI: s_load_dwordx2 561; SI: s_load_dwordx2 562; SI-NOT: and 563; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, -4.0 564; SI-NOT: and 565; SI: buffer_store_dwordx2 566define amdgpu_kernel void @s_and_inline_high_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 567 %and = and i64 %a, 13871086852301127680 568 store i64 %and, i64 addrspace(1)* %out, align 8 569 ret void 570} 571attributes #0 = { nounwind readnone } 572