1; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s 2; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 3; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 4 5declare i32 @llvm.r600.read.tidig.x() #0 6 7; FUNC-LABEL: {{^}}test2: 8; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 9; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 10 11; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 12; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 13 14define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { 15 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1 16 %a = load <2 x i32>, <2 x i32> addrspace(1) * %in 17 %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr 18 %result = and <2 x i32> %a, %b 19 store <2 x i32> %result, <2 x i32> addrspace(1)* %out 20 ret void 21} 22 23; FUNC-LABEL: {{^}}test4: 24; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 25; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 26; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 27; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 28 29; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 30; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 31; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 32; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 33 34define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { 35 %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1 36 %a = load <4 x i32>, <4 x i32> addrspace(1) * %in 37 %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr 38 %result = and <4 x i32> %a, %b 39 store <4 x i32> %result, <4 x i32> addrspace(1)* %out 40 ret void 41} 42 43; FUNC-LABEL: {{^}}s_and_i32: 44; SI: s_and_b32 45define void @s_and_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) { 46 %and = and i32 %a, %b 47 store i32 %and, i32 addrspace(1)* %out, align 4 48 ret void 49} 50 51; FUNC-LABEL: {{^}}s_and_constant_i32: 52; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x12d687 53define void @s_and_constant_i32(i32 addrspace(1)* %out, i32 %a) { 54 %and = and i32 %a, 1234567 55 store i32 %and, i32 addrspace(1)* %out, align 4 56 ret void 57} 58 59; FIXME: We should really duplicate the constant so that the SALU use 60; can fold into the s_and_b32 and the VALU one is materialized 61; directly without copying from the SGPR. 62 63; Second use is a VGPR use of the constant. 64; FUNC-LABEL: {{^}}s_and_multi_use_constant_i32_0: 65; SI: s_mov_b32 [[K:s[0-9]+]], 0x12d687 66; SI-DAG: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, [[K]] 67; SI-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], [[K]] 68; SI: buffer_store_dword [[VK]] 69define void @s_and_multi_use_constant_i32_0(i32 addrspace(1)* %out, i32 %a, i32 %b) { 70 %and = and i32 %a, 1234567 71 72 ; Just to stop future replacement of copy to vgpr + store with VALU op. 73 %foo = add i32 %and, %b 74 store volatile i32 %foo, i32 addrspace(1)* %out 75 store volatile i32 1234567, i32 addrspace(1)* %out 76 ret void 77} 78 79; Second use is another SGPR use of the constant. 80; FUNC-LABEL: {{^}}s_and_multi_use_constant_i32_1: 81; SI: s_mov_b32 [[K:s[0-9]+]], 0x12d687 82; SI: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, [[K]] 83; SI: s_add_i32 84; SI: s_add_i32 [[ADD:s[0-9]+]], s{{[0-9]+}}, [[K]] 85; SI: buffer_store_dword [[VK]] 86define void @s_and_multi_use_constant_i32_1(i32 addrspace(1)* %out, i32 %a, i32 %b) { 87 %and = and i32 %a, 1234567 88 %foo = add i32 %and, 1234567 89 %bar = add i32 %foo, %b 90 store volatile i32 %bar, i32 addrspace(1)* %out 91 ret void 92} 93 94; FUNC-LABEL: {{^}}v_and_i32_vgpr_vgpr: 95; SI: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 96define void @v_and_i32_vgpr_vgpr(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) { 97 %tid = call i32 @llvm.r600.read.tidig.x() #0 98 %gep.a = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid 99 %gep.b = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid 100 %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid 101 %a = load i32, i32 addrspace(1)* %gep.a 102 %b = load i32, i32 addrspace(1)* %gep.b 103 %and = and i32 %a, %b 104 store i32 %and, i32 addrspace(1)* %gep.out 105 ret void 106} 107 108; FUNC-LABEL: {{^}}v_and_i32_sgpr_vgpr: 109; SI-DAG: s_load_dword [[SA:s[0-9]+]] 110; SI-DAG: {{buffer|flat}}_load_dword [[VB:v[0-9]+]] 111; SI: v_and_b32_e32 v{{[0-9]+}}, [[SA]], [[VB]] 112define void @v_and_i32_sgpr_vgpr(i32 addrspace(1)* %out, i32 %a, i32 addrspace(1)* %bptr) { 113 %tid = call i32 @llvm.r600.read.tidig.x() #0 114 %gep.b = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid 115 %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid 116 %b = load i32, i32 addrspace(1)* %gep.b 117 %and = and i32 %a, %b 118 store i32 %and, i32 addrspace(1)* %gep.out 119 ret void 120} 121 122; FUNC-LABEL: {{^}}v_and_i32_vgpr_sgpr: 123; SI-DAG: s_load_dword [[SA:s[0-9]+]] 124; SI-DAG: {{buffer|flat}}_load_dword [[VB:v[0-9]+]] 125; SI: v_and_b32_e32 v{{[0-9]+}}, [[SA]], [[VB]] 126define void @v_and_i32_vgpr_sgpr(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 %b) { 127 %tid = call i32 @llvm.r600.read.tidig.x() #0 128 %gep.a = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid 129 %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid 130 %a = load i32, i32 addrspace(1)* %gep.a 131 %and = and i32 %a, %b 132 store i32 %and, i32 addrspace(1)* %gep.out 133 ret void 134} 135 136; FUNC-LABEL: {{^}}v_and_constant_i32 137; SI: v_and_b32_e32 v{{[0-9]+}}, 0x12d687, v{{[0-9]+}} 138define void @v_and_constant_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) { 139 %a = load i32, i32 addrspace(1)* %aptr, align 4 140 %and = and i32 %a, 1234567 141 store i32 %and, i32 addrspace(1)* %out, align 4 142 ret void 143} 144 145; FUNC-LABEL: {{^}}v_and_inline_imm_64_i32 146; SI: v_and_b32_e32 v{{[0-9]+}}, 64, v{{[0-9]+}} 147define void @v_and_inline_imm_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) { 148 %a = load i32, i32 addrspace(1)* %aptr, align 4 149 %and = and i32 %a, 64 150 store i32 %and, i32 addrspace(1)* %out, align 4 151 ret void 152} 153 154; FUNC-LABEL: {{^}}v_and_inline_imm_neg_16_i32 155; SI: v_and_b32_e32 v{{[0-9]+}}, -16, v{{[0-9]+}} 156define void @v_and_inline_imm_neg_16_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) { 157 %a = load i32, i32 addrspace(1)* %aptr, align 4 158 %and = and i32 %a, -16 159 store i32 %and, i32 addrspace(1)* %out, align 4 160 ret void 161} 162 163; FUNC-LABEL: {{^}}s_and_i64 164; SI: s_and_b64 165define void @s_and_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { 166 %and = and i64 %a, %b 167 store i64 %and, i64 addrspace(1)* %out, align 8 168 ret void 169} 170 171; FIXME: Should use SGPRs 172; FUNC-LABEL: {{^}}s_and_i1: 173; SI: v_and_b32 174define void @s_and_i1(i1 addrspace(1)* %out, i1 %a, i1 %b) { 175 %and = and i1 %a, %b 176 store i1 %and, i1 addrspace(1)* %out 177 ret void 178} 179 180; FUNC-LABEL: {{^}}s_and_constant_i64: 181; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000{{$}} 182; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80{{$}} 183; SI: buffer_store_dwordx2 184define void @s_and_constant_i64(i64 addrspace(1)* %out, i64 %a) { 185 %and = and i64 %a, 549756338176 186 store i64 %and, i64 addrspace(1)* %out, align 8 187 ret void 188} 189 190; FUNC-LABEL: {{^}}s_and_multi_use_constant_i64: 191; XSI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0x80000{{$}} 192; XSI-DAG: s_mov_b32 s[[KHI:[0-9]+]], 0x80{{$}} 193; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}} 194define void @s_and_multi_use_constant_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { 195 %and0 = and i64 %a, 549756338176 196 %and1 = and i64 %b, 549756338176 197 store volatile i64 %and0, i64 addrspace(1)* %out 198 store volatile i64 %and1, i64 addrspace(1)* %out 199 ret void 200} 201 202; FUNC-LABEL: {{^}}s_and_32_bit_constant_i64: 203; SI: s_load_dwordx2 204; SI-NOT: and 205; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x12d687{{$}} 206; SI-NOT: and 207; SI: buffer_store_dwordx2 208define void @s_and_32_bit_constant_i64(i64 addrspace(1)* %out, i64 %a) { 209 %and = and i64 %a, 1234567 210 store i64 %and, i64 addrspace(1)* %out, align 8 211 ret void 212} 213 214; FUNC-LABEL: {{^}}s_and_multi_use_inline_imm_i64: 215; SI: s_load_dwordx2 216; SI: s_load_dwordx2 217; SI: s_load_dwordx2 218; SI: s_load_dwordx2 219; SI-NOT: and 220; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 62 221; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 62 222; SI-NOT: and 223; SI: buffer_store_dwordx2 224define void @s_and_multi_use_inline_imm_i64(i64 addrspace(1)* %out, i64 %a, i64 %b, i64 %c) { 225 %shl.a = shl i64 %a, 1 226 %shl.b = shl i64 %b, 1 227 %and0 = and i64 %shl.a, 62 228 %and1 = and i64 %shl.b, 62 229 %add0 = add i64 %and0, %c 230 %add1 = add i64 %and1, %c 231 store volatile i64 %add0, i64 addrspace(1)* %out 232 store volatile i64 %add1, i64 addrspace(1)* %out 233 ret void 234} 235 236; FUNC-LABEL: {{^}}v_and_i64: 237; SI: v_and_b32 238; SI: v_and_b32 239define void @v_and_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) { 240 %a = load i64, i64 addrspace(1)* %aptr, align 8 241 %b = load i64, i64 addrspace(1)* %bptr, align 8 242 %and = and i64 %a, %b 243 store i64 %and, i64 addrspace(1)* %out, align 8 244 ret void 245} 246 247; FUNC-LABEL: {{^}}v_and_constant_i64: 248; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, 0xab19b207, {{v[0-9]+}} 249; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, 0x11e, {{v[0-9]+}} 250; SI: buffer_store_dwordx2 251define void @v_and_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 252 %a = load i64, i64 addrspace(1)* %aptr, align 8 253 %and = and i64 %a, 1231231234567 254 store i64 %and, i64 addrspace(1)* %out, align 8 255 ret void 256} 257 258; FUNC-LABEL: {{^}}v_and_multi_use_constant_i64: 259; SI: buffer_load_dwordx2 v{{\[}}[[LO0:[0-9]+]]:[[HI0:[0-9]+]]{{\]}} 260; SI: buffer_load_dwordx2 v{{\[}}[[LO1:[0-9]+]]:[[HI1:[0-9]+]]{{\]}} 261; SI-DAG: s_mov_b32 [[KLO:s[0-9]+]], 0xab19b207{{$}} 262; SI-DAG: s_movk_i32 [[KHI:s[0-9]+]], 0x11e{{$}} 263; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], v[[LO0]] 264; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], v[[HI0]] 265; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], v[[LO1]] 266; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], v[[HI1]] 267; SI: buffer_store_dwordx2 268; SI: buffer_store_dwordx2 269define void @v_and_multi_use_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 270 %a = load volatile i64, i64 addrspace(1)* %aptr 271 %b = load volatile i64, i64 addrspace(1)* %aptr 272 %and0 = and i64 %a, 1231231234567 273 %and1 = and i64 %b, 1231231234567 274 store volatile i64 %and0, i64 addrspace(1)* %out 275 store volatile i64 %and1, i64 addrspace(1)* %out 276 ret void 277} 278 279; FUNC-LABEL: {{^}}v_and_multi_use_inline_imm_i64: 280; SI: buffer_load_dwordx2 v{{\[}}[[LO0:[0-9]+]]:[[HI0:[0-9]+]]{{\]}} 281; SI-NOT: and 282; SI: buffer_load_dwordx2 v{{\[}}[[LO1:[0-9]+]]:[[HI1:[0-9]+]]{{\]}} 283; SI-NOT: and 284; SI: v_and_b32_e32 v[[RESLO0:[0-9]+]], 63, v[[LO0]] 285; SI: v_and_b32_e32 v[[RESLO1:[0-9]+]], 63, v[[LO1]] 286; SI-NOT: and 287; SI: buffer_store_dwordx2 288; SI-NOT: and 289; SI: buffer_store_dwordx2 290define void @v_and_multi_use_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 291 %a = load volatile i64, i64 addrspace(1)* %aptr 292 %b = load volatile i64, i64 addrspace(1)* %aptr 293 %and0 = and i64 %a, 63 294 %and1 = and i64 %b, 63 295 store volatile i64 %and0, i64 addrspace(1)* %out 296 store volatile i64 %and1, i64 addrspace(1)* %out 297 ret void 298} 299 300; FUNC-LABEL: {{^}}v_and_i64_32_bit_constant: 301; SI: buffer_load_dword [[VAL:v[0-9]+]] 302; SI-NOT: and 303; SI: v_and_b32_e32 {{v[0-9]+}}, 0x12d687, [[VAL]] 304; SI-NOT: and 305; SI: buffer_store_dwordx2 306define void @v_and_i64_32_bit_constant(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 307 %a = load i64, i64 addrspace(1)* %aptr, align 8 308 %and = and i64 %a, 1234567 309 store i64 %and, i64 addrspace(1)* %out, align 8 310 ret void 311} 312 313; FUNC-LABEL: {{^}}v_and_inline_imm_i64: 314; SI: buffer_load_dword v{{[0-9]+}} 315; SI-NOT: and 316; SI: v_and_b32_e32 {{v[0-9]+}}, 64, {{v[0-9]+}} 317; SI-NOT: and 318; SI: buffer_store_dwordx2 319define void @v_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 320 %a = load i64, i64 addrspace(1)* %aptr, align 8 321 %and = and i64 %a, 64 322 store i64 %and, i64 addrspace(1)* %out, align 8 323 ret void 324} 325 326; FUNC-LABEL: {{^}}s_and_inline_imm_64_i64 327; SI: s_load_dword 328; SI-NOT: and 329; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 64 330; SI-NOT: and 331; SI: buffer_store_dword 332define void @s_and_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 333 %and = and i64 %a, 64 334 store i64 %and, i64 addrspace(1)* %out, align 8 335 ret void 336} 337 338; FUNC-LABEL: {{^}}s_and_inline_imm_64_i64_noshrink: 339; SI: s_lshl_b64 s{{\[}}[[VALLO:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1 340; SI-NOT: and 341; SI: s_and_b32 s{{[0-9]+}}, s[[VALLO]], 64 342; SI-NOT: and 343; SI: s_add_u32 344; SI-NEXT: s_addc_u32 345define void @s_and_inline_imm_64_i64_noshrink(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a, i64 %b) { 346 %shl = shl i64 %a, 1 347 %and = and i64 %shl, 64 348 %add = add i64 %and, %b 349 store i64 %add, i64 addrspace(1)* %out, align 8 350 ret void 351} 352 353; FUNC-LABEL: {{^}}s_and_inline_imm_1_i64 354; SI: s_load_dwordx2 355; SI-NOT: and 356; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1 357; SI-NOT: and 358; SI: buffer_store_dwordx2 359define void @s_and_inline_imm_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 360 %and = and i64 %a, 1 361 store i64 %and, i64 addrspace(1)* %out, align 8 362 ret void 363} 364 365; FUNC-LABEL: {{^}}s_and_inline_imm_1.0_i64 366; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1.0 367 368; SI: s_load_dwordx2 369; SI: s_load_dwordx2 370; SI-NOT: and 371; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x3ff00000 372; SI-NOT: and 373; SI: buffer_store_dwordx2 374define void @s_and_inline_imm_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 375 %and = and i64 %a, 4607182418800017408 376 store i64 %and, i64 addrspace(1)* %out, align 8 377 ret void 378} 379 380; FUNC-LABEL: {{^}}s_and_inline_imm_neg_1.0_i64 381; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -1.0 382 383; SI: s_load_dwordx2 384; SI: s_load_dwordx2 385; SI-NOT: and 386; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xbff00000 387; SI-NOT: and 388; SI: buffer_store_dwordx2 389define void @s_and_inline_imm_neg_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 390 %and = and i64 %a, 13830554455654793216 391 store i64 %and, i64 addrspace(1)* %out, align 8 392 ret void 393} 394 395; FUNC-LABEL: {{^}}s_and_inline_imm_0.5_i64 396; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0.5 397 398; SI: s_load_dwordx2 399; SI: s_load_dwordx2 400; SI-NOT: and 401; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x3fe00000 402; SI-NOT: and 403; SI: buffer_store_dwordx2 404define void @s_and_inline_imm_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 405 %and = and i64 %a, 4602678819172646912 406 store i64 %and, i64 addrspace(1)* %out, align 8 407 ret void 408} 409 410; FUNC-LABEL: {{^}}s_and_inline_imm_neg_0.5_i64: 411; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -0.5 412 413; SI: s_load_dwordx2 414; SI: s_load_dwordx2 415; SI-NOT: and 416; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xbfe00000 417; SI-NOT: and 418; SI: buffer_store_dwordx2 419define void @s_and_inline_imm_neg_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 420 %and = and i64 %a, 13826050856027422720 421 store i64 %and, i64 addrspace(1)* %out, align 8 422 ret void 423} 424 425; FUNC-LABEL: {{^}}s_and_inline_imm_2.0_i64: 426; SI: s_load_dwordx2 427; SI: s_load_dwordx2 428; SI-NOT: and 429; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 2.0 430; SI-NOT: and 431; SI: buffer_store_dwordx2 432define void @s_and_inline_imm_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 433 %and = and i64 %a, 4611686018427387904 434 store i64 %and, i64 addrspace(1)* %out, align 8 435 ret void 436} 437 438; FUNC-LABEL: {{^}}s_and_inline_imm_neg_2.0_i64: 439; SI: s_load_dwordx2 440; SI: s_load_dwordx2 441; SI-NOT: and 442; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, -2.0 443; SI-NOT: and 444; SI: buffer_store_dwordx2 445define void @s_and_inline_imm_neg_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 446 %and = and i64 %a, 13835058055282163712 447 store i64 %and, i64 addrspace(1)* %out, align 8 448 ret void 449} 450 451; FUNC-LABEL: {{^}}s_and_inline_imm_4.0_i64: 452; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 4.0 453 454; SI: s_load_dwordx2 455; SI: s_load_dwordx2 456; SI-NOT: and 457; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x40100000 458; SI-NOT: and 459; SI: buffer_store_dwordx2 460define void @s_and_inline_imm_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 461 %and = and i64 %a, 4616189618054758400 462 store i64 %and, i64 addrspace(1)* %out, align 8 463 ret void 464} 465 466; FUNC-LABEL: {{^}}s_and_inline_imm_neg_4.0_i64: 467; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -4.0 468 469; SI: s_load_dwordx2 470; SI: s_load_dwordx2 471; SI-NOT: and 472; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xc0100000 473; SI-NOT: and 474; SI: buffer_store_dwordx2 475define void @s_and_inline_imm_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 476 %and = and i64 %a, 13839561654909534208 477 store i64 %and, i64 addrspace(1)* %out, align 8 478 ret void 479} 480 481 482; Test with the 64-bit integer bitpattern for a 32-bit float in the 483; low 32-bits, which is not a valid 64-bit inline immmediate. 484 485; FUNC-LABEL: {{^}}s_and_inline_imm_f32_4.0_i64: 486; SI: s_load_dwordx2 487; SI: s_load_dword s 488; SI-NOT: and 489; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, 4.0 490; SI-NOT: and 491; SI: buffer_store_dwordx2 492define void @s_and_inline_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 493 %and = and i64 %a, 1082130432 494 store i64 %and, i64 addrspace(1)* %out, align 8 495 ret void 496} 497 498; FUNC-LABEL: {{^}}s_and_inline_imm_f32_neg_4.0_i64: 499; SI: s_load_dwordx2 500; SI: s_load_dwordx2 501; SI-NOT: and 502; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, -4.0 503; SI-NOT: and 504; SI: buffer_store_dwordx2 505define void @s_and_inline_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 506 %and = and i64 %a, -1065353216 507 store i64 %and, i64 addrspace(1)* %out, align 8 508 ret void 509} 510 511; Shift into upper 32-bits 512; SI: s_load_dwordx2 513; SI: s_load_dwordx2 514; SI-NOT: and 515; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, 4.0 516; SI-NOT: and 517; SI: buffer_store_dwordx2 518define void @s_and_inline_high_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 519 %and = and i64 %a, 4647714815446351872 520 store i64 %and, i64 addrspace(1)* %out, align 8 521 ret void 522} 523 524; FUNC-LABEL: {{^}}s_and_inline_high_imm_f32_neg_4.0_i64: 525; SI: s_load_dwordx2 526; SI: s_load_dwordx2 527; SI-NOT: and 528; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, -4.0 529; SI-NOT: and 530; SI: buffer_store_dwordx2 531define void @s_and_inline_high_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 532 %and = and i64 %a, 13871086852301127680 533 store i64 %and, i64 addrspace(1)* %out, align 8 534 ret void 535} 536 537attributes #0 = { nounwind readnone } 538