1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -S -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-codegenprepare %s | FileCheck -check-prefix=SI %s 3; RUN: opt -S -mtriple=amdgcn-- -mcpu=fiji -amdgpu-codegenprepare %s | FileCheck -check-prefix=VI %s 4; RUN: opt -S -mtriple=amdgcn-- -mcpu=fiji -amdgpu-codegenprepare-mul24=0 -amdgpu-codegenprepare %s | FileCheck -check-prefix=DISABLED %s 5 6define i16 @mul_i16(i16 %lhs, i16 %rhs) { 7; SI-LABEL: @mul_i16( 8; SI-NEXT: [[TMP1:%.*]] = zext i16 [[LHS:%.*]] to i32 9; SI-NEXT: [[TMP2:%.*]] = zext i16 [[RHS:%.*]] to i32 10; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]]) 11; SI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i16 12; SI-NEXT: ret i16 [[MUL]] 13; 14; VI-LABEL: @mul_i16( 15; VI-NEXT: [[MUL:%.*]] = mul i16 [[LHS:%.*]], [[RHS:%.*]] 16; VI-NEXT: ret i16 [[MUL]] 17; 18; DISABLED-LABEL: @mul_i16( 19; DISABLED-NEXT: [[MUL:%.*]] = mul i16 [[LHS:%.*]], [[RHS:%.*]] 20; DISABLED-NEXT: ret i16 [[MUL]] 21; 22 %mul = mul i16 %lhs, %rhs 23 ret i16 %mul 24} 25 26define i32 @smul24_i32(i32 %lhs, i32 %rhs) { 27; SI-LABEL: @smul24_i32( 28; SI-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 8 29; SI-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 8 30; SI-NEXT: [[LSHR_RHS:%.*]] = shl i32 [[RHS:%.*]], 8 31; SI-NEXT: [[RHS24:%.*]] = ashr i32 [[LHS]], 8 32; SI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[LHS24]], i32 [[RHS24]]) 33; SI-NEXT: ret i32 [[MUL]] 34; 35; VI-LABEL: @smul24_i32( 36; VI-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 8 37; VI-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 8 38; VI-NEXT: [[LSHR_RHS:%.*]] = shl i32 [[RHS:%.*]], 8 39; VI-NEXT: [[RHS24:%.*]] = ashr i32 [[LHS]], 8 40; VI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[LHS24]], i32 [[RHS24]]) 41; VI-NEXT: ret i32 [[MUL]] 42; 43; DISABLED-LABEL: @smul24_i32( 44; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 8 45; DISABLED-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 8 46; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl i32 [[RHS:%.*]], 8 47; DISABLED-NEXT: [[RHS24:%.*]] = ashr i32 [[LHS]], 8 48; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 49; DISABLED-NEXT: ret i32 [[MUL]] 50; 51 %shl.lhs = shl i32 %lhs, 8 52 %lhs24 = ashr i32 %shl.lhs, 8 53 %lshr.rhs = shl i32 %rhs, 8 54 %rhs24 = ashr i32 %lhs, 8 55 %mul = mul i32 %lhs24, %rhs24 56 ret i32 %mul 57} 58 59define <2 x i32> @smul24_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 60; SI-LABEL: @smul24_v2i32( 61; SI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i32> [[LHS:%.*]], <i32 8, i32 8> 62; SI-NEXT: [[LHS24:%.*]] = ashr <2 x i32> [[SHL_LHS]], <i32 8, i32 8> 63; SI-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i32> [[RHS:%.*]], <i32 8, i32 8> 64; SI-NEXT: [[RHS24:%.*]] = ashr <2 x i32> [[LHS]], <i32 8, i32 8> 65; SI-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[LHS24]], i64 0 66; SI-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[LHS24]], i64 1 67; SI-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[RHS24]], i64 0 68; SI-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[RHS24]], i64 1 69; SI-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP3]]) 70; SI-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP2]], i32 [[TMP4]]) 71; SI-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> undef, i32 [[TMP5]], i64 0 72; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1 73; SI-NEXT: ret <2 x i32> [[MUL]] 74; 75; VI-LABEL: @smul24_v2i32( 76; VI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i32> [[LHS:%.*]], <i32 8, i32 8> 77; VI-NEXT: [[LHS24:%.*]] = ashr <2 x i32> [[SHL_LHS]], <i32 8, i32 8> 78; VI-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i32> [[RHS:%.*]], <i32 8, i32 8> 79; VI-NEXT: [[RHS24:%.*]] = ashr <2 x i32> [[LHS]], <i32 8, i32 8> 80; VI-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[LHS24]], i64 0 81; VI-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[LHS24]], i64 1 82; VI-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[RHS24]], i64 0 83; VI-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[RHS24]], i64 1 84; VI-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP3]]) 85; VI-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP2]], i32 [[TMP4]]) 86; VI-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> undef, i32 [[TMP5]], i64 0 87; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1 88; VI-NEXT: ret <2 x i32> [[MUL]] 89; 90; DISABLED-LABEL: @smul24_v2i32( 91; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl <2 x i32> [[LHS:%.*]], <i32 8, i32 8> 92; DISABLED-NEXT: [[LHS24:%.*]] = ashr <2 x i32> [[SHL_LHS]], <i32 8, i32 8> 93; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i32> [[RHS:%.*]], <i32 8, i32 8> 94; DISABLED-NEXT: [[RHS24:%.*]] = ashr <2 x i32> [[LHS]], <i32 8, i32 8> 95; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i32> [[LHS24]], [[RHS24]] 96; DISABLED-NEXT: ret <2 x i32> [[MUL]] 97; 98 %shl.lhs = shl <2 x i32> %lhs, <i32 8, i32 8> 99 %lhs24 = ashr <2 x i32> %shl.lhs, <i32 8, i32 8> 100 %lshr.rhs = shl <2 x i32> %rhs, <i32 8, i32 8> 101 %rhs24 = ashr <2 x i32> %lhs, <i32 8, i32 8> 102 %mul = mul <2 x i32> %lhs24, %rhs24 103 ret <2 x i32> %mul 104} 105 106define i32 @umul24_i32(i32 %lhs, i32 %rhs) { 107; SI-LABEL: @umul24_i32( 108; SI-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 16777215 109; SI-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 16777215 110; SI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[LHS24]], i32 [[RHS24]]) 111; SI-NEXT: ret i32 [[MUL]] 112; 113; VI-LABEL: @umul24_i32( 114; VI-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 16777215 115; VI-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 16777215 116; VI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[LHS24]], i32 [[RHS24]]) 117; VI-NEXT: ret i32 [[MUL]] 118; 119; DISABLED-LABEL: @umul24_i32( 120; DISABLED-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 16777215 121; DISABLED-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 16777215 122; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 123; DISABLED-NEXT: ret i32 [[MUL]] 124; 125 %lhs24 = and i32 %lhs, 16777215 126 %rhs24 = and i32 %rhs, 16777215 127 %mul = mul i32 %lhs24, %rhs24 128 ret i32 %mul 129} 130 131define <2 x i32> @umul24_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 132; SI-LABEL: @umul24_v2i32( 133; SI-NEXT: [[LHS24:%.*]] = and <2 x i32> [[LHS:%.*]], <i32 16777215, i32 16777215> 134; SI-NEXT: [[RHS24:%.*]] = and <2 x i32> [[RHS:%.*]], <i32 16777215, i32 16777215> 135; SI-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[LHS24]], i64 0 136; SI-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[LHS24]], i64 1 137; SI-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[RHS24]], i64 0 138; SI-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[RHS24]], i64 1 139; SI-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP3]]) 140; SI-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP2]], i32 [[TMP4]]) 141; SI-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> undef, i32 [[TMP5]], i64 0 142; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1 143; SI-NEXT: ret <2 x i32> [[MUL]] 144; 145; VI-LABEL: @umul24_v2i32( 146; VI-NEXT: [[LHS24:%.*]] = and <2 x i32> [[LHS:%.*]], <i32 16777215, i32 16777215> 147; VI-NEXT: [[RHS24:%.*]] = and <2 x i32> [[RHS:%.*]], <i32 16777215, i32 16777215> 148; VI-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[LHS24]], i64 0 149; VI-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[LHS24]], i64 1 150; VI-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[RHS24]], i64 0 151; VI-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[RHS24]], i64 1 152; VI-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP3]]) 153; VI-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP2]], i32 [[TMP4]]) 154; VI-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> undef, i32 [[TMP5]], i64 0 155; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1 156; VI-NEXT: ret <2 x i32> [[MUL]] 157; 158; DISABLED-LABEL: @umul24_v2i32( 159; DISABLED-NEXT: [[LHS24:%.*]] = and <2 x i32> [[LHS:%.*]], <i32 16777215, i32 16777215> 160; DISABLED-NEXT: [[RHS24:%.*]] = and <2 x i32> [[RHS:%.*]], <i32 16777215, i32 16777215> 161; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i32> [[LHS24]], [[RHS24]] 162; DISABLED-NEXT: ret <2 x i32> [[MUL]] 163; 164 %lhs24 = and <2 x i32> %lhs, <i32 16777215, i32 16777215> 165 %rhs24 = and <2 x i32> %rhs, <i32 16777215, i32 16777215> 166 %mul = mul <2 x i32> %lhs24, %rhs24 167 ret <2 x i32> %mul 168} 169 170define i64 @smul24_i64(i64 %lhs, i64 %rhs) { 171; SI-LABEL: @smul24_i64( 172; SI-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 40 173; SI-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 40 174; SI-NEXT: [[LSHR_RHS:%.*]] = shl i64 [[RHS:%.*]], 40 175; SI-NEXT: [[RHS24:%.*]] = ashr i64 [[LHS]], 40 176; SI-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 177; SI-NEXT: ret i64 [[MUL]] 178; 179; VI-LABEL: @smul24_i64( 180; VI-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 40 181; VI-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 40 182; VI-NEXT: [[LSHR_RHS:%.*]] = shl i64 [[RHS:%.*]], 40 183; VI-NEXT: [[RHS24:%.*]] = ashr i64 [[LHS]], 40 184; VI-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 185; VI-NEXT: ret i64 [[MUL]] 186; 187; DISABLED-LABEL: @smul24_i64( 188; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 40 189; DISABLED-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 40 190; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl i64 [[RHS:%.*]], 40 191; DISABLED-NEXT: [[RHS24:%.*]] = ashr i64 [[LHS]], 40 192; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 193; DISABLED-NEXT: ret i64 [[MUL]] 194; 195 %shl.lhs = shl i64 %lhs, 40 196 %lhs24 = ashr i64 %shl.lhs, 40 197 %lshr.rhs = shl i64 %rhs, 40 198 %rhs24 = ashr i64 %lhs, 40 199 %mul = mul i64 %lhs24, %rhs24 200 ret i64 %mul 201} 202 203define i64 @smul24_i64_2(i64 %lhs, i64 %rhs) { 204; SI-LABEL: @smul24_i64_2( 205; SI-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 49 206; SI-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 49 207; SI-NEXT: [[LSHR_RHS:%.*]] = shl i64 [[RHS:%.*]], 49 208; SI-NEXT: [[RHS24:%.*]] = ashr i64 [[LHS]], 49 209; SI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32 210; SI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32 211; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]]) 212; SI-NEXT: [[MUL:%.*]] = sext i32 [[TMP3]] to i64 213; SI-NEXT: ret i64 [[MUL]] 214; 215; VI-LABEL: @smul24_i64_2( 216; VI-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 49 217; VI-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 49 218; VI-NEXT: [[LSHR_RHS:%.*]] = shl i64 [[RHS:%.*]], 49 219; VI-NEXT: [[RHS24:%.*]] = ashr i64 [[LHS]], 49 220; VI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32 221; VI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32 222; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]]) 223; VI-NEXT: [[MUL:%.*]] = sext i32 [[TMP3]] to i64 224; VI-NEXT: ret i64 [[MUL]] 225; 226; DISABLED-LABEL: @smul24_i64_2( 227; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 49 228; DISABLED-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 49 229; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl i64 [[RHS:%.*]], 49 230; DISABLED-NEXT: [[RHS24:%.*]] = ashr i64 [[LHS]], 49 231; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 232; DISABLED-NEXT: ret i64 [[MUL]] 233; 234 %shl.lhs = shl i64 %lhs, 49 235 %lhs24 = ashr i64 %shl.lhs, 49 236 %lshr.rhs = shl i64 %rhs, 49 237 %rhs24 = ashr i64 %lhs, 49 238 %mul = mul i64 %lhs24, %rhs24 239 ret i64 %mul 240} 241 242define i64 @smul24_i64_3(i64 %lhs, i64 %rhs) { 243; SI-LABEL: @smul24_i64_3( 244; SI-NEXT: [[LHS_TRUNC:%.*]] = trunc i64 [[LHS:%.*]] to i16 245; SI-NEXT: [[LHS24:%.*]] = sext i16 [[LHS_TRUNC]] to i64 246; SI-NEXT: [[RHS_TRUNC:%.*]] = trunc i64 [[RHS:%.*]] to i17 247; SI-NEXT: [[RHS24:%.*]] = sext i17 [[RHS_TRUNC]] to i64 248; SI-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 249; SI-NEXT: ret i64 [[MUL]] 250; 251; VI-LABEL: @smul24_i64_3( 252; VI-NEXT: [[LHS_TRUNC:%.*]] = trunc i64 [[LHS:%.*]] to i16 253; VI-NEXT: [[LHS24:%.*]] = sext i16 [[LHS_TRUNC]] to i64 254; VI-NEXT: [[RHS_TRUNC:%.*]] = trunc i64 [[RHS:%.*]] to i17 255; VI-NEXT: [[RHS24:%.*]] = sext i17 [[RHS_TRUNC]] to i64 256; VI-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 257; VI-NEXT: ret i64 [[MUL]] 258; 259; DISABLED-LABEL: @smul24_i64_3( 260; DISABLED-NEXT: [[LHS_TRUNC:%.*]] = trunc i64 [[LHS:%.*]] to i16 261; DISABLED-NEXT: [[LHS24:%.*]] = sext i16 [[LHS_TRUNC]] to i64 262; DISABLED-NEXT: [[RHS_TRUNC:%.*]] = trunc i64 [[RHS:%.*]] to i17 263; DISABLED-NEXT: [[RHS24:%.*]] = sext i17 [[RHS_TRUNC]] to i64 264; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 265; DISABLED-NEXT: ret i64 [[MUL]] 266; 267 %lhs.trunc = trunc i64 %lhs to i16 268 %lhs24 = sext i16 %lhs.trunc to i64 269 %rhs.trunc = trunc i64 %rhs to i17 270 %rhs24 = sext i17 %rhs.trunc to i64 271 %mul = mul i64 %lhs24, %rhs24 272 ret i64 %mul 273} 274 275define i64 @umul24_i64(i64 %lhs, i64 %rhs) { 276; SI-LABEL: @umul24_i64( 277; SI-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 16777215 278; SI-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 16777215 279; SI-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 280; SI-NEXT: ret i64 [[MUL]] 281; 282; VI-LABEL: @umul24_i64( 283; VI-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 16777215 284; VI-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 16777215 285; VI-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 286; VI-NEXT: ret i64 [[MUL]] 287; 288; DISABLED-LABEL: @umul24_i64( 289; DISABLED-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 16777215 290; DISABLED-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 16777215 291; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 292; DISABLED-NEXT: ret i64 [[MUL]] 293; 294 %lhs24 = and i64 %lhs, 16777215 295 %rhs24 = and i64 %rhs, 16777215 296 %mul = mul i64 %lhs24, %rhs24 297 ret i64 %mul 298} 299 300define i64 @umul24_i64_2(i64 %lhs, i64 %rhs) { 301; SI-LABEL: @umul24_i64_2( 302; SI-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 65535 303; SI-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 65535 304; SI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32 305; SI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32 306; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]]) 307; SI-NEXT: [[MUL:%.*]] = zext i32 [[TMP3]] to i64 308; SI-NEXT: ret i64 [[MUL]] 309; 310; VI-LABEL: @umul24_i64_2( 311; VI-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 65535 312; VI-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 65535 313; VI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32 314; VI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32 315; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]]) 316; VI-NEXT: [[MUL:%.*]] = zext i32 [[TMP3]] to i64 317; VI-NEXT: ret i64 [[MUL]] 318; 319; DISABLED-LABEL: @umul24_i64_2( 320; DISABLED-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 65535 321; DISABLED-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 65535 322; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 323; DISABLED-NEXT: ret i64 [[MUL]] 324; 325 %lhs24 = and i64 %lhs, 65535 326 %rhs24 = and i64 %rhs, 65535 327 %mul = mul i64 %lhs24, %rhs24 328 ret i64 %mul 329} 330 331define i31 @smul24_i31(i31 %lhs, i31 %rhs) { 332; SI-LABEL: @smul24_i31( 333; SI-NEXT: [[SHL_LHS:%.*]] = shl i31 [[LHS:%.*]], 7 334; SI-NEXT: [[LHS24:%.*]] = ashr i31 [[SHL_LHS]], 7 335; SI-NEXT: [[LSHR_RHS:%.*]] = shl i31 [[RHS:%.*]], 7 336; SI-NEXT: [[RHS24:%.*]] = ashr i31 [[LHS]], 7 337; SI-NEXT: [[TMP1:%.*]] = sext i31 [[LHS24]] to i32 338; SI-NEXT: [[TMP2:%.*]] = sext i31 [[RHS24]] to i32 339; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]]) 340; SI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31 341; SI-NEXT: ret i31 [[MUL]] 342; 343; VI-LABEL: @smul24_i31( 344; VI-NEXT: [[SHL_LHS:%.*]] = shl i31 [[LHS:%.*]], 7 345; VI-NEXT: [[LHS24:%.*]] = ashr i31 [[SHL_LHS]], 7 346; VI-NEXT: [[LSHR_RHS:%.*]] = shl i31 [[RHS:%.*]], 7 347; VI-NEXT: [[RHS24:%.*]] = ashr i31 [[LHS]], 7 348; VI-NEXT: [[TMP1:%.*]] = sext i31 [[LHS24]] to i32 349; VI-NEXT: [[TMP2:%.*]] = sext i31 [[RHS24]] to i32 350; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]]) 351; VI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31 352; VI-NEXT: ret i31 [[MUL]] 353; 354; DISABLED-LABEL: @smul24_i31( 355; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i31 [[LHS:%.*]], 7 356; DISABLED-NEXT: [[LHS24:%.*]] = ashr i31 [[SHL_LHS]], 7 357; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl i31 [[RHS:%.*]], 7 358; DISABLED-NEXT: [[RHS24:%.*]] = ashr i31 [[LHS]], 7 359; DISABLED-NEXT: [[MUL:%.*]] = mul i31 [[LHS24]], [[RHS24]] 360; DISABLED-NEXT: ret i31 [[MUL]] 361; 362 %shl.lhs = shl i31 %lhs, 7 363 %lhs24 = ashr i31 %shl.lhs, 7 364 %lshr.rhs = shl i31 %rhs, 7 365 %rhs24 = ashr i31 %lhs, 7 366 %mul = mul i31 %lhs24, %rhs24 367 ret i31 %mul 368} 369 370define i31 @umul24_i31(i31 %lhs, i31 %rhs) { 371; SI-LABEL: @umul24_i31( 372; SI-NEXT: [[LHS24:%.*]] = and i31 [[LHS:%.*]], 16777215 373; SI-NEXT: [[RHS24:%.*]] = and i31 [[RHS:%.*]], 16777215 374; SI-NEXT: [[TMP1:%.*]] = zext i31 [[LHS24]] to i32 375; SI-NEXT: [[TMP2:%.*]] = zext i31 [[RHS24]] to i32 376; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]]) 377; SI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31 378; SI-NEXT: ret i31 [[MUL]] 379; 380; VI-LABEL: @umul24_i31( 381; VI-NEXT: [[LHS24:%.*]] = and i31 [[LHS:%.*]], 16777215 382; VI-NEXT: [[RHS24:%.*]] = and i31 [[RHS:%.*]], 16777215 383; VI-NEXT: [[TMP1:%.*]] = zext i31 [[LHS24]] to i32 384; VI-NEXT: [[TMP2:%.*]] = zext i31 [[RHS24]] to i32 385; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]]) 386; VI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31 387; VI-NEXT: ret i31 [[MUL]] 388; 389; DISABLED-LABEL: @umul24_i31( 390; DISABLED-NEXT: [[LHS24:%.*]] = and i31 [[LHS:%.*]], 16777215 391; DISABLED-NEXT: [[RHS24:%.*]] = and i31 [[RHS:%.*]], 16777215 392; DISABLED-NEXT: [[MUL:%.*]] = mul i31 [[LHS24]], [[RHS24]] 393; DISABLED-NEXT: ret i31 [[MUL]] 394; 395 %lhs24 = and i31 %lhs, 16777215 396 %rhs24 = and i31 %rhs, 16777215 397 %mul = mul i31 %lhs24, %rhs24 398 ret i31 %mul 399} 400 401define <2 x i31> @umul24_v2i31(<2 x i31> %lhs, <2 x i31> %rhs) { 402; SI-LABEL: @umul24_v2i31( 403; SI-NEXT: [[LHS24:%.*]] = and <2 x i31> [[LHS:%.*]], <i31 16777215, i31 16777215> 404; SI-NEXT: [[RHS24:%.*]] = and <2 x i31> [[RHS:%.*]], <i31 16777215, i31 16777215> 405; SI-NEXT: [[TMP1:%.*]] = extractelement <2 x i31> [[LHS24]], i64 0 406; SI-NEXT: [[TMP2:%.*]] = extractelement <2 x i31> [[LHS24]], i64 1 407; SI-NEXT: [[TMP3:%.*]] = extractelement <2 x i31> [[RHS24]], i64 0 408; SI-NEXT: [[TMP4:%.*]] = extractelement <2 x i31> [[RHS24]], i64 1 409; SI-NEXT: [[TMP5:%.*]] = zext i31 [[TMP1]] to i32 410; SI-NEXT: [[TMP6:%.*]] = zext i31 [[TMP3]] to i32 411; SI-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP5]], i32 [[TMP6]]) 412; SI-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i31 413; SI-NEXT: [[TMP9:%.*]] = zext i31 [[TMP2]] to i32 414; SI-NEXT: [[TMP10:%.*]] = zext i31 [[TMP4]] to i32 415; SI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP9]], i32 [[TMP10]]) 416; SI-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i31 417; SI-NEXT: [[TMP13:%.*]] = insertelement <2 x i31> undef, i31 [[TMP8]], i64 0 418; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1 419; SI-NEXT: ret <2 x i31> [[MUL]] 420; 421; VI-LABEL: @umul24_v2i31( 422; VI-NEXT: [[LHS24:%.*]] = and <2 x i31> [[LHS:%.*]], <i31 16777215, i31 16777215> 423; VI-NEXT: [[RHS24:%.*]] = and <2 x i31> [[RHS:%.*]], <i31 16777215, i31 16777215> 424; VI-NEXT: [[TMP1:%.*]] = extractelement <2 x i31> [[LHS24]], i64 0 425; VI-NEXT: [[TMP2:%.*]] = extractelement <2 x i31> [[LHS24]], i64 1 426; VI-NEXT: [[TMP3:%.*]] = extractelement <2 x i31> [[RHS24]], i64 0 427; VI-NEXT: [[TMP4:%.*]] = extractelement <2 x i31> [[RHS24]], i64 1 428; VI-NEXT: [[TMP5:%.*]] = zext i31 [[TMP1]] to i32 429; VI-NEXT: [[TMP6:%.*]] = zext i31 [[TMP3]] to i32 430; VI-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP5]], i32 [[TMP6]]) 431; VI-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i31 432; VI-NEXT: [[TMP9:%.*]] = zext i31 [[TMP2]] to i32 433; VI-NEXT: [[TMP10:%.*]] = zext i31 [[TMP4]] to i32 434; VI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP9]], i32 [[TMP10]]) 435; VI-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i31 436; VI-NEXT: [[TMP13:%.*]] = insertelement <2 x i31> undef, i31 [[TMP8]], i64 0 437; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1 438; VI-NEXT: ret <2 x i31> [[MUL]] 439; 440; DISABLED-LABEL: @umul24_v2i31( 441; DISABLED-NEXT: [[LHS24:%.*]] = and <2 x i31> [[LHS:%.*]], <i31 16777215, i31 16777215> 442; DISABLED-NEXT: [[RHS24:%.*]] = and <2 x i31> [[RHS:%.*]], <i31 16777215, i31 16777215> 443; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i31> [[LHS24]], [[RHS24]] 444; DISABLED-NEXT: ret <2 x i31> [[MUL]] 445; 446 %lhs24 = and <2 x i31> %lhs, <i31 16777215, i31 16777215> 447 %rhs24 = and <2 x i31> %rhs, <i31 16777215, i31 16777215> 448 %mul = mul <2 x i31> %lhs24, %rhs24 449 ret <2 x i31> %mul 450} 451 452define <2 x i31> @smul24_v2i31(<2 x i31> %lhs, <2 x i31> %rhs) { 453; SI-LABEL: @smul24_v2i31( 454; SI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i31> [[LHS:%.*]], <i31 8, i31 8> 455; SI-NEXT: [[LHS24:%.*]] = ashr <2 x i31> [[SHL_LHS]], <i31 8, i31 8> 456; SI-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i31> [[RHS:%.*]], <i31 8, i31 8> 457; SI-NEXT: [[RHS24:%.*]] = ashr <2 x i31> [[LHS]], <i31 8, i31 8> 458; SI-NEXT: [[TMP1:%.*]] = extractelement <2 x i31> [[LHS24]], i64 0 459; SI-NEXT: [[TMP2:%.*]] = extractelement <2 x i31> [[LHS24]], i64 1 460; SI-NEXT: [[TMP3:%.*]] = extractelement <2 x i31> [[RHS24]], i64 0 461; SI-NEXT: [[TMP4:%.*]] = extractelement <2 x i31> [[RHS24]], i64 1 462; SI-NEXT: [[TMP5:%.*]] = sext i31 [[TMP1]] to i32 463; SI-NEXT: [[TMP6:%.*]] = sext i31 [[TMP3]] to i32 464; SI-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP5]], i32 [[TMP6]]) 465; SI-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i31 466; SI-NEXT: [[TMP9:%.*]] = sext i31 [[TMP2]] to i32 467; SI-NEXT: [[TMP10:%.*]] = sext i31 [[TMP4]] to i32 468; SI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP9]], i32 [[TMP10]]) 469; SI-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i31 470; SI-NEXT: [[TMP13:%.*]] = insertelement <2 x i31> undef, i31 [[TMP8]], i64 0 471; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1 472; SI-NEXT: ret <2 x i31> [[MUL]] 473; 474; VI-LABEL: @smul24_v2i31( 475; VI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i31> [[LHS:%.*]], <i31 8, i31 8> 476; VI-NEXT: [[LHS24:%.*]] = ashr <2 x i31> [[SHL_LHS]], <i31 8, i31 8> 477; VI-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i31> [[RHS:%.*]], <i31 8, i31 8> 478; VI-NEXT: [[RHS24:%.*]] = ashr <2 x i31> [[LHS]], <i31 8, i31 8> 479; VI-NEXT: [[TMP1:%.*]] = extractelement <2 x i31> [[LHS24]], i64 0 480; VI-NEXT: [[TMP2:%.*]] = extractelement <2 x i31> [[LHS24]], i64 1 481; VI-NEXT: [[TMP3:%.*]] = extractelement <2 x i31> [[RHS24]], i64 0 482; VI-NEXT: [[TMP4:%.*]] = extractelement <2 x i31> [[RHS24]], i64 1 483; VI-NEXT: [[TMP5:%.*]] = sext i31 [[TMP1]] to i32 484; VI-NEXT: [[TMP6:%.*]] = sext i31 [[TMP3]] to i32 485; VI-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP5]], i32 [[TMP6]]) 486; VI-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i31 487; VI-NEXT: [[TMP9:%.*]] = sext i31 [[TMP2]] to i32 488; VI-NEXT: [[TMP10:%.*]] = sext i31 [[TMP4]] to i32 489; VI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP9]], i32 [[TMP10]]) 490; VI-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i31 491; VI-NEXT: [[TMP13:%.*]] = insertelement <2 x i31> undef, i31 [[TMP8]], i64 0 492; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1 493; VI-NEXT: ret <2 x i31> [[MUL]] 494; 495; DISABLED-LABEL: @smul24_v2i31( 496; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl <2 x i31> [[LHS:%.*]], <i31 8, i31 8> 497; DISABLED-NEXT: [[LHS24:%.*]] = ashr <2 x i31> [[SHL_LHS]], <i31 8, i31 8> 498; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i31> [[RHS:%.*]], <i31 8, i31 8> 499; DISABLED-NEXT: [[RHS24:%.*]] = ashr <2 x i31> [[LHS]], <i31 8, i31 8> 500; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i31> [[LHS24]], [[RHS24]] 501; DISABLED-NEXT: ret <2 x i31> [[MUL]] 502; 503 %shl.lhs = shl <2 x i31> %lhs, <i31 8, i31 8> 504 %lhs24 = ashr <2 x i31> %shl.lhs, <i31 8, i31 8> 505 %lshr.rhs = shl <2 x i31> %rhs, <i31 8, i31 8> 506 %rhs24 = ashr <2 x i31> %lhs, <i31 8, i31 8> 507 %mul = mul <2 x i31> %lhs24, %rhs24 508 ret <2 x i31> %mul 509} 510 511define i33 @smul24_i33(i33 %lhs, i33 %rhs) { 512; SI-LABEL: @smul24_i33( 513; SI-NEXT: [[SHL_LHS:%.*]] = shl i33 [[LHS:%.*]], 9 514; SI-NEXT: [[LHS24:%.*]] = ashr i33 [[SHL_LHS]], 9 515; SI-NEXT: [[LSHR_RHS:%.*]] = shl i33 [[RHS:%.*]], 9 516; SI-NEXT: [[RHS24:%.*]] = ashr i33 [[LHS]], 9 517; SI-NEXT: [[MUL:%.*]] = mul i33 [[LHS24]], [[RHS24]] 518; SI-NEXT: ret i33 [[MUL]] 519; 520; VI-LABEL: @smul24_i33( 521; VI-NEXT: [[SHL_LHS:%.*]] = shl i33 [[LHS:%.*]], 9 522; VI-NEXT: [[LHS24:%.*]] = ashr i33 [[SHL_LHS]], 9 523; VI-NEXT: [[LSHR_RHS:%.*]] = shl i33 [[RHS:%.*]], 9 524; VI-NEXT: [[RHS24:%.*]] = ashr i33 [[LHS]], 9 525; VI-NEXT: [[MUL:%.*]] = mul i33 [[LHS24]], [[RHS24]] 526; VI-NEXT: ret i33 [[MUL]] 527; 528; DISABLED-LABEL: @smul24_i33( 529; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i33 [[LHS:%.*]], 9 530; DISABLED-NEXT: [[LHS24:%.*]] = ashr i33 [[SHL_LHS]], 9 531; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl i33 [[RHS:%.*]], 9 532; DISABLED-NEXT: [[RHS24:%.*]] = ashr i33 [[LHS]], 9 533; DISABLED-NEXT: [[MUL:%.*]] = mul i33 [[LHS24]], [[RHS24]] 534; DISABLED-NEXT: ret i33 [[MUL]] 535; 536 %shl.lhs = shl i33 %lhs, 9 537 %lhs24 = ashr i33 %shl.lhs, 9 538 %lshr.rhs = shl i33 %rhs, 9 539 %rhs24 = ashr i33 %lhs, 9 540 %mul = mul i33 %lhs24, %rhs24 541 ret i33 %mul 542} 543 544define i33 @umul24_i33(i33 %lhs, i33 %rhs) { 545; SI-LABEL: @umul24_i33( 546; SI-NEXT: [[LHS24:%.*]] = and i33 [[LHS:%.*]], 16777215 547; SI-NEXT: [[RHS24:%.*]] = and i33 [[RHS:%.*]], 16777215 548; SI-NEXT: [[MUL:%.*]] = mul i33 [[LHS24]], [[RHS24]] 549; SI-NEXT: ret i33 [[MUL]] 550; 551; VI-LABEL: @umul24_i33( 552; VI-NEXT: [[LHS24:%.*]] = and i33 [[LHS:%.*]], 16777215 553; VI-NEXT: [[RHS24:%.*]] = and i33 [[RHS:%.*]], 16777215 554; VI-NEXT: [[MUL:%.*]] = mul i33 [[LHS24]], [[RHS24]] 555; VI-NEXT: ret i33 [[MUL]] 556; 557; DISABLED-LABEL: @umul24_i33( 558; DISABLED-NEXT: [[LHS24:%.*]] = and i33 [[LHS:%.*]], 16777215 559; DISABLED-NEXT: [[RHS24:%.*]] = and i33 [[RHS:%.*]], 16777215 560; DISABLED-NEXT: [[MUL:%.*]] = mul i33 [[LHS24]], [[RHS24]] 561; DISABLED-NEXT: ret i33 [[MUL]] 562; 563 %lhs24 = and i33 %lhs, 16777215 564 %rhs24 = and i33 %rhs, 16777215 565 %mul = mul i33 %lhs24, %rhs24 566 ret i33 %mul 567} 568 569define i32 @smul25_i32(i32 %lhs, i32 %rhs) { 570; SI-LABEL: @smul25_i32( 571; SI-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 7 572; SI-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 7 573; SI-NEXT: [[LSHR_RHS:%.*]] = shl i32 [[RHS:%.*]], 7 574; SI-NEXT: [[RHS24:%.*]] = ashr i32 [[LHS]], 7 575; SI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 576; SI-NEXT: ret i32 [[MUL]] 577; 578; VI-LABEL: @smul25_i32( 579; VI-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 7 580; VI-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 7 581; VI-NEXT: [[LSHR_RHS:%.*]] = shl i32 [[RHS:%.*]], 7 582; VI-NEXT: [[RHS24:%.*]] = ashr i32 [[LHS]], 7 583; VI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 584; VI-NEXT: ret i32 [[MUL]] 585; 586; DISABLED-LABEL: @smul25_i32( 587; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 7 588; DISABLED-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 7 589; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl i32 [[RHS:%.*]], 7 590; DISABLED-NEXT: [[RHS24:%.*]] = ashr i32 [[LHS]], 7 591; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 592; DISABLED-NEXT: ret i32 [[MUL]] 593; 594 %shl.lhs = shl i32 %lhs, 7 595 %lhs24 = ashr i32 %shl.lhs, 7 596 %lshr.rhs = shl i32 %rhs, 7 597 %rhs24 = ashr i32 %lhs, 7 598 %mul = mul i32 %lhs24, %rhs24 599 ret i32 %mul 600} 601 602define i32 @umul25_i32(i32 %lhs, i32 %rhs) { 603; SI-LABEL: @umul25_i32( 604; SI-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 33554431 605; SI-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 33554431 606; SI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 607; SI-NEXT: ret i32 [[MUL]] 608; 609; VI-LABEL: @umul25_i32( 610; VI-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 33554431 611; VI-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 33554431 612; VI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 613; VI-NEXT: ret i32 [[MUL]] 614; 615; DISABLED-LABEL: @umul25_i32( 616; DISABLED-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 33554431 617; DISABLED-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 33554431 618; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 619; DISABLED-NEXT: ret i32 [[MUL]] 620; 621 %lhs24 = and i32 %lhs, 33554431 622 %rhs24 = and i32 %rhs, 33554431 623 %mul = mul i32 %lhs24, %rhs24 624 ret i32 %mul 625} 626 627define <2 x i33> @smul24_v2i33(<2 x i33> %lhs, <2 x i33> %rhs) { 628; SI-LABEL: @smul24_v2i33( 629; SI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i33> [[LHS:%.*]], <i33 9, i33 9> 630; SI-NEXT: [[LHS24:%.*]] = ashr <2 x i33> [[SHL_LHS]], <i33 9, i33 9> 631; SI-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i33> [[RHS:%.*]], <i33 9, i33 9> 632; SI-NEXT: [[RHS24:%.*]] = ashr <2 x i33> [[LHS]], <i33 9, i33 9> 633; SI-NEXT: [[MUL:%.*]] = mul <2 x i33> [[LHS24]], [[RHS24]] 634; SI-NEXT: ret <2 x i33> [[MUL]] 635; 636; VI-LABEL: @smul24_v2i33( 637; VI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i33> [[LHS:%.*]], <i33 9, i33 9> 638; VI-NEXT: [[LHS24:%.*]] = ashr <2 x i33> [[SHL_LHS]], <i33 9, i33 9> 639; VI-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i33> [[RHS:%.*]], <i33 9, i33 9> 640; VI-NEXT: [[RHS24:%.*]] = ashr <2 x i33> [[LHS]], <i33 9, i33 9> 641; VI-NEXT: [[MUL:%.*]] = mul <2 x i33> [[LHS24]], [[RHS24]] 642; VI-NEXT: ret <2 x i33> [[MUL]] 643; 644; DISABLED-LABEL: @smul24_v2i33( 645; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl <2 x i33> [[LHS:%.*]], <i33 9, i33 9> 646; DISABLED-NEXT: [[LHS24:%.*]] = ashr <2 x i33> [[SHL_LHS]], <i33 9, i33 9> 647; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i33> [[RHS:%.*]], <i33 9, i33 9> 648; DISABLED-NEXT: [[RHS24:%.*]] = ashr <2 x i33> [[LHS]], <i33 9, i33 9> 649; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i33> [[LHS24]], [[RHS24]] 650; DISABLED-NEXT: ret <2 x i33> [[MUL]] 651; 652 %shl.lhs = shl <2 x i33> %lhs, <i33 9, i33 9> 653 %lhs24 = ashr <2 x i33> %shl.lhs, <i33 9, i33 9> 654 %lshr.rhs = shl <2 x i33> %rhs, <i33 9, i33 9> 655 %rhs24 = ashr <2 x i33> %lhs, <i33 9, i33 9> 656 %mul = mul <2 x i33> %lhs24, %rhs24 657 ret <2 x i33> %mul 658} 659