1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --force-update
2; RUN: opt -S -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-codegenprepare -amdgpu-bypass-slow-div=0 %s | FileCheck %s
3; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-bypass-slow-div=0 < %s | FileCheck -check-prefix=GFX6 %s
4; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -amdgpu-bypass-slow-div=0 < %s | FileCheck -check-prefix=GFX9 %s
5
6define amdgpu_kernel void @udiv_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
7; CHECK-LABEL: @udiv_i32(
8; CHECK-NEXT:    [[TMP1:%.*]] = uitofp i32 [[Y:%.*]] to float
9; CHECK-NEXT:    [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]])
10; CHECK-NEXT:    [[TMP3:%.*]] = fmul fast float [[TMP2]], 0x41EFFFFFC0000000
11; CHECK-NEXT:    [[TMP4:%.*]] = fptoui float [[TMP3]] to i32
12; CHECK-NEXT:    [[TMP5:%.*]] = sub i32 0, [[Y]]
13; CHECK-NEXT:    [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP4]]
14; CHECK-NEXT:    [[TMP7:%.*]] = zext i32 [[TMP4]] to i64
15; CHECK-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP6]] to i64
16; CHECK-NEXT:    [[TMP9:%.*]] = mul i64 [[TMP7]], [[TMP8]]
17; CHECK-NEXT:    [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
18; CHECK-NEXT:    [[TMP11:%.*]] = lshr i64 [[TMP9]], 32
19; CHECK-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
20; CHECK-NEXT:    [[TMP13:%.*]] = add i32 [[TMP4]], [[TMP12]]
21; CHECK-NEXT:    [[TMP14:%.*]] = zext i32 [[X:%.*]] to i64
22; CHECK-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP13]] to i64
23; CHECK-NEXT:    [[TMP16:%.*]] = mul i64 [[TMP14]], [[TMP15]]
24; CHECK-NEXT:    [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32
25; CHECK-NEXT:    [[TMP18:%.*]] = lshr i64 [[TMP16]], 32
26; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
27; CHECK-NEXT:    [[TMP20:%.*]] = mul i32 [[TMP19]], [[Y]]
28; CHECK-NEXT:    [[TMP21:%.*]] = sub i32 [[X]], [[TMP20]]
29; CHECK-NEXT:    [[TMP22:%.*]] = icmp uge i32 [[TMP21]], [[Y]]
30; CHECK-NEXT:    [[TMP23:%.*]] = add i32 [[TMP19]], 1
31; CHECK-NEXT:    [[TMP24:%.*]] = select i1 [[TMP22]], i32 [[TMP23]], i32 [[TMP19]]
32; CHECK-NEXT:    [[TMP25:%.*]] = sub i32 [[TMP21]], [[Y]]
33; CHECK-NEXT:    [[TMP26:%.*]] = select i1 [[TMP22]], i32 [[TMP25]], i32 [[TMP21]]
34; CHECK-NEXT:    [[TMP27:%.*]] = icmp uge i32 [[TMP26]], [[Y]]
35; CHECK-NEXT:    [[TMP28:%.*]] = add i32 [[TMP24]], 1
36; CHECK-NEXT:    [[TMP29:%.*]] = select i1 [[TMP27]], i32 [[TMP28]], i32 [[TMP24]]
37; CHECK-NEXT:    store i32 [[TMP29]], i32 addrspace(1)* [[OUT:%.*]], align 4
38; CHECK-NEXT:    ret void
39;
40; GFX6-LABEL: udiv_i32:
41; GFX6:       ; %bb.0:
42; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
43; GFX6-NEXT:    s_mov_b32 s7, 0xf000
44; GFX6-NEXT:    s_mov_b32 s6, -1
45; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
46; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s3
47; GFX6-NEXT:    s_sub_i32 s4, 0, s3
48; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
49; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
50; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
51; GFX6-NEXT:    v_mul_lo_u32 v1, s4, v0
52; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
53; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
54; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
55; GFX6-NEXT:    v_mul_hi_u32 v0, s2, v0
56; GFX6-NEXT:    v_mul_lo_u32 v1, v0, s3
57; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
58; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s2, v1
59; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v1
60; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
61; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v1
62; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[0:1]
63; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
64; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
65; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
66; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
67; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
68; GFX6-NEXT:    s_endpgm
69;
70; GFX9-LABEL: udiv_i32:
71; GFX9:       ; %bb.0:
72; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
73; GFX9-NEXT:    v_mov_b32_e32 v2, 0
74; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
75; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
76; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
77; GFX9-NEXT:    s_sub_i32 s4, 0, s3
78; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
79; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
80; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
81; GFX9-NEXT:    v_mul_lo_u32 v1, s4, v0
82; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
83; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
84; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
85; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s3
86; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
87; GFX9-NEXT:    v_sub_u32_e32 v1, s2, v1
88; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
89; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
90; GFX9-NEXT:    v_subrev_u32_e32 v3, s3, v1
91; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
92; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
93; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
94; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
95; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]
96; GFX9-NEXT:    s_endpgm
97  %r = udiv i32 %x, %y
98  store i32 %r, i32 addrspace(1)* %out
99  ret void
100}
101
102define amdgpu_kernel void @urem_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
103; CHECK-LABEL: @urem_i32(
104; CHECK-NEXT:    [[TMP1:%.*]] = uitofp i32 [[Y:%.*]] to float
105; CHECK-NEXT:    [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]])
106; CHECK-NEXT:    [[TMP3:%.*]] = fmul fast float [[TMP2]], 0x41EFFFFFC0000000
107; CHECK-NEXT:    [[TMP4:%.*]] = fptoui float [[TMP3]] to i32
108; CHECK-NEXT:    [[TMP5:%.*]] = sub i32 0, [[Y]]
109; CHECK-NEXT:    [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP4]]
110; CHECK-NEXT:    [[TMP7:%.*]] = zext i32 [[TMP4]] to i64
111; CHECK-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP6]] to i64
112; CHECK-NEXT:    [[TMP9:%.*]] = mul i64 [[TMP7]], [[TMP8]]
113; CHECK-NEXT:    [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
114; CHECK-NEXT:    [[TMP11:%.*]] = lshr i64 [[TMP9]], 32
115; CHECK-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
116; CHECK-NEXT:    [[TMP13:%.*]] = add i32 [[TMP4]], [[TMP12]]
117; CHECK-NEXT:    [[TMP14:%.*]] = zext i32 [[X:%.*]] to i64
118; CHECK-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP13]] to i64
119; CHECK-NEXT:    [[TMP16:%.*]] = mul i64 [[TMP14]], [[TMP15]]
120; CHECK-NEXT:    [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32
121; CHECK-NEXT:    [[TMP18:%.*]] = lshr i64 [[TMP16]], 32
122; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
123; CHECK-NEXT:    [[TMP20:%.*]] = mul i32 [[TMP19]], [[Y]]
124; CHECK-NEXT:    [[TMP21:%.*]] = sub i32 [[X]], [[TMP20]]
125; CHECK-NEXT:    [[TMP22:%.*]] = icmp uge i32 [[TMP21]], [[Y]]
126; CHECK-NEXT:    [[TMP23:%.*]] = sub i32 [[TMP21]], [[Y]]
127; CHECK-NEXT:    [[TMP24:%.*]] = select i1 [[TMP22]], i32 [[TMP23]], i32 [[TMP21]]
128; CHECK-NEXT:    [[TMP25:%.*]] = icmp uge i32 [[TMP24]], [[Y]]
129; CHECK-NEXT:    [[TMP26:%.*]] = sub i32 [[TMP24]], [[Y]]
130; CHECK-NEXT:    [[TMP27:%.*]] = select i1 [[TMP25]], i32 [[TMP26]], i32 [[TMP24]]
131; CHECK-NEXT:    store i32 [[TMP27]], i32 addrspace(1)* [[OUT:%.*]], align 4
132; CHECK-NEXT:    ret void
133;
134; GFX6-LABEL: urem_i32:
135; GFX6:       ; %bb.0:
136; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
137; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
138; GFX6-NEXT:    s_mov_b32 s3, 0xf000
139; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
140; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s5
141; GFX6-NEXT:    s_sub_i32 s2, 0, s5
142; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
143; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
144; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
145; GFX6-NEXT:    v_mul_lo_u32 v1, s2, v0
146; GFX6-NEXT:    s_mov_b32 s2, -1
147; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
148; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
149; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
150; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s5
151; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
152; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s5, v0
153; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s5, v0
154; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
155; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s5, v0
156; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s5, v0
157; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
158; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
159; GFX6-NEXT:    s_endpgm
160;
161; GFX9-LABEL: urem_i32:
162; GFX9:       ; %bb.0:
163; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
164; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
165; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
166; GFX9-NEXT:    s_sub_i32 s4, 0, s3
167; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
168; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
169; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
170; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
171; GFX9-NEXT:    v_mul_lo_u32 v1, s4, v0
172; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
173; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
174; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
175; GFX9-NEXT:    v_mov_b32_e32 v1, 0
176; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
177; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
178; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v0
179; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v0
180; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
181; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v0
182; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v0
183; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
184; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
185; GFX9-NEXT:    global_store_dword v1, v0, s[0:1]
186; GFX9-NEXT:    s_endpgm
187  %r = urem i32 %x, %y
188  store i32 %r, i32 addrspace(1)* %out
189  ret void
190}
191
192define amdgpu_kernel void @sdiv_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
193; CHECK-LABEL: @sdiv_i32(
194; CHECK-NEXT:    [[TMP1:%.*]] = ashr i32 [[X:%.*]], 31
195; CHECK-NEXT:    [[TMP2:%.*]] = ashr i32 [[Y:%.*]], 31
196; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
197; CHECK-NEXT:    [[TMP4:%.*]] = add i32 [[X]], [[TMP1]]
198; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[Y]], [[TMP2]]
199; CHECK-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP4]], [[TMP1]]
200; CHECK-NEXT:    [[TMP7:%.*]] = xor i32 [[TMP5]], [[TMP2]]
201; CHECK-NEXT:    [[TMP8:%.*]] = uitofp i32 [[TMP7]] to float
202; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP8]])
203; CHECK-NEXT:    [[TMP10:%.*]] = fmul fast float [[TMP9]], 0x41EFFFFFC0000000
204; CHECK-NEXT:    [[TMP11:%.*]] = fptoui float [[TMP10]] to i32
205; CHECK-NEXT:    [[TMP12:%.*]] = sub i32 0, [[TMP7]]
206; CHECK-NEXT:    [[TMP13:%.*]] = mul i32 [[TMP12]], [[TMP11]]
207; CHECK-NEXT:    [[TMP14:%.*]] = zext i32 [[TMP11]] to i64
208; CHECK-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP13]] to i64
209; CHECK-NEXT:    [[TMP16:%.*]] = mul i64 [[TMP14]], [[TMP15]]
210; CHECK-NEXT:    [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32
211; CHECK-NEXT:    [[TMP18:%.*]] = lshr i64 [[TMP16]], 32
212; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
213; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP11]], [[TMP19]]
214; CHECK-NEXT:    [[TMP21:%.*]] = zext i32 [[TMP6]] to i64
215; CHECK-NEXT:    [[TMP22:%.*]] = zext i32 [[TMP20]] to i64
216; CHECK-NEXT:    [[TMP23:%.*]] = mul i64 [[TMP21]], [[TMP22]]
217; CHECK-NEXT:    [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32
218; CHECK-NEXT:    [[TMP25:%.*]] = lshr i64 [[TMP23]], 32
219; CHECK-NEXT:    [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32
220; CHECK-NEXT:    [[TMP27:%.*]] = mul i32 [[TMP26]], [[TMP7]]
221; CHECK-NEXT:    [[TMP28:%.*]] = sub i32 [[TMP6]], [[TMP27]]
222; CHECK-NEXT:    [[TMP29:%.*]] = icmp uge i32 [[TMP28]], [[TMP7]]
223; CHECK-NEXT:    [[TMP30:%.*]] = add i32 [[TMP26]], 1
224; CHECK-NEXT:    [[TMP31:%.*]] = select i1 [[TMP29]], i32 [[TMP30]], i32 [[TMP26]]
225; CHECK-NEXT:    [[TMP32:%.*]] = sub i32 [[TMP28]], [[TMP7]]
226; CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP29]], i32 [[TMP32]], i32 [[TMP28]]
227; CHECK-NEXT:    [[TMP34:%.*]] = icmp uge i32 [[TMP33]], [[TMP7]]
228; CHECK-NEXT:    [[TMP35:%.*]] = add i32 [[TMP31]], 1
229; CHECK-NEXT:    [[TMP36:%.*]] = select i1 [[TMP34]], i32 [[TMP35]], i32 [[TMP31]]
230; CHECK-NEXT:    [[TMP37:%.*]] = xor i32 [[TMP36]], [[TMP3]]
231; CHECK-NEXT:    [[TMP38:%.*]] = sub i32 [[TMP37]], [[TMP3]]
232; CHECK-NEXT:    store i32 [[TMP38]], i32 addrspace(1)* [[OUT:%.*]], align 4
233; CHECK-NEXT:    ret void
234;
235; GFX6-LABEL: sdiv_i32:
236; GFX6:       ; %bb.0:
237; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
238; GFX6-NEXT:    s_mov_b32 s7, 0xf000
239; GFX6-NEXT:    s_mov_b32 s6, -1
240; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
241; GFX6-NEXT:    s_ashr_i32 s8, s3, 31
242; GFX6-NEXT:    s_add_i32 s3, s3, s8
243; GFX6-NEXT:    s_xor_b32 s3, s3, s8
244; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s3
245; GFX6-NEXT:    s_sub_i32 s4, 0, s3
246; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
247; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
248; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
249; GFX6-NEXT:    v_mul_lo_u32 v1, s4, v0
250; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
251; GFX6-NEXT:    s_ashr_i32 s0, s2, 31
252; GFX6-NEXT:    s_add_i32 s1, s2, s0
253; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
254; GFX6-NEXT:    s_xor_b32 s1, s1, s0
255; GFX6-NEXT:    s_xor_b32 s2, s0, s8
256; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
257; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
258; GFX6-NEXT:    v_mul_lo_u32 v1, v0, s3
259; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
260; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v1
261; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v1
262; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
263; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v1
264; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[0:1]
265; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
266; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
267; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
268; GFX6-NEXT:    v_xor_b32_e32 v0, s2, v0
269; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
270; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
271; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
272; GFX6-NEXT:    s_endpgm
273;
274; GFX9-LABEL: sdiv_i32:
275; GFX9:       ; %bb.0:
276; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
277; GFX9-NEXT:    v_mov_b32_e32 v2, 0
278; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
279; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
280; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
281; GFX9-NEXT:    s_add_i32 s3, s3, s4
282; GFX9-NEXT:    s_xor_b32 s3, s3, s4
283; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
284; GFX9-NEXT:    s_sub_i32 s5, 0, s3
285; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
286; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
287; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
288; GFX9-NEXT:    v_mul_lo_u32 v1, s5, v0
289; GFX9-NEXT:    s_ashr_i32 s5, s2, 31
290; GFX9-NEXT:    s_add_i32 s2, s2, s5
291; GFX9-NEXT:    s_xor_b32 s2, s2, s5
292; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
293; GFX9-NEXT:    s_xor_b32 s4, s5, s4
294; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
295; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
296; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s3
297; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
298; GFX9-NEXT:    v_sub_u32_e32 v1, s2, v1
299; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
300; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
301; GFX9-NEXT:    v_subrev_u32_e32 v3, s3, v1
302; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
303; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
304; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
305; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
306; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v0
307; GFX9-NEXT:    v_subrev_u32_e32 v0, s4, v0
308; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]
309; GFX9-NEXT:    s_endpgm
310  %r = sdiv i32 %x, %y
311  store i32 %r, i32 addrspace(1)* %out
312  ret void
313}
314
315define amdgpu_kernel void @srem_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
316; CHECK-LABEL: @srem_i32(
317; CHECK-NEXT:    [[TMP1:%.*]] = ashr i32 [[X:%.*]], 31
318; CHECK-NEXT:    [[TMP2:%.*]] = ashr i32 [[Y:%.*]], 31
319; CHECK-NEXT:    [[TMP3:%.*]] = add i32 [[X]], [[TMP1]]
320; CHECK-NEXT:    [[TMP4:%.*]] = add i32 [[Y]], [[TMP2]]
321; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP1]]
322; CHECK-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP4]], [[TMP2]]
323; CHECK-NEXT:    [[TMP7:%.*]] = uitofp i32 [[TMP6]] to float
324; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
325; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP8]], 0x41EFFFFFC0000000
326; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP9]] to i32
327; CHECK-NEXT:    [[TMP11:%.*]] = sub i32 0, [[TMP6]]
328; CHECK-NEXT:    [[TMP12:%.*]] = mul i32 [[TMP11]], [[TMP10]]
329; CHECK-NEXT:    [[TMP13:%.*]] = zext i32 [[TMP10]] to i64
330; CHECK-NEXT:    [[TMP14:%.*]] = zext i32 [[TMP12]] to i64
331; CHECK-NEXT:    [[TMP15:%.*]] = mul i64 [[TMP13]], [[TMP14]]
332; CHECK-NEXT:    [[TMP16:%.*]] = trunc i64 [[TMP15]] to i32
333; CHECK-NEXT:    [[TMP17:%.*]] = lshr i64 [[TMP15]], 32
334; CHECK-NEXT:    [[TMP18:%.*]] = trunc i64 [[TMP17]] to i32
335; CHECK-NEXT:    [[TMP19:%.*]] = add i32 [[TMP10]], [[TMP18]]
336; CHECK-NEXT:    [[TMP20:%.*]] = zext i32 [[TMP5]] to i64
337; CHECK-NEXT:    [[TMP21:%.*]] = zext i32 [[TMP19]] to i64
338; CHECK-NEXT:    [[TMP22:%.*]] = mul i64 [[TMP20]], [[TMP21]]
339; CHECK-NEXT:    [[TMP23:%.*]] = trunc i64 [[TMP22]] to i32
340; CHECK-NEXT:    [[TMP24:%.*]] = lshr i64 [[TMP22]], 32
341; CHECK-NEXT:    [[TMP25:%.*]] = trunc i64 [[TMP24]] to i32
342; CHECK-NEXT:    [[TMP26:%.*]] = mul i32 [[TMP25]], [[TMP6]]
343; CHECK-NEXT:    [[TMP27:%.*]] = sub i32 [[TMP5]], [[TMP26]]
344; CHECK-NEXT:    [[TMP28:%.*]] = icmp uge i32 [[TMP27]], [[TMP6]]
345; CHECK-NEXT:    [[TMP29:%.*]] = sub i32 [[TMP27]], [[TMP6]]
346; CHECK-NEXT:    [[TMP30:%.*]] = select i1 [[TMP28]], i32 [[TMP29]], i32 [[TMP27]]
347; CHECK-NEXT:    [[TMP31:%.*]] = icmp uge i32 [[TMP30]], [[TMP6]]
348; CHECK-NEXT:    [[TMP32:%.*]] = sub i32 [[TMP30]], [[TMP6]]
349; CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP31]], i32 [[TMP32]], i32 [[TMP30]]
350; CHECK-NEXT:    [[TMP34:%.*]] = xor i32 [[TMP33]], [[TMP1]]
351; CHECK-NEXT:    [[TMP35:%.*]] = sub i32 [[TMP34]], [[TMP1]]
352; CHECK-NEXT:    store i32 [[TMP35]], i32 addrspace(1)* [[OUT:%.*]], align 4
353; CHECK-NEXT:    ret void
354;
355; GFX6-LABEL: srem_i32:
356; GFX6:       ; %bb.0:
357; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
358; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
359; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
360; GFX6-NEXT:    s_ashr_i32 s4, s3, 31
361; GFX6-NEXT:    s_add_i32 s3, s3, s4
362; GFX6-NEXT:    s_xor_b32 s4, s3, s4
363; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s4
364; GFX6-NEXT:    s_sub_i32 s3, 0, s4
365; GFX6-NEXT:    s_ashr_i32 s5, s2, 31
366; GFX6-NEXT:    s_add_i32 s2, s2, s5
367; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
368; GFX6-NEXT:    s_xor_b32 s6, s2, s5
369; GFX6-NEXT:    s_mov_b32 s2, -1
370; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
371; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
372; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v0
373; GFX6-NEXT:    s_mov_b32 s3, 0xf000
374; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
375; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
376; GFX6-NEXT:    v_mul_hi_u32 v0, s6, v0
377; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s4
378; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
379; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s4, v0
380; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s4, v0
381; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
382; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s4, v0
383; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s4, v0
384; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
385; GFX6-NEXT:    v_xor_b32_e32 v0, s5, v0
386; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s5, v0
387; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
388; GFX6-NEXT:    s_endpgm
389;
390; GFX9-LABEL: srem_i32:
391; GFX9:       ; %bb.0:
392; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
393; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
394; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
395; GFX9-NEXT:    s_add_i32 s3, s3, s4
396; GFX9-NEXT:    s_xor_b32 s3, s3, s4
397; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
398; GFX9-NEXT:    s_sub_i32 s4, 0, s3
399; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
400; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
401; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
402; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
403; GFX9-NEXT:    v_mul_lo_u32 v1, s4, v0
404; GFX9-NEXT:    s_ashr_i32 s4, s2, 31
405; GFX9-NEXT:    s_add_i32 s2, s2, s4
406; GFX9-NEXT:    s_xor_b32 s2, s2, s4
407; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
408; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
409; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
410; GFX9-NEXT:    v_mov_b32_e32 v1, 0
411; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
412; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
413; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v0
414; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v0
415; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
416; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v0
417; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v0
418; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
419; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v0
420; GFX9-NEXT:    v_subrev_u32_e32 v0, s4, v0
421; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
422; GFX9-NEXT:    global_store_dword v1, v0, s[0:1]
423; GFX9-NEXT:    s_endpgm
424  %r = srem i32 %x, %y
425  store i32 %r, i32 addrspace(1)* %out
426  ret void
427}
428
429define amdgpu_kernel void @udiv_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
430; CHECK-LABEL: @udiv_i16(
431; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[X:%.*]] to i32
432; CHECK-NEXT:    [[TMP2:%.*]] = zext i16 [[Y:%.*]] to i32
433; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
434; CHECK-NEXT:    [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
435; CHECK-NEXT:    [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
436; CHECK-NEXT:    [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
437; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
438; CHECK-NEXT:    [[TMP8:%.*]] = fneg fast float [[TMP7]]
439; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
440; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
441; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
442; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
443; CHECK-NEXT:    [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
444; CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
445; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
446; CHECK-NEXT:    [[TMP16:%.*]] = and i32 [[TMP15]], 65535
447; CHECK-NEXT:    [[TMP17:%.*]] = trunc i32 [[TMP16]] to i16
448; CHECK-NEXT:    store i16 [[TMP17]], i16 addrspace(1)* [[OUT:%.*]], align 2
449; CHECK-NEXT:    ret void
450;
451; GFX6-LABEL: udiv_i16:
452; GFX6:       ; %bb.0:
453; GFX6-NEXT:    s_load_dword s2, s[0:1], 0xb
454; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
455; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
456; GFX6-NEXT:    s_lshr_b32 s3, s2, 16
457; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s3
458; GFX6-NEXT:    s_and_b32 s2, s2, 0xffff
459; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s2
460; GFX6-NEXT:    s_mov_b32 s3, 0xf000
461; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
462; GFX6-NEXT:    s_mov_b32 s2, -1
463; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
464; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
465; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v2
466; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
467; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
468; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
469; GFX6-NEXT:    buffer_store_short v0, off, s[0:3], 0
470; GFX6-NEXT:    s_endpgm
471;
472; GFX9-LABEL: udiv_i16:
473; GFX9:       ; %bb.0:
474; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
475; GFX9-NEXT:    v_mov_b32_e32 v3, 0
476; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
477; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
478; GFX9-NEXT:    s_lshr_b32 s3, s2, 16
479; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
480; GFX9-NEXT:    s_and_b32 s2, s2, 0xffff
481; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s2
482; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
483; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
484; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
485; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v2
486; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
487; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
488; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v4, vcc
489; GFX9-NEXT:    global_store_short v3, v0, s[0:1]
490; GFX9-NEXT:    s_endpgm
491  %r = udiv i16 %x, %y
492  store i16 %r, i16 addrspace(1)* %out
493  ret void
494}
495
496define amdgpu_kernel void @urem_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
497; CHECK-LABEL: @urem_i16(
498; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[X:%.*]] to i32
499; CHECK-NEXT:    [[TMP2:%.*]] = zext i16 [[Y:%.*]] to i32
500; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
501; CHECK-NEXT:    [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
502; CHECK-NEXT:    [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
503; CHECK-NEXT:    [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
504; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
505; CHECK-NEXT:    [[TMP8:%.*]] = fneg fast float [[TMP7]]
506; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
507; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
508; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
509; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
510; CHECK-NEXT:    [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
511; CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
512; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
513; CHECK-NEXT:    [[TMP16:%.*]] = mul i32 [[TMP15]], [[TMP2]]
514; CHECK-NEXT:    [[TMP17:%.*]] = sub i32 [[TMP1]], [[TMP16]]
515; CHECK-NEXT:    [[TMP18:%.*]] = and i32 [[TMP17]], 65535
516; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i16
517; CHECK-NEXT:    store i16 [[TMP19]], i16 addrspace(1)* [[OUT:%.*]], align 2
518; CHECK-NEXT:    ret void
519;
520; GFX6-LABEL: urem_i16:
521; GFX6:       ; %bb.0:
522; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
523; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
524; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
525; GFX6-NEXT:    s_lshr_b32 s2, s4, 16
526; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s2
527; GFX6-NEXT:    s_and_b32 s3, s4, 0xffff
528; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s3
529; GFX6-NEXT:    s_mov_b32 s3, 0xf000
530; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
531; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
532; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
533; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v2
534; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
535; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
536; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
537; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
538; GFX6-NEXT:    s_mov_b32 s2, -1
539; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
540; GFX6-NEXT:    buffer_store_short v0, off, s[0:3], 0
541; GFX6-NEXT:    s_endpgm
542;
543; GFX9-LABEL: urem_i16:
544; GFX9:       ; %bb.0:
545; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
546; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
547; GFX9-NEXT:    s_lshr_b32 s3, s2, 16
548; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
549; GFX9-NEXT:    s_and_b32 s4, s2, 0xffff
550; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s4
551; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
552; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
553; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
554; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
555; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v2
556; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
557; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
558; GFX9-NEXT:    v_mov_b32_e32 v1, 0
559; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
560; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
561; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
562; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
563; GFX9-NEXT:    global_store_short v1, v0, s[0:1]
564; GFX9-NEXT:    s_endpgm
565  %r = urem i16 %x, %y
566  store i16 %r, i16 addrspace(1)* %out
567  ret void
568}
569
570define amdgpu_kernel void @sdiv_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
571; CHECK-LABEL: @sdiv_i16(
572; CHECK-NEXT:    [[TMP1:%.*]] = sext i16 [[X:%.*]] to i32
573; CHECK-NEXT:    [[TMP2:%.*]] = sext i16 [[Y:%.*]] to i32
574; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
575; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
576; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP4]], 1
577; CHECK-NEXT:    [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
578; CHECK-NEXT:    [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
579; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
580; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
581; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
582; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
583; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
584; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
585; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
586; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
587; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
588; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
589; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
590; CHECK-NEXT:    [[TMP19:%.*]] = shl i32 [[TMP18]], 16
591; CHECK-NEXT:    [[TMP20:%.*]] = ashr i32 [[TMP19]], 16
592; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i16
593; CHECK-NEXT:    store i16 [[TMP21]], i16 addrspace(1)* [[OUT:%.*]], align 2
594; CHECK-NEXT:    ret void
595;
596; GFX6-LABEL: sdiv_i16:
597; GFX6:       ; %bb.0:
598; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
599; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
600; GFX6-NEXT:    s_mov_b32 s3, 0xf000
601; GFX6-NEXT:    s_mov_b32 s2, -1
602; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
603; GFX6-NEXT:    s_ashr_i32 s5, s4, 16
604; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s5
605; GFX6-NEXT:    s_sext_i32_i16 s4, s4
606; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s4
607; GFX6-NEXT:    s_xor_b32 s4, s4, s5
608; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
609; GFX6-NEXT:    s_ashr_i32 s4, s4, 30
610; GFX6-NEXT:    s_or_b32 s4, s4, 1
611; GFX6-NEXT:    v_mov_b32_e32 v3, s4
612; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
613; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
614; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
615; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
616; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
617; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
618; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
619; GFX6-NEXT:    buffer_store_short v0, off, s[0:3], 0
620; GFX6-NEXT:    s_endpgm
621;
622; GFX9-LABEL: sdiv_i16:
623; GFX9:       ; %bb.0:
624; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
625; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
626; GFX9-NEXT:    v_mov_b32_e32 v1, 0
627; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
628; GFX9-NEXT:    s_ashr_i32 s0, s4, 16
629; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s0
630; GFX9-NEXT:    s_sext_i32_i16 s1, s4
631; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s1
632; GFX9-NEXT:    s_xor_b32 s0, s1, s0
633; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
634; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
635; GFX9-NEXT:    s_or_b32 s4, s0, 1
636; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
637; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
638; GFX9-NEXT:    v_mad_f32 v2, -v3, v0, v2
639; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
640; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
641; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
642; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
643; GFX9-NEXT:    v_add_u32_e32 v0, s0, v3
644; GFX9-NEXT:    global_store_short v1, v0, s[2:3]
645; GFX9-NEXT:    s_endpgm
646  %r = sdiv i16 %x, %y
647  store i16 %r, i16 addrspace(1)* %out
648  ret void
649}
650
651define amdgpu_kernel void @srem_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
652; CHECK-LABEL: @srem_i16(
653; CHECK-NEXT:    [[TMP1:%.*]] = sext i16 [[X:%.*]] to i32
654; CHECK-NEXT:    [[TMP2:%.*]] = sext i16 [[Y:%.*]] to i32
655; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
656; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
657; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP4]], 1
658; CHECK-NEXT:    [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
659; CHECK-NEXT:    [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
660; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
661; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
662; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
663; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
664; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
665; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
666; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
667; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
668; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
669; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
670; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
671; CHECK-NEXT:    [[TMP19:%.*]] = mul i32 [[TMP18]], [[TMP2]]
672; CHECK-NEXT:    [[TMP20:%.*]] = sub i32 [[TMP1]], [[TMP19]]
673; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 16
674; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 16
675; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i16
676; CHECK-NEXT:    store i16 [[TMP23]], i16 addrspace(1)* [[OUT:%.*]], align 2
677; CHECK-NEXT:    ret void
678;
679; GFX6-LABEL: srem_i16:
680; GFX6:       ; %bb.0:
681; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
682; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
683; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
684; GFX6-NEXT:    s_ashr_i32 s2, s4, 16
685; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s2
686; GFX6-NEXT:    s_sext_i32_i16 s3, s4
687; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s3
688; GFX6-NEXT:    s_xor_b32 s3, s3, s2
689; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
690; GFX6-NEXT:    s_ashr_i32 s3, s3, 30
691; GFX6-NEXT:    s_or_b32 s3, s3, 1
692; GFX6-NEXT:    v_mov_b32_e32 v3, s3
693; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
694; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
695; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
696; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
697; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
698; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
699; GFX6-NEXT:    s_mov_b32 s3, 0xf000
700; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
701; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
702; GFX6-NEXT:    s_mov_b32 s2, -1
703; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
704; GFX6-NEXT:    buffer_store_short v0, off, s[0:3], 0
705; GFX6-NEXT:    s_endpgm
706;
707; GFX9-LABEL: srem_i16:
708; GFX9:       ; %bb.0:
709; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
710; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
711; GFX9-NEXT:    s_ashr_i32 s5, s4, 16
712; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s5
713; GFX9-NEXT:    s_sext_i32_i16 s2, s4
714; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s2
715; GFX9-NEXT:    s_xor_b32 s2, s2, s5
716; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
717; GFX9-NEXT:    s_ashr_i32 s2, s2, 30
718; GFX9-NEXT:    s_or_b32 s6, s2, 1
719; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
720; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
721; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
722; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
723; GFX9-NEXT:    v_cvt_i32_f32_e32 v2, v2
724; GFX9-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|
725; GFX9-NEXT:    s_and_b64 s[2:3], s[2:3], exec
726; GFX9-NEXT:    s_cselect_b32 s2, s6, 0
727; GFX9-NEXT:    v_add_u32_e32 v0, s2, v2
728; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s5
729; GFX9-NEXT:    v_mov_b32_e32 v1, 0
730; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
731; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
732; GFX9-NEXT:    global_store_short v1, v0, s[0:1]
733; GFX9-NEXT:    s_endpgm
734  %r = srem i16 %x, %y
735  store i16 %r, i16 addrspace(1)* %out
736  ret void
737}
738
739define amdgpu_kernel void @udiv_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
740; CHECK-LABEL: @udiv_i8(
741; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[X:%.*]] to i32
742; CHECK-NEXT:    [[TMP2:%.*]] = zext i8 [[Y:%.*]] to i32
743; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
744; CHECK-NEXT:    [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
745; CHECK-NEXT:    [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
746; CHECK-NEXT:    [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
747; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
748; CHECK-NEXT:    [[TMP8:%.*]] = fneg fast float [[TMP7]]
749; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
750; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
751; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
752; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
753; CHECK-NEXT:    [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
754; CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
755; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
756; CHECK-NEXT:    [[TMP16:%.*]] = and i32 [[TMP15]], 255
757; CHECK-NEXT:    [[TMP17:%.*]] = trunc i32 [[TMP16]] to i8
758; CHECK-NEXT:    store i8 [[TMP17]], i8 addrspace(1)* [[OUT:%.*]], align 1
759; CHECK-NEXT:    ret void
760;
761; GFX6-LABEL: udiv_i8:
762; GFX6:       ; %bb.0:
763; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
764; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
765; GFX6-NEXT:    s_mov_b32 s3, 0xf000
766; GFX6-NEXT:    s_mov_b32 s2, -1
767; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
768; GFX6-NEXT:    v_cvt_f32_ubyte1_e32 v0, s4
769; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v0
770; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v2, s4
771; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1
772; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
773; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v1
774; GFX6-NEXT:    v_mad_f32 v1, -v1, v0, v2
775; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
776; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
777; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
778; GFX6-NEXT:    s_endpgm
779;
780; GFX9-LABEL: udiv_i8:
781; GFX9:       ; %bb.0:
782; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
783; GFX9-NEXT:    v_mov_b32_e32 v2, 0
784; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
785; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
786; GFX9-NEXT:    v_cvt_f32_ubyte1_e32 v0, s2
787; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
788; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v3, s2
789; GFX9-NEXT:    v_mul_f32_e32 v1, v3, v1
790; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
791; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v1
792; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v3
793; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
794; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v4, vcc
795; GFX9-NEXT:    global_store_byte v2, v0, s[0:1]
796; GFX9-NEXT:    s_endpgm
797  %r = udiv i8 %x, %y
798  store i8 %r, i8 addrspace(1)* %out
799  ret void
800}
801
802define amdgpu_kernel void @urem_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
803; CHECK-LABEL: @urem_i8(
804; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[X:%.*]] to i32
805; CHECK-NEXT:    [[TMP2:%.*]] = zext i8 [[Y:%.*]] to i32
806; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
807; CHECK-NEXT:    [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
808; CHECK-NEXT:    [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
809; CHECK-NEXT:    [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
810; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
811; CHECK-NEXT:    [[TMP8:%.*]] = fneg fast float [[TMP7]]
812; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
813; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
814; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
815; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
816; CHECK-NEXT:    [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
817; CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
818; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
819; CHECK-NEXT:    [[TMP16:%.*]] = mul i32 [[TMP15]], [[TMP2]]
820; CHECK-NEXT:    [[TMP17:%.*]] = sub i32 [[TMP1]], [[TMP16]]
821; CHECK-NEXT:    [[TMP18:%.*]] = and i32 [[TMP17]], 255
822; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i8
823; CHECK-NEXT:    store i8 [[TMP19]], i8 addrspace(1)* [[OUT:%.*]], align 1
824; CHECK-NEXT:    ret void
825;
826; GFX6-LABEL: urem_i8:
827; GFX6:       ; %bb.0:
828; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
829; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
830; GFX6-NEXT:    s_mov_b32 s3, 0xf000
831; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
832; GFX6-NEXT:    v_cvt_f32_ubyte1_e32 v0, s4
833; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v0
834; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v2, s4
835; GFX6-NEXT:    s_lshr_b32 s2, s4, 8
836; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1
837; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
838; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v1
839; GFX6-NEXT:    v_mad_f32 v1, -v1, v0, v2
840; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
841; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
842; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
843; GFX6-NEXT:    s_mov_b32 s2, -1
844; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
845; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
846; GFX6-NEXT:    s_endpgm
847;
848; GFX9-LABEL: urem_i8:
849; GFX9:       ; %bb.0:
850; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
851; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
852; GFX9-NEXT:    v_cvt_f32_ubyte1_e32 v0, s2
853; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
854; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v2, s2
855; GFX9-NEXT:    s_lshr_b32 s3, s2, 8
856; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
857; GFX9-NEXT:    v_mul_f32_e32 v1, v2, v1
858; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
859; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v1
860; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v2
861; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
862; GFX9-NEXT:    v_mov_b32_e32 v1, 0
863; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
864; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
865; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
866; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
867; GFX9-NEXT:    global_store_byte v1, v0, s[0:1]
868; GFX9-NEXT:    s_endpgm
869  %r = urem i8 %x, %y
870  store i8 %r, i8 addrspace(1)* %out
871  ret void
872}
873
874define amdgpu_kernel void @sdiv_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
875; CHECK-LABEL: @sdiv_i8(
876; CHECK-NEXT:    [[TMP1:%.*]] = sext i8 [[X:%.*]] to i32
877; CHECK-NEXT:    [[TMP2:%.*]] = sext i8 [[Y:%.*]] to i32
878; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
879; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
880; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP4]], 1
881; CHECK-NEXT:    [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
882; CHECK-NEXT:    [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
883; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
884; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
885; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
886; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
887; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
888; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
889; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
890; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
891; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
892; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
893; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
894; CHECK-NEXT:    [[TMP19:%.*]] = shl i32 [[TMP18]], 24
895; CHECK-NEXT:    [[TMP20:%.*]] = ashr i32 [[TMP19]], 24
896; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i8
897; CHECK-NEXT:    store i8 [[TMP21]], i8 addrspace(1)* [[OUT:%.*]], align 1
898; CHECK-NEXT:    ret void
899;
900; GFX6-LABEL: sdiv_i8:
901; GFX6:       ; %bb.0:
902; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
903; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
904; GFX6-NEXT:    s_mov_b32 s3, 0xf000
905; GFX6-NEXT:    s_mov_b32 s2, -1
906; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
907; GFX6-NEXT:    s_bfe_i32 s5, s4, 0x80008
908; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s5
909; GFX6-NEXT:    s_sext_i32_i8 s4, s4
910; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s4
911; GFX6-NEXT:    s_xor_b32 s4, s4, s5
912; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
913; GFX6-NEXT:    s_ashr_i32 s4, s4, 30
914; GFX6-NEXT:    s_or_b32 s4, s4, 1
915; GFX6-NEXT:    v_mov_b32_e32 v3, s4
916; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
917; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
918; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
919; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
920; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
921; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
922; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
923; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
924; GFX6-NEXT:    s_endpgm
925;
926; GFX9-LABEL: sdiv_i8:
927; GFX9:       ; %bb.0:
928; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
929; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
930; GFX9-NEXT:    v_mov_b32_e32 v1, 0
931; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
932; GFX9-NEXT:    s_bfe_i32 s0, s4, 0x80008
933; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s0
934; GFX9-NEXT:    s_sext_i32_i8 s1, s4
935; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s1
936; GFX9-NEXT:    s_xor_b32 s0, s1, s0
937; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
938; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
939; GFX9-NEXT:    s_or_b32 s4, s0, 1
940; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
941; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
942; GFX9-NEXT:    v_mad_f32 v2, -v3, v0, v2
943; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
944; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
945; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
946; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
947; GFX9-NEXT:    v_add_u32_e32 v0, s0, v3
948; GFX9-NEXT:    global_store_byte v1, v0, s[2:3]
949; GFX9-NEXT:    s_endpgm
950  %r = sdiv i8 %x, %y
951  store i8 %r, i8 addrspace(1)* %out
952  ret void
953}
954
955define amdgpu_kernel void @srem_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
956; CHECK-LABEL: @srem_i8(
957; CHECK-NEXT:    [[TMP1:%.*]] = sext i8 [[X:%.*]] to i32
958; CHECK-NEXT:    [[TMP2:%.*]] = sext i8 [[Y:%.*]] to i32
959; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
960; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
961; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP4]], 1
962; CHECK-NEXT:    [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
963; CHECK-NEXT:    [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
964; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
965; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
966; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
967; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
968; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
969; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
970; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
971; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
972; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
973; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
974; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
975; CHECK-NEXT:    [[TMP19:%.*]] = mul i32 [[TMP18]], [[TMP2]]
976; CHECK-NEXT:    [[TMP20:%.*]] = sub i32 [[TMP1]], [[TMP19]]
977; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 24
978; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 24
979; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i8
980; CHECK-NEXT:    store i8 [[TMP23]], i8 addrspace(1)* [[OUT:%.*]], align 1
981; CHECK-NEXT:    ret void
982;
983; GFX6-LABEL: srem_i8:
984; GFX6:       ; %bb.0:
985; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
986; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
987; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
988; GFX6-NEXT:    s_bfe_i32 s2, s4, 0x80008
989; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s2
990; GFX6-NEXT:    s_sext_i32_i8 s5, s4
991; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s5
992; GFX6-NEXT:    s_xor_b32 s2, s5, s2
993; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
994; GFX6-NEXT:    s_ashr_i32 s2, s2, 30
995; GFX6-NEXT:    s_or_b32 s2, s2, 1
996; GFX6-NEXT:    v_mov_b32_e32 v3, s2
997; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
998; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
999; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
1000; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
1001; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
1002; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
1003; GFX6-NEXT:    s_lshr_b32 s3, s4, 8
1004; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1005; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s3
1006; GFX6-NEXT:    s_mov_b32 s3, 0xf000
1007; GFX6-NEXT:    s_mov_b32 s2, -1
1008; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
1009; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
1010; GFX6-NEXT:    s_endpgm
1011;
1012; GFX9-LABEL: srem_i8:
1013; GFX9:       ; %bb.0:
1014; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
1015; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
1016; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1017; GFX9-NEXT:    s_bfe_i32 s0, s4, 0x80008
1018; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s0
1019; GFX9-NEXT:    s_sext_i32_i8 s1, s4
1020; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s1
1021; GFX9-NEXT:    s_xor_b32 s0, s1, s0
1022; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
1023; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
1024; GFX9-NEXT:    s_lshr_b32 s5, s4, 8
1025; GFX9-NEXT:    s_or_b32 s6, s0, 1
1026; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
1027; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
1028; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
1029; GFX9-NEXT:    v_cvt_i32_f32_e32 v2, v2
1030; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
1031; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
1032; GFX9-NEXT:    s_cselect_b32 s0, s6, 0
1033; GFX9-NEXT:    v_add_u32_e32 v0, s0, v2
1034; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s5
1035; GFX9-NEXT:    v_mov_b32_e32 v1, 0
1036; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
1037; GFX9-NEXT:    global_store_byte v1, v0, s[2:3]
1038; GFX9-NEXT:    s_endpgm
1039  %r = srem i8 %x, %y
1040  store i8 %r, i8 addrspace(1)* %out
1041  ret void
1042}
1043
1044define amdgpu_kernel void @udiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
1045; CHECK-LABEL: @udiv_v4i32(
1046; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i64 0
1047; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 0
1048; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float
1049; CHECK-NEXT:    [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])
1050; CHECK-NEXT:    [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41EFFFFFC0000000
1051; CHECK-NEXT:    [[TMP6:%.*]] = fptoui float [[TMP5]] to i32
1052; CHECK-NEXT:    [[TMP7:%.*]] = sub i32 0, [[TMP2]]
1053; CHECK-NEXT:    [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP6]]
1054; CHECK-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP6]] to i64
1055; CHECK-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP8]] to i64
1056; CHECK-NEXT:    [[TMP11:%.*]] = mul i64 [[TMP9]], [[TMP10]]
1057; CHECK-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
1058; CHECK-NEXT:    [[TMP13:%.*]] = lshr i64 [[TMP11]], 32
1059; CHECK-NEXT:    [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32
1060; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP6]], [[TMP14]]
1061; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP1]] to i64
1062; CHECK-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP15]] to i64
1063; CHECK-NEXT:    [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]
1064; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
1065; CHECK-NEXT:    [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
1066; CHECK-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
1067; CHECK-NEXT:    [[TMP22:%.*]] = mul i32 [[TMP21]], [[TMP2]]
1068; CHECK-NEXT:    [[TMP23:%.*]] = sub i32 [[TMP1]], [[TMP22]]
1069; CHECK-NEXT:    [[TMP24:%.*]] = icmp uge i32 [[TMP23]], [[TMP2]]
1070; CHECK-NEXT:    [[TMP25:%.*]] = add i32 [[TMP21]], 1
1071; CHECK-NEXT:    [[TMP26:%.*]] = select i1 [[TMP24]], i32 [[TMP25]], i32 [[TMP21]]
1072; CHECK-NEXT:    [[TMP27:%.*]] = sub i32 [[TMP23]], [[TMP2]]
1073; CHECK-NEXT:    [[TMP28:%.*]] = select i1 [[TMP24]], i32 [[TMP27]], i32 [[TMP23]]
1074; CHECK-NEXT:    [[TMP29:%.*]] = icmp uge i32 [[TMP28]], [[TMP2]]
1075; CHECK-NEXT:    [[TMP30:%.*]] = add i32 [[TMP26]], 1
1076; CHECK-NEXT:    [[TMP31:%.*]] = select i1 [[TMP29]], i32 [[TMP30]], i32 [[TMP26]]
1077; CHECK-NEXT:    [[TMP32:%.*]] = insertelement <4 x i32> undef, i32 [[TMP31]], i64 0
1078; CHECK-NEXT:    [[TMP33:%.*]] = extractelement <4 x i32> [[X]], i64 1
1079; CHECK-NEXT:    [[TMP34:%.*]] = extractelement <4 x i32> [[Y]], i64 1
1080; CHECK-NEXT:    [[TMP35:%.*]] = uitofp i32 [[TMP34]] to float
1081; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])
1082; CHECK-NEXT:    [[TMP37:%.*]] = fmul fast float [[TMP36]], 0x41EFFFFFC0000000
1083; CHECK-NEXT:    [[TMP38:%.*]] = fptoui float [[TMP37]] to i32
1084; CHECK-NEXT:    [[TMP39:%.*]] = sub i32 0, [[TMP34]]
1085; CHECK-NEXT:    [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP38]]
1086; CHECK-NEXT:    [[TMP41:%.*]] = zext i32 [[TMP38]] to i64
1087; CHECK-NEXT:    [[TMP42:%.*]] = zext i32 [[TMP40]] to i64
1088; CHECK-NEXT:    [[TMP43:%.*]] = mul i64 [[TMP41]], [[TMP42]]
1089; CHECK-NEXT:    [[TMP44:%.*]] = trunc i64 [[TMP43]] to i32
1090; CHECK-NEXT:    [[TMP45:%.*]] = lshr i64 [[TMP43]], 32
1091; CHECK-NEXT:    [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32
1092; CHECK-NEXT:    [[TMP47:%.*]] = add i32 [[TMP38]], [[TMP46]]
1093; CHECK-NEXT:    [[TMP48:%.*]] = zext i32 [[TMP33]] to i64
1094; CHECK-NEXT:    [[TMP49:%.*]] = zext i32 [[TMP47]] to i64
1095; CHECK-NEXT:    [[TMP50:%.*]] = mul i64 [[TMP48]], [[TMP49]]
1096; CHECK-NEXT:    [[TMP51:%.*]] = trunc i64 [[TMP50]] to i32
1097; CHECK-NEXT:    [[TMP52:%.*]] = lshr i64 [[TMP50]], 32
1098; CHECK-NEXT:    [[TMP53:%.*]] = trunc i64 [[TMP52]] to i32
1099; CHECK-NEXT:    [[TMP54:%.*]] = mul i32 [[TMP53]], [[TMP34]]
1100; CHECK-NEXT:    [[TMP55:%.*]] = sub i32 [[TMP33]], [[TMP54]]
1101; CHECK-NEXT:    [[TMP56:%.*]] = icmp uge i32 [[TMP55]], [[TMP34]]
1102; CHECK-NEXT:    [[TMP57:%.*]] = add i32 [[TMP53]], 1
1103; CHECK-NEXT:    [[TMP58:%.*]] = select i1 [[TMP56]], i32 [[TMP57]], i32 [[TMP53]]
1104; CHECK-NEXT:    [[TMP59:%.*]] = sub i32 [[TMP55]], [[TMP34]]
1105; CHECK-NEXT:    [[TMP60:%.*]] = select i1 [[TMP56]], i32 [[TMP59]], i32 [[TMP55]]
1106; CHECK-NEXT:    [[TMP61:%.*]] = icmp uge i32 [[TMP60]], [[TMP34]]
1107; CHECK-NEXT:    [[TMP62:%.*]] = add i32 [[TMP58]], 1
1108; CHECK-NEXT:    [[TMP63:%.*]] = select i1 [[TMP61]], i32 [[TMP62]], i32 [[TMP58]]
1109; CHECK-NEXT:    [[TMP64:%.*]] = insertelement <4 x i32> [[TMP32]], i32 [[TMP63]], i64 1
1110; CHECK-NEXT:    [[TMP65:%.*]] = extractelement <4 x i32> [[X]], i64 2
1111; CHECK-NEXT:    [[TMP66:%.*]] = extractelement <4 x i32> [[Y]], i64 2
1112; CHECK-NEXT:    [[TMP67:%.*]] = uitofp i32 [[TMP66]] to float
1113; CHECK-NEXT:    [[TMP68:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP67]])
1114; CHECK-NEXT:    [[TMP69:%.*]] = fmul fast float [[TMP68]], 0x41EFFFFFC0000000
1115; CHECK-NEXT:    [[TMP70:%.*]] = fptoui float [[TMP69]] to i32
1116; CHECK-NEXT:    [[TMP71:%.*]] = sub i32 0, [[TMP66]]
1117; CHECK-NEXT:    [[TMP72:%.*]] = mul i32 [[TMP71]], [[TMP70]]
1118; CHECK-NEXT:    [[TMP73:%.*]] = zext i32 [[TMP70]] to i64
1119; CHECK-NEXT:    [[TMP74:%.*]] = zext i32 [[TMP72]] to i64
1120; CHECK-NEXT:    [[TMP75:%.*]] = mul i64 [[TMP73]], [[TMP74]]
1121; CHECK-NEXT:    [[TMP76:%.*]] = trunc i64 [[TMP75]] to i32
1122; CHECK-NEXT:    [[TMP77:%.*]] = lshr i64 [[TMP75]], 32
1123; CHECK-NEXT:    [[TMP78:%.*]] = trunc i64 [[TMP77]] to i32
1124; CHECK-NEXT:    [[TMP79:%.*]] = add i32 [[TMP70]], [[TMP78]]
1125; CHECK-NEXT:    [[TMP80:%.*]] = zext i32 [[TMP65]] to i64
1126; CHECK-NEXT:    [[TMP81:%.*]] = zext i32 [[TMP79]] to i64
1127; CHECK-NEXT:    [[TMP82:%.*]] = mul i64 [[TMP80]], [[TMP81]]
1128; CHECK-NEXT:    [[TMP83:%.*]] = trunc i64 [[TMP82]] to i32
1129; CHECK-NEXT:    [[TMP84:%.*]] = lshr i64 [[TMP82]], 32
1130; CHECK-NEXT:    [[TMP85:%.*]] = trunc i64 [[TMP84]] to i32
1131; CHECK-NEXT:    [[TMP86:%.*]] = mul i32 [[TMP85]], [[TMP66]]
1132; CHECK-NEXT:    [[TMP87:%.*]] = sub i32 [[TMP65]], [[TMP86]]
1133; CHECK-NEXT:    [[TMP88:%.*]] = icmp uge i32 [[TMP87]], [[TMP66]]
1134; CHECK-NEXT:    [[TMP89:%.*]] = add i32 [[TMP85]], 1
1135; CHECK-NEXT:    [[TMP90:%.*]] = select i1 [[TMP88]], i32 [[TMP89]], i32 [[TMP85]]
1136; CHECK-NEXT:    [[TMP91:%.*]] = sub i32 [[TMP87]], [[TMP66]]
1137; CHECK-NEXT:    [[TMP92:%.*]] = select i1 [[TMP88]], i32 [[TMP91]], i32 [[TMP87]]
1138; CHECK-NEXT:    [[TMP93:%.*]] = icmp uge i32 [[TMP92]], [[TMP66]]
1139; CHECK-NEXT:    [[TMP94:%.*]] = add i32 [[TMP90]], 1
1140; CHECK-NEXT:    [[TMP95:%.*]] = select i1 [[TMP93]], i32 [[TMP94]], i32 [[TMP90]]
1141; CHECK-NEXT:    [[TMP96:%.*]] = insertelement <4 x i32> [[TMP64]], i32 [[TMP95]], i64 2
1142; CHECK-NEXT:    [[TMP97:%.*]] = extractelement <4 x i32> [[X]], i64 3
1143; CHECK-NEXT:    [[TMP98:%.*]] = extractelement <4 x i32> [[Y]], i64 3
1144; CHECK-NEXT:    [[TMP99:%.*]] = uitofp i32 [[TMP98]] to float
1145; CHECK-NEXT:    [[TMP100:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP99]])
1146; CHECK-NEXT:    [[TMP101:%.*]] = fmul fast float [[TMP100]], 0x41EFFFFFC0000000
1147; CHECK-NEXT:    [[TMP102:%.*]] = fptoui float [[TMP101]] to i32
1148; CHECK-NEXT:    [[TMP103:%.*]] = sub i32 0, [[TMP98]]
1149; CHECK-NEXT:    [[TMP104:%.*]] = mul i32 [[TMP103]], [[TMP102]]
1150; CHECK-NEXT:    [[TMP105:%.*]] = zext i32 [[TMP102]] to i64
1151; CHECK-NEXT:    [[TMP106:%.*]] = zext i32 [[TMP104]] to i64
1152; CHECK-NEXT:    [[TMP107:%.*]] = mul i64 [[TMP105]], [[TMP106]]
1153; CHECK-NEXT:    [[TMP108:%.*]] = trunc i64 [[TMP107]] to i32
1154; CHECK-NEXT:    [[TMP109:%.*]] = lshr i64 [[TMP107]], 32
1155; CHECK-NEXT:    [[TMP110:%.*]] = trunc i64 [[TMP109]] to i32
1156; CHECK-NEXT:    [[TMP111:%.*]] = add i32 [[TMP102]], [[TMP110]]
1157; CHECK-NEXT:    [[TMP112:%.*]] = zext i32 [[TMP97]] to i64
1158; CHECK-NEXT:    [[TMP113:%.*]] = zext i32 [[TMP111]] to i64
1159; CHECK-NEXT:    [[TMP114:%.*]] = mul i64 [[TMP112]], [[TMP113]]
1160; CHECK-NEXT:    [[TMP115:%.*]] = trunc i64 [[TMP114]] to i32
1161; CHECK-NEXT:    [[TMP116:%.*]] = lshr i64 [[TMP114]], 32
1162; CHECK-NEXT:    [[TMP117:%.*]] = trunc i64 [[TMP116]] to i32
1163; CHECK-NEXT:    [[TMP118:%.*]] = mul i32 [[TMP117]], [[TMP98]]
1164; CHECK-NEXT:    [[TMP119:%.*]] = sub i32 [[TMP97]], [[TMP118]]
1165; CHECK-NEXT:    [[TMP120:%.*]] = icmp uge i32 [[TMP119]], [[TMP98]]
1166; CHECK-NEXT:    [[TMP121:%.*]] = add i32 [[TMP117]], 1
1167; CHECK-NEXT:    [[TMP122:%.*]] = select i1 [[TMP120]], i32 [[TMP121]], i32 [[TMP117]]
1168; CHECK-NEXT:    [[TMP123:%.*]] = sub i32 [[TMP119]], [[TMP98]]
1169; CHECK-NEXT:    [[TMP124:%.*]] = select i1 [[TMP120]], i32 [[TMP123]], i32 [[TMP119]]
1170; CHECK-NEXT:    [[TMP125:%.*]] = icmp uge i32 [[TMP124]], [[TMP98]]
1171; CHECK-NEXT:    [[TMP126:%.*]] = add i32 [[TMP122]], 1
1172; CHECK-NEXT:    [[TMP127:%.*]] = select i1 [[TMP125]], i32 [[TMP126]], i32 [[TMP122]]
1173; CHECK-NEXT:    [[TMP128:%.*]] = insertelement <4 x i32> [[TMP96]], i32 [[TMP127]], i64 3
1174; CHECK-NEXT:    store <4 x i32> [[TMP128]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16
1175; CHECK-NEXT:    ret void
1176;
1177; GFX6-LABEL: udiv_v4i32:
1178; GFX6:       ; %bb.0:
1179; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
1180; GFX6-NEXT:    s_mov_b32 s3, 0x4f7ffffe
1181; GFX6-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x9
1182; GFX6-NEXT:    s_mov_b32 s15, 0xf000
1183; GFX6-NEXT:    s_mov_b32 s14, -1
1184; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
1185; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
1186; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
1187; GFX6-NEXT:    s_sub_i32 s2, 0, s8
1188; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s10
1189; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1190; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1191; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s11
1192; GFX6-NEXT:    v_mul_f32_e32 v0, s3, v0
1193; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
1194; GFX6-NEXT:    v_mul_f32_e32 v1, s3, v1
1195; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
1196; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
1197; GFX6-NEXT:    s_sub_i32 s2, 0, s9
1198; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v1
1199; GFX6-NEXT:    s_sub_i32 s2, 0, s10
1200; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
1201; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
1202; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1203; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
1204; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
1205; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
1206; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s8
1207; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
1208; GFX6-NEXT:    v_mul_lo_u32 v5, v1, s9
1209; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s4, v2
1210; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v2
1211; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[0:1]
1212; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v2
1213; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
1214; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
1215; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
1216; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v4
1217; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1218; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s5, v5
1219; GFX6-NEXT:    v_mul_f32_e32 v2, s3, v2
1220; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
1221; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v1
1222; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v3
1223; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[0:1]
1224; GFX6-NEXT:    v_mul_lo_u32 v4, s2, v2
1225; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s9, v3
1226; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
1227; GFX6-NEXT:    v_mul_hi_u32 v4, v2, v4
1228; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v1
1229; GFX6-NEXT:    s_sub_i32 s0, 0, s11
1230; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
1231; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v6
1232; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
1233; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
1234; GFX6-NEXT:    v_mul_hi_u32 v2, s6, v2
1235; GFX6-NEXT:    v_mul_f32_e32 v4, s3, v4
1236; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
1237; GFX6-NEXT:    v_mul_lo_u32 v3, v2, s10
1238; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
1239; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v4
1240; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s6, v3
1241; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v3
1242; GFX6-NEXT:    v_mul_hi_u32 v5, v4, v5
1243; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v6, s[0:1]
1244; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, s10, v3
1245; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1246; GFX6-NEXT:    v_mul_hi_u32 v4, s7, v4
1247; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v6, s[0:1]
1248; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v2
1249; GFX6-NEXT:    v_mul_lo_u32 v6, v4, s11
1250; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
1251; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
1252; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
1253; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s7, v6
1254; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v3
1255; GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]
1256; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s11, v3
1257; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
1258; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
1259; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
1260; GFX6-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc
1261; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[12:15], 0
1262; GFX6-NEXT:    s_endpgm
1263;
1264; GFX9-LABEL: udiv_v4i32:
1265; GFX9:       ; %bb.0:
1266; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
1267; GFX9-NEXT:    s_mov_b32 s12, 0x4f7ffffe
1268; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
1269; GFX9-NEXT:    v_mov_b32_e32 v4, 0
1270; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1271; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
1272; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
1273; GFX9-NEXT:    s_sub_i32 s2, 0, s8
1274; GFX9-NEXT:    s_sub_i32 s3, 0, s9
1275; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1276; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1277; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s10
1278; GFX9-NEXT:    v_mul_f32_e32 v0, s12, v0
1279; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
1280; GFX9-NEXT:    v_mul_f32_e32 v1, s12, v1
1281; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
1282; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v5
1283; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v0
1284; GFX9-NEXT:    s_sub_i32 s2, 0, s10
1285; GFX9-NEXT:    v_mul_lo_u32 v3, s3, v1
1286; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
1287; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
1288; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
1289; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
1290; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
1291; GFX9-NEXT:    v_mul_f32_e32 v3, s12, v5
1292; GFX9-NEXT:    v_mul_hi_u32 v1, s5, v1
1293; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s8
1294; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, s11
1295; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
1296; GFX9-NEXT:    v_add_u32_e32 v7, 1, v0
1297; GFX9-NEXT:    v_sub_u32_e32 v5, s4, v5
1298; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v5
1299; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v7, vcc
1300; GFX9-NEXT:    v_subrev_u32_e32 v7, s8, v5
1301; GFX9-NEXT:    v_mul_lo_u32 v6, v1, s9
1302; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
1303; GFX9-NEXT:    v_add_u32_e32 v7, 1, v0
1304; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v5
1305; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v2
1306; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v7, vcc
1307; GFX9-NEXT:    v_mul_lo_u32 v7, s2, v3
1308; GFX9-NEXT:    v_sub_u32_e32 v6, s5, v6
1309; GFX9-NEXT:    v_add_u32_e32 v5, 1, v1
1310; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v6
1311; GFX9-NEXT:    v_mul_f32_e32 v2, s12, v2
1312; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
1313; GFX9-NEXT:    v_mul_hi_u32 v5, v3, v7
1314; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
1315; GFX9-NEXT:    s_sub_i32 s2, 0, s11
1316; GFX9-NEXT:    v_subrev_u32_e32 v7, s9, v6
1317; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
1318; GFX9-NEXT:    v_mul_lo_u32 v5, s2, v2
1319; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v3
1320; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc
1321; GFX9-NEXT:    v_add_u32_e32 v7, 1, v1
1322; GFX9-NEXT:    v_mul_hi_u32 v5, v2, v5
1323; GFX9-NEXT:    v_mul_lo_u32 v8, v3, s10
1324; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v6
1325; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
1326; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
1327; GFX9-NEXT:    v_mul_hi_u32 v5, s7, v2
1328; GFX9-NEXT:    v_sub_u32_e32 v6, s6, v8
1329; GFX9-NEXT:    v_add_u32_e32 v7, 1, v3
1330; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v6
1331; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v7, vcc
1332; GFX9-NEXT:    v_subrev_u32_e32 v3, s10, v6
1333; GFX9-NEXT:    v_cndmask_b32_e32 v3, v6, v3, vcc
1334; GFX9-NEXT:    v_mul_lo_u32 v6, v5, s11
1335; GFX9-NEXT:    v_add_u32_e32 v7, 1, v2
1336; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
1337; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v7, vcc
1338; GFX9-NEXT:    v_sub_u32_e32 v3, s7, v6
1339; GFX9-NEXT:    v_add_u32_e32 v6, 1, v5
1340; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
1341; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
1342; GFX9-NEXT:    v_subrev_u32_e32 v6, s11, v3
1343; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
1344; GFX9-NEXT:    v_add_u32_e32 v6, 1, v5
1345; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
1346; GFX9-NEXT:    v_cndmask_b32_e32 v3, v5, v6, vcc
1347; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
1348; GFX9-NEXT:    s_endpgm
1349  %r = udiv <4 x i32> %x, %y
1350  store <4 x i32> %r, <4 x i32> addrspace(1)* %out
1351  ret void
1352}
1353
1354define amdgpu_kernel void @urem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
1355; CHECK-LABEL: @urem_v4i32(
1356; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i64 0
1357; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 0
1358; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float
1359; CHECK-NEXT:    [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])
1360; CHECK-NEXT:    [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41EFFFFFC0000000
1361; CHECK-NEXT:    [[TMP6:%.*]] = fptoui float [[TMP5]] to i32
1362; CHECK-NEXT:    [[TMP7:%.*]] = sub i32 0, [[TMP2]]
1363; CHECK-NEXT:    [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP6]]
1364; CHECK-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP6]] to i64
1365; CHECK-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP8]] to i64
1366; CHECK-NEXT:    [[TMP11:%.*]] = mul i64 [[TMP9]], [[TMP10]]
1367; CHECK-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
1368; CHECK-NEXT:    [[TMP13:%.*]] = lshr i64 [[TMP11]], 32
1369; CHECK-NEXT:    [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32
1370; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP6]], [[TMP14]]
1371; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP1]] to i64
1372; CHECK-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP15]] to i64
1373; CHECK-NEXT:    [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]
1374; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
1375; CHECK-NEXT:    [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
1376; CHECK-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
1377; CHECK-NEXT:    [[TMP22:%.*]] = mul i32 [[TMP21]], [[TMP2]]
1378; CHECK-NEXT:    [[TMP23:%.*]] = sub i32 [[TMP1]], [[TMP22]]
1379; CHECK-NEXT:    [[TMP24:%.*]] = icmp uge i32 [[TMP23]], [[TMP2]]
1380; CHECK-NEXT:    [[TMP25:%.*]] = sub i32 [[TMP23]], [[TMP2]]
1381; CHECK-NEXT:    [[TMP26:%.*]] = select i1 [[TMP24]], i32 [[TMP25]], i32 [[TMP23]]
1382; CHECK-NEXT:    [[TMP27:%.*]] = icmp uge i32 [[TMP26]], [[TMP2]]
1383; CHECK-NEXT:    [[TMP28:%.*]] = sub i32 [[TMP26]], [[TMP2]]
1384; CHECK-NEXT:    [[TMP29:%.*]] = select i1 [[TMP27]], i32 [[TMP28]], i32 [[TMP26]]
1385; CHECK-NEXT:    [[TMP30:%.*]] = insertelement <4 x i32> undef, i32 [[TMP29]], i64 0
1386; CHECK-NEXT:    [[TMP31:%.*]] = extractelement <4 x i32> [[X]], i64 1
1387; CHECK-NEXT:    [[TMP32:%.*]] = extractelement <4 x i32> [[Y]], i64 1
1388; CHECK-NEXT:    [[TMP33:%.*]] = uitofp i32 [[TMP32]] to float
1389; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])
1390; CHECK-NEXT:    [[TMP35:%.*]] = fmul fast float [[TMP34]], 0x41EFFFFFC0000000
1391; CHECK-NEXT:    [[TMP36:%.*]] = fptoui float [[TMP35]] to i32
1392; CHECK-NEXT:    [[TMP37:%.*]] = sub i32 0, [[TMP32]]
1393; CHECK-NEXT:    [[TMP38:%.*]] = mul i32 [[TMP37]], [[TMP36]]
1394; CHECK-NEXT:    [[TMP39:%.*]] = zext i32 [[TMP36]] to i64
1395; CHECK-NEXT:    [[TMP40:%.*]] = zext i32 [[TMP38]] to i64
1396; CHECK-NEXT:    [[TMP41:%.*]] = mul i64 [[TMP39]], [[TMP40]]
1397; CHECK-NEXT:    [[TMP42:%.*]] = trunc i64 [[TMP41]] to i32
1398; CHECK-NEXT:    [[TMP43:%.*]] = lshr i64 [[TMP41]], 32
1399; CHECK-NEXT:    [[TMP44:%.*]] = trunc i64 [[TMP43]] to i32
1400; CHECK-NEXT:    [[TMP45:%.*]] = add i32 [[TMP36]], [[TMP44]]
1401; CHECK-NEXT:    [[TMP46:%.*]] = zext i32 [[TMP31]] to i64
1402; CHECK-NEXT:    [[TMP47:%.*]] = zext i32 [[TMP45]] to i64
1403; CHECK-NEXT:    [[TMP48:%.*]] = mul i64 [[TMP46]], [[TMP47]]
1404; CHECK-NEXT:    [[TMP49:%.*]] = trunc i64 [[TMP48]] to i32
1405; CHECK-NEXT:    [[TMP50:%.*]] = lshr i64 [[TMP48]], 32
1406; CHECK-NEXT:    [[TMP51:%.*]] = trunc i64 [[TMP50]] to i32
1407; CHECK-NEXT:    [[TMP52:%.*]] = mul i32 [[TMP51]], [[TMP32]]
1408; CHECK-NEXT:    [[TMP53:%.*]] = sub i32 [[TMP31]], [[TMP52]]
1409; CHECK-NEXT:    [[TMP54:%.*]] = icmp uge i32 [[TMP53]], [[TMP32]]
1410; CHECK-NEXT:    [[TMP55:%.*]] = sub i32 [[TMP53]], [[TMP32]]
1411; CHECK-NEXT:    [[TMP56:%.*]] = select i1 [[TMP54]], i32 [[TMP55]], i32 [[TMP53]]
1412; CHECK-NEXT:    [[TMP57:%.*]] = icmp uge i32 [[TMP56]], [[TMP32]]
1413; CHECK-NEXT:    [[TMP58:%.*]] = sub i32 [[TMP56]], [[TMP32]]
1414; CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP57]], i32 [[TMP58]], i32 [[TMP56]]
1415; CHECK-NEXT:    [[TMP60:%.*]] = insertelement <4 x i32> [[TMP30]], i32 [[TMP59]], i64 1
1416; CHECK-NEXT:    [[TMP61:%.*]] = extractelement <4 x i32> [[X]], i64 2
1417; CHECK-NEXT:    [[TMP62:%.*]] = extractelement <4 x i32> [[Y]], i64 2
1418; CHECK-NEXT:    [[TMP63:%.*]] = uitofp i32 [[TMP62]] to float
1419; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP63]])
1420; CHECK-NEXT:    [[TMP65:%.*]] = fmul fast float [[TMP64]], 0x41EFFFFFC0000000
1421; CHECK-NEXT:    [[TMP66:%.*]] = fptoui float [[TMP65]] to i32
1422; CHECK-NEXT:    [[TMP67:%.*]] = sub i32 0, [[TMP62]]
1423; CHECK-NEXT:    [[TMP68:%.*]] = mul i32 [[TMP67]], [[TMP66]]
1424; CHECK-NEXT:    [[TMP69:%.*]] = zext i32 [[TMP66]] to i64
1425; CHECK-NEXT:    [[TMP70:%.*]] = zext i32 [[TMP68]] to i64
1426; CHECK-NEXT:    [[TMP71:%.*]] = mul i64 [[TMP69]], [[TMP70]]
1427; CHECK-NEXT:    [[TMP72:%.*]] = trunc i64 [[TMP71]] to i32
1428; CHECK-NEXT:    [[TMP73:%.*]] = lshr i64 [[TMP71]], 32
1429; CHECK-NEXT:    [[TMP74:%.*]] = trunc i64 [[TMP73]] to i32
1430; CHECK-NEXT:    [[TMP75:%.*]] = add i32 [[TMP66]], [[TMP74]]
1431; CHECK-NEXT:    [[TMP76:%.*]] = zext i32 [[TMP61]] to i64
1432; CHECK-NEXT:    [[TMP77:%.*]] = zext i32 [[TMP75]] to i64
1433; CHECK-NEXT:    [[TMP78:%.*]] = mul i64 [[TMP76]], [[TMP77]]
1434; CHECK-NEXT:    [[TMP79:%.*]] = trunc i64 [[TMP78]] to i32
1435; CHECK-NEXT:    [[TMP80:%.*]] = lshr i64 [[TMP78]], 32
1436; CHECK-NEXT:    [[TMP81:%.*]] = trunc i64 [[TMP80]] to i32
1437; CHECK-NEXT:    [[TMP82:%.*]] = mul i32 [[TMP81]], [[TMP62]]
1438; CHECK-NEXT:    [[TMP83:%.*]] = sub i32 [[TMP61]], [[TMP82]]
1439; CHECK-NEXT:    [[TMP84:%.*]] = icmp uge i32 [[TMP83]], [[TMP62]]
1440; CHECK-NEXT:    [[TMP85:%.*]] = sub i32 [[TMP83]], [[TMP62]]
1441; CHECK-NEXT:    [[TMP86:%.*]] = select i1 [[TMP84]], i32 [[TMP85]], i32 [[TMP83]]
1442; CHECK-NEXT:    [[TMP87:%.*]] = icmp uge i32 [[TMP86]], [[TMP62]]
1443; CHECK-NEXT:    [[TMP88:%.*]] = sub i32 [[TMP86]], [[TMP62]]
1444; CHECK-NEXT:    [[TMP89:%.*]] = select i1 [[TMP87]], i32 [[TMP88]], i32 [[TMP86]]
1445; CHECK-NEXT:    [[TMP90:%.*]] = insertelement <4 x i32> [[TMP60]], i32 [[TMP89]], i64 2
1446; CHECK-NEXT:    [[TMP91:%.*]] = extractelement <4 x i32> [[X]], i64 3
1447; CHECK-NEXT:    [[TMP92:%.*]] = extractelement <4 x i32> [[Y]], i64 3
1448; CHECK-NEXT:    [[TMP93:%.*]] = uitofp i32 [[TMP92]] to float
1449; CHECK-NEXT:    [[TMP94:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP93]])
1450; CHECK-NEXT:    [[TMP95:%.*]] = fmul fast float [[TMP94]], 0x41EFFFFFC0000000
1451; CHECK-NEXT:    [[TMP96:%.*]] = fptoui float [[TMP95]] to i32
1452; CHECK-NEXT:    [[TMP97:%.*]] = sub i32 0, [[TMP92]]
1453; CHECK-NEXT:    [[TMP98:%.*]] = mul i32 [[TMP97]], [[TMP96]]
1454; CHECK-NEXT:    [[TMP99:%.*]] = zext i32 [[TMP96]] to i64
1455; CHECK-NEXT:    [[TMP100:%.*]] = zext i32 [[TMP98]] to i64
1456; CHECK-NEXT:    [[TMP101:%.*]] = mul i64 [[TMP99]], [[TMP100]]
1457; CHECK-NEXT:    [[TMP102:%.*]] = trunc i64 [[TMP101]] to i32
1458; CHECK-NEXT:    [[TMP103:%.*]] = lshr i64 [[TMP101]], 32
1459; CHECK-NEXT:    [[TMP104:%.*]] = trunc i64 [[TMP103]] to i32
1460; CHECK-NEXT:    [[TMP105:%.*]] = add i32 [[TMP96]], [[TMP104]]
1461; CHECK-NEXT:    [[TMP106:%.*]] = zext i32 [[TMP91]] to i64
1462; CHECK-NEXT:    [[TMP107:%.*]] = zext i32 [[TMP105]] to i64
1463; CHECK-NEXT:    [[TMP108:%.*]] = mul i64 [[TMP106]], [[TMP107]]
1464; CHECK-NEXT:    [[TMP109:%.*]] = trunc i64 [[TMP108]] to i32
1465; CHECK-NEXT:    [[TMP110:%.*]] = lshr i64 [[TMP108]], 32
1466; CHECK-NEXT:    [[TMP111:%.*]] = trunc i64 [[TMP110]] to i32
1467; CHECK-NEXT:    [[TMP112:%.*]] = mul i32 [[TMP111]], [[TMP92]]
1468; CHECK-NEXT:    [[TMP113:%.*]] = sub i32 [[TMP91]], [[TMP112]]
1469; CHECK-NEXT:    [[TMP114:%.*]] = icmp uge i32 [[TMP113]], [[TMP92]]
1470; CHECK-NEXT:    [[TMP115:%.*]] = sub i32 [[TMP113]], [[TMP92]]
1471; CHECK-NEXT:    [[TMP116:%.*]] = select i1 [[TMP114]], i32 [[TMP115]], i32 [[TMP113]]
1472; CHECK-NEXT:    [[TMP117:%.*]] = icmp uge i32 [[TMP116]], [[TMP92]]
1473; CHECK-NEXT:    [[TMP118:%.*]] = sub i32 [[TMP116]], [[TMP92]]
1474; CHECK-NEXT:    [[TMP119:%.*]] = select i1 [[TMP117]], i32 [[TMP118]], i32 [[TMP116]]
1475; CHECK-NEXT:    [[TMP120:%.*]] = insertelement <4 x i32> [[TMP90]], i32 [[TMP119]], i64 3
1476; CHECK-NEXT:    store <4 x i32> [[TMP120]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16
1477; CHECK-NEXT:    ret void
1478;
1479; GFX6-LABEL: urem_v4i32:
1480; GFX6:       ; %bb.0:
1481; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
1482; GFX6-NEXT:    s_mov_b32 s13, 0x4f7ffffe
1483; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
1484; GFX6-NEXT:    s_mov_b32 s3, 0xf000
1485; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
1486; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
1487; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
1488; GFX6-NEXT:    s_sub_i32 s2, 0, s8
1489; GFX6-NEXT:    s_sub_i32 s12, 0, s9
1490; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1491; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1492; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s10
1493; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s11
1494; GFX6-NEXT:    v_mul_f32_e32 v0, s13, v0
1495; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
1496; GFX6-NEXT:    v_mul_f32_e32 v1, s13, v1
1497; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
1498; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1499; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
1500; GFX6-NEXT:    s_mov_b32 s2, -1
1501; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v1
1502; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
1503; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
1504; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1505; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
1506; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
1507; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
1508; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s8
1509; GFX6-NEXT:    v_mul_f32_e32 v2, s13, v3
1510; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
1511; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s9
1512; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
1513; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v0
1514; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1515; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1516; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v0
1517; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1518; GFX6-NEXT:    s_sub_i32 s4, 0, s10
1519; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1520; GFX6-NEXT:    v_mul_lo_u32 v3, s4, v2
1521; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
1522; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s9, v1
1523; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1524; GFX6-NEXT:    v_mul_hi_u32 v3, v2, v3
1525; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
1526; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v5
1527; GFX6-NEXT:    s_sub_i32 s4, 0, s11
1528; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1529; GFX6-NEXT:    v_mul_f32_e32 v3, s13, v4
1530; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
1531; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s9, v1
1532; GFX6-NEXT:    v_mul_hi_u32 v2, s6, v2
1533; GFX6-NEXT:    v_mul_lo_u32 v5, s4, v3
1534; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1535; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
1536; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s10
1537; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v5
1538; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s6, v2
1539; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1540; GFX6-NEXT:    v_mul_hi_u32 v3, s7, v3
1541; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s10, v2
1542; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
1543; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s11
1544; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
1545; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s10, v2
1546; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
1547; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
1548; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s7, v3
1549; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s11, v3
1550; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
1551; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
1552; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s11, v3
1553; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
1554; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
1555; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1556; GFX6-NEXT:    s_endpgm
1557;
1558; GFX9-LABEL: urem_v4i32:
1559; GFX9:       ; %bb.0:
1560; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
1561; GFX9-NEXT:    s_mov_b32 s12, 0x4f7ffffe
1562; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
1563; GFX9-NEXT:    v_mov_b32_e32 v4, 0
1564; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1565; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
1566; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
1567; GFX9-NEXT:    s_sub_i32 s2, 0, s8
1568; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s10
1569; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1570; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1571; GFX9-NEXT:    s_sub_i32 s3, 0, s9
1572; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v5
1573; GFX9-NEXT:    v_mul_f32_e32 v0, s12, v0
1574; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
1575; GFX9-NEXT:    v_mul_f32_e32 v1, s12, v1
1576; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
1577; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s11
1578; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v0
1579; GFX9-NEXT:    s_sub_i32 s2, 0, s10
1580; GFX9-NEXT:    v_mul_lo_u32 v3, s3, v1
1581; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
1582; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
1583; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
1584; GFX9-NEXT:    v_mul_f32_e32 v2, s12, v5
1585; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
1586; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
1587; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v6
1588; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
1589; GFX9-NEXT:    v_mul_lo_u32 v5, s2, v2
1590; GFX9-NEXT:    s_sub_i32 s2, 0, s11
1591; GFX9-NEXT:    v_mul_f32_e32 v3, s12, v3
1592; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
1593; GFX9-NEXT:    v_mul_hi_u32 v5, v2, v5
1594; GFX9-NEXT:    v_mul_hi_u32 v1, s5, v1
1595; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s8
1596; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
1597; GFX9-NEXT:    v_mul_lo_u32 v5, s2, v3
1598; GFX9-NEXT:    v_mul_hi_u32 v2, s6, v2
1599; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s9
1600; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
1601; GFX9-NEXT:    v_mul_hi_u32 v5, v3, v5
1602; GFX9-NEXT:    v_subrev_u32_e32 v6, s8, v0
1603; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1604; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
1605; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
1606; GFX9-NEXT:    v_mul_hi_u32 v3, s7, v3
1607; GFX9-NEXT:    v_mul_lo_u32 v2, v2, s10
1608; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v1
1609; GFX9-NEXT:    v_subrev_u32_e32 v6, s8, v0
1610; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1611; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
1612; GFX9-NEXT:    v_subrev_u32_e32 v6, s9, v1
1613; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1614; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc
1615; GFX9-NEXT:    v_mul_lo_u32 v3, v3, s11
1616; GFX9-NEXT:    v_subrev_u32_e32 v6, s9, v1
1617; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1618; GFX9-NEXT:    v_sub_u32_e32 v2, s6, v2
1619; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc
1620; GFX9-NEXT:    v_subrev_u32_e32 v5, s10, v2
1621; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
1622; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
1623; GFX9-NEXT:    v_subrev_u32_e32 v5, s10, v2
1624; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
1625; GFX9-NEXT:    v_sub_u32_e32 v3, s7, v3
1626; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
1627; GFX9-NEXT:    v_subrev_u32_e32 v5, s11, v3
1628; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
1629; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
1630; GFX9-NEXT:    v_subrev_u32_e32 v5, s11, v3
1631; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
1632; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
1633; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
1634; GFX9-NEXT:    s_endpgm
1635  %r = urem <4 x i32> %x, %y
1636  store <4 x i32> %r, <4 x i32> addrspace(1)* %out
1637  ret void
1638}
1639
1640define amdgpu_kernel void @sdiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
1641; CHECK-LABEL: @sdiv_v4i32(
1642; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i64 0
1643; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 0
1644; CHECK-NEXT:    [[TMP3:%.*]] = ashr i32 [[TMP1]], 31
1645; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP2]], 31
1646; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
1647; CHECK-NEXT:    [[TMP6:%.*]] = add i32 [[TMP1]], [[TMP3]]
1648; CHECK-NEXT:    [[TMP7:%.*]] = add i32 [[TMP2]], [[TMP4]]
1649; CHECK-NEXT:    [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP3]]
1650; CHECK-NEXT:    [[TMP9:%.*]] = xor i32 [[TMP7]], [[TMP4]]
1651; CHECK-NEXT:    [[TMP10:%.*]] = uitofp i32 [[TMP9]] to float
1652; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP10]])
1653; CHECK-NEXT:    [[TMP12:%.*]] = fmul fast float [[TMP11]], 0x41EFFFFFC0000000
1654; CHECK-NEXT:    [[TMP13:%.*]] = fptoui float [[TMP12]] to i32
1655; CHECK-NEXT:    [[TMP14:%.*]] = sub i32 0, [[TMP9]]
1656; CHECK-NEXT:    [[TMP15:%.*]] = mul i32 [[TMP14]], [[TMP13]]
1657; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP13]] to i64
1658; CHECK-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP15]] to i64
1659; CHECK-NEXT:    [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]
1660; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
1661; CHECK-NEXT:    [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
1662; CHECK-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
1663; CHECK-NEXT:    [[TMP22:%.*]] = add i32 [[TMP13]], [[TMP21]]
1664; CHECK-NEXT:    [[TMP23:%.*]] = zext i32 [[TMP8]] to i64
1665; CHECK-NEXT:    [[TMP24:%.*]] = zext i32 [[TMP22]] to i64
1666; CHECK-NEXT:    [[TMP25:%.*]] = mul i64 [[TMP23]], [[TMP24]]
1667; CHECK-NEXT:    [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32
1668; CHECK-NEXT:    [[TMP27:%.*]] = lshr i64 [[TMP25]], 32
1669; CHECK-NEXT:    [[TMP28:%.*]] = trunc i64 [[TMP27]] to i32
1670; CHECK-NEXT:    [[TMP29:%.*]] = mul i32 [[TMP28]], [[TMP9]]
1671; CHECK-NEXT:    [[TMP30:%.*]] = sub i32 [[TMP8]], [[TMP29]]
1672; CHECK-NEXT:    [[TMP31:%.*]] = icmp uge i32 [[TMP30]], [[TMP9]]
1673; CHECK-NEXT:    [[TMP32:%.*]] = add i32 [[TMP28]], 1
1674; CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP31]], i32 [[TMP32]], i32 [[TMP28]]
1675; CHECK-NEXT:    [[TMP34:%.*]] = sub i32 [[TMP30]], [[TMP9]]
1676; CHECK-NEXT:    [[TMP35:%.*]] = select i1 [[TMP31]], i32 [[TMP34]], i32 [[TMP30]]
1677; CHECK-NEXT:    [[TMP36:%.*]] = icmp uge i32 [[TMP35]], [[TMP9]]
1678; CHECK-NEXT:    [[TMP37:%.*]] = add i32 [[TMP33]], 1
1679; CHECK-NEXT:    [[TMP38:%.*]] = select i1 [[TMP36]], i32 [[TMP37]], i32 [[TMP33]]
1680; CHECK-NEXT:    [[TMP39:%.*]] = xor i32 [[TMP38]], [[TMP5]]
1681; CHECK-NEXT:    [[TMP40:%.*]] = sub i32 [[TMP39]], [[TMP5]]
1682; CHECK-NEXT:    [[TMP41:%.*]] = insertelement <4 x i32> undef, i32 [[TMP40]], i64 0
1683; CHECK-NEXT:    [[TMP42:%.*]] = extractelement <4 x i32> [[X]], i64 1
1684; CHECK-NEXT:    [[TMP43:%.*]] = extractelement <4 x i32> [[Y]], i64 1
1685; CHECK-NEXT:    [[TMP44:%.*]] = ashr i32 [[TMP42]], 31
1686; CHECK-NEXT:    [[TMP45:%.*]] = ashr i32 [[TMP43]], 31
1687; CHECK-NEXT:    [[TMP46:%.*]] = xor i32 [[TMP44]], [[TMP45]]
1688; CHECK-NEXT:    [[TMP47:%.*]] = add i32 [[TMP42]], [[TMP44]]
1689; CHECK-NEXT:    [[TMP48:%.*]] = add i32 [[TMP43]], [[TMP45]]
1690; CHECK-NEXT:    [[TMP49:%.*]] = xor i32 [[TMP47]], [[TMP44]]
1691; CHECK-NEXT:    [[TMP50:%.*]] = xor i32 [[TMP48]], [[TMP45]]
1692; CHECK-NEXT:    [[TMP51:%.*]] = uitofp i32 [[TMP50]] to float
1693; CHECK-NEXT:    [[TMP52:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP51]])
1694; CHECK-NEXT:    [[TMP53:%.*]] = fmul fast float [[TMP52]], 0x41EFFFFFC0000000
1695; CHECK-NEXT:    [[TMP54:%.*]] = fptoui float [[TMP53]] to i32
1696; CHECK-NEXT:    [[TMP55:%.*]] = sub i32 0, [[TMP50]]
1697; CHECK-NEXT:    [[TMP56:%.*]] = mul i32 [[TMP55]], [[TMP54]]
1698; CHECK-NEXT:    [[TMP57:%.*]] = zext i32 [[TMP54]] to i64
1699; CHECK-NEXT:    [[TMP58:%.*]] = zext i32 [[TMP56]] to i64
1700; CHECK-NEXT:    [[TMP59:%.*]] = mul i64 [[TMP57]], [[TMP58]]
1701; CHECK-NEXT:    [[TMP60:%.*]] = trunc i64 [[TMP59]] to i32
1702; CHECK-NEXT:    [[TMP61:%.*]] = lshr i64 [[TMP59]], 32
1703; CHECK-NEXT:    [[TMP62:%.*]] = trunc i64 [[TMP61]] to i32
1704; CHECK-NEXT:    [[TMP63:%.*]] = add i32 [[TMP54]], [[TMP62]]
1705; CHECK-NEXT:    [[TMP64:%.*]] = zext i32 [[TMP49]] to i64
1706; CHECK-NEXT:    [[TMP65:%.*]] = zext i32 [[TMP63]] to i64
1707; CHECK-NEXT:    [[TMP66:%.*]] = mul i64 [[TMP64]], [[TMP65]]
1708; CHECK-NEXT:    [[TMP67:%.*]] = trunc i64 [[TMP66]] to i32
1709; CHECK-NEXT:    [[TMP68:%.*]] = lshr i64 [[TMP66]], 32
1710; CHECK-NEXT:    [[TMP69:%.*]] = trunc i64 [[TMP68]] to i32
1711; CHECK-NEXT:    [[TMP70:%.*]] = mul i32 [[TMP69]], [[TMP50]]
1712; CHECK-NEXT:    [[TMP71:%.*]] = sub i32 [[TMP49]], [[TMP70]]
1713; CHECK-NEXT:    [[TMP72:%.*]] = icmp uge i32 [[TMP71]], [[TMP50]]
1714; CHECK-NEXT:    [[TMP73:%.*]] = add i32 [[TMP69]], 1
1715; CHECK-NEXT:    [[TMP74:%.*]] = select i1 [[TMP72]], i32 [[TMP73]], i32 [[TMP69]]
1716; CHECK-NEXT:    [[TMP75:%.*]] = sub i32 [[TMP71]], [[TMP50]]
1717; CHECK-NEXT:    [[TMP76:%.*]] = select i1 [[TMP72]], i32 [[TMP75]], i32 [[TMP71]]
1718; CHECK-NEXT:    [[TMP77:%.*]] = icmp uge i32 [[TMP76]], [[TMP50]]
1719; CHECK-NEXT:    [[TMP78:%.*]] = add i32 [[TMP74]], 1
1720; CHECK-NEXT:    [[TMP79:%.*]] = select i1 [[TMP77]], i32 [[TMP78]], i32 [[TMP74]]
1721; CHECK-NEXT:    [[TMP80:%.*]] = xor i32 [[TMP79]], [[TMP46]]
1722; CHECK-NEXT:    [[TMP81:%.*]] = sub i32 [[TMP80]], [[TMP46]]
1723; CHECK-NEXT:    [[TMP82:%.*]] = insertelement <4 x i32> [[TMP41]], i32 [[TMP81]], i64 1
1724; CHECK-NEXT:    [[TMP83:%.*]] = extractelement <4 x i32> [[X]], i64 2
1725; CHECK-NEXT:    [[TMP84:%.*]] = extractelement <4 x i32> [[Y]], i64 2
1726; CHECK-NEXT:    [[TMP85:%.*]] = ashr i32 [[TMP83]], 31
1727; CHECK-NEXT:    [[TMP86:%.*]] = ashr i32 [[TMP84]], 31
1728; CHECK-NEXT:    [[TMP87:%.*]] = xor i32 [[TMP85]], [[TMP86]]
1729; CHECK-NEXT:    [[TMP88:%.*]] = add i32 [[TMP83]], [[TMP85]]
1730; CHECK-NEXT:    [[TMP89:%.*]] = add i32 [[TMP84]], [[TMP86]]
1731; CHECK-NEXT:    [[TMP90:%.*]] = xor i32 [[TMP88]], [[TMP85]]
1732; CHECK-NEXT:    [[TMP91:%.*]] = xor i32 [[TMP89]], [[TMP86]]
1733; CHECK-NEXT:    [[TMP92:%.*]] = uitofp i32 [[TMP91]] to float
1734; CHECK-NEXT:    [[TMP93:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP92]])
1735; CHECK-NEXT:    [[TMP94:%.*]] = fmul fast float [[TMP93]], 0x41EFFFFFC0000000
1736; CHECK-NEXT:    [[TMP95:%.*]] = fptoui float [[TMP94]] to i32
1737; CHECK-NEXT:    [[TMP96:%.*]] = sub i32 0, [[TMP91]]
1738; CHECK-NEXT:    [[TMP97:%.*]] = mul i32 [[TMP96]], [[TMP95]]
1739; CHECK-NEXT:    [[TMP98:%.*]] = zext i32 [[TMP95]] to i64
1740; CHECK-NEXT:    [[TMP99:%.*]] = zext i32 [[TMP97]] to i64
1741; CHECK-NEXT:    [[TMP100:%.*]] = mul i64 [[TMP98]], [[TMP99]]
1742; CHECK-NEXT:    [[TMP101:%.*]] = trunc i64 [[TMP100]] to i32
1743; CHECK-NEXT:    [[TMP102:%.*]] = lshr i64 [[TMP100]], 32
1744; CHECK-NEXT:    [[TMP103:%.*]] = trunc i64 [[TMP102]] to i32
1745; CHECK-NEXT:    [[TMP104:%.*]] = add i32 [[TMP95]], [[TMP103]]
1746; CHECK-NEXT:    [[TMP105:%.*]] = zext i32 [[TMP90]] to i64
1747; CHECK-NEXT:    [[TMP106:%.*]] = zext i32 [[TMP104]] to i64
1748; CHECK-NEXT:    [[TMP107:%.*]] = mul i64 [[TMP105]], [[TMP106]]
1749; CHECK-NEXT:    [[TMP108:%.*]] = trunc i64 [[TMP107]] to i32
1750; CHECK-NEXT:    [[TMP109:%.*]] = lshr i64 [[TMP107]], 32
1751; CHECK-NEXT:    [[TMP110:%.*]] = trunc i64 [[TMP109]] to i32
1752; CHECK-NEXT:    [[TMP111:%.*]] = mul i32 [[TMP110]], [[TMP91]]
1753; CHECK-NEXT:    [[TMP112:%.*]] = sub i32 [[TMP90]], [[TMP111]]
1754; CHECK-NEXT:    [[TMP113:%.*]] = icmp uge i32 [[TMP112]], [[TMP91]]
1755; CHECK-NEXT:    [[TMP114:%.*]] = add i32 [[TMP110]], 1
1756; CHECK-NEXT:    [[TMP115:%.*]] = select i1 [[TMP113]], i32 [[TMP114]], i32 [[TMP110]]
1757; CHECK-NEXT:    [[TMP116:%.*]] = sub i32 [[TMP112]], [[TMP91]]
1758; CHECK-NEXT:    [[TMP117:%.*]] = select i1 [[TMP113]], i32 [[TMP116]], i32 [[TMP112]]
1759; CHECK-NEXT:    [[TMP118:%.*]] = icmp uge i32 [[TMP117]], [[TMP91]]
1760; CHECK-NEXT:    [[TMP119:%.*]] = add i32 [[TMP115]], 1
1761; CHECK-NEXT:    [[TMP120:%.*]] = select i1 [[TMP118]], i32 [[TMP119]], i32 [[TMP115]]
1762; CHECK-NEXT:    [[TMP121:%.*]] = xor i32 [[TMP120]], [[TMP87]]
1763; CHECK-NEXT:    [[TMP122:%.*]] = sub i32 [[TMP121]], [[TMP87]]
1764; CHECK-NEXT:    [[TMP123:%.*]] = insertelement <4 x i32> [[TMP82]], i32 [[TMP122]], i64 2
1765; CHECK-NEXT:    [[TMP124:%.*]] = extractelement <4 x i32> [[X]], i64 3
1766; CHECK-NEXT:    [[TMP125:%.*]] = extractelement <4 x i32> [[Y]], i64 3
1767; CHECK-NEXT:    [[TMP126:%.*]] = ashr i32 [[TMP124]], 31
1768; CHECK-NEXT:    [[TMP127:%.*]] = ashr i32 [[TMP125]], 31
1769; CHECK-NEXT:    [[TMP128:%.*]] = xor i32 [[TMP126]], [[TMP127]]
1770; CHECK-NEXT:    [[TMP129:%.*]] = add i32 [[TMP124]], [[TMP126]]
1771; CHECK-NEXT:    [[TMP130:%.*]] = add i32 [[TMP125]], [[TMP127]]
1772; CHECK-NEXT:    [[TMP131:%.*]] = xor i32 [[TMP129]], [[TMP126]]
1773; CHECK-NEXT:    [[TMP132:%.*]] = xor i32 [[TMP130]], [[TMP127]]
1774; CHECK-NEXT:    [[TMP133:%.*]] = uitofp i32 [[TMP132]] to float
1775; CHECK-NEXT:    [[TMP134:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP133]])
1776; CHECK-NEXT:    [[TMP135:%.*]] = fmul fast float [[TMP134]], 0x41EFFFFFC0000000
1777; CHECK-NEXT:    [[TMP136:%.*]] = fptoui float [[TMP135]] to i32
1778; CHECK-NEXT:    [[TMP137:%.*]] = sub i32 0, [[TMP132]]
1779; CHECK-NEXT:    [[TMP138:%.*]] = mul i32 [[TMP137]], [[TMP136]]
1780; CHECK-NEXT:    [[TMP139:%.*]] = zext i32 [[TMP136]] to i64
1781; CHECK-NEXT:    [[TMP140:%.*]] = zext i32 [[TMP138]] to i64
1782; CHECK-NEXT:    [[TMP141:%.*]] = mul i64 [[TMP139]], [[TMP140]]
1783; CHECK-NEXT:    [[TMP142:%.*]] = trunc i64 [[TMP141]] to i32
1784; CHECK-NEXT:    [[TMP143:%.*]] = lshr i64 [[TMP141]], 32
1785; CHECK-NEXT:    [[TMP144:%.*]] = trunc i64 [[TMP143]] to i32
1786; CHECK-NEXT:    [[TMP145:%.*]] = add i32 [[TMP136]], [[TMP144]]
1787; CHECK-NEXT:    [[TMP146:%.*]] = zext i32 [[TMP131]] to i64
1788; CHECK-NEXT:    [[TMP147:%.*]] = zext i32 [[TMP145]] to i64
1789; CHECK-NEXT:    [[TMP148:%.*]] = mul i64 [[TMP146]], [[TMP147]]
1790; CHECK-NEXT:    [[TMP149:%.*]] = trunc i64 [[TMP148]] to i32
1791; CHECK-NEXT:    [[TMP150:%.*]] = lshr i64 [[TMP148]], 32
1792; CHECK-NEXT:    [[TMP151:%.*]] = trunc i64 [[TMP150]] to i32
1793; CHECK-NEXT:    [[TMP152:%.*]] = mul i32 [[TMP151]], [[TMP132]]
1794; CHECK-NEXT:    [[TMP153:%.*]] = sub i32 [[TMP131]], [[TMP152]]
1795; CHECK-NEXT:    [[TMP154:%.*]] = icmp uge i32 [[TMP153]], [[TMP132]]
1796; CHECK-NEXT:    [[TMP155:%.*]] = add i32 [[TMP151]], 1
1797; CHECK-NEXT:    [[TMP156:%.*]] = select i1 [[TMP154]], i32 [[TMP155]], i32 [[TMP151]]
1798; CHECK-NEXT:    [[TMP157:%.*]] = sub i32 [[TMP153]], [[TMP132]]
1799; CHECK-NEXT:    [[TMP158:%.*]] = select i1 [[TMP154]], i32 [[TMP157]], i32 [[TMP153]]
1800; CHECK-NEXT:    [[TMP159:%.*]] = icmp uge i32 [[TMP158]], [[TMP132]]
1801; CHECK-NEXT:    [[TMP160:%.*]] = add i32 [[TMP156]], 1
1802; CHECK-NEXT:    [[TMP161:%.*]] = select i1 [[TMP159]], i32 [[TMP160]], i32 [[TMP156]]
1803; CHECK-NEXT:    [[TMP162:%.*]] = xor i32 [[TMP161]], [[TMP128]]
1804; CHECK-NEXT:    [[TMP163:%.*]] = sub i32 [[TMP162]], [[TMP128]]
1805; CHECK-NEXT:    [[TMP164:%.*]] = insertelement <4 x i32> [[TMP123]], i32 [[TMP163]], i64 3
1806; CHECK-NEXT:    store <4 x i32> [[TMP164]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16
1807; CHECK-NEXT:    ret void
1808;
1809; GFX6-LABEL: sdiv_v4i32:
1810; GFX6:       ; %bb.0:
1811; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
1812; GFX6-NEXT:    s_mov_b32 s16, 0x4f7ffffe
1813; GFX6-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x9
1814; GFX6-NEXT:    s_mov_b32 s15, 0xf000
1815; GFX6-NEXT:    s_mov_b32 s14, -1
1816; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
1817; GFX6-NEXT:    s_ashr_i32 s2, s8, 31
1818; GFX6-NEXT:    s_add_i32 s3, s8, s2
1819; GFX6-NEXT:    s_xor_b32 s3, s3, s2
1820; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s3
1821; GFX6-NEXT:    s_ashr_i32 s8, s9, 31
1822; GFX6-NEXT:    s_add_i32 s0, s9, s8
1823; GFX6-NEXT:    s_xor_b32 s9, s0, s8
1824; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1825; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
1826; GFX6-NEXT:    s_sub_i32 s1, 0, s3
1827; GFX6-NEXT:    s_ashr_i32 s0, s4, 31
1828; GFX6-NEXT:    v_mul_f32_e32 v0, s16, v0
1829; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
1830; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1831; GFX6-NEXT:    s_xor_b32 s2, s0, s2
1832; GFX6-NEXT:    v_mul_lo_u32 v2, s1, v0
1833; GFX6-NEXT:    s_add_i32 s1, s4, s0
1834; GFX6-NEXT:    v_mul_f32_e32 v1, s16, v1
1835; GFX6-NEXT:    s_xor_b32 s1, s1, s0
1836; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
1837; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
1838; GFX6-NEXT:    s_sub_i32 s0, 0, s9
1839; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1840; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
1841; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v1
1842; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s3
1843; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v2
1844; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
1845; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s1, v3
1846; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v3
1847; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
1848; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s3, v3
1849; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[0:1]
1850; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
1851; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1852; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v3
1853; GFX6-NEXT:    s_ashr_i32 s0, s5, 31
1854; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
1855; GFX6-NEXT:    s_add_i32 s1, s5, s0
1856; GFX6-NEXT:    v_xor_b32_e32 v0, s2, v0
1857; GFX6-NEXT:    s_ashr_i32 s3, s10, 31
1858; GFX6-NEXT:    s_xor_b32 s1, s1, s0
1859; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
1860; GFX6-NEXT:    s_xor_b32 s2, s0, s8
1861; GFX6-NEXT:    s_add_i32 s0, s10, s3
1862; GFX6-NEXT:    s_xor_b32 s4, s0, s3
1863; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s4
1864; GFX6-NEXT:    v_mul_hi_u32 v1, s1, v1
1865; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1866; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s9
1867; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v1
1868; GFX6-NEXT:    v_mul_f32_e32 v3, s16, v3
1869; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
1870; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
1871; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v2
1872; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[0:1]
1873; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s9, v2
1874; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v4, s[0:1]
1875; GFX6-NEXT:    s_sub_i32 s0, 0, s4
1876; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v3
1877; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v1
1878; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
1879; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
1880; GFX6-NEXT:    v_mul_hi_u32 v2, v3, v5
1881; GFX6-NEXT:    v_xor_b32_e32 v1, s2, v1
1882; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s2, v1
1883; GFX6-NEXT:    s_ashr_i32 s2, s11, 31
1884; GFX6-NEXT:    s_ashr_i32 s0, s6, 31
1885; GFX6-NEXT:    s_add_i32 s5, s11, s2
1886; GFX6-NEXT:    s_add_i32 s1, s6, s0
1887; GFX6-NEXT:    s_xor_b32 s5, s5, s2
1888; GFX6-NEXT:    s_xor_b32 s1, s1, s0
1889; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
1890; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s5
1891; GFX6-NEXT:    v_mul_hi_u32 v2, s1, v2
1892; GFX6-NEXT:    s_xor_b32 s3, s0, s3
1893; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v4
1894; GFX6-NEXT:    v_mul_lo_u32 v3, v2, s4
1895; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v2
1896; GFX6-NEXT:    v_mul_f32_e32 v4, s16, v4
1897; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s1, v3
1898; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
1899; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s4, v3
1900; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v5, s[0:1]
1901; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s4, v3
1902; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
1903; GFX6-NEXT:    s_sub_i32 s0, 0, s5
1904; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v4
1905; GFX6-NEXT:    s_ashr_i32 s0, s7, 31
1906; GFX6-NEXT:    s_add_i32 s1, s7, s0
1907; GFX6-NEXT:    s_xor_b32 s1, s1, s0
1908; GFX6-NEXT:    v_mul_hi_u32 v5, v4, v5
1909; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
1910; GFX6-NEXT:    s_xor_b32 s2, s0, s2
1911; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1912; GFX6-NEXT:    v_mul_hi_u32 v4, s1, v4
1913; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s4, v3
1914; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
1915; GFX6-NEXT:    v_xor_b32_e32 v2, s3, v2
1916; GFX6-NEXT:    v_mul_lo_u32 v3, v4, s5
1917; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
1918; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v2
1919; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s1, v3
1920; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s5, v3
1921; GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]
1922; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s5, v3
1923; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
1924; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
1925; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s5, v3
1926; GFX6-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc
1927; GFX6-NEXT:    v_xor_b32_e32 v3, s2, v3
1928; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s2, v3
1929; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[12:15], 0
1930; GFX6-NEXT:    s_endpgm
1931;
1932; GFX9-LABEL: sdiv_v4i32:
1933; GFX9:       ; %bb.0:
1934; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
1935; GFX9-NEXT:    s_mov_b32 s15, 0x4f7ffffe
1936; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
1937; GFX9-NEXT:    v_mov_b32_e32 v4, 0
1938; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1939; GFX9-NEXT:    s_ashr_i32 s2, s8, 31
1940; GFX9-NEXT:    s_add_i32 s3, s8, s2
1941; GFX9-NEXT:    s_xor_b32 s3, s3, s2
1942; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
1943; GFX9-NEXT:    s_ashr_i32 s12, s9, 31
1944; GFX9-NEXT:    s_add_i32 s9, s9, s12
1945; GFX9-NEXT:    s_xor_b32 s9, s9, s12
1946; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1947; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
1948; GFX9-NEXT:    s_sub_i32 s14, 0, s3
1949; GFX9-NEXT:    s_ashr_i32 s8, s4, 31
1950; GFX9-NEXT:    v_mul_f32_e32 v0, s15, v0
1951; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
1952; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1953; GFX9-NEXT:    s_add_i32 s4, s4, s8
1954; GFX9-NEXT:    s_xor_b32 s4, s4, s8
1955; GFX9-NEXT:    v_mul_lo_u32 v2, s14, v0
1956; GFX9-NEXT:    v_mul_f32_e32 v1, s15, v1
1957; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
1958; GFX9-NEXT:    s_sub_i32 s14, 0, s9
1959; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
1960; GFX9-NEXT:    s_ashr_i32 s13, s5, 31
1961; GFX9-NEXT:    v_mul_lo_u32 v3, s14, v1
1962; GFX9-NEXT:    s_add_i32 s5, s5, s13
1963; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
1964; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
1965; GFX9-NEXT:    v_mul_hi_u32 v2, v1, v3
1966; GFX9-NEXT:    s_xor_b32 s5, s5, s13
1967; GFX9-NEXT:    s_xor_b32 s2, s8, s2
1968; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s3
1969; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
1970; GFX9-NEXT:    v_add_u32_e32 v2, 1, v0
1971; GFX9-NEXT:    v_mul_hi_u32 v1, s5, v1
1972; GFX9-NEXT:    v_sub_u32_e32 v3, s4, v3
1973; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v3
1974; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1975; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v3
1976; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
1977; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2
1978; GFX9-NEXT:    s_ashr_i32 s3, s10, 31
1979; GFX9-NEXT:    s_add_i32 s4, s10, s3
1980; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
1981; GFX9-NEXT:    s_xor_b32 s4, s4, s3
1982; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1983; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, s4
1984; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s9
1985; GFX9-NEXT:    v_add_u32_e32 v5, 1, v1
1986; GFX9-NEXT:    s_ashr_i32 s8, s11, 31
1987; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1988; GFX9-NEXT:    v_sub_u32_e32 v2, s5, v2
1989; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
1990; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
1991; GFX9-NEXT:    v_mul_f32_e32 v3, s15, v3
1992; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
1993; GFX9-NEXT:    v_subrev_u32_e32 v5, s9, v2
1994; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
1995; GFX9-NEXT:    s_sub_i32 s5, 0, s4
1996; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
1997; GFX9-NEXT:    v_mul_lo_u32 v2, s5, v3
1998; GFX9-NEXT:    s_add_i32 s9, s11, s8
1999; GFX9-NEXT:    v_add_u32_e32 v5, 1, v1
2000; GFX9-NEXT:    s_xor_b32 s9, s9, s8
2001; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
2002; GFX9-NEXT:    v_mul_hi_u32 v2, v3, v2
2003; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s9
2004; GFX9-NEXT:    s_ashr_i32 s5, s6, 31
2005; GFX9-NEXT:    s_add_i32 s6, s6, s5
2006; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
2007; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v5
2008; GFX9-NEXT:    s_xor_b32 s6, s6, s5
2009; GFX9-NEXT:    v_mul_hi_u32 v2, s6, v2
2010; GFX9-NEXT:    v_xor_b32_e32 v0, s2, v0
2011; GFX9-NEXT:    v_mul_f32_e32 v3, s15, v3
2012; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
2013; GFX9-NEXT:    v_subrev_u32_e32 v0, s2, v0
2014; GFX9-NEXT:    s_xor_b32 s2, s13, s12
2015; GFX9-NEXT:    v_mul_lo_u32 v5, v2, s4
2016; GFX9-NEXT:    v_xor_b32_e32 v1, s2, v1
2017; GFX9-NEXT:    v_subrev_u32_e32 v1, s2, v1
2018; GFX9-NEXT:    s_xor_b32 s2, s5, s3
2019; GFX9-NEXT:    s_sub_i32 s3, 0, s9
2020; GFX9-NEXT:    v_mul_lo_u32 v7, s3, v3
2021; GFX9-NEXT:    v_sub_u32_e32 v5, s6, v5
2022; GFX9-NEXT:    v_add_u32_e32 v6, 1, v2
2023; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v5
2024; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
2025; GFX9-NEXT:    v_subrev_u32_e32 v6, s4, v5
2026; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
2027; GFX9-NEXT:    v_mul_hi_u32 v6, v3, v7
2028; GFX9-NEXT:    s_ashr_i32 s3, s7, 31
2029; GFX9-NEXT:    s_add_i32 s5, s7, s3
2030; GFX9-NEXT:    s_xor_b32 s5, s5, s3
2031; GFX9-NEXT:    v_add_u32_e32 v3, v3, v6
2032; GFX9-NEXT:    v_mul_hi_u32 v3, s5, v3
2033; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v5
2034; GFX9-NEXT:    v_add_u32_e32 v6, 1, v2
2035; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
2036; GFX9-NEXT:    v_mul_lo_u32 v5, v3, s9
2037; GFX9-NEXT:    v_add_u32_e32 v6, 1, v3
2038; GFX9-NEXT:    v_xor_b32_e32 v2, s2, v2
2039; GFX9-NEXT:    v_subrev_u32_e32 v2, s2, v2
2040; GFX9-NEXT:    v_sub_u32_e32 v5, s5, v5
2041; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v5
2042; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
2043; GFX9-NEXT:    v_subrev_u32_e32 v6, s9, v5
2044; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
2045; GFX9-NEXT:    v_add_u32_e32 v6, 1, v3
2046; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v5
2047; GFX9-NEXT:    s_xor_b32 s2, s3, s8
2048; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
2049; GFX9-NEXT:    v_xor_b32_e32 v3, s2, v3
2050; GFX9-NEXT:    v_subrev_u32_e32 v3, s2, v3
2051; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
2052; GFX9-NEXT:    s_endpgm
2053  %r = sdiv <4 x i32> %x, %y
2054  store <4 x i32> %r, <4 x i32> addrspace(1)* %out
2055  ret void
2056}
2057
2058define amdgpu_kernel void @srem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
2059; CHECK-LABEL: @srem_v4i32(
2060; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i64 0
2061; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 0
2062; CHECK-NEXT:    [[TMP3:%.*]] = ashr i32 [[TMP1]], 31
2063; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP2]], 31
2064; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[TMP1]], [[TMP3]]
2065; CHECK-NEXT:    [[TMP6:%.*]] = add i32 [[TMP2]], [[TMP4]]
2066; CHECK-NEXT:    [[TMP7:%.*]] = xor i32 [[TMP5]], [[TMP3]]
2067; CHECK-NEXT:    [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP4]]
2068; CHECK-NEXT:    [[TMP9:%.*]] = uitofp i32 [[TMP8]] to float
2069; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
2070; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP10]], 0x41EFFFFFC0000000
2071; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP11]] to i32
2072; CHECK-NEXT:    [[TMP13:%.*]] = sub i32 0, [[TMP8]]
2073; CHECK-NEXT:    [[TMP14:%.*]] = mul i32 [[TMP13]], [[TMP12]]
2074; CHECK-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP12]] to i64
2075; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP14]] to i64
2076; CHECK-NEXT:    [[TMP17:%.*]] = mul i64 [[TMP15]], [[TMP16]]
2077; CHECK-NEXT:    [[TMP18:%.*]] = trunc i64 [[TMP17]] to i32
2078; CHECK-NEXT:    [[TMP19:%.*]] = lshr i64 [[TMP17]], 32
2079; CHECK-NEXT:    [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32
2080; CHECK-NEXT:    [[TMP21:%.*]] = add i32 [[TMP12]], [[TMP20]]
2081; CHECK-NEXT:    [[TMP22:%.*]] = zext i32 [[TMP7]] to i64
2082; CHECK-NEXT:    [[TMP23:%.*]] = zext i32 [[TMP21]] to i64
2083; CHECK-NEXT:    [[TMP24:%.*]] = mul i64 [[TMP22]], [[TMP23]]
2084; CHECK-NEXT:    [[TMP25:%.*]] = trunc i64 [[TMP24]] to i32
2085; CHECK-NEXT:    [[TMP26:%.*]] = lshr i64 [[TMP24]], 32
2086; CHECK-NEXT:    [[TMP27:%.*]] = trunc i64 [[TMP26]] to i32
2087; CHECK-NEXT:    [[TMP28:%.*]] = mul i32 [[TMP27]], [[TMP8]]
2088; CHECK-NEXT:    [[TMP29:%.*]] = sub i32 [[TMP7]], [[TMP28]]
2089; CHECK-NEXT:    [[TMP30:%.*]] = icmp uge i32 [[TMP29]], [[TMP8]]
2090; CHECK-NEXT:    [[TMP31:%.*]] = sub i32 [[TMP29]], [[TMP8]]
2091; CHECK-NEXT:    [[TMP32:%.*]] = select i1 [[TMP30]], i32 [[TMP31]], i32 [[TMP29]]
2092; CHECK-NEXT:    [[TMP33:%.*]] = icmp uge i32 [[TMP32]], [[TMP8]]
2093; CHECK-NEXT:    [[TMP34:%.*]] = sub i32 [[TMP32]], [[TMP8]]
2094; CHECK-NEXT:    [[TMP35:%.*]] = select i1 [[TMP33]], i32 [[TMP34]], i32 [[TMP32]]
2095; CHECK-NEXT:    [[TMP36:%.*]] = xor i32 [[TMP35]], [[TMP3]]
2096; CHECK-NEXT:    [[TMP37:%.*]] = sub i32 [[TMP36]], [[TMP3]]
2097; CHECK-NEXT:    [[TMP38:%.*]] = insertelement <4 x i32> undef, i32 [[TMP37]], i64 0
2098; CHECK-NEXT:    [[TMP39:%.*]] = extractelement <4 x i32> [[X]], i64 1
2099; CHECK-NEXT:    [[TMP40:%.*]] = extractelement <4 x i32> [[Y]], i64 1
2100; CHECK-NEXT:    [[TMP41:%.*]] = ashr i32 [[TMP39]], 31
2101; CHECK-NEXT:    [[TMP42:%.*]] = ashr i32 [[TMP40]], 31
2102; CHECK-NEXT:    [[TMP43:%.*]] = add i32 [[TMP39]], [[TMP41]]
2103; CHECK-NEXT:    [[TMP44:%.*]] = add i32 [[TMP40]], [[TMP42]]
2104; CHECK-NEXT:    [[TMP45:%.*]] = xor i32 [[TMP43]], [[TMP41]]
2105; CHECK-NEXT:    [[TMP46:%.*]] = xor i32 [[TMP44]], [[TMP42]]
2106; CHECK-NEXT:    [[TMP47:%.*]] = uitofp i32 [[TMP46]] to float
2107; CHECK-NEXT:    [[TMP48:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP47]])
2108; CHECK-NEXT:    [[TMP49:%.*]] = fmul fast float [[TMP48]], 0x41EFFFFFC0000000
2109; CHECK-NEXT:    [[TMP50:%.*]] = fptoui float [[TMP49]] to i32
2110; CHECK-NEXT:    [[TMP51:%.*]] = sub i32 0, [[TMP46]]
2111; CHECK-NEXT:    [[TMP52:%.*]] = mul i32 [[TMP51]], [[TMP50]]
2112; CHECK-NEXT:    [[TMP53:%.*]] = zext i32 [[TMP50]] to i64
2113; CHECK-NEXT:    [[TMP54:%.*]] = zext i32 [[TMP52]] to i64
2114; CHECK-NEXT:    [[TMP55:%.*]] = mul i64 [[TMP53]], [[TMP54]]
2115; CHECK-NEXT:    [[TMP56:%.*]] = trunc i64 [[TMP55]] to i32
2116; CHECK-NEXT:    [[TMP57:%.*]] = lshr i64 [[TMP55]], 32
2117; CHECK-NEXT:    [[TMP58:%.*]] = trunc i64 [[TMP57]] to i32
2118; CHECK-NEXT:    [[TMP59:%.*]] = add i32 [[TMP50]], [[TMP58]]
2119; CHECK-NEXT:    [[TMP60:%.*]] = zext i32 [[TMP45]] to i64
2120; CHECK-NEXT:    [[TMP61:%.*]] = zext i32 [[TMP59]] to i64
2121; CHECK-NEXT:    [[TMP62:%.*]] = mul i64 [[TMP60]], [[TMP61]]
2122; CHECK-NEXT:    [[TMP63:%.*]] = trunc i64 [[TMP62]] to i32
2123; CHECK-NEXT:    [[TMP64:%.*]] = lshr i64 [[TMP62]], 32
2124; CHECK-NEXT:    [[TMP65:%.*]] = trunc i64 [[TMP64]] to i32
2125; CHECK-NEXT:    [[TMP66:%.*]] = mul i32 [[TMP65]], [[TMP46]]
2126; CHECK-NEXT:    [[TMP67:%.*]] = sub i32 [[TMP45]], [[TMP66]]
2127; CHECK-NEXT:    [[TMP68:%.*]] = icmp uge i32 [[TMP67]], [[TMP46]]
2128; CHECK-NEXT:    [[TMP69:%.*]] = sub i32 [[TMP67]], [[TMP46]]
2129; CHECK-NEXT:    [[TMP70:%.*]] = select i1 [[TMP68]], i32 [[TMP69]], i32 [[TMP67]]
2130; CHECK-NEXT:    [[TMP71:%.*]] = icmp uge i32 [[TMP70]], [[TMP46]]
2131; CHECK-NEXT:    [[TMP72:%.*]] = sub i32 [[TMP70]], [[TMP46]]
2132; CHECK-NEXT:    [[TMP73:%.*]] = select i1 [[TMP71]], i32 [[TMP72]], i32 [[TMP70]]
2133; CHECK-NEXT:    [[TMP74:%.*]] = xor i32 [[TMP73]], [[TMP41]]
2134; CHECK-NEXT:    [[TMP75:%.*]] = sub i32 [[TMP74]], [[TMP41]]
2135; CHECK-NEXT:    [[TMP76:%.*]] = insertelement <4 x i32> [[TMP38]], i32 [[TMP75]], i64 1
2136; CHECK-NEXT:    [[TMP77:%.*]] = extractelement <4 x i32> [[X]], i64 2
2137; CHECK-NEXT:    [[TMP78:%.*]] = extractelement <4 x i32> [[Y]], i64 2
2138; CHECK-NEXT:    [[TMP79:%.*]] = ashr i32 [[TMP77]], 31
2139; CHECK-NEXT:    [[TMP80:%.*]] = ashr i32 [[TMP78]], 31
2140; CHECK-NEXT:    [[TMP81:%.*]] = add i32 [[TMP77]], [[TMP79]]
2141; CHECK-NEXT:    [[TMP82:%.*]] = add i32 [[TMP78]], [[TMP80]]
2142; CHECK-NEXT:    [[TMP83:%.*]] = xor i32 [[TMP81]], [[TMP79]]
2143; CHECK-NEXT:    [[TMP84:%.*]] = xor i32 [[TMP82]], [[TMP80]]
2144; CHECK-NEXT:    [[TMP85:%.*]] = uitofp i32 [[TMP84]] to float
2145; CHECK-NEXT:    [[TMP86:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP85]])
2146; CHECK-NEXT:    [[TMP87:%.*]] = fmul fast float [[TMP86]], 0x41EFFFFFC0000000
2147; CHECK-NEXT:    [[TMP88:%.*]] = fptoui float [[TMP87]] to i32
2148; CHECK-NEXT:    [[TMP89:%.*]] = sub i32 0, [[TMP84]]
2149; CHECK-NEXT:    [[TMP90:%.*]] = mul i32 [[TMP89]], [[TMP88]]
2150; CHECK-NEXT:    [[TMP91:%.*]] = zext i32 [[TMP88]] to i64
2151; CHECK-NEXT:    [[TMP92:%.*]] = zext i32 [[TMP90]] to i64
2152; CHECK-NEXT:    [[TMP93:%.*]] = mul i64 [[TMP91]], [[TMP92]]
2153; CHECK-NEXT:    [[TMP94:%.*]] = trunc i64 [[TMP93]] to i32
2154; CHECK-NEXT:    [[TMP95:%.*]] = lshr i64 [[TMP93]], 32
2155; CHECK-NEXT:    [[TMP96:%.*]] = trunc i64 [[TMP95]] to i32
2156; CHECK-NEXT:    [[TMP97:%.*]] = add i32 [[TMP88]], [[TMP96]]
2157; CHECK-NEXT:    [[TMP98:%.*]] = zext i32 [[TMP83]] to i64
2158; CHECK-NEXT:    [[TMP99:%.*]] = zext i32 [[TMP97]] to i64
2159; CHECK-NEXT:    [[TMP100:%.*]] = mul i64 [[TMP98]], [[TMP99]]
2160; CHECK-NEXT:    [[TMP101:%.*]] = trunc i64 [[TMP100]] to i32
2161; CHECK-NEXT:    [[TMP102:%.*]] = lshr i64 [[TMP100]], 32
2162; CHECK-NEXT:    [[TMP103:%.*]] = trunc i64 [[TMP102]] to i32
2163; CHECK-NEXT:    [[TMP104:%.*]] = mul i32 [[TMP103]], [[TMP84]]
2164; CHECK-NEXT:    [[TMP105:%.*]] = sub i32 [[TMP83]], [[TMP104]]
2165; CHECK-NEXT:    [[TMP106:%.*]] = icmp uge i32 [[TMP105]], [[TMP84]]
2166; CHECK-NEXT:    [[TMP107:%.*]] = sub i32 [[TMP105]], [[TMP84]]
2167; CHECK-NEXT:    [[TMP108:%.*]] = select i1 [[TMP106]], i32 [[TMP107]], i32 [[TMP105]]
2168; CHECK-NEXT:    [[TMP109:%.*]] = icmp uge i32 [[TMP108]], [[TMP84]]
2169; CHECK-NEXT:    [[TMP110:%.*]] = sub i32 [[TMP108]], [[TMP84]]
2170; CHECK-NEXT:    [[TMP111:%.*]] = select i1 [[TMP109]], i32 [[TMP110]], i32 [[TMP108]]
2171; CHECK-NEXT:    [[TMP112:%.*]] = xor i32 [[TMP111]], [[TMP79]]
2172; CHECK-NEXT:    [[TMP113:%.*]] = sub i32 [[TMP112]], [[TMP79]]
2173; CHECK-NEXT:    [[TMP114:%.*]] = insertelement <4 x i32> [[TMP76]], i32 [[TMP113]], i64 2
2174; CHECK-NEXT:    [[TMP115:%.*]] = extractelement <4 x i32> [[X]], i64 3
2175; CHECK-NEXT:    [[TMP116:%.*]] = extractelement <4 x i32> [[Y]], i64 3
2176; CHECK-NEXT:    [[TMP117:%.*]] = ashr i32 [[TMP115]], 31
2177; CHECK-NEXT:    [[TMP118:%.*]] = ashr i32 [[TMP116]], 31
2178; CHECK-NEXT:    [[TMP119:%.*]] = add i32 [[TMP115]], [[TMP117]]
2179; CHECK-NEXT:    [[TMP120:%.*]] = add i32 [[TMP116]], [[TMP118]]
2180; CHECK-NEXT:    [[TMP121:%.*]] = xor i32 [[TMP119]], [[TMP117]]
2181; CHECK-NEXT:    [[TMP122:%.*]] = xor i32 [[TMP120]], [[TMP118]]
2182; CHECK-NEXT:    [[TMP123:%.*]] = uitofp i32 [[TMP122]] to float
2183; CHECK-NEXT:    [[TMP124:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP123]])
2184; CHECK-NEXT:    [[TMP125:%.*]] = fmul fast float [[TMP124]], 0x41EFFFFFC0000000
2185; CHECK-NEXT:    [[TMP126:%.*]] = fptoui float [[TMP125]] to i32
2186; CHECK-NEXT:    [[TMP127:%.*]] = sub i32 0, [[TMP122]]
2187; CHECK-NEXT:    [[TMP128:%.*]] = mul i32 [[TMP127]], [[TMP126]]
2188; CHECK-NEXT:    [[TMP129:%.*]] = zext i32 [[TMP126]] to i64
2189; CHECK-NEXT:    [[TMP130:%.*]] = zext i32 [[TMP128]] to i64
2190; CHECK-NEXT:    [[TMP131:%.*]] = mul i64 [[TMP129]], [[TMP130]]
2191; CHECK-NEXT:    [[TMP132:%.*]] = trunc i64 [[TMP131]] to i32
2192; CHECK-NEXT:    [[TMP133:%.*]] = lshr i64 [[TMP131]], 32
2193; CHECK-NEXT:    [[TMP134:%.*]] = trunc i64 [[TMP133]] to i32
2194; CHECK-NEXT:    [[TMP135:%.*]] = add i32 [[TMP126]], [[TMP134]]
2195; CHECK-NEXT:    [[TMP136:%.*]] = zext i32 [[TMP121]] to i64
2196; CHECK-NEXT:    [[TMP137:%.*]] = zext i32 [[TMP135]] to i64
2197; CHECK-NEXT:    [[TMP138:%.*]] = mul i64 [[TMP136]], [[TMP137]]
2198; CHECK-NEXT:    [[TMP139:%.*]] = trunc i64 [[TMP138]] to i32
2199; CHECK-NEXT:    [[TMP140:%.*]] = lshr i64 [[TMP138]], 32
2200; CHECK-NEXT:    [[TMP141:%.*]] = trunc i64 [[TMP140]] to i32
2201; CHECK-NEXT:    [[TMP142:%.*]] = mul i32 [[TMP141]], [[TMP122]]
2202; CHECK-NEXT:    [[TMP143:%.*]] = sub i32 [[TMP121]], [[TMP142]]
2203; CHECK-NEXT:    [[TMP144:%.*]] = icmp uge i32 [[TMP143]], [[TMP122]]
2204; CHECK-NEXT:    [[TMP145:%.*]] = sub i32 [[TMP143]], [[TMP122]]
2205; CHECK-NEXT:    [[TMP146:%.*]] = select i1 [[TMP144]], i32 [[TMP145]], i32 [[TMP143]]
2206; CHECK-NEXT:    [[TMP147:%.*]] = icmp uge i32 [[TMP146]], [[TMP122]]
2207; CHECK-NEXT:    [[TMP148:%.*]] = sub i32 [[TMP146]], [[TMP122]]
2208; CHECK-NEXT:    [[TMP149:%.*]] = select i1 [[TMP147]], i32 [[TMP148]], i32 [[TMP146]]
2209; CHECK-NEXT:    [[TMP150:%.*]] = xor i32 [[TMP149]], [[TMP117]]
2210; CHECK-NEXT:    [[TMP151:%.*]] = sub i32 [[TMP150]], [[TMP117]]
2211; CHECK-NEXT:    [[TMP152:%.*]] = insertelement <4 x i32> [[TMP114]], i32 [[TMP151]], i64 3
2212; CHECK-NEXT:    store <4 x i32> [[TMP152]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16
2213; CHECK-NEXT:    ret void
2214;
2215; GFX6-LABEL: srem_v4i32:
2216; GFX6:       ; %bb.0:
2217; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
2218; GFX6-NEXT:    s_mov_b32 s14, 0x4f7ffffe
2219; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
2220; GFX6-NEXT:    s_mov_b32 s3, 0xf000
2221; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
2222; GFX6-NEXT:    s_ashr_i32 s2, s8, 31
2223; GFX6-NEXT:    s_add_i32 s8, s8, s2
2224; GFX6-NEXT:    s_xor_b32 s8, s8, s2
2225; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
2226; GFX6-NEXT:    s_ashr_i32 s12, s9, 31
2227; GFX6-NEXT:    s_add_i32 s9, s9, s12
2228; GFX6-NEXT:    s_xor_b32 s9, s9, s12
2229; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
2230; GFX6-NEXT:    s_sub_i32 s13, 0, s8
2231; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
2232; GFX6-NEXT:    s_ashr_i32 s12, s4, 31
2233; GFX6-NEXT:    v_mul_f32_e32 v0, s14, v0
2234; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
2235; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
2236; GFX6-NEXT:    s_add_i32 s4, s4, s12
2237; GFX6-NEXT:    s_xor_b32 s4, s4, s12
2238; GFX6-NEXT:    v_mul_lo_u32 v2, s13, v0
2239; GFX6-NEXT:    v_mul_f32_e32 v1, s14, v1
2240; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
2241; GFX6-NEXT:    s_sub_i32 s13, 0, s9
2242; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
2243; GFX6-NEXT:    s_mov_b32 s2, -1
2244; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2245; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
2246; GFX6-NEXT:    v_mul_lo_u32 v2, s13, v1
2247; GFX6-NEXT:    s_ashr_i32 s13, s5, 31
2248; GFX6-NEXT:    s_add_i32 s5, s5, s13
2249; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s8
2250; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v2
2251; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
2252; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v0
2253; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
2254; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
2255; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v0
2256; GFX6-NEXT:    s_xor_b32 s4, s5, s13
2257; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2258; GFX6-NEXT:    s_ashr_i32 s5, s10, 31
2259; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
2260; GFX6-NEXT:    s_add_i32 s8, s10, s5
2261; GFX6-NEXT:    s_xor_b32 s5, s8, s5
2262; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s5
2263; GFX6-NEXT:    v_mul_hi_u32 v1, s4, v1
2264; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
2265; GFX6-NEXT:    v_xor_b32_e32 v0, s12, v0
2266; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
2267; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s9
2268; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s12, v0
2269; GFX6-NEXT:    v_mul_f32_e32 v2, s14, v2
2270; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
2271; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s4, v1
2272; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s9, v1
2273; GFX6-NEXT:    s_sub_i32 s4, 0, s5
2274; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
2275; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v2
2276; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
2277; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s9, v1
2278; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
2279; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
2280; GFX6-NEXT:    v_mul_hi_u32 v3, v2, v4
2281; GFX6-NEXT:    s_ashr_i32 s8, s11, 31
2282; GFX6-NEXT:    s_add_i32 s9, s11, s8
2283; GFX6-NEXT:    s_ashr_i32 s4, s6, 31
2284; GFX6-NEXT:    s_xor_b32 s8, s9, s8
2285; GFX6-NEXT:    s_add_i32 s6, s6, s4
2286; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
2287; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s8
2288; GFX6-NEXT:    s_xor_b32 s6, s6, s4
2289; GFX6-NEXT:    v_mul_hi_u32 v2, s6, v2
2290; GFX6-NEXT:    v_xor_b32_e32 v1, s13, v1
2291; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
2292; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s13, v1
2293; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s5
2294; GFX6-NEXT:    v_mul_f32_e32 v3, s14, v3
2295; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
2296; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s6, v2
2297; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s5, v2
2298; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s5, v2
2299; GFX6-NEXT:    s_sub_i32 s6, 0, s8
2300; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2301; GFX6-NEXT:    v_mul_lo_u32 v4, s6, v3
2302; GFX6-NEXT:    s_ashr_i32 s6, s7, 31
2303; GFX6-NEXT:    s_add_i32 s7, s7, s6
2304; GFX6-NEXT:    s_xor_b32 s7, s7, s6
2305; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v4
2306; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s5, v2
2307; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
2308; GFX6-NEXT:    v_mul_hi_u32 v3, s7, v3
2309; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s5, v2
2310; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
2311; GFX6-NEXT:    v_xor_b32_e32 v2, s4, v2
2312; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s8
2313; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s4, v2
2314; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s7, v3
2315; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s8, v3
2316; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
2317; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
2318; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s8, v3
2319; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
2320; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
2321; GFX6-NEXT:    v_xor_b32_e32 v3, s6, v3
2322; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s6, v3
2323; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
2324; GFX6-NEXT:    s_endpgm
2325;
2326; GFX9-LABEL: srem_v4i32:
2327; GFX9:       ; %bb.0:
2328; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
2329; GFX9-NEXT:    s_mov_b32 s13, 0x4f7ffffe
2330; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
2331; GFX9-NEXT:    v_mov_b32_e32 v4, 0
2332; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
2333; GFX9-NEXT:    s_ashr_i32 s2, s8, 31
2334; GFX9-NEXT:    s_add_i32 s8, s8, s2
2335; GFX9-NEXT:    s_xor_b32 s2, s8, s2
2336; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s2
2337; GFX9-NEXT:    s_ashr_i32 s3, s9, 31
2338; GFX9-NEXT:    s_sub_i32 s12, 0, s2
2339; GFX9-NEXT:    s_add_i32 s8, s9, s3
2340; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
2341; GFX9-NEXT:    s_xor_b32 s3, s8, s3
2342; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s3
2343; GFX9-NEXT:    s_ashr_i32 s8, s4, 31
2344; GFX9-NEXT:    v_mul_f32_e32 v0, s13, v0
2345; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
2346; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
2347; GFX9-NEXT:    s_add_i32 s4, s4, s8
2348; GFX9-NEXT:    s_xor_b32 s4, s4, s8
2349; GFX9-NEXT:    v_mul_lo_u32 v2, s12, v0
2350; GFX9-NEXT:    v_mul_f32_e32 v1, s13, v1
2351; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
2352; GFX9-NEXT:    s_sub_i32 s12, 0, s3
2353; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
2354; GFX9-NEXT:    s_ashr_i32 s9, s5, 31
2355; GFX9-NEXT:    v_mul_lo_u32 v3, s12, v1
2356; GFX9-NEXT:    s_add_i32 s5, s5, s9
2357; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
2358; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
2359; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
2360; GFX9-NEXT:    s_xor_b32 s5, s5, s9
2361; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s2
2362; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
2363; GFX9-NEXT:    v_mul_hi_u32 v1, s5, v1
2364; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
2365; GFX9-NEXT:    v_subrev_u32_e32 v2, s2, v0
2366; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v0
2367; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
2368; GFX9-NEXT:    v_subrev_u32_e32 v2, s2, v0
2369; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v0
2370; GFX9-NEXT:    s_ashr_i32 s2, s10, 31
2371; GFX9-NEXT:    s_add_i32 s4, s10, s2
2372; GFX9-NEXT:    s_xor_b32 s2, s4, s2
2373; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
2374; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, s2
2375; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s3
2376; GFX9-NEXT:    v_xor_b32_e32 v0, s8, v0
2377; GFX9-NEXT:    v_subrev_u32_e32 v0, s8, v0
2378; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v2
2379; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v1
2380; GFX9-NEXT:    v_subrev_u32_e32 v3, s3, v1
2381; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
2382; GFX9-NEXT:    v_mul_f32_e32 v2, s13, v2
2383; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
2384; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
2385; GFX9-NEXT:    v_subrev_u32_e32 v3, s3, v1
2386; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
2387; GFX9-NEXT:    s_sub_i32 s3, 0, s2
2388; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
2389; GFX9-NEXT:    v_mul_lo_u32 v3, s3, v2
2390; GFX9-NEXT:    s_ashr_i32 s3, s11, 31
2391; GFX9-NEXT:    s_add_i32 s4, s11, s3
2392; GFX9-NEXT:    s_xor_b32 s3, s4, s3
2393; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s3
2394; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v3
2395; GFX9-NEXT:    s_ashr_i32 s4, s6, 31
2396; GFX9-NEXT:    s_add_i32 s5, s6, s4
2397; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v5
2398; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
2399; GFX9-NEXT:    s_xor_b32 s5, s5, s4
2400; GFX9-NEXT:    v_mul_hi_u32 v2, s5, v2
2401; GFX9-NEXT:    v_mul_f32_e32 v3, s13, v5
2402; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
2403; GFX9-NEXT:    s_sub_i32 s6, 0, s3
2404; GFX9-NEXT:    v_mul_lo_u32 v2, v2, s2
2405; GFX9-NEXT:    v_xor_b32_e32 v1, s9, v1
2406; GFX9-NEXT:    v_mul_lo_u32 v5, s6, v3
2407; GFX9-NEXT:    v_subrev_u32_e32 v1, s9, v1
2408; GFX9-NEXT:    v_sub_u32_e32 v2, s5, v2
2409; GFX9-NEXT:    s_ashr_i32 s5, s7, 31
2410; GFX9-NEXT:    v_mul_hi_u32 v5, v3, v5
2411; GFX9-NEXT:    s_add_i32 s6, s7, s5
2412; GFX9-NEXT:    s_xor_b32 s6, s6, s5
2413; GFX9-NEXT:    v_subrev_u32_e32 v6, s2, v2
2414; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
2415; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v3
2416; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v2
2417; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
2418; GFX9-NEXT:    v_subrev_u32_e32 v5, s2, v2
2419; GFX9-NEXT:    v_mul_lo_u32 v3, v3, s3
2420; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v2
2421; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
2422; GFX9-NEXT:    v_xor_b32_e32 v2, s4, v2
2423; GFX9-NEXT:    v_sub_u32_e32 v3, s6, v3
2424; GFX9-NEXT:    v_subrev_u32_e32 v5, s3, v3
2425; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v3
2426; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
2427; GFX9-NEXT:    v_subrev_u32_e32 v5, s3, v3
2428; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v3
2429; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
2430; GFX9-NEXT:    v_xor_b32_e32 v3, s5, v3
2431; GFX9-NEXT:    v_subrev_u32_e32 v2, s4, v2
2432; GFX9-NEXT:    v_subrev_u32_e32 v3, s5, v3
2433; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
2434; GFX9-NEXT:    s_endpgm
2435  %r = srem <4 x i32> %x, %y
2436  store <4 x i32> %r, <4 x i32> addrspace(1)* %out
2437  ret void
2438}
2439
2440define amdgpu_kernel void @udiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x, <4 x i16> %y) {
2441; CHECK-LABEL: @udiv_v4i16(
2442; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i16> [[X:%.*]], i64 0
2443; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i16> [[Y:%.*]], i64 0
2444; CHECK-NEXT:    [[TMP3:%.*]] = zext i16 [[TMP1]] to i32
2445; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[TMP2]] to i32
2446; CHECK-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float
2447; CHECK-NEXT:    [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float
2448; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])
2449; CHECK-NEXT:    [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]
2450; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])
2451; CHECK-NEXT:    [[TMP10:%.*]] = fneg fast float [[TMP9]]
2452; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])
2453; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP9]] to i32
2454; CHECK-NEXT:    [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])
2455; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])
2456; CHECK-NEXT:    [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]
2457; CHECK-NEXT:    [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 0
2458; CHECK-NEXT:    [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]
2459; CHECK-NEXT:    [[TMP18:%.*]] = and i32 [[TMP17]], 65535
2460; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i16
2461; CHECK-NEXT:    [[TMP20:%.*]] = insertelement <4 x i16> undef, i16 [[TMP19]], i64 0
2462; CHECK-NEXT:    [[TMP21:%.*]] = extractelement <4 x i16> [[X]], i64 1
2463; CHECK-NEXT:    [[TMP22:%.*]] = extractelement <4 x i16> [[Y]], i64 1
2464; CHECK-NEXT:    [[TMP23:%.*]] = zext i16 [[TMP21]] to i32
2465; CHECK-NEXT:    [[TMP24:%.*]] = zext i16 [[TMP22]] to i32
2466; CHECK-NEXT:    [[TMP25:%.*]] = uitofp i32 [[TMP23]] to float
2467; CHECK-NEXT:    [[TMP26:%.*]] = uitofp i32 [[TMP24]] to float
2468; CHECK-NEXT:    [[TMP27:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP26]])
2469; CHECK-NEXT:    [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]]
2470; CHECK-NEXT:    [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]])
2471; CHECK-NEXT:    [[TMP30:%.*]] = fneg fast float [[TMP29]]
2472; CHECK-NEXT:    [[TMP31:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP30]], float [[TMP26]], float [[TMP25]])
2473; CHECK-NEXT:    [[TMP32:%.*]] = fptoui float [[TMP29]] to i32
2474; CHECK-NEXT:    [[TMP33:%.*]] = call fast float @llvm.fabs.f32(float [[TMP31]])
2475; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.fabs.f32(float [[TMP26]])
2476; CHECK-NEXT:    [[TMP35:%.*]] = fcmp fast oge float [[TMP33]], [[TMP34]]
2477; CHECK-NEXT:    [[TMP36:%.*]] = select i1 [[TMP35]], i32 1, i32 0
2478; CHECK-NEXT:    [[TMP37:%.*]] = add i32 [[TMP32]], [[TMP36]]
2479; CHECK-NEXT:    [[TMP38:%.*]] = and i32 [[TMP37]], 65535
2480; CHECK-NEXT:    [[TMP39:%.*]] = trunc i32 [[TMP38]] to i16
2481; CHECK-NEXT:    [[TMP40:%.*]] = insertelement <4 x i16> [[TMP20]], i16 [[TMP39]], i64 1
2482; CHECK-NEXT:    [[TMP41:%.*]] = extractelement <4 x i16> [[X]], i64 2
2483; CHECK-NEXT:    [[TMP42:%.*]] = extractelement <4 x i16> [[Y]], i64 2
2484; CHECK-NEXT:    [[TMP43:%.*]] = zext i16 [[TMP41]] to i32
2485; CHECK-NEXT:    [[TMP44:%.*]] = zext i16 [[TMP42]] to i32
2486; CHECK-NEXT:    [[TMP45:%.*]] = uitofp i32 [[TMP43]] to float
2487; CHECK-NEXT:    [[TMP46:%.*]] = uitofp i32 [[TMP44]] to float
2488; CHECK-NEXT:    [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]])
2489; CHECK-NEXT:    [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]]
2490; CHECK-NEXT:    [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]])
2491; CHECK-NEXT:    [[TMP50:%.*]] = fneg fast float [[TMP49]]
2492; CHECK-NEXT:    [[TMP51:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP50]], float [[TMP46]], float [[TMP45]])
2493; CHECK-NEXT:    [[TMP52:%.*]] = fptoui float [[TMP49]] to i32
2494; CHECK-NEXT:    [[TMP53:%.*]] = call fast float @llvm.fabs.f32(float [[TMP51]])
2495; CHECK-NEXT:    [[TMP54:%.*]] = call fast float @llvm.fabs.f32(float [[TMP46]])
2496; CHECK-NEXT:    [[TMP55:%.*]] = fcmp fast oge float [[TMP53]], [[TMP54]]
2497; CHECK-NEXT:    [[TMP56:%.*]] = select i1 [[TMP55]], i32 1, i32 0
2498; CHECK-NEXT:    [[TMP57:%.*]] = add i32 [[TMP52]], [[TMP56]]
2499; CHECK-NEXT:    [[TMP58:%.*]] = and i32 [[TMP57]], 65535
2500; CHECK-NEXT:    [[TMP59:%.*]] = trunc i32 [[TMP58]] to i16
2501; CHECK-NEXT:    [[TMP60:%.*]] = insertelement <4 x i16> [[TMP40]], i16 [[TMP59]], i64 2
2502; CHECK-NEXT:    [[TMP61:%.*]] = extractelement <4 x i16> [[X]], i64 3
2503; CHECK-NEXT:    [[TMP62:%.*]] = extractelement <4 x i16> [[Y]], i64 3
2504; CHECK-NEXT:    [[TMP63:%.*]] = zext i16 [[TMP61]] to i32
2505; CHECK-NEXT:    [[TMP64:%.*]] = zext i16 [[TMP62]] to i32
2506; CHECK-NEXT:    [[TMP65:%.*]] = uitofp i32 [[TMP63]] to float
2507; CHECK-NEXT:    [[TMP66:%.*]] = uitofp i32 [[TMP64]] to float
2508; CHECK-NEXT:    [[TMP67:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP66]])
2509; CHECK-NEXT:    [[TMP68:%.*]] = fmul fast float [[TMP65]], [[TMP67]]
2510; CHECK-NEXT:    [[TMP69:%.*]] = call fast float @llvm.trunc.f32(float [[TMP68]])
2511; CHECK-NEXT:    [[TMP70:%.*]] = fneg fast float [[TMP69]]
2512; CHECK-NEXT:    [[TMP71:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP70]], float [[TMP66]], float [[TMP65]])
2513; CHECK-NEXT:    [[TMP72:%.*]] = fptoui float [[TMP69]] to i32
2514; CHECK-NEXT:    [[TMP73:%.*]] = call fast float @llvm.fabs.f32(float [[TMP71]])
2515; CHECK-NEXT:    [[TMP74:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]])
2516; CHECK-NEXT:    [[TMP75:%.*]] = fcmp fast oge float [[TMP73]], [[TMP74]]
2517; CHECK-NEXT:    [[TMP76:%.*]] = select i1 [[TMP75]], i32 1, i32 0
2518; CHECK-NEXT:    [[TMP77:%.*]] = add i32 [[TMP72]], [[TMP76]]
2519; CHECK-NEXT:    [[TMP78:%.*]] = and i32 [[TMP77]], 65535
2520; CHECK-NEXT:    [[TMP79:%.*]] = trunc i32 [[TMP78]] to i16
2521; CHECK-NEXT:    [[TMP80:%.*]] = insertelement <4 x i16> [[TMP60]], i16 [[TMP79]], i64 3
2522; CHECK-NEXT:    store <4 x i16> [[TMP80]], <4 x i16> addrspace(1)* [[OUT:%.*]], align 8
2523; CHECK-NEXT:    ret void
2524;
2525; GFX6-LABEL: udiv_v4i16:
2526; GFX6:       ; %bb.0:
2527; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
2528; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
2529; GFX6-NEXT:    s_mov_b32 s8, 0xffff
2530; GFX6-NEXT:    s_mov_b32 s3, 0xf000
2531; GFX6-NEXT:    s_mov_b32 s2, -1
2532; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
2533; GFX6-NEXT:    s_and_b32 s9, s6, s8
2534; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s9
2535; GFX6-NEXT:    s_lshr_b32 s9, s4, 16
2536; GFX6-NEXT:    s_and_b32 s4, s4, s8
2537; GFX6-NEXT:    s_lshr_b32 s6, s6, 16
2538; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s4
2539; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
2540; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s6
2541; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s9
2542; GFX6-NEXT:    s_and_b32 s6, s7, s8
2543; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
2544; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
2545; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
2546; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
2547; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
2548; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
2549; GFX6-NEXT:    v_mul_f32_e32 v1, v4, v5
2550; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
2551; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
2552; GFX6-NEXT:    v_mad_f32 v2, -v1, v3, v4
2553; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s6
2554; GFX6-NEXT:    s_lshr_b32 s4, s5, 16
2555; GFX6-NEXT:    s_lshr_b32 s10, s7, 16
2556; GFX6-NEXT:    s_and_b32 s5, s5, s8
2557; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
2558; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s5
2559; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v4
2560; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
2561; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s10
2562; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v1, vcc
2563; GFX6-NEXT:    v_mul_f32_e32 v1, v5, v6
2564; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s4
2565; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v3
2566; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
2567; GFX6-NEXT:    v_mad_f32 v5, -v1, v4, v5
2568; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
2569; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v4
2570; GFX6-NEXT:    v_mul_f32_e32 v4, v6, v7
2571; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
2572; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v4
2573; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
2574; GFX6-NEXT:    v_mad_f32 v4, -v4, v3, v6
2575; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v3
2576; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
2577; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
2578; GFX6-NEXT:    v_and_b32_e32 v1, s8, v1
2579; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
2580; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
2581; GFX6-NEXT:    v_or_b32_e32 v1, v1, v3
2582; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
2583; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2584; GFX6-NEXT:    s_endpgm
2585;
2586; GFX9-LABEL: udiv_v4i16:
2587; GFX9:       ; %bb.0:
2588; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
2589; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
2590; GFX9-NEXT:    s_mov_b32 s0, 0xffff
2591; GFX9-NEXT:    v_mov_b32_e32 v2, 0
2592; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
2593; GFX9-NEXT:    s_and_b32 s8, s6, s0
2594; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
2595; GFX9-NEXT:    s_lshr_b32 s1, s4, 16
2596; GFX9-NEXT:    s_and_b32 s4, s4, s0
2597; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s4
2598; GFX9-NEXT:    s_lshr_b32 s4, s6, 16
2599; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
2600; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s4
2601; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s1
2602; GFX9-NEXT:    s_and_b32 s1, s7, s0
2603; GFX9-NEXT:    v_mul_f32_e32 v3, v1, v3
2604; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v4
2605; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
2606; GFX9-NEXT:    v_mad_f32 v1, -v3, v0, v1
2607; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
2608; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
2609; GFX9-NEXT:    v_mul_f32_e32 v1, v5, v6
2610; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
2611; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
2612; GFX9-NEXT:    v_mad_f32 v3, -v1, v4, v5
2613; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s1
2614; GFX9-NEXT:    s_lshr_b32 s6, s7, 16
2615; GFX9-NEXT:    s_and_b32 s0, s5, s0
2616; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
2617; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
2618; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v5
2619; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v4
2620; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s6
2621; GFX9-NEXT:    s_lshr_b32 s8, s5, 16
2622; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
2623; GFX9-NEXT:    v_mul_f32_e32 v1, v6, v7
2624; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s8
2625; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v4
2626; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
2627; GFX9-NEXT:    v_mad_f32 v6, -v1, v5, v6
2628; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
2629; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, v5
2630; GFX9-NEXT:    v_mul_f32_e32 v5, v7, v8
2631; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
2632; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v5
2633; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
2634; GFX9-NEXT:    v_mad_f32 v5, -v5, v4, v7
2635; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v4
2636; GFX9-NEXT:    v_mov_b32_e32 v5, 0xffff
2637; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v6, vcc
2638; GFX9-NEXT:    v_and_b32_e32 v1, v5, v1
2639; GFX9-NEXT:    v_and_b32_e32 v0, v5, v0
2640; GFX9-NEXT:    v_lshl_or_b32 v1, v4, 16, v1
2641; GFX9-NEXT:    v_lshl_or_b32 v0, v3, 16, v0
2642; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
2643; GFX9-NEXT:    s_endpgm
2644  %r = udiv <4 x i16> %x, %y
2645  store <4 x i16> %r, <4 x i16> addrspace(1)* %out
2646  ret void
2647}
2648
2649define amdgpu_kernel void @urem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x, <4 x i16> %y) {
2650; CHECK-LABEL: @urem_v4i16(
2651; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i16> [[X:%.*]], i64 0
2652; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i16> [[Y:%.*]], i64 0
2653; CHECK-NEXT:    [[TMP3:%.*]] = zext i16 [[TMP1]] to i32
2654; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[TMP2]] to i32
2655; CHECK-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float
2656; CHECK-NEXT:    [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float
2657; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])
2658; CHECK-NEXT:    [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]
2659; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])
2660; CHECK-NEXT:    [[TMP10:%.*]] = fneg fast float [[TMP9]]
2661; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])
2662; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP9]] to i32
2663; CHECK-NEXT:    [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])
2664; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])
2665; CHECK-NEXT:    [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]
2666; CHECK-NEXT:    [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 0
2667; CHECK-NEXT:    [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]
2668; CHECK-NEXT:    [[TMP18:%.*]] = mul i32 [[TMP17]], [[TMP4]]
2669; CHECK-NEXT:    [[TMP19:%.*]] = sub i32 [[TMP3]], [[TMP18]]
2670; CHECK-NEXT:    [[TMP20:%.*]] = and i32 [[TMP19]], 65535
2671; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i16
2672; CHECK-NEXT:    [[TMP22:%.*]] = insertelement <4 x i16> undef, i16 [[TMP21]], i64 0
2673; CHECK-NEXT:    [[TMP23:%.*]] = extractelement <4 x i16> [[X]], i64 1
2674; CHECK-NEXT:    [[TMP24:%.*]] = extractelement <4 x i16> [[Y]], i64 1
2675; CHECK-NEXT:    [[TMP25:%.*]] = zext i16 [[TMP23]] to i32
2676; CHECK-NEXT:    [[TMP26:%.*]] = zext i16 [[TMP24]] to i32
2677; CHECK-NEXT:    [[TMP27:%.*]] = uitofp i32 [[TMP25]] to float
2678; CHECK-NEXT:    [[TMP28:%.*]] = uitofp i32 [[TMP26]] to float
2679; CHECK-NEXT:    [[TMP29:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP28]])
2680; CHECK-NEXT:    [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]]
2681; CHECK-NEXT:    [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]])
2682; CHECK-NEXT:    [[TMP32:%.*]] = fneg fast float [[TMP31]]
2683; CHECK-NEXT:    [[TMP33:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP32]], float [[TMP28]], float [[TMP27]])
2684; CHECK-NEXT:    [[TMP34:%.*]] = fptoui float [[TMP31]] to i32
2685; CHECK-NEXT:    [[TMP35:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
2686; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.fabs.f32(float [[TMP28]])
2687; CHECK-NEXT:    [[TMP37:%.*]] = fcmp fast oge float [[TMP35]], [[TMP36]]
2688; CHECK-NEXT:    [[TMP38:%.*]] = select i1 [[TMP37]], i32 1, i32 0
2689; CHECK-NEXT:    [[TMP39:%.*]] = add i32 [[TMP34]], [[TMP38]]
2690; CHECK-NEXT:    [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP26]]
2691; CHECK-NEXT:    [[TMP41:%.*]] = sub i32 [[TMP25]], [[TMP40]]
2692; CHECK-NEXT:    [[TMP42:%.*]] = and i32 [[TMP41]], 65535
2693; CHECK-NEXT:    [[TMP43:%.*]] = trunc i32 [[TMP42]] to i16
2694; CHECK-NEXT:    [[TMP44:%.*]] = insertelement <4 x i16> [[TMP22]], i16 [[TMP43]], i64 1
2695; CHECK-NEXT:    [[TMP45:%.*]] = extractelement <4 x i16> [[X]], i64 2
2696; CHECK-NEXT:    [[TMP46:%.*]] = extractelement <4 x i16> [[Y]], i64 2
2697; CHECK-NEXT:    [[TMP47:%.*]] = zext i16 [[TMP45]] to i32
2698; CHECK-NEXT:    [[TMP48:%.*]] = zext i16 [[TMP46]] to i32
2699; CHECK-NEXT:    [[TMP49:%.*]] = uitofp i32 [[TMP47]] to float
2700; CHECK-NEXT:    [[TMP50:%.*]] = uitofp i32 [[TMP48]] to float
2701; CHECK-NEXT:    [[TMP51:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP50]])
2702; CHECK-NEXT:    [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]]
2703; CHECK-NEXT:    [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]])
2704; CHECK-NEXT:    [[TMP54:%.*]] = fneg fast float [[TMP53]]
2705; CHECK-NEXT:    [[TMP55:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP54]], float [[TMP50]], float [[TMP49]])
2706; CHECK-NEXT:    [[TMP56:%.*]] = fptoui float [[TMP53]] to i32
2707; CHECK-NEXT:    [[TMP57:%.*]] = call fast float @llvm.fabs.f32(float [[TMP55]])
2708; CHECK-NEXT:    [[TMP58:%.*]] = call fast float @llvm.fabs.f32(float [[TMP50]])
2709; CHECK-NEXT:    [[TMP59:%.*]] = fcmp fast oge float [[TMP57]], [[TMP58]]
2710; CHECK-NEXT:    [[TMP60:%.*]] = select i1 [[TMP59]], i32 1, i32 0
2711; CHECK-NEXT:    [[TMP61:%.*]] = add i32 [[TMP56]], [[TMP60]]
2712; CHECK-NEXT:    [[TMP62:%.*]] = mul i32 [[TMP61]], [[TMP48]]
2713; CHECK-NEXT:    [[TMP63:%.*]] = sub i32 [[TMP47]], [[TMP62]]
2714; CHECK-NEXT:    [[TMP64:%.*]] = and i32 [[TMP63]], 65535
2715; CHECK-NEXT:    [[TMP65:%.*]] = trunc i32 [[TMP64]] to i16
2716; CHECK-NEXT:    [[TMP66:%.*]] = insertelement <4 x i16> [[TMP44]], i16 [[TMP65]], i64 2
2717; CHECK-NEXT:    [[TMP67:%.*]] = extractelement <4 x i16> [[X]], i64 3
2718; CHECK-NEXT:    [[TMP68:%.*]] = extractelement <4 x i16> [[Y]], i64 3
2719; CHECK-NEXT:    [[TMP69:%.*]] = zext i16 [[TMP67]] to i32
2720; CHECK-NEXT:    [[TMP70:%.*]] = zext i16 [[TMP68]] to i32
2721; CHECK-NEXT:    [[TMP71:%.*]] = uitofp i32 [[TMP69]] to float
2722; CHECK-NEXT:    [[TMP72:%.*]] = uitofp i32 [[TMP70]] to float
2723; CHECK-NEXT:    [[TMP73:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP72]])
2724; CHECK-NEXT:    [[TMP74:%.*]] = fmul fast float [[TMP71]], [[TMP73]]
2725; CHECK-NEXT:    [[TMP75:%.*]] = call fast float @llvm.trunc.f32(float [[TMP74]])
2726; CHECK-NEXT:    [[TMP76:%.*]] = fneg fast float [[TMP75]]
2727; CHECK-NEXT:    [[TMP77:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP76]], float [[TMP72]], float [[TMP71]])
2728; CHECK-NEXT:    [[TMP78:%.*]] = fptoui float [[TMP75]] to i32
2729; CHECK-NEXT:    [[TMP79:%.*]] = call fast float @llvm.fabs.f32(float [[TMP77]])
2730; CHECK-NEXT:    [[TMP80:%.*]] = call fast float @llvm.fabs.f32(float [[TMP72]])
2731; CHECK-NEXT:    [[TMP81:%.*]] = fcmp fast oge float [[TMP79]], [[TMP80]]
2732; CHECK-NEXT:    [[TMP82:%.*]] = select i1 [[TMP81]], i32 1, i32 0
2733; CHECK-NEXT:    [[TMP83:%.*]] = add i32 [[TMP78]], [[TMP82]]
2734; CHECK-NEXT:    [[TMP84:%.*]] = mul i32 [[TMP83]], [[TMP70]]
2735; CHECK-NEXT:    [[TMP85:%.*]] = sub i32 [[TMP69]], [[TMP84]]
2736; CHECK-NEXT:    [[TMP86:%.*]] = and i32 [[TMP85]], 65535
2737; CHECK-NEXT:    [[TMP87:%.*]] = trunc i32 [[TMP86]] to i16
2738; CHECK-NEXT:    [[TMP88:%.*]] = insertelement <4 x i16> [[TMP66]], i16 [[TMP87]], i64 3
2739; CHECK-NEXT:    store <4 x i16> [[TMP88]], <4 x i16> addrspace(1)* [[OUT:%.*]], align 8
2740; CHECK-NEXT:    ret void
2741;
2742; GFX6-LABEL: urem_v4i16:
2743; GFX6:       ; %bb.0:
2744; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
2745; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
2746; GFX6-NEXT:    s_mov_b32 s8, 0xffff
2747; GFX6-NEXT:    s_mov_b32 s3, 0xf000
2748; GFX6-NEXT:    s_mov_b32 s2, -1
2749; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
2750; GFX6-NEXT:    s_and_b32 s9, s6, s8
2751; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s9
2752; GFX6-NEXT:    s_and_b32 s10, s4, s8
2753; GFX6-NEXT:    s_lshr_b32 s11, s6, 16
2754; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s10
2755; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
2756; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s11
2757; GFX6-NEXT:    s_lshr_b32 s9, s4, 16
2758; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s9
2759; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
2760; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
2761; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
2762; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
2763; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
2764; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
2765; GFX6-NEXT:    v_mul_f32_e32 v1, v4, v5
2766; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
2767; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
2768; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v1
2769; GFX6-NEXT:    v_mad_f32 v1, -v1, v3, v4
2770; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s6
2771; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v3
2772; GFX6-NEXT:    s_and_b32 s6, s7, s8
2773; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
2774; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s6
2775; GFX6-NEXT:    s_and_b32 s6, s5, s8
2776; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s11
2777; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s6
2778; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
2779; GFX6-NEXT:    s_lshr_b32 s12, s7, 16
2780; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s9, v1
2781; GFX6-NEXT:    v_mul_f32_e32 v1, v3, v4
2782; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s12
2783; GFX6-NEXT:    s_lshr_b32 s10, s5, 16
2784; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s10
2785; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
2786; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v4
2787; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
2788; GFX6-NEXT:    v_mad_f32 v3, -v1, v2, v3
2789; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
2790; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v2
2791; GFX6-NEXT:    v_mul_f32_e32 v2, v6, v7
2792; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
2793; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v2
2794; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
2795; GFX6-NEXT:    v_mad_f32 v2, -v2, v4, v6
2796; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
2797; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
2798; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s7
2799; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s12
2800; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
2801; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
2802; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s10, v2
2803; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
2804; GFX6-NEXT:    v_and_b32_e32 v1, s8, v1
2805; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
2806; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v5
2807; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
2808; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2809; GFX6-NEXT:    s_endpgm
2810;
2811; GFX9-LABEL: urem_v4i16:
2812; GFX9:       ; %bb.0:
2813; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
2814; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
2815; GFX9-NEXT:    s_mov_b32 s0, 0xffff
2816; GFX9-NEXT:    v_mov_b32_e32 v2, 0
2817; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
2818; GFX9-NEXT:    s_and_b32 s8, s6, s0
2819; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
2820; GFX9-NEXT:    s_and_b32 s9, s4, s0
2821; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
2822; GFX9-NEXT:    s_lshr_b32 s9, s6, 16
2823; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
2824; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s9
2825; GFX9-NEXT:    s_lshr_b32 s1, s4, 16
2826; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s1
2827; GFX9-NEXT:    v_mul_f32_e32 v3, v1, v3
2828; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
2829; GFX9-NEXT:    v_mad_f32 v1, -v3, v0, v1
2830; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
2831; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v4
2832; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
2833; GFX9-NEXT:    s_lshr_b32 s10, s7, 16
2834; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
2835; GFX9-NEXT:    v_mul_f32_e32 v1, v5, v6
2836; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s6
2837; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
2838; GFX9-NEXT:    s_and_b32 s6, s7, s0
2839; GFX9-NEXT:    v_mad_f32 v3, -v1, v4, v5
2840; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s6
2841; GFX9-NEXT:    s_and_b32 s0, s5, s0
2842; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
2843; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v4
2844; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v5
2845; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s10
2846; GFX9-NEXT:    s_lshr_b32 s8, s5, 16
2847; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
2848; GFX9-NEXT:    v_mul_f32_e32 v3, v6, v7
2849; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s8
2850; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v4
2851; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
2852; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
2853; GFX9-NEXT:    v_mad_f32 v6, -v3, v5, v6
2854; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
2855; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, v5
2856; GFX9-NEXT:    v_mul_f32_e32 v5, v7, v8
2857; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
2858; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v5
2859; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
2860; GFX9-NEXT:    v_mad_f32 v5, -v5, v4, v7
2861; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v4
2862; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v6, vcc
2863; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s9
2864; GFX9-NEXT:    v_mul_lo_u32 v3, v3, s7
2865; GFX9-NEXT:    v_mul_lo_u32 v4, v4, s10
2866; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
2867; GFX9-NEXT:    v_sub_u32_e32 v5, s1, v1
2868; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v3
2869; GFX9-NEXT:    v_sub_u32_e32 v3, s8, v4
2870; GFX9-NEXT:    v_mov_b32_e32 v4, 0xffff
2871; GFX9-NEXT:    v_and_b32_e32 v1, v4, v1
2872; GFX9-NEXT:    v_and_b32_e32 v0, v4, v0
2873; GFX9-NEXT:    v_lshl_or_b32 v1, v3, 16, v1
2874; GFX9-NEXT:    v_lshl_or_b32 v0, v5, 16, v0
2875; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
2876; GFX9-NEXT:    s_endpgm
2877  %r = urem <4 x i16> %x, %y
2878  store <4 x i16> %r, <4 x i16> addrspace(1)* %out
2879  ret void
2880}
2881
2882define amdgpu_kernel void @sdiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x, <4 x i16> %y) {
2883; CHECK-LABEL: @sdiv_v4i16(
2884; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i16> [[X:%.*]], i64 0
2885; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i16> [[Y:%.*]], i64 0
2886; CHECK-NEXT:    [[TMP3:%.*]] = sext i16 [[TMP1]] to i32
2887; CHECK-NEXT:    [[TMP4:%.*]] = sext i16 [[TMP2]] to i32
2888; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
2889; CHECK-NEXT:    [[TMP6:%.*]] = ashr i32 [[TMP5]], 30
2890; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], 1
2891; CHECK-NEXT:    [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float
2892; CHECK-NEXT:    [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float
2893; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
2894; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]
2895; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])
2896; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
2897; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
2898; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
2899; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
2900; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
2901; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
2902; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
2903; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
2904; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 16
2905; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 16
2906; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i16
2907; CHECK-NEXT:    [[TMP24:%.*]] = insertelement <4 x i16> undef, i16 [[TMP23]], i64 0
2908; CHECK-NEXT:    [[TMP25:%.*]] = extractelement <4 x i16> [[X]], i64 1
2909; CHECK-NEXT:    [[TMP26:%.*]] = extractelement <4 x i16> [[Y]], i64 1
2910; CHECK-NEXT:    [[TMP27:%.*]] = sext i16 [[TMP25]] to i32
2911; CHECK-NEXT:    [[TMP28:%.*]] = sext i16 [[TMP26]] to i32
2912; CHECK-NEXT:    [[TMP29:%.*]] = xor i32 [[TMP27]], [[TMP28]]
2913; CHECK-NEXT:    [[TMP30:%.*]] = ashr i32 [[TMP29]], 30
2914; CHECK-NEXT:    [[TMP31:%.*]] = or i32 [[TMP30]], 1
2915; CHECK-NEXT:    [[TMP32:%.*]] = sitofp i32 [[TMP27]] to float
2916; CHECK-NEXT:    [[TMP33:%.*]] = sitofp i32 [[TMP28]] to float
2917; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])
2918; CHECK-NEXT:    [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]]
2919; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]])
2920; CHECK-NEXT:    [[TMP37:%.*]] = fneg fast float [[TMP36]]
2921; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]])
2922; CHECK-NEXT:    [[TMP39:%.*]] = fptosi float [[TMP36]] to i32
2923; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]])
2924; CHECK-NEXT:    [[TMP41:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
2925; CHECK-NEXT:    [[TMP42:%.*]] = fcmp fast oge float [[TMP40]], [[TMP41]]
2926; CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP31]], i32 0
2927; CHECK-NEXT:    [[TMP44:%.*]] = add i32 [[TMP39]], [[TMP43]]
2928; CHECK-NEXT:    [[TMP45:%.*]] = shl i32 [[TMP44]], 16
2929; CHECK-NEXT:    [[TMP46:%.*]] = ashr i32 [[TMP45]], 16
2930; CHECK-NEXT:    [[TMP47:%.*]] = trunc i32 [[TMP46]] to i16
2931; CHECK-NEXT:    [[TMP48:%.*]] = insertelement <4 x i16> [[TMP24]], i16 [[TMP47]], i64 1
2932; CHECK-NEXT:    [[TMP49:%.*]] = extractelement <4 x i16> [[X]], i64 2
2933; CHECK-NEXT:    [[TMP50:%.*]] = extractelement <4 x i16> [[Y]], i64 2
2934; CHECK-NEXT:    [[TMP51:%.*]] = sext i16 [[TMP49]] to i32
2935; CHECK-NEXT:    [[TMP52:%.*]] = sext i16 [[TMP50]] to i32
2936; CHECK-NEXT:    [[TMP53:%.*]] = xor i32 [[TMP51]], [[TMP52]]
2937; CHECK-NEXT:    [[TMP54:%.*]] = ashr i32 [[TMP53]], 30
2938; CHECK-NEXT:    [[TMP55:%.*]] = or i32 [[TMP54]], 1
2939; CHECK-NEXT:    [[TMP56:%.*]] = sitofp i32 [[TMP51]] to float
2940; CHECK-NEXT:    [[TMP57:%.*]] = sitofp i32 [[TMP52]] to float
2941; CHECK-NEXT:    [[TMP58:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP57]])
2942; CHECK-NEXT:    [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]]
2943; CHECK-NEXT:    [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]])
2944; CHECK-NEXT:    [[TMP61:%.*]] = fneg fast float [[TMP60]]
2945; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]])
2946; CHECK-NEXT:    [[TMP63:%.*]] = fptosi float [[TMP60]] to i32
2947; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]])
2948; CHECK-NEXT:    [[TMP65:%.*]] = call fast float @llvm.fabs.f32(float [[TMP57]])
2949; CHECK-NEXT:    [[TMP66:%.*]] = fcmp fast oge float [[TMP64]], [[TMP65]]
2950; CHECK-NEXT:    [[TMP67:%.*]] = select i1 [[TMP66]], i32 [[TMP55]], i32 0
2951; CHECK-NEXT:    [[TMP68:%.*]] = add i32 [[TMP63]], [[TMP67]]
2952; CHECK-NEXT:    [[TMP69:%.*]] = shl i32 [[TMP68]], 16
2953; CHECK-NEXT:    [[TMP70:%.*]] = ashr i32 [[TMP69]], 16
2954; CHECK-NEXT:    [[TMP71:%.*]] = trunc i32 [[TMP70]] to i16
2955; CHECK-NEXT:    [[TMP72:%.*]] = insertelement <4 x i16> [[TMP48]], i16 [[TMP71]], i64 2
2956; CHECK-NEXT:    [[TMP73:%.*]] = extractelement <4 x i16> [[X]], i64 3
2957; CHECK-NEXT:    [[TMP74:%.*]] = extractelement <4 x i16> [[Y]], i64 3
2958; CHECK-NEXT:    [[TMP75:%.*]] = sext i16 [[TMP73]] to i32
2959; CHECK-NEXT:    [[TMP76:%.*]] = sext i16 [[TMP74]] to i32
2960; CHECK-NEXT:    [[TMP77:%.*]] = xor i32 [[TMP75]], [[TMP76]]
2961; CHECK-NEXT:    [[TMP78:%.*]] = ashr i32 [[TMP77]], 30
2962; CHECK-NEXT:    [[TMP79:%.*]] = or i32 [[TMP78]], 1
2963; CHECK-NEXT:    [[TMP80:%.*]] = sitofp i32 [[TMP75]] to float
2964; CHECK-NEXT:    [[TMP81:%.*]] = sitofp i32 [[TMP76]] to float
2965; CHECK-NEXT:    [[TMP82:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP81]])
2966; CHECK-NEXT:    [[TMP83:%.*]] = fmul fast float [[TMP80]], [[TMP82]]
2967; CHECK-NEXT:    [[TMP84:%.*]] = call fast float @llvm.trunc.f32(float [[TMP83]])
2968; CHECK-NEXT:    [[TMP85:%.*]] = fneg fast float [[TMP84]]
2969; CHECK-NEXT:    [[TMP86:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP85]], float [[TMP81]], float [[TMP80]])
2970; CHECK-NEXT:    [[TMP87:%.*]] = fptosi float [[TMP84]] to i32
2971; CHECK-NEXT:    [[TMP88:%.*]] = call fast float @llvm.fabs.f32(float [[TMP86]])
2972; CHECK-NEXT:    [[TMP89:%.*]] = call fast float @llvm.fabs.f32(float [[TMP81]])
2973; CHECK-NEXT:    [[TMP90:%.*]] = fcmp fast oge float [[TMP88]], [[TMP89]]
2974; CHECK-NEXT:    [[TMP91:%.*]] = select i1 [[TMP90]], i32 [[TMP79]], i32 0
2975; CHECK-NEXT:    [[TMP92:%.*]] = add i32 [[TMP87]], [[TMP91]]
2976; CHECK-NEXT:    [[TMP93:%.*]] = shl i32 [[TMP92]], 16
2977; CHECK-NEXT:    [[TMP94:%.*]] = ashr i32 [[TMP93]], 16
2978; CHECK-NEXT:    [[TMP95:%.*]] = trunc i32 [[TMP94]] to i16
2979; CHECK-NEXT:    [[TMP96:%.*]] = insertelement <4 x i16> [[TMP72]], i16 [[TMP95]], i64 3
2980; CHECK-NEXT:    store <4 x i16> [[TMP96]], <4 x i16> addrspace(1)* [[OUT:%.*]], align 8
2981; CHECK-NEXT:    ret void
2982;
2983; GFX6-LABEL: sdiv_v4i16:
2984; GFX6:       ; %bb.0:
2985; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
2986; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
2987; GFX6-NEXT:    s_mov_b32 s3, 0xf000
2988; GFX6-NEXT:    s_mov_b32 s2, -1
2989; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
2990; GFX6-NEXT:    s_sext_i32_i16 s8, s6
2991; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s8
2992; GFX6-NEXT:    s_sext_i32_i16 s9, s4
2993; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s9
2994; GFX6-NEXT:    s_xor_b32 s8, s9, s8
2995; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
2996; GFX6-NEXT:    s_ashr_i32 s6, s6, 16
2997; GFX6-NEXT:    s_ashr_i32 s8, s8, 30
2998; GFX6-NEXT:    s_or_b32 s8, s8, 1
2999; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
3000; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
3001; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
3002; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
3003; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
3004; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s6
3005; GFX6-NEXT:    v_mov_b32_e32 v3, s8
3006; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
3007; GFX6-NEXT:    s_ashr_i32 s4, s4, 16
3008; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
3009; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s4
3010; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v1
3011; GFX6-NEXT:    s_xor_b32 s4, s4, s6
3012; GFX6-NEXT:    s_ashr_i32 s4, s4, 30
3013; GFX6-NEXT:    s_or_b32 s4, s4, 1
3014; GFX6-NEXT:    v_mul_f32_e32 v3, v2, v3
3015; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
3016; GFX6-NEXT:    v_mad_f32 v2, -v3, v1, v2
3017; GFX6-NEXT:    v_mov_b32_e32 v4, s4
3018; GFX6-NEXT:    s_sext_i32_i16 s4, s7
3019; GFX6-NEXT:    v_cvt_i32_f32_e32 v3, v3
3020; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
3021; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s4
3022; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
3023; GFX6-NEXT:    s_sext_i32_i16 s6, s5
3024; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v1, v3
3025; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s6
3026; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
3027; GFX6-NEXT:    s_xor_b32 s4, s6, s4
3028; GFX6-NEXT:    s_ashr_i32 s4, s4, 30
3029; GFX6-NEXT:    s_or_b32 s4, s4, 1
3030; GFX6-NEXT:    v_mul_f32_e32 v4, v1, v4
3031; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
3032; GFX6-NEXT:    v_mad_f32 v1, -v4, v2, v1
3033; GFX6-NEXT:    v_mov_b32_e32 v5, s4
3034; GFX6-NEXT:    s_ashr_i32 s4, s7, 16
3035; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v4
3036; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v2|
3037; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s4
3038; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
3039; GFX6-NEXT:    s_ashr_i32 s5, s5, 16
3040; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
3041; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s5
3042; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v2
3043; GFX6-NEXT:    s_xor_b32 s4, s5, s4
3044; GFX6-NEXT:    s_ashr_i32 s4, s4, 30
3045; GFX6-NEXT:    s_or_b32 s4, s4, 1
3046; GFX6-NEXT:    v_mul_f32_e32 v5, v4, v5
3047; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
3048; GFX6-NEXT:    v_mad_f32 v4, -v5, v2, v4
3049; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
3050; GFX6-NEXT:    v_mov_b32_e32 v6, s4
3051; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v2|
3052; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v6, vcc
3053; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
3054; GFX6-NEXT:    s_mov_b32 s4, 0xffff
3055; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
3056; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
3057; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
3058; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
3059; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
3060; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
3061; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
3062; GFX6-NEXT:    s_endpgm
3063;
3064; GFX9-LABEL: sdiv_v4i16:
3065; GFX9:       ; %bb.0:
3066; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
3067; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
3068; GFX9-NEXT:    v_mov_b32_e32 v2, 0
3069; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3070; GFX9-NEXT:    s_sext_i32_i16 s0, s6
3071; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s0
3072; GFX9-NEXT:    s_sext_i32_i16 s1, s4
3073; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s1
3074; GFX9-NEXT:    s_xor_b32 s0, s1, s0
3075; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
3076; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3077; GFX9-NEXT:    s_or_b32 s8, s0, 1
3078; GFX9-NEXT:    v_mul_f32_e32 v3, v1, v3
3079; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
3080; GFX9-NEXT:    v_mad_f32 v1, -v3, v0, v1
3081; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
3082; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
3083; GFX9-NEXT:    s_cselect_b32 s0, s8, 0
3084; GFX9-NEXT:    s_ashr_i32 s1, s6, 16
3085; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s1
3086; GFX9-NEXT:    s_ashr_i32 s4, s4, 16
3087; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s4
3088; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
3089; GFX9-NEXT:    v_rcp_iflag_f32_e32 v4, v0
3090; GFX9-NEXT:    v_add_u32_e32 v3, s0, v3
3091; GFX9-NEXT:    v_mul_f32_e32 v4, v1, v4
3092; GFX9-NEXT:    s_xor_b32 s0, s4, s1
3093; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
3094; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3095; GFX9-NEXT:    v_mad_f32 v1, -v4, v0, v1
3096; GFX9-NEXT:    s_or_b32 s4, s0, 1
3097; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
3098; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
3099; GFX9-NEXT:    v_cvt_i32_f32_e32 v4, v4
3100; GFX9-NEXT:    s_sext_i32_i16 s1, s7
3101; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s1
3102; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
3103; GFX9-NEXT:    v_add_u32_e32 v4, s0, v4
3104; GFX9-NEXT:    s_sext_i32_i16 s0, s5
3105; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s0
3106; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v0
3107; GFX9-NEXT:    s_xor_b32 s0, s0, s1
3108; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3109; GFX9-NEXT:    s_or_b32 s4, s0, 1
3110; GFX9-NEXT:    v_mul_f32_e32 v5, v1, v5
3111; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
3112; GFX9-NEXT:    v_mad_f32 v1, -v5, v0, v1
3113; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
3114; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
3115; GFX9-NEXT:    v_cvt_i32_f32_e32 v5, v5
3116; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
3117; GFX9-NEXT:    s_ashr_i32 s1, s7, 16
3118; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s1
3119; GFX9-NEXT:    v_add_u32_e32 v1, s0, v5
3120; GFX9-NEXT:    s_ashr_i32 s0, s5, 16
3121; GFX9-NEXT:    v_cvt_f32_i32_e32 v5, s0
3122; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v0
3123; GFX9-NEXT:    s_xor_b32 s0, s0, s1
3124; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3125; GFX9-NEXT:    s_or_b32 s4, s0, 1
3126; GFX9-NEXT:    v_mul_f32_e32 v6, v5, v6
3127; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
3128; GFX9-NEXT:    v_mad_f32 v5, -v6, v0, v5
3129; GFX9-NEXT:    v_cvt_i32_f32_e32 v6, v6
3130; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v5|, |v0|
3131; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
3132; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
3133; GFX9-NEXT:    v_mov_b32_e32 v5, 0xffff
3134; GFX9-NEXT:    v_add_u32_e32 v0, s0, v6
3135; GFX9-NEXT:    v_and_b32_e32 v1, v5, v1
3136; GFX9-NEXT:    v_lshl_or_b32 v1, v0, 16, v1
3137; GFX9-NEXT:    v_and_b32_e32 v0, v5, v3
3138; GFX9-NEXT:    v_lshl_or_b32 v0, v4, 16, v0
3139; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
3140; GFX9-NEXT:    s_endpgm
3141  %r = sdiv <4 x i16> %x, %y
3142  store <4 x i16> %r, <4 x i16> addrspace(1)* %out
3143  ret void
3144}
3145
3146define amdgpu_kernel void @srem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x, <4 x i16> %y) {
3147; CHECK-LABEL: @srem_v4i16(
3148; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i16> [[X:%.*]], i64 0
3149; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i16> [[Y:%.*]], i64 0
3150; CHECK-NEXT:    [[TMP3:%.*]] = sext i16 [[TMP1]] to i32
3151; CHECK-NEXT:    [[TMP4:%.*]] = sext i16 [[TMP2]] to i32
3152; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
3153; CHECK-NEXT:    [[TMP6:%.*]] = ashr i32 [[TMP5]], 30
3154; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], 1
3155; CHECK-NEXT:    [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float
3156; CHECK-NEXT:    [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float
3157; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
3158; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]
3159; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])
3160; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
3161; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
3162; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
3163; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
3164; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
3165; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
3166; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
3167; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
3168; CHECK-NEXT:    [[TMP21:%.*]] = mul i32 [[TMP20]], [[TMP4]]
3169; CHECK-NEXT:    [[TMP22:%.*]] = sub i32 [[TMP3]], [[TMP21]]
3170; CHECK-NEXT:    [[TMP23:%.*]] = shl i32 [[TMP22]], 16
3171; CHECK-NEXT:    [[TMP24:%.*]] = ashr i32 [[TMP23]], 16
3172; CHECK-NEXT:    [[TMP25:%.*]] = trunc i32 [[TMP24]] to i16
3173; CHECK-NEXT:    [[TMP26:%.*]] = insertelement <4 x i16> undef, i16 [[TMP25]], i64 0
3174; CHECK-NEXT:    [[TMP27:%.*]] = extractelement <4 x i16> [[X]], i64 1
3175; CHECK-NEXT:    [[TMP28:%.*]] = extractelement <4 x i16> [[Y]], i64 1
3176; CHECK-NEXT:    [[TMP29:%.*]] = sext i16 [[TMP27]] to i32
3177; CHECK-NEXT:    [[TMP30:%.*]] = sext i16 [[TMP28]] to i32
3178; CHECK-NEXT:    [[TMP31:%.*]] = xor i32 [[TMP29]], [[TMP30]]
3179; CHECK-NEXT:    [[TMP32:%.*]] = ashr i32 [[TMP31]], 30
3180; CHECK-NEXT:    [[TMP33:%.*]] = or i32 [[TMP32]], 1
3181; CHECK-NEXT:    [[TMP34:%.*]] = sitofp i32 [[TMP29]] to float
3182; CHECK-NEXT:    [[TMP35:%.*]] = sitofp i32 [[TMP30]] to float
3183; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])
3184; CHECK-NEXT:    [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]]
3185; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]])
3186; CHECK-NEXT:    [[TMP39:%.*]] = fneg fast float [[TMP38]]
3187; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]])
3188; CHECK-NEXT:    [[TMP41:%.*]] = fptosi float [[TMP38]] to i32
3189; CHECK-NEXT:    [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]])
3190; CHECK-NEXT:    [[TMP43:%.*]] = call fast float @llvm.fabs.f32(float [[TMP35]])
3191; CHECK-NEXT:    [[TMP44:%.*]] = fcmp fast oge float [[TMP42]], [[TMP43]]
3192; CHECK-NEXT:    [[TMP45:%.*]] = select i1 [[TMP44]], i32 [[TMP33]], i32 0
3193; CHECK-NEXT:    [[TMP46:%.*]] = add i32 [[TMP41]], [[TMP45]]
3194; CHECK-NEXT:    [[TMP47:%.*]] = mul i32 [[TMP46]], [[TMP30]]
3195; CHECK-NEXT:    [[TMP48:%.*]] = sub i32 [[TMP29]], [[TMP47]]
3196; CHECK-NEXT:    [[TMP49:%.*]] = shl i32 [[TMP48]], 16
3197; CHECK-NEXT:    [[TMP50:%.*]] = ashr i32 [[TMP49]], 16
3198; CHECK-NEXT:    [[TMP51:%.*]] = trunc i32 [[TMP50]] to i16
3199; CHECK-NEXT:    [[TMP52:%.*]] = insertelement <4 x i16> [[TMP26]], i16 [[TMP51]], i64 1
3200; CHECK-NEXT:    [[TMP53:%.*]] = extractelement <4 x i16> [[X]], i64 2
3201; CHECK-NEXT:    [[TMP54:%.*]] = extractelement <4 x i16> [[Y]], i64 2
3202; CHECK-NEXT:    [[TMP55:%.*]] = sext i16 [[TMP53]] to i32
3203; CHECK-NEXT:    [[TMP56:%.*]] = sext i16 [[TMP54]] to i32
3204; CHECK-NEXT:    [[TMP57:%.*]] = xor i32 [[TMP55]], [[TMP56]]
3205; CHECK-NEXT:    [[TMP58:%.*]] = ashr i32 [[TMP57]], 30
3206; CHECK-NEXT:    [[TMP59:%.*]] = or i32 [[TMP58]], 1
3207; CHECK-NEXT:    [[TMP60:%.*]] = sitofp i32 [[TMP55]] to float
3208; CHECK-NEXT:    [[TMP61:%.*]] = sitofp i32 [[TMP56]] to float
3209; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP61]])
3210; CHECK-NEXT:    [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]]
3211; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]])
3212; CHECK-NEXT:    [[TMP65:%.*]] = fneg fast float [[TMP64]]
3213; CHECK-NEXT:    [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]])
3214; CHECK-NEXT:    [[TMP67:%.*]] = fptosi float [[TMP64]] to i32
3215; CHECK-NEXT:    [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]])
3216; CHECK-NEXT:    [[TMP69:%.*]] = call fast float @llvm.fabs.f32(float [[TMP61]])
3217; CHECK-NEXT:    [[TMP70:%.*]] = fcmp fast oge float [[TMP68]], [[TMP69]]
3218; CHECK-NEXT:    [[TMP71:%.*]] = select i1 [[TMP70]], i32 [[TMP59]], i32 0
3219; CHECK-NEXT:    [[TMP72:%.*]] = add i32 [[TMP67]], [[TMP71]]
3220; CHECK-NEXT:    [[TMP73:%.*]] = mul i32 [[TMP72]], [[TMP56]]
3221; CHECK-NEXT:    [[TMP74:%.*]] = sub i32 [[TMP55]], [[TMP73]]
3222; CHECK-NEXT:    [[TMP75:%.*]] = shl i32 [[TMP74]], 16
3223; CHECK-NEXT:    [[TMP76:%.*]] = ashr i32 [[TMP75]], 16
3224; CHECK-NEXT:    [[TMP77:%.*]] = trunc i32 [[TMP76]] to i16
3225; CHECK-NEXT:    [[TMP78:%.*]] = insertelement <4 x i16> [[TMP52]], i16 [[TMP77]], i64 2
3226; CHECK-NEXT:    [[TMP79:%.*]] = extractelement <4 x i16> [[X]], i64 3
3227; CHECK-NEXT:    [[TMP80:%.*]] = extractelement <4 x i16> [[Y]], i64 3
3228; CHECK-NEXT:    [[TMP81:%.*]] = sext i16 [[TMP79]] to i32
3229; CHECK-NEXT:    [[TMP82:%.*]] = sext i16 [[TMP80]] to i32
3230; CHECK-NEXT:    [[TMP83:%.*]] = xor i32 [[TMP81]], [[TMP82]]
3231; CHECK-NEXT:    [[TMP84:%.*]] = ashr i32 [[TMP83]], 30
3232; CHECK-NEXT:    [[TMP85:%.*]] = or i32 [[TMP84]], 1
3233; CHECK-NEXT:    [[TMP86:%.*]] = sitofp i32 [[TMP81]] to float
3234; CHECK-NEXT:    [[TMP87:%.*]] = sitofp i32 [[TMP82]] to float
3235; CHECK-NEXT:    [[TMP88:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP87]])
3236; CHECK-NEXT:    [[TMP89:%.*]] = fmul fast float [[TMP86]], [[TMP88]]
3237; CHECK-NEXT:    [[TMP90:%.*]] = call fast float @llvm.trunc.f32(float [[TMP89]])
3238; CHECK-NEXT:    [[TMP91:%.*]] = fneg fast float [[TMP90]]
3239; CHECK-NEXT:    [[TMP92:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP91]], float [[TMP87]], float [[TMP86]])
3240; CHECK-NEXT:    [[TMP93:%.*]] = fptosi float [[TMP90]] to i32
3241; CHECK-NEXT:    [[TMP94:%.*]] = call fast float @llvm.fabs.f32(float [[TMP92]])
3242; CHECK-NEXT:    [[TMP95:%.*]] = call fast float @llvm.fabs.f32(float [[TMP87]])
3243; CHECK-NEXT:    [[TMP96:%.*]] = fcmp fast oge float [[TMP94]], [[TMP95]]
3244; CHECK-NEXT:    [[TMP97:%.*]] = select i1 [[TMP96]], i32 [[TMP85]], i32 0
3245; CHECK-NEXT:    [[TMP98:%.*]] = add i32 [[TMP93]], [[TMP97]]
3246; CHECK-NEXT:    [[TMP99:%.*]] = mul i32 [[TMP98]], [[TMP82]]
3247; CHECK-NEXT:    [[TMP100:%.*]] = sub i32 [[TMP81]], [[TMP99]]
3248; CHECK-NEXT:    [[TMP101:%.*]] = shl i32 [[TMP100]], 16
3249; CHECK-NEXT:    [[TMP102:%.*]] = ashr i32 [[TMP101]], 16
3250; CHECK-NEXT:    [[TMP103:%.*]] = trunc i32 [[TMP102]] to i16
3251; CHECK-NEXT:    [[TMP104:%.*]] = insertelement <4 x i16> [[TMP78]], i16 [[TMP103]], i64 3
3252; CHECK-NEXT:    store <4 x i16> [[TMP104]], <4 x i16> addrspace(1)* [[OUT:%.*]], align 8
3253; CHECK-NEXT:    ret void
3254;
3255; GFX6-LABEL: srem_v4i16:
3256; GFX6:       ; %bb.0:
3257; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
3258; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
3259; GFX6-NEXT:    s_mov_b32 s3, 0xf000
3260; GFX6-NEXT:    s_mov_b32 s2, -1
3261; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
3262; GFX6-NEXT:    s_sext_i32_i16 s8, s6
3263; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s8
3264; GFX6-NEXT:    s_sext_i32_i16 s9, s4
3265; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s9
3266; GFX6-NEXT:    s_xor_b32 s8, s9, s8
3267; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
3268; GFX6-NEXT:    s_ashr_i32 s8, s8, 30
3269; GFX6-NEXT:    s_or_b32 s8, s8, 1
3270; GFX6-NEXT:    v_mov_b32_e32 v3, s8
3271; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
3272; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
3273; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
3274; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
3275; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
3276; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
3277; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
3278; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s6
3279; GFX6-NEXT:    s_ashr_i32 s6, s6, 16
3280; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s6
3281; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
3282; GFX6-NEXT:    s_ashr_i32 s4, s4, 16
3283; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s4
3284; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v1
3285; GFX6-NEXT:    s_xor_b32 s8, s4, s6
3286; GFX6-NEXT:    s_ashr_i32 s8, s8, 30
3287; GFX6-NEXT:    s_or_b32 s8, s8, 1
3288; GFX6-NEXT:    v_mul_f32_e32 v3, v2, v3
3289; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
3290; GFX6-NEXT:    v_mad_f32 v2, -v3, v1, v2
3291; GFX6-NEXT:    v_cvt_i32_f32_e32 v3, v3
3292; GFX6-NEXT:    v_mov_b32_e32 v4, s8
3293; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
3294; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
3295; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
3296; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s6
3297; GFX6-NEXT:    s_sext_i32_i16 s6, s7
3298; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s6
3299; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s4, v1
3300; GFX6-NEXT:    s_sext_i32_i16 s4, s5
3301; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s4
3302; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
3303; GFX6-NEXT:    s_xor_b32 s4, s4, s6
3304; GFX6-NEXT:    s_ashr_i32 s4, s4, 30
3305; GFX6-NEXT:    s_or_b32 s4, s4, 1
3306; GFX6-NEXT:    v_mul_f32_e32 v4, v1, v4
3307; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
3308; GFX6-NEXT:    v_mad_f32 v1, -v4, v2, v1
3309; GFX6-NEXT:    v_mov_b32_e32 v5, s4
3310; GFX6-NEXT:    s_ashr_i32 s4, s7, 16
3311; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v4
3312; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v2|
3313; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s4
3314; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
3315; GFX6-NEXT:    s_ashr_i32 s6, s5, 16
3316; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
3317; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s6
3318; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v2
3319; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s7
3320; GFX6-NEXT:    s_xor_b32 s7, s6, s4
3321; GFX6-NEXT:    s_ashr_i32 s7, s7, 30
3322; GFX6-NEXT:    v_mul_f32_e32 v5, v4, v5
3323; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
3324; GFX6-NEXT:    v_mad_f32 v4, -v5, v2, v4
3325; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
3326; GFX6-NEXT:    s_or_b32 s7, s7, 1
3327; GFX6-NEXT:    v_mov_b32_e32 v6, s7
3328; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v2|
3329; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v6, vcc
3330; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
3331; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s4
3332; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
3333; GFX6-NEXT:    s_mov_b32 s4, 0xffff
3334; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s6, v2
3335; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
3336; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
3337; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
3338; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
3339; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
3340; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
3341; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
3342; GFX6-NEXT:    s_endpgm
3343;
3344; GFX9-LABEL: srem_v4i16:
3345; GFX9:       ; %bb.0:
3346; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
3347; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
3348; GFX9-NEXT:    v_mov_b32_e32 v2, 0
3349; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3350; GFX9-NEXT:    s_sext_i32_i16 s0, s6
3351; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s0
3352; GFX9-NEXT:    s_sext_i32_i16 s1, s4
3353; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s1
3354; GFX9-NEXT:    s_xor_b32 s0, s1, s0
3355; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
3356; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3357; GFX9-NEXT:    s_or_b32 s8, s0, 1
3358; GFX9-NEXT:    v_mul_f32_e32 v3, v1, v3
3359; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
3360; GFX9-NEXT:    v_mad_f32 v1, -v3, v0, v1
3361; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
3362; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
3363; GFX9-NEXT:    s_cselect_b32 s0, s8, 0
3364; GFX9-NEXT:    s_ashr_i32 s9, s6, 16
3365; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
3366; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s9
3367; GFX9-NEXT:    s_ashr_i32 s8, s4, 16
3368; GFX9-NEXT:    v_add_u32_e32 v1, s0, v3
3369; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s8
3370; GFX9-NEXT:    v_rcp_iflag_f32_e32 v4, v0
3371; GFX9-NEXT:    s_xor_b32 s0, s8, s9
3372; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3373; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s6
3374; GFX9-NEXT:    v_mul_f32_e32 v4, v3, v4
3375; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
3376; GFX9-NEXT:    v_mad_f32 v3, -v4, v0, v3
3377; GFX9-NEXT:    v_cvt_i32_f32_e32 v4, v4
3378; GFX9-NEXT:    s_or_b32 s6, s0, 1
3379; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v3|, |v0|
3380; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
3381; GFX9-NEXT:    s_cselect_b32 s0, s6, 0
3382; GFX9-NEXT:    v_add_u32_e32 v0, s0, v4
3383; GFX9-NEXT:    s_sext_i32_i16 s0, s7
3384; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s0
3385; GFX9-NEXT:    s_sext_i32_i16 s1, s5
3386; GFX9-NEXT:    v_cvt_f32_i32_e32 v4, s1
3387; GFX9-NEXT:    s_xor_b32 s0, s1, s0
3388; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v3
3389; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3390; GFX9-NEXT:    s_or_b32 s6, s0, 1
3391; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s9
3392; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
3393; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
3394; GFX9-NEXT:    v_mad_f32 v4, -v5, v3, v4
3395; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v4|, |v3|
3396; GFX9-NEXT:    v_cvt_i32_f32_e32 v5, v5
3397; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
3398; GFX9-NEXT:    s_cselect_b32 s0, s6, 0
3399; GFX9-NEXT:    s_ashr_i32 s6, s7, 16
3400; GFX9-NEXT:    v_cvt_f32_i32_e32 v4, s6
3401; GFX9-NEXT:    v_add_u32_e32 v3, s0, v5
3402; GFX9-NEXT:    v_mul_lo_u32 v3, v3, s7
3403; GFX9-NEXT:    s_ashr_i32 s7, s5, 16
3404; GFX9-NEXT:    v_cvt_f32_i32_e32 v5, s7
3405; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v4
3406; GFX9-NEXT:    s_xor_b32 s0, s7, s6
3407; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3408; GFX9-NEXT:    s_or_b32 s9, s0, 1
3409; GFX9-NEXT:    v_mul_f32_e32 v6, v5, v6
3410; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
3411; GFX9-NEXT:    v_mad_f32 v5, -v6, v4, v5
3412; GFX9-NEXT:    v_cvt_i32_f32_e32 v6, v6
3413; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v5|, |v4|
3414; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
3415; GFX9-NEXT:    s_cselect_b32 s0, s9, 0
3416; GFX9-NEXT:    v_add_u32_e32 v4, s0, v6
3417; GFX9-NEXT:    v_mul_lo_u32 v4, v4, s6
3418; GFX9-NEXT:    v_sub_u32_e32 v5, s4, v1
3419; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v3
3420; GFX9-NEXT:    v_sub_u32_e32 v0, s8, v0
3421; GFX9-NEXT:    v_sub_u32_e32 v3, s7, v4
3422; GFX9-NEXT:    v_mov_b32_e32 v4, 0xffff
3423; GFX9-NEXT:    v_and_b32_e32 v1, v4, v1
3424; GFX9-NEXT:    v_lshl_or_b32 v1, v3, 16, v1
3425; GFX9-NEXT:    v_and_b32_e32 v3, v4, v5
3426; GFX9-NEXT:    v_lshl_or_b32 v0, v0, 16, v3
3427; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
3428; GFX9-NEXT:    s_endpgm
3429  %r = srem <4 x i16> %x, %y
3430  store <4 x i16> %r, <4 x i16> addrspace(1)* %out
3431  ret void
3432}
3433
3434define amdgpu_kernel void @udiv_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) {
3435; CHECK-LABEL: @udiv_i3(
3436; CHECK-NEXT:    [[TMP1:%.*]] = zext i3 [[X:%.*]] to i32
3437; CHECK-NEXT:    [[TMP2:%.*]] = zext i3 [[Y:%.*]] to i32
3438; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
3439; CHECK-NEXT:    [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
3440; CHECK-NEXT:    [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
3441; CHECK-NEXT:    [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
3442; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
3443; CHECK-NEXT:    [[TMP8:%.*]] = fneg fast float [[TMP7]]
3444; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
3445; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
3446; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
3447; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
3448; CHECK-NEXT:    [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
3449; CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
3450; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
3451; CHECK-NEXT:    [[TMP16:%.*]] = and i32 [[TMP15]], 7
3452; CHECK-NEXT:    [[TMP17:%.*]] = trunc i32 [[TMP16]] to i3
3453; CHECK-NEXT:    store i3 [[TMP17]], i3 addrspace(1)* [[OUT:%.*]], align 1
3454; CHECK-NEXT:    ret void
3455;
3456; GFX6-LABEL: udiv_i3:
3457; GFX6:       ; %bb.0:
3458; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
3459; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
3460; GFX6-NEXT:    s_mov_b32 s3, 0xf000
3461; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
3462; GFX6-NEXT:    s_bfe_u32 s2, s4, 0x30008
3463; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v0, s2
3464; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v0
3465; GFX6-NEXT:    s_and_b32 s4, s4, 7
3466; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v2, s4
3467; GFX6-NEXT:    s_mov_b32 s2, -1
3468; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1
3469; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
3470; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v1
3471; GFX6-NEXT:    v_mad_f32 v1, -v1, v0, v2
3472; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
3473; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
3474; GFX6-NEXT:    v_and_b32_e32 v0, 7, v0
3475; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
3476; GFX6-NEXT:    s_endpgm
3477;
3478; GFX9-LABEL: udiv_i3:
3479; GFX9:       ; %bb.0:
3480; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
3481; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
3482; GFX9-NEXT:    v_mov_b32_e32 v2, 0
3483; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3484; GFX9-NEXT:    s_bfe_u32 s0, s4, 0x30008
3485; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, s0
3486; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
3487; GFX9-NEXT:    s_and_b32 s0, s4, 7
3488; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v3, s0
3489; GFX9-NEXT:    v_mul_f32_e32 v1, v3, v1
3490; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
3491; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v1
3492; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v3
3493; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
3494; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v4, vcc
3495; GFX9-NEXT:    v_and_b32_e32 v0, 7, v0
3496; GFX9-NEXT:    global_store_byte v2, v0, s[2:3]
3497; GFX9-NEXT:    s_endpgm
3498  %r = udiv i3 %x, %y
3499  store i3 %r, i3 addrspace(1)* %out
3500  ret void
3501}
3502
3503define amdgpu_kernel void @urem_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) {
3504; CHECK-LABEL: @urem_i3(
3505; CHECK-NEXT:    [[TMP1:%.*]] = zext i3 [[X:%.*]] to i32
3506; CHECK-NEXT:    [[TMP2:%.*]] = zext i3 [[Y:%.*]] to i32
3507; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
3508; CHECK-NEXT:    [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
3509; CHECK-NEXT:    [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
3510; CHECK-NEXT:    [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
3511; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
3512; CHECK-NEXT:    [[TMP8:%.*]] = fneg fast float [[TMP7]]
3513; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
3514; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
3515; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
3516; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
3517; CHECK-NEXT:    [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
3518; CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
3519; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
3520; CHECK-NEXT:    [[TMP16:%.*]] = mul i32 [[TMP15]], [[TMP2]]
3521; CHECK-NEXT:    [[TMP17:%.*]] = sub i32 [[TMP1]], [[TMP16]]
3522; CHECK-NEXT:    [[TMP18:%.*]] = and i32 [[TMP17]], 7
3523; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i3
3524; CHECK-NEXT:    store i3 [[TMP19]], i3 addrspace(1)* [[OUT:%.*]], align 1
3525; CHECK-NEXT:    ret void
3526;
3527; GFX6-LABEL: urem_i3:
3528; GFX6:       ; %bb.0:
3529; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
3530; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
3531; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
3532; GFX6-NEXT:    s_bfe_u32 s2, s4, 0x30008
3533; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v0, s2
3534; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v0
3535; GFX6-NEXT:    s_and_b32 s3, s4, 7
3536; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v2, s3
3537; GFX6-NEXT:    s_lshr_b32 s2, s4, 8
3538; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1
3539; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
3540; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v1
3541; GFX6-NEXT:    v_mad_f32 v1, -v1, v0, v2
3542; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
3543; GFX6-NEXT:    s_mov_b32 s3, 0xf000
3544; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
3545; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
3546; GFX6-NEXT:    s_mov_b32 s2, -1
3547; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
3548; GFX6-NEXT:    v_and_b32_e32 v0, 7, v0
3549; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
3550; GFX6-NEXT:    s_endpgm
3551;
3552; GFX9-LABEL: urem_i3:
3553; GFX9:       ; %bb.0:
3554; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
3555; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3556; GFX9-NEXT:    s_bfe_u32 s3, s2, 0x30008
3557; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, s3
3558; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
3559; GFX9-NEXT:    s_and_b32 s4, s2, 7
3560; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v2, s4
3561; GFX9-NEXT:    s_lshr_b32 s3, s2, 8
3562; GFX9-NEXT:    v_mul_f32_e32 v1, v2, v1
3563; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
3564; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v1
3565; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v2
3566; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
3567; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
3568; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
3569; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
3570; GFX9-NEXT:    v_mov_b32_e32 v1, 0
3571; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
3572; GFX9-NEXT:    v_and_b32_e32 v0, 7, v0
3573; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3574; GFX9-NEXT:    global_store_byte v1, v0, s[0:1]
3575; GFX9-NEXT:    s_endpgm
3576  %r = urem i3 %x, %y
3577  store i3 %r, i3 addrspace(1)* %out
3578  ret void
3579}
3580
3581define amdgpu_kernel void @sdiv_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) {
3582; CHECK-LABEL: @sdiv_i3(
3583; CHECK-NEXT:    [[TMP1:%.*]] = sext i3 [[X:%.*]] to i32
3584; CHECK-NEXT:    [[TMP2:%.*]] = sext i3 [[Y:%.*]] to i32
3585; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
3586; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
3587; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP4]], 1
3588; CHECK-NEXT:    [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
3589; CHECK-NEXT:    [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
3590; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
3591; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
3592; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
3593; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
3594; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
3595; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
3596; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
3597; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
3598; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
3599; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
3600; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
3601; CHECK-NEXT:    [[TMP19:%.*]] = shl i32 [[TMP18]], 29
3602; CHECK-NEXT:    [[TMP20:%.*]] = ashr i32 [[TMP19]], 29
3603; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i3
3604; CHECK-NEXT:    store i3 [[TMP21]], i3 addrspace(1)* [[OUT:%.*]], align 1
3605; CHECK-NEXT:    ret void
3606;
3607; GFX6-LABEL: sdiv_i3:
3608; GFX6:       ; %bb.0:
3609; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
3610; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
3611; GFX6-NEXT:    s_mov_b32 s3, 0xf000
3612; GFX6-NEXT:    s_mov_b32 s2, -1
3613; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
3614; GFX6-NEXT:    s_bfe_i32 s5, s4, 0x30008
3615; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s5
3616; GFX6-NEXT:    s_bfe_i32 s4, s4, 0x30000
3617; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s4
3618; GFX6-NEXT:    s_xor_b32 s4, s4, s5
3619; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
3620; GFX6-NEXT:    s_ashr_i32 s4, s4, 30
3621; GFX6-NEXT:    s_or_b32 s4, s4, 1
3622; GFX6-NEXT:    v_mov_b32_e32 v3, s4
3623; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
3624; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
3625; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
3626; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
3627; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
3628; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
3629; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
3630; GFX6-NEXT:    v_and_b32_e32 v0, 7, v0
3631; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
3632; GFX6-NEXT:    s_endpgm
3633;
3634; GFX9-LABEL: sdiv_i3:
3635; GFX9:       ; %bb.0:
3636; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
3637; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
3638; GFX9-NEXT:    v_mov_b32_e32 v1, 0
3639; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3640; GFX9-NEXT:    s_bfe_i32 s0, s4, 0x30008
3641; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s0
3642; GFX9-NEXT:    s_bfe_i32 s1, s4, 0x30000
3643; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s1
3644; GFX9-NEXT:    s_xor_b32 s0, s1, s0
3645; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
3646; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3647; GFX9-NEXT:    s_or_b32 s4, s0, 1
3648; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
3649; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
3650; GFX9-NEXT:    v_mad_f32 v2, -v3, v0, v2
3651; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
3652; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
3653; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
3654; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
3655; GFX9-NEXT:    v_add_u32_e32 v0, s0, v3
3656; GFX9-NEXT:    v_and_b32_e32 v0, 7, v0
3657; GFX9-NEXT:    global_store_byte v1, v0, s[2:3]
3658; GFX9-NEXT:    s_endpgm
3659  %r = sdiv i3 %x, %y
3660  store i3 %r, i3 addrspace(1)* %out
3661  ret void
3662}
3663
3664define amdgpu_kernel void @srem_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) {
3665; CHECK-LABEL: @srem_i3(
3666; CHECK-NEXT:    [[TMP1:%.*]] = sext i3 [[X:%.*]] to i32
3667; CHECK-NEXT:    [[TMP2:%.*]] = sext i3 [[Y:%.*]] to i32
3668; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
3669; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
3670; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP4]], 1
3671; CHECK-NEXT:    [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
3672; CHECK-NEXT:    [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
3673; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
3674; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
3675; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
3676; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
3677; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
3678; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
3679; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
3680; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
3681; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
3682; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
3683; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
3684; CHECK-NEXT:    [[TMP19:%.*]] = mul i32 [[TMP18]], [[TMP2]]
3685; CHECK-NEXT:    [[TMP20:%.*]] = sub i32 [[TMP1]], [[TMP19]]
3686; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 29
3687; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 29
3688; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i3
3689; CHECK-NEXT:    store i3 [[TMP23]], i3 addrspace(1)* [[OUT:%.*]], align 1
3690; CHECK-NEXT:    ret void
3691;
3692; GFX6-LABEL: srem_i3:
3693; GFX6:       ; %bb.0:
3694; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
3695; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
3696; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
3697; GFX6-NEXT:    s_bfe_i32 s2, s4, 0x30008
3698; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s2
3699; GFX6-NEXT:    s_bfe_i32 s5, s4, 0x30000
3700; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s5
3701; GFX6-NEXT:    s_xor_b32 s2, s5, s2
3702; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
3703; GFX6-NEXT:    s_ashr_i32 s2, s2, 30
3704; GFX6-NEXT:    s_or_b32 s2, s2, 1
3705; GFX6-NEXT:    v_mov_b32_e32 v3, s2
3706; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
3707; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
3708; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
3709; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
3710; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
3711; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
3712; GFX6-NEXT:    s_lshr_b32 s3, s4, 8
3713; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
3714; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s3
3715; GFX6-NEXT:    s_mov_b32 s3, 0xf000
3716; GFX6-NEXT:    s_mov_b32 s2, -1
3717; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
3718; GFX6-NEXT:    v_and_b32_e32 v0, 7, v0
3719; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
3720; GFX6-NEXT:    s_endpgm
3721;
3722; GFX9-LABEL: srem_i3:
3723; GFX9:       ; %bb.0:
3724; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
3725; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3726; GFX9-NEXT:    s_bfe_i32 s2, s4, 0x30008
3727; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s2
3728; GFX9-NEXT:    s_bfe_i32 s3, s4, 0x30000
3729; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s3
3730; GFX9-NEXT:    s_xor_b32 s2, s3, s2
3731; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
3732; GFX9-NEXT:    s_ashr_i32 s2, s2, 30
3733; GFX9-NEXT:    s_lshr_b32 s5, s4, 8
3734; GFX9-NEXT:    s_or_b32 s6, s2, 1
3735; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
3736; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
3737; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
3738; GFX9-NEXT:    v_cvt_i32_f32_e32 v2, v2
3739; GFX9-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|
3740; GFX9-NEXT:    s_and_b64 s[2:3], s[2:3], exec
3741; GFX9-NEXT:    s_cselect_b32 s2, s6, 0
3742; GFX9-NEXT:    v_add_u32_e32 v0, s2, v2
3743; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s5
3744; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
3745; GFX9-NEXT:    v_mov_b32_e32 v1, 0
3746; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
3747; GFX9-NEXT:    v_and_b32_e32 v0, 7, v0
3748; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3749; GFX9-NEXT:    global_store_byte v1, v0, s[0:1]
3750; GFX9-NEXT:    s_endpgm
3751  %r = srem i3 %x, %y
3752  store i3 %r, i3 addrspace(1)* %out
3753  ret void
3754}
3755
3756define amdgpu_kernel void @udiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x, <3 x i16> %y) {
3757; CHECK-LABEL: @udiv_v3i16(
3758; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i16> [[X:%.*]], i64 0
3759; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i16> [[Y:%.*]], i64 0
3760; CHECK-NEXT:    [[TMP3:%.*]] = zext i16 [[TMP1]] to i32
3761; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[TMP2]] to i32
3762; CHECK-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float
3763; CHECK-NEXT:    [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float
3764; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])
3765; CHECK-NEXT:    [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]
3766; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])
3767; CHECK-NEXT:    [[TMP10:%.*]] = fneg fast float [[TMP9]]
3768; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])
3769; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP9]] to i32
3770; CHECK-NEXT:    [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])
3771; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])
3772; CHECK-NEXT:    [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]
3773; CHECK-NEXT:    [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 0
3774; CHECK-NEXT:    [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]
3775; CHECK-NEXT:    [[TMP18:%.*]] = and i32 [[TMP17]], 65535
3776; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i16
3777; CHECK-NEXT:    [[TMP20:%.*]] = insertelement <3 x i16> undef, i16 [[TMP19]], i64 0
3778; CHECK-NEXT:    [[TMP21:%.*]] = extractelement <3 x i16> [[X]], i64 1
3779; CHECK-NEXT:    [[TMP22:%.*]] = extractelement <3 x i16> [[Y]], i64 1
3780; CHECK-NEXT:    [[TMP23:%.*]] = zext i16 [[TMP21]] to i32
3781; CHECK-NEXT:    [[TMP24:%.*]] = zext i16 [[TMP22]] to i32
3782; CHECK-NEXT:    [[TMP25:%.*]] = uitofp i32 [[TMP23]] to float
3783; CHECK-NEXT:    [[TMP26:%.*]] = uitofp i32 [[TMP24]] to float
3784; CHECK-NEXT:    [[TMP27:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP26]])
3785; CHECK-NEXT:    [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]]
3786; CHECK-NEXT:    [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]])
3787; CHECK-NEXT:    [[TMP30:%.*]] = fneg fast float [[TMP29]]
3788; CHECK-NEXT:    [[TMP31:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP30]], float [[TMP26]], float [[TMP25]])
3789; CHECK-NEXT:    [[TMP32:%.*]] = fptoui float [[TMP29]] to i32
3790; CHECK-NEXT:    [[TMP33:%.*]] = call fast float @llvm.fabs.f32(float [[TMP31]])
3791; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.fabs.f32(float [[TMP26]])
3792; CHECK-NEXT:    [[TMP35:%.*]] = fcmp fast oge float [[TMP33]], [[TMP34]]
3793; CHECK-NEXT:    [[TMP36:%.*]] = select i1 [[TMP35]], i32 1, i32 0
3794; CHECK-NEXT:    [[TMP37:%.*]] = add i32 [[TMP32]], [[TMP36]]
3795; CHECK-NEXT:    [[TMP38:%.*]] = and i32 [[TMP37]], 65535
3796; CHECK-NEXT:    [[TMP39:%.*]] = trunc i32 [[TMP38]] to i16
3797; CHECK-NEXT:    [[TMP40:%.*]] = insertelement <3 x i16> [[TMP20]], i16 [[TMP39]], i64 1
3798; CHECK-NEXT:    [[TMP41:%.*]] = extractelement <3 x i16> [[X]], i64 2
3799; CHECK-NEXT:    [[TMP42:%.*]] = extractelement <3 x i16> [[Y]], i64 2
3800; CHECK-NEXT:    [[TMP43:%.*]] = zext i16 [[TMP41]] to i32
3801; CHECK-NEXT:    [[TMP44:%.*]] = zext i16 [[TMP42]] to i32
3802; CHECK-NEXT:    [[TMP45:%.*]] = uitofp i32 [[TMP43]] to float
3803; CHECK-NEXT:    [[TMP46:%.*]] = uitofp i32 [[TMP44]] to float
3804; CHECK-NEXT:    [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]])
3805; CHECK-NEXT:    [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]]
3806; CHECK-NEXT:    [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]])
3807; CHECK-NEXT:    [[TMP50:%.*]] = fneg fast float [[TMP49]]
3808; CHECK-NEXT:    [[TMP51:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP50]], float [[TMP46]], float [[TMP45]])
3809; CHECK-NEXT:    [[TMP52:%.*]] = fptoui float [[TMP49]] to i32
3810; CHECK-NEXT:    [[TMP53:%.*]] = call fast float @llvm.fabs.f32(float [[TMP51]])
3811; CHECK-NEXT:    [[TMP54:%.*]] = call fast float @llvm.fabs.f32(float [[TMP46]])
3812; CHECK-NEXT:    [[TMP55:%.*]] = fcmp fast oge float [[TMP53]], [[TMP54]]
3813; CHECK-NEXT:    [[TMP56:%.*]] = select i1 [[TMP55]], i32 1, i32 0
3814; CHECK-NEXT:    [[TMP57:%.*]] = add i32 [[TMP52]], [[TMP56]]
3815; CHECK-NEXT:    [[TMP58:%.*]] = and i32 [[TMP57]], 65535
3816; CHECK-NEXT:    [[TMP59:%.*]] = trunc i32 [[TMP58]] to i16
3817; CHECK-NEXT:    [[TMP60:%.*]] = insertelement <3 x i16> [[TMP40]], i16 [[TMP59]], i64 2
3818; CHECK-NEXT:    store <3 x i16> [[TMP60]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8
3819; CHECK-NEXT:    ret void
3820;
3821; GFX6-LABEL: udiv_v3i16:
3822; GFX6:       ; %bb.0:
3823; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
3824; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
3825; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
3826; GFX6-NEXT:    s_mov_b32 s8, 0xffff
3827; GFX6-NEXT:    s_mov_b32 s7, 0xf000
3828; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
3829; GFX6-NEXT:    s_and_b32 s6, s2, s8
3830; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s6
3831; GFX6-NEXT:    s_and_b32 s6, s0, s8
3832; GFX6-NEXT:    s_lshr_b32 s2, s2, 16
3833; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s6
3834; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
3835; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s2
3836; GFX6-NEXT:    s_lshr_b32 s0, s0, 16
3837; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s0
3838; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
3839; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
3840; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
3841; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
3842; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
3843; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
3844; GFX6-NEXT:    v_mul_f32_e32 v1, v4, v5
3845; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
3846; GFX6-NEXT:    s_and_b32 s0, s3, s8
3847; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
3848; GFX6-NEXT:    v_mad_f32 v2, -v1, v3, v4
3849; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s0
3850; GFX6-NEXT:    s_and_b32 s0, s1, s8
3851; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s0
3852; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
3853; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v4
3854; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
3855; GFX6-NEXT:    s_mov_b32 s6, -1
3856; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
3857; GFX6-NEXT:    v_mul_f32_e32 v2, v5, v6
3858; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
3859; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v2
3860; GFX6-NEXT:    v_mad_f32 v2, -v2, v4, v5
3861; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
3862; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
3863; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
3864; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
3865; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
3866; GFX6-NEXT:    buffer_store_short v2, off, s[4:7], 0 offset:4
3867; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
3868; GFX6-NEXT:    s_endpgm
3869;
3870; GFX9-LABEL: udiv_v3i16:
3871; GFX9:       ; %bb.0:
3872; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
3873; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
3874; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x2c
3875; GFX9-NEXT:    s_mov_b32 s0, 0xffff
3876; GFX9-NEXT:    v_mov_b32_e32 v1, 0
3877; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3878; GFX9-NEXT:    s_and_b32 s1, s2, s0
3879; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s1
3880; GFX9-NEXT:    s_and_b32 s1, s6, s0
3881; GFX9-NEXT:    s_lshr_b32 s2, s2, 16
3882; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, s1
3883; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
3884; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s2
3885; GFX9-NEXT:    s_lshr_b32 s1, s6, 16
3886; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s1
3887; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
3888; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v4
3889; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
3890; GFX9-NEXT:    v_mad_f32 v2, -v3, v0, v2
3891; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
3892; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v0
3893; GFX9-NEXT:    v_mul_f32_e32 v2, v5, v6
3894; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
3895; GFX9-NEXT:    s_and_b32 s1, s3, s0
3896; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
3897; GFX9-NEXT:    v_mad_f32 v3, -v2, v4, v5
3898; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s1
3899; GFX9-NEXT:    s_and_b32 s0, s7, s0
3900; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
3901; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
3902; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v5
3903; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v4
3904; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v0
3905; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
3906; GFX9-NEXT:    v_mul_f32_e32 v3, v6, v7
3907; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
3908; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v3
3909; GFX9-NEXT:    v_mad_f32 v3, -v3, v5, v6
3910; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v5
3911; GFX9-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
3912; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
3913; GFX9-NEXT:    global_store_short v1, v3, s[4:5] offset:4
3914; GFX9-NEXT:    global_store_dword v1, v0, s[4:5]
3915; GFX9-NEXT:    s_endpgm
3916  %r = udiv <3 x i16> %x, %y
3917  store <3 x i16> %r, <3 x i16> addrspace(1)* %out
3918  ret void
3919}
3920
3921define amdgpu_kernel void @urem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x, <3 x i16> %y) {
3922; CHECK-LABEL: @urem_v3i16(
3923; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i16> [[X:%.*]], i64 0
3924; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i16> [[Y:%.*]], i64 0
3925; CHECK-NEXT:    [[TMP3:%.*]] = zext i16 [[TMP1]] to i32
3926; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[TMP2]] to i32
3927; CHECK-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float
3928; CHECK-NEXT:    [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float
3929; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])
3930; CHECK-NEXT:    [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]
3931; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])
3932; CHECK-NEXT:    [[TMP10:%.*]] = fneg fast float [[TMP9]]
3933; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])
3934; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP9]] to i32
3935; CHECK-NEXT:    [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])
3936; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])
3937; CHECK-NEXT:    [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]
3938; CHECK-NEXT:    [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 0
3939; CHECK-NEXT:    [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]
3940; CHECK-NEXT:    [[TMP18:%.*]] = mul i32 [[TMP17]], [[TMP4]]
3941; CHECK-NEXT:    [[TMP19:%.*]] = sub i32 [[TMP3]], [[TMP18]]
3942; CHECK-NEXT:    [[TMP20:%.*]] = and i32 [[TMP19]], 65535
3943; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i16
3944; CHECK-NEXT:    [[TMP22:%.*]] = insertelement <3 x i16> undef, i16 [[TMP21]], i64 0
3945; CHECK-NEXT:    [[TMP23:%.*]] = extractelement <3 x i16> [[X]], i64 1
3946; CHECK-NEXT:    [[TMP24:%.*]] = extractelement <3 x i16> [[Y]], i64 1
3947; CHECK-NEXT:    [[TMP25:%.*]] = zext i16 [[TMP23]] to i32
3948; CHECK-NEXT:    [[TMP26:%.*]] = zext i16 [[TMP24]] to i32
3949; CHECK-NEXT:    [[TMP27:%.*]] = uitofp i32 [[TMP25]] to float
3950; CHECK-NEXT:    [[TMP28:%.*]] = uitofp i32 [[TMP26]] to float
3951; CHECK-NEXT:    [[TMP29:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP28]])
3952; CHECK-NEXT:    [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]]
3953; CHECK-NEXT:    [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]])
3954; CHECK-NEXT:    [[TMP32:%.*]] = fneg fast float [[TMP31]]
3955; CHECK-NEXT:    [[TMP33:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP32]], float [[TMP28]], float [[TMP27]])
3956; CHECK-NEXT:    [[TMP34:%.*]] = fptoui float [[TMP31]] to i32
3957; CHECK-NEXT:    [[TMP35:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
3958; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.fabs.f32(float [[TMP28]])
3959; CHECK-NEXT:    [[TMP37:%.*]] = fcmp fast oge float [[TMP35]], [[TMP36]]
3960; CHECK-NEXT:    [[TMP38:%.*]] = select i1 [[TMP37]], i32 1, i32 0
3961; CHECK-NEXT:    [[TMP39:%.*]] = add i32 [[TMP34]], [[TMP38]]
3962; CHECK-NEXT:    [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP26]]
3963; CHECK-NEXT:    [[TMP41:%.*]] = sub i32 [[TMP25]], [[TMP40]]
3964; CHECK-NEXT:    [[TMP42:%.*]] = and i32 [[TMP41]], 65535
3965; CHECK-NEXT:    [[TMP43:%.*]] = trunc i32 [[TMP42]] to i16
3966; CHECK-NEXT:    [[TMP44:%.*]] = insertelement <3 x i16> [[TMP22]], i16 [[TMP43]], i64 1
3967; CHECK-NEXT:    [[TMP45:%.*]] = extractelement <3 x i16> [[X]], i64 2
3968; CHECK-NEXT:    [[TMP46:%.*]] = extractelement <3 x i16> [[Y]], i64 2
3969; CHECK-NEXT:    [[TMP47:%.*]] = zext i16 [[TMP45]] to i32
3970; CHECK-NEXT:    [[TMP48:%.*]] = zext i16 [[TMP46]] to i32
3971; CHECK-NEXT:    [[TMP49:%.*]] = uitofp i32 [[TMP47]] to float
3972; CHECK-NEXT:    [[TMP50:%.*]] = uitofp i32 [[TMP48]] to float
3973; CHECK-NEXT:    [[TMP51:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP50]])
3974; CHECK-NEXT:    [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]]
3975; CHECK-NEXT:    [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]])
3976; CHECK-NEXT:    [[TMP54:%.*]] = fneg fast float [[TMP53]]
3977; CHECK-NEXT:    [[TMP55:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP54]], float [[TMP50]], float [[TMP49]])
3978; CHECK-NEXT:    [[TMP56:%.*]] = fptoui float [[TMP53]] to i32
3979; CHECK-NEXT:    [[TMP57:%.*]] = call fast float @llvm.fabs.f32(float [[TMP55]])
3980; CHECK-NEXT:    [[TMP58:%.*]] = call fast float @llvm.fabs.f32(float [[TMP50]])
3981; CHECK-NEXT:    [[TMP59:%.*]] = fcmp fast oge float [[TMP57]], [[TMP58]]
3982; CHECK-NEXT:    [[TMP60:%.*]] = select i1 [[TMP59]], i32 1, i32 0
3983; CHECK-NEXT:    [[TMP61:%.*]] = add i32 [[TMP56]], [[TMP60]]
3984; CHECK-NEXT:    [[TMP62:%.*]] = mul i32 [[TMP61]], [[TMP48]]
3985; CHECK-NEXT:    [[TMP63:%.*]] = sub i32 [[TMP47]], [[TMP62]]
3986; CHECK-NEXT:    [[TMP64:%.*]] = and i32 [[TMP63]], 65535
3987; CHECK-NEXT:    [[TMP65:%.*]] = trunc i32 [[TMP64]] to i16
3988; CHECK-NEXT:    [[TMP66:%.*]] = insertelement <3 x i16> [[TMP44]], i16 [[TMP65]], i64 2
3989; CHECK-NEXT:    store <3 x i16> [[TMP66]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8
3990; CHECK-NEXT:    ret void
3991;
3992; GFX6-LABEL: urem_v3i16:
3993; GFX6:       ; %bb.0:
3994; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
3995; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
3996; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
3997; GFX6-NEXT:    s_mov_b32 s8, 0xffff
3998; GFX6-NEXT:    s_mov_b32 s7, 0xf000
3999; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
4000; GFX6-NEXT:    s_and_b32 s6, s2, s8
4001; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s6
4002; GFX6-NEXT:    s_and_b32 s6, s0, s8
4003; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s6
4004; GFX6-NEXT:    v_mov_b32_e32 v4, s2
4005; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v0
4006; GFX6-NEXT:    v_alignbit_b32 v4, s3, v4, 16
4007; GFX6-NEXT:    v_and_b32_e32 v5, s8, v4
4008; GFX6-NEXT:    v_mov_b32_e32 v1, s0
4009; GFX6-NEXT:    v_mul_f32_e32 v3, v2, v3
4010; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
4011; GFX6-NEXT:    v_cvt_u32_f32_e32 v6, v3
4012; GFX6-NEXT:    v_mad_f32 v2, -v3, v0, v2
4013; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v0
4014; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, v5
4015; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v6, vcc
4016; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
4017; GFX6-NEXT:    v_alignbit_b32 v1, s1, v1, 16
4018; GFX6-NEXT:    v_and_b32_e32 v3, s8, v1
4019; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, v3
4020; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v2
4021; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
4022; GFX6-NEXT:    s_and_b32 s0, s3, s8
4023; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s0
4024; GFX6-NEXT:    v_mul_f32_e32 v5, v3, v5
4025; GFX6-NEXT:    s_and_b32 s0, s1, s8
4026; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
4027; GFX6-NEXT:    v_cvt_f32_u32_e32 v7, s0
4028; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v6
4029; GFX6-NEXT:    v_mad_f32 v3, -v5, v2, v3
4030; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v5
4031; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v2
4032; GFX6-NEXT:    v_mul_f32_e32 v3, v7, v8
4033; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
4034; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
4035; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v4
4036; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v3
4037; GFX6-NEXT:    v_mad_f32 v3, -v3, v6, v7
4038; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v6
4039; GFX6-NEXT:    s_mov_b32 s6, -1
4040; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
4041; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s3
4042; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v2
4043; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
4044; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s1, v3
4045; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
4046; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
4047; GFX6-NEXT:    buffer_store_short v2, off, s[4:7], 0 offset:4
4048; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
4049; GFX6-NEXT:    s_endpgm
4050;
4051; GFX9-LABEL: urem_v3i16:
4052; GFX9:       ; %bb.0:
4053; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
4054; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
4055; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x24
4056; GFX9-NEXT:    s_mov_b32 s0, 0xffff
4057; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
4058; GFX9-NEXT:    s_and_b32 s1, s2, s0
4059; GFX9-NEXT:    s_and_b32 s8, s4, s0
4060; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
4061; GFX9-NEXT:    s_lshr_b32 s4, s4, 16
4062; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, s4
4063; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s1
4064; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
4065; GFX9-NEXT:    s_lshr_b32 s2, s2, 16
4066; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s2
4067; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v2
4068; GFX9-NEXT:    v_mul_f32_e32 v3, v1, v3
4069; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
4070; GFX9-NEXT:    v_mad_f32 v1, -v3, v0, v1
4071; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
4072; GFX9-NEXT:    v_mul_f32_e32 v1, v4, v5
4073; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
4074; GFX9-NEXT:    s_and_b32 s5, s5, s0
4075; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v3
4076; GFX9-NEXT:    v_mad_f32 v3, -v1, v2, v4
4077; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s5
4078; GFX9-NEXT:    s_and_b32 s0, s3, s0
4079; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v6, vcc
4080; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s0
4081; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v4
4082; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
4083; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v2
4084; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s8
4085; GFX9-NEXT:    v_mul_f32_e32 v2, v5, v6
4086; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
4087; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v2
4088; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
4089; GFX9-NEXT:    v_mad_f32 v2, -v2, v4, v5
4090; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
4091; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v3, vcc
4092; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s4
4093; GFX9-NEXT:    v_mul_lo_u32 v2, v2, s5
4094; GFX9-NEXT:    v_sub_u32_e32 v0, s1, v0
4095; GFX9-NEXT:    v_mov_b32_e32 v3, 0
4096; GFX9-NEXT:    v_sub_u32_e32 v1, s2, v1
4097; GFX9-NEXT:    v_sub_u32_e32 v2, s0, v2
4098; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v0
4099; GFX9-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
4100; GFX9-NEXT:    global_store_short v3, v2, s[6:7] offset:4
4101; GFX9-NEXT:    global_store_dword v3, v0, s[6:7]
4102; GFX9-NEXT:    s_endpgm
4103  %r = urem <3 x i16> %x, %y
4104  store <3 x i16> %r, <3 x i16> addrspace(1)* %out
4105  ret void
4106}
4107
4108define amdgpu_kernel void @sdiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x, <3 x i16> %y) {
4109; CHECK-LABEL: @sdiv_v3i16(
4110; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i16> [[X:%.*]], i64 0
4111; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i16> [[Y:%.*]], i64 0
4112; CHECK-NEXT:    [[TMP3:%.*]] = sext i16 [[TMP1]] to i32
4113; CHECK-NEXT:    [[TMP4:%.*]] = sext i16 [[TMP2]] to i32
4114; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
4115; CHECK-NEXT:    [[TMP6:%.*]] = ashr i32 [[TMP5]], 30
4116; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], 1
4117; CHECK-NEXT:    [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float
4118; CHECK-NEXT:    [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float
4119; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
4120; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]
4121; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])
4122; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
4123; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
4124; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
4125; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
4126; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
4127; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
4128; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
4129; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
4130; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 16
4131; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 16
4132; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i16
4133; CHECK-NEXT:    [[TMP24:%.*]] = insertelement <3 x i16> undef, i16 [[TMP23]], i64 0
4134; CHECK-NEXT:    [[TMP25:%.*]] = extractelement <3 x i16> [[X]], i64 1
4135; CHECK-NEXT:    [[TMP26:%.*]] = extractelement <3 x i16> [[Y]], i64 1
4136; CHECK-NEXT:    [[TMP27:%.*]] = sext i16 [[TMP25]] to i32
4137; CHECK-NEXT:    [[TMP28:%.*]] = sext i16 [[TMP26]] to i32
4138; CHECK-NEXT:    [[TMP29:%.*]] = xor i32 [[TMP27]], [[TMP28]]
4139; CHECK-NEXT:    [[TMP30:%.*]] = ashr i32 [[TMP29]], 30
4140; CHECK-NEXT:    [[TMP31:%.*]] = or i32 [[TMP30]], 1
4141; CHECK-NEXT:    [[TMP32:%.*]] = sitofp i32 [[TMP27]] to float
4142; CHECK-NEXT:    [[TMP33:%.*]] = sitofp i32 [[TMP28]] to float
4143; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])
4144; CHECK-NEXT:    [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]]
4145; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]])
4146; CHECK-NEXT:    [[TMP37:%.*]] = fneg fast float [[TMP36]]
4147; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]])
4148; CHECK-NEXT:    [[TMP39:%.*]] = fptosi float [[TMP36]] to i32
4149; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]])
4150; CHECK-NEXT:    [[TMP41:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
4151; CHECK-NEXT:    [[TMP42:%.*]] = fcmp fast oge float [[TMP40]], [[TMP41]]
4152; CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP31]], i32 0
4153; CHECK-NEXT:    [[TMP44:%.*]] = add i32 [[TMP39]], [[TMP43]]
4154; CHECK-NEXT:    [[TMP45:%.*]] = shl i32 [[TMP44]], 16
4155; CHECK-NEXT:    [[TMP46:%.*]] = ashr i32 [[TMP45]], 16
4156; CHECK-NEXT:    [[TMP47:%.*]] = trunc i32 [[TMP46]] to i16
4157; CHECK-NEXT:    [[TMP48:%.*]] = insertelement <3 x i16> [[TMP24]], i16 [[TMP47]], i64 1
4158; CHECK-NEXT:    [[TMP49:%.*]] = extractelement <3 x i16> [[X]], i64 2
4159; CHECK-NEXT:    [[TMP50:%.*]] = extractelement <3 x i16> [[Y]], i64 2
4160; CHECK-NEXT:    [[TMP51:%.*]] = sext i16 [[TMP49]] to i32
4161; CHECK-NEXT:    [[TMP52:%.*]] = sext i16 [[TMP50]] to i32
4162; CHECK-NEXT:    [[TMP53:%.*]] = xor i32 [[TMP51]], [[TMP52]]
4163; CHECK-NEXT:    [[TMP54:%.*]] = ashr i32 [[TMP53]], 30
4164; CHECK-NEXT:    [[TMP55:%.*]] = or i32 [[TMP54]], 1
4165; CHECK-NEXT:    [[TMP56:%.*]] = sitofp i32 [[TMP51]] to float
4166; CHECK-NEXT:    [[TMP57:%.*]] = sitofp i32 [[TMP52]] to float
4167; CHECK-NEXT:    [[TMP58:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP57]])
4168; CHECK-NEXT:    [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]]
4169; CHECK-NEXT:    [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]])
4170; CHECK-NEXT:    [[TMP61:%.*]] = fneg fast float [[TMP60]]
4171; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]])
4172; CHECK-NEXT:    [[TMP63:%.*]] = fptosi float [[TMP60]] to i32
4173; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]])
4174; CHECK-NEXT:    [[TMP65:%.*]] = call fast float @llvm.fabs.f32(float [[TMP57]])
4175; CHECK-NEXT:    [[TMP66:%.*]] = fcmp fast oge float [[TMP64]], [[TMP65]]
4176; CHECK-NEXT:    [[TMP67:%.*]] = select i1 [[TMP66]], i32 [[TMP55]], i32 0
4177; CHECK-NEXT:    [[TMP68:%.*]] = add i32 [[TMP63]], [[TMP67]]
4178; CHECK-NEXT:    [[TMP69:%.*]] = shl i32 [[TMP68]], 16
4179; CHECK-NEXT:    [[TMP70:%.*]] = ashr i32 [[TMP69]], 16
4180; CHECK-NEXT:    [[TMP71:%.*]] = trunc i32 [[TMP70]] to i16
4181; CHECK-NEXT:    [[TMP72:%.*]] = insertelement <3 x i16> [[TMP48]], i16 [[TMP71]], i64 2
4182; CHECK-NEXT:    store <3 x i16> [[TMP72]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8
4183; CHECK-NEXT:    ret void
4184;
4185; GFX6-LABEL: sdiv_v3i16:
4186; GFX6:       ; %bb.0:
4187; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
4188; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
4189; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
4190; GFX6-NEXT:    s_mov_b32 s7, 0xf000
4191; GFX6-NEXT:    s_mov_b32 s6, -1
4192; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
4193; GFX6-NEXT:    s_sext_i32_i16 s8, s2
4194; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s8
4195; GFX6-NEXT:    s_sext_i32_i16 s9, s0
4196; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s9
4197; GFX6-NEXT:    s_xor_b32 s8, s9, s8
4198; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
4199; GFX6-NEXT:    s_ashr_i32 s2, s2, 16
4200; GFX6-NEXT:    s_ashr_i32 s8, s8, 30
4201; GFX6-NEXT:    s_or_b32 s8, s8, 1
4202; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
4203; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
4204; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
4205; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
4206; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
4207; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s2
4208; GFX6-NEXT:    v_mov_b32_e32 v3, s8
4209; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
4210; GFX6-NEXT:    s_ashr_i32 s0, s0, 16
4211; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
4212; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s0
4213; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v1
4214; GFX6-NEXT:    s_xor_b32 s0, s0, s2
4215; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
4216; GFX6-NEXT:    s_or_b32 s0, s0, 1
4217; GFX6-NEXT:    v_mul_f32_e32 v3, v2, v3
4218; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
4219; GFX6-NEXT:    v_mad_f32 v2, -v3, v1, v2
4220; GFX6-NEXT:    v_mov_b32_e32 v4, s0
4221; GFX6-NEXT:    s_sext_i32_i16 s0, s3
4222; GFX6-NEXT:    v_cvt_i32_f32_e32 v3, v3
4223; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
4224; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s0
4225; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
4226; GFX6-NEXT:    s_sext_i32_i16 s1, s1
4227; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
4228; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s1
4229; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
4230; GFX6-NEXT:    s_xor_b32 s0, s1, s0
4231; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
4232; GFX6-NEXT:    s_or_b32 s0, s0, 1
4233; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
4234; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
4235; GFX6-NEXT:    v_mad_f32 v3, -v4, v2, v3
4236; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v4
4237; GFX6-NEXT:    v_mov_b32_e32 v5, s0
4238; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
4239; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
4240; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
4241; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
4242; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0
4243; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
4244; GFX6-NEXT:    buffer_store_short v2, off, s[4:7], 0 offset:4
4245; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
4246; GFX6-NEXT:    s_endpgm
4247;
4248; GFX9-LABEL: sdiv_v3i16:
4249; GFX9:       ; %bb.0:
4250; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
4251; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
4252; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x24
4253; GFX9-NEXT:    v_mov_b32_e32 v1, 0
4254; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
4255; GFX9-NEXT:    s_sext_i32_i16 s0, s2
4256; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s0
4257; GFX9-NEXT:    s_sext_i32_i16 s1, s4
4258; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s1
4259; GFX9-NEXT:    s_xor_b32 s0, s1, s0
4260; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
4261; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
4262; GFX9-NEXT:    s_or_b32 s8, s0, 1
4263; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
4264; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
4265; GFX9-NEXT:    v_mad_f32 v2, -v3, v0, v2
4266; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
4267; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
4268; GFX9-NEXT:    s_cselect_b32 s0, s8, 0
4269; GFX9-NEXT:    s_ashr_i32 s1, s2, 16
4270; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
4271; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s1
4272; GFX9-NEXT:    s_ashr_i32 s2, s4, 16
4273; GFX9-NEXT:    v_add_u32_e32 v2, s0, v3
4274; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s2
4275; GFX9-NEXT:    v_rcp_iflag_f32_e32 v4, v0
4276; GFX9-NEXT:    s_xor_b32 s0, s2, s1
4277; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
4278; GFX9-NEXT:    s_or_b32 s2, s0, 1
4279; GFX9-NEXT:    v_mul_f32_e32 v4, v3, v4
4280; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
4281; GFX9-NEXT:    v_mad_f32 v3, -v4, v0, v3
4282; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v3|, |v0|
4283; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
4284; GFX9-NEXT:    v_cvt_i32_f32_e32 v4, v4
4285; GFX9-NEXT:    s_sext_i32_i16 s1, s3
4286; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s1
4287; GFX9-NEXT:    s_cselect_b32 s0, s2, 0
4288; GFX9-NEXT:    v_add_u32_e32 v3, s0, v4
4289; GFX9-NEXT:    s_sext_i32_i16 s0, s5
4290; GFX9-NEXT:    v_cvt_f32_i32_e32 v4, s0
4291; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v0
4292; GFX9-NEXT:    s_xor_b32 s0, s0, s1
4293; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
4294; GFX9-NEXT:    s_or_b32 s2, s0, 1
4295; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
4296; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
4297; GFX9-NEXT:    v_mad_f32 v4, -v5, v0, v4
4298; GFX9-NEXT:    v_cvt_i32_f32_e32 v5, v5
4299; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v4|, |v0|
4300; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
4301; GFX9-NEXT:    s_cselect_b32 s0, s2, 0
4302; GFX9-NEXT:    v_add_u32_e32 v0, s0, v5
4303; GFX9-NEXT:    v_and_b32_e32 v2, 0xffff, v2
4304; GFX9-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
4305; GFX9-NEXT:    global_store_short v1, v0, s[6:7] offset:4
4306; GFX9-NEXT:    global_store_dword v1, v2, s[6:7]
4307; GFX9-NEXT:    s_endpgm
4308  %r = sdiv <3 x i16> %x, %y
4309  store <3 x i16> %r, <3 x i16> addrspace(1)* %out
4310  ret void
4311}
4312
4313define amdgpu_kernel void @srem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x, <3 x i16> %y) {
4314; CHECK-LABEL: @srem_v3i16(
4315; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i16> [[X:%.*]], i64 0
4316; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i16> [[Y:%.*]], i64 0
4317; CHECK-NEXT:    [[TMP3:%.*]] = sext i16 [[TMP1]] to i32
4318; CHECK-NEXT:    [[TMP4:%.*]] = sext i16 [[TMP2]] to i32
4319; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
4320; CHECK-NEXT:    [[TMP6:%.*]] = ashr i32 [[TMP5]], 30
4321; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], 1
4322; CHECK-NEXT:    [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float
4323; CHECK-NEXT:    [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float
4324; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
4325; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]
4326; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])
4327; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
4328; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
4329; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
4330; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
4331; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
4332; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
4333; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
4334; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
4335; CHECK-NEXT:    [[TMP21:%.*]] = mul i32 [[TMP20]], [[TMP4]]
4336; CHECK-NEXT:    [[TMP22:%.*]] = sub i32 [[TMP3]], [[TMP21]]
4337; CHECK-NEXT:    [[TMP23:%.*]] = shl i32 [[TMP22]], 16
4338; CHECK-NEXT:    [[TMP24:%.*]] = ashr i32 [[TMP23]], 16
4339; CHECK-NEXT:    [[TMP25:%.*]] = trunc i32 [[TMP24]] to i16
4340; CHECK-NEXT:    [[TMP26:%.*]] = insertelement <3 x i16> undef, i16 [[TMP25]], i64 0
4341; CHECK-NEXT:    [[TMP27:%.*]] = extractelement <3 x i16> [[X]], i64 1
4342; CHECK-NEXT:    [[TMP28:%.*]] = extractelement <3 x i16> [[Y]], i64 1
4343; CHECK-NEXT:    [[TMP29:%.*]] = sext i16 [[TMP27]] to i32
4344; CHECK-NEXT:    [[TMP30:%.*]] = sext i16 [[TMP28]] to i32
4345; CHECK-NEXT:    [[TMP31:%.*]] = xor i32 [[TMP29]], [[TMP30]]
4346; CHECK-NEXT:    [[TMP32:%.*]] = ashr i32 [[TMP31]], 30
4347; CHECK-NEXT:    [[TMP33:%.*]] = or i32 [[TMP32]], 1
4348; CHECK-NEXT:    [[TMP34:%.*]] = sitofp i32 [[TMP29]] to float
4349; CHECK-NEXT:    [[TMP35:%.*]] = sitofp i32 [[TMP30]] to float
4350; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])
4351; CHECK-NEXT:    [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]]
4352; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]])
4353; CHECK-NEXT:    [[TMP39:%.*]] = fneg fast float [[TMP38]]
4354; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]])
4355; CHECK-NEXT:    [[TMP41:%.*]] = fptosi float [[TMP38]] to i32
4356; CHECK-NEXT:    [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]])
4357; CHECK-NEXT:    [[TMP43:%.*]] = call fast float @llvm.fabs.f32(float [[TMP35]])
4358; CHECK-NEXT:    [[TMP44:%.*]] = fcmp fast oge float [[TMP42]], [[TMP43]]
4359; CHECK-NEXT:    [[TMP45:%.*]] = select i1 [[TMP44]], i32 [[TMP33]], i32 0
4360; CHECK-NEXT:    [[TMP46:%.*]] = add i32 [[TMP41]], [[TMP45]]
4361; CHECK-NEXT:    [[TMP47:%.*]] = mul i32 [[TMP46]], [[TMP30]]
4362; CHECK-NEXT:    [[TMP48:%.*]] = sub i32 [[TMP29]], [[TMP47]]
4363; CHECK-NEXT:    [[TMP49:%.*]] = shl i32 [[TMP48]], 16
4364; CHECK-NEXT:    [[TMP50:%.*]] = ashr i32 [[TMP49]], 16
4365; CHECK-NEXT:    [[TMP51:%.*]] = trunc i32 [[TMP50]] to i16
4366; CHECK-NEXT:    [[TMP52:%.*]] = insertelement <3 x i16> [[TMP26]], i16 [[TMP51]], i64 1
4367; CHECK-NEXT:    [[TMP53:%.*]] = extractelement <3 x i16> [[X]], i64 2
4368; CHECK-NEXT:    [[TMP54:%.*]] = extractelement <3 x i16> [[Y]], i64 2
4369; CHECK-NEXT:    [[TMP55:%.*]] = sext i16 [[TMP53]] to i32
4370; CHECK-NEXT:    [[TMP56:%.*]] = sext i16 [[TMP54]] to i32
4371; CHECK-NEXT:    [[TMP57:%.*]] = xor i32 [[TMP55]], [[TMP56]]
4372; CHECK-NEXT:    [[TMP58:%.*]] = ashr i32 [[TMP57]], 30
4373; CHECK-NEXT:    [[TMP59:%.*]] = or i32 [[TMP58]], 1
4374; CHECK-NEXT:    [[TMP60:%.*]] = sitofp i32 [[TMP55]] to float
4375; CHECK-NEXT:    [[TMP61:%.*]] = sitofp i32 [[TMP56]] to float
4376; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP61]])
4377; CHECK-NEXT:    [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]]
4378; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]])
4379; CHECK-NEXT:    [[TMP65:%.*]] = fneg fast float [[TMP64]]
4380; CHECK-NEXT:    [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]])
4381; CHECK-NEXT:    [[TMP67:%.*]] = fptosi float [[TMP64]] to i32
4382; CHECK-NEXT:    [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]])
4383; CHECK-NEXT:    [[TMP69:%.*]] = call fast float @llvm.fabs.f32(float [[TMP61]])
4384; CHECK-NEXT:    [[TMP70:%.*]] = fcmp fast oge float [[TMP68]], [[TMP69]]
4385; CHECK-NEXT:    [[TMP71:%.*]] = select i1 [[TMP70]], i32 [[TMP59]], i32 0
4386; CHECK-NEXT:    [[TMP72:%.*]] = add i32 [[TMP67]], [[TMP71]]
4387; CHECK-NEXT:    [[TMP73:%.*]] = mul i32 [[TMP72]], [[TMP56]]
4388; CHECK-NEXT:    [[TMP74:%.*]] = sub i32 [[TMP55]], [[TMP73]]
4389; CHECK-NEXT:    [[TMP75:%.*]] = shl i32 [[TMP74]], 16
4390; CHECK-NEXT:    [[TMP76:%.*]] = ashr i32 [[TMP75]], 16
4391; CHECK-NEXT:    [[TMP77:%.*]] = trunc i32 [[TMP76]] to i16
4392; CHECK-NEXT:    [[TMP78:%.*]] = insertelement <3 x i16> [[TMP52]], i16 [[TMP77]], i64 2
4393; CHECK-NEXT:    store <3 x i16> [[TMP78]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8
4394; CHECK-NEXT:    ret void
4395;
4396; GFX6-LABEL: srem_v3i16:
4397; GFX6:       ; %bb.0:
4398; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
4399; GFX6-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0xb
4400; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
4401; GFX6-NEXT:    s_mov_b32 s3, 0xf000
4402; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
4403; GFX6-NEXT:    s_sext_i32_i16 s2, s4
4404; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s2
4405; GFX6-NEXT:    s_sext_i32_i16 s8, s6
4406; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s8
4407; GFX6-NEXT:    s_xor_b32 s2, s8, s2
4408; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
4409; GFX6-NEXT:    s_ashr_i32 s2, s2, 30
4410; GFX6-NEXT:    s_or_b32 s2, s2, 1
4411; GFX6-NEXT:    v_mov_b32_e32 v3, s2
4412; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
4413; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
4414; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
4415; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
4416; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
4417; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
4418; GFX6-NEXT:    v_mov_b32_e32 v1, s6
4419; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
4420; GFX6-NEXT:    v_mov_b32_e32 v2, s4
4421; GFX6-NEXT:    v_alignbit_b32 v2, s5, v2, 16
4422; GFX6-NEXT:    v_bfe_i32 v3, v2, 0, 16
4423; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, v3
4424; GFX6-NEXT:    v_alignbit_b32 v1, s7, v1, 16
4425; GFX6-NEXT:    v_bfe_i32 v5, v1, 0, 16
4426; GFX6-NEXT:    v_cvt_f32_i32_e32 v6, v5
4427; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v4
4428; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s4
4429; GFX6-NEXT:    v_xor_b32_e32 v3, v5, v3
4430; GFX6-NEXT:    s_sext_i32_i16 s4, s5
4431; GFX6-NEXT:    v_mul_f32_e32 v5, v6, v7
4432; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
4433; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
4434; GFX6-NEXT:    v_mad_f32 v6, -v5, v4, v6
4435; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
4436; GFX6-NEXT:    v_ashrrev_i32_e32 v3, 30, v3
4437; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, |v4|
4438; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s4
4439; GFX6-NEXT:    v_or_b32_e32 v3, 1, v3
4440; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
4441; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
4442; GFX6-NEXT:    s_sext_i32_i16 s6, s7
4443; GFX6-NEXT:    v_mul_lo_u32 v2, v3, v2
4444; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s6
4445; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v4
4446; GFX6-NEXT:    s_xor_b32 s4, s6, s4
4447; GFX6-NEXT:    s_ashr_i32 s4, s4, 30
4448; GFX6-NEXT:    s_or_b32 s4, s4, 1
4449; GFX6-NEXT:    v_mul_f32_e32 v5, v3, v5
4450; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
4451; GFX6-NEXT:    v_mad_f32 v3, -v5, v4, v3
4452; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
4453; GFX6-NEXT:    v_mov_b32_e32 v6, s4
4454; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v4|
4455; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v6, vcc
4456; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
4457; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s5
4458; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v2
4459; GFX6-NEXT:    s_mov_b32 s2, -1
4460; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s7, v3
4461; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
4462; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0
4463; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
4464; GFX6-NEXT:    buffer_store_short v2, off, s[0:3], 0 offset:4
4465; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
4466; GFX6-NEXT:    s_endpgm
4467;
4468; GFX9-LABEL: srem_v3i16:
4469; GFX9:       ; %bb.0:
4470; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
4471; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
4472; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
4473; GFX9-NEXT:    s_sext_i32_i16 s8, s2
4474; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s8
4475; GFX9-NEXT:    s_sext_i32_i16 s9, s4
4476; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s9
4477; GFX9-NEXT:    s_xor_b32 s6, s9, s8
4478; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
4479; GFX9-NEXT:    s_ashr_i32 s6, s6, 30
4480; GFX9-NEXT:    s_or_b32 s10, s6, 1
4481; GFX9-NEXT:    s_sext_i32_i16 s5, s5
4482; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
4483; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
4484; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
4485; GFX9-NEXT:    v_cmp_ge_f32_e64 s[6:7], |v1|, |v0|
4486; GFX9-NEXT:    s_and_b64 s[6:7], s[6:7], exec
4487; GFX9-NEXT:    s_cselect_b32 s6, s10, 0
4488; GFX9-NEXT:    s_ashr_i32 s2, s2, 16
4489; GFX9-NEXT:    v_cvt_i32_f32_e32 v2, v2
4490; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s2
4491; GFX9-NEXT:    s_ashr_i32 s4, s4, 16
4492; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
4493; GFX9-NEXT:    v_add_u32_e32 v1, s6, v2
4494; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s4
4495; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
4496; GFX9-NEXT:    s_xor_b32 s6, s4, s2
4497; GFX9-NEXT:    s_ashr_i32 s6, s6, 30
4498; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s8
4499; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
4500; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
4501; GFX9-NEXT:    v_mad_f32 v2, -v3, v0, v2
4502; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
4503; GFX9-NEXT:    s_or_b32 s8, s6, 1
4504; GFX9-NEXT:    v_cmp_ge_f32_e64 s[6:7], |v2|, |v0|
4505; GFX9-NEXT:    s_and_b64 s[6:7], s[6:7], exec
4506; GFX9-NEXT:    s_cselect_b32 s6, s8, 0
4507; GFX9-NEXT:    v_add_u32_e32 v0, s6, v3
4508; GFX9-NEXT:    s_sext_i32_i16 s6, s3
4509; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s6
4510; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s5
4511; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s2
4512; GFX9-NEXT:    s_xor_b32 s2, s5, s6
4513; GFX9-NEXT:    v_rcp_iflag_f32_e32 v4, v2
4514; GFX9-NEXT:    s_ashr_i32 s2, s2, 30
4515; GFX9-NEXT:    s_or_b32 s7, s2, 1
4516; GFX9-NEXT:    v_sub_u32_e32 v1, s9, v1
4517; GFX9-NEXT:    v_mul_f32_e32 v4, v3, v4
4518; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
4519; GFX9-NEXT:    v_mad_f32 v3, -v4, v2, v3
4520; GFX9-NEXT:    v_cvt_i32_f32_e32 v4, v4
4521; GFX9-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v3|, |v2|
4522; GFX9-NEXT:    s_and_b64 s[2:3], s[2:3], exec
4523; GFX9-NEXT:    s_cselect_b32 s2, s7, 0
4524; GFX9-NEXT:    v_add_u32_e32 v2, s2, v4
4525; GFX9-NEXT:    v_mul_lo_u32 v2, v2, s6
4526; GFX9-NEXT:    v_mov_b32_e32 v3, 0
4527; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
4528; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff, v1
4529; GFX9-NEXT:    v_sub_u32_e32 v2, s5, v2
4530; GFX9-NEXT:    v_lshl_or_b32 v0, v0, 16, v1
4531; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
4532; GFX9-NEXT:    global_store_short v3, v2, s[0:1] offset:4
4533; GFX9-NEXT:    global_store_dword v3, v0, s[0:1]
4534; GFX9-NEXT:    s_endpgm
4535  %r = srem <3 x i16> %x, %y
4536  store <3 x i16> %r, <3 x i16> addrspace(1)* %out
4537  ret void
4538}
4539
4540define amdgpu_kernel void @udiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x, <3 x i15> %y) {
4541; CHECK-LABEL: @udiv_v3i15(
4542; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i15> [[X:%.*]], i64 0
4543; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i15> [[Y:%.*]], i64 0
4544; CHECK-NEXT:    [[TMP3:%.*]] = zext i15 [[TMP1]] to i32
4545; CHECK-NEXT:    [[TMP4:%.*]] = zext i15 [[TMP2]] to i32
4546; CHECK-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float
4547; CHECK-NEXT:    [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float
4548; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])
4549; CHECK-NEXT:    [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]
4550; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])
4551; CHECK-NEXT:    [[TMP10:%.*]] = fneg fast float [[TMP9]]
4552; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])
4553; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP9]] to i32
4554; CHECK-NEXT:    [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])
4555; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])
4556; CHECK-NEXT:    [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]
4557; CHECK-NEXT:    [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 0
4558; CHECK-NEXT:    [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]
4559; CHECK-NEXT:    [[TMP18:%.*]] = and i32 [[TMP17]], 32767
4560; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i15
4561; CHECK-NEXT:    [[TMP20:%.*]] = insertelement <3 x i15> undef, i15 [[TMP19]], i64 0
4562; CHECK-NEXT:    [[TMP21:%.*]] = extractelement <3 x i15> [[X]], i64 1
4563; CHECK-NEXT:    [[TMP22:%.*]] = extractelement <3 x i15> [[Y]], i64 1
4564; CHECK-NEXT:    [[TMP23:%.*]] = zext i15 [[TMP21]] to i32
4565; CHECK-NEXT:    [[TMP24:%.*]] = zext i15 [[TMP22]] to i32
4566; CHECK-NEXT:    [[TMP25:%.*]] = uitofp i32 [[TMP23]] to float
4567; CHECK-NEXT:    [[TMP26:%.*]] = uitofp i32 [[TMP24]] to float
4568; CHECK-NEXT:    [[TMP27:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP26]])
4569; CHECK-NEXT:    [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]]
4570; CHECK-NEXT:    [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]])
4571; CHECK-NEXT:    [[TMP30:%.*]] = fneg fast float [[TMP29]]
4572; CHECK-NEXT:    [[TMP31:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP30]], float [[TMP26]], float [[TMP25]])
4573; CHECK-NEXT:    [[TMP32:%.*]] = fptoui float [[TMP29]] to i32
4574; CHECK-NEXT:    [[TMP33:%.*]] = call fast float @llvm.fabs.f32(float [[TMP31]])
4575; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.fabs.f32(float [[TMP26]])
4576; CHECK-NEXT:    [[TMP35:%.*]] = fcmp fast oge float [[TMP33]], [[TMP34]]
4577; CHECK-NEXT:    [[TMP36:%.*]] = select i1 [[TMP35]], i32 1, i32 0
4578; CHECK-NEXT:    [[TMP37:%.*]] = add i32 [[TMP32]], [[TMP36]]
4579; CHECK-NEXT:    [[TMP38:%.*]] = and i32 [[TMP37]], 32767
4580; CHECK-NEXT:    [[TMP39:%.*]] = trunc i32 [[TMP38]] to i15
4581; CHECK-NEXT:    [[TMP40:%.*]] = insertelement <3 x i15> [[TMP20]], i15 [[TMP39]], i64 1
4582; CHECK-NEXT:    [[TMP41:%.*]] = extractelement <3 x i15> [[X]], i64 2
4583; CHECK-NEXT:    [[TMP42:%.*]] = extractelement <3 x i15> [[Y]], i64 2
4584; CHECK-NEXT:    [[TMP43:%.*]] = zext i15 [[TMP41]] to i32
4585; CHECK-NEXT:    [[TMP44:%.*]] = zext i15 [[TMP42]] to i32
4586; CHECK-NEXT:    [[TMP45:%.*]] = uitofp i32 [[TMP43]] to float
4587; CHECK-NEXT:    [[TMP46:%.*]] = uitofp i32 [[TMP44]] to float
4588; CHECK-NEXT:    [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]])
4589; CHECK-NEXT:    [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]]
4590; CHECK-NEXT:    [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]])
4591; CHECK-NEXT:    [[TMP50:%.*]] = fneg fast float [[TMP49]]
4592; CHECK-NEXT:    [[TMP51:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP50]], float [[TMP46]], float [[TMP45]])
4593; CHECK-NEXT:    [[TMP52:%.*]] = fptoui float [[TMP49]] to i32
4594; CHECK-NEXT:    [[TMP53:%.*]] = call fast float @llvm.fabs.f32(float [[TMP51]])
4595; CHECK-NEXT:    [[TMP54:%.*]] = call fast float @llvm.fabs.f32(float [[TMP46]])
4596; CHECK-NEXT:    [[TMP55:%.*]] = fcmp fast oge float [[TMP53]], [[TMP54]]
4597; CHECK-NEXT:    [[TMP56:%.*]] = select i1 [[TMP55]], i32 1, i32 0
4598; CHECK-NEXT:    [[TMP57:%.*]] = add i32 [[TMP52]], [[TMP56]]
4599; CHECK-NEXT:    [[TMP58:%.*]] = and i32 [[TMP57]], 32767
4600; CHECK-NEXT:    [[TMP59:%.*]] = trunc i32 [[TMP58]] to i15
4601; CHECK-NEXT:    [[TMP60:%.*]] = insertelement <3 x i15> [[TMP40]], i15 [[TMP59]], i64 2
4602; CHECK-NEXT:    store <3 x i15> [[TMP60]], <3 x i15> addrspace(1)* [[OUT:%.*]], align 8
4603; CHECK-NEXT:    ret void
4604;
4605; GFX6-LABEL: udiv_v3i15:
4606; GFX6:       ; %bb.0:
4607; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
4608; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
4609; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
4610; GFX6-NEXT:    s_mov_b32 s7, 0xf000
4611; GFX6-NEXT:    s_mov_b32 s6, -1
4612; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
4613; GFX6-NEXT:    v_mov_b32_e32 v0, s2
4614; GFX6-NEXT:    v_alignbit_b32 v0, s3, v0, 30
4615; GFX6-NEXT:    s_movk_i32 s3, 0x7fff
4616; GFX6-NEXT:    s_and_b32 s9, s0, s3
4617; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
4618; GFX6-NEXT:    s_and_b32 s8, s2, s3
4619; GFX6-NEXT:    v_mov_b32_e32 v2, s0
4620; GFX6-NEXT:    s_bfe_u32 s0, s0, 0xf000f
4621; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s8
4622; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v1
4623; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s0
4624; GFX6-NEXT:    s_bfe_u32 s2, s2, 0xf000f
4625; GFX6-NEXT:    v_alignbit_b32 v2, s1, v2, 30
4626; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
4627; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s2
4628; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v5
4629; GFX6-NEXT:    v_and_b32_e32 v2, s3, v2
4630; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
4631; GFX6-NEXT:    v_mad_f32 v3, -v4, v1, v3
4632; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
4633; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, v2
4634; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v1
4635; GFX6-NEXT:    v_mul_f32_e32 v1, v6, v7
4636; GFX6-NEXT:    v_and_b32_e32 v0, s3, v0
4637; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
4638; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
4639; GFX6-NEXT:    v_mad_f32 v4, -v1, v5, v6
4640; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
4641; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, v0
4642; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v2
4643; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v5
4644; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
4645; GFX6-NEXT:    v_mul_f32_e32 v1, v0, v6
4646; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
4647; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v1
4648; GFX6-NEXT:    v_mad_f32 v0, -v1, v2, v0
4649; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, v2
4650; GFX6-NEXT:    v_and_b32_e32 v2, s3, v3
4651; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
4652; GFX6-NEXT:    v_and_b32_e32 v3, s3, v4
4653; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 30
4654; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
4655; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
4656; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
4657; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
4658; GFX6-NEXT:    s_waitcnt expcnt(0)
4659; GFX6-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
4660; GFX6-NEXT:    buffer_store_short v0, off, s[4:7], 0 offset:4
4661; GFX6-NEXT:    s_endpgm
4662;
4663; GFX9-LABEL: udiv_v3i15:
4664; GFX9:       ; %bb.0:
4665; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
4666; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
4667; GFX9-NEXT:    s_movk_i32 s6, 0x7fff
4668; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
4669; GFX9-NEXT:    v_mov_b32_e32 v2, 0
4670; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
4671; GFX9-NEXT:    v_mov_b32_e32 v0, s2
4672; GFX9-NEXT:    v_alignbit_b32 v0, s3, v0, 30
4673; GFX9-NEXT:    s_and_b32 s3, s2, s6
4674; GFX9-NEXT:    s_and_b32 s7, s0, s6
4675; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s7
4676; GFX9-NEXT:    v_mov_b32_e32 v3, s0
4677; GFX9-NEXT:    s_bfe_u32 s0, s0, 0xf000f
4678; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s3
4679; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v1
4680; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
4681; GFX9-NEXT:    s_bfe_u32 s2, s2, 0xf000f
4682; GFX9-NEXT:    v_alignbit_b32 v3, s1, v3, 30
4683; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
4684; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s2
4685; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v6
4686; GFX9-NEXT:    v_and_b32_e32 v3, s6, v3
4687; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
4688; GFX9-NEXT:    v_mad_f32 v4, -v5, v1, v4
4689; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
4690; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, v3
4691; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v1
4692; GFX9-NEXT:    v_mul_f32_e32 v1, v7, v8
4693; GFX9-NEXT:    v_and_b32_e32 v0, s6, v0
4694; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
4695; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
4696; GFX9-NEXT:    v_mad_f32 v5, -v1, v6, v7
4697; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
4698; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, v0
4699; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v3
4700; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v6
4701; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
4702; GFX9-NEXT:    v_mul_f32_e32 v1, v0, v7
4703; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
4704; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v1
4705; GFX9-NEXT:    v_mad_f32 v0, -v1, v3, v0
4706; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, v3
4707; GFX9-NEXT:    v_and_b32_e32 v3, s6, v4
4708; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v6, vcc
4709; GFX9-NEXT:    v_and_b32_e32 v4, s6, v5
4710; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 30, v[0:1]
4711; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 15, v4
4712; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
4713; GFX9-NEXT:    v_or_b32_e32 v0, v3, v0
4714; GFX9-NEXT:    global_store_dword v2, v0, s[4:5]
4715; GFX9-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
4716; GFX9-NEXT:    global_store_short v2, v0, s[4:5] offset:4
4717; GFX9-NEXT:    s_endpgm
4718  %r = udiv <3 x i15> %x, %y
4719  store <3 x i15> %r, <3 x i15> addrspace(1)* %out
4720  ret void
4721}
4722
4723define amdgpu_kernel void @urem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x, <3 x i15> %y) {
4724; CHECK-LABEL: @urem_v3i15(
4725; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i15> [[X:%.*]], i64 0
4726; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i15> [[Y:%.*]], i64 0
4727; CHECK-NEXT:    [[TMP3:%.*]] = zext i15 [[TMP1]] to i32
4728; CHECK-NEXT:    [[TMP4:%.*]] = zext i15 [[TMP2]] to i32
4729; CHECK-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float
4730; CHECK-NEXT:    [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float
4731; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])
4732; CHECK-NEXT:    [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]
4733; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])
4734; CHECK-NEXT:    [[TMP10:%.*]] = fneg fast float [[TMP9]]
4735; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])
4736; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP9]] to i32
4737; CHECK-NEXT:    [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])
4738; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])
4739; CHECK-NEXT:    [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]
4740; CHECK-NEXT:    [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 0
4741; CHECK-NEXT:    [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]
4742; CHECK-NEXT:    [[TMP18:%.*]] = mul i32 [[TMP17]], [[TMP4]]
4743; CHECK-NEXT:    [[TMP19:%.*]] = sub i32 [[TMP3]], [[TMP18]]
4744; CHECK-NEXT:    [[TMP20:%.*]] = and i32 [[TMP19]], 32767
4745; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i15
4746; CHECK-NEXT:    [[TMP22:%.*]] = insertelement <3 x i15> undef, i15 [[TMP21]], i64 0
4747; CHECK-NEXT:    [[TMP23:%.*]] = extractelement <3 x i15> [[X]], i64 1
4748; CHECK-NEXT:    [[TMP24:%.*]] = extractelement <3 x i15> [[Y]], i64 1
4749; CHECK-NEXT:    [[TMP25:%.*]] = zext i15 [[TMP23]] to i32
4750; CHECK-NEXT:    [[TMP26:%.*]] = zext i15 [[TMP24]] to i32
4751; CHECK-NEXT:    [[TMP27:%.*]] = uitofp i32 [[TMP25]] to float
4752; CHECK-NEXT:    [[TMP28:%.*]] = uitofp i32 [[TMP26]] to float
4753; CHECK-NEXT:    [[TMP29:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP28]])
4754; CHECK-NEXT:    [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]]
4755; CHECK-NEXT:    [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]])
4756; CHECK-NEXT:    [[TMP32:%.*]] = fneg fast float [[TMP31]]
4757; CHECK-NEXT:    [[TMP33:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP32]], float [[TMP28]], float [[TMP27]])
4758; CHECK-NEXT:    [[TMP34:%.*]] = fptoui float [[TMP31]] to i32
4759; CHECK-NEXT:    [[TMP35:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
4760; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.fabs.f32(float [[TMP28]])
4761; CHECK-NEXT:    [[TMP37:%.*]] = fcmp fast oge float [[TMP35]], [[TMP36]]
4762; CHECK-NEXT:    [[TMP38:%.*]] = select i1 [[TMP37]], i32 1, i32 0
4763; CHECK-NEXT:    [[TMP39:%.*]] = add i32 [[TMP34]], [[TMP38]]
4764; CHECK-NEXT:    [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP26]]
4765; CHECK-NEXT:    [[TMP41:%.*]] = sub i32 [[TMP25]], [[TMP40]]
4766; CHECK-NEXT:    [[TMP42:%.*]] = and i32 [[TMP41]], 32767
4767; CHECK-NEXT:    [[TMP43:%.*]] = trunc i32 [[TMP42]] to i15
4768; CHECK-NEXT:    [[TMP44:%.*]] = insertelement <3 x i15> [[TMP22]], i15 [[TMP43]], i64 1
4769; CHECK-NEXT:    [[TMP45:%.*]] = extractelement <3 x i15> [[X]], i64 2
4770; CHECK-NEXT:    [[TMP46:%.*]] = extractelement <3 x i15> [[Y]], i64 2
4771; CHECK-NEXT:    [[TMP47:%.*]] = zext i15 [[TMP45]] to i32
4772; CHECK-NEXT:    [[TMP48:%.*]] = zext i15 [[TMP46]] to i32
4773; CHECK-NEXT:    [[TMP49:%.*]] = uitofp i32 [[TMP47]] to float
4774; CHECK-NEXT:    [[TMP50:%.*]] = uitofp i32 [[TMP48]] to float
4775; CHECK-NEXT:    [[TMP51:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP50]])
4776; CHECK-NEXT:    [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]]
4777; CHECK-NEXT:    [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]])
4778; CHECK-NEXT:    [[TMP54:%.*]] = fneg fast float [[TMP53]]
4779; CHECK-NEXT:    [[TMP55:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP54]], float [[TMP50]], float [[TMP49]])
4780; CHECK-NEXT:    [[TMP56:%.*]] = fptoui float [[TMP53]] to i32
4781; CHECK-NEXT:    [[TMP57:%.*]] = call fast float @llvm.fabs.f32(float [[TMP55]])
4782; CHECK-NEXT:    [[TMP58:%.*]] = call fast float @llvm.fabs.f32(float [[TMP50]])
4783; CHECK-NEXT:    [[TMP59:%.*]] = fcmp fast oge float [[TMP57]], [[TMP58]]
4784; CHECK-NEXT:    [[TMP60:%.*]] = select i1 [[TMP59]], i32 1, i32 0
4785; CHECK-NEXT:    [[TMP61:%.*]] = add i32 [[TMP56]], [[TMP60]]
4786; CHECK-NEXT:    [[TMP62:%.*]] = mul i32 [[TMP61]], [[TMP48]]
4787; CHECK-NEXT:    [[TMP63:%.*]] = sub i32 [[TMP47]], [[TMP62]]
4788; CHECK-NEXT:    [[TMP64:%.*]] = and i32 [[TMP63]], 32767
4789; CHECK-NEXT:    [[TMP65:%.*]] = trunc i32 [[TMP64]] to i15
4790; CHECK-NEXT:    [[TMP66:%.*]] = insertelement <3 x i15> [[TMP44]], i15 [[TMP65]], i64 2
4791; CHECK-NEXT:    store <3 x i15> [[TMP66]], <3 x i15> addrspace(1)* [[OUT:%.*]], align 8
4792; CHECK-NEXT:    ret void
4793;
4794; GFX6-LABEL: urem_v3i15:
4795; GFX6:       ; %bb.0:
4796; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
4797; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
4798; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
4799; GFX6-NEXT:    s_mov_b32 s7, 0xf000
4800; GFX6-NEXT:    s_mov_b32 s6, -1
4801; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
4802; GFX6-NEXT:    v_mov_b32_e32 v0, s2
4803; GFX6-NEXT:    v_alignbit_b32 v0, s3, v0, 30
4804; GFX6-NEXT:    s_movk_i32 s3, 0x7fff
4805; GFX6-NEXT:    s_and_b32 s10, s0, s3
4806; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s10
4807; GFX6-NEXT:    s_and_b32 s9, s2, s3
4808; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s9
4809; GFX6-NEXT:    v_mov_b32_e32 v2, s0
4810; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v1
4811; GFX6-NEXT:    v_alignbit_b32 v2, s1, v2, 30
4812; GFX6-NEXT:    s_bfe_u32 s1, s0, 0xf000f
4813; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s1
4814; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
4815; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
4816; GFX6-NEXT:    v_mad_f32 v3, -v4, v1, v3
4817; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
4818; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v1
4819; GFX6-NEXT:    s_bfe_u32 s10, s2, 0xf000f
4820; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s10
4821; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v4, vcc
4822; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s0
4823; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v5
4824; GFX6-NEXT:    v_and_b32_e32 v2, s3, v2
4825; GFX6-NEXT:    v_and_b32_e32 v0, s3, v0
4826; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, s2, v1
4827; GFX6-NEXT:    v_mul_f32_e32 v1, v3, v4
4828; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, v2
4829; GFX6-NEXT:    v_cvt_f32_u32_e32 v7, v0
4830; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
4831; GFX6-NEXT:    v_mad_f32 v3, -v1, v5, v3
4832; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v4
4833; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
4834; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v5
4835; GFX6-NEXT:    s_lshr_b32 s0, s0, 15
4836; GFX6-NEXT:    v_mul_f32_e32 v3, v7, v8
4837; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
4838; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v3
4839; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
4840; GFX6-NEXT:    v_mad_f32 v3, -v3, v4, v7
4841; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v4
4842; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s0
4843; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
4844; GFX6-NEXT:    v_mul_lo_u32 v2, v3, v2
4845; GFX6-NEXT:    s_lshr_b32 s8, s2, 15
4846; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s8, v1
4847; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, v2, v0
4848; GFX6-NEXT:    v_and_b32_e32 v3, s3, v3
4849; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 30
4850; GFX6-NEXT:    v_and_b32_e32 v2, s3, v6
4851; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
4852; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
4853; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
4854; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
4855; GFX6-NEXT:    s_waitcnt expcnt(0)
4856; GFX6-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
4857; GFX6-NEXT:    buffer_store_short v0, off, s[4:7], 0 offset:4
4858; GFX6-NEXT:    s_endpgm
4859;
4860; GFX9-LABEL: urem_v3i15:
4861; GFX9:       ; %bb.0:
4862; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
4863; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
4864; GFX9-NEXT:    s_movk_i32 s6, 0x7fff
4865; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
4866; GFX9-NEXT:    v_mov_b32_e32 v2, 0
4867; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
4868; GFX9-NEXT:    v_mov_b32_e32 v0, s2
4869; GFX9-NEXT:    v_alignbit_b32 v0, s3, v0, 30
4870; GFX9-NEXT:    s_and_b32 s3, s2, s6
4871; GFX9-NEXT:    s_and_b32 s8, s0, s6
4872; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s8
4873; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s3
4874; GFX9-NEXT:    s_bfe_u32 s3, s0, 0xf000f
4875; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s3
4876; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v1
4877; GFX9-NEXT:    v_mov_b32_e32 v3, s0
4878; GFX9-NEXT:    v_alignbit_b32 v3, s1, v3, 30
4879; GFX9-NEXT:    s_bfe_u32 s7, s2, 0xf000f
4880; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
4881; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
4882; GFX9-NEXT:    v_mad_f32 v4, -v5, v1, v4
4883; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
4884; GFX9-NEXT:    v_and_b32_e32 v3, s6, v3
4885; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v1
4886; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s7
4887; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v6
4888; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v5, vcc
4889; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v3
4890; GFX9-NEXT:    v_and_b32_e32 v0, s6, v0
4891; GFX9-NEXT:    v_mul_f32_e32 v4, v7, v8
4892; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, v0
4893; GFX9-NEXT:    v_rcp_iflag_f32_e32 v9, v5
4894; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
4895; GFX9-NEXT:    v_mad_f32 v7, -v4, v6, v7
4896; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
4897; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v7|, v6
4898; GFX9-NEXT:    v_mul_f32_e32 v6, v8, v9
4899; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
4900; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v6
4901; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
4902; GFX9-NEXT:    v_mad_f32 v6, -v6, v5, v8
4903; GFX9-NEXT:    s_lshr_b32 s1, s0, 15
4904; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, v5
4905; GFX9-NEXT:    v_mul_lo_u32 v4, v4, s1
4906; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
4907; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s0
4908; GFX9-NEXT:    v_mul_lo_u32 v3, v5, v3
4909; GFX9-NEXT:    s_lshr_b32 s0, s2, 15
4910; GFX9-NEXT:    v_sub_u32_e32 v4, s0, v4
4911; GFX9-NEXT:    v_sub_u32_e32 v5, s2, v1
4912; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v3
4913; GFX9-NEXT:    v_and_b32_e32 v4, s6, v4
4914; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 30, v[0:1]
4915; GFX9-NEXT:    v_and_b32_e32 v3, s6, v5
4916; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 15, v4
4917; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
4918; GFX9-NEXT:    v_or_b32_e32 v0, v3, v0
4919; GFX9-NEXT:    global_store_dword v2, v0, s[4:5]
4920; GFX9-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
4921; GFX9-NEXT:    global_store_short v2, v0, s[4:5] offset:4
4922; GFX9-NEXT:    s_endpgm
4923  %r = urem <3 x i15> %x, %y
4924  store <3 x i15> %r, <3 x i15> addrspace(1)* %out
4925  ret void
4926}
4927
4928define amdgpu_kernel void @sdiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x, <3 x i15> %y) {
4929; CHECK-LABEL: @sdiv_v3i15(
4930; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i15> [[X:%.*]], i64 0
4931; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i15> [[Y:%.*]], i64 0
4932; CHECK-NEXT:    [[TMP3:%.*]] = sext i15 [[TMP1]] to i32
4933; CHECK-NEXT:    [[TMP4:%.*]] = sext i15 [[TMP2]] to i32
4934; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
4935; CHECK-NEXT:    [[TMP6:%.*]] = ashr i32 [[TMP5]], 30
4936; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], 1
4937; CHECK-NEXT:    [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float
4938; CHECK-NEXT:    [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float
4939; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
4940; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]
4941; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])
4942; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
4943; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
4944; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
4945; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
4946; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
4947; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
4948; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
4949; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
4950; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 17
4951; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 17
4952; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i15
4953; CHECK-NEXT:    [[TMP24:%.*]] = insertelement <3 x i15> undef, i15 [[TMP23]], i64 0
4954; CHECK-NEXT:    [[TMP25:%.*]] = extractelement <3 x i15> [[X]], i64 1
4955; CHECK-NEXT:    [[TMP26:%.*]] = extractelement <3 x i15> [[Y]], i64 1
4956; CHECK-NEXT:    [[TMP27:%.*]] = sext i15 [[TMP25]] to i32
4957; CHECK-NEXT:    [[TMP28:%.*]] = sext i15 [[TMP26]] to i32
4958; CHECK-NEXT:    [[TMP29:%.*]] = xor i32 [[TMP27]], [[TMP28]]
4959; CHECK-NEXT:    [[TMP30:%.*]] = ashr i32 [[TMP29]], 30
4960; CHECK-NEXT:    [[TMP31:%.*]] = or i32 [[TMP30]], 1
4961; CHECK-NEXT:    [[TMP32:%.*]] = sitofp i32 [[TMP27]] to float
4962; CHECK-NEXT:    [[TMP33:%.*]] = sitofp i32 [[TMP28]] to float
4963; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])
4964; CHECK-NEXT:    [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]]
4965; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]])
4966; CHECK-NEXT:    [[TMP37:%.*]] = fneg fast float [[TMP36]]
4967; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]])
4968; CHECK-NEXT:    [[TMP39:%.*]] = fptosi float [[TMP36]] to i32
4969; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]])
4970; CHECK-NEXT:    [[TMP41:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
4971; CHECK-NEXT:    [[TMP42:%.*]] = fcmp fast oge float [[TMP40]], [[TMP41]]
4972; CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP31]], i32 0
4973; CHECK-NEXT:    [[TMP44:%.*]] = add i32 [[TMP39]], [[TMP43]]
4974; CHECK-NEXT:    [[TMP45:%.*]] = shl i32 [[TMP44]], 17
4975; CHECK-NEXT:    [[TMP46:%.*]] = ashr i32 [[TMP45]], 17
4976; CHECK-NEXT:    [[TMP47:%.*]] = trunc i32 [[TMP46]] to i15
4977; CHECK-NEXT:    [[TMP48:%.*]] = insertelement <3 x i15> [[TMP24]], i15 [[TMP47]], i64 1
4978; CHECK-NEXT:    [[TMP49:%.*]] = extractelement <3 x i15> [[X]], i64 2
4979; CHECK-NEXT:    [[TMP50:%.*]] = extractelement <3 x i15> [[Y]], i64 2
4980; CHECK-NEXT:    [[TMP51:%.*]] = sext i15 [[TMP49]] to i32
4981; CHECK-NEXT:    [[TMP52:%.*]] = sext i15 [[TMP50]] to i32
4982; CHECK-NEXT:    [[TMP53:%.*]] = xor i32 [[TMP51]], [[TMP52]]
4983; CHECK-NEXT:    [[TMP54:%.*]] = ashr i32 [[TMP53]], 30
4984; CHECK-NEXT:    [[TMP55:%.*]] = or i32 [[TMP54]], 1
4985; CHECK-NEXT:    [[TMP56:%.*]] = sitofp i32 [[TMP51]] to float
4986; CHECK-NEXT:    [[TMP57:%.*]] = sitofp i32 [[TMP52]] to float
4987; CHECK-NEXT:    [[TMP58:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP57]])
4988; CHECK-NEXT:    [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]]
4989; CHECK-NEXT:    [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]])
4990; CHECK-NEXT:    [[TMP61:%.*]] = fneg fast float [[TMP60]]
4991; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]])
4992; CHECK-NEXT:    [[TMP63:%.*]] = fptosi float [[TMP60]] to i32
4993; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]])
4994; CHECK-NEXT:    [[TMP65:%.*]] = call fast float @llvm.fabs.f32(float [[TMP57]])
4995; CHECK-NEXT:    [[TMP66:%.*]] = fcmp fast oge float [[TMP64]], [[TMP65]]
4996; CHECK-NEXT:    [[TMP67:%.*]] = select i1 [[TMP66]], i32 [[TMP55]], i32 0
4997; CHECK-NEXT:    [[TMP68:%.*]] = add i32 [[TMP63]], [[TMP67]]
4998; CHECK-NEXT:    [[TMP69:%.*]] = shl i32 [[TMP68]], 17
4999; CHECK-NEXT:    [[TMP70:%.*]] = ashr i32 [[TMP69]], 17
5000; CHECK-NEXT:    [[TMP71:%.*]] = trunc i32 [[TMP70]] to i15
5001; CHECK-NEXT:    [[TMP72:%.*]] = insertelement <3 x i15> [[TMP48]], i15 [[TMP71]], i64 2
5002; CHECK-NEXT:    store <3 x i15> [[TMP72]], <3 x i15> addrspace(1)* [[OUT:%.*]], align 8
5003; CHECK-NEXT:    ret void
5004;
5005; GFX6-LABEL: sdiv_v3i15:
5006; GFX6:       ; %bb.0:
5007; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
5008; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
5009; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
5010; GFX6-NEXT:    s_mov_b32 s7, 0xf000
5011; GFX6-NEXT:    s_mov_b32 s6, -1
5012; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5013; GFX6-NEXT:    v_mov_b32_e32 v0, s2
5014; GFX6-NEXT:    v_alignbit_b32 v0, s3, v0, 30
5015; GFX6-NEXT:    s_bfe_i32 s3, s0, 0xf0000
5016; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s3
5017; GFX6-NEXT:    v_mov_b32_e32 v1, s0
5018; GFX6-NEXT:    v_alignbit_b32 v1, s1, v1, 30
5019; GFX6-NEXT:    s_bfe_i32 s1, s2, 0xf0000
5020; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s1
5021; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
5022; GFX6-NEXT:    s_xor_b32 s1, s1, s3
5023; GFX6-NEXT:    s_bfe_i32 s0, s0, 0xf000f
5024; GFX6-NEXT:    s_ashr_i32 s1, s1, 30
5025; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
5026; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
5027; GFX6-NEXT:    v_mad_f32 v3, -v4, v2, v3
5028; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v4
5029; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
5030; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s0
5031; GFX6-NEXT:    s_or_b32 s1, s1, 1
5032; GFX6-NEXT:    v_mov_b32_e32 v5, s1
5033; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
5034; GFX6-NEXT:    s_bfe_i32 s1, s2, 0xf000f
5035; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
5036; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s1
5037; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
5038; GFX6-NEXT:    s_xor_b32 s0, s1, s0
5039; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 15
5040; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
5041; GFX6-NEXT:    v_mul_f32_e32 v5, v4, v5
5042; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
5043; GFX6-NEXT:    v_mad_f32 v4, -v5, v3, v4
5044; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
5045; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v3|
5046; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, v1
5047; GFX6-NEXT:    s_or_b32 s0, s0, 1
5048; GFX6-NEXT:    v_mov_b32_e32 v6, s0
5049; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v6, vcc
5050; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 15
5051; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
5052; GFX6-NEXT:    v_cvt_f32_i32_e32 v5, v0
5053; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v4
5054; GFX6-NEXT:    v_xor_b32_e32 v0, v0, v1
5055; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
5056; GFX6-NEXT:    v_or_b32_e32 v0, 1, v0
5057; GFX6-NEXT:    v_mul_f32_e32 v1, v5, v6
5058; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
5059; GFX6-NEXT:    v_mad_f32 v5, -v1, v4, v5
5060; GFX6-NEXT:    v_cvt_i32_f32_e32 v1, v1
5061; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, |v4|
5062; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
5063; GFX6-NEXT:    s_movk_i32 s0, 0x7fff
5064; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
5065; GFX6-NEXT:    v_and_b32_e32 v3, s0, v3
5066; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 30
5067; GFX6-NEXT:    v_and_b32_e32 v2, s0, v2
5068; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
5069; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
5070; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
5071; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
5072; GFX6-NEXT:    s_waitcnt expcnt(0)
5073; GFX6-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
5074; GFX6-NEXT:    buffer_store_short v0, off, s[4:7], 0 offset:4
5075; GFX6-NEXT:    s_endpgm
5076;
5077; GFX9-LABEL: sdiv_v3i15:
5078; GFX9:       ; %bb.0:
5079; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
5080; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
5081; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x24
5082; GFX9-NEXT:    v_mov_b32_e32 v2, 0
5083; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5084; GFX9-NEXT:    s_bfe_i32 s1, s2, 0xf0000
5085; GFX9-NEXT:    s_bfe_i32 s0, s4, 0xf0000
5086; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s0
5087; GFX9-NEXT:    v_cvt_f32_i32_e32 v4, s1
5088; GFX9-NEXT:    s_xor_b32 s0, s1, s0
5089; GFX9-NEXT:    v_mov_b32_e32 v0, s2
5090; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v3
5091; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
5092; GFX9-NEXT:    v_alignbit_b32 v0, s3, v0, 30
5093; GFX9-NEXT:    s_or_b32 s3, s0, 1
5094; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
5095; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
5096; GFX9-NEXT:    v_mad_f32 v4, -v5, v3, v4
5097; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v4|, |v3|
5098; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
5099; GFX9-NEXT:    v_cvt_i32_f32_e32 v5, v5
5100; GFX9-NEXT:    s_cselect_b32 s0, s3, 0
5101; GFX9-NEXT:    s_bfe_i32 s1, s4, 0xf000f
5102; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s1
5103; GFX9-NEXT:    v_add_u32_e32 v4, s0, v5
5104; GFX9-NEXT:    s_bfe_i32 s0, s2, 0xf000f
5105; GFX9-NEXT:    v_cvt_f32_i32_e32 v5, s0
5106; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v3
5107; GFX9-NEXT:    v_mov_b32_e32 v1, s4
5108; GFX9-NEXT:    v_alignbit_b32 v1, s5, v1, 30
5109; GFX9-NEXT:    s_xor_b32 s0, s0, s1
5110; GFX9-NEXT:    v_mul_f32_e32 v6, v5, v6
5111; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
5112; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
5113; GFX9-NEXT:    v_mad_f32 v5, -v6, v3, v5
5114; GFX9-NEXT:    v_bfe_i32 v1, v1, 0, 15
5115; GFX9-NEXT:    s_or_b32 s2, s0, 1
5116; GFX9-NEXT:    v_cvt_i32_f32_e32 v6, v6
5117; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v5|, |v3|
5118; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, v1
5119; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
5120; GFX9-NEXT:    s_cselect_b32 s0, s2, 0
5121; GFX9-NEXT:    v_bfe_i32 v0, v0, 0, 15
5122; GFX9-NEXT:    v_add_u32_e32 v5, s0, v6
5123; GFX9-NEXT:    v_cvt_f32_i32_e32 v6, v0
5124; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v3
5125; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v1
5126; GFX9-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
5127; GFX9-NEXT:    v_or_b32_e32 v0, 1, v0
5128; GFX9-NEXT:    v_mul_f32_e32 v1, v6, v7
5129; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
5130; GFX9-NEXT:    v_cvt_i32_f32_e32 v7, v1
5131; GFX9-NEXT:    v_mad_f32 v1, -v1, v3, v6
5132; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
5133; GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
5134; GFX9-NEXT:    s_movk_i32 s0, 0x7fff
5135; GFX9-NEXT:    v_add_u32_e32 v0, v7, v0
5136; GFX9-NEXT:    v_and_b32_e32 v3, s0, v4
5137; GFX9-NEXT:    v_and_b32_e32 v4, s0, v5
5138; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 30, v[0:1]
5139; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 15, v4
5140; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
5141; GFX9-NEXT:    v_or_b32_e32 v0, v3, v0
5142; GFX9-NEXT:    global_store_dword v2, v0, s[6:7]
5143; GFX9-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
5144; GFX9-NEXT:    global_store_short v2, v0, s[6:7] offset:4
5145; GFX9-NEXT:    s_endpgm
5146  %r = sdiv <3 x i15> %x, %y
5147  store <3 x i15> %r, <3 x i15> addrspace(1)* %out
5148  ret void
5149}
5150
5151define amdgpu_kernel void @srem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x, <3 x i15> %y) {
5152; CHECK-LABEL: @srem_v3i15(
5153; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i15> [[X:%.*]], i64 0
5154; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i15> [[Y:%.*]], i64 0
5155; CHECK-NEXT:    [[TMP3:%.*]] = sext i15 [[TMP1]] to i32
5156; CHECK-NEXT:    [[TMP4:%.*]] = sext i15 [[TMP2]] to i32
5157; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
5158; CHECK-NEXT:    [[TMP6:%.*]] = ashr i32 [[TMP5]], 30
5159; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], 1
5160; CHECK-NEXT:    [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float
5161; CHECK-NEXT:    [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float
5162; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
5163; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]
5164; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])
5165; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
5166; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
5167; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
5168; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
5169; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
5170; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
5171; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
5172; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
5173; CHECK-NEXT:    [[TMP21:%.*]] = mul i32 [[TMP20]], [[TMP4]]
5174; CHECK-NEXT:    [[TMP22:%.*]] = sub i32 [[TMP3]], [[TMP21]]
5175; CHECK-NEXT:    [[TMP23:%.*]] = shl i32 [[TMP22]], 17
5176; CHECK-NEXT:    [[TMP24:%.*]] = ashr i32 [[TMP23]], 17
5177; CHECK-NEXT:    [[TMP25:%.*]] = trunc i32 [[TMP24]] to i15
5178; CHECK-NEXT:    [[TMP26:%.*]] = insertelement <3 x i15> undef, i15 [[TMP25]], i64 0
5179; CHECK-NEXT:    [[TMP27:%.*]] = extractelement <3 x i15> [[X]], i64 1
5180; CHECK-NEXT:    [[TMP28:%.*]] = extractelement <3 x i15> [[Y]], i64 1
5181; CHECK-NEXT:    [[TMP29:%.*]] = sext i15 [[TMP27]] to i32
5182; CHECK-NEXT:    [[TMP30:%.*]] = sext i15 [[TMP28]] to i32
5183; CHECK-NEXT:    [[TMP31:%.*]] = xor i32 [[TMP29]], [[TMP30]]
5184; CHECK-NEXT:    [[TMP32:%.*]] = ashr i32 [[TMP31]], 30
5185; CHECK-NEXT:    [[TMP33:%.*]] = or i32 [[TMP32]], 1
5186; CHECK-NEXT:    [[TMP34:%.*]] = sitofp i32 [[TMP29]] to float
5187; CHECK-NEXT:    [[TMP35:%.*]] = sitofp i32 [[TMP30]] to float
5188; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])
5189; CHECK-NEXT:    [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]]
5190; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]])
5191; CHECK-NEXT:    [[TMP39:%.*]] = fneg fast float [[TMP38]]
5192; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]])
5193; CHECK-NEXT:    [[TMP41:%.*]] = fptosi float [[TMP38]] to i32
5194; CHECK-NEXT:    [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]])
5195; CHECK-NEXT:    [[TMP43:%.*]] = call fast float @llvm.fabs.f32(float [[TMP35]])
5196; CHECK-NEXT:    [[TMP44:%.*]] = fcmp fast oge float [[TMP42]], [[TMP43]]
5197; CHECK-NEXT:    [[TMP45:%.*]] = select i1 [[TMP44]], i32 [[TMP33]], i32 0
5198; CHECK-NEXT:    [[TMP46:%.*]] = add i32 [[TMP41]], [[TMP45]]
5199; CHECK-NEXT:    [[TMP47:%.*]] = mul i32 [[TMP46]], [[TMP30]]
5200; CHECK-NEXT:    [[TMP48:%.*]] = sub i32 [[TMP29]], [[TMP47]]
5201; CHECK-NEXT:    [[TMP49:%.*]] = shl i32 [[TMP48]], 17
5202; CHECK-NEXT:    [[TMP50:%.*]] = ashr i32 [[TMP49]], 17
5203; CHECK-NEXT:    [[TMP51:%.*]] = trunc i32 [[TMP50]] to i15
5204; CHECK-NEXT:    [[TMP52:%.*]] = insertelement <3 x i15> [[TMP26]], i15 [[TMP51]], i64 1
5205; CHECK-NEXT:    [[TMP53:%.*]] = extractelement <3 x i15> [[X]], i64 2
5206; CHECK-NEXT:    [[TMP54:%.*]] = extractelement <3 x i15> [[Y]], i64 2
5207; CHECK-NEXT:    [[TMP55:%.*]] = sext i15 [[TMP53]] to i32
5208; CHECK-NEXT:    [[TMP56:%.*]] = sext i15 [[TMP54]] to i32
5209; CHECK-NEXT:    [[TMP57:%.*]] = xor i32 [[TMP55]], [[TMP56]]
5210; CHECK-NEXT:    [[TMP58:%.*]] = ashr i32 [[TMP57]], 30
5211; CHECK-NEXT:    [[TMP59:%.*]] = or i32 [[TMP58]], 1
5212; CHECK-NEXT:    [[TMP60:%.*]] = sitofp i32 [[TMP55]] to float
5213; CHECK-NEXT:    [[TMP61:%.*]] = sitofp i32 [[TMP56]] to float
5214; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP61]])
5215; CHECK-NEXT:    [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]]
5216; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]])
5217; CHECK-NEXT:    [[TMP65:%.*]] = fneg fast float [[TMP64]]
5218; CHECK-NEXT:    [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]])
5219; CHECK-NEXT:    [[TMP67:%.*]] = fptosi float [[TMP64]] to i32
5220; CHECK-NEXT:    [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]])
5221; CHECK-NEXT:    [[TMP69:%.*]] = call fast float @llvm.fabs.f32(float [[TMP61]])
5222; CHECK-NEXT:    [[TMP70:%.*]] = fcmp fast oge float [[TMP68]], [[TMP69]]
5223; CHECK-NEXT:    [[TMP71:%.*]] = select i1 [[TMP70]], i32 [[TMP59]], i32 0
5224; CHECK-NEXT:    [[TMP72:%.*]] = add i32 [[TMP67]], [[TMP71]]
5225; CHECK-NEXT:    [[TMP73:%.*]] = mul i32 [[TMP72]], [[TMP56]]
5226; CHECK-NEXT:    [[TMP74:%.*]] = sub i32 [[TMP55]], [[TMP73]]
5227; CHECK-NEXT:    [[TMP75:%.*]] = shl i32 [[TMP74]], 17
5228; CHECK-NEXT:    [[TMP76:%.*]] = ashr i32 [[TMP75]], 17
5229; CHECK-NEXT:    [[TMP77:%.*]] = trunc i32 [[TMP76]] to i15
5230; CHECK-NEXT:    [[TMP78:%.*]] = insertelement <3 x i15> [[TMP52]], i15 [[TMP77]], i64 2
5231; CHECK-NEXT:    store <3 x i15> [[TMP78]], <3 x i15> addrspace(1)* [[OUT:%.*]], align 8
5232; CHECK-NEXT:    ret void
5233;
5234; GFX6-LABEL: srem_v3i15:
5235; GFX6:       ; %bb.0:
5236; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
5237; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
5238; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
5239; GFX6-NEXT:    s_mov_b32 s7, 0xf000
5240; GFX6-NEXT:    s_mov_b32 s6, -1
5241; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5242; GFX6-NEXT:    v_mov_b32_e32 v0, s2
5243; GFX6-NEXT:    v_alignbit_b32 v0, s3, v0, 30
5244; GFX6-NEXT:    s_movk_i32 s3, 0x7fff
5245; GFX6-NEXT:    s_and_b32 s11, s0, s3
5246; GFX6-NEXT:    s_bfe_i32 s11, s11, 0xf0000
5247; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s11
5248; GFX6-NEXT:    s_and_b32 s9, s2, s3
5249; GFX6-NEXT:    s_bfe_i32 s9, s9, 0xf0000
5250; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s9
5251; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
5252; GFX6-NEXT:    s_xor_b32 s9, s9, s11
5253; GFX6-NEXT:    s_ashr_i32 s9, s9, 30
5254; GFX6-NEXT:    s_or_b32 s9, s9, 1
5255; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
5256; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
5257; GFX6-NEXT:    v_mad_f32 v3, -v4, v2, v3
5258; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v4
5259; GFX6-NEXT:    v_mov_b32_e32 v5, s9
5260; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
5261; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
5262; GFX6-NEXT:    v_mov_b32_e32 v1, s0
5263; GFX6-NEXT:    s_bfe_u32 s12, s0, 0xf000f
5264; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
5265; GFX6-NEXT:    v_alignbit_b32 v1, s1, v1, 30
5266; GFX6-NEXT:    s_lshr_b32 s1, s0, 15
5267; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s0
5268; GFX6-NEXT:    s_bfe_i32 s0, s12, 0xf0000
5269; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s0
5270; GFX6-NEXT:    s_bfe_u32 s10, s2, 0xf000f
5271; GFX6-NEXT:    s_lshr_b32 s8, s2, 15
5272; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s2, v2
5273; GFX6-NEXT:    s_bfe_i32 s2, s10, 0xf0000
5274; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s2
5275; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
5276; GFX6-NEXT:    s_xor_b32 s0, s2, s0
5277; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
5278; GFX6-NEXT:    s_or_b32 s0, s0, 1
5279; GFX6-NEXT:    v_mul_f32_e32 v5, v4, v5
5280; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
5281; GFX6-NEXT:    v_mad_f32 v4, -v5, v3, v4
5282; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
5283; GFX6-NEXT:    v_and_b32_e32 v1, s3, v1
5284; GFX6-NEXT:    v_mov_b32_e32 v6, s0
5285; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v3|
5286; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v6, vcc
5287; GFX6-NEXT:    v_bfe_i32 v4, v1, 0, 15
5288; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
5289; GFX6-NEXT:    v_cvt_f32_i32_e32 v5, v4
5290; GFX6-NEXT:    v_and_b32_e32 v0, s3, v0
5291; GFX6-NEXT:    v_bfe_i32 v6, v0, 0, 15
5292; GFX6-NEXT:    v_cvt_f32_i32_e32 v7, v6
5293; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v5
5294; GFX6-NEXT:    v_xor_b32_e32 v4, v6, v4
5295; GFX6-NEXT:    v_ashrrev_i32_e32 v4, 30, v4
5296; GFX6-NEXT:    v_or_b32_e32 v4, 1, v4
5297; GFX6-NEXT:    v_mul_f32_e32 v6, v7, v8
5298; GFX6-NEXT:    v_trunc_f32_e32 v6, v6
5299; GFX6-NEXT:    v_mad_f32 v7, -v6, v5, v7
5300; GFX6-NEXT:    v_cvt_i32_f32_e32 v6, v6
5301; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v7|, |v5|
5302; GFX6-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
5303; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s1
5304; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
5305; GFX6-NEXT:    v_mul_lo_u32 v1, v4, v1
5306; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s8, v3
5307; GFX6-NEXT:    v_and_b32_e32 v3, s3, v3
5308; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, v1, v0
5309; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 30
5310; GFX6-NEXT:    v_and_b32_e32 v2, s3, v2
5311; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
5312; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
5313; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
5314; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
5315; GFX6-NEXT:    s_waitcnt expcnt(0)
5316; GFX6-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
5317; GFX6-NEXT:    buffer_store_short v0, off, s[4:7], 0 offset:4
5318; GFX6-NEXT:    s_endpgm
5319;
5320; GFX9-LABEL: srem_v3i15:
5321; GFX9:       ; %bb.0:
5322; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
5323; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
5324; GFX9-NEXT:    s_movk_i32 s8, 0x7fff
5325; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
5326; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5327; GFX9-NEXT:    v_mov_b32_e32 v0, s2
5328; GFX9-NEXT:    v_alignbit_b32 v0, s3, v0, 30
5329; GFX9-NEXT:    s_and_b32 s3, s2, s8
5330; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5331; GFX9-NEXT:    v_alignbit_b32 v1, s1, v1, 30
5332; GFX9-NEXT:    s_and_b32 s1, s0, s8
5333; GFX9-NEXT:    s_bfe_i32 s1, s1, 0xf0000
5334; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s1
5335; GFX9-NEXT:    s_bfe_i32 s3, s3, 0xf0000
5336; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s3
5337; GFX9-NEXT:    s_xor_b32 s1, s3, s1
5338; GFX9-NEXT:    v_rcp_iflag_f32_e32 v4, v2
5339; GFX9-NEXT:    s_ashr_i32 s1, s1, 30
5340; GFX9-NEXT:    s_lshr_b32 s9, s2, 15
5341; GFX9-NEXT:    s_bfe_u32 s10, s2, 0xf000f
5342; GFX9-NEXT:    v_mul_f32_e32 v4, v3, v4
5343; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
5344; GFX9-NEXT:    v_mad_f32 v3, -v4, v2, v3
5345; GFX9-NEXT:    v_cvt_i32_f32_e32 v4, v4
5346; GFX9-NEXT:    s_lshr_b32 s11, s0, 15
5347; GFX9-NEXT:    s_bfe_u32 s12, s0, 0xf000f
5348; GFX9-NEXT:    s_or_b32 s1, s1, 1
5349; GFX9-NEXT:    v_cmp_ge_f32_e64 s[6:7], |v3|, |v2|
5350; GFX9-NEXT:    s_and_b64 s[6:7], s[6:7], exec
5351; GFX9-NEXT:    s_cselect_b32 s1, s1, 0
5352; GFX9-NEXT:    v_add_u32_e32 v2, s1, v4
5353; GFX9-NEXT:    s_bfe_i32 s1, s12, 0xf0000
5354; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s1
5355; GFX9-NEXT:    v_mul_lo_u32 v2, v2, s0
5356; GFX9-NEXT:    s_bfe_i32 s0, s10, 0xf0000
5357; GFX9-NEXT:    v_cvt_f32_i32_e32 v4, s0
5358; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v3
5359; GFX9-NEXT:    s_xor_b32 s0, s0, s1
5360; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
5361; GFX9-NEXT:    s_or_b32 s3, s0, 1
5362; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
5363; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
5364; GFX9-NEXT:    v_mad_f32 v4, -v5, v3, v4
5365; GFX9-NEXT:    v_cvt_i32_f32_e32 v5, v5
5366; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v4|, |v3|
5367; GFX9-NEXT:    v_and_b32_e32 v1, s8, v1
5368; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
5369; GFX9-NEXT:    s_cselect_b32 s0, s3, 0
5370; GFX9-NEXT:    v_bfe_i32 v4, v1, 0, 15
5371; GFX9-NEXT:    v_add_u32_e32 v3, s0, v5
5372; GFX9-NEXT:    v_cvt_f32_i32_e32 v5, v4
5373; GFX9-NEXT:    v_and_b32_e32 v0, s8, v0
5374; GFX9-NEXT:    v_bfe_i32 v6, v0, 0, 15
5375; GFX9-NEXT:    v_cvt_f32_i32_e32 v7, v6
5376; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v5
5377; GFX9-NEXT:    v_xor_b32_e32 v4, v6, v4
5378; GFX9-NEXT:    v_ashrrev_i32_e32 v4, 30, v4
5379; GFX9-NEXT:    v_or_b32_e32 v4, 1, v4
5380; GFX9-NEXT:    v_mul_f32_e32 v6, v7, v8
5381; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
5382; GFX9-NEXT:    v_cvt_i32_f32_e32 v8, v6
5383; GFX9-NEXT:    v_mad_f32 v6, -v6, v5, v7
5384; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, |v5|
5385; GFX9-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
5386; GFX9-NEXT:    v_mul_lo_u32 v3, v3, s11
5387; GFX9-NEXT:    v_add_u32_e32 v4, v8, v4
5388; GFX9-NEXT:    v_mul_lo_u32 v1, v4, v1
5389; GFX9-NEXT:    v_sub_u32_e32 v2, s2, v2
5390; GFX9-NEXT:    v_sub_u32_e32 v3, s9, v3
5391; GFX9-NEXT:    v_and_b32_e32 v3, s8, v3
5392; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v1
5393; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 30, v[0:1]
5394; GFX9-NEXT:    v_and_b32_e32 v2, s8, v2
5395; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
5396; GFX9-NEXT:    v_or_b32_e32 v2, v2, v3
5397; GFX9-NEXT:    v_mov_b32_e32 v4, 0
5398; GFX9-NEXT:    v_or_b32_e32 v0, v2, v0
5399; GFX9-NEXT:    global_store_dword v4, v0, s[4:5]
5400; GFX9-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
5401; GFX9-NEXT:    global_store_short v4, v0, s[4:5] offset:4
5402; GFX9-NEXT:    s_endpgm
5403  %r = srem <3 x i15> %x, %y
5404  store <3 x i15> %r, <3 x i15> addrspace(1)* %out
5405  ret void
5406}
5407
5408define amdgpu_kernel void @udiv_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
5409; CHECK-LABEL: @udiv_i32_oddk_denom(
5410; CHECK-NEXT:    [[R:%.*]] = udiv i32 [[X:%.*]], 1235195
5411; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
5412; CHECK-NEXT:    ret void
5413;
5414; GFX6-LABEL: udiv_i32_oddk_denom:
5415; GFX6:       ; %bb.0:
5416; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
5417; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
5418; GFX6-NEXT:    v_mov_b32_e32 v0, 0xb2a50881
5419; GFX6-NEXT:    s_mov_b32 s3, 0xf000
5420; GFX6-NEXT:    s_mov_b32 s2, -1
5421; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5422; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
5423; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s4, v0
5424; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
5425; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
5426; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 20, v0
5427; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
5428; GFX6-NEXT:    s_endpgm
5429;
5430; GFX9-LABEL: udiv_i32_oddk_denom:
5431; GFX9:       ; %bb.0:
5432; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
5433; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
5434; GFX9-NEXT:    v_mov_b32_e32 v0, 0
5435; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5436; GFX9-NEXT:    s_mul_hi_u32 s0, s4, 0xb2a50881
5437; GFX9-NEXT:    s_sub_i32 s1, s4, s0
5438; GFX9-NEXT:    s_lshr_b32 s1, s1, 1
5439; GFX9-NEXT:    s_add_i32 s1, s1, s0
5440; GFX9-NEXT:    s_lshr_b32 s0, s1, 20
5441; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5442; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
5443; GFX9-NEXT:    s_endpgm
5444  %r = udiv i32 %x, 1235195
5445  store i32 %r, i32 addrspace(1)* %out
5446  ret void
5447}
5448
5449define amdgpu_kernel void @udiv_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x) {
5450; CHECK-LABEL: @udiv_i32_pow2k_denom(
5451; CHECK-NEXT:    [[R:%.*]] = udiv i32 [[X:%.*]], 4096
5452; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
5453; CHECK-NEXT:    ret void
5454;
5455; GFX6-LABEL: udiv_i32_pow2k_denom:
5456; GFX6:       ; %bb.0:
5457; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
5458; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
5459; GFX6-NEXT:    s_mov_b32 s3, 0xf000
5460; GFX6-NEXT:    s_mov_b32 s2, -1
5461; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5462; GFX6-NEXT:    s_lshr_b32 s4, s4, 12
5463; GFX6-NEXT:    v_mov_b32_e32 v0, s4
5464; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
5465; GFX6-NEXT:    s_endpgm
5466;
5467; GFX9-LABEL: udiv_i32_pow2k_denom:
5468; GFX9:       ; %bb.0:
5469; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
5470; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
5471; GFX9-NEXT:    v_mov_b32_e32 v0, 0
5472; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5473; GFX9-NEXT:    s_lshr_b32 s0, s4, 12
5474; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5475; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
5476; GFX9-NEXT:    s_endpgm
5477  %r = udiv i32 %x, 4096
5478  store i32 %r, i32 addrspace(1)* %out
5479  ret void
5480}
5481
5482define amdgpu_kernel void @udiv_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %x, i32 %y) {
5483; CHECK-LABEL: @udiv_i32_pow2_shl_denom(
5484; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]]
5485; CHECK-NEXT:    [[R:%.*]] = udiv i32 [[X:%.*]], [[SHL_Y]]
5486; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
5487; CHECK-NEXT:    ret void
5488;
5489; GFX6-LABEL: udiv_i32_pow2_shl_denom:
5490; GFX6:       ; %bb.0:
5491; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
5492; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
5493; GFX6-NEXT:    s_mov_b32 s3, 0xf000
5494; GFX6-NEXT:    s_mov_b32 s2, -1
5495; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5496; GFX6-NEXT:    s_add_i32 s5, s5, 12
5497; GFX6-NEXT:    s_lshr_b32 s4, s4, s5
5498; GFX6-NEXT:    v_mov_b32_e32 v0, s4
5499; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
5500; GFX6-NEXT:    s_endpgm
5501;
5502; GFX9-LABEL: udiv_i32_pow2_shl_denom:
5503; GFX9:       ; %bb.0:
5504; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
5505; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
5506; GFX9-NEXT:    v_mov_b32_e32 v0, 0
5507; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5508; GFX9-NEXT:    s_add_i32 s0, s3, 12
5509; GFX9-NEXT:    s_lshr_b32 s0, s2, s0
5510; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5511; GFX9-NEXT:    global_store_dword v0, v1, s[4:5]
5512; GFX9-NEXT:    s_endpgm
5513  %shl.y = shl i32 4096, %y
5514  %r = udiv i32 %x, %shl.y
5515  store i32 %r, i32 addrspace(1)* %out
5516  ret void
5517}
5518
5519define amdgpu_kernel void @udiv_v2i32_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) {
5520; CHECK-LABEL: @udiv_v2i32_pow2k_denom(
5521; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
5522; CHECK-NEXT:    [[TMP2:%.*]] = udiv i32 [[TMP1]], 4096
5523; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0
5524; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1
5525; CHECK-NEXT:    [[TMP5:%.*]] = udiv i32 [[TMP4]], 4096
5526; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1
5527; CHECK-NEXT:    store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
5528; CHECK-NEXT:    ret void
5529;
5530; GFX6-LABEL: udiv_v2i32_pow2k_denom:
5531; GFX6:       ; %bb.0:
5532; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
5533; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
5534; GFX6-NEXT:    s_mov_b32 s3, 0xf000
5535; GFX6-NEXT:    s_mov_b32 s2, -1
5536; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5537; GFX6-NEXT:    s_lshr_b32 s4, s4, 12
5538; GFX6-NEXT:    s_lshr_b32 s5, s5, 12
5539; GFX6-NEXT:    v_mov_b32_e32 v0, s4
5540; GFX6-NEXT:    v_mov_b32_e32 v1, s5
5541; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
5542; GFX6-NEXT:    s_endpgm
5543;
5544; GFX9-LABEL: udiv_v2i32_pow2k_denom:
5545; GFX9:       ; %bb.0:
5546; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
5547; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
5548; GFX9-NEXT:    v_mov_b32_e32 v2, 0
5549; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5550; GFX9-NEXT:    s_lshr_b32 s0, s2, 12
5551; GFX9-NEXT:    s_lshr_b32 s1, s3, 12
5552; GFX9-NEXT:    v_mov_b32_e32 v0, s0
5553; GFX9-NEXT:    v_mov_b32_e32 v1, s1
5554; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
5555; GFX9-NEXT:    s_endpgm
5556  %r = udiv <2 x i32> %x, <i32 4096, i32 4096>
5557  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
5558  ret void
5559}
5560
5561define amdgpu_kernel void @udiv_v2i32_mixed_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) {
5562; CHECK-LABEL: @udiv_v2i32_mixed_pow2k_denom(
5563; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
5564; CHECK-NEXT:    [[TMP2:%.*]] = udiv i32 [[TMP1]], 4096
5565; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0
5566; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1
5567; CHECK-NEXT:    [[TMP5:%.*]] = udiv i32 [[TMP4]], 4095
5568; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1
5569; CHECK-NEXT:    store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
5570; CHECK-NEXT:    ret void
5571;
5572; GFX6-LABEL: udiv_v2i32_mixed_pow2k_denom:
5573; GFX6:       ; %bb.0:
5574; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
5575; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
5576; GFX6-NEXT:    v_mov_b32_e32 v0, 0x100101
5577; GFX6-NEXT:    s_mov_b32 s3, 0xf000
5578; GFX6-NEXT:    s_mov_b32 s2, -1
5579; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5580; GFX6-NEXT:    v_mul_hi_u32 v0, s5, v0
5581; GFX6-NEXT:    s_lshr_b32 s4, s4, 12
5582; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v0
5583; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
5584; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
5585; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 11, v0
5586; GFX6-NEXT:    v_mov_b32_e32 v0, s4
5587; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
5588; GFX6-NEXT:    s_endpgm
5589;
5590; GFX9-LABEL: udiv_v2i32_mixed_pow2k_denom:
5591; GFX9:       ; %bb.0:
5592; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
5593; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
5594; GFX9-NEXT:    v_mov_b32_e32 v2, 0
5595; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5596; GFX9-NEXT:    s_mul_hi_u32 s1, s3, 0x100101
5597; GFX9-NEXT:    s_lshr_b32 s0, s2, 12
5598; GFX9-NEXT:    s_sub_i32 s2, s3, s1
5599; GFX9-NEXT:    s_lshr_b32 s2, s2, 1
5600; GFX9-NEXT:    s_add_i32 s2, s2, s1
5601; GFX9-NEXT:    s_lshr_b32 s1, s2, 11
5602; GFX9-NEXT:    v_mov_b32_e32 v0, s0
5603; GFX9-NEXT:    v_mov_b32_e32 v1, s1
5604; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
5605; GFX9-NEXT:    s_endpgm
5606  %r = udiv <2 x i32> %x, <i32 4096, i32 4095>
5607  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
5608  ret void
5609}
5610
5611define amdgpu_kernel void @udiv_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) {
5612; CHECK-LABEL: @udiv_v2i32_pow2_shl_denom(
5613; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i32> <i32 4096, i32 4096>, [[Y:%.*]]
5614; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
5615; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 0
5616; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float
5617; CHECK-NEXT:    [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])
5618; CHECK-NEXT:    [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41EFFFFFC0000000
5619; CHECK-NEXT:    [[TMP6:%.*]] = fptoui float [[TMP5]] to i32
5620; CHECK-NEXT:    [[TMP7:%.*]] = sub i32 0, [[TMP2]]
5621; CHECK-NEXT:    [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP6]]
5622; CHECK-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP6]] to i64
5623; CHECK-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP8]] to i64
5624; CHECK-NEXT:    [[TMP11:%.*]] = mul i64 [[TMP9]], [[TMP10]]
5625; CHECK-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
5626; CHECK-NEXT:    [[TMP13:%.*]] = lshr i64 [[TMP11]], 32
5627; CHECK-NEXT:    [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32
5628; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP6]], [[TMP14]]
5629; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP1]] to i64
5630; CHECK-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP15]] to i64
5631; CHECK-NEXT:    [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]
5632; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
5633; CHECK-NEXT:    [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
5634; CHECK-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
5635; CHECK-NEXT:    [[TMP22:%.*]] = mul i32 [[TMP21]], [[TMP2]]
5636; CHECK-NEXT:    [[TMP23:%.*]] = sub i32 [[TMP1]], [[TMP22]]
5637; CHECK-NEXT:    [[TMP24:%.*]] = icmp uge i32 [[TMP23]], [[TMP2]]
5638; CHECK-NEXT:    [[TMP25:%.*]] = add i32 [[TMP21]], 1
5639; CHECK-NEXT:    [[TMP26:%.*]] = select i1 [[TMP24]], i32 [[TMP25]], i32 [[TMP21]]
5640; CHECK-NEXT:    [[TMP27:%.*]] = sub i32 [[TMP23]], [[TMP2]]
5641; CHECK-NEXT:    [[TMP28:%.*]] = select i1 [[TMP24]], i32 [[TMP27]], i32 [[TMP23]]
5642; CHECK-NEXT:    [[TMP29:%.*]] = icmp uge i32 [[TMP28]], [[TMP2]]
5643; CHECK-NEXT:    [[TMP30:%.*]] = add i32 [[TMP26]], 1
5644; CHECK-NEXT:    [[TMP31:%.*]] = select i1 [[TMP29]], i32 [[TMP30]], i32 [[TMP26]]
5645; CHECK-NEXT:    [[TMP32:%.*]] = insertelement <2 x i32> undef, i32 [[TMP31]], i64 0
5646; CHECK-NEXT:    [[TMP33:%.*]] = extractelement <2 x i32> [[X]], i64 1
5647; CHECK-NEXT:    [[TMP34:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1
5648; CHECK-NEXT:    [[TMP35:%.*]] = uitofp i32 [[TMP34]] to float
5649; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])
5650; CHECK-NEXT:    [[TMP37:%.*]] = fmul fast float [[TMP36]], 0x41EFFFFFC0000000
5651; CHECK-NEXT:    [[TMP38:%.*]] = fptoui float [[TMP37]] to i32
5652; CHECK-NEXT:    [[TMP39:%.*]] = sub i32 0, [[TMP34]]
5653; CHECK-NEXT:    [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP38]]
5654; CHECK-NEXT:    [[TMP41:%.*]] = zext i32 [[TMP38]] to i64
5655; CHECK-NEXT:    [[TMP42:%.*]] = zext i32 [[TMP40]] to i64
5656; CHECK-NEXT:    [[TMP43:%.*]] = mul i64 [[TMP41]], [[TMP42]]
5657; CHECK-NEXT:    [[TMP44:%.*]] = trunc i64 [[TMP43]] to i32
5658; CHECK-NEXT:    [[TMP45:%.*]] = lshr i64 [[TMP43]], 32
5659; CHECK-NEXT:    [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32
5660; CHECK-NEXT:    [[TMP47:%.*]] = add i32 [[TMP38]], [[TMP46]]
5661; CHECK-NEXT:    [[TMP48:%.*]] = zext i32 [[TMP33]] to i64
5662; CHECK-NEXT:    [[TMP49:%.*]] = zext i32 [[TMP47]] to i64
5663; CHECK-NEXT:    [[TMP50:%.*]] = mul i64 [[TMP48]], [[TMP49]]
5664; CHECK-NEXT:    [[TMP51:%.*]] = trunc i64 [[TMP50]] to i32
5665; CHECK-NEXT:    [[TMP52:%.*]] = lshr i64 [[TMP50]], 32
5666; CHECK-NEXT:    [[TMP53:%.*]] = trunc i64 [[TMP52]] to i32
5667; CHECK-NEXT:    [[TMP54:%.*]] = mul i32 [[TMP53]], [[TMP34]]
5668; CHECK-NEXT:    [[TMP55:%.*]] = sub i32 [[TMP33]], [[TMP54]]
5669; CHECK-NEXT:    [[TMP56:%.*]] = icmp uge i32 [[TMP55]], [[TMP34]]
5670; CHECK-NEXT:    [[TMP57:%.*]] = add i32 [[TMP53]], 1
5671; CHECK-NEXT:    [[TMP58:%.*]] = select i1 [[TMP56]], i32 [[TMP57]], i32 [[TMP53]]
5672; CHECK-NEXT:    [[TMP59:%.*]] = sub i32 [[TMP55]], [[TMP34]]
5673; CHECK-NEXT:    [[TMP60:%.*]] = select i1 [[TMP56]], i32 [[TMP59]], i32 [[TMP55]]
5674; CHECK-NEXT:    [[TMP61:%.*]] = icmp uge i32 [[TMP60]], [[TMP34]]
5675; CHECK-NEXT:    [[TMP62:%.*]] = add i32 [[TMP58]], 1
5676; CHECK-NEXT:    [[TMP63:%.*]] = select i1 [[TMP61]], i32 [[TMP62]], i32 [[TMP58]]
5677; CHECK-NEXT:    [[TMP64:%.*]] = insertelement <2 x i32> [[TMP32]], i32 [[TMP63]], i64 1
5678; CHECK-NEXT:    store <2 x i32> [[TMP64]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
5679; CHECK-NEXT:    ret void
5680;
5681; GFX6-LABEL: udiv_v2i32_pow2_shl_denom:
5682; GFX6:       ; %bb.0:
5683; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
5684; GFX6-NEXT:    s_movk_i32 s4, 0x1000
5685; GFX6-NEXT:    s_mov_b32 s7, 0xf000
5686; GFX6-NEXT:    s_mov_b32 s6, -1
5687; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5688; GFX6-NEXT:    s_lshl_b32 s8, s4, s2
5689; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
5690; GFX6-NEXT:    s_lshl_b32 s9, s4, s3
5691; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
5692; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
5693; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
5694; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
5695; GFX6-NEXT:    s_mov_b32 s0, 0x4f7ffffe
5696; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
5697; GFX6-NEXT:    v_mul_f32_e32 v0, s0, v0
5698; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
5699; GFX6-NEXT:    v_mul_f32_e32 v1, s0, v1
5700; GFX6-NEXT:    s_sub_i32 s0, 0, s8
5701; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
5702; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v0
5703; GFX6-NEXT:    s_sub_i32 s0, 0, s9
5704; GFX6-NEXT:    v_mul_lo_u32 v3, s0, v1
5705; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
5706; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
5707; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
5708; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5709; GFX6-NEXT:    v_mul_hi_u32 v0, s2, v0
5710; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
5711; GFX6-NEXT:    v_mul_hi_u32 v1, s3, v1
5712; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s8
5713; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
5714; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s9
5715; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s2, v2
5716; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v2
5717; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[0:1]
5718; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v2
5719; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
5720; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
5721; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
5722; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
5723; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s3, v4
5724; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
5725; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v2
5726; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
5727; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s9, v2
5728; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
5729; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
5730; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
5731; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5732; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
5733; GFX6-NEXT:    s_endpgm
5734;
5735; GFX9-LABEL: udiv_v2i32_pow2_shl_denom:
5736; GFX9:       ; %bb.0:
5737; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
5738; GFX9-NEXT:    s_movk_i32 s4, 0x1000
5739; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5740; GFX9-NEXT:    s_lshl_b32 s5, s4, s3
5741; GFX9-NEXT:    s_lshl_b32 s4, s4, s2
5742; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s4
5743; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s5
5744; GFX9-NEXT:    s_mov_b32 s2, 0x4f7ffffe
5745; GFX9-NEXT:    s_sub_i32 s3, 0, s5
5746; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
5747; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
5748; GFX9-NEXT:    v_mul_f32_e32 v0, s2, v0
5749; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
5750; GFX9-NEXT:    v_mul_f32_e32 v1, s2, v1
5751; GFX9-NEXT:    s_sub_i32 s2, 0, s4
5752; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
5753; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v0
5754; GFX9-NEXT:    v_mul_lo_u32 v3, s3, v1
5755; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
5756; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
5757; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
5758; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
5759; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
5760; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5761; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
5762; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
5763; GFX9-NEXT:    v_mul_hi_u32 v1, s3, v1
5764; GFX9-NEXT:    v_mov_b32_e32 v2, 0
5765; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s4
5766; GFX9-NEXT:    v_add_u32_e32 v5, 1, v0
5767; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s5
5768; GFX9-NEXT:    v_add_u32_e32 v6, 1, v1
5769; GFX9-NEXT:    v_sub_u32_e32 v3, s2, v3
5770; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v3
5771; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
5772; GFX9-NEXT:    v_subrev_u32_e32 v5, s4, v3
5773; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
5774; GFX9-NEXT:    v_sub_u32_e32 v4, s3, v4
5775; GFX9-NEXT:    v_add_u32_e32 v5, 1, v0
5776; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v3
5777; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
5778; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v4
5779; GFX9-NEXT:    v_subrev_u32_e32 v3, s5, v4
5780; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc
5781; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
5782; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
5783; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v3
5784; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
5785; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
5786; GFX9-NEXT:    s_endpgm
5787  %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
5788  %r = udiv <2 x i32> %x, %shl.y
5789  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
5790  ret void
5791}
5792
5793define amdgpu_kernel void @urem_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
5794; CHECK-LABEL: @urem_i32_oddk_denom(
5795; CHECK-NEXT:    [[R:%.*]] = urem i32 [[X:%.*]], 1235195
5796; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
5797; CHECK-NEXT:    ret void
5798;
5799; GFX6-LABEL: urem_i32_oddk_denom:
5800; GFX6:       ; %bb.0:
5801; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
5802; GFX6-NEXT:    v_mov_b32_e32 v0, 0xb2a50881
5803; GFX6-NEXT:    s_mov_b32 s2, 0x12d8fb
5804; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
5805; GFX6-NEXT:    s_mov_b32 s3, 0xf000
5806; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5807; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
5808; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s4, v0
5809; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
5810; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
5811; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 20, v0
5812; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
5813; GFX6-NEXT:    s_mov_b32 s2, -1
5814; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
5815; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
5816; GFX6-NEXT:    s_endpgm
5817;
5818; GFX9-LABEL: urem_i32_oddk_denom:
5819; GFX9:       ; %bb.0:
5820; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
5821; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
5822; GFX9-NEXT:    v_mov_b32_e32 v0, 0
5823; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5824; GFX9-NEXT:    s_mul_hi_u32 s0, s4, 0xb2a50881
5825; GFX9-NEXT:    s_sub_i32 s1, s4, s0
5826; GFX9-NEXT:    s_lshr_b32 s1, s1, 1
5827; GFX9-NEXT:    s_add_i32 s1, s1, s0
5828; GFX9-NEXT:    s_lshr_b32 s0, s1, 20
5829; GFX9-NEXT:    s_mul_i32 s0, s0, 0x12d8fb
5830; GFX9-NEXT:    s_sub_i32 s0, s4, s0
5831; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5832; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
5833; GFX9-NEXT:    s_endpgm
5834  %r = urem i32 %x, 1235195
5835  store i32 %r, i32 addrspace(1)* %out
5836  ret void
5837}
5838
5839define amdgpu_kernel void @urem_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x) {
5840; CHECK-LABEL: @urem_i32_pow2k_denom(
5841; CHECK-NEXT:    [[R:%.*]] = urem i32 [[X:%.*]], 4096
5842; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
5843; CHECK-NEXT:    ret void
5844;
5845; GFX6-LABEL: urem_i32_pow2k_denom:
5846; GFX6:       ; %bb.0:
5847; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
5848; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
5849; GFX6-NEXT:    s_mov_b32 s3, 0xf000
5850; GFX6-NEXT:    s_mov_b32 s2, -1
5851; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5852; GFX6-NEXT:    s_and_b32 s4, s4, 0xfff
5853; GFX6-NEXT:    v_mov_b32_e32 v0, s4
5854; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
5855; GFX6-NEXT:    s_endpgm
5856;
5857; GFX9-LABEL: urem_i32_pow2k_denom:
5858; GFX9:       ; %bb.0:
5859; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
5860; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
5861; GFX9-NEXT:    v_mov_b32_e32 v0, 0
5862; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5863; GFX9-NEXT:    s_and_b32 s0, s4, 0xfff
5864; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5865; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
5866; GFX9-NEXT:    s_endpgm
5867  %r = urem i32 %x, 4096
5868  store i32 %r, i32 addrspace(1)* %out
5869  ret void
5870}
5871
5872define amdgpu_kernel void @urem_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %x, i32 %y) {
5873; CHECK-LABEL: @urem_i32_pow2_shl_denom(
5874; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]]
5875; CHECK-NEXT:    [[R:%.*]] = urem i32 [[X:%.*]], [[SHL_Y]]
5876; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
5877; CHECK-NEXT:    ret void
5878;
5879; GFX6-LABEL: urem_i32_pow2_shl_denom:
5880; GFX6:       ; %bb.0:
5881; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
5882; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
5883; GFX6-NEXT:    s_mov_b32 s3, 0xf000
5884; GFX6-NEXT:    s_mov_b32 s2, -1
5885; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5886; GFX6-NEXT:    s_lshl_b32 s5, 0x1000, s5
5887; GFX6-NEXT:    s_add_i32 s5, s5, -1
5888; GFX6-NEXT:    s_and_b32 s4, s4, s5
5889; GFX6-NEXT:    v_mov_b32_e32 v0, s4
5890; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
5891; GFX6-NEXT:    s_endpgm
5892;
5893; GFX9-LABEL: urem_i32_pow2_shl_denom:
5894; GFX9:       ; %bb.0:
5895; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
5896; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
5897; GFX9-NEXT:    v_mov_b32_e32 v0, 0
5898; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5899; GFX9-NEXT:    s_lshl_b32 s0, 0x1000, s3
5900; GFX9-NEXT:    s_add_i32 s0, s0, -1
5901; GFX9-NEXT:    s_and_b32 s0, s2, s0
5902; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5903; GFX9-NEXT:    global_store_dword v0, v1, s[4:5]
5904; GFX9-NEXT:    s_endpgm
5905  %shl.y = shl i32 4096, %y
5906  %r = urem i32 %x, %shl.y
5907  store i32 %r, i32 addrspace(1)* %out
5908  ret void
5909}
5910
5911define amdgpu_kernel void @urem_v2i32_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) {
5912; CHECK-LABEL: @urem_v2i32_pow2k_denom(
5913; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
5914; CHECK-NEXT:    [[TMP2:%.*]] = urem i32 [[TMP1]], 4096
5915; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0
5916; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1
5917; CHECK-NEXT:    [[TMP5:%.*]] = urem i32 [[TMP4]], 4096
5918; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1
5919; CHECK-NEXT:    store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
5920; CHECK-NEXT:    ret void
5921;
5922; GFX6-LABEL: urem_v2i32_pow2k_denom:
5923; GFX6:       ; %bb.0:
5924; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
5925; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
5926; GFX6-NEXT:    s_movk_i32 s6, 0xfff
5927; GFX6-NEXT:    s_mov_b32 s3, 0xf000
5928; GFX6-NEXT:    s_mov_b32 s2, -1
5929; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5930; GFX6-NEXT:    s_and_b32 s4, s4, s6
5931; GFX6-NEXT:    s_and_b32 s5, s5, s6
5932; GFX6-NEXT:    v_mov_b32_e32 v0, s4
5933; GFX6-NEXT:    v_mov_b32_e32 v1, s5
5934; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
5935; GFX6-NEXT:    s_endpgm
5936;
5937; GFX9-LABEL: urem_v2i32_pow2k_denom:
5938; GFX9:       ; %bb.0:
5939; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
5940; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
5941; GFX9-NEXT:    s_movk_i32 s0, 0xfff
5942; GFX9-NEXT:    v_mov_b32_e32 v2, 0
5943; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5944; GFX9-NEXT:    s_and_b32 s1, s2, s0
5945; GFX9-NEXT:    s_and_b32 s0, s3, s0
5946; GFX9-NEXT:    v_mov_b32_e32 v0, s1
5947; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5948; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
5949; GFX9-NEXT:    s_endpgm
5950  %r = urem <2 x i32> %x, <i32 4096, i32 4096>
5951  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
5952  ret void
5953}
5954
5955define amdgpu_kernel void @urem_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) {
5956; CHECK-LABEL: @urem_v2i32_pow2_shl_denom(
5957; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i32> <i32 4096, i32 4096>, [[Y:%.*]]
5958; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
5959; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 0
5960; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float
5961; CHECK-NEXT:    [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])
5962; CHECK-NEXT:    [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41EFFFFFC0000000
5963; CHECK-NEXT:    [[TMP6:%.*]] = fptoui float [[TMP5]] to i32
5964; CHECK-NEXT:    [[TMP7:%.*]] = sub i32 0, [[TMP2]]
5965; CHECK-NEXT:    [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP6]]
5966; CHECK-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP6]] to i64
5967; CHECK-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP8]] to i64
5968; CHECK-NEXT:    [[TMP11:%.*]] = mul i64 [[TMP9]], [[TMP10]]
5969; CHECK-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
5970; CHECK-NEXT:    [[TMP13:%.*]] = lshr i64 [[TMP11]], 32
5971; CHECK-NEXT:    [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32
5972; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP6]], [[TMP14]]
5973; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP1]] to i64
5974; CHECK-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP15]] to i64
5975; CHECK-NEXT:    [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]
5976; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
5977; CHECK-NEXT:    [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
5978; CHECK-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
5979; CHECK-NEXT:    [[TMP22:%.*]] = mul i32 [[TMP21]], [[TMP2]]
5980; CHECK-NEXT:    [[TMP23:%.*]] = sub i32 [[TMP1]], [[TMP22]]
5981; CHECK-NEXT:    [[TMP24:%.*]] = icmp uge i32 [[TMP23]], [[TMP2]]
5982; CHECK-NEXT:    [[TMP25:%.*]] = sub i32 [[TMP23]], [[TMP2]]
5983; CHECK-NEXT:    [[TMP26:%.*]] = select i1 [[TMP24]], i32 [[TMP25]], i32 [[TMP23]]
5984; CHECK-NEXT:    [[TMP27:%.*]] = icmp uge i32 [[TMP26]], [[TMP2]]
5985; CHECK-NEXT:    [[TMP28:%.*]] = sub i32 [[TMP26]], [[TMP2]]
5986; CHECK-NEXT:    [[TMP29:%.*]] = select i1 [[TMP27]], i32 [[TMP28]], i32 [[TMP26]]
5987; CHECK-NEXT:    [[TMP30:%.*]] = insertelement <2 x i32> undef, i32 [[TMP29]], i64 0
5988; CHECK-NEXT:    [[TMP31:%.*]] = extractelement <2 x i32> [[X]], i64 1
5989; CHECK-NEXT:    [[TMP32:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1
5990; CHECK-NEXT:    [[TMP33:%.*]] = uitofp i32 [[TMP32]] to float
5991; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])
5992; CHECK-NEXT:    [[TMP35:%.*]] = fmul fast float [[TMP34]], 0x41EFFFFFC0000000
5993; CHECK-NEXT:    [[TMP36:%.*]] = fptoui float [[TMP35]] to i32
5994; CHECK-NEXT:    [[TMP37:%.*]] = sub i32 0, [[TMP32]]
5995; CHECK-NEXT:    [[TMP38:%.*]] = mul i32 [[TMP37]], [[TMP36]]
5996; CHECK-NEXT:    [[TMP39:%.*]] = zext i32 [[TMP36]] to i64
5997; CHECK-NEXT:    [[TMP40:%.*]] = zext i32 [[TMP38]] to i64
5998; CHECK-NEXT:    [[TMP41:%.*]] = mul i64 [[TMP39]], [[TMP40]]
5999; CHECK-NEXT:    [[TMP42:%.*]] = trunc i64 [[TMP41]] to i32
6000; CHECK-NEXT:    [[TMP43:%.*]] = lshr i64 [[TMP41]], 32
6001; CHECK-NEXT:    [[TMP44:%.*]] = trunc i64 [[TMP43]] to i32
6002; CHECK-NEXT:    [[TMP45:%.*]] = add i32 [[TMP36]], [[TMP44]]
6003; CHECK-NEXT:    [[TMP46:%.*]] = zext i32 [[TMP31]] to i64
6004; CHECK-NEXT:    [[TMP47:%.*]] = zext i32 [[TMP45]] to i64
6005; CHECK-NEXT:    [[TMP48:%.*]] = mul i64 [[TMP46]], [[TMP47]]
6006; CHECK-NEXT:    [[TMP49:%.*]] = trunc i64 [[TMP48]] to i32
6007; CHECK-NEXT:    [[TMP50:%.*]] = lshr i64 [[TMP48]], 32
6008; CHECK-NEXT:    [[TMP51:%.*]] = trunc i64 [[TMP50]] to i32
6009; CHECK-NEXT:    [[TMP52:%.*]] = mul i32 [[TMP51]], [[TMP32]]
6010; CHECK-NEXT:    [[TMP53:%.*]] = sub i32 [[TMP31]], [[TMP52]]
6011; CHECK-NEXT:    [[TMP54:%.*]] = icmp uge i32 [[TMP53]], [[TMP32]]
6012; CHECK-NEXT:    [[TMP55:%.*]] = sub i32 [[TMP53]], [[TMP32]]
6013; CHECK-NEXT:    [[TMP56:%.*]] = select i1 [[TMP54]], i32 [[TMP55]], i32 [[TMP53]]
6014; CHECK-NEXT:    [[TMP57:%.*]] = icmp uge i32 [[TMP56]], [[TMP32]]
6015; CHECK-NEXT:    [[TMP58:%.*]] = sub i32 [[TMP56]], [[TMP32]]
6016; CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP57]], i32 [[TMP58]], i32 [[TMP56]]
6017; CHECK-NEXT:    [[TMP60:%.*]] = insertelement <2 x i32> [[TMP30]], i32 [[TMP59]], i64 1
6018; CHECK-NEXT:    store <2 x i32> [[TMP60]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
6019; CHECK-NEXT:    ret void
6020;
6021; GFX6-LABEL: urem_v2i32_pow2_shl_denom:
6022; GFX6:       ; %bb.0:
6023; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
6024; GFX6-NEXT:    s_movk_i32 s4, 0x1000
6025; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6026; GFX6-NEXT:    s_lshl_b32 s6, s4, s2
6027; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s6
6028; GFX6-NEXT:    s_lshl_b32 s7, s4, s3
6029; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s7
6030; GFX6-NEXT:    s_mov_b32 s2, 0x4f7ffffe
6031; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6032; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
6033; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
6034; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6035; GFX6-NEXT:    v_mul_f32_e32 v0, s2, v0
6036; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
6037; GFX6-NEXT:    v_mul_f32_e32 v1, s2, v1
6038; GFX6-NEXT:    s_sub_i32 s2, 0, s6
6039; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
6040; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
6041; GFX6-NEXT:    s_sub_i32 s2, 0, s7
6042; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6043; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v1
6044; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
6045; GFX6-NEXT:    s_mov_b32 s2, -1
6046; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
6047; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
6048; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6049; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
6050; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
6051; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
6052; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s6
6053; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s7
6054; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
6055; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s6, v0
6056; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
6057; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
6058; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s6, v0
6059; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
6060; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
6061; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
6062; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s7, v1
6063; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
6064; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
6065; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s7, v1
6066; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
6067; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
6068; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
6069; GFX6-NEXT:    s_endpgm
6070;
6071; GFX9-LABEL: urem_v2i32_pow2_shl_denom:
6072; GFX9:       ; %bb.0:
6073; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
6074; GFX9-NEXT:    s_movk_i32 s4, 0x1000
6075; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6076; GFX9-NEXT:    s_lshl_b32 s5, s4, s3
6077; GFX9-NEXT:    s_lshl_b32 s4, s4, s2
6078; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s4
6079; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s5
6080; GFX9-NEXT:    s_mov_b32 s2, 0x4f7ffffe
6081; GFX9-NEXT:    s_sub_i32 s3, 0, s5
6082; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6083; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
6084; GFX9-NEXT:    v_mul_f32_e32 v0, s2, v0
6085; GFX9-NEXT:    v_mul_f32_e32 v1, s2, v1
6086; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
6087; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
6088; GFX9-NEXT:    s_sub_i32 s2, 0, s4
6089; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v0
6090; GFX9-NEXT:    v_mul_lo_u32 v3, s3, v1
6091; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
6092; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
6093; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
6094; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
6095; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
6096; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
6097; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6098; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
6099; GFX9-NEXT:    v_mul_hi_u32 v1, s3, v1
6100; GFX9-NEXT:    v_mov_b32_e32 v2, 0
6101; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s4
6102; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s5
6103; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
6104; GFX9-NEXT:    v_sub_u32_e32 v1, s3, v1
6105; GFX9-NEXT:    v_subrev_u32_e32 v3, s4, v0
6106; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v0
6107; GFX9-NEXT:    v_subrev_u32_e32 v4, s5, v1
6108; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
6109; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v1
6110; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
6111; GFX9-NEXT:    v_subrev_u32_e32 v3, s4, v0
6112; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v0
6113; GFX9-NEXT:    v_subrev_u32_e32 v4, s5, v1
6114; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
6115; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v1
6116; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
6117; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
6118; GFX9-NEXT:    s_endpgm
6119  %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
6120  %r = urem <2 x i32> %x, %shl.y
6121  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
6122  ret void
6123}
6124
6125define amdgpu_kernel void @sdiv_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
6126; CHECK-LABEL: @sdiv_i32_oddk_denom(
6127; CHECK-NEXT:    [[R:%.*]] = sdiv i32 [[X:%.*]], 1235195
6128; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
6129; CHECK-NEXT:    ret void
6130;
6131; GFX6-LABEL: sdiv_i32_oddk_denom:
6132; GFX6:       ; %bb.0:
6133; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
6134; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6135; GFX6-NEXT:    v_mov_b32_e32 v0, 0xd9528441
6136; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6137; GFX6-NEXT:    s_mov_b32 s2, -1
6138; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6139; GFX6-NEXT:    v_mul_hi_i32 v0, s4, v0
6140; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s4, v0
6141; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 31, v0
6142; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 20, v0
6143; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
6144; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
6145; GFX6-NEXT:    s_endpgm
6146;
6147; GFX9-LABEL: sdiv_i32_oddk_denom:
6148; GFX9:       ; %bb.0:
6149; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
6150; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
6151; GFX9-NEXT:    v_mov_b32_e32 v0, 0
6152; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6153; GFX9-NEXT:    s_mul_hi_i32 s0, s4, 0xd9528441
6154; GFX9-NEXT:    s_add_i32 s0, s0, s4
6155; GFX9-NEXT:    s_lshr_b32 s1, s0, 31
6156; GFX9-NEXT:    s_ashr_i32 s0, s0, 20
6157; GFX9-NEXT:    s_add_i32 s0, s0, s1
6158; GFX9-NEXT:    v_mov_b32_e32 v1, s0
6159; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
6160; GFX9-NEXT:    s_endpgm
6161  %r = sdiv i32 %x, 1235195
6162  store i32 %r, i32 addrspace(1)* %out
6163  ret void
6164}
6165
6166define amdgpu_kernel void @sdiv_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x) {
6167; CHECK-LABEL: @sdiv_i32_pow2k_denom(
6168; CHECK-NEXT:    [[R:%.*]] = sdiv i32 [[X:%.*]], 4096
6169; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
6170; CHECK-NEXT:    ret void
6171;
6172; GFX6-LABEL: sdiv_i32_pow2k_denom:
6173; GFX6:       ; %bb.0:
6174; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
6175; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6176; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6177; GFX6-NEXT:    s_mov_b32 s2, -1
6178; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6179; GFX6-NEXT:    s_ashr_i32 s5, s4, 31
6180; GFX6-NEXT:    s_lshr_b32 s5, s5, 20
6181; GFX6-NEXT:    s_add_i32 s4, s4, s5
6182; GFX6-NEXT:    s_ashr_i32 s4, s4, 12
6183; GFX6-NEXT:    v_mov_b32_e32 v0, s4
6184; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
6185; GFX6-NEXT:    s_endpgm
6186;
6187; GFX9-LABEL: sdiv_i32_pow2k_denom:
6188; GFX9:       ; %bb.0:
6189; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
6190; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
6191; GFX9-NEXT:    v_mov_b32_e32 v0, 0
6192; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6193; GFX9-NEXT:    s_ashr_i32 s0, s4, 31
6194; GFX9-NEXT:    s_lshr_b32 s0, s0, 20
6195; GFX9-NEXT:    s_add_i32 s4, s4, s0
6196; GFX9-NEXT:    s_ashr_i32 s0, s4, 12
6197; GFX9-NEXT:    v_mov_b32_e32 v1, s0
6198; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
6199; GFX9-NEXT:    s_endpgm
6200  %r = sdiv i32 %x, 4096
6201  store i32 %r, i32 addrspace(1)* %out
6202  ret void
6203}
6204
6205define amdgpu_kernel void @sdiv_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %x, i32 %y) {
6206; CHECK-LABEL: @sdiv_i32_pow2_shl_denom(
6207; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]]
6208; CHECK-NEXT:    [[R:%.*]] = sdiv i32 [[X:%.*]], [[SHL_Y]]
6209; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
6210; CHECK-NEXT:    ret void
6211;
6212; GFX6-LABEL: sdiv_i32_pow2_shl_denom:
6213; GFX6:       ; %bb.0:
6214; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
6215; GFX6-NEXT:    s_mov_b32 s7, 0xf000
6216; GFX6-NEXT:    s_mov_b32 s6, -1
6217; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6218; GFX6-NEXT:    s_lshl_b32 s3, 0x1000, s3
6219; GFX6-NEXT:    s_ashr_i32 s8, s3, 31
6220; GFX6-NEXT:    s_add_i32 s3, s3, s8
6221; GFX6-NEXT:    s_xor_b32 s3, s3, s8
6222; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s3
6223; GFX6-NEXT:    s_sub_i32 s4, 0, s3
6224; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6225; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
6226; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
6227; GFX6-NEXT:    v_mul_lo_u32 v1, s4, v0
6228; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
6229; GFX6-NEXT:    s_ashr_i32 s0, s2, 31
6230; GFX6-NEXT:    s_add_i32 s1, s2, s0
6231; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
6232; GFX6-NEXT:    s_xor_b32 s1, s1, s0
6233; GFX6-NEXT:    s_xor_b32 s2, s0, s8
6234; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
6235; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
6236; GFX6-NEXT:    v_mul_lo_u32 v1, v0, s3
6237; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
6238; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v1
6239; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v1
6240; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
6241; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v1
6242; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
6243; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[0:1]
6244; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
6245; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
6246; GFX6-NEXT:    v_xor_b32_e32 v0, s2, v0
6247; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
6248; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6249; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
6250; GFX6-NEXT:    s_endpgm
6251;
6252; GFX9-LABEL: sdiv_i32_pow2_shl_denom:
6253; GFX9:       ; %bb.0:
6254; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
6255; GFX9-NEXT:    v_mov_b32_e32 v2, 0
6256; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
6257; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6258; GFX9-NEXT:    s_lshl_b32 s3, 0x1000, s3
6259; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
6260; GFX9-NEXT:    s_add_i32 s3, s3, s4
6261; GFX9-NEXT:    s_xor_b32 s3, s3, s4
6262; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
6263; GFX9-NEXT:    s_sub_i32 s5, 0, s3
6264; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6265; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
6266; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
6267; GFX9-NEXT:    v_mul_lo_u32 v1, s5, v0
6268; GFX9-NEXT:    s_ashr_i32 s5, s2, 31
6269; GFX9-NEXT:    s_add_i32 s2, s2, s5
6270; GFX9-NEXT:    s_xor_b32 s2, s2, s5
6271; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
6272; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
6273; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
6274; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s3
6275; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
6276; GFX9-NEXT:    v_sub_u32_e32 v1, s2, v1
6277; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
6278; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
6279; GFX9-NEXT:    v_subrev_u32_e32 v3, s3, v1
6280; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
6281; GFX9-NEXT:    v_add_u32_e32 v4, 1, v0
6282; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
6283; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
6284; GFX9-NEXT:    s_xor_b32 s2, s5, s4
6285; GFX9-NEXT:    v_xor_b32_e32 v0, s2, v0
6286; GFX9-NEXT:    v_subrev_u32_e32 v0, s2, v0
6287; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]
6288; GFX9-NEXT:    s_endpgm
6289  %shl.y = shl i32 4096, %y
6290  %r = sdiv i32 %x, %shl.y
6291  store i32 %r, i32 addrspace(1)* %out
6292  ret void
6293}
6294
6295define amdgpu_kernel void @sdiv_v2i32_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) {
6296; CHECK-LABEL: @sdiv_v2i32_pow2k_denom(
6297; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
6298; CHECK-NEXT:    [[TMP2:%.*]] = sdiv i32 [[TMP1]], 4096
6299; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0
6300; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1
6301; CHECK-NEXT:    [[TMP5:%.*]] = sdiv i32 [[TMP4]], 4096
6302; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1
6303; CHECK-NEXT:    store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
6304; CHECK-NEXT:    ret void
6305;
6306; GFX6-LABEL: sdiv_v2i32_pow2k_denom:
6307; GFX6:       ; %bb.0:
6308; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
6309; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6310; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6311; GFX6-NEXT:    s_mov_b32 s2, -1
6312; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6313; GFX6-NEXT:    s_ashr_i32 s6, s4, 31
6314; GFX6-NEXT:    s_ashr_i32 s7, s5, 31
6315; GFX6-NEXT:    s_lshr_b32 s6, s6, 20
6316; GFX6-NEXT:    s_add_i32 s4, s4, s6
6317; GFX6-NEXT:    s_lshr_b32 s6, s7, 20
6318; GFX6-NEXT:    s_add_i32 s5, s5, s6
6319; GFX6-NEXT:    s_ashr_i32 s4, s4, 12
6320; GFX6-NEXT:    s_ashr_i32 s5, s5, 12
6321; GFX6-NEXT:    v_mov_b32_e32 v0, s4
6322; GFX6-NEXT:    v_mov_b32_e32 v1, s5
6323; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
6324; GFX6-NEXT:    s_endpgm
6325;
6326; GFX9-LABEL: sdiv_v2i32_pow2k_denom:
6327; GFX9:       ; %bb.0:
6328; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
6329; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
6330; GFX9-NEXT:    v_mov_b32_e32 v2, 0
6331; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6332; GFX9-NEXT:    s_ashr_i32 s0, s2, 31
6333; GFX9-NEXT:    s_ashr_i32 s1, s3, 31
6334; GFX9-NEXT:    s_lshr_b32 s0, s0, 20
6335; GFX9-NEXT:    s_lshr_b32 s1, s1, 20
6336; GFX9-NEXT:    s_add_i32 s0, s2, s0
6337; GFX9-NEXT:    s_add_i32 s1, s3, s1
6338; GFX9-NEXT:    s_ashr_i32 s0, s0, 12
6339; GFX9-NEXT:    s_ashr_i32 s1, s1, 12
6340; GFX9-NEXT:    v_mov_b32_e32 v0, s0
6341; GFX9-NEXT:    v_mov_b32_e32 v1, s1
6342; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
6343; GFX9-NEXT:    s_endpgm
6344  %r = sdiv <2 x i32> %x, <i32 4096, i32 4096>
6345  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
6346  ret void
6347}
6348
6349define amdgpu_kernel void @ssdiv_v2i32_mixed_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) {
6350; CHECK-LABEL: @ssdiv_v2i32_mixed_pow2k_denom(
6351; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
6352; CHECK-NEXT:    [[TMP2:%.*]] = sdiv i32 [[TMP1]], 4096
6353; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0
6354; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1
6355; CHECK-NEXT:    [[TMP5:%.*]] = sdiv i32 [[TMP4]], 4095
6356; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1
6357; CHECK-NEXT:    store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
6358; CHECK-NEXT:    ret void
6359;
6360; GFX6-LABEL: ssdiv_v2i32_mixed_pow2k_denom:
6361; GFX6:       ; %bb.0:
6362; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
6363; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6364; GFX6-NEXT:    v_mov_b32_e32 v0, 0x80080081
6365; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6366; GFX6-NEXT:    s_mov_b32 s2, -1
6367; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6368; GFX6-NEXT:    v_mul_hi_i32 v0, s5, v0
6369; GFX6-NEXT:    s_ashr_i32 s6, s4, 31
6370; GFX6-NEXT:    s_lshr_b32 s6, s6, 20
6371; GFX6-NEXT:    s_add_i32 s4, s4, s6
6372; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s5, v0
6373; GFX6-NEXT:    s_ashr_i32 s4, s4, 12
6374; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 31, v0
6375; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 11, v0
6376; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v0
6377; GFX6-NEXT:    v_mov_b32_e32 v0, s4
6378; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
6379; GFX6-NEXT:    s_endpgm
6380;
6381; GFX9-LABEL: ssdiv_v2i32_mixed_pow2k_denom:
6382; GFX9:       ; %bb.0:
6383; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
6384; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
6385; GFX9-NEXT:    v_mov_b32_e32 v2, 0
6386; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6387; GFX9-NEXT:    s_ashr_i32 s0, s2, 31
6388; GFX9-NEXT:    s_mul_hi_i32 s1, s3, 0x80080081
6389; GFX9-NEXT:    s_lshr_b32 s0, s0, 20
6390; GFX9-NEXT:    s_add_i32 s1, s1, s3
6391; GFX9-NEXT:    s_add_i32 s0, s2, s0
6392; GFX9-NEXT:    s_lshr_b32 s2, s1, 31
6393; GFX9-NEXT:    s_ashr_i32 s1, s1, 11
6394; GFX9-NEXT:    s_ashr_i32 s0, s0, 12
6395; GFX9-NEXT:    s_add_i32 s1, s1, s2
6396; GFX9-NEXT:    v_mov_b32_e32 v0, s0
6397; GFX9-NEXT:    v_mov_b32_e32 v1, s1
6398; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
6399; GFX9-NEXT:    s_endpgm
6400  %r = sdiv <2 x i32> %x, <i32 4096, i32 4095>
6401  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
6402  ret void
6403}
6404
6405define amdgpu_kernel void @sdiv_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) {
6406; CHECK-LABEL: @sdiv_v2i32_pow2_shl_denom(
6407; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i32> <i32 4096, i32 4096>, [[Y:%.*]]
6408; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
6409; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 0
6410; CHECK-NEXT:    [[TMP3:%.*]] = ashr i32 [[TMP1]], 31
6411; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP2]], 31
6412; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
6413; CHECK-NEXT:    [[TMP6:%.*]] = add i32 [[TMP1]], [[TMP3]]
6414; CHECK-NEXT:    [[TMP7:%.*]] = add i32 [[TMP2]], [[TMP4]]
6415; CHECK-NEXT:    [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP3]]
6416; CHECK-NEXT:    [[TMP9:%.*]] = xor i32 [[TMP7]], [[TMP4]]
6417; CHECK-NEXT:    [[TMP10:%.*]] = uitofp i32 [[TMP9]] to float
6418; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP10]])
6419; CHECK-NEXT:    [[TMP12:%.*]] = fmul fast float [[TMP11]], 0x41EFFFFFC0000000
6420; CHECK-NEXT:    [[TMP13:%.*]] = fptoui float [[TMP12]] to i32
6421; CHECK-NEXT:    [[TMP14:%.*]] = sub i32 0, [[TMP9]]
6422; CHECK-NEXT:    [[TMP15:%.*]] = mul i32 [[TMP14]], [[TMP13]]
6423; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP13]] to i64
6424; CHECK-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP15]] to i64
6425; CHECK-NEXT:    [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]
6426; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
6427; CHECK-NEXT:    [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
6428; CHECK-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
6429; CHECK-NEXT:    [[TMP22:%.*]] = add i32 [[TMP13]], [[TMP21]]
6430; CHECK-NEXT:    [[TMP23:%.*]] = zext i32 [[TMP8]] to i64
6431; CHECK-NEXT:    [[TMP24:%.*]] = zext i32 [[TMP22]] to i64
6432; CHECK-NEXT:    [[TMP25:%.*]] = mul i64 [[TMP23]], [[TMP24]]
6433; CHECK-NEXT:    [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32
6434; CHECK-NEXT:    [[TMP27:%.*]] = lshr i64 [[TMP25]], 32
6435; CHECK-NEXT:    [[TMP28:%.*]] = trunc i64 [[TMP27]] to i32
6436; CHECK-NEXT:    [[TMP29:%.*]] = mul i32 [[TMP28]], [[TMP9]]
6437; CHECK-NEXT:    [[TMP30:%.*]] = sub i32 [[TMP8]], [[TMP29]]
6438; CHECK-NEXT:    [[TMP31:%.*]] = icmp uge i32 [[TMP30]], [[TMP9]]
6439; CHECK-NEXT:    [[TMP32:%.*]] = add i32 [[TMP28]], 1
6440; CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP31]], i32 [[TMP32]], i32 [[TMP28]]
6441; CHECK-NEXT:    [[TMP34:%.*]] = sub i32 [[TMP30]], [[TMP9]]
6442; CHECK-NEXT:    [[TMP35:%.*]] = select i1 [[TMP31]], i32 [[TMP34]], i32 [[TMP30]]
6443; CHECK-NEXT:    [[TMP36:%.*]] = icmp uge i32 [[TMP35]], [[TMP9]]
6444; CHECK-NEXT:    [[TMP37:%.*]] = add i32 [[TMP33]], 1
6445; CHECK-NEXT:    [[TMP38:%.*]] = select i1 [[TMP36]], i32 [[TMP37]], i32 [[TMP33]]
6446; CHECK-NEXT:    [[TMP39:%.*]] = xor i32 [[TMP38]], [[TMP5]]
6447; CHECK-NEXT:    [[TMP40:%.*]] = sub i32 [[TMP39]], [[TMP5]]
6448; CHECK-NEXT:    [[TMP41:%.*]] = insertelement <2 x i32> undef, i32 [[TMP40]], i64 0
6449; CHECK-NEXT:    [[TMP42:%.*]] = extractelement <2 x i32> [[X]], i64 1
6450; CHECK-NEXT:    [[TMP43:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1
6451; CHECK-NEXT:    [[TMP44:%.*]] = ashr i32 [[TMP42]], 31
6452; CHECK-NEXT:    [[TMP45:%.*]] = ashr i32 [[TMP43]], 31
6453; CHECK-NEXT:    [[TMP46:%.*]] = xor i32 [[TMP44]], [[TMP45]]
6454; CHECK-NEXT:    [[TMP47:%.*]] = add i32 [[TMP42]], [[TMP44]]
6455; CHECK-NEXT:    [[TMP48:%.*]] = add i32 [[TMP43]], [[TMP45]]
6456; CHECK-NEXT:    [[TMP49:%.*]] = xor i32 [[TMP47]], [[TMP44]]
6457; CHECK-NEXT:    [[TMP50:%.*]] = xor i32 [[TMP48]], [[TMP45]]
6458; CHECK-NEXT:    [[TMP51:%.*]] = uitofp i32 [[TMP50]] to float
6459; CHECK-NEXT:    [[TMP52:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP51]])
6460; CHECK-NEXT:    [[TMP53:%.*]] = fmul fast float [[TMP52]], 0x41EFFFFFC0000000
6461; CHECK-NEXT:    [[TMP54:%.*]] = fptoui float [[TMP53]] to i32
6462; CHECK-NEXT:    [[TMP55:%.*]] = sub i32 0, [[TMP50]]
6463; CHECK-NEXT:    [[TMP56:%.*]] = mul i32 [[TMP55]], [[TMP54]]
6464; CHECK-NEXT:    [[TMP57:%.*]] = zext i32 [[TMP54]] to i64
6465; CHECK-NEXT:    [[TMP58:%.*]] = zext i32 [[TMP56]] to i64
6466; CHECK-NEXT:    [[TMP59:%.*]] = mul i64 [[TMP57]], [[TMP58]]
6467; CHECK-NEXT:    [[TMP60:%.*]] = trunc i64 [[TMP59]] to i32
6468; CHECK-NEXT:    [[TMP61:%.*]] = lshr i64 [[TMP59]], 32
6469; CHECK-NEXT:    [[TMP62:%.*]] = trunc i64 [[TMP61]] to i32
6470; CHECK-NEXT:    [[TMP63:%.*]] = add i32 [[TMP54]], [[TMP62]]
6471; CHECK-NEXT:    [[TMP64:%.*]] = zext i32 [[TMP49]] to i64
6472; CHECK-NEXT:    [[TMP65:%.*]] = zext i32 [[TMP63]] to i64
6473; CHECK-NEXT:    [[TMP66:%.*]] = mul i64 [[TMP64]], [[TMP65]]
6474; CHECK-NEXT:    [[TMP67:%.*]] = trunc i64 [[TMP66]] to i32
6475; CHECK-NEXT:    [[TMP68:%.*]] = lshr i64 [[TMP66]], 32
6476; CHECK-NEXT:    [[TMP69:%.*]] = trunc i64 [[TMP68]] to i32
6477; CHECK-NEXT:    [[TMP70:%.*]] = mul i32 [[TMP69]], [[TMP50]]
6478; CHECK-NEXT:    [[TMP71:%.*]] = sub i32 [[TMP49]], [[TMP70]]
6479; CHECK-NEXT:    [[TMP72:%.*]] = icmp uge i32 [[TMP71]], [[TMP50]]
6480; CHECK-NEXT:    [[TMP73:%.*]] = add i32 [[TMP69]], 1
6481; CHECK-NEXT:    [[TMP74:%.*]] = select i1 [[TMP72]], i32 [[TMP73]], i32 [[TMP69]]
6482; CHECK-NEXT:    [[TMP75:%.*]] = sub i32 [[TMP71]], [[TMP50]]
6483; CHECK-NEXT:    [[TMP76:%.*]] = select i1 [[TMP72]], i32 [[TMP75]], i32 [[TMP71]]
6484; CHECK-NEXT:    [[TMP77:%.*]] = icmp uge i32 [[TMP76]], [[TMP50]]
6485; CHECK-NEXT:    [[TMP78:%.*]] = add i32 [[TMP74]], 1
6486; CHECK-NEXT:    [[TMP79:%.*]] = select i1 [[TMP77]], i32 [[TMP78]], i32 [[TMP74]]
6487; CHECK-NEXT:    [[TMP80:%.*]] = xor i32 [[TMP79]], [[TMP46]]
6488; CHECK-NEXT:    [[TMP81:%.*]] = sub i32 [[TMP80]], [[TMP46]]
6489; CHECK-NEXT:    [[TMP82:%.*]] = insertelement <2 x i32> [[TMP41]], i32 [[TMP81]], i64 1
6490; CHECK-NEXT:    store <2 x i32> [[TMP82]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
6491; CHECK-NEXT:    ret void
6492;
6493; GFX6-LABEL: sdiv_v2i32_pow2_shl_denom:
6494; GFX6:       ; %bb.0:
6495; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
6496; GFX6-NEXT:    s_movk_i32 s10, 0x1000
6497; GFX6-NEXT:    s_mov_b32 s12, 0x4f7ffffe
6498; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
6499; GFX6-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xb
6500; GFX6-NEXT:    s_mov_b32 s7, 0xf000
6501; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6502; GFX6-NEXT:    s_lshl_b32 s2, s10, s2
6503; GFX6-NEXT:    s_ashr_i32 s11, s2, 31
6504; GFX6-NEXT:    s_add_i32 s2, s2, s11
6505; GFX6-NEXT:    s_xor_b32 s2, s2, s11
6506; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s2
6507; GFX6-NEXT:    s_lshl_b32 s0, s10, s3
6508; GFX6-NEXT:    s_sub_i32 s10, 0, s2
6509; GFX6-NEXT:    s_ashr_i32 s3, s0, 31
6510; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6511; GFX6-NEXT:    s_add_i32 s0, s0, s3
6512; GFX6-NEXT:    s_ashr_i32 s1, s8, 31
6513; GFX6-NEXT:    s_mov_b32 s6, -1
6514; GFX6-NEXT:    v_mul_f32_e32 v0, s12, v0
6515; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
6516; GFX6-NEXT:    v_mul_lo_u32 v1, s10, v0
6517; GFX6-NEXT:    s_xor_b32 s10, s0, s3
6518; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s10
6519; GFX6-NEXT:    s_add_i32 s0, s8, s1
6520; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
6521; GFX6-NEXT:    s_xor_b32 s0, s0, s1
6522; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
6523; GFX6-NEXT:    s_xor_b32 s8, s1, s11
6524; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
6525; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
6526; GFX6-NEXT:    v_mul_f32_e32 v1, s12, v2
6527; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
6528; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s2
6529; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
6530; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s0, v2
6531; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v2
6532; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[0:1]
6533; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s2, v2
6534; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
6535; GFX6-NEXT:    s_sub_i32 s0, 0, s10
6536; GFX6-NEXT:    v_mul_lo_u32 v3, s0, v1
6537; GFX6-NEXT:    s_ashr_i32 s0, s9, 31
6538; GFX6-NEXT:    s_add_i32 s1, s9, s0
6539; GFX6-NEXT:    s_xor_b32 s1, s1, s0
6540; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
6541; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
6542; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
6543; GFX6-NEXT:    v_mul_hi_u32 v1, s1, v1
6544; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s2, v2
6545; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
6546; GFX6-NEXT:    s_xor_b32 s2, s0, s3
6547; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s10
6548; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
6549; GFX6-NEXT:    v_xor_b32_e32 v0, s8, v0
6550; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
6551; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v2
6552; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
6553; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s10, v2
6554; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v0
6555; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
6556; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
6557; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
6558; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
6559; GFX6-NEXT:    v_xor_b32_e32 v1, s2, v1
6560; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s2, v1
6561; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
6562; GFX6-NEXT:    s_endpgm
6563;
6564; GFX9-LABEL: sdiv_v2i32_pow2_shl_denom:
6565; GFX9:       ; %bb.0:
6566; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
6567; GFX9-NEXT:    s_movk_i32 s8, 0x1000
6568; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
6569; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x2c
6570; GFX9-NEXT:    s_mov_b32 s10, 0x4f7ffffe
6571; GFX9-NEXT:    v_mov_b32_e32 v2, 0
6572; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6573; GFX9-NEXT:    s_lshl_b32 s2, s8, s2
6574; GFX9-NEXT:    s_ashr_i32 s9, s2, 31
6575; GFX9-NEXT:    s_add_i32 s2, s2, s9
6576; GFX9-NEXT:    s_xor_b32 s2, s2, s9
6577; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s2
6578; GFX9-NEXT:    s_lshl_b32 s0, s8, s3
6579; GFX9-NEXT:    s_ashr_i32 s1, s0, 31
6580; GFX9-NEXT:    s_add_i32 s0, s0, s1
6581; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6582; GFX9-NEXT:    s_xor_b32 s0, s0, s1
6583; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s0
6584; GFX9-NEXT:    s_sub_i32 s3, 0, s2
6585; GFX9-NEXT:    v_mul_f32_e32 v0, s10, v0
6586; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
6587; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
6588; GFX9-NEXT:    s_sub_i32 s8, 0, s0
6589; GFX9-NEXT:    v_mul_lo_u32 v3, s3, v0
6590; GFX9-NEXT:    v_mul_f32_e32 v1, s10, v1
6591; GFX9-NEXT:    s_ashr_i32 s3, s6, 31
6592; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
6593; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v3
6594; GFX9-NEXT:    s_add_i32 s6, s6, s3
6595; GFX9-NEXT:    s_xor_b32 s6, s6, s3
6596; GFX9-NEXT:    s_xor_b32 s3, s3, s9
6597; GFX9-NEXT:    v_add_u32_e32 v0, v0, v3
6598; GFX9-NEXT:    v_mul_hi_u32 v0, s6, v0
6599; GFX9-NEXT:    v_mul_lo_u32 v3, s8, v1
6600; GFX9-NEXT:    s_ashr_i32 s8, s7, 31
6601; GFX9-NEXT:    s_xor_b32 s1, s8, s1
6602; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s2
6603; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
6604; GFX9-NEXT:    v_add_u32_e32 v5, 1, v0
6605; GFX9-NEXT:    v_sub_u32_e32 v4, s6, v4
6606; GFX9-NEXT:    s_add_i32 s6, s7, s8
6607; GFX9-NEXT:    s_xor_b32 s6, s6, s8
6608; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
6609; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v4
6610; GFX9-NEXT:    v_mul_hi_u32 v1, s6, v1
6611; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
6612; GFX9-NEXT:    v_subrev_u32_e32 v5, s2, v4
6613; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
6614; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
6615; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v4
6616; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
6617; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s0
6618; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
6619; GFX9-NEXT:    v_xor_b32_e32 v0, s3, v0
6620; GFX9-NEXT:    v_subrev_u32_e32 v0, s3, v0
6621; GFX9-NEXT:    v_sub_u32_e32 v3, s6, v3
6622; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s0, v3
6623; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
6624; GFX9-NEXT:    v_subrev_u32_e32 v4, s0, v3
6625; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
6626; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
6627; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s0, v3
6628; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
6629; GFX9-NEXT:    v_xor_b32_e32 v1, s1, v1
6630; GFX9-NEXT:    v_subrev_u32_e32 v1, s1, v1
6631; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
6632; GFX9-NEXT:    s_endpgm
6633  %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
6634  %r = sdiv <2 x i32> %x, %shl.y
6635  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
6636  ret void
6637}
6638
6639define amdgpu_kernel void @srem_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
6640; CHECK-LABEL: @srem_i32_oddk_denom(
6641; CHECK-NEXT:    [[R:%.*]] = srem i32 [[X:%.*]], 1235195
6642; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
6643; CHECK-NEXT:    ret void
6644;
6645; GFX6-LABEL: srem_i32_oddk_denom:
6646; GFX6:       ; %bb.0:
6647; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
6648; GFX6-NEXT:    v_mov_b32_e32 v0, 0xd9528441
6649; GFX6-NEXT:    s_mov_b32 s2, 0x12d8fb
6650; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6651; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6652; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6653; GFX6-NEXT:    v_mul_hi_i32 v0, s4, v0
6654; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s4, v0
6655; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 31, v0
6656; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 20, v0
6657; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
6658; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
6659; GFX6-NEXT:    s_mov_b32 s2, -1
6660; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
6661; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
6662; GFX6-NEXT:    s_endpgm
6663;
6664; GFX9-LABEL: srem_i32_oddk_denom:
6665; GFX9:       ; %bb.0:
6666; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
6667; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
6668; GFX9-NEXT:    v_mov_b32_e32 v0, 0
6669; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6670; GFX9-NEXT:    s_mul_hi_i32 s0, s4, 0xd9528441
6671; GFX9-NEXT:    s_add_i32 s0, s0, s4
6672; GFX9-NEXT:    s_lshr_b32 s1, s0, 31
6673; GFX9-NEXT:    s_ashr_i32 s0, s0, 20
6674; GFX9-NEXT:    s_add_i32 s0, s0, s1
6675; GFX9-NEXT:    s_mul_i32 s0, s0, 0x12d8fb
6676; GFX9-NEXT:    s_sub_i32 s0, s4, s0
6677; GFX9-NEXT:    v_mov_b32_e32 v1, s0
6678; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
6679; GFX9-NEXT:    s_endpgm
6680  %r = srem i32 %x, 1235195
6681  store i32 %r, i32 addrspace(1)* %out
6682  ret void
6683}
6684
6685define amdgpu_kernel void @srem_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x) {
6686; CHECK-LABEL: @srem_i32_pow2k_denom(
6687; CHECK-NEXT:    [[R:%.*]] = srem i32 [[X:%.*]], 4096
6688; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
6689; CHECK-NEXT:    ret void
6690;
6691; GFX6-LABEL: srem_i32_pow2k_denom:
6692; GFX6:       ; %bb.0:
6693; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
6694; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6695; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6696; GFX6-NEXT:    s_mov_b32 s2, -1
6697; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6698; GFX6-NEXT:    s_ashr_i32 s5, s4, 31
6699; GFX6-NEXT:    s_lshr_b32 s5, s5, 20
6700; GFX6-NEXT:    s_add_i32 s5, s4, s5
6701; GFX6-NEXT:    s_and_b32 s5, s5, 0xfffff000
6702; GFX6-NEXT:    s_sub_i32 s4, s4, s5
6703; GFX6-NEXT:    v_mov_b32_e32 v0, s4
6704; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
6705; GFX6-NEXT:    s_endpgm
6706;
6707; GFX9-LABEL: srem_i32_pow2k_denom:
6708; GFX9:       ; %bb.0:
6709; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
6710; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
6711; GFX9-NEXT:    v_mov_b32_e32 v0, 0
6712; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6713; GFX9-NEXT:    s_ashr_i32 s0, s4, 31
6714; GFX9-NEXT:    s_lshr_b32 s0, s0, 20
6715; GFX9-NEXT:    s_add_i32 s0, s4, s0
6716; GFX9-NEXT:    s_and_b32 s0, s0, 0xfffff000
6717; GFX9-NEXT:    s_sub_i32 s0, s4, s0
6718; GFX9-NEXT:    v_mov_b32_e32 v1, s0
6719; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
6720; GFX9-NEXT:    s_endpgm
6721  %r = srem i32 %x, 4096
6722  store i32 %r, i32 addrspace(1)* %out
6723  ret void
6724}
6725
6726define amdgpu_kernel void @srem_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %x, i32 %y) {
6727; CHECK-LABEL: @srem_i32_pow2_shl_denom(
6728; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]]
6729; CHECK-NEXT:    [[R:%.*]] = srem i32 [[X:%.*]], [[SHL_Y]]
6730; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
6731; CHECK-NEXT:    ret void
6732;
6733; GFX6-LABEL: srem_i32_pow2_shl_denom:
6734; GFX6:       ; %bb.0:
6735; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
6736; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6737; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6738; GFX6-NEXT:    s_lshl_b32 s3, 0x1000, s3
6739; GFX6-NEXT:    s_ashr_i32 s4, s3, 31
6740; GFX6-NEXT:    s_add_i32 s3, s3, s4
6741; GFX6-NEXT:    s_xor_b32 s4, s3, s4
6742; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s4
6743; GFX6-NEXT:    s_sub_i32 s3, 0, s4
6744; GFX6-NEXT:    s_ashr_i32 s5, s2, 31
6745; GFX6-NEXT:    s_add_i32 s2, s2, s5
6746; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6747; GFX6-NEXT:    s_xor_b32 s6, s2, s5
6748; GFX6-NEXT:    s_mov_b32 s2, -1
6749; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
6750; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
6751; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v0
6752; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6753; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
6754; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
6755; GFX6-NEXT:    v_mul_hi_u32 v0, s6, v0
6756; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s4
6757; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
6758; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s4, v0
6759; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s4, v0
6760; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
6761; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s4, v0
6762; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s4, v0
6763; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
6764; GFX6-NEXT:    v_xor_b32_e32 v0, s5, v0
6765; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s5, v0
6766; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
6767; GFX6-NEXT:    s_endpgm
6768;
6769; GFX9-LABEL: srem_i32_pow2_shl_denom:
6770; GFX9:       ; %bb.0:
6771; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
6772; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6773; GFX9-NEXT:    s_lshl_b32 s3, 0x1000, s3
6774; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
6775; GFX9-NEXT:    s_add_i32 s3, s3, s4
6776; GFX9-NEXT:    s_xor_b32 s3, s3, s4
6777; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
6778; GFX9-NEXT:    s_sub_i32 s4, 0, s3
6779; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
6780; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6781; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
6782; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
6783; GFX9-NEXT:    v_mul_lo_u32 v1, s4, v0
6784; GFX9-NEXT:    s_ashr_i32 s4, s2, 31
6785; GFX9-NEXT:    s_add_i32 s2, s2, s4
6786; GFX9-NEXT:    s_xor_b32 s2, s2, s4
6787; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
6788; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
6789; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
6790; GFX9-NEXT:    v_mov_b32_e32 v1, 0
6791; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
6792; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
6793; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v0
6794; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v0
6795; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
6796; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v0
6797; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v0
6798; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
6799; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v0
6800; GFX9-NEXT:    v_subrev_u32_e32 v0, s4, v0
6801; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6802; GFX9-NEXT:    global_store_dword v1, v0, s[0:1]
6803; GFX9-NEXT:    s_endpgm
6804  %shl.y = shl i32 4096, %y
6805  %r = srem i32 %x, %shl.y
6806  store i32 %r, i32 addrspace(1)* %out
6807  ret void
6808}
6809
6810define amdgpu_kernel void @srem_v2i32_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) {
6811; CHECK-LABEL: @srem_v2i32_pow2k_denom(
6812; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
6813; CHECK-NEXT:    [[TMP2:%.*]] = srem i32 [[TMP1]], 4096
6814; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0
6815; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1
6816; CHECK-NEXT:    [[TMP5:%.*]] = srem i32 [[TMP4]], 4096
6817; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1
6818; CHECK-NEXT:    store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
6819; CHECK-NEXT:    ret void
6820;
6821; GFX6-LABEL: srem_v2i32_pow2k_denom:
6822; GFX6:       ; %bb.0:
6823; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
6824; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6825; GFX6-NEXT:    s_movk_i32 s6, 0xf000
6826; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6827; GFX6-NEXT:    s_mov_b32 s2, -1
6828; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6829; GFX6-NEXT:    s_ashr_i32 s7, s4, 31
6830; GFX6-NEXT:    s_lshr_b32 s7, s7, 20
6831; GFX6-NEXT:    s_add_i32 s7, s4, s7
6832; GFX6-NEXT:    s_and_b32 s7, s7, s6
6833; GFX6-NEXT:    s_sub_i32 s4, s4, s7
6834; GFX6-NEXT:    s_ashr_i32 s7, s5, 31
6835; GFX6-NEXT:    s_lshr_b32 s7, s7, 20
6836; GFX6-NEXT:    s_add_i32 s7, s5, s7
6837; GFX6-NEXT:    s_and_b32 s6, s7, s6
6838; GFX6-NEXT:    s_sub_i32 s5, s5, s6
6839; GFX6-NEXT:    v_mov_b32_e32 v0, s4
6840; GFX6-NEXT:    v_mov_b32_e32 v1, s5
6841; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
6842; GFX6-NEXT:    s_endpgm
6843;
6844; GFX9-LABEL: srem_v2i32_pow2k_denom:
6845; GFX9:       ; %bb.0:
6846; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
6847; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
6848; GFX9-NEXT:    s_movk_i32 s0, 0xf000
6849; GFX9-NEXT:    v_mov_b32_e32 v2, 0
6850; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6851; GFX9-NEXT:    s_ashr_i32 s1, s2, 31
6852; GFX9-NEXT:    s_lshr_b32 s1, s1, 20
6853; GFX9-NEXT:    s_add_i32 s1, s2, s1
6854; GFX9-NEXT:    s_ashr_i32 s6, s3, 31
6855; GFX9-NEXT:    s_and_b32 s1, s1, s0
6856; GFX9-NEXT:    s_sub_i32 s1, s2, s1
6857; GFX9-NEXT:    s_lshr_b32 s2, s6, 20
6858; GFX9-NEXT:    s_add_i32 s2, s3, s2
6859; GFX9-NEXT:    s_and_b32 s0, s2, s0
6860; GFX9-NEXT:    s_sub_i32 s0, s3, s0
6861; GFX9-NEXT:    v_mov_b32_e32 v0, s1
6862; GFX9-NEXT:    v_mov_b32_e32 v1, s0
6863; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
6864; GFX9-NEXT:    s_endpgm
6865  %r = srem <2 x i32> %x, <i32 4096, i32 4096>
6866  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
6867  ret void
6868}
6869
6870define amdgpu_kernel void @srem_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) {
6871; CHECK-LABEL: @srem_v2i32_pow2_shl_denom(
6872; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i32> <i32 4096, i32 4096>, [[Y:%.*]]
6873; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
6874; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 0
6875; CHECK-NEXT:    [[TMP3:%.*]] = ashr i32 [[TMP1]], 31
6876; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP2]], 31
6877; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[TMP1]], [[TMP3]]
6878; CHECK-NEXT:    [[TMP6:%.*]] = add i32 [[TMP2]], [[TMP4]]
6879; CHECK-NEXT:    [[TMP7:%.*]] = xor i32 [[TMP5]], [[TMP3]]
6880; CHECK-NEXT:    [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP4]]
6881; CHECK-NEXT:    [[TMP9:%.*]] = uitofp i32 [[TMP8]] to float
6882; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
6883; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP10]], 0x41EFFFFFC0000000
6884; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP11]] to i32
6885; CHECK-NEXT:    [[TMP13:%.*]] = sub i32 0, [[TMP8]]
6886; CHECK-NEXT:    [[TMP14:%.*]] = mul i32 [[TMP13]], [[TMP12]]
6887; CHECK-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP12]] to i64
6888; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP14]] to i64
6889; CHECK-NEXT:    [[TMP17:%.*]] = mul i64 [[TMP15]], [[TMP16]]
6890; CHECK-NEXT:    [[TMP18:%.*]] = trunc i64 [[TMP17]] to i32
6891; CHECK-NEXT:    [[TMP19:%.*]] = lshr i64 [[TMP17]], 32
6892; CHECK-NEXT:    [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32
6893; CHECK-NEXT:    [[TMP21:%.*]] = add i32 [[TMP12]], [[TMP20]]
6894; CHECK-NEXT:    [[TMP22:%.*]] = zext i32 [[TMP7]] to i64
6895; CHECK-NEXT:    [[TMP23:%.*]] = zext i32 [[TMP21]] to i64
6896; CHECK-NEXT:    [[TMP24:%.*]] = mul i64 [[TMP22]], [[TMP23]]
6897; CHECK-NEXT:    [[TMP25:%.*]] = trunc i64 [[TMP24]] to i32
6898; CHECK-NEXT:    [[TMP26:%.*]] = lshr i64 [[TMP24]], 32
6899; CHECK-NEXT:    [[TMP27:%.*]] = trunc i64 [[TMP26]] to i32
6900; CHECK-NEXT:    [[TMP28:%.*]] = mul i32 [[TMP27]], [[TMP8]]
6901; CHECK-NEXT:    [[TMP29:%.*]] = sub i32 [[TMP7]], [[TMP28]]
6902; CHECK-NEXT:    [[TMP30:%.*]] = icmp uge i32 [[TMP29]], [[TMP8]]
6903; CHECK-NEXT:    [[TMP31:%.*]] = sub i32 [[TMP29]], [[TMP8]]
6904; CHECK-NEXT:    [[TMP32:%.*]] = select i1 [[TMP30]], i32 [[TMP31]], i32 [[TMP29]]
6905; CHECK-NEXT:    [[TMP33:%.*]] = icmp uge i32 [[TMP32]], [[TMP8]]
6906; CHECK-NEXT:    [[TMP34:%.*]] = sub i32 [[TMP32]], [[TMP8]]
6907; CHECK-NEXT:    [[TMP35:%.*]] = select i1 [[TMP33]], i32 [[TMP34]], i32 [[TMP32]]
6908; CHECK-NEXT:    [[TMP36:%.*]] = xor i32 [[TMP35]], [[TMP3]]
6909; CHECK-NEXT:    [[TMP37:%.*]] = sub i32 [[TMP36]], [[TMP3]]
6910; CHECK-NEXT:    [[TMP38:%.*]] = insertelement <2 x i32> undef, i32 [[TMP37]], i64 0
6911; CHECK-NEXT:    [[TMP39:%.*]] = extractelement <2 x i32> [[X]], i64 1
6912; CHECK-NEXT:    [[TMP40:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1
6913; CHECK-NEXT:    [[TMP41:%.*]] = ashr i32 [[TMP39]], 31
6914; CHECK-NEXT:    [[TMP42:%.*]] = ashr i32 [[TMP40]], 31
6915; CHECK-NEXT:    [[TMP43:%.*]] = add i32 [[TMP39]], [[TMP41]]
6916; CHECK-NEXT:    [[TMP44:%.*]] = add i32 [[TMP40]], [[TMP42]]
6917; CHECK-NEXT:    [[TMP45:%.*]] = xor i32 [[TMP43]], [[TMP41]]
6918; CHECK-NEXT:    [[TMP46:%.*]] = xor i32 [[TMP44]], [[TMP42]]
6919; CHECK-NEXT:    [[TMP47:%.*]] = uitofp i32 [[TMP46]] to float
6920; CHECK-NEXT:    [[TMP48:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP47]])
6921; CHECK-NEXT:    [[TMP49:%.*]] = fmul fast float [[TMP48]], 0x41EFFFFFC0000000
6922; CHECK-NEXT:    [[TMP50:%.*]] = fptoui float [[TMP49]] to i32
6923; CHECK-NEXT:    [[TMP51:%.*]] = sub i32 0, [[TMP46]]
6924; CHECK-NEXT:    [[TMP52:%.*]] = mul i32 [[TMP51]], [[TMP50]]
6925; CHECK-NEXT:    [[TMP53:%.*]] = zext i32 [[TMP50]] to i64
6926; CHECK-NEXT:    [[TMP54:%.*]] = zext i32 [[TMP52]] to i64
6927; CHECK-NEXT:    [[TMP55:%.*]] = mul i64 [[TMP53]], [[TMP54]]
6928; CHECK-NEXT:    [[TMP56:%.*]] = trunc i64 [[TMP55]] to i32
6929; CHECK-NEXT:    [[TMP57:%.*]] = lshr i64 [[TMP55]], 32
6930; CHECK-NEXT:    [[TMP58:%.*]] = trunc i64 [[TMP57]] to i32
6931; CHECK-NEXT:    [[TMP59:%.*]] = add i32 [[TMP50]], [[TMP58]]
6932; CHECK-NEXT:    [[TMP60:%.*]] = zext i32 [[TMP45]] to i64
6933; CHECK-NEXT:    [[TMP61:%.*]] = zext i32 [[TMP59]] to i64
6934; CHECK-NEXT:    [[TMP62:%.*]] = mul i64 [[TMP60]], [[TMP61]]
6935; CHECK-NEXT:    [[TMP63:%.*]] = trunc i64 [[TMP62]] to i32
6936; CHECK-NEXT:    [[TMP64:%.*]] = lshr i64 [[TMP62]], 32
6937; CHECK-NEXT:    [[TMP65:%.*]] = trunc i64 [[TMP64]] to i32
6938; CHECK-NEXT:    [[TMP66:%.*]] = mul i32 [[TMP65]], [[TMP46]]
6939; CHECK-NEXT:    [[TMP67:%.*]] = sub i32 [[TMP45]], [[TMP66]]
6940; CHECK-NEXT:    [[TMP68:%.*]] = icmp uge i32 [[TMP67]], [[TMP46]]
6941; CHECK-NEXT:    [[TMP69:%.*]] = sub i32 [[TMP67]], [[TMP46]]
6942; CHECK-NEXT:    [[TMP70:%.*]] = select i1 [[TMP68]], i32 [[TMP69]], i32 [[TMP67]]
6943; CHECK-NEXT:    [[TMP71:%.*]] = icmp uge i32 [[TMP70]], [[TMP46]]
6944; CHECK-NEXT:    [[TMP72:%.*]] = sub i32 [[TMP70]], [[TMP46]]
6945; CHECK-NEXT:    [[TMP73:%.*]] = select i1 [[TMP71]], i32 [[TMP72]], i32 [[TMP70]]
6946; CHECK-NEXT:    [[TMP74:%.*]] = xor i32 [[TMP73]], [[TMP41]]
6947; CHECK-NEXT:    [[TMP75:%.*]] = sub i32 [[TMP74]], [[TMP41]]
6948; CHECK-NEXT:    [[TMP76:%.*]] = insertelement <2 x i32> [[TMP38]], i32 [[TMP75]], i64 1
6949; CHECK-NEXT:    store <2 x i32> [[TMP76]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
6950; CHECK-NEXT:    ret void
6951;
6952; GFX6-LABEL: srem_v2i32_pow2_shl_denom:
6953; GFX6:       ; %bb.0:
6954; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
6955; GFX6-NEXT:    s_movk_i32 s6, 0x1000
6956; GFX6-NEXT:    s_mov_b32 s10, 0x4f7ffffe
6957; GFX6-NEXT:    s_mov_b32 s7, 0xf000
6958; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6959; GFX6-NEXT:    s_lshl_b32 s2, s6, s2
6960; GFX6-NEXT:    s_ashr_i32 s4, s2, 31
6961; GFX6-NEXT:    s_add_i32 s2, s2, s4
6962; GFX6-NEXT:    s_xor_b32 s2, s2, s4
6963; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s2
6964; GFX6-NEXT:    s_lshl_b32 s3, s6, s3
6965; GFX6-NEXT:    s_ashr_i32 s6, s3, 31
6966; GFX6-NEXT:    s_add_i32 s3, s3, s6
6967; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6968; GFX6-NEXT:    s_sub_i32 s9, 0, s2
6969; GFX6-NEXT:    s_xor_b32 s3, s3, s6
6970; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s3
6971; GFX6-NEXT:    v_mul_f32_e32 v0, s10, v0
6972; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
6973; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
6974; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
6975; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
6976; GFX6-NEXT:    s_mov_b32 s6, -1
6977; GFX6-NEXT:    v_mul_lo_u32 v1, s9, v0
6978; GFX6-NEXT:    s_sub_i32 s9, 0, s3
6979; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6980; GFX6-NEXT:    s_ashr_i32 s8, s0, 31
6981; GFX6-NEXT:    s_add_i32 s0, s0, s8
6982; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
6983; GFX6-NEXT:    s_xor_b32 s0, s0, s8
6984; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
6985; GFX6-NEXT:    v_mul_f32_e32 v1, s10, v2
6986; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
6987; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
6988; GFX6-NEXT:    v_mul_lo_u32 v2, s9, v1
6989; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
6990; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v2
6991; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
6992; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s2, v0
6993; GFX6-NEXT:    s_ashr_i32 s0, s1, 31
6994; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s2, v0
6995; GFX6-NEXT:    s_add_i32 s1, s1, s0
6996; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
6997; GFX6-NEXT:    s_xor_b32 s1, s1, s0
6998; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
6999; GFX6-NEXT:    v_mul_hi_u32 v1, s1, v1
7000; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s2, v0
7001; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s2, v0
7002; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s3
7003; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
7004; GFX6-NEXT:    v_xor_b32_e32 v0, s8, v0
7005; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v0
7006; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v1
7007; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v1
7008; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
7009; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
7010; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v1
7011; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
7012; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
7013; GFX6-NEXT:    v_xor_b32_e32 v1, s0, v1
7014; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s0, v1
7015; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
7016; GFX6-NEXT:    s_endpgm
7017;
7018; GFX9-LABEL: srem_v2i32_pow2_shl_denom:
7019; GFX9:       ; %bb.0:
7020; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
7021; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
7022; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x2c
7023; GFX9-NEXT:    s_movk_i32 s0, 0x1000
7024; GFX9-NEXT:    s_mov_b32 s8, 0x4f7ffffe
7025; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7026; GFX9-NEXT:    s_lshl_b32 s1, s0, s2
7027; GFX9-NEXT:    s_ashr_i32 s2, s1, 31
7028; GFX9-NEXT:    s_add_i32 s1, s1, s2
7029; GFX9-NEXT:    s_xor_b32 s1, s1, s2
7030; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s1
7031; GFX9-NEXT:    s_lshl_b32 s0, s0, s3
7032; GFX9-NEXT:    s_ashr_i32 s2, s0, 31
7033; GFX9-NEXT:    s_add_i32 s0, s0, s2
7034; GFX9-NEXT:    s_xor_b32 s0, s0, s2
7035; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
7036; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s0
7037; GFX9-NEXT:    s_sub_i32 s3, 0, s1
7038; GFX9-NEXT:    s_ashr_i32 s2, s6, 31
7039; GFX9-NEXT:    v_mul_f32_e32 v0, s8, v0
7040; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
7041; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
7042; GFX9-NEXT:    v_mov_b32_e32 v2, 0
7043; GFX9-NEXT:    v_mul_f32_e32 v1, s8, v1
7044; GFX9-NEXT:    v_mul_lo_u32 v3, s3, v0
7045; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
7046; GFX9-NEXT:    s_add_i32 s3, s6, s2
7047; GFX9-NEXT:    s_sub_i32 s6, 0, s0
7048; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v3
7049; GFX9-NEXT:    v_mul_lo_u32 v4, s6, v1
7050; GFX9-NEXT:    s_xor_b32 s3, s3, s2
7051; GFX9-NEXT:    s_ashr_i32 s6, s7, 31
7052; GFX9-NEXT:    v_add_u32_e32 v0, v0, v3
7053; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v4
7054; GFX9-NEXT:    v_mul_hi_u32 v0, s3, v0
7055; GFX9-NEXT:    s_add_i32 s7, s7, s6
7056; GFX9-NEXT:    s_xor_b32 s7, s7, s6
7057; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
7058; GFX9-NEXT:    v_mul_hi_u32 v1, s7, v1
7059; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s1
7060; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s0
7061; GFX9-NEXT:    v_sub_u32_e32 v0, s3, v0
7062; GFX9-NEXT:    v_subrev_u32_e32 v3, s1, v0
7063; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s1, v0
7064; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
7065; GFX9-NEXT:    v_subrev_u32_e32 v3, s1, v0
7066; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s1, v0
7067; GFX9-NEXT:    v_sub_u32_e32 v1, s7, v1
7068; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
7069; GFX9-NEXT:    v_subrev_u32_e32 v3, s0, v1
7070; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s0, v1
7071; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
7072; GFX9-NEXT:    v_subrev_u32_e32 v3, s0, v1
7073; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s0, v1
7074; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
7075; GFX9-NEXT:    v_xor_b32_e32 v0, s2, v0
7076; GFX9-NEXT:    v_xor_b32_e32 v1, s6, v1
7077; GFX9-NEXT:    v_subrev_u32_e32 v0, s2, v0
7078; GFX9-NEXT:    v_subrev_u32_e32 v1, s6, v1
7079; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
7080; GFX9-NEXT:    s_endpgm
7081  %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
7082  %r = srem <2 x i32> %x, %shl.y
7083  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
7084  ret void
7085}
7086
7087define amdgpu_kernel void @udiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
7088; CHECK-LABEL: @udiv_i64_oddk_denom(
7089; CHECK-NEXT:    [[R:%.*]] = udiv i64 [[X:%.*]], 1235195949943
7090; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
7091; CHECK-NEXT:    ret void
7092;
7093; GFX6-LABEL: udiv_i64_oddk_denom:
7094; GFX6:       ; %bb.0:
7095; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f176a73
7096; GFX6-NEXT:    v_mov_b32_e32 v1, 0x4f800000
7097; GFX6-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
7098; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
7099; GFX6-NEXT:    s_movk_i32 s4, 0xfee0
7100; GFX6-NEXT:    s_mov_b32 s5, 0x68958c89
7101; GFX6-NEXT:    v_mov_b32_e32 v7, 0
7102; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
7103; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
7104; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
7105; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
7106; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
7107; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
7108; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
7109; GFX6-NEXT:    s_movk_i32 s8, 0x11f
7110; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s4
7111; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s5
7112; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s5
7113; GFX6-NEXT:    s_mov_b32 s9, 0x976a7377
7114; GFX6-NEXT:    s_mov_b32 s7, 0xf000
7115; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7116; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s5
7117; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
7118; GFX6-NEXT:    v_mul_lo_u32 v4, v0, v2
7119; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v3
7120; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
7121; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
7122; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
7123; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
7124; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
7125; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
7126; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
7127; GFX6-NEXT:    s_mov_b32 s6, -1
7128; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
7129; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
7130; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
7131; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7132; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
7133; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
7134; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
7135; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s4
7136; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s5
7137; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s5
7138; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7139; GFX6-NEXT:    s_mov_b32 s4, s0
7140; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7141; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s5
7142; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
7143; GFX6-NEXT:    v_mul_lo_u32 v4, v0, v2
7144; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v3
7145; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
7146; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
7147; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
7148; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
7149; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
7150; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
7151; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
7152; GFX6-NEXT:    s_mov_b32 s5, s1
7153; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
7154; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
7155; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
7156; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7157; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
7158; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
7159; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
7160; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
7161; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
7162; GFX6-NEXT:    v_mul_hi_u32 v4, s2, v1
7163; GFX6-NEXT:    v_mul_hi_u32 v5, s3, v1
7164; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v1
7165; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7166; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
7167; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v0
7168; GFX6-NEXT:    v_mul_hi_u32 v0, s3, v0
7169; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
7170; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
7171; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
7172; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
7173; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
7174; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s8
7175; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s9
7176; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s9
7177; GFX6-NEXT:    v_mov_b32_e32 v5, s8
7178; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7179; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s9
7180; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
7181; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s3, v2
7182; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s2, v3
7183; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
7184; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s9, v3
7185; GFX6-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
7186; GFX6-NEXT:    s_movk_i32 s2, 0x11e
7187; GFX6-NEXT:    v_cmp_lt_u32_e64 s[0:1], s2, v4
7188; GFX6-NEXT:    s_mov_b32 s9, 0x976a7376
7189; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
7190; GFX6-NEXT:    v_cmp_lt_u32_e64 s[0:1], s9, v5
7191; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
7192; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s8, v4
7193; GFX6-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
7194; GFX6-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
7195; GFX6-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
7196; GFX6-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
7197; GFX6-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
7198; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
7199; GFX6-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
7200; GFX6-NEXT:    v_mov_b32_e32 v6, s3
7201; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
7202; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s2, v2
7203; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
7204; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s9, v3
7205; GFX6-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
7206; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s8, v2
7207; GFX6-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
7208; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
7209; GFX6-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
7210; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
7211; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
7212; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
7213; GFX6-NEXT:    s_endpgm
7214;
7215; GFX9-LABEL: udiv_i64_oddk_denom:
7216; GFX9:       ; %bb.0:
7217; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f176a73
7218; GFX9-NEXT:    v_mov_b32_e32 v1, 0x4f800000
7219; GFX9-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
7220; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
7221; GFX9-NEXT:    s_movk_i32 s2, 0xfee0
7222; GFX9-NEXT:    s_mov_b32 s3, 0x68958c89
7223; GFX9-NEXT:    v_mov_b32_e32 v6, 0
7224; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
7225; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
7226; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
7227; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
7228; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
7229; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
7230; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
7231; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s2
7232; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s3
7233; GFX9-NEXT:    v_mul_lo_u32 v5, v1, s3
7234; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s3
7235; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
7236; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
7237; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
7238; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
7239; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
7240; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
7241; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
7242; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
7243; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
7244; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
7245; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
7246; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
7247; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
7248; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
7249; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7250; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
7251; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
7252; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
7253; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s2
7254; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s3
7255; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s3
7256; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s3
7257; GFX9-NEXT:    s_movk_i32 s2, 0x11f
7258; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
7259; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
7260; GFX9-NEXT:    v_mul_lo_u32 v3, v0, v2
7261; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v5
7262; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
7263; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
7264; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
7265; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
7266; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v7, vcc
7267; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v5
7268; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v5
7269; GFX9-NEXT:    s_mov_b32 s3, 0x976a7377
7270; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
7271; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v4, v5, vcc
7272; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
7273; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7274; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
7275; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
7276; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
7277; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7278; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
7279; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
7280; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
7281; GFX9-NEXT:    v_mul_hi_u32 v5, s7, v1
7282; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
7283; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7284; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
7285; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v0
7286; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
7287; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
7288; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
7289; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v5, v6, vcc
7290; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
7291; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
7292; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s2
7293; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s3
7294; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s3
7295; GFX9-NEXT:    v_mov_b32_e32 v5, s2
7296; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
7297; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s3
7298; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
7299; GFX9-NEXT:    v_sub_u32_e32 v4, s7, v2
7300; GFX9-NEXT:    v_sub_co_u32_e32 v3, vcc, s6, v3
7301; GFX9-NEXT:    v_subb_co_u32_e64 v4, s[0:1], v4, v5, vcc
7302; GFX9-NEXT:    v_subrev_co_u32_e64 v5, s[0:1], s3, v3
7303; GFX9-NEXT:    v_subbrev_co_u32_e64 v4, s[0:1], 0, v4, s[0:1]
7304; GFX9-NEXT:    s_movk_i32 s3, 0x11e
7305; GFX9-NEXT:    v_cmp_lt_u32_e64 s[0:1], s3, v4
7306; GFX9-NEXT:    s_mov_b32 s6, 0x976a7376
7307; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
7308; GFX9-NEXT:    v_cmp_lt_u32_e64 s[0:1], s6, v5
7309; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
7310; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s2, v4
7311; GFX9-NEXT:    v_cndmask_b32_e64 v4, v7, v5, s[0:1]
7312; GFX9-NEXT:    v_add_co_u32_e64 v5, s[0:1], 2, v0
7313; GFX9-NEXT:    v_addc_co_u32_e64 v7, s[0:1], 0, v1, s[0:1]
7314; GFX9-NEXT:    v_add_co_u32_e64 v8, s[0:1], 1, v0
7315; GFX9-NEXT:    v_addc_co_u32_e64 v9, s[0:1], 0, v1, s[0:1]
7316; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
7317; GFX9-NEXT:    v_cndmask_b32_e64 v4, v9, v7, s[0:1]
7318; GFX9-NEXT:    v_mov_b32_e32 v7, s7
7319; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v7, v2, vcc
7320; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s3, v2
7321; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
7322; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v3
7323; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
7324; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v2
7325; GFX9-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc
7326; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
7327; GFX9-NEXT:    v_cndmask_b32_e64 v2, v8, v5, s[0:1]
7328; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
7329; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
7330; GFX9-NEXT:    global_store_dwordx2 v6, v[0:1], s[4:5]
7331; GFX9-NEXT:    s_endpgm
7332  %r = udiv i64 %x, 1235195949943
7333  store i64 %r, i64 addrspace(1)* %out
7334  ret void
7335}
7336
7337define amdgpu_kernel void @udiv_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) {
7338; CHECK-LABEL: @udiv_i64_pow2k_denom(
7339; CHECK-NEXT:    [[R:%.*]] = udiv i64 [[X:%.*]], 4096
7340; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
7341; CHECK-NEXT:    ret void
7342;
7343; GFX6-LABEL: udiv_i64_pow2k_denom:
7344; GFX6:       ; %bb.0:
7345; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
7346; GFX6-NEXT:    s_mov_b32 s7, 0xf000
7347; GFX6-NEXT:    s_mov_b32 s6, -1
7348; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7349; GFX6-NEXT:    s_mov_b32 s4, s0
7350; GFX6-NEXT:    s_mov_b32 s5, s1
7351; GFX6-NEXT:    s_lshr_b64 s[0:1], s[2:3], 12
7352; GFX6-NEXT:    v_mov_b32_e32 v0, s0
7353; GFX6-NEXT:    v_mov_b32_e32 v1, s1
7354; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
7355; GFX6-NEXT:    s_endpgm
7356;
7357; GFX9-LABEL: udiv_i64_pow2k_denom:
7358; GFX9:       ; %bb.0:
7359; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
7360; GFX9-NEXT:    v_mov_b32_e32 v2, 0
7361; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7362; GFX9-NEXT:    s_lshr_b64 s[2:3], s[2:3], 12
7363; GFX9-NEXT:    v_mov_b32_e32 v0, s2
7364; GFX9-NEXT:    v_mov_b32_e32 v1, s3
7365; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
7366; GFX9-NEXT:    s_endpgm
7367  %r = udiv i64 %x, 4096
7368  store i64 %r, i64 addrspace(1)* %out
7369  ret void
7370}
7371
7372define amdgpu_kernel void @udiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %x, i64 %y) {
7373; CHECK-LABEL: @udiv_i64_pow2_shl_denom(
7374; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]]
7375; CHECK-NEXT:    [[R:%.*]] = udiv i64 [[X:%.*]], [[SHL_Y]]
7376; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
7377; CHECK-NEXT:    ret void
7378;
7379; GFX6-LABEL: udiv_i64_pow2_shl_denom:
7380; GFX6:       ; %bb.0:
7381; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
7382; GFX6-NEXT:    s_load_dword s8, s[0:1], 0xd
7383; GFX6-NEXT:    s_mov_b32 s3, 0xf000
7384; GFX6-NEXT:    s_mov_b32 s2, -1
7385; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7386; GFX6-NEXT:    s_mov_b32 s0, s4
7387; GFX6-NEXT:    s_add_i32 s8, s8, 12
7388; GFX6-NEXT:    s_mov_b32 s1, s5
7389; GFX6-NEXT:    s_lshr_b64 s[4:5], s[6:7], s8
7390; GFX6-NEXT:    v_mov_b32_e32 v0, s4
7391; GFX6-NEXT:    v_mov_b32_e32 v1, s5
7392; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
7393; GFX6-NEXT:    s_endpgm
7394;
7395; GFX9-LABEL: udiv_i64_pow2_shl_denom:
7396; GFX9:       ; %bb.0:
7397; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x34
7398; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
7399; GFX9-NEXT:    v_mov_b32_e32 v2, 0
7400; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7401; GFX9-NEXT:    s_add_i32 s2, s2, 12
7402; GFX9-NEXT:    s_lshr_b64 s[0:1], s[6:7], s2
7403; GFX9-NEXT:    v_mov_b32_e32 v0, s0
7404; GFX9-NEXT:    v_mov_b32_e32 v1, s1
7405; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
7406; GFX9-NEXT:    s_endpgm
7407  %shl.y = shl i64 4096, %y
7408  %r = udiv i64 %x, %shl.y
7409  store i64 %r, i64 addrspace(1)* %out
7410  ret void
7411}
7412
7413define amdgpu_kernel void @udiv_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
7414; CHECK-LABEL: @udiv_v2i64_pow2k_denom(
7415; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
7416; CHECK-NEXT:    [[TMP2:%.*]] = udiv i64 [[TMP1]], 4096
7417; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
7418; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
7419; CHECK-NEXT:    [[TMP5:%.*]] = udiv i64 [[TMP4]], 4096
7420; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
7421; CHECK-NEXT:    store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
7422; CHECK-NEXT:    ret void
7423;
7424; GFX6-LABEL: udiv_v2i64_pow2k_denom:
7425; GFX6:       ; %bb.0:
7426; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
7427; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
7428; GFX6-NEXT:    s_mov_b32 s3, 0xf000
7429; GFX6-NEXT:    s_mov_b32 s2, -1
7430; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7431; GFX6-NEXT:    s_lshr_b64 s[4:5], s[4:5], 12
7432; GFX6-NEXT:    s_lshr_b64 s[6:7], s[6:7], 12
7433; GFX6-NEXT:    v_mov_b32_e32 v0, s4
7434; GFX6-NEXT:    v_mov_b32_e32 v1, s5
7435; GFX6-NEXT:    v_mov_b32_e32 v2, s6
7436; GFX6-NEXT:    v_mov_b32_e32 v3, s7
7437; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
7438; GFX6-NEXT:    s_endpgm
7439;
7440; GFX9-LABEL: udiv_v2i64_pow2k_denom:
7441; GFX9:       ; %bb.0:
7442; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
7443; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
7444; GFX9-NEXT:    v_mov_b32_e32 v4, 0
7445; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7446; GFX9-NEXT:    s_lshr_b64 s[0:1], s[4:5], 12
7447; GFX9-NEXT:    s_lshr_b64 s[4:5], s[6:7], 12
7448; GFX9-NEXT:    v_mov_b32_e32 v0, s0
7449; GFX9-NEXT:    v_mov_b32_e32 v1, s1
7450; GFX9-NEXT:    v_mov_b32_e32 v2, s4
7451; GFX9-NEXT:    v_mov_b32_e32 v3, s5
7452; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
7453; GFX9-NEXT:    s_endpgm
7454  %r = udiv <2 x i64> %x, <i64 4096, i64 4096>
7455  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
7456  ret void
7457}
7458
7459define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
7460; CHECK-LABEL: @udiv_v2i64_mixed_pow2k_denom(
7461; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
7462; CHECK-NEXT:    [[TMP2:%.*]] = udiv i64 [[TMP1]], 4096
7463; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
7464; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
7465; CHECK-NEXT:    [[TMP5:%.*]] = udiv i64 [[TMP4]], 4095
7466; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
7467; CHECK-NEXT:    store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
7468; CHECK-NEXT:    ret void
7469;
7470; GFX6-LABEL: udiv_v2i64_mixed_pow2k_denom:
7471; GFX6:       ; %bb.0:
7472; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f800000
7473; GFX6-NEXT:    v_madak_f32 v0, 0, v0, 0x457ff000
7474; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
7475; GFX6-NEXT:    s_movk_i32 s6, 0xf001
7476; GFX6-NEXT:    v_mov_b32_e32 v7, 0
7477; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
7478; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
7479; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
7480; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
7481; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
7482; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
7483; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
7484; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
7485; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7486; GFX6-NEXT:    s_lshr_b64 s[8:9], s[0:1], 12
7487; GFX6-NEXT:    s_movk_i32 s0, 0xfff
7488; GFX6-NEXT:    v_mul_hi_u32 v2, v0, s6
7489; GFX6-NEXT:    v_mul_lo_u32 v3, v1, s6
7490; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s6
7491; GFX6-NEXT:    s_mov_b32 s7, 0xf000
7492; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
7493; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7494; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
7495; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v4
7496; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
7497; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
7498; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
7499; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
7500; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
7501; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
7502; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
7503; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
7504; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
7505; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
7506; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7507; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
7508; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
7509; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
7510; GFX6-NEXT:    v_mul_hi_u32 v2, v0, s6
7511; GFX6-NEXT:    v_mul_lo_u32 v3, v1, s6
7512; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s6
7513; GFX6-NEXT:    s_mov_b32 s6, -1
7514; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
7515; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
7516; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
7517; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v4
7518; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
7519; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
7520; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
7521; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
7522; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
7523; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
7524; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
7525; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
7526; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
7527; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
7528; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7529; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
7530; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
7531; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
7532; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
7533; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
7534; GFX6-NEXT:    v_mul_hi_u32 v4, s2, v1
7535; GFX6-NEXT:    v_mul_hi_u32 v5, s3, v1
7536; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v1
7537; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7538; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
7539; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v0
7540; GFX6-NEXT:    v_mul_hi_u32 v0, s3, v0
7541; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
7542; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
7543; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
7544; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
7545; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
7546; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s0
7547; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s0
7548; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 2, v0
7549; GFX6-NEXT:    v_mul_lo_u32 v8, v0, s0
7550; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
7551; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v0
7552; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v1, vcc
7553; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
7554; GFX6-NEXT:    v_mov_b32_e32 v5, s3
7555; GFX6-NEXT:    v_sub_i32_e32 v8, vcc, s2, v8
7556; GFX6-NEXT:    v_subb_u32_e32 v4, vcc, v5, v4, vcc
7557; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s0, v8
7558; GFX6-NEXT:    v_subbrev_u32_e32 v9, vcc, 0, v4, vcc
7559; GFX6-NEXT:    s_movk_i32 s0, 0xffe
7560; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v5
7561; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
7562; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v9
7563; GFX6-NEXT:    v_cndmask_b32_e32 v5, -1, v5, vcc
7564; GFX6-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v8
7565; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
7566; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
7567; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v4
7568; GFX6-NEXT:    v_cndmask_b32_e64 v4, -1, v5, s[0:1]
7569; GFX6-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
7570; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
7571; GFX6-NEXT:    v_cndmask_b32_e64 v3, v1, v3, s[0:1]
7572; GFX6-NEXT:    v_cndmask_b32_e32 v1, v6, v2, vcc
7573; GFX6-NEXT:    v_cndmask_b32_e64 v2, v0, v1, s[0:1]
7574; GFX6-NEXT:    v_mov_b32_e32 v0, s8
7575; GFX6-NEXT:    v_mov_b32_e32 v1, s9
7576; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
7577; GFX6-NEXT:    s_endpgm
7578;
7579; GFX9-LABEL: udiv_v2i64_mixed_pow2k_denom:
7580; GFX9:       ; %bb.0:
7581; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f800000
7582; GFX9-NEXT:    v_madak_f32 v0, 0, v0, 0x457ff000
7583; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
7584; GFX9-NEXT:    s_movk_i32 s2, 0xf001
7585; GFX9-NEXT:    v_mov_b32_e32 v5, 0
7586; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
7587; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
7588; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
7589; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
7590; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
7591; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
7592; GFX9-NEXT:    v_mul_hi_u32 v2, v0, s2
7593; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s2
7594; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s2
7595; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
7596; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
7597; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v3
7598; GFX9-NEXT:    v_mul_lo_u32 v4, v0, v2
7599; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
7600; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v3
7601; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
7602; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
7603; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
7604; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
7605; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
7606; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v7
7607; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
7608; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
7609; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7610; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
7611; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
7612; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
7613; GFX9-NEXT:    v_mul_hi_u32 v2, v0, s2
7614; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s2
7615; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s2
7616; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
7617; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
7618; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
7619; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
7620; GFX9-NEXT:    v_mul_lo_u32 v3, v0, v2
7621; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v4
7622; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
7623; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
7624; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
7625; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v6, v3
7626; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
7627; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
7628; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
7629; GFX9-NEXT:    s_movk_i32 s0, 0xfff
7630; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7631; GFX9-NEXT:    s_lshr_b64 s[4:5], s[4:5], 12
7632; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
7633; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
7634; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
7635; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7636; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
7637; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
7638; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
7639; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
7640; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
7641; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
7642; GFX9-NEXT:    v_mul_hi_u32 v6, s7, v1
7643; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
7644; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7645; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
7646; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v0
7647; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
7648; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
7649; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
7650; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
7651; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
7652; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
7653; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, 2, v0
7654; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s0
7655; GFX9-NEXT:    v_mul_hi_u32 v6, v0, s0
7656; GFX9-NEXT:    v_mul_lo_u32 v9, v0, s0
7657; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
7658; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, 1, v0
7659; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v1, vcc
7660; GFX9-NEXT:    v_add_u32_e32 v4, v6, v4
7661; GFX9-NEXT:    v_mov_b32_e32 v6, s7
7662; GFX9-NEXT:    v_sub_co_u32_e32 v9, vcc, s6, v9
7663; GFX9-NEXT:    v_subb_co_u32_e32 v4, vcc, v6, v4, vcc
7664; GFX9-NEXT:    v_subrev_co_u32_e32 v6, vcc, s0, v9
7665; GFX9-NEXT:    v_subbrev_co_u32_e32 v10, vcc, 0, v4, vcc
7666; GFX9-NEXT:    s_movk_i32 s0, 0xffe
7667; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v6
7668; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
7669; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v10
7670; GFX9-NEXT:    v_cndmask_b32_e32 v6, -1, v6, vcc
7671; GFX9-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v9
7672; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
7673; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
7674; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v4
7675; GFX9-NEXT:    v_cndmask_b32_e64 v4, -1, v6, s[0:1]
7676; GFX9-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
7677; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
7678; GFX9-NEXT:    v_cndmask_b32_e64 v3, v1, v3, s[0:1]
7679; GFX9-NEXT:    v_cndmask_b32_e32 v1, v7, v2, vcc
7680; GFX9-NEXT:    v_cndmask_b32_e64 v2, v0, v1, s[0:1]
7681; GFX9-NEXT:    v_mov_b32_e32 v0, s4
7682; GFX9-NEXT:    v_mov_b32_e32 v1, s5
7683; GFX9-NEXT:    global_store_dwordx4 v5, v[0:3], s[2:3]
7684; GFX9-NEXT:    s_endpgm
7685  %r = udiv <2 x i64> %x, <i64 4096, i64 4095>
7686  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
7687  ret void
7688}
7689
7690define amdgpu_kernel void @udiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
7691; CHECK-LABEL: @udiv_v2i64_pow2_shl_denom(
7692; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.*]]
7693; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
7694; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 0
7695; CHECK-NEXT:    [[TMP3:%.*]] = udiv i64 [[TMP1]], [[TMP2]]
7696; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i64 0
7697; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 1
7698; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
7699; CHECK-NEXT:    [[TMP7:%.*]] = udiv i64 [[TMP5]], [[TMP6]]
7700; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
7701; CHECK-NEXT:    store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
7702; CHECK-NEXT:    ret void
7703;
7704; GFX6-LABEL: udiv_v2i64_pow2_shl_denom:
7705; GFX6:       ; %bb.0:
7706; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x11
7707; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
7708; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
7709; GFX6-NEXT:    s_mov_b32 s3, 0xf000
7710; GFX6-NEXT:    s_mov_b32 s2, -1
7711; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7712; GFX6-NEXT:    s_add_i32 s4, s4, 12
7713; GFX6-NEXT:    s_add_i32 s6, s6, 12
7714; GFX6-NEXT:    s_lshr_b64 s[4:5], s[8:9], s4
7715; GFX6-NEXT:    s_lshr_b64 s[6:7], s[10:11], s6
7716; GFX6-NEXT:    v_mov_b32_e32 v0, s4
7717; GFX6-NEXT:    v_mov_b32_e32 v1, s5
7718; GFX6-NEXT:    v_mov_b32_e32 v2, s6
7719; GFX6-NEXT:    v_mov_b32_e32 v3, s7
7720; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
7721; GFX6-NEXT:    s_endpgm
7722;
7723; GFX9-LABEL: udiv_v2i64_pow2_shl_denom:
7724; GFX9:       ; %bb.0:
7725; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x44
7726; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
7727; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
7728; GFX9-NEXT:    v_mov_b32_e32 v4, 0
7729; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7730; GFX9-NEXT:    s_add_i32 s0, s4, 12
7731; GFX9-NEXT:    s_add_i32 s4, s6, 12
7732; GFX9-NEXT:    s_lshr_b64 s[0:1], s[8:9], s0
7733; GFX9-NEXT:    s_lshr_b64 s[4:5], s[10:11], s4
7734; GFX9-NEXT:    v_mov_b32_e32 v0, s0
7735; GFX9-NEXT:    v_mov_b32_e32 v1, s1
7736; GFX9-NEXT:    v_mov_b32_e32 v2, s4
7737; GFX9-NEXT:    v_mov_b32_e32 v3, s5
7738; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
7739; GFX9-NEXT:    s_endpgm
7740  %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
7741  %r = udiv <2 x i64> %x, %shl.y
7742  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
7743  ret void
7744}
7745
7746define amdgpu_kernel void @urem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
7747; CHECK-LABEL: @urem_i64_oddk_denom(
7748; CHECK-NEXT:    [[R:%.*]] = urem i64 [[X:%.*]], 1235195393993
7749; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
7750; CHECK-NEXT:    ret void
7751;
7752; GFX6-LABEL: urem_i64_oddk_denom:
7753; GFX6:       ; %bb.0:
7754; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f1761f8
7755; GFX6-NEXT:    v_mov_b32_e32 v1, 0x4f800000
7756; GFX6-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
7757; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
7758; GFX6-NEXT:    s_movk_i32 s2, 0xfee0
7759; GFX6-NEXT:    s_mov_b32 s3, 0x689e0837
7760; GFX6-NEXT:    v_mov_b32_e32 v7, 0
7761; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
7762; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
7763; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
7764; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
7765; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
7766; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
7767; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
7768; GFX6-NEXT:    s_mov_b32 s12, 0x9761f7c9
7769; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s2
7770; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s3
7771; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s3
7772; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7773; GFX6-NEXT:    s_mov_b32 s8, s4
7774; GFX6-NEXT:    s_movk_i32 s4, 0x11f
7775; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7776; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s3
7777; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
7778; GFX6-NEXT:    v_mul_lo_u32 v4, v0, v2
7779; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v3
7780; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
7781; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
7782; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
7783; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
7784; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
7785; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
7786; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
7787; GFX6-NEXT:    s_mov_b32 s9, s5
7788; GFX6-NEXT:    s_movk_i32 s5, 0x11e
7789; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
7790; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
7791; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
7792; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7793; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
7794; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
7795; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
7796; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s2
7797; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s3
7798; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s3
7799; GFX6-NEXT:    s_mov_b32 s11, 0xf000
7800; GFX6-NEXT:    s_mov_b32 s10, -1
7801; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7802; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s3
7803; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
7804; GFX6-NEXT:    v_mul_lo_u32 v4, v0, v2
7805; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v3
7806; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
7807; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
7808; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
7809; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
7810; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
7811; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
7812; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
7813; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
7814; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
7815; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
7816; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7817; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
7818; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
7819; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
7820; GFX6-NEXT:    v_mul_lo_u32 v2, s6, v1
7821; GFX6-NEXT:    v_mul_hi_u32 v3, s6, v0
7822; GFX6-NEXT:    v_mul_hi_u32 v4, s6, v1
7823; GFX6-NEXT:    v_mul_hi_u32 v5, s7, v1
7824; GFX6-NEXT:    v_mul_lo_u32 v1, s7, v1
7825; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7826; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
7827; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v0
7828; GFX6-NEXT:    v_mul_hi_u32 v0, s7, v0
7829; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
7830; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
7831; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
7832; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
7833; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
7834; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s4
7835; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s12
7836; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s12
7837; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s12
7838; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7839; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
7840; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s7, v1
7841; GFX6-NEXT:    v_mov_b32_e32 v3, s4
7842; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
7843; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
7844; GFX6-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
7845; GFX6-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
7846; GFX6-NEXT:    v_cmp_lt_u32_e64 s[2:3], s5, v5
7847; GFX6-NEXT:    s_mov_b32 s6, 0x9761f7c8
7848; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
7849; GFX6-NEXT:    v_cmp_lt_u32_e64 s[2:3], s6, v4
7850; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
7851; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
7852; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s4, v5
7853; GFX6-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
7854; GFX6-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
7855; GFX6-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
7856; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
7857; GFX6-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
7858; GFX6-NEXT:    v_mov_b32_e32 v5, s7
7859; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
7860; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s5, v1
7861; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
7862; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v0
7863; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
7864; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v1
7865; GFX6-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
7866; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
7867; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
7868; GFX6-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
7869; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
7870; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
7871; GFX6-NEXT:    s_endpgm
7872;
7873; GFX9-LABEL: urem_i64_oddk_denom:
7874; GFX9:       ; %bb.0:
7875; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f1761f8
7876; GFX9-NEXT:    v_mov_b32_e32 v1, 0x4f800000
7877; GFX9-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
7878; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
7879; GFX9-NEXT:    s_movk_i32 s2, 0xfee0
7880; GFX9-NEXT:    s_mov_b32 s3, 0x689e0837
7881; GFX9-NEXT:    v_mov_b32_e32 v6, 0
7882; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
7883; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
7884; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
7885; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
7886; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
7887; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
7888; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
7889; GFX9-NEXT:    s_movk_i32 s8, 0x11f
7890; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s2
7891; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s3
7892; GFX9-NEXT:    v_mul_lo_u32 v5, v1, s3
7893; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s3
7894; GFX9-NEXT:    s_mov_b32 s9, 0x9761f7c9
7895; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
7896; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
7897; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
7898; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
7899; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
7900; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
7901; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
7902; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
7903; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
7904; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
7905; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
7906; GFX9-NEXT:    s_mov_b32 s10, 0x9761f7c8
7907; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
7908; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
7909; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
7910; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7911; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
7912; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
7913; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
7914; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s2
7915; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s3
7916; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s3
7917; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s3
7918; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
7919; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
7920; GFX9-NEXT:    v_mul_lo_u32 v3, v0, v2
7921; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v5
7922; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
7923; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
7924; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
7925; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
7926; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v7, vcc
7927; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v5
7928; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v5
7929; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
7930; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v4, v5, vcc
7931; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
7932; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7933; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
7934; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
7935; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
7936; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7937; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
7938; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
7939; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
7940; GFX9-NEXT:    v_mul_hi_u32 v5, s7, v1
7941; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
7942; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7943; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
7944; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v0
7945; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
7946; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
7947; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
7948; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v5, v6, vcc
7949; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
7950; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
7951; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s8
7952; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s9
7953; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s9
7954; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s9
7955; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
7956; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
7957; GFX9-NEXT:    v_sub_u32_e32 v2, s7, v1
7958; GFX9-NEXT:    v_mov_b32_e32 v3, s8
7959; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, s6, v0
7960; GFX9-NEXT:    v_subb_co_u32_e64 v2, s[0:1], v2, v3, vcc
7961; GFX9-NEXT:    v_subrev_co_u32_e64 v4, s[0:1], s9, v0
7962; GFX9-NEXT:    v_subbrev_co_u32_e64 v5, s[2:3], 0, v2, s[0:1]
7963; GFX9-NEXT:    s_movk_i32 s6, 0x11e
7964; GFX9-NEXT:    v_cmp_lt_u32_e64 s[2:3], s6, v5
7965; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
7966; GFX9-NEXT:    v_cmp_lt_u32_e64 s[2:3], s10, v4
7967; GFX9-NEXT:    v_subb_co_u32_e64 v2, s[0:1], v2, v3, s[0:1]
7968; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[2:3]
7969; GFX9-NEXT:    v_cmp_eq_u32_e64 s[2:3], s8, v5
7970; GFX9-NEXT:    v_subrev_co_u32_e64 v3, s[0:1], s9, v4
7971; GFX9-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[2:3]
7972; GFX9-NEXT:    v_subbrev_co_u32_e64 v2, s[0:1], 0, v2, s[0:1]
7973; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v7
7974; GFX9-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
7975; GFX9-NEXT:    v_mov_b32_e32 v5, s7
7976; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v5, v1, vcc
7977; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v1
7978; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
7979; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s10, v0
7980; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
7981; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s8, v1
7982; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
7983; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
7984; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
7985; GFX9-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
7986; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
7987; GFX9-NEXT:    global_store_dwordx2 v6, v[0:1], s[4:5]
7988; GFX9-NEXT:    s_endpgm
7989  %r = urem i64 %x, 1235195393993
7990  store i64 %r, i64 addrspace(1)* %out
7991  ret void
7992}
7993
7994define amdgpu_kernel void @urem_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) {
7995; CHECK-LABEL: @urem_i64_pow2k_denom(
7996; CHECK-NEXT:    [[R:%.*]] = urem i64 [[X:%.*]], 4096
7997; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
7998; CHECK-NEXT:    ret void
7999;
8000; GFX6-LABEL: urem_i64_pow2k_denom:
8001; GFX6:       ; %bb.0:
8002; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
8003; GFX6-NEXT:    s_mov_b32 s7, 0xf000
8004; GFX6-NEXT:    s_mov_b32 s6, -1
8005; GFX6-NEXT:    v_mov_b32_e32 v1, 0
8006; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8007; GFX6-NEXT:    s_mov_b32 s4, s0
8008; GFX6-NEXT:    s_and_b32 s0, s2, 0xfff
8009; GFX6-NEXT:    s_mov_b32 s5, s1
8010; GFX6-NEXT:    v_mov_b32_e32 v0, s0
8011; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
8012; GFX6-NEXT:    s_endpgm
8013;
8014; GFX9-LABEL: urem_i64_pow2k_denom:
8015; GFX9:       ; %bb.0:
8016; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
8017; GFX9-NEXT:    v_mov_b32_e32 v1, 0
8018; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8019; GFX9-NEXT:    s_and_b32 s2, s2, 0xfff
8020; GFX9-NEXT:    v_mov_b32_e32 v0, s2
8021; GFX9-NEXT:    global_store_dwordx2 v1, v[0:1], s[0:1]
8022; GFX9-NEXT:    s_endpgm
8023  %r = urem i64 %x, 4096
8024  store i64 %r, i64 addrspace(1)* %out
8025  ret void
8026}
8027
8028define amdgpu_kernel void @urem_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %x, i64 %y) {
8029; CHECK-LABEL: @urem_i64_pow2_shl_denom(
8030; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]]
8031; CHECK-NEXT:    [[R:%.*]] = urem i64 [[X:%.*]], [[SHL_Y]]
8032; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
8033; CHECK-NEXT:    ret void
8034;
8035; GFX6-LABEL: urem_i64_pow2_shl_denom:
8036; GFX6:       ; %bb.0:
8037; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
8038; GFX6-NEXT:    s_load_dword s8, s[0:1], 0xd
8039; GFX6-NEXT:    s_mov_b32 s3, 0xf000
8040; GFX6-NEXT:    s_mov_b32 s2, -1
8041; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8042; GFX6-NEXT:    s_mov_b32 s0, s4
8043; GFX6-NEXT:    s_mov_b32 s1, s5
8044; GFX6-NEXT:    s_mov_b64 s[4:5], 0x1000
8045; GFX6-NEXT:    s_lshl_b64 s[4:5], s[4:5], s8
8046; GFX6-NEXT:    s_add_u32 s4, s4, -1
8047; GFX6-NEXT:    s_addc_u32 s5, s5, -1
8048; GFX6-NEXT:    s_and_b64 s[4:5], s[6:7], s[4:5]
8049; GFX6-NEXT:    v_mov_b32_e32 v0, s4
8050; GFX6-NEXT:    v_mov_b32_e32 v1, s5
8051; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
8052; GFX6-NEXT:    s_endpgm
8053;
8054; GFX9-LABEL: urem_i64_pow2_shl_denom:
8055; GFX9:       ; %bb.0:
8056; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x34
8057; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
8058; GFX9-NEXT:    s_mov_b64 s[0:1], 0x1000
8059; GFX9-NEXT:    v_mov_b32_e32 v2, 0
8060; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8061; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s2
8062; GFX9-NEXT:    s_add_u32 s0, s0, -1
8063; GFX9-NEXT:    s_addc_u32 s1, s1, -1
8064; GFX9-NEXT:    s_and_b64 s[0:1], s[6:7], s[0:1]
8065; GFX9-NEXT:    v_mov_b32_e32 v0, s0
8066; GFX9-NEXT:    v_mov_b32_e32 v1, s1
8067; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
8068; GFX9-NEXT:    s_endpgm
8069  %shl.y = shl i64 4096, %y
8070  %r = urem i64 %x, %shl.y
8071  store i64 %r, i64 addrspace(1)* %out
8072  ret void
8073}
8074
8075define amdgpu_kernel void @urem_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
8076; CHECK-LABEL: @urem_v2i64_pow2k_denom(
8077; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
8078; CHECK-NEXT:    [[TMP2:%.*]] = urem i64 [[TMP1]], 4096
8079; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
8080; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
8081; CHECK-NEXT:    [[TMP5:%.*]] = urem i64 [[TMP4]], 4096
8082; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
8083; CHECK-NEXT:    store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
8084; CHECK-NEXT:    ret void
8085;
8086; GFX6-LABEL: urem_v2i64_pow2k_denom:
8087; GFX6:       ; %bb.0:
8088; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
8089; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
8090; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8091; GFX6-NEXT:    s_movk_i32 s5, 0xfff
8092; GFX6-NEXT:    v_mov_b32_e32 v1, 0
8093; GFX6-NEXT:    s_mov_b32 s3, 0xf000
8094; GFX6-NEXT:    s_and_b32 s4, s4, s5
8095; GFX6-NEXT:    s_and_b32 s5, s6, s5
8096; GFX6-NEXT:    s_mov_b32 s2, -1
8097; GFX6-NEXT:    v_mov_b32_e32 v0, s4
8098; GFX6-NEXT:    v_mov_b32_e32 v2, s5
8099; GFX6-NEXT:    v_mov_b32_e32 v3, v1
8100; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
8101; GFX6-NEXT:    s_endpgm
8102;
8103; GFX9-LABEL: urem_v2i64_pow2k_denom:
8104; GFX9:       ; %bb.0:
8105; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
8106; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
8107; GFX9-NEXT:    s_movk_i32 s0, 0xfff
8108; GFX9-NEXT:    v_mov_b32_e32 v1, 0
8109; GFX9-NEXT:    v_mov_b32_e32 v3, v1
8110; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8111; GFX9-NEXT:    s_and_b32 s1, s4, s0
8112; GFX9-NEXT:    s_and_b32 s0, s6, s0
8113; GFX9-NEXT:    v_mov_b32_e32 v0, s1
8114; GFX9-NEXT:    v_mov_b32_e32 v2, s0
8115; GFX9-NEXT:    global_store_dwordx4 v1, v[0:3], s[2:3]
8116; GFX9-NEXT:    s_endpgm
8117  %r = urem <2 x i64> %x, <i64 4096, i64 4096>
8118  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
8119  ret void
8120}
8121
8122define amdgpu_kernel void @urem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
8123; CHECK-LABEL: @urem_v2i64_pow2_shl_denom(
8124; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.*]]
8125; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
8126; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 0
8127; CHECK-NEXT:    [[TMP3:%.*]] = urem i64 [[TMP1]], [[TMP2]]
8128; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i64 0
8129; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 1
8130; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
8131; CHECK-NEXT:    [[TMP7:%.*]] = urem i64 [[TMP5]], [[TMP6]]
8132; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
8133; CHECK-NEXT:    store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
8134; CHECK-NEXT:    ret void
8135;
8136; GFX6-LABEL: urem_v2i64_pow2_shl_denom:
8137; GFX6:       ; %bb.0:
8138; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
8139; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
8140; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
8141; GFX6-NEXT:    s_mov_b64 s[12:13], 0x1000
8142; GFX6-NEXT:    s_mov_b32 s7, 0xf000
8143; GFX6-NEXT:    s_mov_b32 s6, -1
8144; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8145; GFX6-NEXT:    s_lshl_b64 s[2:3], s[12:13], s2
8146; GFX6-NEXT:    s_lshl_b64 s[0:1], s[12:13], s0
8147; GFX6-NEXT:    s_add_u32 s0, s0, -1
8148; GFX6-NEXT:    s_addc_u32 s1, s1, -1
8149; GFX6-NEXT:    s_and_b64 s[0:1], s[8:9], s[0:1]
8150; GFX6-NEXT:    s_add_u32 s2, s2, -1
8151; GFX6-NEXT:    s_addc_u32 s3, s3, -1
8152; GFX6-NEXT:    s_and_b64 s[2:3], s[10:11], s[2:3]
8153; GFX6-NEXT:    v_mov_b32_e32 v0, s0
8154; GFX6-NEXT:    v_mov_b32_e32 v1, s1
8155; GFX6-NEXT:    v_mov_b32_e32 v2, s2
8156; GFX6-NEXT:    v_mov_b32_e32 v3, s3
8157; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
8158; GFX6-NEXT:    s_endpgm
8159;
8160; GFX9-LABEL: urem_v2i64_pow2_shl_denom:
8161; GFX9:       ; %bb.0:
8162; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x44
8163; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
8164; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
8165; GFX9-NEXT:    s_mov_b64 s[0:1], 0x1000
8166; GFX9-NEXT:    v_mov_b32_e32 v4, 0
8167; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8168; GFX9-NEXT:    s_lshl_b64 s[6:7], s[0:1], s6
8169; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s4
8170; GFX9-NEXT:    s_add_u32 s0, s0, -1
8171; GFX9-NEXT:    s_addc_u32 s1, s1, -1
8172; GFX9-NEXT:    s_and_b64 s[0:1], s[8:9], s[0:1]
8173; GFX9-NEXT:    s_add_u32 s4, s6, -1
8174; GFX9-NEXT:    s_addc_u32 s5, s7, -1
8175; GFX9-NEXT:    s_and_b64 s[4:5], s[10:11], s[4:5]
8176; GFX9-NEXT:    v_mov_b32_e32 v0, s0
8177; GFX9-NEXT:    v_mov_b32_e32 v1, s1
8178; GFX9-NEXT:    v_mov_b32_e32 v2, s4
8179; GFX9-NEXT:    v_mov_b32_e32 v3, s5
8180; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
8181; GFX9-NEXT:    s_endpgm
8182  %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
8183  %r = urem <2 x i64> %x, %shl.y
8184  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
8185  ret void
8186}
8187
8188define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
8189; CHECK-LABEL: @sdiv_i64_oddk_denom(
8190; CHECK-NEXT:    [[R:%.*]] = sdiv i64 [[X:%.*]], 1235195
8191; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
8192; CHECK-NEXT:    ret void
8193;
8194; GFX6-LABEL: sdiv_i64_oddk_denom:
8195; GFX6:       ; %bb.0:
8196; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f800000
8197; GFX6-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
8198; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
8199; GFX6-NEXT:    s_mov_b32 s5, 0xffed2705
8200; GFX6-NEXT:    v_mov_b32_e32 v7, 0
8201; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
8202; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
8203; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
8204; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
8205; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
8206; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
8207; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
8208; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8209; GFX6-NEXT:    s_ashr_i32 s8, s3, 31
8210; GFX6-NEXT:    s_add_u32 s2, s2, s8
8211; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s5
8212; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s5
8213; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s5
8214; GFX6-NEXT:    s_mov_b32 s9, s8
8215; GFX6-NEXT:    s_addc_u32 s3, s3, s8
8216; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8217; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
8218; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
8219; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v4
8220; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
8221; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
8222; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
8223; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
8224; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
8225; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
8226; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
8227; GFX6-NEXT:    s_xor_b64 s[2:3], s[2:3], s[8:9]
8228; GFX6-NEXT:    s_mov_b32 s4, s0
8229; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
8230; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
8231; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
8232; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8233; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
8234; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
8235; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
8236; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s5
8237; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s5
8238; GFX6-NEXT:    s_mov_b32 s0, 0x12d8fb
8239; GFX6-NEXT:    s_mov_b32 s7, 0xf000
8240; GFX6-NEXT:    s_mov_b32 s6, -1
8241; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8242; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s5
8243; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
8244; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v2
8245; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v3
8246; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v2
8247; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v3
8248; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
8249; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v2
8250; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
8251; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
8252; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
8253; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
8254; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v5, vcc
8255; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v4, v7, vcc
8256; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8257; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
8258; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
8259; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
8260; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
8261; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
8262; GFX6-NEXT:    v_mul_hi_u32 v4, s2, v1
8263; GFX6-NEXT:    v_mul_hi_u32 v5, s3, v1
8264; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v1
8265; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8266; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
8267; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v0
8268; GFX6-NEXT:    v_mul_hi_u32 v0, s3, v0
8269; GFX6-NEXT:    s_mov_b32 s5, s1
8270; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
8271; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
8272; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
8273; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
8274; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
8275; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s0
8276; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s0
8277; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 2, v0
8278; GFX6-NEXT:    v_mul_lo_u32 v8, v0, s0
8279; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
8280; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v0
8281; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v1, vcc
8282; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
8283; GFX6-NEXT:    v_mov_b32_e32 v5, s3
8284; GFX6-NEXT:    v_sub_i32_e32 v8, vcc, s2, v8
8285; GFX6-NEXT:    v_subb_u32_e32 v4, vcc, v5, v4, vcc
8286; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s0, v8
8287; GFX6-NEXT:    v_subbrev_u32_e32 v9, vcc, 0, v4, vcc
8288; GFX6-NEXT:    s_mov_b32 s0, 0x12d8fa
8289; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v5
8290; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
8291; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v9
8292; GFX6-NEXT:    v_cndmask_b32_e32 v5, -1, v5, vcc
8293; GFX6-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v8
8294; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
8295; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
8296; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v4
8297; GFX6-NEXT:    v_cndmask_b32_e64 v4, -1, v5, s[0:1]
8298; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
8299; GFX6-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
8300; GFX6-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
8301; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
8302; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
8303; GFX6-NEXT:    v_xor_b32_e32 v0, s8, v0
8304; GFX6-NEXT:    v_xor_b32_e32 v1, s8, v1
8305; GFX6-NEXT:    v_mov_b32_e32 v2, s8
8306; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v0
8307; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
8308; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
8309; GFX6-NEXT:    s_endpgm
8310;
8311; GFX9-LABEL: sdiv_i64_oddk_denom:
8312; GFX9:       ; %bb.0:
8313; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f800000
8314; GFX9-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
8315; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
8316; GFX9-NEXT:    s_mov_b32 s2, 0xffed2705
8317; GFX9-NEXT:    v_mov_b32_e32 v5, 0
8318; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
8319; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
8320; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
8321; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
8322; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
8323; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
8324; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
8325; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s2
8326; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s2
8327; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s2
8328; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
8329; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
8330; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
8331; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
8332; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
8333; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
8334; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
8335; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
8336; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
8337; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
8338; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
8339; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
8340; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
8341; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
8342; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
8343; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
8344; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
8345; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
8346; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s2
8347; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s2
8348; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s2
8349; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8350; GFX9-NEXT:    s_ashr_i32 s2, s7, 31
8351; GFX9-NEXT:    s_add_u32 s0, s6, s2
8352; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
8353; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
8354; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v2
8355; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v4
8356; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v2
8357; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v4
8358; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v4
8359; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v2
8360; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
8361; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
8362; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
8363; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v7, v4
8364; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
8365; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v5, vcc
8366; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
8367; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
8368; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
8369; GFX9-NEXT:    s_mov_b32 s3, s2
8370; GFX9-NEXT:    s_addc_u32 s1, s7, s2
8371; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
8372; GFX9-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
8373; GFX9-NEXT:    v_mul_lo_u32 v2, s0, v1
8374; GFX9-NEXT:    v_mul_hi_u32 v3, s0, v0
8375; GFX9-NEXT:    v_mul_hi_u32 v4, s0, v1
8376; GFX9-NEXT:    v_mul_hi_u32 v6, s1, v1
8377; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v1
8378; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
8379; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
8380; GFX9-NEXT:    v_mul_lo_u32 v4, s1, v0
8381; GFX9-NEXT:    v_mul_hi_u32 v0, s1, v0
8382; GFX9-NEXT:    s_mov_b32 s3, 0x12d8fb
8383; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
8384; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
8385; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
8386; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
8387; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
8388; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, 2, v0
8389; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s3
8390; GFX9-NEXT:    v_mul_hi_u32 v6, v0, s3
8391; GFX9-NEXT:    v_mul_lo_u32 v9, v0, s3
8392; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
8393; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, 1, v0
8394; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v1, vcc
8395; GFX9-NEXT:    v_add_u32_e32 v4, v6, v4
8396; GFX9-NEXT:    v_mov_b32_e32 v6, s1
8397; GFX9-NEXT:    v_sub_co_u32_e32 v9, vcc, s0, v9
8398; GFX9-NEXT:    v_subb_co_u32_e32 v4, vcc, v6, v4, vcc
8399; GFX9-NEXT:    v_subrev_co_u32_e32 v6, vcc, s3, v9
8400; GFX9-NEXT:    v_subbrev_co_u32_e32 v10, vcc, 0, v4, vcc
8401; GFX9-NEXT:    s_mov_b32 s0, 0x12d8fa
8402; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v6
8403; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
8404; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v10
8405; GFX9-NEXT:    v_cndmask_b32_e32 v6, -1, v6, vcc
8406; GFX9-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v9
8407; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
8408; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
8409; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v4
8410; GFX9-NEXT:    v_cndmask_b32_e64 v4, -1, v6, s[0:1]
8411; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
8412; GFX9-NEXT:    v_cndmask_b32_e32 v2, v7, v2, vcc
8413; GFX9-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
8414; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
8415; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
8416; GFX9-NEXT:    v_xor_b32_e32 v0, s2, v0
8417; GFX9-NEXT:    v_xor_b32_e32 v1, s2, v1
8418; GFX9-NEXT:    v_mov_b32_e32 v2, s2
8419; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s2, v0
8420; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
8421; GFX9-NEXT:    global_store_dwordx2 v5, v[0:1], s[4:5]
8422; GFX9-NEXT:    s_endpgm
8423  %r = sdiv i64 %x, 1235195
8424  store i64 %r, i64 addrspace(1)* %out
8425  ret void
8426}
8427
8428define amdgpu_kernel void @sdiv_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) {
8429; CHECK-LABEL: @sdiv_i64_pow2k_denom(
8430; CHECK-NEXT:    [[R:%.*]] = sdiv i64 [[X:%.*]], 4096
8431; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
8432; CHECK-NEXT:    ret void
8433;
8434; GFX6-LABEL: sdiv_i64_pow2k_denom:
8435; GFX6:       ; %bb.0:
8436; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
8437; GFX6-NEXT:    s_mov_b32 s7, 0xf000
8438; GFX6-NEXT:    s_mov_b32 s6, -1
8439; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8440; GFX6-NEXT:    s_mov_b32 s4, s0
8441; GFX6-NEXT:    s_ashr_i32 s0, s3, 31
8442; GFX6-NEXT:    s_lshr_b32 s0, s0, 20
8443; GFX6-NEXT:    s_add_u32 s0, s2, s0
8444; GFX6-NEXT:    s_mov_b32 s5, s1
8445; GFX6-NEXT:    s_addc_u32 s1, s3, 0
8446; GFX6-NEXT:    s_ashr_i64 s[0:1], s[0:1], 12
8447; GFX6-NEXT:    v_mov_b32_e32 v0, s0
8448; GFX6-NEXT:    v_mov_b32_e32 v1, s1
8449; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
8450; GFX6-NEXT:    s_endpgm
8451;
8452; GFX9-LABEL: sdiv_i64_pow2k_denom:
8453; GFX9:       ; %bb.0:
8454; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
8455; GFX9-NEXT:    v_mov_b32_e32 v2, 0
8456; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8457; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
8458; GFX9-NEXT:    s_lshr_b32 s4, s4, 20
8459; GFX9-NEXT:    s_add_u32 s2, s2, s4
8460; GFX9-NEXT:    s_addc_u32 s3, s3, 0
8461; GFX9-NEXT:    s_ashr_i64 s[2:3], s[2:3], 12
8462; GFX9-NEXT:    v_mov_b32_e32 v0, s2
8463; GFX9-NEXT:    v_mov_b32_e32 v1, s3
8464; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
8465; GFX9-NEXT:    s_endpgm
8466  %r = sdiv i64 %x, 4096
8467  store i64 %r, i64 addrspace(1)* %out
8468  ret void
8469}
8470
8471define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %x, i64 %y) {
8472; CHECK-LABEL: @sdiv_i64_pow2_shl_denom(
8473; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]]
8474; CHECK-NEXT:    [[R:%.*]] = sdiv i64 [[X:%.*]], [[SHL_Y]]
8475; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
8476; CHECK-NEXT:    ret void
8477;
8478; GFX6-LABEL: sdiv_i64_pow2_shl_denom:
8479; GFX6:       ; %bb.0:
8480; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xd
8481; GFX6-NEXT:    s_mov_b64 s[2:3], 0x1000
8482; GFX6-NEXT:    s_mov_b32 s7, 0xf000
8483; GFX6-NEXT:    s_mov_b32 s6, -1
8484; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8485; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
8486; GFX6-NEXT:    s_ashr_i32 s8, s3, 31
8487; GFX6-NEXT:    s_add_u32 s2, s2, s8
8488; GFX6-NEXT:    s_mov_b32 s9, s8
8489; GFX6-NEXT:    s_addc_u32 s3, s3, s8
8490; GFX6-NEXT:    s_xor_b64 s[10:11], s[2:3], s[8:9]
8491; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s10
8492; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s11
8493; GFX6-NEXT:    s_sub_u32 s4, 0, s10
8494; GFX6-NEXT:    s_subb_u32 s5, 0, s11
8495; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
8496; GFX6-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
8497; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
8498; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8499; GFX6-NEXT:    s_ashr_i32 s12, s3, 31
8500; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
8501; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
8502; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
8503; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
8504; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
8505; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
8506; GFX6-NEXT:    s_add_u32 s2, s2, s12
8507; GFX6-NEXT:    s_mov_b32 s13, s12
8508; GFX6-NEXT:    v_mul_lo_u32 v2, s4, v1
8509; GFX6-NEXT:    v_mul_hi_u32 v3, s4, v0
8510; GFX6-NEXT:    v_mul_lo_u32 v5, s5, v0
8511; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v0
8512; GFX6-NEXT:    s_addc_u32 s3, s3, s12
8513; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8514; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
8515; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
8516; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
8517; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
8518; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
8519; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
8520; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
8521; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
8522; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
8523; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
8524; GFX6-NEXT:    s_xor_b64 s[2:3], s[2:3], s[12:13]
8525; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
8526; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
8527; GFX6-NEXT:    v_mov_b32_e32 v4, 0
8528; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
8529; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8530; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
8531; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
8532; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
8533; GFX6-NEXT:    v_mul_lo_u32 v2, s4, v1
8534; GFX6-NEXT:    v_mul_hi_u32 v3, s4, v0
8535; GFX6-NEXT:    v_mul_lo_u32 v5, s5, v0
8536; GFX6-NEXT:    s_mov_b32 s5, s1
8537; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8538; GFX6-NEXT:    v_mul_lo_u32 v3, s4, v0
8539; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
8540; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v2
8541; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v3
8542; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v2
8543; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v3
8544; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
8545; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v2
8546; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
8547; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
8548; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
8549; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
8550; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v6, vcc
8551; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v5, v4, vcc
8552; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8553; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
8554; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
8555; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
8556; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
8557; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
8558; GFX6-NEXT:    v_mul_hi_u32 v5, s2, v1
8559; GFX6-NEXT:    v_mul_hi_u32 v6, s3, v1
8560; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v1
8561; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8562; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
8563; GFX6-NEXT:    v_mul_lo_u32 v5, s3, v0
8564; GFX6-NEXT:    v_mul_hi_u32 v0, s3, v0
8565; GFX6-NEXT:    s_mov_b32 s4, s0
8566; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
8567; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
8568; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v6, v4, vcc
8569; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
8570; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
8571; GFX6-NEXT:    v_mul_lo_u32 v2, s10, v1
8572; GFX6-NEXT:    v_mul_hi_u32 v3, s10, v0
8573; GFX6-NEXT:    v_mul_lo_u32 v4, s11, v0
8574; GFX6-NEXT:    v_mov_b32_e32 v5, s11
8575; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8576; GFX6-NEXT:    v_mul_lo_u32 v3, s10, v0
8577; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
8578; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s3, v2
8579; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s2, v3
8580; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
8581; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s10, v3
8582; GFX6-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
8583; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v4
8584; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
8585; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v5
8586; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
8587; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v4
8588; GFX6-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
8589; GFX6-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
8590; GFX6-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
8591; GFX6-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
8592; GFX6-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
8593; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
8594; GFX6-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
8595; GFX6-NEXT:    v_mov_b32_e32 v6, s3
8596; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
8597; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v2
8598; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
8599; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
8600; GFX6-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
8601; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v2
8602; GFX6-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
8603; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
8604; GFX6-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
8605; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
8606; GFX6-NEXT:    s_xor_b64 s[0:1], s[12:13], s[8:9]
8607; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
8608; GFX6-NEXT:    v_xor_b32_e32 v0, s0, v0
8609; GFX6-NEXT:    v_xor_b32_e32 v1, s1, v1
8610; GFX6-NEXT:    v_mov_b32_e32 v2, s1
8611; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
8612; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
8613; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
8614; GFX6-NEXT:    s_endpgm
8615;
8616; GFX9-LABEL: sdiv_i64_pow2_shl_denom:
8617; GFX9:       ; %bb.0:
8618; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x34
8619; GFX9-NEXT:    s_mov_b64 s[2:3], 0x1000
8620; GFX9-NEXT:    v_mov_b32_e32 v2, 0
8621; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8622; GFX9-NEXT:    s_lshl_b64 s[4:5], s[2:3], s4
8623; GFX9-NEXT:    s_ashr_i32 s2, s5, 31
8624; GFX9-NEXT:    s_add_u32 s4, s4, s2
8625; GFX9-NEXT:    s_mov_b32 s3, s2
8626; GFX9-NEXT:    s_addc_u32 s5, s5, s2
8627; GFX9-NEXT:    s_xor_b64 s[8:9], s[4:5], s[2:3]
8628; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
8629; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
8630; GFX9-NEXT:    s_sub_u32 s10, 0, s8
8631; GFX9-NEXT:    s_subb_u32 s4, 0, s9
8632; GFX9-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
8633; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
8634; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
8635; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
8636; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
8637; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
8638; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
8639; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
8640; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v1
8641; GFX9-NEXT:    v_mul_hi_u32 v4, s10, v0
8642; GFX9-NEXT:    v_mul_lo_u32 v6, s4, v0
8643; GFX9-NEXT:    v_mul_lo_u32 v5, s10, v0
8644; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
8645; GFX9-NEXT:    v_add_u32_e32 v3, v3, v6
8646; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v5
8647; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v3
8648; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v3
8649; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v5
8650; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
8651; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v3
8652; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
8653; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
8654; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
8655; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v5
8656; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
8657; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v2, vcc
8658; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
8659; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
8660; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
8661; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
8662; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v1
8663; GFX9-NEXT:    v_mul_hi_u32 v4, s10, v0
8664; GFX9-NEXT:    v_mul_lo_u32 v5, s4, v0
8665; GFX9-NEXT:    v_mul_lo_u32 v6, s10, v0
8666; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
8667; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
8668; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
8669; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v3
8670; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v6
8671; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v3
8672; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v6
8673; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
8674; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v3
8675; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
8676; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
8677; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
8678; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
8679; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v5, vcc
8680; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v2, vcc
8681; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
8682; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8683; GFX9-NEXT:    s_ashr_i32 s10, s7, 31
8684; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
8685; GFX9-NEXT:    s_add_u32 s0, s6, s10
8686; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
8687; GFX9-NEXT:    s_mov_b32 s11, s10
8688; GFX9-NEXT:    s_addc_u32 s1, s7, s10
8689; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
8690; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[10:11]
8691; GFX9-NEXT:    v_mul_lo_u32 v3, s6, v1
8692; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v0
8693; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v1
8694; GFX9-NEXT:    v_mul_hi_u32 v6, s7, v1
8695; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
8696; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
8697; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
8698; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v0
8699; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
8700; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
8701; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v4, v0, vcc
8702; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v2, vcc
8703; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
8704; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
8705; GFX9-NEXT:    v_mul_lo_u32 v3, s8, v1
8706; GFX9-NEXT:    v_mul_hi_u32 v4, s8, v0
8707; GFX9-NEXT:    v_mul_lo_u32 v5, s9, v0
8708; GFX9-NEXT:    v_mov_b32_e32 v6, s9
8709; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
8710; GFX9-NEXT:    v_mul_lo_u32 v4, s8, v0
8711; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
8712; GFX9-NEXT:    v_sub_u32_e32 v5, s7, v3
8713; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, s6, v4
8714; GFX9-NEXT:    v_subb_co_u32_e64 v5, s[0:1], v5, v6, vcc
8715; GFX9-NEXT:    v_subrev_co_u32_e64 v6, s[0:1], s8, v4
8716; GFX9-NEXT:    v_subbrev_co_u32_e64 v5, s[0:1], 0, v5, s[0:1]
8717; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v5
8718; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
8719; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v6
8720; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
8721; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v5
8722; GFX9-NEXT:    v_cndmask_b32_e64 v5, v7, v6, s[0:1]
8723; GFX9-NEXT:    v_add_co_u32_e64 v6, s[0:1], 2, v0
8724; GFX9-NEXT:    v_addc_co_u32_e64 v7, s[0:1], 0, v1, s[0:1]
8725; GFX9-NEXT:    v_add_co_u32_e64 v8, s[0:1], 1, v0
8726; GFX9-NEXT:    v_addc_co_u32_e64 v9, s[0:1], 0, v1, s[0:1]
8727; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
8728; GFX9-NEXT:    v_cndmask_b32_e64 v5, v9, v7, s[0:1]
8729; GFX9-NEXT:    v_mov_b32_e32 v7, s7
8730; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v7, v3, vcc
8731; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
8732; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
8733; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v4
8734; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
8735; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v3
8736; GFX9-NEXT:    v_cndmask_b32_e32 v3, v7, v4, vcc
8737; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
8738; GFX9-NEXT:    v_cndmask_b32_e64 v3, v8, v6, s[0:1]
8739; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
8740; GFX9-NEXT:    s_xor_b64 s[0:1], s[10:11], s[2:3]
8741; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
8742; GFX9-NEXT:    v_xor_b32_e32 v0, s0, v0
8743; GFX9-NEXT:    v_xor_b32_e32 v1, s1, v1
8744; GFX9-NEXT:    v_mov_b32_e32 v3, s1
8745; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s0, v0
8746; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
8747; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
8748; GFX9-NEXT:    s_endpgm
8749  %shl.y = shl i64 4096, %y
8750  %r = sdiv i64 %x, %shl.y
8751  store i64 %r, i64 addrspace(1)* %out
8752  ret void
8753}
8754
8755define amdgpu_kernel void @sdiv_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
8756; CHECK-LABEL: @sdiv_v2i64_pow2k_denom(
8757; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
8758; CHECK-NEXT:    [[TMP2:%.*]] = sdiv i64 [[TMP1]], 4096
8759; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
8760; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
8761; CHECK-NEXT:    [[TMP5:%.*]] = sdiv i64 [[TMP4]], 4096
8762; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
8763; CHECK-NEXT:    store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
8764; CHECK-NEXT:    ret void
8765;
8766; GFX6-LABEL: sdiv_v2i64_pow2k_denom:
8767; GFX6:       ; %bb.0:
8768; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
8769; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
8770; GFX6-NEXT:    s_mov_b32 s3, 0xf000
8771; GFX6-NEXT:    s_mov_b32 s2, -1
8772; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8773; GFX6-NEXT:    s_ashr_i32 s8, s5, 31
8774; GFX6-NEXT:    s_lshr_b32 s8, s8, 20
8775; GFX6-NEXT:    s_add_u32 s4, s4, s8
8776; GFX6-NEXT:    s_addc_u32 s5, s5, 0
8777; GFX6-NEXT:    s_ashr_i32 s8, s7, 31
8778; GFX6-NEXT:    s_ashr_i64 s[4:5], s[4:5], 12
8779; GFX6-NEXT:    s_lshr_b32 s8, s8, 20
8780; GFX6-NEXT:    s_add_u32 s6, s6, s8
8781; GFX6-NEXT:    s_addc_u32 s7, s7, 0
8782; GFX6-NEXT:    s_ashr_i64 s[6:7], s[6:7], 12
8783; GFX6-NEXT:    v_mov_b32_e32 v0, s4
8784; GFX6-NEXT:    v_mov_b32_e32 v1, s5
8785; GFX6-NEXT:    v_mov_b32_e32 v2, s6
8786; GFX6-NEXT:    v_mov_b32_e32 v3, s7
8787; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
8788; GFX6-NEXT:    s_endpgm
8789;
8790; GFX9-LABEL: sdiv_v2i64_pow2k_denom:
8791; GFX9:       ; %bb.0:
8792; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
8793; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
8794; GFX9-NEXT:    v_mov_b32_e32 v4, 0
8795; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8796; GFX9-NEXT:    s_ashr_i32 s0, s5, 31
8797; GFX9-NEXT:    s_lshr_b32 s0, s0, 20
8798; GFX9-NEXT:    s_add_u32 s0, s4, s0
8799; GFX9-NEXT:    s_addc_u32 s1, s5, 0
8800; GFX9-NEXT:    s_ashr_i32 s4, s7, 31
8801; GFX9-NEXT:    s_ashr_i64 s[0:1], s[0:1], 12
8802; GFX9-NEXT:    s_lshr_b32 s4, s4, 20
8803; GFX9-NEXT:    s_add_u32 s4, s6, s4
8804; GFX9-NEXT:    s_addc_u32 s5, s7, 0
8805; GFX9-NEXT:    s_ashr_i64 s[4:5], s[4:5], 12
8806; GFX9-NEXT:    v_mov_b32_e32 v0, s0
8807; GFX9-NEXT:    v_mov_b32_e32 v1, s1
8808; GFX9-NEXT:    v_mov_b32_e32 v2, s4
8809; GFX9-NEXT:    v_mov_b32_e32 v3, s5
8810; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
8811; GFX9-NEXT:    s_endpgm
8812  %r = sdiv <2 x i64> %x, <i64 4096, i64 4096>
8813  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
8814  ret void
8815}
8816
8817define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
8818; CHECK-LABEL: @ssdiv_v2i64_mixed_pow2k_denom(
8819; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
8820; CHECK-NEXT:    [[TMP2:%.*]] = sdiv i64 [[TMP1]], 4096
8821; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
8822; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
8823; CHECK-NEXT:    [[TMP5:%.*]] = sdiv i64 [[TMP4]], 4095
8824; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
8825; CHECK-NEXT:    store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
8826; CHECK-NEXT:    ret void
8827;
8828; GFX6-LABEL: ssdiv_v2i64_mixed_pow2k_denom:
8829; GFX6:       ; %bb.0:
8830; GFX6-NEXT:    v_mov_b32_e32 v0, 0x457ff000
8831; GFX6-NEXT:    v_mov_b32_e32 v1, 0x4f800000
8832; GFX6-NEXT:    v_mac_f32_e32 v0, 0, v1
8833; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
8834; GFX6-NEXT:    s_movk_i32 s6, 0xf001
8835; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
8836; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
8837; GFX6-NEXT:    s_mov_b32 s7, 0xf000
8838; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
8839; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
8840; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
8841; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
8842; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
8843; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
8844; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8845; GFX6-NEXT:    s_ashr_i32 s8, s1, 31
8846; GFX6-NEXT:    s_lshr_b32 s8, s8, 20
8847; GFX6-NEXT:    v_mul_hi_u32 v2, v0, s6
8848; GFX6-NEXT:    v_mul_lo_u32 v3, v1, s6
8849; GFX6-NEXT:    s_add_u32 s0, s0, s8
8850; GFX6-NEXT:    s_addc_u32 s1, s1, 0
8851; GFX6-NEXT:    s_ashr_i64 s[8:9], s[0:1], 12
8852; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
8853; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s6
8854; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
8855; GFX6-NEXT:    v_mul_lo_u32 v4, v0, v2
8856; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v3
8857; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
8858; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
8859; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
8860; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
8861; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
8862; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
8863; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
8864; GFX6-NEXT:    s_ashr_i32 s10, s3, 31
8865; GFX6-NEXT:    s_add_u32 s0, s2, s10
8866; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
8867; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
8868; GFX6-NEXT:    v_mov_b32_e32 v4, 0
8869; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
8870; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8871; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
8872; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
8873; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
8874; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s6
8875; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s6
8876; GFX6-NEXT:    s_mov_b32 s11, s10
8877; GFX6-NEXT:    s_addc_u32 s1, s3, s10
8878; GFX6-NEXT:    s_xor_b64 s[0:1], s[0:1], s[10:11]
8879; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8880; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s6
8881; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
8882; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v2
8883; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v3
8884; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v2
8885; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v3
8886; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
8887; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v2
8888; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
8889; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
8890; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
8891; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
8892; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v6, vcc
8893; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v5, v4, vcc
8894; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8895; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
8896; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
8897; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
8898; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v1
8899; GFX6-NEXT:    v_mul_hi_u32 v3, s0, v0
8900; GFX6-NEXT:    v_mul_hi_u32 v5, s0, v1
8901; GFX6-NEXT:    v_mul_hi_u32 v6, s1, v1
8902; GFX6-NEXT:    v_mul_lo_u32 v1, s1, v1
8903; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8904; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
8905; GFX6-NEXT:    v_mul_lo_u32 v5, s1, v0
8906; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
8907; GFX6-NEXT:    s_movk_i32 s2, 0xfff
8908; GFX6-NEXT:    s_mov_b32 s6, -1
8909; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
8910; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
8911; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v6, v4, vcc
8912; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
8913; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
8914; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s2
8915; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s2
8916; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 2, v0
8917; GFX6-NEXT:    v_mul_lo_u32 v8, v0, s2
8918; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
8919; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v0
8920; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v1, vcc
8921; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
8922; GFX6-NEXT:    v_mov_b32_e32 v5, s1
8923; GFX6-NEXT:    v_sub_i32_e32 v8, vcc, s0, v8
8924; GFX6-NEXT:    v_subb_u32_e32 v4, vcc, v5, v4, vcc
8925; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s2, v8
8926; GFX6-NEXT:    v_subbrev_u32_e32 v9, vcc, 0, v4, vcc
8927; GFX6-NEXT:    s_movk_i32 s0, 0xffe
8928; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v5
8929; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
8930; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v9
8931; GFX6-NEXT:    v_cndmask_b32_e32 v5, -1, v5, vcc
8932; GFX6-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v8
8933; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
8934; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
8935; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v4
8936; GFX6-NEXT:    v_cndmask_b32_e64 v4, -1, v5, s[0:1]
8937; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
8938; GFX6-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
8939; GFX6-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
8940; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
8941; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
8942; GFX6-NEXT:    v_xor_b32_e32 v0, s10, v0
8943; GFX6-NEXT:    v_xor_b32_e32 v1, s10, v1
8944; GFX6-NEXT:    v_mov_b32_e32 v3, s10
8945; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s10, v0
8946; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v1, v3, vcc
8947; GFX6-NEXT:    v_mov_b32_e32 v0, s8
8948; GFX6-NEXT:    v_mov_b32_e32 v1, s9
8949; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
8950; GFX6-NEXT:    s_endpgm
8951;
8952; GFX9-LABEL: ssdiv_v2i64_mixed_pow2k_denom:
8953; GFX9:       ; %bb.0:
8954; GFX9-NEXT:    v_mov_b32_e32 v0, 0x457ff000
8955; GFX9-NEXT:    v_mov_b32_e32 v1, 0x4f800000
8956; GFX9-NEXT:    v_mac_f32_e32 v0, 0, v1
8957; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
8958; GFX9-NEXT:    s_movk_i32 s8, 0xf001
8959; GFX9-NEXT:    v_mov_b32_e32 v4, 0
8960; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
8961; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
8962; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
8963; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
8964; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
8965; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
8966; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
8967; GFX9-NEXT:    v_mul_hi_u32 v2, v0, s8
8968; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s8
8969; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s8
8970; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
8971; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
8972; GFX9-NEXT:    v_mul_lo_u32 v3, v0, v2
8973; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v5
8974; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
8975; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
8976; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
8977; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v6, v3
8978; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
8979; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v5
8980; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v5
8981; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
8982; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
8983; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v4, vcc
8984; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
8985; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
8986; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
8987; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
8988; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s8
8989; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s8
8990; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s8
8991; GFX9-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
8992; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8993; GFX9-NEXT:    s_ashr_i32 s2, s5, 31
8994; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
8995; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
8996; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v2
8997; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v5
8998; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v2
8999; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v5
9000; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
9001; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v2
9002; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
9003; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
9004; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
9005; GFX9-NEXT:    s_lshr_b32 s2, s2, 20
9006; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
9007; GFX9-NEXT:    s_add_u32 s2, s4, s2
9008; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v6, vcc
9009; GFX9-NEXT:    s_addc_u32 s3, s5, 0
9010; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
9011; GFX9-NEXT:    s_ashr_i64 s[2:3], s[2:3], 12
9012; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v5, v2
9013; GFX9-NEXT:    s_ashr_i32 s4, s7, 31
9014; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
9015; GFX9-NEXT:    s_add_u32 s6, s6, s4
9016; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
9017; GFX9-NEXT:    s_mov_b32 s5, s4
9018; GFX9-NEXT:    s_addc_u32 s7, s7, s4
9019; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
9020; GFX9-NEXT:    s_xor_b64 s[6:7], s[6:7], s[4:5]
9021; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
9022; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
9023; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v1
9024; GFX9-NEXT:    v_mul_hi_u32 v6, s7, v1
9025; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
9026; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
9027; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
9028; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v0
9029; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
9030; GFX9-NEXT:    s_movk_i32 s0, 0xfff
9031; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v5
9032; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
9033; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v4, vcc
9034; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
9035; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
9036; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, 2, v0
9037; GFX9-NEXT:    v_mul_lo_u32 v5, v1, s0
9038; GFX9-NEXT:    v_mul_hi_u32 v6, v0, s0
9039; GFX9-NEXT:    v_mul_lo_u32 v9, v0, s0
9040; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
9041; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, 1, v0
9042; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v1, vcc
9043; GFX9-NEXT:    v_add_u32_e32 v5, v6, v5
9044; GFX9-NEXT:    v_mov_b32_e32 v6, s7
9045; GFX9-NEXT:    v_sub_co_u32_e32 v9, vcc, s6, v9
9046; GFX9-NEXT:    v_subb_co_u32_e32 v5, vcc, v6, v5, vcc
9047; GFX9-NEXT:    v_subrev_co_u32_e32 v6, vcc, s0, v9
9048; GFX9-NEXT:    v_subbrev_co_u32_e32 v10, vcc, 0, v5, vcc
9049; GFX9-NEXT:    s_movk_i32 s0, 0xffe
9050; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v6
9051; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
9052; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v10
9053; GFX9-NEXT:    v_cndmask_b32_e32 v6, -1, v6, vcc
9054; GFX9-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v9
9055; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
9056; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
9057; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v5
9058; GFX9-NEXT:    v_cndmask_b32_e64 v5, -1, v6, s[0:1]
9059; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
9060; GFX9-NEXT:    v_cndmask_b32_e32 v2, v7, v2, vcc
9061; GFX9-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
9062; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
9063; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
9064; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v0
9065; GFX9-NEXT:    v_xor_b32_e32 v1, s4, v1
9066; GFX9-NEXT:    v_mov_b32_e32 v3, s4
9067; GFX9-NEXT:    v_subrev_co_u32_e32 v2, vcc, s4, v0
9068; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v1, v3, vcc
9069; GFX9-NEXT:    v_mov_b32_e32 v0, s2
9070; GFX9-NEXT:    v_mov_b32_e32 v1, s3
9071; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[8:9]
9072; GFX9-NEXT:    s_endpgm
9073  %r = sdiv <2 x i64> %x, <i64 4096, i64 4095>
9074  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
9075  ret void
9076}
9077
9078define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
9079; CHECK-LABEL: @sdiv_v2i64_pow2_shl_denom(
9080; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.*]]
9081; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
9082; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 0
9083; CHECK-NEXT:    [[TMP3:%.*]] = sdiv i64 [[TMP1]], [[TMP2]]
9084; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i64 0
9085; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 1
9086; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
9087; CHECK-NEXT:    [[TMP7:%.*]] = sdiv i64 [[TMP5]], [[TMP6]]
9088; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
9089; CHECK-NEXT:    store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
9090; CHECK-NEXT:    ret void
9091;
9092; GFX6-LABEL: sdiv_v2i64_pow2_shl_denom:
9093; GFX6:       ; %bb.0:
9094; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x11
9095; GFX6-NEXT:    s_mov_b64 s[2:3], 0x1000
9096; GFX6-NEXT:    s_mov_b32 s18, 0x4f800000
9097; GFX6-NEXT:    s_mov_b32 s19, 0x5f7ffffc
9098; GFX6-NEXT:    s_mov_b32 s20, 0x2f800000
9099; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
9100; GFX6-NEXT:    s_lshl_b64 s[8:9], s[2:3], s6
9101; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
9102; GFX6-NEXT:    s_ashr_i32 s12, s3, 31
9103; GFX6-NEXT:    s_add_u32 s2, s2, s12
9104; GFX6-NEXT:    s_mov_b32 s13, s12
9105; GFX6-NEXT:    s_addc_u32 s3, s3, s12
9106; GFX6-NEXT:    s_xor_b64 s[10:11], s[2:3], s[12:13]
9107; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s10
9108; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s11
9109; GFX6-NEXT:    s_mov_b32 s21, 0xcf800000
9110; GFX6-NEXT:    s_sub_u32 s6, 0, s10
9111; GFX6-NEXT:    s_subb_u32 s7, 0, s11
9112; GFX6-NEXT:    v_mac_f32_e32 v0, s18, v1
9113; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
9114; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
9115; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
9116; GFX6-NEXT:    v_mul_f32_e32 v0, s19, v0
9117; GFX6-NEXT:    v_mul_f32_e32 v1, s20, v0
9118; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
9119; GFX6-NEXT:    v_mac_f32_e32 v0, s21, v1
9120; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
9121; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v0
9122; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
9123; GFX6-NEXT:    s_ashr_i32 s14, s1, 31
9124; GFX6-NEXT:    s_add_u32 s0, s0, s14
9125; GFX6-NEXT:    v_mul_lo_u32 v0, s6, v1
9126; GFX6-NEXT:    v_mul_hi_u32 v3, s6, v2
9127; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v2
9128; GFX6-NEXT:    v_mul_lo_u32 v5, s6, v2
9129; GFX6-NEXT:    s_mov_b32 s15, s14
9130; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
9131; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v0, v4
9132; GFX6-NEXT:    v_mul_lo_u32 v0, v2, v3
9133; GFX6-NEXT:    v_mul_hi_u32 v4, v2, v5
9134; GFX6-NEXT:    v_mul_hi_u32 v6, v2, v3
9135; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v3
9136; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
9137; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v4, v0
9138; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v6, vcc
9139; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v5
9140; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v5
9141; GFX6-NEXT:    s_addc_u32 s1, s1, s14
9142; GFX6-NEXT:    s_xor_b64 s[16:17], s[0:1], s[14:15]
9143; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
9144; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v4, v5, vcc
9145; GFX6-NEXT:    v_mov_b32_e32 v0, 0
9146; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v0, vcc
9147; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
9148; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
9149; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
9150; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
9151; GFX6-NEXT:    v_mul_lo_u32 v3, s6, v1
9152; GFX6-NEXT:    v_mul_hi_u32 v4, s6, v2
9153; GFX6-NEXT:    v_mul_lo_u32 v5, s7, v2
9154; GFX6-NEXT:    s_xor_b64 s[14:15], s[14:15], s[12:13]
9155; GFX6-NEXT:    s_ashr_i32 s12, s9, 31
9156; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
9157; GFX6-NEXT:    v_mul_lo_u32 v4, s6, v2
9158; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
9159; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v3
9160; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v4
9161; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v3
9162; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v4
9163; GFX6-NEXT:    v_mul_lo_u32 v4, v1, v4
9164; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v3
9165; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
9166; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
9167; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
9168; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
9169; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
9170; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v5, v0, vcc
9171; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
9172; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
9173; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
9174; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
9175; GFX6-NEXT:    v_mul_lo_u32 v3, s16, v1
9176; GFX6-NEXT:    v_mul_hi_u32 v4, s16, v2
9177; GFX6-NEXT:    v_mul_hi_u32 v5, s16, v1
9178; GFX6-NEXT:    v_mul_hi_u32 v6, s17, v1
9179; GFX6-NEXT:    v_mul_lo_u32 v1, s17, v1
9180; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
9181; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
9182; GFX6-NEXT:    v_mul_lo_u32 v5, s17, v2
9183; GFX6-NEXT:    v_mul_hi_u32 v2, s17, v2
9184; GFX6-NEXT:    s_add_u32 s8, s8, s12
9185; GFX6-NEXT:    s_mov_b32 s13, s12
9186; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
9187; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v4, v2, vcc
9188; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v0, vcc
9189; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
9190; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
9191; GFX6-NEXT:    v_mul_lo_u32 v3, s10, v2
9192; GFX6-NEXT:    v_mul_hi_u32 v4, s10, v1
9193; GFX6-NEXT:    v_mul_lo_u32 v5, s11, v1
9194; GFX6-NEXT:    v_mov_b32_e32 v6, s11
9195; GFX6-NEXT:    s_addc_u32 s9, s9, s12
9196; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
9197; GFX6-NEXT:    v_mul_lo_u32 v4, s10, v1
9198; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
9199; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s17, v3
9200; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s16, v4
9201; GFX6-NEXT:    v_subb_u32_e64 v5, s[0:1], v5, v6, vcc
9202; GFX6-NEXT:    v_subrev_i32_e64 v6, s[0:1], s10, v4
9203; GFX6-NEXT:    v_subbrev_u32_e64 v5, s[0:1], 0, v5, s[0:1]
9204; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v5
9205; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
9206; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v6
9207; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
9208; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v5
9209; GFX6-NEXT:    v_cndmask_b32_e64 v5, v7, v6, s[0:1]
9210; GFX6-NEXT:    v_add_i32_e64 v6, s[0:1], 2, v1
9211; GFX6-NEXT:    v_addc_u32_e64 v7, s[0:1], 0, v2, s[0:1]
9212; GFX6-NEXT:    v_add_i32_e64 v8, s[0:1], 1, v1
9213; GFX6-NEXT:    v_addc_u32_e64 v9, s[0:1], 0, v2, s[0:1]
9214; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
9215; GFX6-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
9216; GFX6-NEXT:    v_cndmask_b32_e64 v5, v9, v7, s[0:1]
9217; GFX6-NEXT:    v_mov_b32_e32 v7, s17
9218; GFX6-NEXT:    v_cvt_f32_u32_e32 v9, s8
9219; GFX6-NEXT:    v_cvt_f32_u32_e32 v10, s9
9220; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v7, v3, vcc
9221; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
9222; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
9223; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v4
9224; GFX6-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
9225; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v3
9226; GFX6-NEXT:    v_mac_f32_e32 v9, s18, v10
9227; GFX6-NEXT:    v_cndmask_b32_e32 v3, v7, v4, vcc
9228; GFX6-NEXT:    v_rcp_f32_e32 v4, v9
9229; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
9230; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
9231; GFX6-NEXT:    v_cndmask_b32_e64 v3, v8, v6, s[0:1]
9232; GFX6-NEXT:    v_mul_f32_e32 v4, s19, v4
9233; GFX6-NEXT:    v_mul_f32_e32 v5, s20, v4
9234; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
9235; GFX6-NEXT:    v_mac_f32_e32 v4, s21, v5
9236; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
9237; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v5
9238; GFX6-NEXT:    s_sub_u32 s0, 0, s8
9239; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
9240; GFX6-NEXT:    v_mul_hi_u32 v3, s0, v4
9241; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v5
9242; GFX6-NEXT:    s_subb_u32 s1, 0, s9
9243; GFX6-NEXT:    v_mul_lo_u32 v7, s1, v4
9244; GFX6-NEXT:    s_ashr_i32 s10, s3, 31
9245; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
9246; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v4
9247; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
9248; GFX6-NEXT:    v_mul_lo_u32 v7, v4, v3
9249; GFX6-NEXT:    v_mul_hi_u32 v8, v4, v6
9250; GFX6-NEXT:    v_mul_hi_u32 v9, v4, v3
9251; GFX6-NEXT:    v_mul_hi_u32 v10, v5, v3
9252; GFX6-NEXT:    v_mul_lo_u32 v3, v5, v3
9253; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
9254; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
9255; GFX6-NEXT:    v_mul_lo_u32 v9, v5, v6
9256; GFX6-NEXT:    v_mul_hi_u32 v6, v5, v6
9257; GFX6-NEXT:    s_mov_b32 s11, s10
9258; GFX6-NEXT:    v_xor_b32_e32 v1, s14, v1
9259; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
9260; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v8, v6, vcc
9261; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v10, v0, vcc
9262; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
9263; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
9264; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
9265; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v5, v6, vcc
9266; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v4
9267; GFX6-NEXT:    v_mul_hi_u32 v6, s0, v3
9268; GFX6-NEXT:    v_mul_lo_u32 v7, s1, v3
9269; GFX6-NEXT:    v_xor_b32_e32 v2, s15, v2
9270; GFX6-NEXT:    s_mov_b32 s7, 0xf000
9271; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
9272; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v3
9273; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
9274; GFX6-NEXT:    v_mul_lo_u32 v9, v3, v5
9275; GFX6-NEXT:    v_mul_hi_u32 v10, v3, v6
9276; GFX6-NEXT:    v_mul_hi_u32 v11, v3, v5
9277; GFX6-NEXT:    v_mul_hi_u32 v8, v4, v6
9278; GFX6-NEXT:    v_mul_lo_u32 v6, v4, v6
9279; GFX6-NEXT:    v_mul_hi_u32 v7, v4, v5
9280; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
9281; GFX6-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
9282; GFX6-NEXT:    v_mul_lo_u32 v5, v4, v5
9283; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
9284; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v10, v8, vcc
9285; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v7, v0, vcc
9286; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
9287; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
9288; GFX6-NEXT:    s_add_u32 s0, s2, s10
9289; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
9290; GFX6-NEXT:    s_addc_u32 s1, s3, s10
9291; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
9292; GFX6-NEXT:    s_xor_b64 s[2:3], s[0:1], s[10:11]
9293; GFX6-NEXT:    v_mul_lo_u32 v5, s2, v4
9294; GFX6-NEXT:    v_mul_hi_u32 v6, s2, v3
9295; GFX6-NEXT:    v_mul_hi_u32 v8, s2, v4
9296; GFX6-NEXT:    v_mul_hi_u32 v9, s3, v4
9297; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v4
9298; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
9299; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
9300; GFX6-NEXT:    v_mul_lo_u32 v8, s3, v3
9301; GFX6-NEXT:    v_mul_hi_u32 v3, s3, v3
9302; GFX6-NEXT:    v_mov_b32_e32 v7, s15
9303; GFX6-NEXT:    s_mov_b32 s6, -1
9304; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
9305; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v3, vcc
9306; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v9, v0, vcc
9307; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
9308; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v0, vcc
9309; GFX6-NEXT:    v_mul_lo_u32 v5, s8, v4
9310; GFX6-NEXT:    v_mul_hi_u32 v6, s8, v3
9311; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s14, v1
9312; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v2, v7, vcc
9313; GFX6-NEXT:    v_mul_lo_u32 v2, s9, v3
9314; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
9315; GFX6-NEXT:    v_mov_b32_e32 v7, s9
9316; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
9317; GFX6-NEXT:    v_mul_lo_u32 v5, s8, v3
9318; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, s3, v2
9319; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s2, v5
9320; GFX6-NEXT:    v_subb_u32_e64 v6, s[0:1], v6, v7, vcc
9321; GFX6-NEXT:    v_subrev_i32_e64 v7, s[0:1], s8, v5
9322; GFX6-NEXT:    v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1]
9323; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v6
9324; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[0:1]
9325; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v7
9326; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
9327; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v6
9328; GFX6-NEXT:    v_cndmask_b32_e64 v6, v8, v7, s[0:1]
9329; GFX6-NEXT:    v_add_i32_e64 v7, s[0:1], 2, v3
9330; GFX6-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v4, s[0:1]
9331; GFX6-NEXT:    v_add_i32_e64 v9, s[0:1], 1, v3
9332; GFX6-NEXT:    v_addc_u32_e64 v10, s[0:1], 0, v4, s[0:1]
9333; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
9334; GFX6-NEXT:    v_cndmask_b32_e64 v6, v10, v8, s[0:1]
9335; GFX6-NEXT:    v_mov_b32_e32 v8, s3
9336; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v8, v2, vcc
9337; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
9338; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
9339; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v5
9340; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
9341; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v2
9342; GFX6-NEXT:    v_cndmask_b32_e32 v2, v8, v5, vcc
9343; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
9344; GFX6-NEXT:    v_cndmask_b32_e32 v2, v4, v6, vcc
9345; GFX6-NEXT:    v_cndmask_b32_e64 v4, v9, v7, s[0:1]
9346; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
9347; GFX6-NEXT:    s_xor_b64 s[0:1], s[10:11], s[12:13]
9348; GFX6-NEXT:    v_xor_b32_e32 v3, s0, v3
9349; GFX6-NEXT:    v_xor_b32_e32 v4, s1, v2
9350; GFX6-NEXT:    v_mov_b32_e32 v5, s1
9351; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s0, v3
9352; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v4, v5, vcc
9353; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
9354; GFX6-NEXT:    s_endpgm
9355;
9356; GFX9-LABEL: sdiv_v2i64_pow2_shl_denom:
9357; GFX9:       ; %bb.0:
9358; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x44
9359; GFX9-NEXT:    s_mov_b64 s[2:3], 0x1000
9360; GFX9-NEXT:    s_mov_b32 s16, 0x4f800000
9361; GFX9-NEXT:    s_mov_b32 s17, 0x5f7ffffc
9362; GFX9-NEXT:    s_mov_b32 s18, 0x2f800000
9363; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
9364; GFX9-NEXT:    s_lshl_b64 s[8:9], s[2:3], s6
9365; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
9366; GFX9-NEXT:    s_ashr_i32 s12, s3, 31
9367; GFX9-NEXT:    s_add_u32 s2, s2, s12
9368; GFX9-NEXT:    s_mov_b32 s13, s12
9369; GFX9-NEXT:    s_addc_u32 s3, s3, s12
9370; GFX9-NEXT:    s_xor_b64 s[10:11], s[2:3], s[12:13]
9371; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s10
9372; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s11
9373; GFX9-NEXT:    s_mov_b32 s19, 0xcf800000
9374; GFX9-NEXT:    s_sub_u32 s2, 0, s10
9375; GFX9-NEXT:    s_subb_u32 s3, 0, s11
9376; GFX9-NEXT:    v_mac_f32_e32 v0, s16, v1
9377; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
9378; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
9379; GFX9-NEXT:    v_mul_f32_e32 v0, s17, v0
9380; GFX9-NEXT:    v_mul_f32_e32 v1, s18, v0
9381; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
9382; GFX9-NEXT:    v_mac_f32_e32 v0, s19, v1
9383; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
9384; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v0
9385; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
9386; GFX9-NEXT:    s_ashr_i32 s14, s5, 31
9387; GFX9-NEXT:    s_mov_b32 s15, s14
9388; GFX9-NEXT:    v_mul_lo_u32 v0, s2, v1
9389; GFX9-NEXT:    v_mul_hi_u32 v3, s2, v2
9390; GFX9-NEXT:    v_mul_lo_u32 v5, s3, v2
9391; GFX9-NEXT:    v_mul_lo_u32 v4, s2, v2
9392; GFX9-NEXT:    v_add_u32_e32 v0, v3, v0
9393; GFX9-NEXT:    v_add_u32_e32 v5, v0, v5
9394; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v4
9395; GFX9-NEXT:    v_mul_lo_u32 v6, v2, v5
9396; GFX9-NEXT:    v_mul_hi_u32 v7, v2, v5
9397; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v5
9398; GFX9-NEXT:    v_mov_b32_e32 v0, 0
9399; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
9400; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
9401; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
9402; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
9403; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
9404; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
9405; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v5
9406; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v0, vcc
9407; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v4
9408; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
9409; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
9410; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
9411; GFX9-NEXT:    v_mul_lo_u32 v3, s2, v1
9412; GFX9-NEXT:    v_mul_hi_u32 v4, s2, v2
9413; GFX9-NEXT:    v_mul_lo_u32 v5, s3, v2
9414; GFX9-NEXT:    v_mul_lo_u32 v6, s2, v2
9415; GFX9-NEXT:    s_add_u32 s2, s4, s14
9416; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
9417; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
9418; GFX9-NEXT:    v_mul_lo_u32 v7, v2, v3
9419; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v6
9420; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v3
9421; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v6
9422; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
9423; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v3
9424; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
9425; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
9426; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
9427; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
9428; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v5, vcc
9429; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v0, vcc
9430; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
9431; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
9432; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
9433; GFX9-NEXT:    s_addc_u32 s3, s5, s14
9434; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
9435; GFX9-NEXT:    s_xor_b64 s[4:5], s[2:3], s[14:15]
9436; GFX9-NEXT:    v_mul_lo_u32 v3, s4, v1
9437; GFX9-NEXT:    v_mul_hi_u32 v4, s4, v2
9438; GFX9-NEXT:    v_mul_hi_u32 v5, s4, v1
9439; GFX9-NEXT:    v_mul_hi_u32 v6, s5, v1
9440; GFX9-NEXT:    v_mul_lo_u32 v1, s5, v1
9441; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
9442; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
9443; GFX9-NEXT:    v_mul_lo_u32 v5, s5, v2
9444; GFX9-NEXT:    v_mul_hi_u32 v2, s5, v2
9445; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
9446; GFX9-NEXT:    s_xor_b64 s[12:13], s[14:15], s[12:13]
9447; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
9448; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v4, v2, vcc
9449; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v0, vcc
9450; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v2, v1
9451; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v3, vcc
9452; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v2
9453; GFX9-NEXT:    v_mul_hi_u32 v4, s10, v1
9454; GFX9-NEXT:    v_mul_lo_u32 v5, s11, v1
9455; GFX9-NEXT:    v_mov_b32_e32 v6, s11
9456; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
9457; GFX9-NEXT:    v_mul_lo_u32 v4, s10, v1
9458; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
9459; GFX9-NEXT:    v_sub_u32_e32 v5, s5, v3
9460; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, s4, v4
9461; GFX9-NEXT:    v_subb_co_u32_e64 v5, s[0:1], v5, v6, vcc
9462; GFX9-NEXT:    v_subrev_co_u32_e64 v6, s[0:1], s10, v4
9463; GFX9-NEXT:    v_subbrev_co_u32_e64 v5, s[0:1], 0, v5, s[0:1]
9464; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v5
9465; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
9466; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v6
9467; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
9468; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v5
9469; GFX9-NEXT:    v_cndmask_b32_e64 v5, v7, v6, s[0:1]
9470; GFX9-NEXT:    v_add_co_u32_e64 v6, s[0:1], 2, v1
9471; GFX9-NEXT:    v_addc_co_u32_e64 v7, s[0:1], 0, v2, s[0:1]
9472; GFX9-NEXT:    v_add_co_u32_e64 v8, s[0:1], 1, v1
9473; GFX9-NEXT:    v_addc_co_u32_e64 v9, s[0:1], 0, v2, s[0:1]
9474; GFX9-NEXT:    s_ashr_i32 s4, s9, 31
9475; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
9476; GFX9-NEXT:    s_add_u32 s8, s8, s4
9477; GFX9-NEXT:    v_cndmask_b32_e64 v5, v9, v7, s[0:1]
9478; GFX9-NEXT:    v_mov_b32_e32 v7, s5
9479; GFX9-NEXT:    s_mov_b32 s5, s4
9480; GFX9-NEXT:    s_addc_u32 s9, s9, s4
9481; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[4:5]
9482; GFX9-NEXT:    v_cvt_f32_u32_e32 v9, s8
9483; GFX9-NEXT:    v_cvt_f32_u32_e32 v10, s9
9484; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v7, v3, vcc
9485; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
9486; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
9487; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v4
9488; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
9489; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v3
9490; GFX9-NEXT:    v_mac_f32_e32 v9, s16, v10
9491; GFX9-NEXT:    v_cndmask_b32_e32 v3, v7, v4, vcc
9492; GFX9-NEXT:    v_rcp_f32_e32 v4, v9
9493; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
9494; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
9495; GFX9-NEXT:    v_cndmask_b32_e64 v3, v8, v6, s[0:1]
9496; GFX9-NEXT:    v_mul_f32_e32 v4, s17, v4
9497; GFX9-NEXT:    v_mul_f32_e32 v5, s18, v4
9498; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
9499; GFX9-NEXT:    v_mac_f32_e32 v4, s19, v5
9500; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
9501; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
9502; GFX9-NEXT:    s_sub_u32 s0, 0, s8
9503; GFX9-NEXT:    s_subb_u32 s1, 0, s9
9504; GFX9-NEXT:    v_mul_hi_u32 v6, s0, v4
9505; GFX9-NEXT:    v_mul_lo_u32 v7, s0, v5
9506; GFX9-NEXT:    v_mul_lo_u32 v8, s1, v4
9507; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
9508; GFX9-NEXT:    v_mul_lo_u32 v3, s0, v4
9509; GFX9-NEXT:    v_add_u32_e32 v6, v6, v7
9510; GFX9-NEXT:    v_add_u32_e32 v6, v6, v8
9511; GFX9-NEXT:    v_mul_lo_u32 v7, v4, v6
9512; GFX9-NEXT:    v_mul_hi_u32 v8, v4, v3
9513; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v6
9514; GFX9-NEXT:    v_mul_hi_u32 v10, v5, v6
9515; GFX9-NEXT:    v_mul_lo_u32 v6, v5, v6
9516; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
9517; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
9518; GFX9-NEXT:    v_mul_lo_u32 v9, v5, v3
9519; GFX9-NEXT:    v_mul_hi_u32 v3, v5, v3
9520; GFX9-NEXT:    s_ashr_i32 s10, s7, 31
9521; GFX9-NEXT:    s_mov_b32 s11, s10
9522; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v9
9523; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v8, v3, vcc
9524; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v10, v0, vcc
9525; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
9526; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
9527; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
9528; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v6, vcc
9529; GFX9-NEXT:    v_mul_lo_u32 v5, s0, v4
9530; GFX9-NEXT:    v_mul_hi_u32 v6, s0, v3
9531; GFX9-NEXT:    v_mul_lo_u32 v7, s1, v3
9532; GFX9-NEXT:    v_mul_lo_u32 v8, s0, v3
9533; GFX9-NEXT:    s_add_u32 s0, s6, s10
9534; GFX9-NEXT:    v_add_u32_e32 v5, v6, v5
9535; GFX9-NEXT:    v_add_u32_e32 v5, v5, v7
9536; GFX9-NEXT:    v_mul_lo_u32 v9, v3, v5
9537; GFX9-NEXT:    v_mul_hi_u32 v10, v3, v8
9538; GFX9-NEXT:    v_mul_hi_u32 v11, v3, v5
9539; GFX9-NEXT:    v_mul_hi_u32 v7, v4, v8
9540; GFX9-NEXT:    v_mul_lo_u32 v8, v4, v8
9541; GFX9-NEXT:    v_mul_hi_u32 v6, v4, v5
9542; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
9543; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
9544; GFX9-NEXT:    v_mul_lo_u32 v5, v4, v5
9545; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
9546; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v10, v7, vcc
9547; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v6, v0, vcc
9548; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
9549; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
9550; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
9551; GFX9-NEXT:    s_addc_u32 s1, s7, s10
9552; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v6, vcc
9553; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[10:11]
9554; GFX9-NEXT:    v_mul_lo_u32 v5, s6, v4
9555; GFX9-NEXT:    v_mul_hi_u32 v6, s6, v3
9556; GFX9-NEXT:    v_mul_hi_u32 v8, s6, v4
9557; GFX9-NEXT:    v_mul_hi_u32 v9, s7, v4
9558; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v4
9559; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v6, v5
9560; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
9561; GFX9-NEXT:    v_mul_lo_u32 v8, s7, v3
9562; GFX9-NEXT:    v_mul_hi_u32 v3, s7, v3
9563; GFX9-NEXT:    v_xor_b32_e32 v1, s12, v1
9564; GFX9-NEXT:    v_xor_b32_e32 v2, s13, v2
9565; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v8
9566; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
9567; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v0, vcc
9568; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v4
9569; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
9570; GFX9-NEXT:    v_mul_lo_u32 v5, s8, v4
9571; GFX9-NEXT:    v_mul_hi_u32 v6, s8, v3
9572; GFX9-NEXT:    v_mul_lo_u32 v8, s9, v3
9573; GFX9-NEXT:    v_mov_b32_e32 v7, s13
9574; GFX9-NEXT:    v_subrev_co_u32_e32 v1, vcc, s12, v1
9575; GFX9-NEXT:    v_add_u32_e32 v5, v6, v5
9576; GFX9-NEXT:    v_mul_lo_u32 v6, s8, v3
9577; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v2, v7, vcc
9578; GFX9-NEXT:    v_add_u32_e32 v5, v5, v8
9579; GFX9-NEXT:    v_sub_u32_e32 v7, s7, v5
9580; GFX9-NEXT:    v_mov_b32_e32 v8, s9
9581; GFX9-NEXT:    v_sub_co_u32_e32 v6, vcc, s6, v6
9582; GFX9-NEXT:    v_subb_co_u32_e64 v7, s[0:1], v7, v8, vcc
9583; GFX9-NEXT:    v_subrev_co_u32_e64 v8, s[0:1], s8, v6
9584; GFX9-NEXT:    v_subbrev_co_u32_e64 v7, s[0:1], 0, v7, s[0:1]
9585; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v7
9586; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[0:1]
9587; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v8
9588; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[0:1]
9589; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v7
9590; GFX9-NEXT:    v_cndmask_b32_e64 v7, v9, v8, s[0:1]
9591; GFX9-NEXT:    v_add_co_u32_e64 v8, s[0:1], 2, v3
9592; GFX9-NEXT:    v_addc_co_u32_e64 v9, s[0:1], 0, v4, s[0:1]
9593; GFX9-NEXT:    v_add_co_u32_e64 v10, s[0:1], 1, v3
9594; GFX9-NEXT:    v_addc_co_u32_e64 v11, s[0:1], 0, v4, s[0:1]
9595; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v7
9596; GFX9-NEXT:    v_cndmask_b32_e64 v7, v11, v9, s[0:1]
9597; GFX9-NEXT:    v_mov_b32_e32 v9, s7
9598; GFX9-NEXT:    v_subb_co_u32_e32 v5, vcc, v9, v5, vcc
9599; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v5
9600; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
9601; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v6
9602; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
9603; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v5
9604; GFX9-NEXT:    v_cndmask_b32_e32 v5, v9, v6, vcc
9605; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
9606; GFX9-NEXT:    v_cndmask_b32_e64 v5, v10, v8, s[0:1]
9607; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
9608; GFX9-NEXT:    s_xor_b64 s[0:1], s[10:11], s[4:5]
9609; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v7, vcc
9610; GFX9-NEXT:    v_xor_b32_e32 v3, s0, v3
9611; GFX9-NEXT:    v_xor_b32_e32 v4, s1, v4
9612; GFX9-NEXT:    v_mov_b32_e32 v5, s1
9613; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s0, v3
9614; GFX9-NEXT:    v_subb_co_u32_e32 v4, vcc, v4, v5, vcc
9615; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
9616; GFX9-NEXT:    global_store_dwordx4 v0, v[1:4], s[2:3]
9617; GFX9-NEXT:    s_endpgm
9618  %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
9619  %r = sdiv <2 x i64> %x, %shl.y
9620  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
9621  ret void
9622}
9623
9624define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
9625; CHECK-LABEL: @srem_i64_oddk_denom(
9626; CHECK-NEXT:    [[R:%.*]] = srem i64 [[X:%.*]], 1235195
9627; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
9628; CHECK-NEXT:    ret void
9629;
9630; GFX6-LABEL: srem_i64_oddk_denom:
9631; GFX6:       ; %bb.0:
9632; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f800000
9633; GFX6-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
9634; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
9635; GFX6-NEXT:    s_mov_b32 s4, 0xffed2705
9636; GFX6-NEXT:    v_mov_b32_e32 v5, 0
9637; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
9638; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
9639; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
9640; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
9641; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
9642; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
9643; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
9644; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
9645; GFX6-NEXT:    s_ashr_i32 s8, s3, 31
9646; GFX6-NEXT:    s_add_u32 s2, s2, s8
9647; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s4
9648; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s4
9649; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s4
9650; GFX6-NEXT:    s_mov_b32 s9, s8
9651; GFX6-NEXT:    s_addc_u32 s3, s3, s8
9652; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9653; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
9654; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
9655; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v2
9656; GFX6-NEXT:    v_mul_hi_u32 v7, v0, v2
9657; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
9658; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
9659; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
9660; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
9661; GFX6-NEXT:    v_mul_lo_u32 v7, v1, v4
9662; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
9663; GFX6-NEXT:    s_xor_b64 s[2:3], s[2:3], s[8:9]
9664; GFX6-NEXT:    s_mov_b32 s5, s1
9665; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
9666; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v4, vcc
9667; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v5, vcc
9668; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9669; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
9670; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
9671; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
9672; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s4
9673; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s4
9674; GFX6-NEXT:    s_mov_b32 s7, 0xf000
9675; GFX6-NEXT:    s_mov_b32 s6, -1
9676; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9677; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s4
9678; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
9679; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v2
9680; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v3
9681; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v2
9682; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v3
9683; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
9684; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v2
9685; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
9686; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
9687; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
9688; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
9689; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v6, vcc
9690; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v4, v5, vcc
9691; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9692; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
9693; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
9694; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
9695; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
9696; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
9697; GFX6-NEXT:    v_mul_hi_u32 v4, s2, v1
9698; GFX6-NEXT:    v_mul_hi_u32 v6, s3, v1
9699; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v1
9700; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9701; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
9702; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v0
9703; GFX6-NEXT:    v_mul_hi_u32 v0, s3, v0
9704; GFX6-NEXT:    s_mov_b32 s4, s0
9705; GFX6-NEXT:    s_mov_b32 s0, 0x12d8fb
9706; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
9707; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
9708; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v6, v5, vcc
9709; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
9710; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
9711; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s0
9712; GFX6-NEXT:    v_mul_hi_u32 v2, v0, s0
9713; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s0
9714; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
9715; GFX6-NEXT:    v_mov_b32_e32 v2, s3
9716; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
9717; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
9718; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s0, v0
9719; GFX6-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v1, vcc
9720; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s0, v2
9721; GFX6-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v3, vcc
9722; GFX6-NEXT:    s_mov_b32 s0, 0x12d8fa
9723; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v2
9724; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
9725; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
9726; GFX6-NEXT:    v_cndmask_b32_e32 v6, -1, v6, vcc
9727; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
9728; GFX6-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v0
9729; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
9730; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
9731; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
9732; GFX6-NEXT:    v_cndmask_b32_e64 v5, -1, v5, s[0:1]
9733; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
9734; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
9735; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
9736; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
9737; GFX6-NEXT:    v_xor_b32_e32 v0, s8, v0
9738; GFX6-NEXT:    v_xor_b32_e32 v1, s8, v1
9739; GFX6-NEXT:    v_mov_b32_e32 v2, s8
9740; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v0
9741; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
9742; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
9743; GFX6-NEXT:    s_endpgm
9744;
9745; GFX9-LABEL: srem_i64_oddk_denom:
9746; GFX9:       ; %bb.0:
9747; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f800000
9748; GFX9-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
9749; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
9750; GFX9-NEXT:    s_mov_b32 s2, 0xffed2705
9751; GFX9-NEXT:    v_mov_b32_e32 v5, 0
9752; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
9753; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
9754; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
9755; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
9756; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
9757; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
9758; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
9759; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s2
9760; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s2
9761; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s2
9762; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
9763; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
9764; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
9765; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
9766; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
9767; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
9768; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
9769; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
9770; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
9771; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
9772; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
9773; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
9774; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
9775; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
9776; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
9777; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
9778; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
9779; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
9780; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s2
9781; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s2
9782; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s2
9783; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
9784; GFX9-NEXT:    s_ashr_i32 s2, s7, 31
9785; GFX9-NEXT:    s_add_u32 s0, s6, s2
9786; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
9787; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
9788; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v2
9789; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v4
9790; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v2
9791; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v4
9792; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v4
9793; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v2
9794; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
9795; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
9796; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
9797; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v7, v4
9798; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
9799; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v5, vcc
9800; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
9801; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
9802; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
9803; GFX9-NEXT:    s_mov_b32 s3, s2
9804; GFX9-NEXT:    s_addc_u32 s1, s7, s2
9805; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
9806; GFX9-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
9807; GFX9-NEXT:    v_mul_lo_u32 v2, s0, v1
9808; GFX9-NEXT:    v_mul_hi_u32 v3, s0, v0
9809; GFX9-NEXT:    v_mul_hi_u32 v4, s0, v1
9810; GFX9-NEXT:    v_mul_hi_u32 v6, s1, v1
9811; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v1
9812; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
9813; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
9814; GFX9-NEXT:    v_mul_lo_u32 v4, s1, v0
9815; GFX9-NEXT:    v_mul_hi_u32 v0, s1, v0
9816; GFX9-NEXT:    s_mov_b32 s3, 0x12d8fb
9817; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
9818; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
9819; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
9820; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
9821; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
9822; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s3
9823; GFX9-NEXT:    v_mul_hi_u32 v2, v0, s3
9824; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
9825; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
9826; GFX9-NEXT:    v_mov_b32_e32 v2, s1
9827; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, s0, v0
9828; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v2, v1, vcc
9829; GFX9-NEXT:    v_subrev_co_u32_e32 v2, vcc, s3, v0
9830; GFX9-NEXT:    v_subbrev_co_u32_e32 v3, vcc, 0, v1, vcc
9831; GFX9-NEXT:    v_subrev_co_u32_e32 v4, vcc, s3, v2
9832; GFX9-NEXT:    v_subbrev_co_u32_e32 v6, vcc, 0, v3, vcc
9833; GFX9-NEXT:    s_mov_b32 s0, 0x12d8fa
9834; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v2
9835; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
9836; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
9837; GFX9-NEXT:    v_cndmask_b32_e32 v7, -1, v7, vcc
9838; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
9839; GFX9-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v0
9840; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
9841; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
9842; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
9843; GFX9-NEXT:    v_cndmask_b32_e64 v6, -1, v6, s[0:1]
9844; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
9845; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
9846; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
9847; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
9848; GFX9-NEXT:    v_xor_b32_e32 v0, s2, v0
9849; GFX9-NEXT:    v_xor_b32_e32 v1, s2, v1
9850; GFX9-NEXT:    v_mov_b32_e32 v2, s2
9851; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s2, v0
9852; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
9853; GFX9-NEXT:    global_store_dwordx2 v5, v[0:1], s[4:5]
9854; GFX9-NEXT:    s_endpgm
9855  %r = srem i64 %x, 1235195
9856  store i64 %r, i64 addrspace(1)* %out
9857  ret void
9858}
9859
9860define amdgpu_kernel void @srem_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) {
9861; CHECK-LABEL: @srem_i64_pow2k_denom(
9862; CHECK-NEXT:    [[R:%.*]] = srem i64 [[X:%.*]], 4096
9863; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
9864; CHECK-NEXT:    ret void
9865;
9866; GFX6-LABEL: srem_i64_pow2k_denom:
9867; GFX6:       ; %bb.0:
9868; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
9869; GFX6-NEXT:    s_mov_b32 s7, 0xf000
9870; GFX6-NEXT:    s_mov_b32 s6, -1
9871; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
9872; GFX6-NEXT:    s_mov_b32 s4, s0
9873; GFX6-NEXT:    s_ashr_i32 s0, s3, 31
9874; GFX6-NEXT:    s_lshr_b32 s0, s0, 20
9875; GFX6-NEXT:    s_add_u32 s0, s2, s0
9876; GFX6-NEXT:    s_mov_b32 s5, s1
9877; GFX6-NEXT:    s_addc_u32 s1, s3, 0
9878; GFX6-NEXT:    s_and_b32 s0, s0, 0xfffff000
9879; GFX6-NEXT:    s_sub_u32 s0, s2, s0
9880; GFX6-NEXT:    s_subb_u32 s1, s3, s1
9881; GFX6-NEXT:    v_mov_b32_e32 v0, s0
9882; GFX6-NEXT:    v_mov_b32_e32 v1, s1
9883; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
9884; GFX6-NEXT:    s_endpgm
9885;
9886; GFX9-LABEL: srem_i64_pow2k_denom:
9887; GFX9:       ; %bb.0:
9888; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
9889; GFX9-NEXT:    v_mov_b32_e32 v2, 0
9890; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
9891; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
9892; GFX9-NEXT:    s_lshr_b32 s4, s4, 20
9893; GFX9-NEXT:    s_add_u32 s4, s2, s4
9894; GFX9-NEXT:    s_addc_u32 s5, s3, 0
9895; GFX9-NEXT:    s_and_b32 s4, s4, 0xfffff000
9896; GFX9-NEXT:    s_sub_u32 s2, s2, s4
9897; GFX9-NEXT:    s_subb_u32 s3, s3, s5
9898; GFX9-NEXT:    v_mov_b32_e32 v0, s2
9899; GFX9-NEXT:    v_mov_b32_e32 v1, s3
9900; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
9901; GFX9-NEXT:    s_endpgm
9902  %r = srem i64 %x, 4096
9903  store i64 %r, i64 addrspace(1)* %out
9904  ret void
9905}
9906
9907define amdgpu_kernel void @srem_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %x, i64 %y) {
9908; CHECK-LABEL: @srem_i64_pow2_shl_denom(
9909; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]]
9910; CHECK-NEXT:    [[R:%.*]] = srem i64 [[X:%.*]], [[SHL_Y]]
9911; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
9912; CHECK-NEXT:    ret void
9913;
9914; GFX6-LABEL: srem_i64_pow2_shl_denom:
9915; GFX6:       ; %bb.0:
9916; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xd
9917; GFX6-NEXT:    s_mov_b64 s[2:3], 0x1000
9918; GFX6-NEXT:    s_mov_b32 s7, 0xf000
9919; GFX6-NEXT:    s_mov_b32 s6, -1
9920; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
9921; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
9922; GFX6-NEXT:    s_ashr_i32 s4, s3, 31
9923; GFX6-NEXT:    s_add_u32 s2, s2, s4
9924; GFX6-NEXT:    s_mov_b32 s5, s4
9925; GFX6-NEXT:    s_addc_u32 s3, s3, s4
9926; GFX6-NEXT:    s_xor_b64 s[8:9], s[2:3], s[4:5]
9927; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
9928; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
9929; GFX6-NEXT:    s_sub_u32 s4, 0, s8
9930; GFX6-NEXT:    s_subb_u32 s5, 0, s9
9931; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
9932; GFX6-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
9933; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
9934; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
9935; GFX6-NEXT:    s_ashr_i32 s10, s3, 31
9936; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
9937; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
9938; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
9939; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
9940; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
9941; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
9942; GFX6-NEXT:    s_add_u32 s2, s2, s10
9943; GFX6-NEXT:    s_mov_b32 s11, s10
9944; GFX6-NEXT:    v_mul_lo_u32 v2, s4, v1
9945; GFX6-NEXT:    v_mul_hi_u32 v3, s4, v0
9946; GFX6-NEXT:    v_mul_lo_u32 v5, s5, v0
9947; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v0
9948; GFX6-NEXT:    s_addc_u32 s3, s3, s10
9949; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9950; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
9951; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
9952; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
9953; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
9954; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
9955; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
9956; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
9957; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
9958; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
9959; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
9960; GFX6-NEXT:    s_xor_b64 s[12:13], s[2:3], s[10:11]
9961; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
9962; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
9963; GFX6-NEXT:    v_mov_b32_e32 v4, 0
9964; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
9965; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9966; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
9967; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
9968; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
9969; GFX6-NEXT:    v_mul_lo_u32 v2, s4, v1
9970; GFX6-NEXT:    v_mul_hi_u32 v3, s4, v0
9971; GFX6-NEXT:    v_mul_lo_u32 v5, s5, v0
9972; GFX6-NEXT:    s_mov_b32 s5, s1
9973; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9974; GFX6-NEXT:    v_mul_lo_u32 v3, s4, v0
9975; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
9976; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v2
9977; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v3
9978; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v2
9979; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v3
9980; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
9981; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v2
9982; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
9983; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
9984; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
9985; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
9986; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v6, vcc
9987; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v5, v4, vcc
9988; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9989; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
9990; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
9991; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
9992; GFX6-NEXT:    v_mul_lo_u32 v2, s12, v1
9993; GFX6-NEXT:    v_mul_hi_u32 v3, s12, v0
9994; GFX6-NEXT:    v_mul_hi_u32 v5, s12, v1
9995; GFX6-NEXT:    v_mul_hi_u32 v6, s13, v1
9996; GFX6-NEXT:    v_mul_lo_u32 v1, s13, v1
9997; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9998; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
9999; GFX6-NEXT:    v_mul_lo_u32 v5, s13, v0
10000; GFX6-NEXT:    v_mul_hi_u32 v0, s13, v0
10001; GFX6-NEXT:    s_mov_b32 s4, s0
10002; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
10003; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
10004; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v6, v4, vcc
10005; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
10006; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
10007; GFX6-NEXT:    v_mul_lo_u32 v1, s8, v1
10008; GFX6-NEXT:    v_mul_hi_u32 v2, s8, v0
10009; GFX6-NEXT:    v_mul_lo_u32 v3, s9, v0
10010; GFX6-NEXT:    v_mul_lo_u32 v0, s8, v0
10011; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
10012; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
10013; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s13, v1
10014; GFX6-NEXT:    v_mov_b32_e32 v3, s9
10015; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s12, v0
10016; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
10017; GFX6-NEXT:    v_subrev_i32_e64 v4, s[0:1], s8, v0
10018; GFX6-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
10019; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v5
10020; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
10021; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v4
10022; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
10023; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
10024; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v5
10025; GFX6-NEXT:    v_subrev_i32_e64 v3, s[0:1], s8, v4
10026; GFX6-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
10027; GFX6-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
10028; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
10029; GFX6-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
10030; GFX6-NEXT:    v_mov_b32_e32 v5, s13
10031; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
10032; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
10033; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
10034; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
10035; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
10036; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
10037; GFX6-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
10038; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
10039; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
10040; GFX6-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
10041; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
10042; GFX6-NEXT:    v_xor_b32_e32 v0, s10, v0
10043; GFX6-NEXT:    v_xor_b32_e32 v1, s10, v1
10044; GFX6-NEXT:    v_mov_b32_e32 v2, s10
10045; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s10, v0
10046; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
10047; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
10048; GFX6-NEXT:    s_endpgm
10049;
10050; GFX9-LABEL: srem_i64_pow2_shl_denom:
10051; GFX9:       ; %bb.0:
10052; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x34
10053; GFX9-NEXT:    s_mov_b64 s[2:3], 0x1000
10054; GFX9-NEXT:    v_mov_b32_e32 v2, 0
10055; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
10056; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
10057; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
10058; GFX9-NEXT:    s_add_u32 s2, s2, s4
10059; GFX9-NEXT:    s_mov_b32 s5, s4
10060; GFX9-NEXT:    s_addc_u32 s3, s3, s4
10061; GFX9-NEXT:    s_xor_b64 s[8:9], s[2:3], s[4:5]
10062; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
10063; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
10064; GFX9-NEXT:    s_sub_u32 s2, 0, s8
10065; GFX9-NEXT:    s_subb_u32 s3, 0, s9
10066; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
10067; GFX9-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
10068; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
10069; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
10070; GFX9-NEXT:    s_ashr_i32 s10, s7, 31
10071; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
10072; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
10073; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
10074; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
10075; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
10076; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
10077; GFX9-NEXT:    s_add_u32 s0, s6, s10
10078; GFX9-NEXT:    s_mov_b32 s11, s10
10079; GFX9-NEXT:    v_mul_lo_u32 v3, s2, v1
10080; GFX9-NEXT:    v_mul_hi_u32 v4, s2, v0
10081; GFX9-NEXT:    v_mul_lo_u32 v6, s3, v0
10082; GFX9-NEXT:    v_mul_lo_u32 v5, s2, v0
10083; GFX9-NEXT:    s_addc_u32 s1, s7, s10
10084; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
10085; GFX9-NEXT:    v_add_u32_e32 v3, v3, v6
10086; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v5
10087; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v3
10088; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v3
10089; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v5
10090; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
10091; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v3
10092; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
10093; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
10094; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
10095; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v5
10096; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
10097; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v2, vcc
10098; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
10099; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
10100; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
10101; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
10102; GFX9-NEXT:    v_mul_lo_u32 v3, s2, v1
10103; GFX9-NEXT:    v_mul_hi_u32 v4, s2, v0
10104; GFX9-NEXT:    v_mul_lo_u32 v5, s3, v0
10105; GFX9-NEXT:    v_mul_lo_u32 v6, s2, v0
10106; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[10:11]
10107; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
10108; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
10109; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v3
10110; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v6
10111; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v3
10112; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v6
10113; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
10114; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v3
10115; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
10116; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
10117; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
10118; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
10119; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v5, vcc
10120; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v2, vcc
10121; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
10122; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
10123; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
10124; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
10125; GFX9-NEXT:    v_mul_lo_u32 v3, s6, v1
10126; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v0
10127; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v1
10128; GFX9-NEXT:    v_mul_hi_u32 v6, s7, v1
10129; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
10130; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
10131; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
10132; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v0
10133; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
10134; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
10135; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v4, v0, vcc
10136; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v2, vcc
10137; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
10138; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
10139; GFX9-NEXT:    v_mul_lo_u32 v1, s8, v1
10140; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v0
10141; GFX9-NEXT:    v_mul_lo_u32 v4, s9, v0
10142; GFX9-NEXT:    v_mul_lo_u32 v0, s8, v0
10143; GFX9-NEXT:    v_add_u32_e32 v1, v3, v1
10144; GFX9-NEXT:    v_add_u32_e32 v1, v1, v4
10145; GFX9-NEXT:    v_sub_u32_e32 v3, s7, v1
10146; GFX9-NEXT:    v_mov_b32_e32 v4, s9
10147; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, s6, v0
10148; GFX9-NEXT:    v_subb_co_u32_e64 v3, s[0:1], v3, v4, vcc
10149; GFX9-NEXT:    v_subrev_co_u32_e64 v5, s[0:1], s8, v0
10150; GFX9-NEXT:    v_subbrev_co_u32_e64 v6, s[2:3], 0, v3, s[0:1]
10151; GFX9-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v6
10152; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
10153; GFX9-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v5
10154; GFX9-NEXT:    v_subb_co_u32_e64 v3, s[0:1], v3, v4, s[0:1]
10155; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[2:3]
10156; GFX9-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v6
10157; GFX9-NEXT:    v_subrev_co_u32_e64 v4, s[0:1], s8, v5
10158; GFX9-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[2:3]
10159; GFX9-NEXT:    v_subbrev_co_u32_e64 v3, s[0:1], 0, v3, s[0:1]
10160; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v7
10161; GFX9-NEXT:    v_cndmask_b32_e64 v3, v6, v3, s[0:1]
10162; GFX9-NEXT:    v_mov_b32_e32 v6, s7
10163; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v6, v1, vcc
10164; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
10165; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
10166; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
10167; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
10168; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
10169; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc
10170; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
10171; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
10172; GFX9-NEXT:    v_cndmask_b32_e64 v3, v5, v4, s[0:1]
10173; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
10174; GFX9-NEXT:    v_xor_b32_e32 v0, s10, v0
10175; GFX9-NEXT:    v_xor_b32_e32 v1, s10, v1
10176; GFX9-NEXT:    v_mov_b32_e32 v3, s10
10177; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s10, v0
10178; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
10179; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
10180; GFX9-NEXT:    s_endpgm
10181  %shl.y = shl i64 4096, %y
10182  %r = srem i64 %x, %shl.y
10183  store i64 %r, i64 addrspace(1)* %out
10184  ret void
10185}
10186
10187define amdgpu_kernel void @srem_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
10188; CHECK-LABEL: @srem_v2i64_pow2k_denom(
10189; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
10190; CHECK-NEXT:    [[TMP2:%.*]] = srem i64 [[TMP1]], 4096
10191; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
10192; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
10193; CHECK-NEXT:    [[TMP5:%.*]] = srem i64 [[TMP4]], 4096
10194; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
10195; CHECK-NEXT:    store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
10196; CHECK-NEXT:    ret void
10197;
10198; GFX6-LABEL: srem_v2i64_pow2k_denom:
10199; GFX6:       ; %bb.0:
10200; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
10201; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
10202; GFX6-NEXT:    s_movk_i32 s8, 0xf000
10203; GFX6-NEXT:    s_mov_b32 s3, 0xf000
10204; GFX6-NEXT:    s_mov_b32 s2, -1
10205; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
10206; GFX6-NEXT:    s_ashr_i32 s9, s5, 31
10207; GFX6-NEXT:    s_lshr_b32 s9, s9, 20
10208; GFX6-NEXT:    s_add_u32 s9, s4, s9
10209; GFX6-NEXT:    s_addc_u32 s10, s5, 0
10210; GFX6-NEXT:    s_and_b32 s9, s9, s8
10211; GFX6-NEXT:    s_sub_u32 s4, s4, s9
10212; GFX6-NEXT:    s_subb_u32 s5, s5, s10
10213; GFX6-NEXT:    s_ashr_i32 s9, s7, 31
10214; GFX6-NEXT:    s_lshr_b32 s9, s9, 20
10215; GFX6-NEXT:    s_add_u32 s9, s6, s9
10216; GFX6-NEXT:    s_addc_u32 s10, s7, 0
10217; GFX6-NEXT:    s_and_b32 s8, s9, s8
10218; GFX6-NEXT:    s_sub_u32 s6, s6, s8
10219; GFX6-NEXT:    s_subb_u32 s7, s7, s10
10220; GFX6-NEXT:    v_mov_b32_e32 v0, s4
10221; GFX6-NEXT:    v_mov_b32_e32 v1, s5
10222; GFX6-NEXT:    v_mov_b32_e32 v2, s6
10223; GFX6-NEXT:    v_mov_b32_e32 v3, s7
10224; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
10225; GFX6-NEXT:    s_endpgm
10226;
10227; GFX9-LABEL: srem_v2i64_pow2k_denom:
10228; GFX9:       ; %bb.0:
10229; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
10230; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
10231; GFX9-NEXT:    s_movk_i32 s0, 0xf000
10232; GFX9-NEXT:    v_mov_b32_e32 v4, 0
10233; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
10234; GFX9-NEXT:    s_ashr_i32 s1, s5, 31
10235; GFX9-NEXT:    s_lshr_b32 s1, s1, 20
10236; GFX9-NEXT:    s_add_u32 s1, s4, s1
10237; GFX9-NEXT:    s_addc_u32 s8, s5, 0
10238; GFX9-NEXT:    s_and_b32 s1, s1, s0
10239; GFX9-NEXT:    s_sub_u32 s1, s4, s1
10240; GFX9-NEXT:    s_subb_u32 s4, s5, s8
10241; GFX9-NEXT:    s_ashr_i32 s5, s7, 31
10242; GFX9-NEXT:    s_lshr_b32 s5, s5, 20
10243; GFX9-NEXT:    s_add_u32 s5, s6, s5
10244; GFX9-NEXT:    s_addc_u32 s8, s7, 0
10245; GFX9-NEXT:    s_and_b32 s0, s5, s0
10246; GFX9-NEXT:    s_sub_u32 s0, s6, s0
10247; GFX9-NEXT:    s_subb_u32 s5, s7, s8
10248; GFX9-NEXT:    v_mov_b32_e32 v0, s1
10249; GFX9-NEXT:    v_mov_b32_e32 v1, s4
10250; GFX9-NEXT:    v_mov_b32_e32 v2, s0
10251; GFX9-NEXT:    v_mov_b32_e32 v3, s5
10252; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
10253; GFX9-NEXT:    s_endpgm
10254  %r = srem <2 x i64> %x, <i64 4096, i64 4096>
10255  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
10256  ret void
10257}
10258
10259define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
10260; CHECK-LABEL: @srem_v2i64_pow2_shl_denom(
10261; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.*]]
10262; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
10263; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 0
10264; CHECK-NEXT:    [[TMP3:%.*]] = srem i64 [[TMP1]], [[TMP2]]
10265; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i64 0
10266; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 1
10267; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
10268; CHECK-NEXT:    [[TMP7:%.*]] = srem i64 [[TMP5]], [[TMP6]]
10269; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
10270; CHECK-NEXT:    store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
10271; CHECK-NEXT:    ret void
10272;
10273; GFX6-LABEL: srem_v2i64_pow2_shl_denom:
10274; GFX6:       ; %bb.0:
10275; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x11
10276; GFX6-NEXT:    s_mov_b64 s[2:3], 0x1000
10277; GFX6-NEXT:    s_mov_b32 s18, 0x4f800000
10278; GFX6-NEXT:    s_mov_b32 s19, 0x5f7ffffc
10279; GFX6-NEXT:    s_mov_b32 s20, 0x2f800000
10280; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
10281; GFX6-NEXT:    s_lshl_b64 s[14:15], s[2:3], s6
10282; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
10283; GFX6-NEXT:    s_ashr_i32 s4, s3, 31
10284; GFX6-NEXT:    s_add_u32 s2, s2, s4
10285; GFX6-NEXT:    s_mov_b32 s5, s4
10286; GFX6-NEXT:    s_addc_u32 s3, s3, s4
10287; GFX6-NEXT:    s_xor_b64 s[16:17], s[2:3], s[4:5]
10288; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s16
10289; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s17
10290; GFX6-NEXT:    s_mov_b32 s21, 0xcf800000
10291; GFX6-NEXT:    s_sub_u32 s2, 0, s16
10292; GFX6-NEXT:    s_subb_u32 s3, 0, s17
10293; GFX6-NEXT:    v_mac_f32_e32 v0, s18, v1
10294; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
10295; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
10296; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
10297; GFX6-NEXT:    s_mov_b32 s7, 0xf000
10298; GFX6-NEXT:    s_mov_b32 s6, -1
10299; GFX6-NEXT:    v_mul_f32_e32 v0, s19, v0
10300; GFX6-NEXT:    v_mul_f32_e32 v1, s20, v0
10301; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
10302; GFX6-NEXT:    v_mac_f32_e32 v0, s21, v1
10303; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
10304; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v0
10305; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
10306; GFX6-NEXT:    s_ashr_i32 s12, s9, 31
10307; GFX6-NEXT:    s_add_u32 s0, s8, s12
10308; GFX6-NEXT:    v_mul_lo_u32 v0, s2, v1
10309; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v2
10310; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v2
10311; GFX6-NEXT:    v_mul_lo_u32 v5, s2, v2
10312; GFX6-NEXT:    s_mov_b32 s13, s12
10313; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
10314; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v0, v4
10315; GFX6-NEXT:    v_mul_lo_u32 v0, v2, v3
10316; GFX6-NEXT:    v_mul_hi_u32 v4, v2, v5
10317; GFX6-NEXT:    v_mul_hi_u32 v6, v2, v3
10318; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v3
10319; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
10320; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v4, v0
10321; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v6, vcc
10322; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v5
10323; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v5
10324; GFX6-NEXT:    s_addc_u32 s1, s9, s12
10325; GFX6-NEXT:    s_xor_b64 s[8:9], s[0:1], s[12:13]
10326; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
10327; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v4, v5, vcc
10328; GFX6-NEXT:    v_mov_b32_e32 v0, 0
10329; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v0, vcc
10330; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
10331; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
10332; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
10333; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
10334; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v1
10335; GFX6-NEXT:    v_mul_hi_u32 v4, s2, v2
10336; GFX6-NEXT:    v_mul_lo_u32 v5, s3, v2
10337; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
10338; GFX6-NEXT:    v_mul_lo_u32 v4, s2, v2
10339; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
10340; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v3
10341; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v4
10342; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v3
10343; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v4
10344; GFX6-NEXT:    v_mul_lo_u32 v4, v1, v4
10345; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v3
10346; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
10347; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
10348; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
10349; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
10350; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
10351; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v5, v0, vcc
10352; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
10353; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
10354; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
10355; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
10356; GFX6-NEXT:    v_mul_lo_u32 v3, s8, v1
10357; GFX6-NEXT:    v_mul_hi_u32 v4, s8, v2
10358; GFX6-NEXT:    v_mul_hi_u32 v5, s8, v1
10359; GFX6-NEXT:    v_mul_hi_u32 v6, s9, v1
10360; GFX6-NEXT:    v_mul_lo_u32 v1, s9, v1
10361; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
10362; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
10363; GFX6-NEXT:    v_mul_lo_u32 v5, s9, v2
10364; GFX6-NEXT:    v_mul_hi_u32 v2, s9, v2
10365; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
10366; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v4, v2, vcc
10367; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v0, vcc
10368; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
10369; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
10370; GFX6-NEXT:    v_mul_lo_u32 v2, s16, v2
10371; GFX6-NEXT:    v_mul_hi_u32 v3, s16, v1
10372; GFX6-NEXT:    v_mul_lo_u32 v4, s17, v1
10373; GFX6-NEXT:    v_mul_lo_u32 v1, s16, v1
10374; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
10375; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
10376; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s9, v2
10377; GFX6-NEXT:    v_mov_b32_e32 v4, s17
10378; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s8, v1
10379; GFX6-NEXT:    v_subb_u32_e64 v3, s[0:1], v3, v4, vcc
10380; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s16, v1
10381; GFX6-NEXT:    v_subbrev_u32_e64 v6, s[2:3], 0, v3, s[0:1]
10382; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s17, v6
10383; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
10384; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s16, v5
10385; GFX6-NEXT:    v_subb_u32_e64 v3, s[0:1], v3, v4, s[0:1]
10386; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[2:3]
10387; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s17, v6
10388; GFX6-NEXT:    v_subrev_i32_e64 v4, s[0:1], s16, v5
10389; GFX6-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[2:3]
10390; GFX6-NEXT:    v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]
10391; GFX6-NEXT:    s_ashr_i32 s2, s15, 31
10392; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v7
10393; GFX6-NEXT:    s_add_u32 s8, s14, s2
10394; GFX6-NEXT:    v_cndmask_b32_e64 v3, v6, v3, s[0:1]
10395; GFX6-NEXT:    v_mov_b32_e32 v6, s9
10396; GFX6-NEXT:    s_mov_b32 s3, s2
10397; GFX6-NEXT:    s_addc_u32 s9, s15, s2
10398; GFX6-NEXT:    s_xor_b64 s[8:9], s[8:9], s[2:3]
10399; GFX6-NEXT:    v_cvt_f32_u32_e32 v7, s8
10400; GFX6-NEXT:    v_cvt_f32_u32_e32 v8, s9
10401; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
10402; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s17, v2
10403; GFX6-NEXT:    v_mac_f32_e32 v7, s18, v8
10404; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
10405; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s16, v1
10406; GFX6-NEXT:    v_rcp_f32_e32 v7, v7
10407; GFX6-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
10408; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s17, v2
10409; GFX6-NEXT:    v_cndmask_b32_e32 v6, v6, v9, vcc
10410; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
10411; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
10412; GFX6-NEXT:    v_cndmask_b32_e64 v3, v5, v4, s[0:1]
10413; GFX6-NEXT:    v_mul_f32_e32 v4, s19, v7
10414; GFX6-NEXT:    v_mul_f32_e32 v5, s20, v4
10415; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
10416; GFX6-NEXT:    v_mac_f32_e32 v4, s21, v5
10417; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
10418; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v5
10419; GFX6-NEXT:    s_sub_u32 s0, 0, s8
10420; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
10421; GFX6-NEXT:    v_mul_hi_u32 v3, s0, v4
10422; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v5
10423; GFX6-NEXT:    s_subb_u32 s1, 0, s9
10424; GFX6-NEXT:    v_mul_lo_u32 v7, s1, v4
10425; GFX6-NEXT:    s_ashr_i32 s14, s11, 31
10426; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
10427; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v4
10428; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
10429; GFX6-NEXT:    v_mul_lo_u32 v7, v4, v3
10430; GFX6-NEXT:    v_mul_hi_u32 v8, v4, v6
10431; GFX6-NEXT:    v_mul_hi_u32 v9, v4, v3
10432; GFX6-NEXT:    v_mul_hi_u32 v10, v5, v3
10433; GFX6-NEXT:    v_mul_lo_u32 v3, v5, v3
10434; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
10435; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
10436; GFX6-NEXT:    v_mul_lo_u32 v9, v5, v6
10437; GFX6-NEXT:    v_mul_hi_u32 v6, v5, v6
10438; GFX6-NEXT:    s_mov_b32 s15, s14
10439; GFX6-NEXT:    v_xor_b32_e32 v1, s12, v1
10440; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
10441; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v8, v6, vcc
10442; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v10, v0, vcc
10443; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
10444; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
10445; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
10446; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v5, v6, vcc
10447; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v4
10448; GFX6-NEXT:    v_mul_hi_u32 v6, s0, v3
10449; GFX6-NEXT:    v_mul_lo_u32 v7, s1, v3
10450; GFX6-NEXT:    v_xor_b32_e32 v2, s12, v2
10451; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
10452; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v3
10453; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
10454; GFX6-NEXT:    v_mul_lo_u32 v9, v3, v5
10455; GFX6-NEXT:    v_mul_hi_u32 v10, v3, v6
10456; GFX6-NEXT:    v_mul_hi_u32 v11, v3, v5
10457; GFX6-NEXT:    v_mul_hi_u32 v8, v4, v6
10458; GFX6-NEXT:    v_mul_lo_u32 v6, v4, v6
10459; GFX6-NEXT:    v_mul_hi_u32 v7, v4, v5
10460; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
10461; GFX6-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
10462; GFX6-NEXT:    v_mul_lo_u32 v5, v4, v5
10463; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
10464; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v10, v8, vcc
10465; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v7, v0, vcc
10466; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
10467; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
10468; GFX6-NEXT:    s_add_u32 s0, s10, s14
10469; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
10470; GFX6-NEXT:    s_addc_u32 s1, s11, s14
10471; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
10472; GFX6-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
10473; GFX6-NEXT:    v_mul_lo_u32 v5, s10, v4
10474; GFX6-NEXT:    v_mul_hi_u32 v6, s10, v3
10475; GFX6-NEXT:    v_mul_hi_u32 v8, s10, v4
10476; GFX6-NEXT:    v_mul_hi_u32 v9, s11, v4
10477; GFX6-NEXT:    v_mul_lo_u32 v4, s11, v4
10478; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
10479; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
10480; GFX6-NEXT:    v_mul_lo_u32 v8, s11, v3
10481; GFX6-NEXT:    v_mul_hi_u32 v3, s11, v3
10482; GFX6-NEXT:    v_mov_b32_e32 v7, s12
10483; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
10484; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v3, vcc
10485; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v9, v0, vcc
10486; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
10487; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v0, vcc
10488; GFX6-NEXT:    v_mul_lo_u32 v4, s8, v0
10489; GFX6-NEXT:    v_mul_hi_u32 v5, s8, v3
10490; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s12, v1
10491; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v2, v7, vcc
10492; GFX6-NEXT:    v_mul_lo_u32 v2, s9, v3
10493; GFX6-NEXT:    v_mul_lo_u32 v3, s8, v3
10494; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
10495; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
10496; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s11, v2
10497; GFX6-NEXT:    v_mov_b32_e32 v5, s9
10498; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s10, v3
10499; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
10500; GFX6-NEXT:    v_subrev_i32_e64 v6, s[0:1], s8, v3
10501; GFX6-NEXT:    v_subbrev_u32_e64 v7, s[2:3], 0, v4, s[0:1]
10502; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v7
10503; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[2:3]
10504; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v6
10505; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, s[0:1]
10506; GFX6-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[2:3]
10507; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v7
10508; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s8, v6
10509; GFX6-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[2:3]
10510; GFX6-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
10511; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v8
10512; GFX6-NEXT:    v_cndmask_b32_e64 v4, v7, v4, s[0:1]
10513; GFX6-NEXT:    v_mov_b32_e32 v7, s11
10514; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v7, v2, vcc
10515; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
10516; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
10517; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
10518; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
10519; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v2
10520; GFX6-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
10521; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
10522; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
10523; GFX6-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
10524; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
10525; GFX6-NEXT:    v_xor_b32_e32 v3, s14, v3
10526; GFX6-NEXT:    v_xor_b32_e32 v4, s14, v2
10527; GFX6-NEXT:    v_mov_b32_e32 v5, s14
10528; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s14, v3
10529; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v4, v5, vcc
10530; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
10531; GFX6-NEXT:    s_endpgm
10532;
10533; GFX9-LABEL: srem_v2i64_pow2_shl_denom:
10534; GFX9:       ; %bb.0:
10535; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x44
10536; GFX9-NEXT:    s_mov_b64 s[2:3], 0x1000
10537; GFX9-NEXT:    s_mov_b32 s16, 0x4f800000
10538; GFX9-NEXT:    s_mov_b32 s17, 0x5f7ffffc
10539; GFX9-NEXT:    s_mov_b32 s18, 0x2f800000
10540; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
10541; GFX9-NEXT:    s_lshl_b64 s[10:11], s[2:3], s6
10542; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
10543; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
10544; GFX9-NEXT:    s_add_u32 s2, s2, s4
10545; GFX9-NEXT:    s_mov_b32 s5, s4
10546; GFX9-NEXT:    s_addc_u32 s3, s3, s4
10547; GFX9-NEXT:    s_xor_b64 s[12:13], s[2:3], s[4:5]
10548; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s12
10549; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s13
10550; GFX9-NEXT:    s_mov_b32 s19, 0xcf800000
10551; GFX9-NEXT:    s_sub_u32 s2, 0, s12
10552; GFX9-NEXT:    s_subb_u32 s3, 0, s13
10553; GFX9-NEXT:    v_mac_f32_e32 v0, s16, v1
10554; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
10555; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
10556; GFX9-NEXT:    v_mul_f32_e32 v0, s17, v0
10557; GFX9-NEXT:    v_mul_f32_e32 v1, s18, v0
10558; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
10559; GFX9-NEXT:    v_mac_f32_e32 v0, s19, v1
10560; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
10561; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v0
10562; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
10563; GFX9-NEXT:    s_ashr_i32 s8, s5, 31
10564; GFX9-NEXT:    s_mov_b32 s9, s8
10565; GFX9-NEXT:    v_mul_lo_u32 v0, s2, v1
10566; GFX9-NEXT:    v_mul_hi_u32 v3, s2, v2
10567; GFX9-NEXT:    v_mul_lo_u32 v5, s3, v2
10568; GFX9-NEXT:    v_mul_lo_u32 v4, s2, v2
10569; GFX9-NEXT:    v_add_u32_e32 v0, v3, v0
10570; GFX9-NEXT:    v_add_u32_e32 v5, v0, v5
10571; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v4
10572; GFX9-NEXT:    v_mul_lo_u32 v6, v2, v5
10573; GFX9-NEXT:    v_mul_hi_u32 v7, v2, v5
10574; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v5
10575; GFX9-NEXT:    v_mov_b32_e32 v0, 0
10576; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
10577; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
10578; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
10579; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
10580; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
10581; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
10582; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v5
10583; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v0, vcc
10584; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v4
10585; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
10586; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
10587; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
10588; GFX9-NEXT:    v_mul_lo_u32 v3, s2, v1
10589; GFX9-NEXT:    v_mul_hi_u32 v4, s2, v2
10590; GFX9-NEXT:    v_mul_lo_u32 v5, s3, v2
10591; GFX9-NEXT:    v_mul_lo_u32 v6, s2, v2
10592; GFX9-NEXT:    s_add_u32 s2, s4, s8
10593; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
10594; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
10595; GFX9-NEXT:    v_mul_lo_u32 v7, v2, v3
10596; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v6
10597; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v3
10598; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v6
10599; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
10600; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v3
10601; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
10602; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
10603; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
10604; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
10605; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v5, vcc
10606; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v0, vcc
10607; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
10608; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
10609; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
10610; GFX9-NEXT:    s_addc_u32 s3, s5, s8
10611; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
10612; GFX9-NEXT:    s_xor_b64 s[14:15], s[2:3], s[8:9]
10613; GFX9-NEXT:    v_mul_lo_u32 v3, s14, v1
10614; GFX9-NEXT:    v_mul_hi_u32 v4, s14, v2
10615; GFX9-NEXT:    v_mul_hi_u32 v5, s14, v1
10616; GFX9-NEXT:    v_mul_hi_u32 v6, s15, v1
10617; GFX9-NEXT:    v_mul_lo_u32 v1, s15, v1
10618; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
10619; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
10620; GFX9-NEXT:    v_mul_lo_u32 v5, s15, v2
10621; GFX9-NEXT:    v_mul_hi_u32 v2, s15, v2
10622; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
10623; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
10624; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v4, v2, vcc
10625; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v0, vcc
10626; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v2, v1
10627; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v3, vcc
10628; GFX9-NEXT:    v_mul_lo_u32 v2, s12, v2
10629; GFX9-NEXT:    v_mul_hi_u32 v3, s12, v1
10630; GFX9-NEXT:    v_mul_lo_u32 v4, s13, v1
10631; GFX9-NEXT:    v_mul_lo_u32 v1, s12, v1
10632; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
10633; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
10634; GFX9-NEXT:    v_sub_u32_e32 v3, s15, v2
10635; GFX9-NEXT:    v_mov_b32_e32 v4, s13
10636; GFX9-NEXT:    v_sub_co_u32_e32 v1, vcc, s14, v1
10637; GFX9-NEXT:    v_subb_co_u32_e64 v3, s[0:1], v3, v4, vcc
10638; GFX9-NEXT:    v_subrev_co_u32_e64 v5, s[0:1], s12, v1
10639; GFX9-NEXT:    v_subbrev_co_u32_e64 v6, s[2:3], 0, v3, s[0:1]
10640; GFX9-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v6
10641; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
10642; GFX9-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v5
10643; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[2:3]
10644; GFX9-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v6
10645; GFX9-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[2:3]
10646; GFX9-NEXT:    s_ashr_i32 s2, s11, 31
10647; GFX9-NEXT:    v_subb_co_u32_e64 v3, s[0:1], v3, v4, s[0:1]
10648; GFX9-NEXT:    s_add_u32 s10, s10, s2
10649; GFX9-NEXT:    v_subrev_co_u32_e64 v4, s[0:1], s12, v5
10650; GFX9-NEXT:    s_mov_b32 s3, s2
10651; GFX9-NEXT:    s_addc_u32 s11, s11, s2
10652; GFX9-NEXT:    v_subbrev_co_u32_e64 v3, s[0:1], 0, v3, s[0:1]
10653; GFX9-NEXT:    s_xor_b64 s[10:11], s[10:11], s[2:3]
10654; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v7
10655; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s10
10656; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, s11
10657; GFX9-NEXT:    v_cndmask_b32_e64 v3, v6, v3, s[0:1]
10658; GFX9-NEXT:    v_mov_b32_e32 v6, s15
10659; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v6, v2, vcc
10660; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s13, v2
10661; GFX9-NEXT:    v_mac_f32_e32 v7, s16, v8
10662; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
10663; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s12, v1
10664; GFX9-NEXT:    v_rcp_f32_e32 v7, v7
10665; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
10666; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v2
10667; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v9, vcc
10668; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
10669; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
10670; GFX9-NEXT:    v_cndmask_b32_e64 v3, v5, v4, s[0:1]
10671; GFX9-NEXT:    v_mul_f32_e32 v4, s17, v7
10672; GFX9-NEXT:    v_mul_f32_e32 v5, s18, v4
10673; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
10674; GFX9-NEXT:    v_mac_f32_e32 v4, s19, v5
10675; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
10676; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
10677; GFX9-NEXT:    s_sub_u32 s0, 0, s10
10678; GFX9-NEXT:    s_subb_u32 s1, 0, s11
10679; GFX9-NEXT:    v_mul_hi_u32 v6, s0, v4
10680; GFX9-NEXT:    v_mul_lo_u32 v7, s0, v5
10681; GFX9-NEXT:    v_mul_lo_u32 v8, s1, v4
10682; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
10683; GFX9-NEXT:    v_mul_lo_u32 v3, s0, v4
10684; GFX9-NEXT:    v_add_u32_e32 v6, v6, v7
10685; GFX9-NEXT:    v_add_u32_e32 v6, v6, v8
10686; GFX9-NEXT:    v_mul_lo_u32 v7, v4, v6
10687; GFX9-NEXT:    v_mul_hi_u32 v8, v4, v3
10688; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v6
10689; GFX9-NEXT:    v_mul_hi_u32 v10, v5, v6
10690; GFX9-NEXT:    v_mul_lo_u32 v6, v5, v6
10691; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
10692; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
10693; GFX9-NEXT:    v_mul_lo_u32 v9, v5, v3
10694; GFX9-NEXT:    v_mul_hi_u32 v3, v5, v3
10695; GFX9-NEXT:    s_ashr_i32 s12, s7, 31
10696; GFX9-NEXT:    s_mov_b32 s13, s12
10697; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v9
10698; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v8, v3, vcc
10699; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v10, v0, vcc
10700; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
10701; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
10702; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
10703; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v6, vcc
10704; GFX9-NEXT:    v_mul_lo_u32 v5, s0, v4
10705; GFX9-NEXT:    v_mul_hi_u32 v6, s0, v3
10706; GFX9-NEXT:    v_mul_lo_u32 v7, s1, v3
10707; GFX9-NEXT:    v_mul_lo_u32 v8, s0, v3
10708; GFX9-NEXT:    s_add_u32 s0, s6, s12
10709; GFX9-NEXT:    v_add_u32_e32 v5, v6, v5
10710; GFX9-NEXT:    v_add_u32_e32 v5, v5, v7
10711; GFX9-NEXT:    v_mul_lo_u32 v9, v3, v5
10712; GFX9-NEXT:    v_mul_hi_u32 v10, v3, v8
10713; GFX9-NEXT:    v_mul_hi_u32 v11, v3, v5
10714; GFX9-NEXT:    v_mul_hi_u32 v7, v4, v8
10715; GFX9-NEXT:    v_mul_lo_u32 v8, v4, v8
10716; GFX9-NEXT:    v_mul_hi_u32 v6, v4, v5
10717; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
10718; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
10719; GFX9-NEXT:    v_mul_lo_u32 v5, v4, v5
10720; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
10721; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v10, v7, vcc
10722; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v6, v0, vcc
10723; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
10724; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
10725; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
10726; GFX9-NEXT:    s_addc_u32 s1, s7, s12
10727; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v6, vcc
10728; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[12:13]
10729; GFX9-NEXT:    v_mul_lo_u32 v5, s6, v4
10730; GFX9-NEXT:    v_mul_hi_u32 v6, s6, v3
10731; GFX9-NEXT:    v_mul_hi_u32 v8, s6, v4
10732; GFX9-NEXT:    v_mul_hi_u32 v9, s7, v4
10733; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v4
10734; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v6, v5
10735; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
10736; GFX9-NEXT:    v_mul_lo_u32 v8, s7, v3
10737; GFX9-NEXT:    v_mul_hi_u32 v3, s7, v3
10738; GFX9-NEXT:    v_xor_b32_e32 v1, s8, v1
10739; GFX9-NEXT:    v_xor_b32_e32 v2, s8, v2
10740; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v8
10741; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
10742; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v0, vcc
10743; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v4
10744; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
10745; GFX9-NEXT:    v_mul_lo_u32 v4, s10, v4
10746; GFX9-NEXT:    v_mul_hi_u32 v5, s10, v3
10747; GFX9-NEXT:    v_mul_lo_u32 v6, s11, v3
10748; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v3
10749; GFX9-NEXT:    v_mov_b32_e32 v7, s8
10750; GFX9-NEXT:    v_subrev_co_u32_e32 v1, vcc, s8, v1
10751; GFX9-NEXT:    v_add_u32_e32 v4, v5, v4
10752; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v2, v7, vcc
10753; GFX9-NEXT:    v_add_u32_e32 v4, v4, v6
10754; GFX9-NEXT:    v_sub_u32_e32 v5, s7, v4
10755; GFX9-NEXT:    v_mov_b32_e32 v6, s11
10756; GFX9-NEXT:    v_sub_co_u32_e32 v3, vcc, s6, v3
10757; GFX9-NEXT:    v_subb_co_u32_e64 v5, s[0:1], v5, v6, vcc
10758; GFX9-NEXT:    v_subrev_co_u32_e64 v7, s[0:1], s10, v3
10759; GFX9-NEXT:    v_subbrev_co_u32_e64 v8, s[2:3], 0, v5, s[0:1]
10760; GFX9-NEXT:    v_cmp_le_u32_e64 s[2:3], s11, v8
10761; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[2:3]
10762; GFX9-NEXT:    v_cmp_le_u32_e64 s[2:3], s10, v7
10763; GFX9-NEXT:    v_subb_co_u32_e64 v5, s[0:1], v5, v6, s[0:1]
10764; GFX9-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[2:3]
10765; GFX9-NEXT:    v_cmp_eq_u32_e64 s[2:3], s11, v8
10766; GFX9-NEXT:    v_subrev_co_u32_e64 v6, s[0:1], s10, v7
10767; GFX9-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[2:3]
10768; GFX9-NEXT:    v_subbrev_co_u32_e64 v5, s[0:1], 0, v5, s[0:1]
10769; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v9
10770; GFX9-NEXT:    v_cndmask_b32_e64 v5, v8, v5, s[0:1]
10771; GFX9-NEXT:    v_mov_b32_e32 v8, s7
10772; GFX9-NEXT:    v_subb_co_u32_e32 v4, vcc, v8, v4, vcc
10773; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v4
10774; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
10775; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
10776; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
10777; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v4
10778; GFX9-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
10779; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
10780; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
10781; GFX9-NEXT:    v_cndmask_b32_e64 v5, v7, v6, s[0:1]
10782; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
10783; GFX9-NEXT:    v_xor_b32_e32 v3, s12, v3
10784; GFX9-NEXT:    v_xor_b32_e32 v4, s12, v4
10785; GFX9-NEXT:    v_mov_b32_e32 v5, s12
10786; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s12, v3
10787; GFX9-NEXT:    v_subb_co_u32_e32 v4, vcc, v4, v5, vcc
10788; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
10789; GFX9-NEXT:    global_store_dwordx4 v0, v[1:4], s[4:5]
10790; GFX9-NEXT:    s_endpgm
10791  %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
10792  %r = srem <2 x i64> %x, %shl.y
10793  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
10794  ret void
10795}
10796