1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
3; RUN: opt -S -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-codegenprepare -amdgpu-bypass-slow-div=0 %s | FileCheck %s
4; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-bypass-slow-div=0 < %s | FileCheck -check-prefix=GFX6 %s
5; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -amdgpu-bypass-slow-div=0 < %s | FileCheck -check-prefix=GFX9 %s
6
7define amdgpu_kernel void @udiv_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
8; CHECK-LABEL: @udiv_i32(
9; CHECK-NEXT:    [[TMP1:%.*]] = uitofp i32 [[Y:%.*]] to float
10; CHECK-NEXT:    [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]])
11; CHECK-NEXT:    [[TMP3:%.*]] = fmul fast float [[TMP2]], 0x41EFFFFFC0000000
12; CHECK-NEXT:    [[TMP4:%.*]] = fptoui float [[TMP3]] to i32
13; CHECK-NEXT:    [[TMP5:%.*]] = sub i32 0, [[Y]]
14; CHECK-NEXT:    [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP4]]
15; CHECK-NEXT:    [[TMP7:%.*]] = zext i32 [[TMP4]] to i64
16; CHECK-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP6]] to i64
17; CHECK-NEXT:    [[TMP9:%.*]] = mul i64 [[TMP7]], [[TMP8]]
18; CHECK-NEXT:    [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
19; CHECK-NEXT:    [[TMP11:%.*]] = lshr i64 [[TMP9]], 32
20; CHECK-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
21; CHECK-NEXT:    [[TMP13:%.*]] = add i32 [[TMP4]], [[TMP12]]
22; CHECK-NEXT:    [[TMP14:%.*]] = zext i32 [[X:%.*]] to i64
23; CHECK-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP13]] to i64
24; CHECK-NEXT:    [[TMP16:%.*]] = mul i64 [[TMP14]], [[TMP15]]
25; CHECK-NEXT:    [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32
26; CHECK-NEXT:    [[TMP18:%.*]] = lshr i64 [[TMP16]], 32
27; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
28; CHECK-NEXT:    [[TMP20:%.*]] = mul i32 [[TMP19]], [[Y]]
29; CHECK-NEXT:    [[TMP21:%.*]] = sub i32 [[X]], [[TMP20]]
30; CHECK-NEXT:    [[TMP22:%.*]] = icmp uge i32 [[TMP21]], [[Y]]
31; CHECK-NEXT:    [[TMP23:%.*]] = add i32 [[TMP19]], 1
32; CHECK-NEXT:    [[TMP24:%.*]] = select i1 [[TMP22]], i32 [[TMP23]], i32 [[TMP19]]
33; CHECK-NEXT:    [[TMP25:%.*]] = sub i32 [[TMP21]], [[Y]]
34; CHECK-NEXT:    [[TMP26:%.*]] = select i1 [[TMP22]], i32 [[TMP25]], i32 [[TMP21]]
35; CHECK-NEXT:    [[TMP27:%.*]] = icmp uge i32 [[TMP26]], [[Y]]
36; CHECK-NEXT:    [[TMP28:%.*]] = add i32 [[TMP24]], 1
37; CHECK-NEXT:    [[TMP29:%.*]] = select i1 [[TMP27]], i32 [[TMP28]], i32 [[TMP24]]
38; CHECK-NEXT:    store i32 [[TMP29]], i32 addrspace(1)* [[OUT:%.*]], align 4
39; CHECK-NEXT:    ret void
40;
41; GFX6-LABEL: udiv_i32:
42; GFX6:       ; %bb.0:
43; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
44; GFX6-NEXT:    s_mov_b32 s7, 0xf000
45; GFX6-NEXT:    s_mov_b32 s6, -1
46; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
47; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s3
48; GFX6-NEXT:    s_sub_i32 s4, 0, s3
49; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
50; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
51; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
52; GFX6-NEXT:    v_mul_lo_u32 v1, s4, v0
53; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
54; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
55; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
56; GFX6-NEXT:    v_mul_hi_u32 v0, s2, v0
57; GFX6-NEXT:    v_mul_lo_u32 v1, v0, s3
58; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
59; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s2, v1
60; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v1
61; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
62; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v1
63; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[0:1]
64; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
65; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
66; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
67; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
68; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
69; GFX6-NEXT:    s_endpgm
70;
71; GFX9-LABEL: udiv_i32:
72; GFX9:       ; %bb.0:
73; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
74; GFX9-NEXT:    v_mov_b32_e32 v2, 0
75; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
76; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
77; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
78; GFX9-NEXT:    s_sub_i32 s4, 0, s3
79; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
80; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
81; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
82; GFX9-NEXT:    v_mul_lo_u32 v1, s4, v0
83; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
84; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
85; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
86; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s3
87; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
88; GFX9-NEXT:    v_sub_u32_e32 v1, s2, v1
89; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
90; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
91; GFX9-NEXT:    v_subrev_u32_e32 v3, s3, v1
92; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
93; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
94; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
95; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
96; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]
97; GFX9-NEXT:    s_endpgm
98  %r = udiv i32 %x, %y
99  store i32 %r, i32 addrspace(1)* %out
100  ret void
101}
102
103define amdgpu_kernel void @urem_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
104; CHECK-LABEL: @urem_i32(
105; CHECK-NEXT:    [[TMP1:%.*]] = uitofp i32 [[Y:%.*]] to float
106; CHECK-NEXT:    [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]])
107; CHECK-NEXT:    [[TMP3:%.*]] = fmul fast float [[TMP2]], 0x41EFFFFFC0000000
108; CHECK-NEXT:    [[TMP4:%.*]] = fptoui float [[TMP3]] to i32
109; CHECK-NEXT:    [[TMP5:%.*]] = sub i32 0, [[Y]]
110; CHECK-NEXT:    [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP4]]
111; CHECK-NEXT:    [[TMP7:%.*]] = zext i32 [[TMP4]] to i64
112; CHECK-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP6]] to i64
113; CHECK-NEXT:    [[TMP9:%.*]] = mul i64 [[TMP7]], [[TMP8]]
114; CHECK-NEXT:    [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
115; CHECK-NEXT:    [[TMP11:%.*]] = lshr i64 [[TMP9]], 32
116; CHECK-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
117; CHECK-NEXT:    [[TMP13:%.*]] = add i32 [[TMP4]], [[TMP12]]
118; CHECK-NEXT:    [[TMP14:%.*]] = zext i32 [[X:%.*]] to i64
119; CHECK-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP13]] to i64
120; CHECK-NEXT:    [[TMP16:%.*]] = mul i64 [[TMP14]], [[TMP15]]
121; CHECK-NEXT:    [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32
122; CHECK-NEXT:    [[TMP18:%.*]] = lshr i64 [[TMP16]], 32
123; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
124; CHECK-NEXT:    [[TMP20:%.*]] = mul i32 [[TMP19]], [[Y]]
125; CHECK-NEXT:    [[TMP21:%.*]] = sub i32 [[X]], [[TMP20]]
126; CHECK-NEXT:    [[TMP22:%.*]] = icmp uge i32 [[TMP21]], [[Y]]
127; CHECK-NEXT:    [[TMP23:%.*]] = sub i32 [[TMP21]], [[Y]]
128; CHECK-NEXT:    [[TMP24:%.*]] = select i1 [[TMP22]], i32 [[TMP23]], i32 [[TMP21]]
129; CHECK-NEXT:    [[TMP25:%.*]] = icmp uge i32 [[TMP24]], [[Y]]
130; CHECK-NEXT:    [[TMP26:%.*]] = sub i32 [[TMP24]], [[Y]]
131; CHECK-NEXT:    [[TMP27:%.*]] = select i1 [[TMP25]], i32 [[TMP26]], i32 [[TMP24]]
132; CHECK-NEXT:    store i32 [[TMP27]], i32 addrspace(1)* [[OUT:%.*]], align 4
133; CHECK-NEXT:    ret void
134;
135; GFX6-LABEL: urem_i32:
136; GFX6:       ; %bb.0:
137; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
138; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
139; GFX6-NEXT:    s_mov_b32 s3, 0xf000
140; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
141; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s5
142; GFX6-NEXT:    s_sub_i32 s2, 0, s5
143; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
144; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
145; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
146; GFX6-NEXT:    v_mul_lo_u32 v1, s2, v0
147; GFX6-NEXT:    s_mov_b32 s2, -1
148; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
149; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
150; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
151; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s5
152; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
153; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s5, v0
154; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s5, v0
155; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
156; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s5, v0
157; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s5, v0
158; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
159; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
160; GFX6-NEXT:    s_endpgm
161;
162; GFX9-LABEL: urem_i32:
163; GFX9:       ; %bb.0:
164; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
165; GFX9-NEXT:    s_nop 0
166; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
167; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
168; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
169; GFX9-NEXT:    s_sub_i32 s4, 0, s3
170; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
171; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
172; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
173; GFX9-NEXT:    v_mul_lo_u32 v1, s4, v0
174; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
175; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
176; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
177; GFX9-NEXT:    v_mov_b32_e32 v1, 0
178; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
179; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
180; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v0
181; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v0
182; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
183; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v0
184; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v0
185; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
186; GFX9-NEXT:    global_store_dword v1, v0, s[0:1]
187; GFX9-NEXT:    s_endpgm
188  %r = urem i32 %x, %y
189  store i32 %r, i32 addrspace(1)* %out
190  ret void
191}
192
193define amdgpu_kernel void @sdiv_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
194; CHECK-LABEL: @sdiv_i32(
195; CHECK-NEXT:    [[TMP1:%.*]] = ashr i32 [[X:%.*]], 31
196; CHECK-NEXT:    [[TMP2:%.*]] = ashr i32 [[Y:%.*]], 31
197; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
198; CHECK-NEXT:    [[TMP4:%.*]] = add i32 [[X]], [[TMP1]]
199; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[Y]], [[TMP2]]
200; CHECK-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP4]], [[TMP1]]
201; CHECK-NEXT:    [[TMP7:%.*]] = xor i32 [[TMP5]], [[TMP2]]
202; CHECK-NEXT:    [[TMP8:%.*]] = uitofp i32 [[TMP7]] to float
203; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP8]])
204; CHECK-NEXT:    [[TMP10:%.*]] = fmul fast float [[TMP9]], 0x41EFFFFFC0000000
205; CHECK-NEXT:    [[TMP11:%.*]] = fptoui float [[TMP10]] to i32
206; CHECK-NEXT:    [[TMP12:%.*]] = sub i32 0, [[TMP7]]
207; CHECK-NEXT:    [[TMP13:%.*]] = mul i32 [[TMP12]], [[TMP11]]
208; CHECK-NEXT:    [[TMP14:%.*]] = zext i32 [[TMP11]] to i64
209; CHECK-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP13]] to i64
210; CHECK-NEXT:    [[TMP16:%.*]] = mul i64 [[TMP14]], [[TMP15]]
211; CHECK-NEXT:    [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32
212; CHECK-NEXT:    [[TMP18:%.*]] = lshr i64 [[TMP16]], 32
213; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
214; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP11]], [[TMP19]]
215; CHECK-NEXT:    [[TMP21:%.*]] = zext i32 [[TMP6]] to i64
216; CHECK-NEXT:    [[TMP22:%.*]] = zext i32 [[TMP20]] to i64
217; CHECK-NEXT:    [[TMP23:%.*]] = mul i64 [[TMP21]], [[TMP22]]
218; CHECK-NEXT:    [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32
219; CHECK-NEXT:    [[TMP25:%.*]] = lshr i64 [[TMP23]], 32
220; CHECK-NEXT:    [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32
221; CHECK-NEXT:    [[TMP27:%.*]] = mul i32 [[TMP26]], [[TMP7]]
222; CHECK-NEXT:    [[TMP28:%.*]] = sub i32 [[TMP6]], [[TMP27]]
223; CHECK-NEXT:    [[TMP29:%.*]] = icmp uge i32 [[TMP28]], [[TMP7]]
224; CHECK-NEXT:    [[TMP30:%.*]] = add i32 [[TMP26]], 1
225; CHECK-NEXT:    [[TMP31:%.*]] = select i1 [[TMP29]], i32 [[TMP30]], i32 [[TMP26]]
226; CHECK-NEXT:    [[TMP32:%.*]] = sub i32 [[TMP28]], [[TMP7]]
227; CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP29]], i32 [[TMP32]], i32 [[TMP28]]
228; CHECK-NEXT:    [[TMP34:%.*]] = icmp uge i32 [[TMP33]], [[TMP7]]
229; CHECK-NEXT:    [[TMP35:%.*]] = add i32 [[TMP31]], 1
230; CHECK-NEXT:    [[TMP36:%.*]] = select i1 [[TMP34]], i32 [[TMP35]], i32 [[TMP31]]
231; CHECK-NEXT:    [[TMP37:%.*]] = xor i32 [[TMP36]], [[TMP3]]
232; CHECK-NEXT:    [[TMP38:%.*]] = sub i32 [[TMP37]], [[TMP3]]
233; CHECK-NEXT:    store i32 [[TMP38]], i32 addrspace(1)* [[OUT:%.*]], align 4
234; CHECK-NEXT:    ret void
235;
236; GFX6-LABEL: sdiv_i32:
237; GFX6:       ; %bb.0:
238; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
239; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
240; GFX6-NEXT:    s_mov_b32 s7, 0xf000
241; GFX6-NEXT:    s_mov_b32 s6, -1
242; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
243; GFX6-NEXT:    s_ashr_i32 s8, s3, 31
244; GFX6-NEXT:    s_add_i32 s3, s3, s8
245; GFX6-NEXT:    s_xor_b32 s9, s3, s8
246; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s9
247; GFX6-NEXT:    s_sub_i32 s3, 0, s9
248; GFX6-NEXT:    s_ashr_i32 s0, s2, 31
249; GFX6-NEXT:    s_add_i32 s1, s2, s0
250; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
251; GFX6-NEXT:    s_xor_b32 s1, s1, s0
252; GFX6-NEXT:    s_xor_b32 s2, s0, s8
253; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
254; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
255; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v0
256; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
257; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
258; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
259; GFX6-NEXT:    v_mul_lo_u32 v1, v0, s9
260; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
261; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v1
262; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v1
263; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
264; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s9, v1
265; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[0:1]
266; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
267; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
268; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
269; GFX6-NEXT:    v_xor_b32_e32 v0, s2, v0
270; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
271; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
272; GFX6-NEXT:    s_endpgm
273;
274; GFX9-LABEL: sdiv_i32:
275; GFX9:       ; %bb.0:
276; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
277; GFX9-NEXT:    v_mov_b32_e32 v2, 0
278; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
279; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
280; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
281; GFX9-NEXT:    s_add_i32 s3, s3, s4
282; GFX9-NEXT:    s_xor_b32 s5, s3, s4
283; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s5
284; GFX9-NEXT:    s_sub_i32 s3, 0, s5
285; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
286; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
287; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
288; GFX9-NEXT:    v_mul_lo_u32 v1, s3, v0
289; GFX9-NEXT:    s_ashr_i32 s3, s2, 31
290; GFX9-NEXT:    s_add_i32 s2, s2, s3
291; GFX9-NEXT:    s_xor_b32 s2, s2, s3
292; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
293; GFX9-NEXT:    s_xor_b32 s3, s3, s4
294; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
295; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
296; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s5
297; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
298; GFX9-NEXT:    v_sub_u32_e32 v1, s2, v1
299; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v1
300; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
301; GFX9-NEXT:    v_subrev_u32_e32 v3, s5, v1
302; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
303; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
304; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v1
305; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
306; GFX9-NEXT:    v_xor_b32_e32 v0, s3, v0
307; GFX9-NEXT:    v_subrev_u32_e32 v0, s3, v0
308; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]
309; GFX9-NEXT:    s_endpgm
310  %r = sdiv i32 %x, %y
311  store i32 %r, i32 addrspace(1)* %out
312  ret void
313}
314
315define amdgpu_kernel void @srem_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
316; CHECK-LABEL: @srem_i32(
317; CHECK-NEXT:    [[TMP1:%.*]] = ashr i32 [[X:%.*]], 31
318; CHECK-NEXT:    [[TMP2:%.*]] = ashr i32 [[Y:%.*]], 31
319; CHECK-NEXT:    [[TMP3:%.*]] = add i32 [[X]], [[TMP1]]
320; CHECK-NEXT:    [[TMP4:%.*]] = add i32 [[Y]], [[TMP2]]
321; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP1]]
322; CHECK-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP4]], [[TMP2]]
323; CHECK-NEXT:    [[TMP7:%.*]] = uitofp i32 [[TMP6]] to float
324; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
325; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP8]], 0x41EFFFFFC0000000
326; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP9]] to i32
327; CHECK-NEXT:    [[TMP11:%.*]] = sub i32 0, [[TMP6]]
328; CHECK-NEXT:    [[TMP12:%.*]] = mul i32 [[TMP11]], [[TMP10]]
329; CHECK-NEXT:    [[TMP13:%.*]] = zext i32 [[TMP10]] to i64
330; CHECK-NEXT:    [[TMP14:%.*]] = zext i32 [[TMP12]] to i64
331; CHECK-NEXT:    [[TMP15:%.*]] = mul i64 [[TMP13]], [[TMP14]]
332; CHECK-NEXT:    [[TMP16:%.*]] = trunc i64 [[TMP15]] to i32
333; CHECK-NEXT:    [[TMP17:%.*]] = lshr i64 [[TMP15]], 32
334; CHECK-NEXT:    [[TMP18:%.*]] = trunc i64 [[TMP17]] to i32
335; CHECK-NEXT:    [[TMP19:%.*]] = add i32 [[TMP10]], [[TMP18]]
336; CHECK-NEXT:    [[TMP20:%.*]] = zext i32 [[TMP5]] to i64
337; CHECK-NEXT:    [[TMP21:%.*]] = zext i32 [[TMP19]] to i64
338; CHECK-NEXT:    [[TMP22:%.*]] = mul i64 [[TMP20]], [[TMP21]]
339; CHECK-NEXT:    [[TMP23:%.*]] = trunc i64 [[TMP22]] to i32
340; CHECK-NEXT:    [[TMP24:%.*]] = lshr i64 [[TMP22]], 32
341; CHECK-NEXT:    [[TMP25:%.*]] = trunc i64 [[TMP24]] to i32
342; CHECK-NEXT:    [[TMP26:%.*]] = mul i32 [[TMP25]], [[TMP6]]
343; CHECK-NEXT:    [[TMP27:%.*]] = sub i32 [[TMP5]], [[TMP26]]
344; CHECK-NEXT:    [[TMP28:%.*]] = icmp uge i32 [[TMP27]], [[TMP6]]
345; CHECK-NEXT:    [[TMP29:%.*]] = sub i32 [[TMP27]], [[TMP6]]
346; CHECK-NEXT:    [[TMP30:%.*]] = select i1 [[TMP28]], i32 [[TMP29]], i32 [[TMP27]]
347; CHECK-NEXT:    [[TMP31:%.*]] = icmp uge i32 [[TMP30]], [[TMP6]]
348; CHECK-NEXT:    [[TMP32:%.*]] = sub i32 [[TMP30]], [[TMP6]]
349; CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP31]], i32 [[TMP32]], i32 [[TMP30]]
350; CHECK-NEXT:    [[TMP34:%.*]] = xor i32 [[TMP33]], [[TMP1]]
351; CHECK-NEXT:    [[TMP35:%.*]] = sub i32 [[TMP34]], [[TMP1]]
352; CHECK-NEXT:    store i32 [[TMP35]], i32 addrspace(1)* [[OUT:%.*]], align 4
353; CHECK-NEXT:    ret void
354;
355; GFX6-LABEL: srem_i32:
356; GFX6:       ; %bb.0:
357; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
358; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
359; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
360; GFX6-NEXT:    s_ashr_i32 s4, s3, 31
361; GFX6-NEXT:    s_add_i32 s3, s3, s4
362; GFX6-NEXT:    s_xor_b32 s6, s3, s4
363; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s6
364; GFX6-NEXT:    s_sub_i32 s3, 0, s6
365; GFX6-NEXT:    s_ashr_i32 s4, s2, 31
366; GFX6-NEXT:    s_add_i32 s2, s2, s4
367; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
368; GFX6-NEXT:    s_xor_b32 s5, s2, s4
369; GFX6-NEXT:    s_mov_b32 s2, -1
370; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
371; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
372; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v0
373; GFX6-NEXT:    s_mov_b32 s3, 0xf000
374; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
375; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
376; GFX6-NEXT:    v_mul_hi_u32 v0, s5, v0
377; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s6
378; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
379; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s6, v0
380; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
381; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
382; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s6, v0
383; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
384; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
385; GFX6-NEXT:    v_xor_b32_e32 v0, s4, v0
386; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s4, v0
387; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
388; GFX6-NEXT:    s_endpgm
389;
390; GFX9-LABEL: srem_i32:
391; GFX9:       ; %bb.0:
392; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
393; GFX9-NEXT:    s_nop 0
394; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
395; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
396; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
397; GFX9-NEXT:    s_add_i32 s3, s3, s4
398; GFX9-NEXT:    s_xor_b32 s3, s3, s4
399; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
400; GFX9-NEXT:    s_sub_i32 s4, 0, s3
401; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
402; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
403; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
404; GFX9-NEXT:    v_mul_lo_u32 v1, s4, v0
405; GFX9-NEXT:    s_ashr_i32 s4, s2, 31
406; GFX9-NEXT:    s_add_i32 s2, s2, s4
407; GFX9-NEXT:    s_xor_b32 s2, s2, s4
408; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
409; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
410; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
411; GFX9-NEXT:    v_mov_b32_e32 v1, 0
412; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
413; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
414; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v0
415; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v0
416; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
417; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v0
418; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v0
419; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
420; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v0
421; GFX9-NEXT:    v_subrev_u32_e32 v0, s4, v0
422; GFX9-NEXT:    global_store_dword v1, v0, s[0:1]
423; GFX9-NEXT:    s_endpgm
424  %r = srem i32 %x, %y
425  store i32 %r, i32 addrspace(1)* %out
426  ret void
427}
428
429define amdgpu_kernel void @udiv_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
430; CHECK-LABEL: @udiv_i16(
431; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[X:%.*]] to i32
432; CHECK-NEXT:    [[TMP2:%.*]] = zext i16 [[Y:%.*]] to i32
433; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
434; CHECK-NEXT:    [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
435; CHECK-NEXT:    [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
436; CHECK-NEXT:    [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
437; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
438; CHECK-NEXT:    [[TMP8:%.*]] = fneg fast float [[TMP7]]
439; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
440; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
441; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
442; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
443; CHECK-NEXT:    [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
444; CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
445; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
446; CHECK-NEXT:    [[TMP16:%.*]] = and i32 [[TMP15]], 65535
447; CHECK-NEXT:    [[TMP17:%.*]] = trunc i32 [[TMP16]] to i16
448; CHECK-NEXT:    store i16 [[TMP17]], i16 addrspace(1)* [[OUT:%.*]], align 2
449; CHECK-NEXT:    ret void
450;
451; GFX6-LABEL: udiv_i16:
452; GFX6:       ; %bb.0:
453; GFX6-NEXT:    s_load_dword s2, s[0:1], 0xb
454; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
455; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
456; GFX6-NEXT:    s_lshr_b32 s3, s2, 16
457; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s3
458; GFX6-NEXT:    s_and_b32 s2, s2, 0xffff
459; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s2
460; GFX6-NEXT:    s_mov_b32 s3, 0xf000
461; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
462; GFX6-NEXT:    s_mov_b32 s2, -1
463; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
464; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
465; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v2
466; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
467; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
468; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
469; GFX6-NEXT:    buffer_store_short v0, off, s[0:3], 0
470; GFX6-NEXT:    s_endpgm
471;
472; GFX9-LABEL: udiv_i16:
473; GFX9:       ; %bb.0:
474; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
475; GFX9-NEXT:    v_mov_b32_e32 v3, 0
476; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
477; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
478; GFX9-NEXT:    s_lshr_b32 s3, s2, 16
479; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
480; GFX9-NEXT:    s_and_b32 s2, s2, 0xffff
481; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s2
482; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
483; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
484; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
485; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v2
486; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
487; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
488; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v4, vcc
489; GFX9-NEXT:    global_store_short v3, v0, s[0:1]
490; GFX9-NEXT:    s_endpgm
491  %r = udiv i16 %x, %y
492  store i16 %r, i16 addrspace(1)* %out
493  ret void
494}
495
496define amdgpu_kernel void @urem_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
497; CHECK-LABEL: @urem_i16(
498; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[X:%.*]] to i32
499; CHECK-NEXT:    [[TMP2:%.*]] = zext i16 [[Y:%.*]] to i32
500; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
501; CHECK-NEXT:    [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
502; CHECK-NEXT:    [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
503; CHECK-NEXT:    [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
504; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
505; CHECK-NEXT:    [[TMP8:%.*]] = fneg fast float [[TMP7]]
506; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
507; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
508; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
509; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
510; CHECK-NEXT:    [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
511; CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
512; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
513; CHECK-NEXT:    [[TMP16:%.*]] = mul i32 [[TMP15]], [[TMP2]]
514; CHECK-NEXT:    [[TMP17:%.*]] = sub i32 [[TMP1]], [[TMP16]]
515; CHECK-NEXT:    [[TMP18:%.*]] = and i32 [[TMP17]], 65535
516; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i16
517; CHECK-NEXT:    store i16 [[TMP19]], i16 addrspace(1)* [[OUT:%.*]], align 2
518; CHECK-NEXT:    ret void
519;
520; GFX6-LABEL: urem_i16:
521; GFX6:       ; %bb.0:
522; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
523; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
524; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
525; GFX6-NEXT:    s_lshr_b32 s2, s4, 16
526; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s2
527; GFX6-NEXT:    s_and_b32 s3, s4, 0xffff
528; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s3
529; GFX6-NEXT:    s_mov_b32 s3, 0xf000
530; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
531; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
532; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
533; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v2
534; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
535; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
536; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
537; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
538; GFX6-NEXT:    s_mov_b32 s2, -1
539; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
540; GFX6-NEXT:    buffer_store_short v0, off, s[0:3], 0
541; GFX6-NEXT:    s_endpgm
542;
543; GFX9-LABEL: urem_i16:
544; GFX9:       ; %bb.0:
545; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
546; GFX9-NEXT:    s_nop 0
547; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
548; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
549; GFX9-NEXT:    s_lshr_b32 s3, s2, 16
550; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
551; GFX9-NEXT:    s_and_b32 s4, s2, 0xffff
552; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s4
553; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
554; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
555; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
556; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v2
557; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
558; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
559; GFX9-NEXT:    v_mov_b32_e32 v1, 0
560; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
561; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
562; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
563; GFX9-NEXT:    global_store_short v1, v0, s[0:1]
564; GFX9-NEXT:    s_endpgm
565  %r = urem i16 %x, %y
566  store i16 %r, i16 addrspace(1)* %out
567  ret void
568}
569
570define amdgpu_kernel void @sdiv_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
571; CHECK-LABEL: @sdiv_i16(
572; CHECK-NEXT:    [[TMP1:%.*]] = sext i16 [[X:%.*]] to i32
573; CHECK-NEXT:    [[TMP2:%.*]] = sext i16 [[Y:%.*]] to i32
574; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
575; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
576; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP4]], 1
577; CHECK-NEXT:    [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
578; CHECK-NEXT:    [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
579; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
580; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
581; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
582; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
583; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
584; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
585; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
586; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
587; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
588; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
589; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
590; CHECK-NEXT:    [[TMP19:%.*]] = shl i32 [[TMP18]], 16
591; CHECK-NEXT:    [[TMP20:%.*]] = ashr i32 [[TMP19]], 16
592; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i16
593; CHECK-NEXT:    store i16 [[TMP21]], i16 addrspace(1)* [[OUT:%.*]], align 2
594; CHECK-NEXT:    ret void
595;
596; GFX6-LABEL: sdiv_i16:
597; GFX6:       ; %bb.0:
598; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
599; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
600; GFX6-NEXT:    s_mov_b32 s7, 0xf000
601; GFX6-NEXT:    s_mov_b32 s6, -1
602; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
603; GFX6-NEXT:    s_ashr_i32 s1, s0, 16
604; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s1
605; GFX6-NEXT:    s_sext_i32_i16 s0, s0
606; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s0
607; GFX6-NEXT:    s_xor_b32 s0, s0, s1
608; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
609; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
610; GFX6-NEXT:    s_or_b32 s0, s0, 1
611; GFX6-NEXT:    v_mov_b32_e32 v3, s0
612; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
613; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
614; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
615; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
616; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
617; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
618; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
619; GFX6-NEXT:    buffer_store_short v0, off, s[4:7], 0
620; GFX6-NEXT:    s_endpgm
621;
622; GFX9-LABEL: sdiv_i16:
623; GFX9:       ; %bb.0:
624; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
625; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
626; GFX9-NEXT:    v_mov_b32_e32 v1, 0
627; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
628; GFX9-NEXT:    s_ashr_i32 s0, s4, 16
629; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s0
630; GFX9-NEXT:    s_sext_i32_i16 s1, s4
631; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s1
632; GFX9-NEXT:    s_xor_b32 s0, s1, s0
633; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
634; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
635; GFX9-NEXT:    s_or_b32 s4, s0, 1
636; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
637; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
638; GFX9-NEXT:    v_mad_f32 v2, -v3, v0, v2
639; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
640; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
641; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
642; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
643; GFX9-NEXT:    v_add_u32_e32 v0, s0, v3
644; GFX9-NEXT:    global_store_short v1, v0, s[2:3]
645; GFX9-NEXT:    s_endpgm
646  %r = sdiv i16 %x, %y
647  store i16 %r, i16 addrspace(1)* %out
648  ret void
649}
650
651define amdgpu_kernel void @srem_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
652; CHECK-LABEL: @srem_i16(
653; CHECK-NEXT:    [[TMP1:%.*]] = sext i16 [[X:%.*]] to i32
654; CHECK-NEXT:    [[TMP2:%.*]] = sext i16 [[Y:%.*]] to i32
655; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
656; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
657; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP4]], 1
658; CHECK-NEXT:    [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
659; CHECK-NEXT:    [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
660; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
661; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
662; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
663; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
664; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
665; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
666; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
667; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
668; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
669; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
670; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
671; CHECK-NEXT:    [[TMP19:%.*]] = mul i32 [[TMP18]], [[TMP2]]
672; CHECK-NEXT:    [[TMP20:%.*]] = sub i32 [[TMP1]], [[TMP19]]
673; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 16
674; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 16
675; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i16
676; CHECK-NEXT:    store i16 [[TMP23]], i16 addrspace(1)* [[OUT:%.*]], align 2
677; CHECK-NEXT:    ret void
678;
679; GFX6-LABEL: srem_i16:
680; GFX6:       ; %bb.0:
681; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
682; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
683; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
684; GFX6-NEXT:    s_ashr_i32 s2, s4, 16
685; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s2
686; GFX6-NEXT:    s_sext_i32_i16 s3, s4
687; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s3
688; GFX6-NEXT:    s_xor_b32 s3, s3, s2
689; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
690; GFX6-NEXT:    s_ashr_i32 s3, s3, 30
691; GFX6-NEXT:    s_or_b32 s3, s3, 1
692; GFX6-NEXT:    v_mov_b32_e32 v3, s3
693; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
694; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
695; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
696; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
697; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
698; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
699; GFX6-NEXT:    s_mov_b32 s3, 0xf000
700; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
701; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
702; GFX6-NEXT:    s_mov_b32 s2, -1
703; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
704; GFX6-NEXT:    buffer_store_short v0, off, s[0:3], 0
705; GFX6-NEXT:    s_endpgm
706;
707; GFX9-LABEL: srem_i16:
708; GFX9:       ; %bb.0:
709; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
710; GFX9-NEXT:    s_nop 0
711; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
712; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
713; GFX9-NEXT:    s_ashr_i32 s5, s4, 16
714; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s5
715; GFX9-NEXT:    s_sext_i32_i16 s2, s4
716; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s2
717; GFX9-NEXT:    s_xor_b32 s2, s2, s5
718; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
719; GFX9-NEXT:    s_ashr_i32 s2, s2, 30
720; GFX9-NEXT:    s_or_b32 s6, s2, 1
721; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
722; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
723; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
724; GFX9-NEXT:    v_cvt_i32_f32_e32 v2, v2
725; GFX9-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|
726; GFX9-NEXT:    s_cmp_lg_u64 s[2:3], 0
727; GFX9-NEXT:    s_cselect_b32 s2, s6, 0
728; GFX9-NEXT:    v_add_u32_e32 v0, s2, v2
729; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s5
730; GFX9-NEXT:    v_mov_b32_e32 v1, 0
731; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
732; GFX9-NEXT:    global_store_short v1, v0, s[0:1]
733; GFX9-NEXT:    s_endpgm
734  %r = srem i16 %x, %y
735  store i16 %r, i16 addrspace(1)* %out
736  ret void
737}
738
739define amdgpu_kernel void @udiv_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
740; CHECK-LABEL: @udiv_i8(
741; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[X:%.*]] to i32
742; CHECK-NEXT:    [[TMP2:%.*]] = zext i8 [[Y:%.*]] to i32
743; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
744; CHECK-NEXT:    [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
745; CHECK-NEXT:    [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
746; CHECK-NEXT:    [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
747; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
748; CHECK-NEXT:    [[TMP8:%.*]] = fneg fast float [[TMP7]]
749; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
750; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
751; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
752; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
753; CHECK-NEXT:    [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
754; CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
755; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
756; CHECK-NEXT:    [[TMP16:%.*]] = and i32 [[TMP15]], 255
757; CHECK-NEXT:    [[TMP17:%.*]] = trunc i32 [[TMP16]] to i8
758; CHECK-NEXT:    store i8 [[TMP17]], i8 addrspace(1)* [[OUT:%.*]], align 1
759; CHECK-NEXT:    ret void
760;
761; GFX6-LABEL: udiv_i8:
762; GFX6:       ; %bb.0:
763; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
764; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
765; GFX6-NEXT:    s_mov_b32 s7, 0xf000
766; GFX6-NEXT:    s_mov_b32 s6, -1
767; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
768; GFX6-NEXT:    v_cvt_f32_ubyte1_e32 v0, s0
769; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v0
770; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v2, s0
771; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1
772; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
773; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v1
774; GFX6-NEXT:    v_mad_f32 v1, -v1, v0, v2
775; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
776; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
777; GFX6-NEXT:    buffer_store_byte v0, off, s[4:7], 0
778; GFX6-NEXT:    s_endpgm
779;
780; GFX9-LABEL: udiv_i8:
781; GFX9:       ; %bb.0:
782; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
783; GFX9-NEXT:    v_mov_b32_e32 v2, 0
784; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
785; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
786; GFX9-NEXT:    v_cvt_f32_ubyte1_e32 v0, s2
787; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
788; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v3, s2
789; GFX9-NEXT:    v_mul_f32_e32 v1, v3, v1
790; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
791; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v1
792; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v3
793; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
794; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v4, vcc
795; GFX9-NEXT:    global_store_byte v2, v0, s[0:1]
796; GFX9-NEXT:    s_endpgm
797  %r = udiv i8 %x, %y
798  store i8 %r, i8 addrspace(1)* %out
799  ret void
800}
801
802define amdgpu_kernel void @urem_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
803; CHECK-LABEL: @urem_i8(
804; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[X:%.*]] to i32
805; CHECK-NEXT:    [[TMP2:%.*]] = zext i8 [[Y:%.*]] to i32
806; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
807; CHECK-NEXT:    [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
808; CHECK-NEXT:    [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
809; CHECK-NEXT:    [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
810; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
811; CHECK-NEXT:    [[TMP8:%.*]] = fneg fast float [[TMP7]]
812; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
813; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
814; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
815; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
816; CHECK-NEXT:    [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
817; CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
818; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
819; CHECK-NEXT:    [[TMP16:%.*]] = mul i32 [[TMP15]], [[TMP2]]
820; CHECK-NEXT:    [[TMP17:%.*]] = sub i32 [[TMP1]], [[TMP16]]
821; CHECK-NEXT:    [[TMP18:%.*]] = and i32 [[TMP17]], 255
822; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i8
823; CHECK-NEXT:    store i8 [[TMP19]], i8 addrspace(1)* [[OUT:%.*]], align 1
824; CHECK-NEXT:    ret void
825;
826; GFX6-LABEL: urem_i8:
827; GFX6:       ; %bb.0:
828; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
829; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
830; GFX6-NEXT:    s_mov_b32 s3, 0xf000
831; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
832; GFX6-NEXT:    v_cvt_f32_ubyte1_e32 v0, s4
833; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v0
834; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v2, s4
835; GFX6-NEXT:    s_lshr_b32 s2, s4, 8
836; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1
837; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
838; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v1
839; GFX6-NEXT:    v_mad_f32 v1, -v1, v0, v2
840; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
841; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
842; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
843; GFX6-NEXT:    s_mov_b32 s2, -1
844; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
845; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
846; GFX6-NEXT:    s_endpgm
847;
848; GFX9-LABEL: urem_i8:
849; GFX9:       ; %bb.0:
850; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
851; GFX9-NEXT:    s_nop 0
852; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
853; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
854; GFX9-NEXT:    v_cvt_f32_ubyte1_e32 v0, s2
855; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
856; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v2, s2
857; GFX9-NEXT:    s_lshr_b32 s3, s2, 8
858; GFX9-NEXT:    v_mul_f32_e32 v1, v2, v1
859; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
860; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v1
861; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v2
862; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
863; GFX9-NEXT:    v_mov_b32_e32 v1, 0
864; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
865; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
866; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
867; GFX9-NEXT:    global_store_byte v1, v0, s[0:1]
868; GFX9-NEXT:    s_endpgm
869  %r = urem i8 %x, %y
870  store i8 %r, i8 addrspace(1)* %out
871  ret void
872}
873
874define amdgpu_kernel void @sdiv_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
875; CHECK-LABEL: @sdiv_i8(
876; CHECK-NEXT:    [[TMP1:%.*]] = sext i8 [[X:%.*]] to i32
877; CHECK-NEXT:    [[TMP2:%.*]] = sext i8 [[Y:%.*]] to i32
878; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
879; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
880; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP4]], 1
881; CHECK-NEXT:    [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
882; CHECK-NEXT:    [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
883; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
884; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
885; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
886; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
887; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
888; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
889; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
890; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
891; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
892; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
893; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
894; CHECK-NEXT:    [[TMP19:%.*]] = shl i32 [[TMP18]], 24
895; CHECK-NEXT:    [[TMP20:%.*]] = ashr i32 [[TMP19]], 24
896; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i8
897; CHECK-NEXT:    store i8 [[TMP21]], i8 addrspace(1)* [[OUT:%.*]], align 1
898; CHECK-NEXT:    ret void
899;
900; GFX6-LABEL: sdiv_i8:
901; GFX6:       ; %bb.0:
902; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
903; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
904; GFX6-NEXT:    s_mov_b32 s7, 0xf000
905; GFX6-NEXT:    s_mov_b32 s6, -1
906; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
907; GFX6-NEXT:    s_bfe_i32 s1, s0, 0x80008
908; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s1
909; GFX6-NEXT:    s_sext_i32_i8 s0, s0
910; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s0
911; GFX6-NEXT:    s_xor_b32 s0, s0, s1
912; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
913; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
914; GFX6-NEXT:    s_or_b32 s0, s0, 1
915; GFX6-NEXT:    v_mov_b32_e32 v3, s0
916; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
917; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
918; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
919; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
920; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
921; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
922; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
923; GFX6-NEXT:    buffer_store_byte v0, off, s[4:7], 0
924; GFX6-NEXT:    s_endpgm
925;
926; GFX9-LABEL: sdiv_i8:
927; GFX9:       ; %bb.0:
928; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
929; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
930; GFX9-NEXT:    v_mov_b32_e32 v1, 0
931; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
932; GFX9-NEXT:    s_bfe_i32 s0, s4, 0x80008
933; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s0
934; GFX9-NEXT:    s_sext_i32_i8 s1, s4
935; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s1
936; GFX9-NEXT:    s_xor_b32 s0, s1, s0
937; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
938; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
939; GFX9-NEXT:    s_or_b32 s4, s0, 1
940; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
941; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
942; GFX9-NEXT:    v_mad_f32 v2, -v3, v0, v2
943; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
944; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
945; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
946; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
947; GFX9-NEXT:    v_add_u32_e32 v0, s0, v3
948; GFX9-NEXT:    global_store_byte v1, v0, s[2:3]
949; GFX9-NEXT:    s_endpgm
950  %r = sdiv i8 %x, %y
951  store i8 %r, i8 addrspace(1)* %out
952  ret void
953}
954
955define amdgpu_kernel void @srem_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
956; CHECK-LABEL: @srem_i8(
957; CHECK-NEXT:    [[TMP1:%.*]] = sext i8 [[X:%.*]] to i32
958; CHECK-NEXT:    [[TMP2:%.*]] = sext i8 [[Y:%.*]] to i32
959; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
960; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
961; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP4]], 1
962; CHECK-NEXT:    [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
963; CHECK-NEXT:    [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
964; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
965; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
966; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
967; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
968; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
969; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
970; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
971; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
972; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
973; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
974; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
975; CHECK-NEXT:    [[TMP19:%.*]] = mul i32 [[TMP18]], [[TMP2]]
976; CHECK-NEXT:    [[TMP20:%.*]] = sub i32 [[TMP1]], [[TMP19]]
977; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 24
978; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 24
979; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i8
980; CHECK-NEXT:    store i8 [[TMP23]], i8 addrspace(1)* [[OUT:%.*]], align 1
981; CHECK-NEXT:    ret void
982;
983; GFX6-LABEL: srem_i8:
984; GFX6:       ; %bb.0:
985; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
986; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
987; GFX6-NEXT:    s_mov_b32 s7, 0xf000
988; GFX6-NEXT:    s_mov_b32 s6, -1
989; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
990; GFX6-NEXT:    s_bfe_i32 s1, s0, 0x80008
991; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s1
992; GFX6-NEXT:    s_sext_i32_i8 s3, s0
993; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s3
994; GFX6-NEXT:    s_xor_b32 s1, s3, s1
995; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
996; GFX6-NEXT:    s_ashr_i32 s1, s1, 30
997; GFX6-NEXT:    s_or_b32 s1, s1, 1
998; GFX6-NEXT:    v_mov_b32_e32 v3, s1
999; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
1000; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
1001; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
1002; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
1003; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
1004; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
1005; GFX6-NEXT:    s_lshr_b32 s2, s0, 8
1006; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1007; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
1008; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
1009; GFX6-NEXT:    buffer_store_byte v0, off, s[4:7], 0
1010; GFX6-NEXT:    s_endpgm
1011;
1012; GFX9-LABEL: srem_i8:
1013; GFX9:       ; %bb.0:
1014; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
1015; GFX9-NEXT:    s_nop 0
1016; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
1017; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1018; GFX9-NEXT:    s_bfe_i32 s2, s4, 0x80008
1019; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s2
1020; GFX9-NEXT:    s_sext_i32_i8 s3, s4
1021; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s3
1022; GFX9-NEXT:    s_xor_b32 s2, s3, s2
1023; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
1024; GFX9-NEXT:    s_ashr_i32 s2, s2, 30
1025; GFX9-NEXT:    s_lshr_b32 s5, s4, 8
1026; GFX9-NEXT:    s_or_b32 s6, s2, 1
1027; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
1028; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
1029; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
1030; GFX9-NEXT:    v_cvt_i32_f32_e32 v2, v2
1031; GFX9-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|
1032; GFX9-NEXT:    s_cmp_lg_u64 s[2:3], 0
1033; GFX9-NEXT:    s_cselect_b32 s2, s6, 0
1034; GFX9-NEXT:    v_add_u32_e32 v0, s2, v2
1035; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s5
1036; GFX9-NEXT:    v_mov_b32_e32 v1, 0
1037; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
1038; GFX9-NEXT:    global_store_byte v1, v0, s[0:1]
1039; GFX9-NEXT:    s_endpgm
1040  %r = srem i8 %x, %y
1041  store i8 %r, i8 addrspace(1)* %out
1042  ret void
1043}
1044
1045define amdgpu_kernel void @udiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
1046; CHECK-LABEL: @udiv_v4i32(
1047; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i64 0
1048; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 0
1049; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float
1050; CHECK-NEXT:    [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])
1051; CHECK-NEXT:    [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41EFFFFFC0000000
1052; CHECK-NEXT:    [[TMP6:%.*]] = fptoui float [[TMP5]] to i32
1053; CHECK-NEXT:    [[TMP7:%.*]] = sub i32 0, [[TMP2]]
1054; CHECK-NEXT:    [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP6]]
1055; CHECK-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP6]] to i64
1056; CHECK-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP8]] to i64
1057; CHECK-NEXT:    [[TMP11:%.*]] = mul i64 [[TMP9]], [[TMP10]]
1058; CHECK-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
1059; CHECK-NEXT:    [[TMP13:%.*]] = lshr i64 [[TMP11]], 32
1060; CHECK-NEXT:    [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32
1061; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP6]], [[TMP14]]
1062; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP1]] to i64
1063; CHECK-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP15]] to i64
1064; CHECK-NEXT:    [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]
1065; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
1066; CHECK-NEXT:    [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
1067; CHECK-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
1068; CHECK-NEXT:    [[TMP22:%.*]] = mul i32 [[TMP21]], [[TMP2]]
1069; CHECK-NEXT:    [[TMP23:%.*]] = sub i32 [[TMP1]], [[TMP22]]
1070; CHECK-NEXT:    [[TMP24:%.*]] = icmp uge i32 [[TMP23]], [[TMP2]]
1071; CHECK-NEXT:    [[TMP25:%.*]] = add i32 [[TMP21]], 1
1072; CHECK-NEXT:    [[TMP26:%.*]] = select i1 [[TMP24]], i32 [[TMP25]], i32 [[TMP21]]
1073; CHECK-NEXT:    [[TMP27:%.*]] = sub i32 [[TMP23]], [[TMP2]]
1074; CHECK-NEXT:    [[TMP28:%.*]] = select i1 [[TMP24]], i32 [[TMP27]], i32 [[TMP23]]
1075; CHECK-NEXT:    [[TMP29:%.*]] = icmp uge i32 [[TMP28]], [[TMP2]]
1076; CHECK-NEXT:    [[TMP30:%.*]] = add i32 [[TMP26]], 1
1077; CHECK-NEXT:    [[TMP31:%.*]] = select i1 [[TMP29]], i32 [[TMP30]], i32 [[TMP26]]
1078; CHECK-NEXT:    [[TMP32:%.*]] = insertelement <4 x i32> undef, i32 [[TMP31]], i64 0
1079; CHECK-NEXT:    [[TMP33:%.*]] = extractelement <4 x i32> [[X]], i64 1
1080; CHECK-NEXT:    [[TMP34:%.*]] = extractelement <4 x i32> [[Y]], i64 1
1081; CHECK-NEXT:    [[TMP35:%.*]] = uitofp i32 [[TMP34]] to float
1082; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])
1083; CHECK-NEXT:    [[TMP37:%.*]] = fmul fast float [[TMP36]], 0x41EFFFFFC0000000
1084; CHECK-NEXT:    [[TMP38:%.*]] = fptoui float [[TMP37]] to i32
1085; CHECK-NEXT:    [[TMP39:%.*]] = sub i32 0, [[TMP34]]
1086; CHECK-NEXT:    [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP38]]
1087; CHECK-NEXT:    [[TMP41:%.*]] = zext i32 [[TMP38]] to i64
1088; CHECK-NEXT:    [[TMP42:%.*]] = zext i32 [[TMP40]] to i64
1089; CHECK-NEXT:    [[TMP43:%.*]] = mul i64 [[TMP41]], [[TMP42]]
1090; CHECK-NEXT:    [[TMP44:%.*]] = trunc i64 [[TMP43]] to i32
1091; CHECK-NEXT:    [[TMP45:%.*]] = lshr i64 [[TMP43]], 32
1092; CHECK-NEXT:    [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32
1093; CHECK-NEXT:    [[TMP47:%.*]] = add i32 [[TMP38]], [[TMP46]]
1094; CHECK-NEXT:    [[TMP48:%.*]] = zext i32 [[TMP33]] to i64
1095; CHECK-NEXT:    [[TMP49:%.*]] = zext i32 [[TMP47]] to i64
1096; CHECK-NEXT:    [[TMP50:%.*]] = mul i64 [[TMP48]], [[TMP49]]
1097; CHECK-NEXT:    [[TMP51:%.*]] = trunc i64 [[TMP50]] to i32
1098; CHECK-NEXT:    [[TMP52:%.*]] = lshr i64 [[TMP50]], 32
1099; CHECK-NEXT:    [[TMP53:%.*]] = trunc i64 [[TMP52]] to i32
1100; CHECK-NEXT:    [[TMP54:%.*]] = mul i32 [[TMP53]], [[TMP34]]
1101; CHECK-NEXT:    [[TMP55:%.*]] = sub i32 [[TMP33]], [[TMP54]]
1102; CHECK-NEXT:    [[TMP56:%.*]] = icmp uge i32 [[TMP55]], [[TMP34]]
1103; CHECK-NEXT:    [[TMP57:%.*]] = add i32 [[TMP53]], 1
1104; CHECK-NEXT:    [[TMP58:%.*]] = select i1 [[TMP56]], i32 [[TMP57]], i32 [[TMP53]]
1105; CHECK-NEXT:    [[TMP59:%.*]] = sub i32 [[TMP55]], [[TMP34]]
1106; CHECK-NEXT:    [[TMP60:%.*]] = select i1 [[TMP56]], i32 [[TMP59]], i32 [[TMP55]]
1107; CHECK-NEXT:    [[TMP61:%.*]] = icmp uge i32 [[TMP60]], [[TMP34]]
1108; CHECK-NEXT:    [[TMP62:%.*]] = add i32 [[TMP58]], 1
1109; CHECK-NEXT:    [[TMP63:%.*]] = select i1 [[TMP61]], i32 [[TMP62]], i32 [[TMP58]]
1110; CHECK-NEXT:    [[TMP64:%.*]] = insertelement <4 x i32> [[TMP32]], i32 [[TMP63]], i64 1
1111; CHECK-NEXT:    [[TMP65:%.*]] = extractelement <4 x i32> [[X]], i64 2
1112; CHECK-NEXT:    [[TMP66:%.*]] = extractelement <4 x i32> [[Y]], i64 2
1113; CHECK-NEXT:    [[TMP67:%.*]] = uitofp i32 [[TMP66]] to float
1114; CHECK-NEXT:    [[TMP68:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP67]])
1115; CHECK-NEXT:    [[TMP69:%.*]] = fmul fast float [[TMP68]], 0x41EFFFFFC0000000
1116; CHECK-NEXT:    [[TMP70:%.*]] = fptoui float [[TMP69]] to i32
1117; CHECK-NEXT:    [[TMP71:%.*]] = sub i32 0, [[TMP66]]
1118; CHECK-NEXT:    [[TMP72:%.*]] = mul i32 [[TMP71]], [[TMP70]]
1119; CHECK-NEXT:    [[TMP73:%.*]] = zext i32 [[TMP70]] to i64
1120; CHECK-NEXT:    [[TMP74:%.*]] = zext i32 [[TMP72]] to i64
1121; CHECK-NEXT:    [[TMP75:%.*]] = mul i64 [[TMP73]], [[TMP74]]
1122; CHECK-NEXT:    [[TMP76:%.*]] = trunc i64 [[TMP75]] to i32
1123; CHECK-NEXT:    [[TMP77:%.*]] = lshr i64 [[TMP75]], 32
1124; CHECK-NEXT:    [[TMP78:%.*]] = trunc i64 [[TMP77]] to i32
1125; CHECK-NEXT:    [[TMP79:%.*]] = add i32 [[TMP70]], [[TMP78]]
1126; CHECK-NEXT:    [[TMP80:%.*]] = zext i32 [[TMP65]] to i64
1127; CHECK-NEXT:    [[TMP81:%.*]] = zext i32 [[TMP79]] to i64
1128; CHECK-NEXT:    [[TMP82:%.*]] = mul i64 [[TMP80]], [[TMP81]]
1129; CHECK-NEXT:    [[TMP83:%.*]] = trunc i64 [[TMP82]] to i32
1130; CHECK-NEXT:    [[TMP84:%.*]] = lshr i64 [[TMP82]], 32
1131; CHECK-NEXT:    [[TMP85:%.*]] = trunc i64 [[TMP84]] to i32
1132; CHECK-NEXT:    [[TMP86:%.*]] = mul i32 [[TMP85]], [[TMP66]]
1133; CHECK-NEXT:    [[TMP87:%.*]] = sub i32 [[TMP65]], [[TMP86]]
1134; CHECK-NEXT:    [[TMP88:%.*]] = icmp uge i32 [[TMP87]], [[TMP66]]
1135; CHECK-NEXT:    [[TMP89:%.*]] = add i32 [[TMP85]], 1
1136; CHECK-NEXT:    [[TMP90:%.*]] = select i1 [[TMP88]], i32 [[TMP89]], i32 [[TMP85]]
1137; CHECK-NEXT:    [[TMP91:%.*]] = sub i32 [[TMP87]], [[TMP66]]
1138; CHECK-NEXT:    [[TMP92:%.*]] = select i1 [[TMP88]], i32 [[TMP91]], i32 [[TMP87]]
1139; CHECK-NEXT:    [[TMP93:%.*]] = icmp uge i32 [[TMP92]], [[TMP66]]
1140; CHECK-NEXT:    [[TMP94:%.*]] = add i32 [[TMP90]], 1
1141; CHECK-NEXT:    [[TMP95:%.*]] = select i1 [[TMP93]], i32 [[TMP94]], i32 [[TMP90]]
1142; CHECK-NEXT:    [[TMP96:%.*]] = insertelement <4 x i32> [[TMP64]], i32 [[TMP95]], i64 2
1143; CHECK-NEXT:    [[TMP97:%.*]] = extractelement <4 x i32> [[X]], i64 3
1144; CHECK-NEXT:    [[TMP98:%.*]] = extractelement <4 x i32> [[Y]], i64 3
1145; CHECK-NEXT:    [[TMP99:%.*]] = uitofp i32 [[TMP98]] to float
1146; CHECK-NEXT:    [[TMP100:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP99]])
1147; CHECK-NEXT:    [[TMP101:%.*]] = fmul fast float [[TMP100]], 0x41EFFFFFC0000000
1148; CHECK-NEXT:    [[TMP102:%.*]] = fptoui float [[TMP101]] to i32
1149; CHECK-NEXT:    [[TMP103:%.*]] = sub i32 0, [[TMP98]]
1150; CHECK-NEXT:    [[TMP104:%.*]] = mul i32 [[TMP103]], [[TMP102]]
1151; CHECK-NEXT:    [[TMP105:%.*]] = zext i32 [[TMP102]] to i64
1152; CHECK-NEXT:    [[TMP106:%.*]] = zext i32 [[TMP104]] to i64
1153; CHECK-NEXT:    [[TMP107:%.*]] = mul i64 [[TMP105]], [[TMP106]]
1154; CHECK-NEXT:    [[TMP108:%.*]] = trunc i64 [[TMP107]] to i32
1155; CHECK-NEXT:    [[TMP109:%.*]] = lshr i64 [[TMP107]], 32
1156; CHECK-NEXT:    [[TMP110:%.*]] = trunc i64 [[TMP109]] to i32
1157; CHECK-NEXT:    [[TMP111:%.*]] = add i32 [[TMP102]], [[TMP110]]
1158; CHECK-NEXT:    [[TMP112:%.*]] = zext i32 [[TMP97]] to i64
1159; CHECK-NEXT:    [[TMP113:%.*]] = zext i32 [[TMP111]] to i64
1160; CHECK-NEXT:    [[TMP114:%.*]] = mul i64 [[TMP112]], [[TMP113]]
1161; CHECK-NEXT:    [[TMP115:%.*]] = trunc i64 [[TMP114]] to i32
1162; CHECK-NEXT:    [[TMP116:%.*]] = lshr i64 [[TMP114]], 32
1163; CHECK-NEXT:    [[TMP117:%.*]] = trunc i64 [[TMP116]] to i32
1164; CHECK-NEXT:    [[TMP118:%.*]] = mul i32 [[TMP117]], [[TMP98]]
1165; CHECK-NEXT:    [[TMP119:%.*]] = sub i32 [[TMP97]], [[TMP118]]
1166; CHECK-NEXT:    [[TMP120:%.*]] = icmp uge i32 [[TMP119]], [[TMP98]]
1167; CHECK-NEXT:    [[TMP121:%.*]] = add i32 [[TMP117]], 1
1168; CHECK-NEXT:    [[TMP122:%.*]] = select i1 [[TMP120]], i32 [[TMP121]], i32 [[TMP117]]
1169; CHECK-NEXT:    [[TMP123:%.*]] = sub i32 [[TMP119]], [[TMP98]]
1170; CHECK-NEXT:    [[TMP124:%.*]] = select i1 [[TMP120]], i32 [[TMP123]], i32 [[TMP119]]
1171; CHECK-NEXT:    [[TMP125:%.*]] = icmp uge i32 [[TMP124]], [[TMP98]]
1172; CHECK-NEXT:    [[TMP126:%.*]] = add i32 [[TMP122]], 1
1173; CHECK-NEXT:    [[TMP127:%.*]] = select i1 [[TMP125]], i32 [[TMP126]], i32 [[TMP122]]
1174; CHECK-NEXT:    [[TMP128:%.*]] = insertelement <4 x i32> [[TMP96]], i32 [[TMP127]], i64 3
1175; CHECK-NEXT:    store <4 x i32> [[TMP128]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16
1176; CHECK-NEXT:    ret void
1177;
1178; GFX6-LABEL: udiv_v4i32:
1179; GFX6:       ; %bb.0:
1180; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
1181; GFX6-NEXT:    s_mov_b32 s3, 0x4f7ffffe
1182; GFX6-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x9
1183; GFX6-NEXT:    s_mov_b32 s15, 0xf000
1184; GFX6-NEXT:    s_mov_b32 s14, -1
1185; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
1186; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
1187; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
1188; GFX6-NEXT:    s_sub_i32 s2, 0, s8
1189; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s10
1190; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1191; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1192; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s11
1193; GFX6-NEXT:    v_mul_f32_e32 v0, s3, v0
1194; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
1195; GFX6-NEXT:    v_mul_f32_e32 v1, s3, v1
1196; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
1197; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
1198; GFX6-NEXT:    s_sub_i32 s2, 0, s9
1199; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v1
1200; GFX6-NEXT:    s_sub_i32 s2, 0, s10
1201; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
1202; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
1203; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1204; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
1205; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
1206; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
1207; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s8
1208; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
1209; GFX6-NEXT:    v_mul_lo_u32 v5, v1, s9
1210; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s4, v2
1211; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v2
1212; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[0:1]
1213; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v2
1214; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
1215; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
1216; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
1217; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v4
1218; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1219; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s5, v5
1220; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v1
1221; GFX6-NEXT:    v_mul_f32_e32 v2, s3, v2
1222; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
1223; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v3
1224; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[0:1]
1225; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s9, v3
1226; GFX6-NEXT:    v_mul_lo_u32 v4, s2, v2
1227; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
1228; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v1
1229; GFX6-NEXT:    s_sub_i32 s0, 0, s11
1230; GFX6-NEXT:    v_mul_hi_u32 v4, v2, v4
1231; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
1232; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v6
1233; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
1234; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
1235; GFX6-NEXT:    v_mul_hi_u32 v2, s6, v2
1236; GFX6-NEXT:    v_mul_f32_e32 v4, s3, v4
1237; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
1238; GFX6-NEXT:    v_mul_lo_u32 v3, v2, s10
1239; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
1240; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v4
1241; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s6, v3
1242; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v3
1243; GFX6-NEXT:    v_mul_hi_u32 v5, v4, v5
1244; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v6, s[0:1]
1245; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, s10, v3
1246; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v6, s[0:1]
1247; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1248; GFX6-NEXT:    v_mul_hi_u32 v4, s7, v4
1249; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v2
1250; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
1251; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
1252; GFX6-NEXT:    v_mul_lo_u32 v6, v4, s11
1253; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
1254; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s7, v6
1255; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v3
1256; GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]
1257; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s11, v3
1258; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
1259; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
1260; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
1261; GFX6-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc
1262; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[12:15], 0
1263; GFX6-NEXT:    s_endpgm
1264;
1265; GFX9-LABEL: udiv_v4i32:
1266; GFX9:       ; %bb.0:
1267; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
1268; GFX9-NEXT:    s_mov_b32 s12, 0x4f7ffffe
1269; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
1270; GFX9-NEXT:    v_mov_b32_e32 v4, 0
1271; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1272; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
1273; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
1274; GFX9-NEXT:    s_sub_i32 s2, 0, s8
1275; GFX9-NEXT:    s_sub_i32 s3, 0, s9
1276; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1277; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1278; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s10
1279; GFX9-NEXT:    v_mul_f32_e32 v0, s12, v0
1280; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
1281; GFX9-NEXT:    v_mul_f32_e32 v1, s12, v1
1282; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
1283; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v5
1284; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v0
1285; GFX9-NEXT:    s_sub_i32 s2, 0, s10
1286; GFX9-NEXT:    v_mul_lo_u32 v3, s3, v1
1287; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
1288; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
1289; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
1290; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
1291; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
1292; GFX9-NEXT:    v_mul_f32_e32 v2, s12, v5
1293; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
1294; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s8
1295; GFX9-NEXT:    v_add_u32_e32 v6, 1, v0
1296; GFX9-NEXT:    v_mul_hi_u32 v1, s5, v1
1297; GFX9-NEXT:    v_sub_u32_e32 v3, s4, v3
1298; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
1299; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
1300; GFX9-NEXT:    v_subrev_u32_e32 v6, s8, v3
1301; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
1302; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
1303; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, s11
1304; GFX9-NEXT:    v_add_u32_e32 v6, 1, v0
1305; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
1306; GFX9-NEXT:    v_mul_lo_u32 v6, s2, v2
1307; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1308; GFX9-NEXT:    v_mul_lo_u32 v5, v1, s9
1309; GFX9-NEXT:    s_sub_i32 s2, 0, s11
1310; GFX9-NEXT:    v_mul_hi_u32 v6, v2, v6
1311; GFX9-NEXT:    v_mul_f32_e32 v3, s12, v3
1312; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
1313; GFX9-NEXT:    v_sub_u32_e32 v5, s5, v5
1314; GFX9-NEXT:    v_add_u32_e32 v2, v2, v6
1315; GFX9-NEXT:    v_add_u32_e32 v7, 1, v1
1316; GFX9-NEXT:    v_mul_lo_u32 v6, s2, v3
1317; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v5
1318; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
1319; GFX9-NEXT:    v_subrev_u32_e32 v7, s9, v5
1320; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
1321; GFX9-NEXT:    v_mul_hi_u32 v2, s6, v2
1322; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v5
1323; GFX9-NEXT:    v_mul_hi_u32 v5, v3, v6
1324; GFX9-NEXT:    v_add_u32_e32 v7, 1, v1
1325; GFX9-NEXT:    v_mul_lo_u32 v8, v2, s10
1326; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
1327; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
1328; GFX9-NEXT:    v_mul_hi_u32 v3, s7, v3
1329; GFX9-NEXT:    v_sub_u32_e32 v6, s6, v8
1330; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v6
1331; GFX9-NEXT:    v_subrev_u32_e32 v5, s10, v6
1332; GFX9-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
1333; GFX9-NEXT:    v_mul_lo_u32 v6, v3, s11
1334; GFX9-NEXT:    v_add_u32_e32 v7, 1, v2
1335; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v7, vcc
1336; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v5
1337; GFX9-NEXT:    v_add_u32_e32 v7, 1, v2
1338; GFX9-NEXT:    v_sub_u32_e32 v5, s7, v6
1339; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v7, vcc
1340; GFX9-NEXT:    v_add_u32_e32 v6, 1, v3
1341; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v5
1342; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
1343; GFX9-NEXT:    v_subrev_u32_e32 v6, s11, v5
1344; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
1345; GFX9-NEXT:    v_add_u32_e32 v6, 1, v3
1346; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v5
1347; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
1348; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
1349; GFX9-NEXT:    s_endpgm
1350  %r = udiv <4 x i32> %x, %y
1351  store <4 x i32> %r, <4 x i32> addrspace(1)* %out
1352  ret void
1353}
1354
1355define amdgpu_kernel void @urem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
1356; CHECK-LABEL: @urem_v4i32(
1357; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i64 0
1358; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 0
1359; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float
1360; CHECK-NEXT:    [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])
1361; CHECK-NEXT:    [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41EFFFFFC0000000
1362; CHECK-NEXT:    [[TMP6:%.*]] = fptoui float [[TMP5]] to i32
1363; CHECK-NEXT:    [[TMP7:%.*]] = sub i32 0, [[TMP2]]
1364; CHECK-NEXT:    [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP6]]
1365; CHECK-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP6]] to i64
1366; CHECK-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP8]] to i64
1367; CHECK-NEXT:    [[TMP11:%.*]] = mul i64 [[TMP9]], [[TMP10]]
1368; CHECK-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
1369; CHECK-NEXT:    [[TMP13:%.*]] = lshr i64 [[TMP11]], 32
1370; CHECK-NEXT:    [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32
1371; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP6]], [[TMP14]]
1372; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP1]] to i64
1373; CHECK-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP15]] to i64
1374; CHECK-NEXT:    [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]
1375; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
1376; CHECK-NEXT:    [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
1377; CHECK-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
1378; CHECK-NEXT:    [[TMP22:%.*]] = mul i32 [[TMP21]], [[TMP2]]
1379; CHECK-NEXT:    [[TMP23:%.*]] = sub i32 [[TMP1]], [[TMP22]]
1380; CHECK-NEXT:    [[TMP24:%.*]] = icmp uge i32 [[TMP23]], [[TMP2]]
1381; CHECK-NEXT:    [[TMP25:%.*]] = sub i32 [[TMP23]], [[TMP2]]
1382; CHECK-NEXT:    [[TMP26:%.*]] = select i1 [[TMP24]], i32 [[TMP25]], i32 [[TMP23]]
1383; CHECK-NEXT:    [[TMP27:%.*]] = icmp uge i32 [[TMP26]], [[TMP2]]
1384; CHECK-NEXT:    [[TMP28:%.*]] = sub i32 [[TMP26]], [[TMP2]]
1385; CHECK-NEXT:    [[TMP29:%.*]] = select i1 [[TMP27]], i32 [[TMP28]], i32 [[TMP26]]
1386; CHECK-NEXT:    [[TMP30:%.*]] = insertelement <4 x i32> undef, i32 [[TMP29]], i64 0
1387; CHECK-NEXT:    [[TMP31:%.*]] = extractelement <4 x i32> [[X]], i64 1
1388; CHECK-NEXT:    [[TMP32:%.*]] = extractelement <4 x i32> [[Y]], i64 1
1389; CHECK-NEXT:    [[TMP33:%.*]] = uitofp i32 [[TMP32]] to float
1390; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])
1391; CHECK-NEXT:    [[TMP35:%.*]] = fmul fast float [[TMP34]], 0x41EFFFFFC0000000
1392; CHECK-NEXT:    [[TMP36:%.*]] = fptoui float [[TMP35]] to i32
1393; CHECK-NEXT:    [[TMP37:%.*]] = sub i32 0, [[TMP32]]
1394; CHECK-NEXT:    [[TMP38:%.*]] = mul i32 [[TMP37]], [[TMP36]]
1395; CHECK-NEXT:    [[TMP39:%.*]] = zext i32 [[TMP36]] to i64
1396; CHECK-NEXT:    [[TMP40:%.*]] = zext i32 [[TMP38]] to i64
1397; CHECK-NEXT:    [[TMP41:%.*]] = mul i64 [[TMP39]], [[TMP40]]
1398; CHECK-NEXT:    [[TMP42:%.*]] = trunc i64 [[TMP41]] to i32
1399; CHECK-NEXT:    [[TMP43:%.*]] = lshr i64 [[TMP41]], 32
1400; CHECK-NEXT:    [[TMP44:%.*]] = trunc i64 [[TMP43]] to i32
1401; CHECK-NEXT:    [[TMP45:%.*]] = add i32 [[TMP36]], [[TMP44]]
1402; CHECK-NEXT:    [[TMP46:%.*]] = zext i32 [[TMP31]] to i64
1403; CHECK-NEXT:    [[TMP47:%.*]] = zext i32 [[TMP45]] to i64
1404; CHECK-NEXT:    [[TMP48:%.*]] = mul i64 [[TMP46]], [[TMP47]]
1405; CHECK-NEXT:    [[TMP49:%.*]] = trunc i64 [[TMP48]] to i32
1406; CHECK-NEXT:    [[TMP50:%.*]] = lshr i64 [[TMP48]], 32
1407; CHECK-NEXT:    [[TMP51:%.*]] = trunc i64 [[TMP50]] to i32
1408; CHECK-NEXT:    [[TMP52:%.*]] = mul i32 [[TMP51]], [[TMP32]]
1409; CHECK-NEXT:    [[TMP53:%.*]] = sub i32 [[TMP31]], [[TMP52]]
1410; CHECK-NEXT:    [[TMP54:%.*]] = icmp uge i32 [[TMP53]], [[TMP32]]
1411; CHECK-NEXT:    [[TMP55:%.*]] = sub i32 [[TMP53]], [[TMP32]]
1412; CHECK-NEXT:    [[TMP56:%.*]] = select i1 [[TMP54]], i32 [[TMP55]], i32 [[TMP53]]
1413; CHECK-NEXT:    [[TMP57:%.*]] = icmp uge i32 [[TMP56]], [[TMP32]]
1414; CHECK-NEXT:    [[TMP58:%.*]] = sub i32 [[TMP56]], [[TMP32]]
1415; CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP57]], i32 [[TMP58]], i32 [[TMP56]]
1416; CHECK-NEXT:    [[TMP60:%.*]] = insertelement <4 x i32> [[TMP30]], i32 [[TMP59]], i64 1
1417; CHECK-NEXT:    [[TMP61:%.*]] = extractelement <4 x i32> [[X]], i64 2
1418; CHECK-NEXT:    [[TMP62:%.*]] = extractelement <4 x i32> [[Y]], i64 2
1419; CHECK-NEXT:    [[TMP63:%.*]] = uitofp i32 [[TMP62]] to float
1420; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP63]])
1421; CHECK-NEXT:    [[TMP65:%.*]] = fmul fast float [[TMP64]], 0x41EFFFFFC0000000
1422; CHECK-NEXT:    [[TMP66:%.*]] = fptoui float [[TMP65]] to i32
1423; CHECK-NEXT:    [[TMP67:%.*]] = sub i32 0, [[TMP62]]
1424; CHECK-NEXT:    [[TMP68:%.*]] = mul i32 [[TMP67]], [[TMP66]]
1425; CHECK-NEXT:    [[TMP69:%.*]] = zext i32 [[TMP66]] to i64
1426; CHECK-NEXT:    [[TMP70:%.*]] = zext i32 [[TMP68]] to i64
1427; CHECK-NEXT:    [[TMP71:%.*]] = mul i64 [[TMP69]], [[TMP70]]
1428; CHECK-NEXT:    [[TMP72:%.*]] = trunc i64 [[TMP71]] to i32
1429; CHECK-NEXT:    [[TMP73:%.*]] = lshr i64 [[TMP71]], 32
1430; CHECK-NEXT:    [[TMP74:%.*]] = trunc i64 [[TMP73]] to i32
1431; CHECK-NEXT:    [[TMP75:%.*]] = add i32 [[TMP66]], [[TMP74]]
1432; CHECK-NEXT:    [[TMP76:%.*]] = zext i32 [[TMP61]] to i64
1433; CHECK-NEXT:    [[TMP77:%.*]] = zext i32 [[TMP75]] to i64
1434; CHECK-NEXT:    [[TMP78:%.*]] = mul i64 [[TMP76]], [[TMP77]]
1435; CHECK-NEXT:    [[TMP79:%.*]] = trunc i64 [[TMP78]] to i32
1436; CHECK-NEXT:    [[TMP80:%.*]] = lshr i64 [[TMP78]], 32
1437; CHECK-NEXT:    [[TMP81:%.*]] = trunc i64 [[TMP80]] to i32
1438; CHECK-NEXT:    [[TMP82:%.*]] = mul i32 [[TMP81]], [[TMP62]]
1439; CHECK-NEXT:    [[TMP83:%.*]] = sub i32 [[TMP61]], [[TMP82]]
1440; CHECK-NEXT:    [[TMP84:%.*]] = icmp uge i32 [[TMP83]], [[TMP62]]
1441; CHECK-NEXT:    [[TMP85:%.*]] = sub i32 [[TMP83]], [[TMP62]]
1442; CHECK-NEXT:    [[TMP86:%.*]] = select i1 [[TMP84]], i32 [[TMP85]], i32 [[TMP83]]
1443; CHECK-NEXT:    [[TMP87:%.*]] = icmp uge i32 [[TMP86]], [[TMP62]]
1444; CHECK-NEXT:    [[TMP88:%.*]] = sub i32 [[TMP86]], [[TMP62]]
1445; CHECK-NEXT:    [[TMP89:%.*]] = select i1 [[TMP87]], i32 [[TMP88]], i32 [[TMP86]]
1446; CHECK-NEXT:    [[TMP90:%.*]] = insertelement <4 x i32> [[TMP60]], i32 [[TMP89]], i64 2
1447; CHECK-NEXT:    [[TMP91:%.*]] = extractelement <4 x i32> [[X]], i64 3
1448; CHECK-NEXT:    [[TMP92:%.*]] = extractelement <4 x i32> [[Y]], i64 3
1449; CHECK-NEXT:    [[TMP93:%.*]] = uitofp i32 [[TMP92]] to float
1450; CHECK-NEXT:    [[TMP94:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP93]])
1451; CHECK-NEXT:    [[TMP95:%.*]] = fmul fast float [[TMP94]], 0x41EFFFFFC0000000
1452; CHECK-NEXT:    [[TMP96:%.*]] = fptoui float [[TMP95]] to i32
1453; CHECK-NEXT:    [[TMP97:%.*]] = sub i32 0, [[TMP92]]
1454; CHECK-NEXT:    [[TMP98:%.*]] = mul i32 [[TMP97]], [[TMP96]]
1455; CHECK-NEXT:    [[TMP99:%.*]] = zext i32 [[TMP96]] to i64
1456; CHECK-NEXT:    [[TMP100:%.*]] = zext i32 [[TMP98]] to i64
1457; CHECK-NEXT:    [[TMP101:%.*]] = mul i64 [[TMP99]], [[TMP100]]
1458; CHECK-NEXT:    [[TMP102:%.*]] = trunc i64 [[TMP101]] to i32
1459; CHECK-NEXT:    [[TMP103:%.*]] = lshr i64 [[TMP101]], 32
1460; CHECK-NEXT:    [[TMP104:%.*]] = trunc i64 [[TMP103]] to i32
1461; CHECK-NEXT:    [[TMP105:%.*]] = add i32 [[TMP96]], [[TMP104]]
1462; CHECK-NEXT:    [[TMP106:%.*]] = zext i32 [[TMP91]] to i64
1463; CHECK-NEXT:    [[TMP107:%.*]] = zext i32 [[TMP105]] to i64
1464; CHECK-NEXT:    [[TMP108:%.*]] = mul i64 [[TMP106]], [[TMP107]]
1465; CHECK-NEXT:    [[TMP109:%.*]] = trunc i64 [[TMP108]] to i32
1466; CHECK-NEXT:    [[TMP110:%.*]] = lshr i64 [[TMP108]], 32
1467; CHECK-NEXT:    [[TMP111:%.*]] = trunc i64 [[TMP110]] to i32
1468; CHECK-NEXT:    [[TMP112:%.*]] = mul i32 [[TMP111]], [[TMP92]]
1469; CHECK-NEXT:    [[TMP113:%.*]] = sub i32 [[TMP91]], [[TMP112]]
1470; CHECK-NEXT:    [[TMP114:%.*]] = icmp uge i32 [[TMP113]], [[TMP92]]
1471; CHECK-NEXT:    [[TMP115:%.*]] = sub i32 [[TMP113]], [[TMP92]]
1472; CHECK-NEXT:    [[TMP116:%.*]] = select i1 [[TMP114]], i32 [[TMP115]], i32 [[TMP113]]
1473; CHECK-NEXT:    [[TMP117:%.*]] = icmp uge i32 [[TMP116]], [[TMP92]]
1474; CHECK-NEXT:    [[TMP118:%.*]] = sub i32 [[TMP116]], [[TMP92]]
1475; CHECK-NEXT:    [[TMP119:%.*]] = select i1 [[TMP117]], i32 [[TMP118]], i32 [[TMP116]]
1476; CHECK-NEXT:    [[TMP120:%.*]] = insertelement <4 x i32> [[TMP90]], i32 [[TMP119]], i64 3
1477; CHECK-NEXT:    store <4 x i32> [[TMP120]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16
1478; CHECK-NEXT:    ret void
1479;
1480; GFX6-LABEL: urem_v4i32:
1481; GFX6:       ; %bb.0:
1482; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
1483; GFX6-NEXT:    s_mov_b32 s13, 0x4f7ffffe
1484; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
1485; GFX6-NEXT:    s_mov_b32 s3, 0xf000
1486; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
1487; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
1488; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
1489; GFX6-NEXT:    s_sub_i32 s2, 0, s8
1490; GFX6-NEXT:    s_sub_i32 s12, 0, s9
1491; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1492; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1493; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s10
1494; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s11
1495; GFX6-NEXT:    v_mul_f32_e32 v0, s13, v0
1496; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
1497; GFX6-NEXT:    v_mul_f32_e32 v1, s13, v1
1498; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
1499; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1500; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
1501; GFX6-NEXT:    s_mov_b32 s2, -1
1502; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v1
1503; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
1504; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
1505; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1506; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
1507; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
1508; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
1509; GFX6-NEXT:    v_mul_f32_e32 v2, s13, v3
1510; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s8
1511; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
1512; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s9
1513; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
1514; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v0
1515; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1516; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1517; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v0
1518; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1519; GFX6-NEXT:    s_sub_i32 s4, 0, s10
1520; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1521; GFX6-NEXT:    v_mul_lo_u32 v3, s4, v2
1522; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
1523; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s9, v1
1524; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1525; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
1526; GFX6-NEXT:    v_mul_hi_u32 v3, v2, v3
1527; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v5
1528; GFX6-NEXT:    s_sub_i32 s4, 0, s11
1529; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1530; GFX6-NEXT:    v_mul_f32_e32 v3, s13, v4
1531; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
1532; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s9, v1
1533; GFX6-NEXT:    v_mul_hi_u32 v2, s6, v2
1534; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1535; GFX6-NEXT:    v_mul_lo_u32 v5, s4, v3
1536; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
1537; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s10
1538; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v5
1539; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s6, v2
1540; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s10, v2
1541; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1542; GFX6-NEXT:    v_mul_hi_u32 v3, s7, v3
1543; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
1544; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
1545; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s10, v2
1546; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s11
1547; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
1548; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
1549; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s7, v3
1550; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s11, v3
1551; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
1552; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
1553; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s11, v3
1554; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
1555; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
1556; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1557; GFX6-NEXT:    s_endpgm
1558;
1559; GFX9-LABEL: urem_v4i32:
1560; GFX9:       ; %bb.0:
1561; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
1562; GFX9-NEXT:    s_mov_b32 s12, 0x4f7ffffe
1563; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
1564; GFX9-NEXT:    v_mov_b32_e32 v4, 0
1565; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1566; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
1567; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
1568; GFX9-NEXT:    s_sub_i32 s2, 0, s8
1569; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s10
1570; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1571; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1572; GFX9-NEXT:    s_sub_i32 s3, 0, s9
1573; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v5
1574; GFX9-NEXT:    v_mul_f32_e32 v0, s12, v0
1575; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
1576; GFX9-NEXT:    v_mul_f32_e32 v1, s12, v1
1577; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
1578; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s11
1579; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v0
1580; GFX9-NEXT:    s_sub_i32 s2, 0, s10
1581; GFX9-NEXT:    v_mul_lo_u32 v3, s3, v1
1582; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
1583; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
1584; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
1585; GFX9-NEXT:    v_mul_f32_e32 v2, s12, v5
1586; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
1587; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
1588; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v6
1589; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
1590; GFX9-NEXT:    v_mul_lo_u32 v5, s2, v2
1591; GFX9-NEXT:    s_sub_i32 s2, 0, s11
1592; GFX9-NEXT:    v_mul_f32_e32 v3, s12, v3
1593; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
1594; GFX9-NEXT:    v_mul_hi_u32 v5, v2, v5
1595; GFX9-NEXT:    v_mul_hi_u32 v1, s5, v1
1596; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s8
1597; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
1598; GFX9-NEXT:    v_mul_lo_u32 v5, s2, v3
1599; GFX9-NEXT:    v_mul_hi_u32 v2, s6, v2
1600; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s9
1601; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
1602; GFX9-NEXT:    v_mul_hi_u32 v5, v3, v5
1603; GFX9-NEXT:    v_subrev_u32_e32 v6, s8, v0
1604; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1605; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
1606; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
1607; GFX9-NEXT:    v_mul_hi_u32 v3, s7, v3
1608; GFX9-NEXT:    v_mul_lo_u32 v2, v2, s10
1609; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v1
1610; GFX9-NEXT:    v_subrev_u32_e32 v6, s8, v0
1611; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1612; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
1613; GFX9-NEXT:    v_subrev_u32_e32 v6, s9, v1
1614; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1615; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc
1616; GFX9-NEXT:    v_mul_lo_u32 v3, v3, s11
1617; GFX9-NEXT:    v_sub_u32_e32 v2, s6, v2
1618; GFX9-NEXT:    v_subrev_u32_e32 v6, s9, v1
1619; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1620; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc
1621; GFX9-NEXT:    v_subrev_u32_e32 v5, s10, v2
1622; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
1623; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
1624; GFX9-NEXT:    v_subrev_u32_e32 v5, s10, v2
1625; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
1626; GFX9-NEXT:    v_sub_u32_e32 v3, s7, v3
1627; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
1628; GFX9-NEXT:    v_subrev_u32_e32 v5, s11, v3
1629; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
1630; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
1631; GFX9-NEXT:    v_subrev_u32_e32 v5, s11, v3
1632; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
1633; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
1634; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
1635; GFX9-NEXT:    s_endpgm
1636  %r = urem <4 x i32> %x, %y
1637  store <4 x i32> %r, <4 x i32> addrspace(1)* %out
1638  ret void
1639}
1640
1641define amdgpu_kernel void @sdiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
1642; CHECK-LABEL: @sdiv_v4i32(
1643; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i64 0
1644; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 0
1645; CHECK-NEXT:    [[TMP3:%.*]] = ashr i32 [[TMP1]], 31
1646; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP2]], 31
1647; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
1648; CHECK-NEXT:    [[TMP6:%.*]] = add i32 [[TMP1]], [[TMP3]]
1649; CHECK-NEXT:    [[TMP7:%.*]] = add i32 [[TMP2]], [[TMP4]]
1650; CHECK-NEXT:    [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP3]]
1651; CHECK-NEXT:    [[TMP9:%.*]] = xor i32 [[TMP7]], [[TMP4]]
1652; CHECK-NEXT:    [[TMP10:%.*]] = uitofp i32 [[TMP9]] to float
1653; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP10]])
1654; CHECK-NEXT:    [[TMP12:%.*]] = fmul fast float [[TMP11]], 0x41EFFFFFC0000000
1655; CHECK-NEXT:    [[TMP13:%.*]] = fptoui float [[TMP12]] to i32
1656; CHECK-NEXT:    [[TMP14:%.*]] = sub i32 0, [[TMP9]]
1657; CHECK-NEXT:    [[TMP15:%.*]] = mul i32 [[TMP14]], [[TMP13]]
1658; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP13]] to i64
1659; CHECK-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP15]] to i64
1660; CHECK-NEXT:    [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]
1661; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
1662; CHECK-NEXT:    [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
1663; CHECK-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
1664; CHECK-NEXT:    [[TMP22:%.*]] = add i32 [[TMP13]], [[TMP21]]
1665; CHECK-NEXT:    [[TMP23:%.*]] = zext i32 [[TMP8]] to i64
1666; CHECK-NEXT:    [[TMP24:%.*]] = zext i32 [[TMP22]] to i64
1667; CHECK-NEXT:    [[TMP25:%.*]] = mul i64 [[TMP23]], [[TMP24]]
1668; CHECK-NEXT:    [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32
1669; CHECK-NEXT:    [[TMP27:%.*]] = lshr i64 [[TMP25]], 32
1670; CHECK-NEXT:    [[TMP28:%.*]] = trunc i64 [[TMP27]] to i32
1671; CHECK-NEXT:    [[TMP29:%.*]] = mul i32 [[TMP28]], [[TMP9]]
1672; CHECK-NEXT:    [[TMP30:%.*]] = sub i32 [[TMP8]], [[TMP29]]
1673; CHECK-NEXT:    [[TMP31:%.*]] = icmp uge i32 [[TMP30]], [[TMP9]]
1674; CHECK-NEXT:    [[TMP32:%.*]] = add i32 [[TMP28]], 1
1675; CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP31]], i32 [[TMP32]], i32 [[TMP28]]
1676; CHECK-NEXT:    [[TMP34:%.*]] = sub i32 [[TMP30]], [[TMP9]]
1677; CHECK-NEXT:    [[TMP35:%.*]] = select i1 [[TMP31]], i32 [[TMP34]], i32 [[TMP30]]
1678; CHECK-NEXT:    [[TMP36:%.*]] = icmp uge i32 [[TMP35]], [[TMP9]]
1679; CHECK-NEXT:    [[TMP37:%.*]] = add i32 [[TMP33]], 1
1680; CHECK-NEXT:    [[TMP38:%.*]] = select i1 [[TMP36]], i32 [[TMP37]], i32 [[TMP33]]
1681; CHECK-NEXT:    [[TMP39:%.*]] = xor i32 [[TMP38]], [[TMP5]]
1682; CHECK-NEXT:    [[TMP40:%.*]] = sub i32 [[TMP39]], [[TMP5]]
1683; CHECK-NEXT:    [[TMP41:%.*]] = insertelement <4 x i32> undef, i32 [[TMP40]], i64 0
1684; CHECK-NEXT:    [[TMP42:%.*]] = extractelement <4 x i32> [[X]], i64 1
1685; CHECK-NEXT:    [[TMP43:%.*]] = extractelement <4 x i32> [[Y]], i64 1
1686; CHECK-NEXT:    [[TMP44:%.*]] = ashr i32 [[TMP42]], 31
1687; CHECK-NEXT:    [[TMP45:%.*]] = ashr i32 [[TMP43]], 31
1688; CHECK-NEXT:    [[TMP46:%.*]] = xor i32 [[TMP44]], [[TMP45]]
1689; CHECK-NEXT:    [[TMP47:%.*]] = add i32 [[TMP42]], [[TMP44]]
1690; CHECK-NEXT:    [[TMP48:%.*]] = add i32 [[TMP43]], [[TMP45]]
1691; CHECK-NEXT:    [[TMP49:%.*]] = xor i32 [[TMP47]], [[TMP44]]
1692; CHECK-NEXT:    [[TMP50:%.*]] = xor i32 [[TMP48]], [[TMP45]]
1693; CHECK-NEXT:    [[TMP51:%.*]] = uitofp i32 [[TMP50]] to float
1694; CHECK-NEXT:    [[TMP52:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP51]])
1695; CHECK-NEXT:    [[TMP53:%.*]] = fmul fast float [[TMP52]], 0x41EFFFFFC0000000
1696; CHECK-NEXT:    [[TMP54:%.*]] = fptoui float [[TMP53]] to i32
1697; CHECK-NEXT:    [[TMP55:%.*]] = sub i32 0, [[TMP50]]
1698; CHECK-NEXT:    [[TMP56:%.*]] = mul i32 [[TMP55]], [[TMP54]]
1699; CHECK-NEXT:    [[TMP57:%.*]] = zext i32 [[TMP54]] to i64
1700; CHECK-NEXT:    [[TMP58:%.*]] = zext i32 [[TMP56]] to i64
1701; CHECK-NEXT:    [[TMP59:%.*]] = mul i64 [[TMP57]], [[TMP58]]
1702; CHECK-NEXT:    [[TMP60:%.*]] = trunc i64 [[TMP59]] to i32
1703; CHECK-NEXT:    [[TMP61:%.*]] = lshr i64 [[TMP59]], 32
1704; CHECK-NEXT:    [[TMP62:%.*]] = trunc i64 [[TMP61]] to i32
1705; CHECK-NEXT:    [[TMP63:%.*]] = add i32 [[TMP54]], [[TMP62]]
1706; CHECK-NEXT:    [[TMP64:%.*]] = zext i32 [[TMP49]] to i64
1707; CHECK-NEXT:    [[TMP65:%.*]] = zext i32 [[TMP63]] to i64
1708; CHECK-NEXT:    [[TMP66:%.*]] = mul i64 [[TMP64]], [[TMP65]]
1709; CHECK-NEXT:    [[TMP67:%.*]] = trunc i64 [[TMP66]] to i32
1710; CHECK-NEXT:    [[TMP68:%.*]] = lshr i64 [[TMP66]], 32
1711; CHECK-NEXT:    [[TMP69:%.*]] = trunc i64 [[TMP68]] to i32
1712; CHECK-NEXT:    [[TMP70:%.*]] = mul i32 [[TMP69]], [[TMP50]]
1713; CHECK-NEXT:    [[TMP71:%.*]] = sub i32 [[TMP49]], [[TMP70]]
1714; CHECK-NEXT:    [[TMP72:%.*]] = icmp uge i32 [[TMP71]], [[TMP50]]
1715; CHECK-NEXT:    [[TMP73:%.*]] = add i32 [[TMP69]], 1
1716; CHECK-NEXT:    [[TMP74:%.*]] = select i1 [[TMP72]], i32 [[TMP73]], i32 [[TMP69]]
1717; CHECK-NEXT:    [[TMP75:%.*]] = sub i32 [[TMP71]], [[TMP50]]
1718; CHECK-NEXT:    [[TMP76:%.*]] = select i1 [[TMP72]], i32 [[TMP75]], i32 [[TMP71]]
1719; CHECK-NEXT:    [[TMP77:%.*]] = icmp uge i32 [[TMP76]], [[TMP50]]
1720; CHECK-NEXT:    [[TMP78:%.*]] = add i32 [[TMP74]], 1
1721; CHECK-NEXT:    [[TMP79:%.*]] = select i1 [[TMP77]], i32 [[TMP78]], i32 [[TMP74]]
1722; CHECK-NEXT:    [[TMP80:%.*]] = xor i32 [[TMP79]], [[TMP46]]
1723; CHECK-NEXT:    [[TMP81:%.*]] = sub i32 [[TMP80]], [[TMP46]]
1724; CHECK-NEXT:    [[TMP82:%.*]] = insertelement <4 x i32> [[TMP41]], i32 [[TMP81]], i64 1
1725; CHECK-NEXT:    [[TMP83:%.*]] = extractelement <4 x i32> [[X]], i64 2
1726; CHECK-NEXT:    [[TMP84:%.*]] = extractelement <4 x i32> [[Y]], i64 2
1727; CHECK-NEXT:    [[TMP85:%.*]] = ashr i32 [[TMP83]], 31
1728; CHECK-NEXT:    [[TMP86:%.*]] = ashr i32 [[TMP84]], 31
1729; CHECK-NEXT:    [[TMP87:%.*]] = xor i32 [[TMP85]], [[TMP86]]
1730; CHECK-NEXT:    [[TMP88:%.*]] = add i32 [[TMP83]], [[TMP85]]
1731; CHECK-NEXT:    [[TMP89:%.*]] = add i32 [[TMP84]], [[TMP86]]
1732; CHECK-NEXT:    [[TMP90:%.*]] = xor i32 [[TMP88]], [[TMP85]]
1733; CHECK-NEXT:    [[TMP91:%.*]] = xor i32 [[TMP89]], [[TMP86]]
1734; CHECK-NEXT:    [[TMP92:%.*]] = uitofp i32 [[TMP91]] to float
1735; CHECK-NEXT:    [[TMP93:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP92]])
1736; CHECK-NEXT:    [[TMP94:%.*]] = fmul fast float [[TMP93]], 0x41EFFFFFC0000000
1737; CHECK-NEXT:    [[TMP95:%.*]] = fptoui float [[TMP94]] to i32
1738; CHECK-NEXT:    [[TMP96:%.*]] = sub i32 0, [[TMP91]]
1739; CHECK-NEXT:    [[TMP97:%.*]] = mul i32 [[TMP96]], [[TMP95]]
1740; CHECK-NEXT:    [[TMP98:%.*]] = zext i32 [[TMP95]] to i64
1741; CHECK-NEXT:    [[TMP99:%.*]] = zext i32 [[TMP97]] to i64
1742; CHECK-NEXT:    [[TMP100:%.*]] = mul i64 [[TMP98]], [[TMP99]]
1743; CHECK-NEXT:    [[TMP101:%.*]] = trunc i64 [[TMP100]] to i32
1744; CHECK-NEXT:    [[TMP102:%.*]] = lshr i64 [[TMP100]], 32
1745; CHECK-NEXT:    [[TMP103:%.*]] = trunc i64 [[TMP102]] to i32
1746; CHECK-NEXT:    [[TMP104:%.*]] = add i32 [[TMP95]], [[TMP103]]
1747; CHECK-NEXT:    [[TMP105:%.*]] = zext i32 [[TMP90]] to i64
1748; CHECK-NEXT:    [[TMP106:%.*]] = zext i32 [[TMP104]] to i64
1749; CHECK-NEXT:    [[TMP107:%.*]] = mul i64 [[TMP105]], [[TMP106]]
1750; CHECK-NEXT:    [[TMP108:%.*]] = trunc i64 [[TMP107]] to i32
1751; CHECK-NEXT:    [[TMP109:%.*]] = lshr i64 [[TMP107]], 32
1752; CHECK-NEXT:    [[TMP110:%.*]] = trunc i64 [[TMP109]] to i32
1753; CHECK-NEXT:    [[TMP111:%.*]] = mul i32 [[TMP110]], [[TMP91]]
1754; CHECK-NEXT:    [[TMP112:%.*]] = sub i32 [[TMP90]], [[TMP111]]
1755; CHECK-NEXT:    [[TMP113:%.*]] = icmp uge i32 [[TMP112]], [[TMP91]]
1756; CHECK-NEXT:    [[TMP114:%.*]] = add i32 [[TMP110]], 1
1757; CHECK-NEXT:    [[TMP115:%.*]] = select i1 [[TMP113]], i32 [[TMP114]], i32 [[TMP110]]
1758; CHECK-NEXT:    [[TMP116:%.*]] = sub i32 [[TMP112]], [[TMP91]]
1759; CHECK-NEXT:    [[TMP117:%.*]] = select i1 [[TMP113]], i32 [[TMP116]], i32 [[TMP112]]
1760; CHECK-NEXT:    [[TMP118:%.*]] = icmp uge i32 [[TMP117]], [[TMP91]]
1761; CHECK-NEXT:    [[TMP119:%.*]] = add i32 [[TMP115]], 1
1762; CHECK-NEXT:    [[TMP120:%.*]] = select i1 [[TMP118]], i32 [[TMP119]], i32 [[TMP115]]
1763; CHECK-NEXT:    [[TMP121:%.*]] = xor i32 [[TMP120]], [[TMP87]]
1764; CHECK-NEXT:    [[TMP122:%.*]] = sub i32 [[TMP121]], [[TMP87]]
1765; CHECK-NEXT:    [[TMP123:%.*]] = insertelement <4 x i32> [[TMP82]], i32 [[TMP122]], i64 2
1766; CHECK-NEXT:    [[TMP124:%.*]] = extractelement <4 x i32> [[X]], i64 3
1767; CHECK-NEXT:    [[TMP125:%.*]] = extractelement <4 x i32> [[Y]], i64 3
1768; CHECK-NEXT:    [[TMP126:%.*]] = ashr i32 [[TMP124]], 31
1769; CHECK-NEXT:    [[TMP127:%.*]] = ashr i32 [[TMP125]], 31
1770; CHECK-NEXT:    [[TMP128:%.*]] = xor i32 [[TMP126]], [[TMP127]]
1771; CHECK-NEXT:    [[TMP129:%.*]] = add i32 [[TMP124]], [[TMP126]]
1772; CHECK-NEXT:    [[TMP130:%.*]] = add i32 [[TMP125]], [[TMP127]]
1773; CHECK-NEXT:    [[TMP131:%.*]] = xor i32 [[TMP129]], [[TMP126]]
1774; CHECK-NEXT:    [[TMP132:%.*]] = xor i32 [[TMP130]], [[TMP127]]
1775; CHECK-NEXT:    [[TMP133:%.*]] = uitofp i32 [[TMP132]] to float
1776; CHECK-NEXT:    [[TMP134:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP133]])
1777; CHECK-NEXT:    [[TMP135:%.*]] = fmul fast float [[TMP134]], 0x41EFFFFFC0000000
1778; CHECK-NEXT:    [[TMP136:%.*]] = fptoui float [[TMP135]] to i32
1779; CHECK-NEXT:    [[TMP137:%.*]] = sub i32 0, [[TMP132]]
1780; CHECK-NEXT:    [[TMP138:%.*]] = mul i32 [[TMP137]], [[TMP136]]
1781; CHECK-NEXT:    [[TMP139:%.*]] = zext i32 [[TMP136]] to i64
1782; CHECK-NEXT:    [[TMP140:%.*]] = zext i32 [[TMP138]] to i64
1783; CHECK-NEXT:    [[TMP141:%.*]] = mul i64 [[TMP139]], [[TMP140]]
1784; CHECK-NEXT:    [[TMP142:%.*]] = trunc i64 [[TMP141]] to i32
1785; CHECK-NEXT:    [[TMP143:%.*]] = lshr i64 [[TMP141]], 32
1786; CHECK-NEXT:    [[TMP144:%.*]] = trunc i64 [[TMP143]] to i32
1787; CHECK-NEXT:    [[TMP145:%.*]] = add i32 [[TMP136]], [[TMP144]]
1788; CHECK-NEXT:    [[TMP146:%.*]] = zext i32 [[TMP131]] to i64
1789; CHECK-NEXT:    [[TMP147:%.*]] = zext i32 [[TMP145]] to i64
1790; CHECK-NEXT:    [[TMP148:%.*]] = mul i64 [[TMP146]], [[TMP147]]
1791; CHECK-NEXT:    [[TMP149:%.*]] = trunc i64 [[TMP148]] to i32
1792; CHECK-NEXT:    [[TMP150:%.*]] = lshr i64 [[TMP148]], 32
1793; CHECK-NEXT:    [[TMP151:%.*]] = trunc i64 [[TMP150]] to i32
1794; CHECK-NEXT:    [[TMP152:%.*]] = mul i32 [[TMP151]], [[TMP132]]
1795; CHECK-NEXT:    [[TMP153:%.*]] = sub i32 [[TMP131]], [[TMP152]]
1796; CHECK-NEXT:    [[TMP154:%.*]] = icmp uge i32 [[TMP153]], [[TMP132]]
1797; CHECK-NEXT:    [[TMP155:%.*]] = add i32 [[TMP151]], 1
1798; CHECK-NEXT:    [[TMP156:%.*]] = select i1 [[TMP154]], i32 [[TMP155]], i32 [[TMP151]]
1799; CHECK-NEXT:    [[TMP157:%.*]] = sub i32 [[TMP153]], [[TMP132]]
1800; CHECK-NEXT:    [[TMP158:%.*]] = select i1 [[TMP154]], i32 [[TMP157]], i32 [[TMP153]]
1801; CHECK-NEXT:    [[TMP159:%.*]] = icmp uge i32 [[TMP158]], [[TMP132]]
1802; CHECK-NEXT:    [[TMP160:%.*]] = add i32 [[TMP156]], 1
1803; CHECK-NEXT:    [[TMP161:%.*]] = select i1 [[TMP159]], i32 [[TMP160]], i32 [[TMP156]]
1804; CHECK-NEXT:    [[TMP162:%.*]] = xor i32 [[TMP161]], [[TMP128]]
1805; CHECK-NEXT:    [[TMP163:%.*]] = sub i32 [[TMP162]], [[TMP128]]
1806; CHECK-NEXT:    [[TMP164:%.*]] = insertelement <4 x i32> [[TMP123]], i32 [[TMP163]], i64 3
1807; CHECK-NEXT:    store <4 x i32> [[TMP164]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16
1808; CHECK-NEXT:    ret void
1809;
1810; GFX6-LABEL: sdiv_v4i32:
1811; GFX6:       ; %bb.0:
1812; GFX6-NEXT:    s_load_dwordx8 s[8:15], s[0:1], 0xd
1813; GFX6-NEXT:    s_mov_b32 s16, 0x4f7ffffe
1814; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
1815; GFX6-NEXT:    s_mov_b32 s7, 0xf000
1816; GFX6-NEXT:    s_mov_b32 s6, -1
1817; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
1818; GFX6-NEXT:    s_ashr_i32 s2, s12, 31
1819; GFX6-NEXT:    s_add_i32 s3, s12, s2
1820; GFX6-NEXT:    s_xor_b32 s12, s3, s2
1821; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s12
1822; GFX6-NEXT:    s_ashr_i32 s3, s13, 31
1823; GFX6-NEXT:    s_add_i32 s0, s13, s3
1824; GFX6-NEXT:    s_xor_b32 s13, s0, s3
1825; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1826; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s13
1827; GFX6-NEXT:    s_sub_i32 s1, 0, s12
1828; GFX6-NEXT:    s_ashr_i32 s0, s8, 31
1829; GFX6-NEXT:    v_mul_f32_e32 v0, s16, v0
1830; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
1831; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1832; GFX6-NEXT:    s_xor_b32 s2, s0, s2
1833; GFX6-NEXT:    v_mul_lo_u32 v2, s1, v0
1834; GFX6-NEXT:    s_add_i32 s1, s8, s0
1835; GFX6-NEXT:    v_mul_f32_e32 v1, s16, v1
1836; GFX6-NEXT:    s_xor_b32 s1, s1, s0
1837; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
1838; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
1839; GFX6-NEXT:    s_sub_i32 s0, 0, s13
1840; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1841; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
1842; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v1
1843; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s12
1844; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v2
1845; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
1846; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s1, v3
1847; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s12, v3
1848; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
1849; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s12, v3
1850; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[0:1]
1851; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
1852; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1853; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v3
1854; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
1855; GFX6-NEXT:    v_xor_b32_e32 v0, s2, v0
1856; GFX6-NEXT:    s_ashr_i32 s0, s9, 31
1857; GFX6-NEXT:    s_add_i32 s1, s9, s0
1858; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
1859; GFX6-NEXT:    s_xor_b32 s2, s0, s3
1860; GFX6-NEXT:    s_ashr_i32 s3, s14, 31
1861; GFX6-NEXT:    s_xor_b32 s1, s1, s0
1862; GFX6-NEXT:    s_add_i32 s0, s14, s3
1863; GFX6-NEXT:    s_xor_b32 s9, s0, s3
1864; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s9
1865; GFX6-NEXT:    v_mul_hi_u32 v1, s1, v1
1866; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1867; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s13
1868; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v1
1869; GFX6-NEXT:    v_mul_f32_e32 v3, s16, v3
1870; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
1871; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
1872; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s13, v2
1873; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[0:1]
1874; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s13, v2
1875; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v4, s[0:1]
1876; GFX6-NEXT:    s_sub_i32 s0, 0, s9
1877; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v3
1878; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v1
1879; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s13, v2
1880; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
1881; GFX6-NEXT:    v_mul_hi_u32 v2, v3, v5
1882; GFX6-NEXT:    v_xor_b32_e32 v1, s2, v1
1883; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s2, v1
1884; GFX6-NEXT:    s_ashr_i32 s2, s15, 31
1885; GFX6-NEXT:    s_ashr_i32 s0, s10, 31
1886; GFX6-NEXT:    s_add_i32 s8, s15, s2
1887; GFX6-NEXT:    s_add_i32 s1, s10, s0
1888; GFX6-NEXT:    s_xor_b32 s8, s8, s2
1889; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s8
1890; GFX6-NEXT:    s_xor_b32 s1, s1, s0
1891; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
1892; GFX6-NEXT:    v_mul_hi_u32 v2, s1, v2
1893; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v4
1894; GFX6-NEXT:    s_xor_b32 s3, s0, s3
1895; GFX6-NEXT:    v_mul_lo_u32 v3, v2, s9
1896; GFX6-NEXT:    v_mul_f32_e32 v4, s16, v4
1897; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
1898; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v2
1899; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s1, v3
1900; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v3
1901; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v5, s[0:1]
1902; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s9, v3
1903; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
1904; GFX6-NEXT:    s_sub_i32 s0, 0, s8
1905; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v4
1906; GFX6-NEXT:    s_ashr_i32 s0, s11, 31
1907; GFX6-NEXT:    s_add_i32 s1, s11, s0
1908; GFX6-NEXT:    s_xor_b32 s1, s1, s0
1909; GFX6-NEXT:    v_mul_hi_u32 v5, v4, v5
1910; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
1911; GFX6-NEXT:    s_xor_b32 s2, s0, s2
1912; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1913; GFX6-NEXT:    v_mul_hi_u32 v4, s1, v4
1914; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
1915; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
1916; GFX6-NEXT:    v_xor_b32_e32 v2, s3, v2
1917; GFX6-NEXT:    v_mul_lo_u32 v3, v4, s8
1918; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
1919; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v2
1920; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s1, v3
1921; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v3
1922; GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]
1923; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s8, v3
1924; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
1925; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
1926; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
1927; GFX6-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc
1928; GFX6-NEXT:    v_xor_b32_e32 v3, s2, v3
1929; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s2, v3
1930; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
1931; GFX6-NEXT:    s_endpgm
1932;
1933; GFX9-LABEL: sdiv_v4i32:
1934; GFX9:       ; %bb.0:
1935; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
1936; GFX9-NEXT:    s_mov_b32 s13, 0x4f7ffffe
1937; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
1938; GFX9-NEXT:    v_mov_b32_e32 v4, 0
1939; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1940; GFX9-NEXT:    s_ashr_i32 s2, s8, 31
1941; GFX9-NEXT:    s_add_i32 s3, s8, s2
1942; GFX9-NEXT:    s_xor_b32 s14, s3, s2
1943; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s14
1944; GFX9-NEXT:    s_ashr_i32 s8, s9, 31
1945; GFX9-NEXT:    s_add_i32 s9, s9, s8
1946; GFX9-NEXT:    s_xor_b32 s15, s9, s8
1947; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1948; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s15
1949; GFX9-NEXT:    s_sub_i32 s12, 0, s14
1950; GFX9-NEXT:    s_ashr_i32 s3, s4, 31
1951; GFX9-NEXT:    v_mul_f32_e32 v0, s13, v0
1952; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
1953; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1954; GFX9-NEXT:    s_add_i32 s4, s4, s3
1955; GFX9-NEXT:    s_xor_b32 s4, s4, s3
1956; GFX9-NEXT:    v_mul_lo_u32 v2, s12, v0
1957; GFX9-NEXT:    v_mul_f32_e32 v1, s13, v1
1958; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
1959; GFX9-NEXT:    s_sub_i32 s12, 0, s15
1960; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
1961; GFX9-NEXT:    s_ashr_i32 s9, s5, 31
1962; GFX9-NEXT:    v_mul_lo_u32 v3, s12, v1
1963; GFX9-NEXT:    s_xor_b32 s2, s3, s2
1964; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
1965; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
1966; GFX9-NEXT:    v_mul_hi_u32 v2, v1, v3
1967; GFX9-NEXT:    s_add_i32 s3, s5, s9
1968; GFX9-NEXT:    s_xor_b32 s3, s3, s9
1969; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s14
1970; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
1971; GFX9-NEXT:    v_mul_hi_u32 v1, s3, v1
1972; GFX9-NEXT:    v_add_u32_e32 v2, 1, v0
1973; GFX9-NEXT:    v_sub_u32_e32 v3, s4, v3
1974; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s14, v3
1975; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1976; GFX9-NEXT:    v_subrev_u32_e32 v2, s14, v3
1977; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
1978; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s14, v2
1979; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s15
1980; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
1981; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1982; GFX9-NEXT:    v_xor_b32_e32 v0, s2, v0
1983; GFX9-NEXT:    v_sub_u32_e32 v2, s3, v2
1984; GFX9-NEXT:    s_ashr_i32 s3, s10, 31
1985; GFX9-NEXT:    s_add_i32 s4, s10, s3
1986; GFX9-NEXT:    v_subrev_u32_e32 v0, s2, v0
1987; GFX9-NEXT:    s_xor_b32 s2, s9, s8
1988; GFX9-NEXT:    s_xor_b32 s9, s4, s3
1989; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, s9
1990; GFX9-NEXT:    v_add_u32_e32 v5, 1, v1
1991; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s15, v2
1992; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
1993; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1994; GFX9-NEXT:    v_subrev_u32_e32 v5, s15, v2
1995; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
1996; GFX9-NEXT:    s_sub_i32 s4, 0, s9
1997; GFX9-NEXT:    v_mul_f32_e32 v3, s13, v3
1998; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
1999; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s15, v2
2000; GFX9-NEXT:    v_add_u32_e32 v5, 1, v1
2001; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
2002; GFX9-NEXT:    v_mul_lo_u32 v2, s4, v3
2003; GFX9-NEXT:    s_ashr_i32 s4, s6, 31
2004; GFX9-NEXT:    s_add_i32 s5, s6, s4
2005; GFX9-NEXT:    s_ashr_i32 s6, s11, 31
2006; GFX9-NEXT:    s_add_i32 s8, s11, s6
2007; GFX9-NEXT:    s_xor_b32 s8, s8, s6
2008; GFX9-NEXT:    v_mul_hi_u32 v2, v3, v2
2009; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s8
2010; GFX9-NEXT:    s_xor_b32 s5, s5, s4
2011; GFX9-NEXT:    v_xor_b32_e32 v1, s2, v1
2012; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
2013; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v5
2014; GFX9-NEXT:    v_mul_hi_u32 v2, s5, v2
2015; GFX9-NEXT:    v_subrev_u32_e32 v1, s2, v1
2016; GFX9-NEXT:    s_xor_b32 s2, s4, s3
2017; GFX9-NEXT:    v_mul_f32_e32 v3, s13, v3
2018; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
2019; GFX9-NEXT:    v_mul_lo_u32 v5, v2, s9
2020; GFX9-NEXT:    s_sub_i32 s3, 0, s8
2021; GFX9-NEXT:    v_add_u32_e32 v6, 1, v2
2022; GFX9-NEXT:    v_mul_lo_u32 v7, s3, v3
2023; GFX9-NEXT:    v_sub_u32_e32 v5, s5, v5
2024; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v5
2025; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
2026; GFX9-NEXT:    v_subrev_u32_e32 v6, s9, v5
2027; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
2028; GFX9-NEXT:    v_mul_hi_u32 v6, v3, v7
2029; GFX9-NEXT:    s_ashr_i32 s3, s7, 31
2030; GFX9-NEXT:    s_add_i32 s4, s7, s3
2031; GFX9-NEXT:    s_xor_b32 s4, s4, s3
2032; GFX9-NEXT:    v_add_u32_e32 v3, v3, v6
2033; GFX9-NEXT:    v_mul_hi_u32 v3, s4, v3
2034; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v5
2035; GFX9-NEXT:    v_add_u32_e32 v6, 1, v2
2036; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
2037; GFX9-NEXT:    v_mul_lo_u32 v5, v3, s8
2038; GFX9-NEXT:    v_add_u32_e32 v6, 1, v3
2039; GFX9-NEXT:    v_xor_b32_e32 v2, s2, v2
2040; GFX9-NEXT:    v_subrev_u32_e32 v2, s2, v2
2041; GFX9-NEXT:    v_sub_u32_e32 v5, s4, v5
2042; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v5
2043; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
2044; GFX9-NEXT:    v_subrev_u32_e32 v6, s8, v5
2045; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
2046; GFX9-NEXT:    v_add_u32_e32 v6, 1, v3
2047; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v5
2048; GFX9-NEXT:    s_xor_b32 s2, s3, s6
2049; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
2050; GFX9-NEXT:    v_xor_b32_e32 v3, s2, v3
2051; GFX9-NEXT:    v_subrev_u32_e32 v3, s2, v3
2052; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
2053; GFX9-NEXT:    s_endpgm
2054  %r = sdiv <4 x i32> %x, %y
2055  store <4 x i32> %r, <4 x i32> addrspace(1)* %out
2056  ret void
2057}
2058
2059define amdgpu_kernel void @srem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
2060; CHECK-LABEL: @srem_v4i32(
2061; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i64 0
2062; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 0
2063; CHECK-NEXT:    [[TMP3:%.*]] = ashr i32 [[TMP1]], 31
2064; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP2]], 31
2065; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[TMP1]], [[TMP3]]
2066; CHECK-NEXT:    [[TMP6:%.*]] = add i32 [[TMP2]], [[TMP4]]
2067; CHECK-NEXT:    [[TMP7:%.*]] = xor i32 [[TMP5]], [[TMP3]]
2068; CHECK-NEXT:    [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP4]]
2069; CHECK-NEXT:    [[TMP9:%.*]] = uitofp i32 [[TMP8]] to float
2070; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
2071; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP10]], 0x41EFFFFFC0000000
2072; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP11]] to i32
2073; CHECK-NEXT:    [[TMP13:%.*]] = sub i32 0, [[TMP8]]
2074; CHECK-NEXT:    [[TMP14:%.*]] = mul i32 [[TMP13]], [[TMP12]]
2075; CHECK-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP12]] to i64
2076; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP14]] to i64
2077; CHECK-NEXT:    [[TMP17:%.*]] = mul i64 [[TMP15]], [[TMP16]]
2078; CHECK-NEXT:    [[TMP18:%.*]] = trunc i64 [[TMP17]] to i32
2079; CHECK-NEXT:    [[TMP19:%.*]] = lshr i64 [[TMP17]], 32
2080; CHECK-NEXT:    [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32
2081; CHECK-NEXT:    [[TMP21:%.*]] = add i32 [[TMP12]], [[TMP20]]
2082; CHECK-NEXT:    [[TMP22:%.*]] = zext i32 [[TMP7]] to i64
2083; CHECK-NEXT:    [[TMP23:%.*]] = zext i32 [[TMP21]] to i64
2084; CHECK-NEXT:    [[TMP24:%.*]] = mul i64 [[TMP22]], [[TMP23]]
2085; CHECK-NEXT:    [[TMP25:%.*]] = trunc i64 [[TMP24]] to i32
2086; CHECK-NEXT:    [[TMP26:%.*]] = lshr i64 [[TMP24]], 32
2087; CHECK-NEXT:    [[TMP27:%.*]] = trunc i64 [[TMP26]] to i32
2088; CHECK-NEXT:    [[TMP28:%.*]] = mul i32 [[TMP27]], [[TMP8]]
2089; CHECK-NEXT:    [[TMP29:%.*]] = sub i32 [[TMP7]], [[TMP28]]
2090; CHECK-NEXT:    [[TMP30:%.*]] = icmp uge i32 [[TMP29]], [[TMP8]]
2091; CHECK-NEXT:    [[TMP31:%.*]] = sub i32 [[TMP29]], [[TMP8]]
2092; CHECK-NEXT:    [[TMP32:%.*]] = select i1 [[TMP30]], i32 [[TMP31]], i32 [[TMP29]]
2093; CHECK-NEXT:    [[TMP33:%.*]] = icmp uge i32 [[TMP32]], [[TMP8]]
2094; CHECK-NEXT:    [[TMP34:%.*]] = sub i32 [[TMP32]], [[TMP8]]
2095; CHECK-NEXT:    [[TMP35:%.*]] = select i1 [[TMP33]], i32 [[TMP34]], i32 [[TMP32]]
2096; CHECK-NEXT:    [[TMP36:%.*]] = xor i32 [[TMP35]], [[TMP3]]
2097; CHECK-NEXT:    [[TMP37:%.*]] = sub i32 [[TMP36]], [[TMP3]]
2098; CHECK-NEXT:    [[TMP38:%.*]] = insertelement <4 x i32> undef, i32 [[TMP37]], i64 0
2099; CHECK-NEXT:    [[TMP39:%.*]] = extractelement <4 x i32> [[X]], i64 1
2100; CHECK-NEXT:    [[TMP40:%.*]] = extractelement <4 x i32> [[Y]], i64 1
2101; CHECK-NEXT:    [[TMP41:%.*]] = ashr i32 [[TMP39]], 31
2102; CHECK-NEXT:    [[TMP42:%.*]] = ashr i32 [[TMP40]], 31
2103; CHECK-NEXT:    [[TMP43:%.*]] = add i32 [[TMP39]], [[TMP41]]
2104; CHECK-NEXT:    [[TMP44:%.*]] = add i32 [[TMP40]], [[TMP42]]
2105; CHECK-NEXT:    [[TMP45:%.*]] = xor i32 [[TMP43]], [[TMP41]]
2106; CHECK-NEXT:    [[TMP46:%.*]] = xor i32 [[TMP44]], [[TMP42]]
2107; CHECK-NEXT:    [[TMP47:%.*]] = uitofp i32 [[TMP46]] to float
2108; CHECK-NEXT:    [[TMP48:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP47]])
2109; CHECK-NEXT:    [[TMP49:%.*]] = fmul fast float [[TMP48]], 0x41EFFFFFC0000000
2110; CHECK-NEXT:    [[TMP50:%.*]] = fptoui float [[TMP49]] to i32
2111; CHECK-NEXT:    [[TMP51:%.*]] = sub i32 0, [[TMP46]]
2112; CHECK-NEXT:    [[TMP52:%.*]] = mul i32 [[TMP51]], [[TMP50]]
2113; CHECK-NEXT:    [[TMP53:%.*]] = zext i32 [[TMP50]] to i64
2114; CHECK-NEXT:    [[TMP54:%.*]] = zext i32 [[TMP52]] to i64
2115; CHECK-NEXT:    [[TMP55:%.*]] = mul i64 [[TMP53]], [[TMP54]]
2116; CHECK-NEXT:    [[TMP56:%.*]] = trunc i64 [[TMP55]] to i32
2117; CHECK-NEXT:    [[TMP57:%.*]] = lshr i64 [[TMP55]], 32
2118; CHECK-NEXT:    [[TMP58:%.*]] = trunc i64 [[TMP57]] to i32
2119; CHECK-NEXT:    [[TMP59:%.*]] = add i32 [[TMP50]], [[TMP58]]
2120; CHECK-NEXT:    [[TMP60:%.*]] = zext i32 [[TMP45]] to i64
2121; CHECK-NEXT:    [[TMP61:%.*]] = zext i32 [[TMP59]] to i64
2122; CHECK-NEXT:    [[TMP62:%.*]] = mul i64 [[TMP60]], [[TMP61]]
2123; CHECK-NEXT:    [[TMP63:%.*]] = trunc i64 [[TMP62]] to i32
2124; CHECK-NEXT:    [[TMP64:%.*]] = lshr i64 [[TMP62]], 32
2125; CHECK-NEXT:    [[TMP65:%.*]] = trunc i64 [[TMP64]] to i32
2126; CHECK-NEXT:    [[TMP66:%.*]] = mul i32 [[TMP65]], [[TMP46]]
2127; CHECK-NEXT:    [[TMP67:%.*]] = sub i32 [[TMP45]], [[TMP66]]
2128; CHECK-NEXT:    [[TMP68:%.*]] = icmp uge i32 [[TMP67]], [[TMP46]]
2129; CHECK-NEXT:    [[TMP69:%.*]] = sub i32 [[TMP67]], [[TMP46]]
2130; CHECK-NEXT:    [[TMP70:%.*]] = select i1 [[TMP68]], i32 [[TMP69]], i32 [[TMP67]]
2131; CHECK-NEXT:    [[TMP71:%.*]] = icmp uge i32 [[TMP70]], [[TMP46]]
2132; CHECK-NEXT:    [[TMP72:%.*]] = sub i32 [[TMP70]], [[TMP46]]
2133; CHECK-NEXT:    [[TMP73:%.*]] = select i1 [[TMP71]], i32 [[TMP72]], i32 [[TMP70]]
2134; CHECK-NEXT:    [[TMP74:%.*]] = xor i32 [[TMP73]], [[TMP41]]
2135; CHECK-NEXT:    [[TMP75:%.*]] = sub i32 [[TMP74]], [[TMP41]]
2136; CHECK-NEXT:    [[TMP76:%.*]] = insertelement <4 x i32> [[TMP38]], i32 [[TMP75]], i64 1
2137; CHECK-NEXT:    [[TMP77:%.*]] = extractelement <4 x i32> [[X]], i64 2
2138; CHECK-NEXT:    [[TMP78:%.*]] = extractelement <4 x i32> [[Y]], i64 2
2139; CHECK-NEXT:    [[TMP79:%.*]] = ashr i32 [[TMP77]], 31
2140; CHECK-NEXT:    [[TMP80:%.*]] = ashr i32 [[TMP78]], 31
2141; CHECK-NEXT:    [[TMP81:%.*]] = add i32 [[TMP77]], [[TMP79]]
2142; CHECK-NEXT:    [[TMP82:%.*]] = add i32 [[TMP78]], [[TMP80]]
2143; CHECK-NEXT:    [[TMP83:%.*]] = xor i32 [[TMP81]], [[TMP79]]
2144; CHECK-NEXT:    [[TMP84:%.*]] = xor i32 [[TMP82]], [[TMP80]]
2145; CHECK-NEXT:    [[TMP85:%.*]] = uitofp i32 [[TMP84]] to float
2146; CHECK-NEXT:    [[TMP86:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP85]])
2147; CHECK-NEXT:    [[TMP87:%.*]] = fmul fast float [[TMP86]], 0x41EFFFFFC0000000
2148; CHECK-NEXT:    [[TMP88:%.*]] = fptoui float [[TMP87]] to i32
2149; CHECK-NEXT:    [[TMP89:%.*]] = sub i32 0, [[TMP84]]
2150; CHECK-NEXT:    [[TMP90:%.*]] = mul i32 [[TMP89]], [[TMP88]]
2151; CHECK-NEXT:    [[TMP91:%.*]] = zext i32 [[TMP88]] to i64
2152; CHECK-NEXT:    [[TMP92:%.*]] = zext i32 [[TMP90]] to i64
2153; CHECK-NEXT:    [[TMP93:%.*]] = mul i64 [[TMP91]], [[TMP92]]
2154; CHECK-NEXT:    [[TMP94:%.*]] = trunc i64 [[TMP93]] to i32
2155; CHECK-NEXT:    [[TMP95:%.*]] = lshr i64 [[TMP93]], 32
2156; CHECK-NEXT:    [[TMP96:%.*]] = trunc i64 [[TMP95]] to i32
2157; CHECK-NEXT:    [[TMP97:%.*]] = add i32 [[TMP88]], [[TMP96]]
2158; CHECK-NEXT:    [[TMP98:%.*]] = zext i32 [[TMP83]] to i64
2159; CHECK-NEXT:    [[TMP99:%.*]] = zext i32 [[TMP97]] to i64
2160; CHECK-NEXT:    [[TMP100:%.*]] = mul i64 [[TMP98]], [[TMP99]]
2161; CHECK-NEXT:    [[TMP101:%.*]] = trunc i64 [[TMP100]] to i32
2162; CHECK-NEXT:    [[TMP102:%.*]] = lshr i64 [[TMP100]], 32
2163; CHECK-NEXT:    [[TMP103:%.*]] = trunc i64 [[TMP102]] to i32
2164; CHECK-NEXT:    [[TMP104:%.*]] = mul i32 [[TMP103]], [[TMP84]]
2165; CHECK-NEXT:    [[TMP105:%.*]] = sub i32 [[TMP83]], [[TMP104]]
2166; CHECK-NEXT:    [[TMP106:%.*]] = icmp uge i32 [[TMP105]], [[TMP84]]
2167; CHECK-NEXT:    [[TMP107:%.*]] = sub i32 [[TMP105]], [[TMP84]]
2168; CHECK-NEXT:    [[TMP108:%.*]] = select i1 [[TMP106]], i32 [[TMP107]], i32 [[TMP105]]
2169; CHECK-NEXT:    [[TMP109:%.*]] = icmp uge i32 [[TMP108]], [[TMP84]]
2170; CHECK-NEXT:    [[TMP110:%.*]] = sub i32 [[TMP108]], [[TMP84]]
2171; CHECK-NEXT:    [[TMP111:%.*]] = select i1 [[TMP109]], i32 [[TMP110]], i32 [[TMP108]]
2172; CHECK-NEXT:    [[TMP112:%.*]] = xor i32 [[TMP111]], [[TMP79]]
2173; CHECK-NEXT:    [[TMP113:%.*]] = sub i32 [[TMP112]], [[TMP79]]
2174; CHECK-NEXT:    [[TMP114:%.*]] = insertelement <4 x i32> [[TMP76]], i32 [[TMP113]], i64 2
2175; CHECK-NEXT:    [[TMP115:%.*]] = extractelement <4 x i32> [[X]], i64 3
2176; CHECK-NEXT:    [[TMP116:%.*]] = extractelement <4 x i32> [[Y]], i64 3
2177; CHECK-NEXT:    [[TMP117:%.*]] = ashr i32 [[TMP115]], 31
2178; CHECK-NEXT:    [[TMP118:%.*]] = ashr i32 [[TMP116]], 31
2179; CHECK-NEXT:    [[TMP119:%.*]] = add i32 [[TMP115]], [[TMP117]]
2180; CHECK-NEXT:    [[TMP120:%.*]] = add i32 [[TMP116]], [[TMP118]]
2181; CHECK-NEXT:    [[TMP121:%.*]] = xor i32 [[TMP119]], [[TMP117]]
2182; CHECK-NEXT:    [[TMP122:%.*]] = xor i32 [[TMP120]], [[TMP118]]
2183; CHECK-NEXT:    [[TMP123:%.*]] = uitofp i32 [[TMP122]] to float
2184; CHECK-NEXT:    [[TMP124:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP123]])
2185; CHECK-NEXT:    [[TMP125:%.*]] = fmul fast float [[TMP124]], 0x41EFFFFFC0000000
2186; CHECK-NEXT:    [[TMP126:%.*]] = fptoui float [[TMP125]] to i32
2187; CHECK-NEXT:    [[TMP127:%.*]] = sub i32 0, [[TMP122]]
2188; CHECK-NEXT:    [[TMP128:%.*]] = mul i32 [[TMP127]], [[TMP126]]
2189; CHECK-NEXT:    [[TMP129:%.*]] = zext i32 [[TMP126]] to i64
2190; CHECK-NEXT:    [[TMP130:%.*]] = zext i32 [[TMP128]] to i64
2191; CHECK-NEXT:    [[TMP131:%.*]] = mul i64 [[TMP129]], [[TMP130]]
2192; CHECK-NEXT:    [[TMP132:%.*]] = trunc i64 [[TMP131]] to i32
2193; CHECK-NEXT:    [[TMP133:%.*]] = lshr i64 [[TMP131]], 32
2194; CHECK-NEXT:    [[TMP134:%.*]] = trunc i64 [[TMP133]] to i32
2195; CHECK-NEXT:    [[TMP135:%.*]] = add i32 [[TMP126]], [[TMP134]]
2196; CHECK-NEXT:    [[TMP136:%.*]] = zext i32 [[TMP121]] to i64
2197; CHECK-NEXT:    [[TMP137:%.*]] = zext i32 [[TMP135]] to i64
2198; CHECK-NEXT:    [[TMP138:%.*]] = mul i64 [[TMP136]], [[TMP137]]
2199; CHECK-NEXT:    [[TMP139:%.*]] = trunc i64 [[TMP138]] to i32
2200; CHECK-NEXT:    [[TMP140:%.*]] = lshr i64 [[TMP138]], 32
2201; CHECK-NEXT:    [[TMP141:%.*]] = trunc i64 [[TMP140]] to i32
2202; CHECK-NEXT:    [[TMP142:%.*]] = mul i32 [[TMP141]], [[TMP122]]
2203; CHECK-NEXT:    [[TMP143:%.*]] = sub i32 [[TMP121]], [[TMP142]]
2204; CHECK-NEXT:    [[TMP144:%.*]] = icmp uge i32 [[TMP143]], [[TMP122]]
2205; CHECK-NEXT:    [[TMP145:%.*]] = sub i32 [[TMP143]], [[TMP122]]
2206; CHECK-NEXT:    [[TMP146:%.*]] = select i1 [[TMP144]], i32 [[TMP145]], i32 [[TMP143]]
2207; CHECK-NEXT:    [[TMP147:%.*]] = icmp uge i32 [[TMP146]], [[TMP122]]
2208; CHECK-NEXT:    [[TMP148:%.*]] = sub i32 [[TMP146]], [[TMP122]]
2209; CHECK-NEXT:    [[TMP149:%.*]] = select i1 [[TMP147]], i32 [[TMP148]], i32 [[TMP146]]
2210; CHECK-NEXT:    [[TMP150:%.*]] = xor i32 [[TMP149]], [[TMP117]]
2211; CHECK-NEXT:    [[TMP151:%.*]] = sub i32 [[TMP150]], [[TMP117]]
2212; CHECK-NEXT:    [[TMP152:%.*]] = insertelement <4 x i32> [[TMP114]], i32 [[TMP151]], i64 3
2213; CHECK-NEXT:    store <4 x i32> [[TMP152]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16
2214; CHECK-NEXT:    ret void
2215;
2216; GFX6-LABEL: srem_v4i32:
2217; GFX6:       ; %bb.0:
2218; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
2219; GFX6-NEXT:    s_mov_b32 s13, 0x4f7ffffe
2220; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
2221; GFX6-NEXT:    s_mov_b32 s3, 0xf000
2222; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
2223; GFX6-NEXT:    s_ashr_i32 s2, s8, 31
2224; GFX6-NEXT:    s_add_i32 s8, s8, s2
2225; GFX6-NEXT:    s_xor_b32 s12, s8, s2
2226; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s12
2227; GFX6-NEXT:    s_ashr_i32 s8, s9, 31
2228; GFX6-NEXT:    s_add_i32 s9, s9, s8
2229; GFX6-NEXT:    s_xor_b32 s14, s9, s8
2230; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
2231; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s14
2232; GFX6-NEXT:    s_sub_i32 s9, 0, s12
2233; GFX6-NEXT:    s_ashr_i32 s8, s4, 31
2234; GFX6-NEXT:    v_mul_f32_e32 v0, s13, v0
2235; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
2236; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
2237; GFX6-NEXT:    s_add_i32 s4, s4, s8
2238; GFX6-NEXT:    s_xor_b32 s4, s4, s8
2239; GFX6-NEXT:    v_mul_lo_u32 v2, s9, v0
2240; GFX6-NEXT:    v_mul_f32_e32 v1, s13, v1
2241; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
2242; GFX6-NEXT:    s_sub_i32 s9, 0, s14
2243; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
2244; GFX6-NEXT:    s_mov_b32 s2, -1
2245; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2246; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
2247; GFX6-NEXT:    v_mul_lo_u32 v2, s9, v1
2248; GFX6-NEXT:    s_ashr_i32 s9, s5, 31
2249; GFX6-NEXT:    s_add_i32 s5, s5, s9
2250; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s12
2251; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v2
2252; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
2253; GFX6-NEXT:    s_xor_b32 s4, s5, s9
2254; GFX6-NEXT:    s_ashr_i32 s5, s10, 31
2255; GFX6-NEXT:    s_add_i32 s10, s10, s5
2256; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s12, v0
2257; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
2258; GFX6-NEXT:    s_xor_b32 s10, s10, s5
2259; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
2260; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2261; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s10
2262; GFX6-NEXT:    v_mul_hi_u32 v1, s4, v1
2263; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s12, v0
2264; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
2265; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
2266; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s14
2267; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
2268; GFX6-NEXT:    v_xor_b32_e32 v0, s8, v0
2269; GFX6-NEXT:    v_mul_f32_e32 v2, s13, v2
2270; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
2271; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s4, v1
2272; GFX6-NEXT:    s_sub_i32 s4, 0, s10
2273; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v0
2274; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s14, v1
2275; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s14, v1
2276; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v2
2277; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
2278; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s14, v1
2279; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s14, v1
2280; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
2281; GFX6-NEXT:    v_mul_hi_u32 v3, v2, v4
2282; GFX6-NEXT:    s_ashr_i32 s4, s6, 31
2283; GFX6-NEXT:    s_add_i32 s5, s6, s4
2284; GFX6-NEXT:    s_ashr_i32 s6, s11, 31
2285; GFX6-NEXT:    s_add_i32 s8, s11, s6
2286; GFX6-NEXT:    s_xor_b32 s8, s8, s6
2287; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
2288; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s8
2289; GFX6-NEXT:    s_xor_b32 s5, s5, s4
2290; GFX6-NEXT:    v_mul_hi_u32 v2, s5, v2
2291; GFX6-NEXT:    v_xor_b32_e32 v1, s9, v1
2292; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
2293; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s9, v1
2294; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s10
2295; GFX6-NEXT:    v_mul_f32_e32 v3, s13, v3
2296; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
2297; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s5, v2
2298; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s10, v2
2299; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
2300; GFX6-NEXT:    s_sub_i32 s5, 0, s8
2301; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2302; GFX6-NEXT:    v_mul_lo_u32 v4, s5, v3
2303; GFX6-NEXT:    s_ashr_i32 s5, s7, 31
2304; GFX6-NEXT:    s_add_i32 s6, s7, s5
2305; GFX6-NEXT:    s_xor_b32 s6, s6, s5
2306; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v4
2307; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s10, v2
2308; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
2309; GFX6-NEXT:    v_mul_hi_u32 v3, s6, v3
2310; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
2311; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
2312; GFX6-NEXT:    v_xor_b32_e32 v2, s4, v2
2313; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s8
2314; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s4, v2
2315; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s6, v3
2316; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s8, v3
2317; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
2318; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
2319; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s8, v3
2320; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
2321; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
2322; GFX6-NEXT:    v_xor_b32_e32 v3, s5, v3
2323; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s5, v3
2324; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
2325; GFX6-NEXT:    s_endpgm
2326;
2327; GFX9-LABEL: srem_v4i32:
2328; GFX9:       ; %bb.0:
2329; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
2330; GFX9-NEXT:    s_mov_b32 s13, 0x4f7ffffe
2331; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
2332; GFX9-NEXT:    v_mov_b32_e32 v4, 0
2333; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
2334; GFX9-NEXT:    s_ashr_i32 s2, s8, 31
2335; GFX9-NEXT:    s_add_i32 s8, s8, s2
2336; GFX9-NEXT:    s_xor_b32 s2, s8, s2
2337; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s2
2338; GFX9-NEXT:    s_ashr_i32 s3, s9, 31
2339; GFX9-NEXT:    s_sub_i32 s12, 0, s2
2340; GFX9-NEXT:    s_add_i32 s8, s9, s3
2341; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
2342; GFX9-NEXT:    s_xor_b32 s3, s8, s3
2343; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s3
2344; GFX9-NEXT:    s_ashr_i32 s8, s4, 31
2345; GFX9-NEXT:    v_mul_f32_e32 v0, s13, v0
2346; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
2347; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
2348; GFX9-NEXT:    s_add_i32 s4, s4, s8
2349; GFX9-NEXT:    s_xor_b32 s4, s4, s8
2350; GFX9-NEXT:    v_mul_lo_u32 v2, s12, v0
2351; GFX9-NEXT:    v_mul_f32_e32 v1, s13, v1
2352; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
2353; GFX9-NEXT:    s_sub_i32 s12, 0, s3
2354; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
2355; GFX9-NEXT:    s_ashr_i32 s9, s5, 31
2356; GFX9-NEXT:    v_mul_lo_u32 v3, s12, v1
2357; GFX9-NEXT:    s_add_i32 s5, s5, s9
2358; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
2359; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
2360; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
2361; GFX9-NEXT:    s_xor_b32 s5, s5, s9
2362; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s2
2363; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
2364; GFX9-NEXT:    v_mul_hi_u32 v1, s5, v1
2365; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
2366; GFX9-NEXT:    v_subrev_u32_e32 v2, s2, v0
2367; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v0
2368; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
2369; GFX9-NEXT:    v_subrev_u32_e32 v2, s2, v0
2370; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v0
2371; GFX9-NEXT:    s_ashr_i32 s2, s10, 31
2372; GFX9-NEXT:    s_add_i32 s4, s10, s2
2373; GFX9-NEXT:    s_xor_b32 s2, s4, s2
2374; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
2375; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, s2
2376; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s3
2377; GFX9-NEXT:    s_sub_i32 s4, 0, s2
2378; GFX9-NEXT:    v_xor_b32_e32 v0, s8, v0
2379; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v2
2380; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v1
2381; GFX9-NEXT:    v_subrev_u32_e32 v3, s3, v1
2382; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
2383; GFX9-NEXT:    v_mul_f32_e32 v2, s13, v2
2384; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
2385; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
2386; GFX9-NEXT:    v_subrev_u32_e32 v3, s3, v1
2387; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
2388; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
2389; GFX9-NEXT:    v_mul_lo_u32 v3, s4, v2
2390; GFX9-NEXT:    s_ashr_i32 s4, s11, 31
2391; GFX9-NEXT:    s_add_i32 s5, s11, s4
2392; GFX9-NEXT:    s_xor_b32 s4, s5, s4
2393; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s4
2394; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v3
2395; GFX9-NEXT:    s_ashr_i32 s3, s6, 31
2396; GFX9-NEXT:    s_add_i32 s5, s6, s3
2397; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v5
2398; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
2399; GFX9-NEXT:    s_xor_b32 s5, s5, s3
2400; GFX9-NEXT:    v_mul_hi_u32 v2, s5, v2
2401; GFX9-NEXT:    v_mul_f32_e32 v3, s13, v5
2402; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
2403; GFX9-NEXT:    s_sub_i32 s6, 0, s4
2404; GFX9-NEXT:    v_mul_lo_u32 v2, v2, s2
2405; GFX9-NEXT:    v_xor_b32_e32 v1, s9, v1
2406; GFX9-NEXT:    v_mul_lo_u32 v5, s6, v3
2407; GFX9-NEXT:    v_subrev_u32_e32 v0, s8, v0
2408; GFX9-NEXT:    v_sub_u32_e32 v2, s5, v2
2409; GFX9-NEXT:    s_ashr_i32 s5, s7, 31
2410; GFX9-NEXT:    v_mul_hi_u32 v5, v3, v5
2411; GFX9-NEXT:    s_add_i32 s6, s7, s5
2412; GFX9-NEXT:    s_xor_b32 s6, s6, s5
2413; GFX9-NEXT:    v_subrev_u32_e32 v6, s2, v2
2414; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
2415; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v3
2416; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v2
2417; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
2418; GFX9-NEXT:    v_subrev_u32_e32 v5, s2, v2
2419; GFX9-NEXT:    v_mul_lo_u32 v3, v3, s4
2420; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v2
2421; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
2422; GFX9-NEXT:    v_xor_b32_e32 v2, s3, v2
2423; GFX9-NEXT:    v_sub_u32_e32 v3, s6, v3
2424; GFX9-NEXT:    v_subrev_u32_e32 v5, s4, v3
2425; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v3
2426; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
2427; GFX9-NEXT:    v_subrev_u32_e32 v5, s4, v3
2428; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v3
2429; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
2430; GFX9-NEXT:    v_xor_b32_e32 v3, s5, v3
2431; GFX9-NEXT:    v_subrev_u32_e32 v1, s9, v1
2432; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v2
2433; GFX9-NEXT:    v_subrev_u32_e32 v3, s5, v3
2434; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
2435; GFX9-NEXT:    s_endpgm
2436  %r = srem <4 x i32> %x, %y
2437  store <4 x i32> %r, <4 x i32> addrspace(1)* %out
2438  ret void
2439}
2440
2441define amdgpu_kernel void @udiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x, <4 x i16> %y) {
2442; CHECK-LABEL: @udiv_v4i16(
2443; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i16> [[X:%.*]], i64 0
2444; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i16> [[Y:%.*]], i64 0
2445; CHECK-NEXT:    [[TMP3:%.*]] = zext i16 [[TMP1]] to i32
2446; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[TMP2]] to i32
2447; CHECK-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float
2448; CHECK-NEXT:    [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float
2449; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])
2450; CHECK-NEXT:    [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]
2451; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])
2452; CHECK-NEXT:    [[TMP10:%.*]] = fneg fast float [[TMP9]]
2453; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])
2454; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP9]] to i32
2455; CHECK-NEXT:    [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])
2456; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])
2457; CHECK-NEXT:    [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]
2458; CHECK-NEXT:    [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 0
2459; CHECK-NEXT:    [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]
2460; CHECK-NEXT:    [[TMP18:%.*]] = and i32 [[TMP17]], 65535
2461; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i16
2462; CHECK-NEXT:    [[TMP20:%.*]] = insertelement <4 x i16> undef, i16 [[TMP19]], i64 0
2463; CHECK-NEXT:    [[TMP21:%.*]] = extractelement <4 x i16> [[X]], i64 1
2464; CHECK-NEXT:    [[TMP22:%.*]] = extractelement <4 x i16> [[Y]], i64 1
2465; CHECK-NEXT:    [[TMP23:%.*]] = zext i16 [[TMP21]] to i32
2466; CHECK-NEXT:    [[TMP24:%.*]] = zext i16 [[TMP22]] to i32
2467; CHECK-NEXT:    [[TMP25:%.*]] = uitofp i32 [[TMP23]] to float
2468; CHECK-NEXT:    [[TMP26:%.*]] = uitofp i32 [[TMP24]] to float
2469; CHECK-NEXT:    [[TMP27:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP26]])
2470; CHECK-NEXT:    [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]]
2471; CHECK-NEXT:    [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]])
2472; CHECK-NEXT:    [[TMP30:%.*]] = fneg fast float [[TMP29]]
2473; CHECK-NEXT:    [[TMP31:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP30]], float [[TMP26]], float [[TMP25]])
2474; CHECK-NEXT:    [[TMP32:%.*]] = fptoui float [[TMP29]] to i32
2475; CHECK-NEXT:    [[TMP33:%.*]] = call fast float @llvm.fabs.f32(float [[TMP31]])
2476; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.fabs.f32(float [[TMP26]])
2477; CHECK-NEXT:    [[TMP35:%.*]] = fcmp fast oge float [[TMP33]], [[TMP34]]
2478; CHECK-NEXT:    [[TMP36:%.*]] = select i1 [[TMP35]], i32 1, i32 0
2479; CHECK-NEXT:    [[TMP37:%.*]] = add i32 [[TMP32]], [[TMP36]]
2480; CHECK-NEXT:    [[TMP38:%.*]] = and i32 [[TMP37]], 65535
2481; CHECK-NEXT:    [[TMP39:%.*]] = trunc i32 [[TMP38]] to i16
2482; CHECK-NEXT:    [[TMP40:%.*]] = insertelement <4 x i16> [[TMP20]], i16 [[TMP39]], i64 1
2483; CHECK-NEXT:    [[TMP41:%.*]] = extractelement <4 x i16> [[X]], i64 2
2484; CHECK-NEXT:    [[TMP42:%.*]] = extractelement <4 x i16> [[Y]], i64 2
2485; CHECK-NEXT:    [[TMP43:%.*]] = zext i16 [[TMP41]] to i32
2486; CHECK-NEXT:    [[TMP44:%.*]] = zext i16 [[TMP42]] to i32
2487; CHECK-NEXT:    [[TMP45:%.*]] = uitofp i32 [[TMP43]] to float
2488; CHECK-NEXT:    [[TMP46:%.*]] = uitofp i32 [[TMP44]] to float
2489; CHECK-NEXT:    [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]])
2490; CHECK-NEXT:    [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]]
2491; CHECK-NEXT:    [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]])
2492; CHECK-NEXT:    [[TMP50:%.*]] = fneg fast float [[TMP49]]
2493; CHECK-NEXT:    [[TMP51:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP50]], float [[TMP46]], float [[TMP45]])
2494; CHECK-NEXT:    [[TMP52:%.*]] = fptoui float [[TMP49]] to i32
2495; CHECK-NEXT:    [[TMP53:%.*]] = call fast float @llvm.fabs.f32(float [[TMP51]])
2496; CHECK-NEXT:    [[TMP54:%.*]] = call fast float @llvm.fabs.f32(float [[TMP46]])
2497; CHECK-NEXT:    [[TMP55:%.*]] = fcmp fast oge float [[TMP53]], [[TMP54]]
2498; CHECK-NEXT:    [[TMP56:%.*]] = select i1 [[TMP55]], i32 1, i32 0
2499; CHECK-NEXT:    [[TMP57:%.*]] = add i32 [[TMP52]], [[TMP56]]
2500; CHECK-NEXT:    [[TMP58:%.*]] = and i32 [[TMP57]], 65535
2501; CHECK-NEXT:    [[TMP59:%.*]] = trunc i32 [[TMP58]] to i16
2502; CHECK-NEXT:    [[TMP60:%.*]] = insertelement <4 x i16> [[TMP40]], i16 [[TMP59]], i64 2
2503; CHECK-NEXT:    [[TMP61:%.*]] = extractelement <4 x i16> [[X]], i64 3
2504; CHECK-NEXT:    [[TMP62:%.*]] = extractelement <4 x i16> [[Y]], i64 3
2505; CHECK-NEXT:    [[TMP63:%.*]] = zext i16 [[TMP61]] to i32
2506; CHECK-NEXT:    [[TMP64:%.*]] = zext i16 [[TMP62]] to i32
2507; CHECK-NEXT:    [[TMP65:%.*]] = uitofp i32 [[TMP63]] to float
2508; CHECK-NEXT:    [[TMP66:%.*]] = uitofp i32 [[TMP64]] to float
2509; CHECK-NEXT:    [[TMP67:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP66]])
2510; CHECK-NEXT:    [[TMP68:%.*]] = fmul fast float [[TMP65]], [[TMP67]]
2511; CHECK-NEXT:    [[TMP69:%.*]] = call fast float @llvm.trunc.f32(float [[TMP68]])
2512; CHECK-NEXT:    [[TMP70:%.*]] = fneg fast float [[TMP69]]
2513; CHECK-NEXT:    [[TMP71:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP70]], float [[TMP66]], float [[TMP65]])
2514; CHECK-NEXT:    [[TMP72:%.*]] = fptoui float [[TMP69]] to i32
2515; CHECK-NEXT:    [[TMP73:%.*]] = call fast float @llvm.fabs.f32(float [[TMP71]])
2516; CHECK-NEXT:    [[TMP74:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]])
2517; CHECK-NEXT:    [[TMP75:%.*]] = fcmp fast oge float [[TMP73]], [[TMP74]]
2518; CHECK-NEXT:    [[TMP76:%.*]] = select i1 [[TMP75]], i32 1, i32 0
2519; CHECK-NEXT:    [[TMP77:%.*]] = add i32 [[TMP72]], [[TMP76]]
2520; CHECK-NEXT:    [[TMP78:%.*]] = and i32 [[TMP77]], 65535
2521; CHECK-NEXT:    [[TMP79:%.*]] = trunc i32 [[TMP78]] to i16
2522; CHECK-NEXT:    [[TMP80:%.*]] = insertelement <4 x i16> [[TMP60]], i16 [[TMP79]], i64 3
2523; CHECK-NEXT:    store <4 x i16> [[TMP80]], <4 x i16> addrspace(1)* [[OUT:%.*]], align 8
2524; CHECK-NEXT:    ret void
2525;
2526; GFX6-LABEL: udiv_v4i16:
2527; GFX6:       ; %bb.0:
2528; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
2529; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xb
2530; GFX6-NEXT:    s_mov_b32 s8, 0xffff
2531; GFX6-NEXT:    s_mov_b32 s7, 0xf000
2532; GFX6-NEXT:    s_mov_b32 s6, -1
2533; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
2534; GFX6-NEXT:    s_and_b32 s9, s2, s8
2535; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s9
2536; GFX6-NEXT:    s_lshr_b32 s9, s0, 16
2537; GFX6-NEXT:    s_and_b32 s0, s0, s8
2538; GFX6-NEXT:    s_lshr_b32 s2, s2, 16
2539; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s2
2540; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s0
2541; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
2542; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s9
2543; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
2544; GFX6-NEXT:    s_and_b32 s2, s3, s8
2545; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
2546; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
2547; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
2548; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
2549; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
2550; GFX6-NEXT:    v_mul_f32_e32 v1, v4, v5
2551; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
2552; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
2553; GFX6-NEXT:    v_mad_f32 v2, -v1, v3, v4
2554; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s2
2555; GFX6-NEXT:    s_lshr_b32 s0, s1, 16
2556; GFX6-NEXT:    s_and_b32 s1, s1, s8
2557; GFX6-NEXT:    s_lshr_b32 s10, s3, 16
2558; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
2559; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
2560; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s10
2561; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s1
2562; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v4
2563; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v1, vcc
2564; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v3
2565; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
2566; GFX6-NEXT:    v_mul_f32_e32 v1, v5, v6
2567; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s0
2568; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
2569; GFX6-NEXT:    v_mad_f32 v5, -v1, v4, v5
2570; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v4
2571; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
2572; GFX6-NEXT:    v_mul_f32_e32 v4, v6, v7
2573; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
2574; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v4
2575; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
2576; GFX6-NEXT:    v_mad_f32 v4, -v4, v3, v6
2577; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v3
2578; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
2579; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
2580; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
2581; GFX6-NEXT:    v_and_b32_e32 v1, s8, v1
2582; GFX6-NEXT:    v_or_b32_e32 v1, v1, v3
2583; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
2584; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
2585; GFX6-NEXT:    s_endpgm
2586;
2587; GFX9-LABEL: udiv_v4i16:
2588; GFX9:       ; %bb.0:
2589; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
2590; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
2591; GFX9-NEXT:    s_mov_b32 s8, 0xffff
2592; GFX9-NEXT:    v_mov_b32_e32 v2, 0
2593; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
2594; GFX9-NEXT:    s_and_b32 s1, s6, s8
2595; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s1
2596; GFX9-NEXT:    s_lshr_b32 s0, s4, 16
2597; GFX9-NEXT:    s_and_b32 s4, s4, s8
2598; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s4
2599; GFX9-NEXT:    s_lshr_b32 s4, s6, 16
2600; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
2601; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s4
2602; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s0
2603; GFX9-NEXT:    s_and_b32 s0, s7, s8
2604; GFX9-NEXT:    v_mul_f32_e32 v3, v1, v3
2605; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v4
2606; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
2607; GFX9-NEXT:    v_mad_f32 v1, -v3, v0, v1
2608; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
2609; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
2610; GFX9-NEXT:    v_mul_f32_e32 v1, v5, v6
2611; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
2612; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
2613; GFX9-NEXT:    v_mad_f32 v3, -v1, v4, v5
2614; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s0
2615; GFX9-NEXT:    s_and_b32 s0, s5, s8
2616; GFX9-NEXT:    s_lshr_b32 s6, s7, 16
2617; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v4
2618; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
2619; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s6
2620; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
2621; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v5
2622; GFX9-NEXT:    s_lshr_b32 s1, s5, 16
2623; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
2624; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v4
2625; GFX9-NEXT:    v_mul_f32_e32 v1, v6, v7
2626; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s1
2627; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
2628; GFX9-NEXT:    v_mad_f32 v6, -v1, v5, v6
2629; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, v5
2630; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
2631; GFX9-NEXT:    v_mul_f32_e32 v5, v7, v8
2632; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
2633; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v5
2634; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
2635; GFX9-NEXT:    v_mad_f32 v5, -v5, v4, v7
2636; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v4
2637; GFX9-NEXT:    v_mov_b32_e32 v5, 0xffff
2638; GFX9-NEXT:    v_and_b32_e32 v0, v5, v0
2639; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v6, vcc
2640; GFX9-NEXT:    v_and_b32_e32 v1, v5, v1
2641; GFX9-NEXT:    v_lshl_or_b32 v1, v4, 16, v1
2642; GFX9-NEXT:    v_lshl_or_b32 v0, v3, 16, v0
2643; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
2644; GFX9-NEXT:    s_endpgm
2645  %r = udiv <4 x i16> %x, %y
2646  store <4 x i16> %r, <4 x i16> addrspace(1)* %out
2647  ret void
2648}
2649
2650define amdgpu_kernel void @urem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x, <4 x i16> %y) {
2651; CHECK-LABEL: @urem_v4i16(
2652; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i16> [[X:%.*]], i64 0
2653; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i16> [[Y:%.*]], i64 0
2654; CHECK-NEXT:    [[TMP3:%.*]] = zext i16 [[TMP1]] to i32
2655; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[TMP2]] to i32
2656; CHECK-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float
2657; CHECK-NEXT:    [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float
2658; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])
2659; CHECK-NEXT:    [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]
2660; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])
2661; CHECK-NEXT:    [[TMP10:%.*]] = fneg fast float [[TMP9]]
2662; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])
2663; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP9]] to i32
2664; CHECK-NEXT:    [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])
2665; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])
2666; CHECK-NEXT:    [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]
2667; CHECK-NEXT:    [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 0
2668; CHECK-NEXT:    [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]
2669; CHECK-NEXT:    [[TMP18:%.*]] = mul i32 [[TMP17]], [[TMP4]]
2670; CHECK-NEXT:    [[TMP19:%.*]] = sub i32 [[TMP3]], [[TMP18]]
2671; CHECK-NEXT:    [[TMP20:%.*]] = and i32 [[TMP19]], 65535
2672; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i16
2673; CHECK-NEXT:    [[TMP22:%.*]] = insertelement <4 x i16> undef, i16 [[TMP21]], i64 0
2674; CHECK-NEXT:    [[TMP23:%.*]] = extractelement <4 x i16> [[X]], i64 1
2675; CHECK-NEXT:    [[TMP24:%.*]] = extractelement <4 x i16> [[Y]], i64 1
2676; CHECK-NEXT:    [[TMP25:%.*]] = zext i16 [[TMP23]] to i32
2677; CHECK-NEXT:    [[TMP26:%.*]] = zext i16 [[TMP24]] to i32
2678; CHECK-NEXT:    [[TMP27:%.*]] = uitofp i32 [[TMP25]] to float
2679; CHECK-NEXT:    [[TMP28:%.*]] = uitofp i32 [[TMP26]] to float
2680; CHECK-NEXT:    [[TMP29:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP28]])
2681; CHECK-NEXT:    [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]]
2682; CHECK-NEXT:    [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]])
2683; CHECK-NEXT:    [[TMP32:%.*]] = fneg fast float [[TMP31]]
2684; CHECK-NEXT:    [[TMP33:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP32]], float [[TMP28]], float [[TMP27]])
2685; CHECK-NEXT:    [[TMP34:%.*]] = fptoui float [[TMP31]] to i32
2686; CHECK-NEXT:    [[TMP35:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
2687; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.fabs.f32(float [[TMP28]])
2688; CHECK-NEXT:    [[TMP37:%.*]] = fcmp fast oge float [[TMP35]], [[TMP36]]
2689; CHECK-NEXT:    [[TMP38:%.*]] = select i1 [[TMP37]], i32 1, i32 0
2690; CHECK-NEXT:    [[TMP39:%.*]] = add i32 [[TMP34]], [[TMP38]]
2691; CHECK-NEXT:    [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP26]]
2692; CHECK-NEXT:    [[TMP41:%.*]] = sub i32 [[TMP25]], [[TMP40]]
2693; CHECK-NEXT:    [[TMP42:%.*]] = and i32 [[TMP41]], 65535
2694; CHECK-NEXT:    [[TMP43:%.*]] = trunc i32 [[TMP42]] to i16
2695; CHECK-NEXT:    [[TMP44:%.*]] = insertelement <4 x i16> [[TMP22]], i16 [[TMP43]], i64 1
2696; CHECK-NEXT:    [[TMP45:%.*]] = extractelement <4 x i16> [[X]], i64 2
2697; CHECK-NEXT:    [[TMP46:%.*]] = extractelement <4 x i16> [[Y]], i64 2
2698; CHECK-NEXT:    [[TMP47:%.*]] = zext i16 [[TMP45]] to i32
2699; CHECK-NEXT:    [[TMP48:%.*]] = zext i16 [[TMP46]] to i32
2700; CHECK-NEXT:    [[TMP49:%.*]] = uitofp i32 [[TMP47]] to float
2701; CHECK-NEXT:    [[TMP50:%.*]] = uitofp i32 [[TMP48]] to float
2702; CHECK-NEXT:    [[TMP51:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP50]])
2703; CHECK-NEXT:    [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]]
2704; CHECK-NEXT:    [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]])
2705; CHECK-NEXT:    [[TMP54:%.*]] = fneg fast float [[TMP53]]
2706; CHECK-NEXT:    [[TMP55:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP54]], float [[TMP50]], float [[TMP49]])
2707; CHECK-NEXT:    [[TMP56:%.*]] = fptoui float [[TMP53]] to i32
2708; CHECK-NEXT:    [[TMP57:%.*]] = call fast float @llvm.fabs.f32(float [[TMP55]])
2709; CHECK-NEXT:    [[TMP58:%.*]] = call fast float @llvm.fabs.f32(float [[TMP50]])
2710; CHECK-NEXT:    [[TMP59:%.*]] = fcmp fast oge float [[TMP57]], [[TMP58]]
2711; CHECK-NEXT:    [[TMP60:%.*]] = select i1 [[TMP59]], i32 1, i32 0
2712; CHECK-NEXT:    [[TMP61:%.*]] = add i32 [[TMP56]], [[TMP60]]
2713; CHECK-NEXT:    [[TMP62:%.*]] = mul i32 [[TMP61]], [[TMP48]]
2714; CHECK-NEXT:    [[TMP63:%.*]] = sub i32 [[TMP47]], [[TMP62]]
2715; CHECK-NEXT:    [[TMP64:%.*]] = and i32 [[TMP63]], 65535
2716; CHECK-NEXT:    [[TMP65:%.*]] = trunc i32 [[TMP64]] to i16
2717; CHECK-NEXT:    [[TMP66:%.*]] = insertelement <4 x i16> [[TMP44]], i16 [[TMP65]], i64 2
2718; CHECK-NEXT:    [[TMP67:%.*]] = extractelement <4 x i16> [[X]], i64 3
2719; CHECK-NEXT:    [[TMP68:%.*]] = extractelement <4 x i16> [[Y]], i64 3
2720; CHECK-NEXT:    [[TMP69:%.*]] = zext i16 [[TMP67]] to i32
2721; CHECK-NEXT:    [[TMP70:%.*]] = zext i16 [[TMP68]] to i32
2722; CHECK-NEXT:    [[TMP71:%.*]] = uitofp i32 [[TMP69]] to float
2723; CHECK-NEXT:    [[TMP72:%.*]] = uitofp i32 [[TMP70]] to float
2724; CHECK-NEXT:    [[TMP73:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP72]])
2725; CHECK-NEXT:    [[TMP74:%.*]] = fmul fast float [[TMP71]], [[TMP73]]
2726; CHECK-NEXT:    [[TMP75:%.*]] = call fast float @llvm.trunc.f32(float [[TMP74]])
2727; CHECK-NEXT:    [[TMP76:%.*]] = fneg fast float [[TMP75]]
2728; CHECK-NEXT:    [[TMP77:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP76]], float [[TMP72]], float [[TMP71]])
2729; CHECK-NEXT:    [[TMP78:%.*]] = fptoui float [[TMP75]] to i32
2730; CHECK-NEXT:    [[TMP79:%.*]] = call fast float @llvm.fabs.f32(float [[TMP77]])
2731; CHECK-NEXT:    [[TMP80:%.*]] = call fast float @llvm.fabs.f32(float [[TMP72]])
2732; CHECK-NEXT:    [[TMP81:%.*]] = fcmp fast oge float [[TMP79]], [[TMP80]]
2733; CHECK-NEXT:    [[TMP82:%.*]] = select i1 [[TMP81]], i32 1, i32 0
2734; CHECK-NEXT:    [[TMP83:%.*]] = add i32 [[TMP78]], [[TMP82]]
2735; CHECK-NEXT:    [[TMP84:%.*]] = mul i32 [[TMP83]], [[TMP70]]
2736; CHECK-NEXT:    [[TMP85:%.*]] = sub i32 [[TMP69]], [[TMP84]]
2737; CHECK-NEXT:    [[TMP86:%.*]] = and i32 [[TMP85]], 65535
2738; CHECK-NEXT:    [[TMP87:%.*]] = trunc i32 [[TMP86]] to i16
2739; CHECK-NEXT:    [[TMP88:%.*]] = insertelement <4 x i16> [[TMP66]], i16 [[TMP87]], i64 3
2740; CHECK-NEXT:    store <4 x i16> [[TMP88]], <4 x i16> addrspace(1)* [[OUT:%.*]], align 8
2741; CHECK-NEXT:    ret void
2742;
2743; GFX6-LABEL: urem_v4i16:
2744; GFX6:       ; %bb.0:
2745; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
2746; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xb
2747; GFX6-NEXT:    s_mov_b32 s8, 0xffff
2748; GFX6-NEXT:    s_mov_b32 s7, 0xf000
2749; GFX6-NEXT:    s_mov_b32 s6, -1
2750; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
2751; GFX6-NEXT:    s_and_b32 s9, s2, s8
2752; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s9
2753; GFX6-NEXT:    s_and_b32 s10, s0, s8
2754; GFX6-NEXT:    s_lshr_b32 s11, s2, 16
2755; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s10
2756; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
2757; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s11
2758; GFX6-NEXT:    s_lshr_b32 s9, s0, 16
2759; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s9
2760; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
2761; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
2762; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
2763; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
2764; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
2765; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
2766; GFX6-NEXT:    v_mul_f32_e32 v1, v4, v5
2767; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
2768; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
2769; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v1
2770; GFX6-NEXT:    v_mad_f32 v1, -v1, v3, v4
2771; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v3
2772; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
2773; GFX6-NEXT:    s_and_b32 s2, s3, s8
2774; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
2775; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s2
2776; GFX6-NEXT:    s_and_b32 s2, s1, s8
2777; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s11
2778; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s2
2779; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
2780; GFX6-NEXT:    s_lshr_b32 s12, s3, 16
2781; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s9, v1
2782; GFX6-NEXT:    s_lshr_b32 s10, s1, 16
2783; GFX6-NEXT:    v_mul_f32_e32 v1, v3, v4
2784; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s12
2785; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s10
2786; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
2787; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
2788; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v4
2789; GFX6-NEXT:    v_mad_f32 v3, -v1, v2, v3
2790; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v2
2791; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
2792; GFX6-NEXT:    v_mul_f32_e32 v2, v6, v7
2793; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
2794; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v2
2795; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
2796; GFX6-NEXT:    v_mad_f32 v2, -v2, v4, v6
2797; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
2798; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
2799; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s3
2800; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s12
2801; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
2802; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v1
2803; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s10, v2
2804; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
2805; GFX6-NEXT:    v_and_b32_e32 v1, s8, v1
2806; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
2807; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v5
2808; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
2809; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
2810; GFX6-NEXT:    s_endpgm
2811;
2812; GFX9-LABEL: urem_v4i16:
2813; GFX9:       ; %bb.0:
2814; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
2815; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
2816; GFX9-NEXT:    s_mov_b32 s8, 0xffff
2817; GFX9-NEXT:    v_mov_b32_e32 v2, 0
2818; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
2819; GFX9-NEXT:    s_and_b32 s1, s6, s8
2820; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s1
2821; GFX9-NEXT:    s_and_b32 s9, s4, s8
2822; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
2823; GFX9-NEXT:    s_lshr_b32 s9, s6, 16
2824; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
2825; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s9
2826; GFX9-NEXT:    s_lshr_b32 s0, s4, 16
2827; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s0
2828; GFX9-NEXT:    v_mul_f32_e32 v3, v1, v3
2829; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
2830; GFX9-NEXT:    v_mad_f32 v1, -v3, v0, v1
2831; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
2832; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v4
2833; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
2834; GFX9-NEXT:    s_lshr_b32 s10, s7, 16
2835; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
2836; GFX9-NEXT:    v_mul_f32_e32 v1, v5, v6
2837; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s6
2838; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
2839; GFX9-NEXT:    s_and_b32 s6, s7, s8
2840; GFX9-NEXT:    v_mad_f32 v3, -v1, v4, v5
2841; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s6
2842; GFX9-NEXT:    s_and_b32 s6, s5, s8
2843; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v4
2844; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s10
2845; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s6
2846; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v5
2847; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
2848; GFX9-NEXT:    s_lshr_b32 s1, s5, 16
2849; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v4
2850; GFX9-NEXT:    v_mul_f32_e32 v3, v6, v7
2851; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s1
2852; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
2853; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
2854; GFX9-NEXT:    v_mad_f32 v6, -v3, v5, v6
2855; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, v5
2856; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
2857; GFX9-NEXT:    v_mul_f32_e32 v5, v7, v8
2858; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
2859; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v5
2860; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
2861; GFX9-NEXT:    v_mad_f32 v5, -v5, v4, v7
2862; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v4
2863; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v6, vcc
2864; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s9
2865; GFX9-NEXT:    v_mul_lo_u32 v3, v3, s7
2866; GFX9-NEXT:    v_mul_lo_u32 v4, v4, s10
2867; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
2868; GFX9-NEXT:    v_sub_u32_e32 v5, s0, v1
2869; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v3
2870; GFX9-NEXT:    v_sub_u32_e32 v3, s1, v4
2871; GFX9-NEXT:    v_mov_b32_e32 v4, 0xffff
2872; GFX9-NEXT:    v_and_b32_e32 v1, v4, v1
2873; GFX9-NEXT:    v_and_b32_e32 v0, v4, v0
2874; GFX9-NEXT:    v_lshl_or_b32 v1, v3, 16, v1
2875; GFX9-NEXT:    v_lshl_or_b32 v0, v5, 16, v0
2876; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
2877; GFX9-NEXT:    s_endpgm
2878  %r = urem <4 x i16> %x, %y
2879  store <4 x i16> %r, <4 x i16> addrspace(1)* %out
2880  ret void
2881}
2882
2883define amdgpu_kernel void @sdiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x, <4 x i16> %y) {
2884; CHECK-LABEL: @sdiv_v4i16(
2885; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i16> [[X:%.*]], i64 0
2886; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i16> [[Y:%.*]], i64 0
2887; CHECK-NEXT:    [[TMP3:%.*]] = sext i16 [[TMP1]] to i32
2888; CHECK-NEXT:    [[TMP4:%.*]] = sext i16 [[TMP2]] to i32
2889; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
2890; CHECK-NEXT:    [[TMP6:%.*]] = ashr i32 [[TMP5]], 30
2891; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], 1
2892; CHECK-NEXT:    [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float
2893; CHECK-NEXT:    [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float
2894; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
2895; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]
2896; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])
2897; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
2898; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
2899; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
2900; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
2901; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
2902; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
2903; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
2904; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
2905; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 16
2906; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 16
2907; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i16
2908; CHECK-NEXT:    [[TMP24:%.*]] = insertelement <4 x i16> undef, i16 [[TMP23]], i64 0
2909; CHECK-NEXT:    [[TMP25:%.*]] = extractelement <4 x i16> [[X]], i64 1
2910; CHECK-NEXT:    [[TMP26:%.*]] = extractelement <4 x i16> [[Y]], i64 1
2911; CHECK-NEXT:    [[TMP27:%.*]] = sext i16 [[TMP25]] to i32
2912; CHECK-NEXT:    [[TMP28:%.*]] = sext i16 [[TMP26]] to i32
2913; CHECK-NEXT:    [[TMP29:%.*]] = xor i32 [[TMP27]], [[TMP28]]
2914; CHECK-NEXT:    [[TMP30:%.*]] = ashr i32 [[TMP29]], 30
2915; CHECK-NEXT:    [[TMP31:%.*]] = or i32 [[TMP30]], 1
2916; CHECK-NEXT:    [[TMP32:%.*]] = sitofp i32 [[TMP27]] to float
2917; CHECK-NEXT:    [[TMP33:%.*]] = sitofp i32 [[TMP28]] to float
2918; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])
2919; CHECK-NEXT:    [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]]
2920; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]])
2921; CHECK-NEXT:    [[TMP37:%.*]] = fneg fast float [[TMP36]]
2922; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]])
2923; CHECK-NEXT:    [[TMP39:%.*]] = fptosi float [[TMP36]] to i32
2924; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]])
2925; CHECK-NEXT:    [[TMP41:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
2926; CHECK-NEXT:    [[TMP42:%.*]] = fcmp fast oge float [[TMP40]], [[TMP41]]
2927; CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP31]], i32 0
2928; CHECK-NEXT:    [[TMP44:%.*]] = add i32 [[TMP39]], [[TMP43]]
2929; CHECK-NEXT:    [[TMP45:%.*]] = shl i32 [[TMP44]], 16
2930; CHECK-NEXT:    [[TMP46:%.*]] = ashr i32 [[TMP45]], 16
2931; CHECK-NEXT:    [[TMP47:%.*]] = trunc i32 [[TMP46]] to i16
2932; CHECK-NEXT:    [[TMP48:%.*]] = insertelement <4 x i16> [[TMP24]], i16 [[TMP47]], i64 1
2933; CHECK-NEXT:    [[TMP49:%.*]] = extractelement <4 x i16> [[X]], i64 2
2934; CHECK-NEXT:    [[TMP50:%.*]] = extractelement <4 x i16> [[Y]], i64 2
2935; CHECK-NEXT:    [[TMP51:%.*]] = sext i16 [[TMP49]] to i32
2936; CHECK-NEXT:    [[TMP52:%.*]] = sext i16 [[TMP50]] to i32
2937; CHECK-NEXT:    [[TMP53:%.*]] = xor i32 [[TMP51]], [[TMP52]]
2938; CHECK-NEXT:    [[TMP54:%.*]] = ashr i32 [[TMP53]], 30
2939; CHECK-NEXT:    [[TMP55:%.*]] = or i32 [[TMP54]], 1
2940; CHECK-NEXT:    [[TMP56:%.*]] = sitofp i32 [[TMP51]] to float
2941; CHECK-NEXT:    [[TMP57:%.*]] = sitofp i32 [[TMP52]] to float
2942; CHECK-NEXT:    [[TMP58:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP57]])
2943; CHECK-NEXT:    [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]]
2944; CHECK-NEXT:    [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]])
2945; CHECK-NEXT:    [[TMP61:%.*]] = fneg fast float [[TMP60]]
2946; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]])
2947; CHECK-NEXT:    [[TMP63:%.*]] = fptosi float [[TMP60]] to i32
2948; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]])
2949; CHECK-NEXT:    [[TMP65:%.*]] = call fast float @llvm.fabs.f32(float [[TMP57]])
2950; CHECK-NEXT:    [[TMP66:%.*]] = fcmp fast oge float [[TMP64]], [[TMP65]]
2951; CHECK-NEXT:    [[TMP67:%.*]] = select i1 [[TMP66]], i32 [[TMP55]], i32 0
2952; CHECK-NEXT:    [[TMP68:%.*]] = add i32 [[TMP63]], [[TMP67]]
2953; CHECK-NEXT:    [[TMP69:%.*]] = shl i32 [[TMP68]], 16
2954; CHECK-NEXT:    [[TMP70:%.*]] = ashr i32 [[TMP69]], 16
2955; CHECK-NEXT:    [[TMP71:%.*]] = trunc i32 [[TMP70]] to i16
2956; CHECK-NEXT:    [[TMP72:%.*]] = insertelement <4 x i16> [[TMP48]], i16 [[TMP71]], i64 2
2957; CHECK-NEXT:    [[TMP73:%.*]] = extractelement <4 x i16> [[X]], i64 3
2958; CHECK-NEXT:    [[TMP74:%.*]] = extractelement <4 x i16> [[Y]], i64 3
2959; CHECK-NEXT:    [[TMP75:%.*]] = sext i16 [[TMP73]] to i32
2960; CHECK-NEXT:    [[TMP76:%.*]] = sext i16 [[TMP74]] to i32
2961; CHECK-NEXT:    [[TMP77:%.*]] = xor i32 [[TMP75]], [[TMP76]]
2962; CHECK-NEXT:    [[TMP78:%.*]] = ashr i32 [[TMP77]], 30
2963; CHECK-NEXT:    [[TMP79:%.*]] = or i32 [[TMP78]], 1
2964; CHECK-NEXT:    [[TMP80:%.*]] = sitofp i32 [[TMP75]] to float
2965; CHECK-NEXT:    [[TMP81:%.*]] = sitofp i32 [[TMP76]] to float
2966; CHECK-NEXT:    [[TMP82:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP81]])
2967; CHECK-NEXT:    [[TMP83:%.*]] = fmul fast float [[TMP80]], [[TMP82]]
2968; CHECK-NEXT:    [[TMP84:%.*]] = call fast float @llvm.trunc.f32(float [[TMP83]])
2969; CHECK-NEXT:    [[TMP85:%.*]] = fneg fast float [[TMP84]]
2970; CHECK-NEXT:    [[TMP86:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP85]], float [[TMP81]], float [[TMP80]])
2971; CHECK-NEXT:    [[TMP87:%.*]] = fptosi float [[TMP84]] to i32
2972; CHECK-NEXT:    [[TMP88:%.*]] = call fast float @llvm.fabs.f32(float [[TMP86]])
2973; CHECK-NEXT:    [[TMP89:%.*]] = call fast float @llvm.fabs.f32(float [[TMP81]])
2974; CHECK-NEXT:    [[TMP90:%.*]] = fcmp fast oge float [[TMP88]], [[TMP89]]
2975; CHECK-NEXT:    [[TMP91:%.*]] = select i1 [[TMP90]], i32 [[TMP79]], i32 0
2976; CHECK-NEXT:    [[TMP92:%.*]] = add i32 [[TMP87]], [[TMP91]]
2977; CHECK-NEXT:    [[TMP93:%.*]] = shl i32 [[TMP92]], 16
2978; CHECK-NEXT:    [[TMP94:%.*]] = ashr i32 [[TMP93]], 16
2979; CHECK-NEXT:    [[TMP95:%.*]] = trunc i32 [[TMP94]] to i16
2980; CHECK-NEXT:    [[TMP96:%.*]] = insertelement <4 x i16> [[TMP72]], i16 [[TMP95]], i64 3
2981; CHECK-NEXT:    store <4 x i16> [[TMP96]], <4 x i16> addrspace(1)* [[OUT:%.*]], align 8
2982; CHECK-NEXT:    ret void
2983;
2984; GFX6-LABEL: sdiv_v4i16:
2985; GFX6:       ; %bb.0:
2986; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
2987; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xb
2988; GFX6-NEXT:    s_mov_b32 s7, 0xf000
2989; GFX6-NEXT:    s_mov_b32 s6, -1
2990; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
2991; GFX6-NEXT:    s_sext_i32_i16 s8, s2
2992; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s8
2993; GFX6-NEXT:    s_sext_i32_i16 s9, s0
2994; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s9
2995; GFX6-NEXT:    s_xor_b32 s8, s9, s8
2996; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
2997; GFX6-NEXT:    s_ashr_i32 s2, s2, 16
2998; GFX6-NEXT:    s_ashr_i32 s8, s8, 30
2999; GFX6-NEXT:    s_or_b32 s8, s8, 1
3000; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
3001; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
3002; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
3003; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
3004; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
3005; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s2
3006; GFX6-NEXT:    v_mov_b32_e32 v3, s8
3007; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
3008; GFX6-NEXT:    s_ashr_i32 s0, s0, 16
3009; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
3010; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s0
3011; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v1
3012; GFX6-NEXT:    s_xor_b32 s0, s0, s2
3013; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
3014; GFX6-NEXT:    s_or_b32 s0, s0, 1
3015; GFX6-NEXT:    v_mul_f32_e32 v3, v2, v3
3016; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
3017; GFX6-NEXT:    v_mad_f32 v2, -v3, v1, v2
3018; GFX6-NEXT:    v_mov_b32_e32 v4, s0
3019; GFX6-NEXT:    s_sext_i32_i16 s0, s3
3020; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
3021; GFX6-NEXT:    v_cvt_i32_f32_e32 v3, v3
3022; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s0
3023; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
3024; GFX6-NEXT:    s_sext_i32_i16 s2, s1
3025; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v1, v3
3026; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s2
3027; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
3028; GFX6-NEXT:    s_xor_b32 s0, s2, s0
3029; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
3030; GFX6-NEXT:    s_or_b32 s0, s0, 1
3031; GFX6-NEXT:    v_mul_f32_e32 v4, v1, v4
3032; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
3033; GFX6-NEXT:    v_mad_f32 v1, -v4, v2, v1
3034; GFX6-NEXT:    v_mov_b32_e32 v5, s0
3035; GFX6-NEXT:    s_ashr_i32 s0, s3, 16
3036; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v2|
3037; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v4
3038; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s0
3039; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
3040; GFX6-NEXT:    s_ashr_i32 s1, s1, 16
3041; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
3042; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s1
3043; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v2
3044; GFX6-NEXT:    s_xor_b32 s0, s1, s0
3045; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
3046; GFX6-NEXT:    s_or_b32 s0, s0, 1
3047; GFX6-NEXT:    v_mul_f32_e32 v5, v4, v5
3048; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
3049; GFX6-NEXT:    v_mad_f32 v4, -v5, v2, v4
3050; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
3051; GFX6-NEXT:    v_mov_b32_e32 v6, s0
3052; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v2|
3053; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v6, vcc
3054; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
3055; GFX6-NEXT:    s_mov_b32 s0, 0xffff
3056; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
3057; GFX6-NEXT:    v_and_b32_e32 v1, s0, v1
3058; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
3059; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
3060; GFX6-NEXT:    v_and_b32_e32 v0, s0, v0
3061; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
3062; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
3063; GFX6-NEXT:    s_endpgm
3064;
3065; GFX9-LABEL: sdiv_v4i16:
3066; GFX9:       ; %bb.0:
3067; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
3068; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
3069; GFX9-NEXT:    v_mov_b32_e32 v2, 0
3070; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3071; GFX9-NEXT:    s_sext_i32_i16 s0, s6
3072; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s0
3073; GFX9-NEXT:    s_sext_i32_i16 s1, s4
3074; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s1
3075; GFX9-NEXT:    s_xor_b32 s0, s1, s0
3076; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
3077; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3078; GFX9-NEXT:    s_or_b32 s8, s0, 1
3079; GFX9-NEXT:    v_mul_f32_e32 v3, v1, v3
3080; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
3081; GFX9-NEXT:    v_mad_f32 v1, -v3, v0, v1
3082; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
3083; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
3084; GFX9-NEXT:    s_cselect_b32 s0, s8, 0
3085; GFX9-NEXT:    s_ashr_i32 s1, s6, 16
3086; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s1
3087; GFX9-NEXT:    s_ashr_i32 s4, s4, 16
3088; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s4
3089; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
3090; GFX9-NEXT:    v_rcp_iflag_f32_e32 v4, v0
3091; GFX9-NEXT:    v_add_u32_e32 v3, s0, v3
3092; GFX9-NEXT:    v_mul_f32_e32 v4, v1, v4
3093; GFX9-NEXT:    s_xor_b32 s0, s4, s1
3094; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
3095; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3096; GFX9-NEXT:    v_mad_f32 v1, -v4, v0, v1
3097; GFX9-NEXT:    s_or_b32 s4, s0, 1
3098; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
3099; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
3100; GFX9-NEXT:    s_sext_i32_i16 s1, s7
3101; GFX9-NEXT:    v_cvt_i32_f32_e32 v4, v4
3102; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s1
3103; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
3104; GFX9-NEXT:    v_add_u32_e32 v4, s0, v4
3105; GFX9-NEXT:    s_sext_i32_i16 s0, s5
3106; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s0
3107; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v0
3108; GFX9-NEXT:    s_xor_b32 s0, s0, s1
3109; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3110; GFX9-NEXT:    s_or_b32 s4, s0, 1
3111; GFX9-NEXT:    v_mul_f32_e32 v5, v1, v5
3112; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
3113; GFX9-NEXT:    v_mad_f32 v1, -v5, v0, v1
3114; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
3115; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
3116; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
3117; GFX9-NEXT:    v_cvt_i32_f32_e32 v5, v5
3118; GFX9-NEXT:    s_ashr_i32 s1, s7, 16
3119; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s1
3120; GFX9-NEXT:    v_add_u32_e32 v1, s0, v5
3121; GFX9-NEXT:    s_ashr_i32 s0, s5, 16
3122; GFX9-NEXT:    v_cvt_f32_i32_e32 v5, s0
3123; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v0
3124; GFX9-NEXT:    s_xor_b32 s0, s0, s1
3125; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3126; GFX9-NEXT:    s_or_b32 s4, s0, 1
3127; GFX9-NEXT:    v_mul_f32_e32 v6, v5, v6
3128; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
3129; GFX9-NEXT:    v_mad_f32 v5, -v6, v0, v5
3130; GFX9-NEXT:    v_cvt_i32_f32_e32 v6, v6
3131; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v5|, |v0|
3132; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
3133; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
3134; GFX9-NEXT:    v_mov_b32_e32 v5, 0xffff
3135; GFX9-NEXT:    v_add_u32_e32 v0, s0, v6
3136; GFX9-NEXT:    v_and_b32_e32 v1, v5, v1
3137; GFX9-NEXT:    v_lshl_or_b32 v1, v0, 16, v1
3138; GFX9-NEXT:    v_and_b32_e32 v0, v5, v3
3139; GFX9-NEXT:    v_lshl_or_b32 v0, v4, 16, v0
3140; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
3141; GFX9-NEXT:    s_endpgm
3142  %r = sdiv <4 x i16> %x, %y
3143  store <4 x i16> %r, <4 x i16> addrspace(1)* %out
3144  ret void
3145}
3146
3147define amdgpu_kernel void @srem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x, <4 x i16> %y) {
3148; CHECK-LABEL: @srem_v4i16(
3149; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i16> [[X:%.*]], i64 0
3150; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i16> [[Y:%.*]], i64 0
3151; CHECK-NEXT:    [[TMP3:%.*]] = sext i16 [[TMP1]] to i32
3152; CHECK-NEXT:    [[TMP4:%.*]] = sext i16 [[TMP2]] to i32
3153; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
3154; CHECK-NEXT:    [[TMP6:%.*]] = ashr i32 [[TMP5]], 30
3155; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], 1
3156; CHECK-NEXT:    [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float
3157; CHECK-NEXT:    [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float
3158; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
3159; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]
3160; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])
3161; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
3162; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
3163; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
3164; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
3165; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
3166; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
3167; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
3168; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
3169; CHECK-NEXT:    [[TMP21:%.*]] = mul i32 [[TMP20]], [[TMP4]]
3170; CHECK-NEXT:    [[TMP22:%.*]] = sub i32 [[TMP3]], [[TMP21]]
3171; CHECK-NEXT:    [[TMP23:%.*]] = shl i32 [[TMP22]], 16
3172; CHECK-NEXT:    [[TMP24:%.*]] = ashr i32 [[TMP23]], 16
3173; CHECK-NEXT:    [[TMP25:%.*]] = trunc i32 [[TMP24]] to i16
3174; CHECK-NEXT:    [[TMP26:%.*]] = insertelement <4 x i16> undef, i16 [[TMP25]], i64 0
3175; CHECK-NEXT:    [[TMP27:%.*]] = extractelement <4 x i16> [[X]], i64 1
3176; CHECK-NEXT:    [[TMP28:%.*]] = extractelement <4 x i16> [[Y]], i64 1
3177; CHECK-NEXT:    [[TMP29:%.*]] = sext i16 [[TMP27]] to i32
3178; CHECK-NEXT:    [[TMP30:%.*]] = sext i16 [[TMP28]] to i32
3179; CHECK-NEXT:    [[TMP31:%.*]] = xor i32 [[TMP29]], [[TMP30]]
3180; CHECK-NEXT:    [[TMP32:%.*]] = ashr i32 [[TMP31]], 30
3181; CHECK-NEXT:    [[TMP33:%.*]] = or i32 [[TMP32]], 1
3182; CHECK-NEXT:    [[TMP34:%.*]] = sitofp i32 [[TMP29]] to float
3183; CHECK-NEXT:    [[TMP35:%.*]] = sitofp i32 [[TMP30]] to float
3184; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])
3185; CHECK-NEXT:    [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]]
3186; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]])
3187; CHECK-NEXT:    [[TMP39:%.*]] = fneg fast float [[TMP38]]
3188; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]])
3189; CHECK-NEXT:    [[TMP41:%.*]] = fptosi float [[TMP38]] to i32
3190; CHECK-NEXT:    [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]])
3191; CHECK-NEXT:    [[TMP43:%.*]] = call fast float @llvm.fabs.f32(float [[TMP35]])
3192; CHECK-NEXT:    [[TMP44:%.*]] = fcmp fast oge float [[TMP42]], [[TMP43]]
3193; CHECK-NEXT:    [[TMP45:%.*]] = select i1 [[TMP44]], i32 [[TMP33]], i32 0
3194; CHECK-NEXT:    [[TMP46:%.*]] = add i32 [[TMP41]], [[TMP45]]
3195; CHECK-NEXT:    [[TMP47:%.*]] = mul i32 [[TMP46]], [[TMP30]]
3196; CHECK-NEXT:    [[TMP48:%.*]] = sub i32 [[TMP29]], [[TMP47]]
3197; CHECK-NEXT:    [[TMP49:%.*]] = shl i32 [[TMP48]], 16
3198; CHECK-NEXT:    [[TMP50:%.*]] = ashr i32 [[TMP49]], 16
3199; CHECK-NEXT:    [[TMP51:%.*]] = trunc i32 [[TMP50]] to i16
3200; CHECK-NEXT:    [[TMP52:%.*]] = insertelement <4 x i16> [[TMP26]], i16 [[TMP51]], i64 1
3201; CHECK-NEXT:    [[TMP53:%.*]] = extractelement <4 x i16> [[X]], i64 2
3202; CHECK-NEXT:    [[TMP54:%.*]] = extractelement <4 x i16> [[Y]], i64 2
3203; CHECK-NEXT:    [[TMP55:%.*]] = sext i16 [[TMP53]] to i32
3204; CHECK-NEXT:    [[TMP56:%.*]] = sext i16 [[TMP54]] to i32
3205; CHECK-NEXT:    [[TMP57:%.*]] = xor i32 [[TMP55]], [[TMP56]]
3206; CHECK-NEXT:    [[TMP58:%.*]] = ashr i32 [[TMP57]], 30
3207; CHECK-NEXT:    [[TMP59:%.*]] = or i32 [[TMP58]], 1
3208; CHECK-NEXT:    [[TMP60:%.*]] = sitofp i32 [[TMP55]] to float
3209; CHECK-NEXT:    [[TMP61:%.*]] = sitofp i32 [[TMP56]] to float
3210; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP61]])
3211; CHECK-NEXT:    [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]]
3212; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]])
3213; CHECK-NEXT:    [[TMP65:%.*]] = fneg fast float [[TMP64]]
3214; CHECK-NEXT:    [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]])
3215; CHECK-NEXT:    [[TMP67:%.*]] = fptosi float [[TMP64]] to i32
3216; CHECK-NEXT:    [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]])
3217; CHECK-NEXT:    [[TMP69:%.*]] = call fast float @llvm.fabs.f32(float [[TMP61]])
3218; CHECK-NEXT:    [[TMP70:%.*]] = fcmp fast oge float [[TMP68]], [[TMP69]]
3219; CHECK-NEXT:    [[TMP71:%.*]] = select i1 [[TMP70]], i32 [[TMP59]], i32 0
3220; CHECK-NEXT:    [[TMP72:%.*]] = add i32 [[TMP67]], [[TMP71]]
3221; CHECK-NEXT:    [[TMP73:%.*]] = mul i32 [[TMP72]], [[TMP56]]
3222; CHECK-NEXT:    [[TMP74:%.*]] = sub i32 [[TMP55]], [[TMP73]]
3223; CHECK-NEXT:    [[TMP75:%.*]] = shl i32 [[TMP74]], 16
3224; CHECK-NEXT:    [[TMP76:%.*]] = ashr i32 [[TMP75]], 16
3225; CHECK-NEXT:    [[TMP77:%.*]] = trunc i32 [[TMP76]] to i16
3226; CHECK-NEXT:    [[TMP78:%.*]] = insertelement <4 x i16> [[TMP52]], i16 [[TMP77]], i64 2
3227; CHECK-NEXT:    [[TMP79:%.*]] = extractelement <4 x i16> [[X]], i64 3
3228; CHECK-NEXT:    [[TMP80:%.*]] = extractelement <4 x i16> [[Y]], i64 3
3229; CHECK-NEXT:    [[TMP81:%.*]] = sext i16 [[TMP79]] to i32
3230; CHECK-NEXT:    [[TMP82:%.*]] = sext i16 [[TMP80]] to i32
3231; CHECK-NEXT:    [[TMP83:%.*]] = xor i32 [[TMP81]], [[TMP82]]
3232; CHECK-NEXT:    [[TMP84:%.*]] = ashr i32 [[TMP83]], 30
3233; CHECK-NEXT:    [[TMP85:%.*]] = or i32 [[TMP84]], 1
3234; CHECK-NEXT:    [[TMP86:%.*]] = sitofp i32 [[TMP81]] to float
3235; CHECK-NEXT:    [[TMP87:%.*]] = sitofp i32 [[TMP82]] to float
3236; CHECK-NEXT:    [[TMP88:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP87]])
3237; CHECK-NEXT:    [[TMP89:%.*]] = fmul fast float [[TMP86]], [[TMP88]]
3238; CHECK-NEXT:    [[TMP90:%.*]] = call fast float @llvm.trunc.f32(float [[TMP89]])
3239; CHECK-NEXT:    [[TMP91:%.*]] = fneg fast float [[TMP90]]
3240; CHECK-NEXT:    [[TMP92:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP91]], float [[TMP87]], float [[TMP86]])
3241; CHECK-NEXT:    [[TMP93:%.*]] = fptosi float [[TMP90]] to i32
3242; CHECK-NEXT:    [[TMP94:%.*]] = call fast float @llvm.fabs.f32(float [[TMP92]])
3243; CHECK-NEXT:    [[TMP95:%.*]] = call fast float @llvm.fabs.f32(float [[TMP87]])
3244; CHECK-NEXT:    [[TMP96:%.*]] = fcmp fast oge float [[TMP94]], [[TMP95]]
3245; CHECK-NEXT:    [[TMP97:%.*]] = select i1 [[TMP96]], i32 [[TMP85]], i32 0
3246; CHECK-NEXT:    [[TMP98:%.*]] = add i32 [[TMP93]], [[TMP97]]
3247; CHECK-NEXT:    [[TMP99:%.*]] = mul i32 [[TMP98]], [[TMP82]]
3248; CHECK-NEXT:    [[TMP100:%.*]] = sub i32 [[TMP81]], [[TMP99]]
3249; CHECK-NEXT:    [[TMP101:%.*]] = shl i32 [[TMP100]], 16
3250; CHECK-NEXT:    [[TMP102:%.*]] = ashr i32 [[TMP101]], 16
3251; CHECK-NEXT:    [[TMP103:%.*]] = trunc i32 [[TMP102]] to i16
3252; CHECK-NEXT:    [[TMP104:%.*]] = insertelement <4 x i16> [[TMP78]], i16 [[TMP103]], i64 3
3253; CHECK-NEXT:    store <4 x i16> [[TMP104]], <4 x i16> addrspace(1)* [[OUT:%.*]], align 8
3254; CHECK-NEXT:    ret void
3255;
3256; GFX6-LABEL: srem_v4i16:
3257; GFX6:       ; %bb.0:
3258; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
3259; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xb
3260; GFX6-NEXT:    s_mov_b32 s7, 0xf000
3261; GFX6-NEXT:    s_mov_b32 s6, -1
3262; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
3263; GFX6-NEXT:    s_sext_i32_i16 s8, s2
3264; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s8
3265; GFX6-NEXT:    s_sext_i32_i16 s9, s0
3266; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s9
3267; GFX6-NEXT:    s_xor_b32 s8, s9, s8
3268; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
3269; GFX6-NEXT:    s_ashr_i32 s8, s8, 30
3270; GFX6-NEXT:    s_or_b32 s8, s8, 1
3271; GFX6-NEXT:    v_mov_b32_e32 v3, s8
3272; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
3273; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
3274; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
3275; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
3276; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
3277; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
3278; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
3279; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
3280; GFX6-NEXT:    s_ashr_i32 s2, s2, 16
3281; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s2
3282; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
3283; GFX6-NEXT:    s_ashr_i32 s0, s0, 16
3284; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s0
3285; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v1
3286; GFX6-NEXT:    s_xor_b32 s8, s0, s2
3287; GFX6-NEXT:    s_ashr_i32 s8, s8, 30
3288; GFX6-NEXT:    s_or_b32 s8, s8, 1
3289; GFX6-NEXT:    v_mul_f32_e32 v3, v2, v3
3290; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
3291; GFX6-NEXT:    v_mad_f32 v2, -v3, v1, v2
3292; GFX6-NEXT:    v_cvt_i32_f32_e32 v3, v3
3293; GFX6-NEXT:    v_mov_b32_e32 v4, s8
3294; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
3295; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
3296; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
3297; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s2
3298; GFX6-NEXT:    s_sext_i32_i16 s2, s3
3299; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s2
3300; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s0, v1
3301; GFX6-NEXT:    s_sext_i32_i16 s0, s1
3302; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s0
3303; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
3304; GFX6-NEXT:    s_xor_b32 s0, s0, s2
3305; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
3306; GFX6-NEXT:    s_or_b32 s0, s0, 1
3307; GFX6-NEXT:    v_mul_f32_e32 v4, v1, v4
3308; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
3309; GFX6-NEXT:    v_mad_f32 v1, -v4, v2, v1
3310; GFX6-NEXT:    v_mov_b32_e32 v5, s0
3311; GFX6-NEXT:    s_ashr_i32 s0, s3, 16
3312; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v2|
3313; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v4
3314; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s0
3315; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
3316; GFX6-NEXT:    s_ashr_i32 s2, s1, 16
3317; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
3318; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s2
3319; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v2
3320; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s3
3321; GFX6-NEXT:    s_xor_b32 s3, s2, s0
3322; GFX6-NEXT:    s_ashr_i32 s3, s3, 30
3323; GFX6-NEXT:    v_mul_f32_e32 v5, v4, v5
3324; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
3325; GFX6-NEXT:    v_mad_f32 v4, -v5, v2, v4
3326; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
3327; GFX6-NEXT:    s_or_b32 s3, s3, 1
3328; GFX6-NEXT:    v_mov_b32_e32 v6, s3
3329; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v2|
3330; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v6, vcc
3331; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
3332; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s0
3333; GFX6-NEXT:    s_mov_b32 s0, 0xffff
3334; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v1
3335; GFX6-NEXT:    v_and_b32_e32 v1, s0, v1
3336; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s2, v2
3337; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
3338; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
3339; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
3340; GFX6-NEXT:    v_and_b32_e32 v0, s0, v0
3341; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
3342; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
3343; GFX6-NEXT:    s_endpgm
3344;
3345; GFX9-LABEL: srem_v4i16:
3346; GFX9:       ; %bb.0:
3347; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
3348; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
3349; GFX9-NEXT:    v_mov_b32_e32 v2, 0
3350; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3351; GFX9-NEXT:    s_sext_i32_i16 s0, s6
3352; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s0
3353; GFX9-NEXT:    s_sext_i32_i16 s1, s4
3354; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s1
3355; GFX9-NEXT:    s_xor_b32 s0, s1, s0
3356; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
3357; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3358; GFX9-NEXT:    s_or_b32 s8, s0, 1
3359; GFX9-NEXT:    v_mul_f32_e32 v3, v1, v3
3360; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
3361; GFX9-NEXT:    v_mad_f32 v1, -v3, v0, v1
3362; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
3363; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
3364; GFX9-NEXT:    s_cselect_b32 s0, s8, 0
3365; GFX9-NEXT:    s_ashr_i32 s9, s6, 16
3366; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
3367; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s9
3368; GFX9-NEXT:    s_ashr_i32 s8, s4, 16
3369; GFX9-NEXT:    v_add_u32_e32 v1, s0, v3
3370; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s8
3371; GFX9-NEXT:    v_rcp_iflag_f32_e32 v4, v0
3372; GFX9-NEXT:    s_xor_b32 s0, s8, s9
3373; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3374; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s6
3375; GFX9-NEXT:    v_mul_f32_e32 v4, v3, v4
3376; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
3377; GFX9-NEXT:    v_mad_f32 v3, -v4, v0, v3
3378; GFX9-NEXT:    v_cvt_i32_f32_e32 v4, v4
3379; GFX9-NEXT:    s_or_b32 s6, s0, 1
3380; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v3|, |v0|
3381; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
3382; GFX9-NEXT:    s_cselect_b32 s0, s6, 0
3383; GFX9-NEXT:    v_add_u32_e32 v0, s0, v4
3384; GFX9-NEXT:    s_sext_i32_i16 s0, s7
3385; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s0
3386; GFX9-NEXT:    s_sext_i32_i16 s1, s5
3387; GFX9-NEXT:    v_cvt_f32_i32_e32 v4, s1
3388; GFX9-NEXT:    s_xor_b32 s0, s1, s0
3389; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v3
3390; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3391; GFX9-NEXT:    s_or_b32 s6, s0, 1
3392; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s9
3393; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
3394; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
3395; GFX9-NEXT:    v_mad_f32 v4, -v5, v3, v4
3396; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v4|, |v3|
3397; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
3398; GFX9-NEXT:    v_cvt_i32_f32_e32 v5, v5
3399; GFX9-NEXT:    s_cselect_b32 s0, s6, 0
3400; GFX9-NEXT:    s_ashr_i32 s6, s7, 16
3401; GFX9-NEXT:    v_cvt_f32_i32_e32 v4, s6
3402; GFX9-NEXT:    v_add_u32_e32 v3, s0, v5
3403; GFX9-NEXT:    v_mul_lo_u32 v3, v3, s7
3404; GFX9-NEXT:    s_ashr_i32 s7, s5, 16
3405; GFX9-NEXT:    v_cvt_f32_i32_e32 v5, s7
3406; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v4
3407; GFX9-NEXT:    s_xor_b32 s0, s7, s6
3408; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3409; GFX9-NEXT:    s_or_b32 s9, s0, 1
3410; GFX9-NEXT:    v_mul_f32_e32 v6, v5, v6
3411; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
3412; GFX9-NEXT:    v_mad_f32 v5, -v6, v4, v5
3413; GFX9-NEXT:    v_cvt_i32_f32_e32 v6, v6
3414; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v5|, |v4|
3415; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
3416; GFX9-NEXT:    s_cselect_b32 s0, s9, 0
3417; GFX9-NEXT:    v_add_u32_e32 v4, s0, v6
3418; GFX9-NEXT:    v_mul_lo_u32 v4, v4, s6
3419; GFX9-NEXT:    v_sub_u32_e32 v5, s4, v1
3420; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v3
3421; GFX9-NEXT:    v_sub_u32_e32 v0, s8, v0
3422; GFX9-NEXT:    v_sub_u32_e32 v3, s7, v4
3423; GFX9-NEXT:    v_mov_b32_e32 v4, 0xffff
3424; GFX9-NEXT:    v_and_b32_e32 v1, v4, v1
3425; GFX9-NEXT:    v_lshl_or_b32 v1, v3, 16, v1
3426; GFX9-NEXT:    v_and_b32_e32 v3, v4, v5
3427; GFX9-NEXT:    v_lshl_or_b32 v0, v0, 16, v3
3428; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
3429; GFX9-NEXT:    s_endpgm
3430  %r = srem <4 x i16> %x, %y
3431  store <4 x i16> %r, <4 x i16> addrspace(1)* %out
3432  ret void
3433}
3434
3435define amdgpu_kernel void @udiv_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) {
3436; CHECK-LABEL: @udiv_i3(
3437; CHECK-NEXT:    [[TMP1:%.*]] = zext i3 [[X:%.*]] to i32
3438; CHECK-NEXT:    [[TMP2:%.*]] = zext i3 [[Y:%.*]] to i32
3439; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
3440; CHECK-NEXT:    [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
3441; CHECK-NEXT:    [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
3442; CHECK-NEXT:    [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
3443; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
3444; CHECK-NEXT:    [[TMP8:%.*]] = fneg fast float [[TMP7]]
3445; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
3446; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
3447; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
3448; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
3449; CHECK-NEXT:    [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
3450; CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
3451; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
3452; CHECK-NEXT:    [[TMP16:%.*]] = and i32 [[TMP15]], 7
3453; CHECK-NEXT:    [[TMP17:%.*]] = trunc i32 [[TMP16]] to i3
3454; CHECK-NEXT:    store i3 [[TMP17]], i3 addrspace(1)* [[OUT:%.*]], align 1
3455; CHECK-NEXT:    ret void
3456;
3457; GFX6-LABEL: udiv_i3:
3458; GFX6:       ; %bb.0:
3459; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
3460; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
3461; GFX6-NEXT:    s_mov_b32 s7, 0xf000
3462; GFX6-NEXT:    s_mov_b32 s6, -1
3463; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
3464; GFX6-NEXT:    s_bfe_u32 s1, s0, 0x30008
3465; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v0, s1
3466; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v0
3467; GFX6-NEXT:    s_and_b32 s0, s0, 7
3468; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v2, s0
3469; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1
3470; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
3471; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v1
3472; GFX6-NEXT:    v_mad_f32 v1, -v1, v0, v2
3473; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
3474; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
3475; GFX6-NEXT:    v_and_b32_e32 v0, 7, v0
3476; GFX6-NEXT:    buffer_store_byte v0, off, s[4:7], 0
3477; GFX6-NEXT:    s_endpgm
3478;
3479; GFX9-LABEL: udiv_i3:
3480; GFX9:       ; %bb.0:
3481; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
3482; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
3483; GFX9-NEXT:    v_mov_b32_e32 v2, 0
3484; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3485; GFX9-NEXT:    s_bfe_u32 s0, s4, 0x30008
3486; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, s0
3487; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
3488; GFX9-NEXT:    s_and_b32 s0, s4, 7
3489; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v3, s0
3490; GFX9-NEXT:    v_mul_f32_e32 v1, v3, v1
3491; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
3492; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v1
3493; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v3
3494; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
3495; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v4, vcc
3496; GFX9-NEXT:    v_and_b32_e32 v0, 7, v0
3497; GFX9-NEXT:    global_store_byte v2, v0, s[2:3]
3498; GFX9-NEXT:    s_endpgm
3499  %r = udiv i3 %x, %y
3500  store i3 %r, i3 addrspace(1)* %out
3501  ret void
3502}
3503
3504define amdgpu_kernel void @urem_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) {
3505; CHECK-LABEL: @urem_i3(
3506; CHECK-NEXT:    [[TMP1:%.*]] = zext i3 [[X:%.*]] to i32
3507; CHECK-NEXT:    [[TMP2:%.*]] = zext i3 [[Y:%.*]] to i32
3508; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
3509; CHECK-NEXT:    [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
3510; CHECK-NEXT:    [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
3511; CHECK-NEXT:    [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
3512; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
3513; CHECK-NEXT:    [[TMP8:%.*]] = fneg fast float [[TMP7]]
3514; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
3515; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
3516; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
3517; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
3518; CHECK-NEXT:    [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
3519; CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
3520; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
3521; CHECK-NEXT:    [[TMP16:%.*]] = mul i32 [[TMP15]], [[TMP2]]
3522; CHECK-NEXT:    [[TMP17:%.*]] = sub i32 [[TMP1]], [[TMP16]]
3523; CHECK-NEXT:    [[TMP18:%.*]] = and i32 [[TMP17]], 7
3524; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i3
3525; CHECK-NEXT:    store i3 [[TMP19]], i3 addrspace(1)* [[OUT:%.*]], align 1
3526; CHECK-NEXT:    ret void
3527;
3528; GFX6-LABEL: urem_i3:
3529; GFX6:       ; %bb.0:
3530; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
3531; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
3532; GFX6-NEXT:    s_mov_b32 s7, 0xf000
3533; GFX6-NEXT:    s_mov_b32 s6, -1
3534; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
3535; GFX6-NEXT:    s_bfe_u32 s1, s0, 0x30008
3536; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v0, s1
3537; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v0
3538; GFX6-NEXT:    s_and_b32 s2, s0, 7
3539; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v2, s2
3540; GFX6-NEXT:    s_lshr_b32 s1, s0, 8
3541; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1
3542; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
3543; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v1
3544; GFX6-NEXT:    v_mad_f32 v1, -v1, v0, v2
3545; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
3546; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
3547; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s1
3548; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
3549; GFX6-NEXT:    v_and_b32_e32 v0, 7, v0
3550; GFX6-NEXT:    buffer_store_byte v0, off, s[4:7], 0
3551; GFX6-NEXT:    s_endpgm
3552;
3553; GFX9-LABEL: urem_i3:
3554; GFX9:       ; %bb.0:
3555; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
3556; GFX9-NEXT:    s_nop 0
3557; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
3558; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3559; GFX9-NEXT:    s_bfe_u32 s3, s2, 0x30008
3560; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, s3
3561; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
3562; GFX9-NEXT:    s_and_b32 s4, s2, 7
3563; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v2, s4
3564; GFX9-NEXT:    s_lshr_b32 s3, s2, 8
3565; GFX9-NEXT:    v_mul_f32_e32 v1, v2, v1
3566; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
3567; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v1
3568; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v2
3569; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
3570; GFX9-NEXT:    v_mov_b32_e32 v1, 0
3571; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
3572; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
3573; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
3574; GFX9-NEXT:    v_and_b32_e32 v0, 7, v0
3575; GFX9-NEXT:    global_store_byte v1, v0, s[0:1]
3576; GFX9-NEXT:    s_endpgm
3577  %r = urem i3 %x, %y
3578  store i3 %r, i3 addrspace(1)* %out
3579  ret void
3580}
3581
3582define amdgpu_kernel void @sdiv_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) {
3583; CHECK-LABEL: @sdiv_i3(
3584; CHECK-NEXT:    [[TMP1:%.*]] = sext i3 [[X:%.*]] to i32
3585; CHECK-NEXT:    [[TMP2:%.*]] = sext i3 [[Y:%.*]] to i32
3586; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
3587; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
3588; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP4]], 1
3589; CHECK-NEXT:    [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
3590; CHECK-NEXT:    [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
3591; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
3592; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
3593; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
3594; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
3595; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
3596; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
3597; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
3598; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
3599; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
3600; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
3601; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
3602; CHECK-NEXT:    [[TMP19:%.*]] = shl i32 [[TMP18]], 29
3603; CHECK-NEXT:    [[TMP20:%.*]] = ashr i32 [[TMP19]], 29
3604; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i3
3605; CHECK-NEXT:    store i3 [[TMP21]], i3 addrspace(1)* [[OUT:%.*]], align 1
3606; CHECK-NEXT:    ret void
3607;
3608; GFX6-LABEL: sdiv_i3:
3609; GFX6:       ; %bb.0:
3610; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
3611; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
3612; GFX6-NEXT:    s_mov_b32 s7, 0xf000
3613; GFX6-NEXT:    s_mov_b32 s6, -1
3614; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
3615; GFX6-NEXT:    s_bfe_i32 s1, s0, 0x30008
3616; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s1
3617; GFX6-NEXT:    s_bfe_i32 s0, s0, 0x30000
3618; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s0
3619; GFX6-NEXT:    s_xor_b32 s0, s0, s1
3620; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
3621; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
3622; GFX6-NEXT:    s_or_b32 s0, s0, 1
3623; GFX6-NEXT:    v_mov_b32_e32 v3, s0
3624; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
3625; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
3626; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
3627; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
3628; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
3629; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
3630; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
3631; GFX6-NEXT:    v_and_b32_e32 v0, 7, v0
3632; GFX6-NEXT:    buffer_store_byte v0, off, s[4:7], 0
3633; GFX6-NEXT:    s_endpgm
3634;
3635; GFX9-LABEL: sdiv_i3:
3636; GFX9:       ; %bb.0:
3637; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
3638; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
3639; GFX9-NEXT:    v_mov_b32_e32 v1, 0
3640; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3641; GFX9-NEXT:    s_bfe_i32 s0, s4, 0x30008
3642; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s0
3643; GFX9-NEXT:    s_bfe_i32 s1, s4, 0x30000
3644; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s1
3645; GFX9-NEXT:    s_xor_b32 s0, s1, s0
3646; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
3647; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3648; GFX9-NEXT:    s_or_b32 s4, s0, 1
3649; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
3650; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
3651; GFX9-NEXT:    v_mad_f32 v2, -v3, v0, v2
3652; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
3653; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
3654; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
3655; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
3656; GFX9-NEXT:    v_add_u32_e32 v0, s0, v3
3657; GFX9-NEXT:    v_and_b32_e32 v0, 7, v0
3658; GFX9-NEXT:    global_store_byte v1, v0, s[2:3]
3659; GFX9-NEXT:    s_endpgm
3660  %r = sdiv i3 %x, %y
3661  store i3 %r, i3 addrspace(1)* %out
3662  ret void
3663}
3664
3665define amdgpu_kernel void @srem_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) {
3666; CHECK-LABEL: @srem_i3(
3667; CHECK-NEXT:    [[TMP1:%.*]] = sext i3 [[X:%.*]] to i32
3668; CHECK-NEXT:    [[TMP2:%.*]] = sext i3 [[Y:%.*]] to i32
3669; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
3670; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
3671; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP4]], 1
3672; CHECK-NEXT:    [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
3673; CHECK-NEXT:    [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
3674; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
3675; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
3676; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
3677; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
3678; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
3679; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
3680; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
3681; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
3682; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
3683; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
3684; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
3685; CHECK-NEXT:    [[TMP19:%.*]] = mul i32 [[TMP18]], [[TMP2]]
3686; CHECK-NEXT:    [[TMP20:%.*]] = sub i32 [[TMP1]], [[TMP19]]
3687; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 29
3688; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 29
3689; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i3
3690; CHECK-NEXT:    store i3 [[TMP23]], i3 addrspace(1)* [[OUT:%.*]], align 1
3691; CHECK-NEXT:    ret void
3692;
3693; GFX6-LABEL: srem_i3:
3694; GFX6:       ; %bb.0:
3695; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
3696; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
3697; GFX6-NEXT:    s_mov_b32 s7, 0xf000
3698; GFX6-NEXT:    s_mov_b32 s6, -1
3699; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
3700; GFX6-NEXT:    s_bfe_i32 s1, s0, 0x30008
3701; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s1
3702; GFX6-NEXT:    s_bfe_i32 s3, s0, 0x30000
3703; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s3
3704; GFX6-NEXT:    s_xor_b32 s1, s3, s1
3705; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
3706; GFX6-NEXT:    s_ashr_i32 s1, s1, 30
3707; GFX6-NEXT:    s_or_b32 s1, s1, 1
3708; GFX6-NEXT:    v_mov_b32_e32 v3, s1
3709; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
3710; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
3711; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
3712; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
3713; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
3714; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
3715; GFX6-NEXT:    s_lshr_b32 s2, s0, 8
3716; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
3717; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
3718; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
3719; GFX6-NEXT:    v_and_b32_e32 v0, 7, v0
3720; GFX6-NEXT:    buffer_store_byte v0, off, s[4:7], 0
3721; GFX6-NEXT:    s_endpgm
3722;
3723; GFX9-LABEL: srem_i3:
3724; GFX9:       ; %bb.0:
3725; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
3726; GFX9-NEXT:    s_nop 0
3727; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
3728; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3729; GFX9-NEXT:    s_bfe_i32 s2, s4, 0x30008
3730; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s2
3731; GFX9-NEXT:    s_bfe_i32 s3, s4, 0x30000
3732; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s3
3733; GFX9-NEXT:    s_xor_b32 s2, s3, s2
3734; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
3735; GFX9-NEXT:    s_ashr_i32 s2, s2, 30
3736; GFX9-NEXT:    s_lshr_b32 s5, s4, 8
3737; GFX9-NEXT:    s_or_b32 s6, s2, 1
3738; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
3739; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
3740; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
3741; GFX9-NEXT:    v_cvt_i32_f32_e32 v2, v2
3742; GFX9-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|
3743; GFX9-NEXT:    s_cmp_lg_u64 s[2:3], 0
3744; GFX9-NEXT:    s_cselect_b32 s2, s6, 0
3745; GFX9-NEXT:    v_add_u32_e32 v0, s2, v2
3746; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s5
3747; GFX9-NEXT:    v_mov_b32_e32 v1, 0
3748; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
3749; GFX9-NEXT:    v_and_b32_e32 v0, 7, v0
3750; GFX9-NEXT:    global_store_byte v1, v0, s[0:1]
3751; GFX9-NEXT:    s_endpgm
3752  %r = srem i3 %x, %y
3753  store i3 %r, i3 addrspace(1)* %out
3754  ret void
3755}
3756
3757define amdgpu_kernel void @udiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x, <3 x i16> %y) {
3758; CHECK-LABEL: @udiv_v3i16(
3759; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i16> [[X:%.*]], i64 0
3760; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i16> [[Y:%.*]], i64 0
3761; CHECK-NEXT:    [[TMP3:%.*]] = zext i16 [[TMP1]] to i32
3762; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[TMP2]] to i32
3763; CHECK-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float
3764; CHECK-NEXT:    [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float
3765; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])
3766; CHECK-NEXT:    [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]
3767; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])
3768; CHECK-NEXT:    [[TMP10:%.*]] = fneg fast float [[TMP9]]
3769; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])
3770; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP9]] to i32
3771; CHECK-NEXT:    [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])
3772; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])
3773; CHECK-NEXT:    [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]
3774; CHECK-NEXT:    [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 0
3775; CHECK-NEXT:    [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]
3776; CHECK-NEXT:    [[TMP18:%.*]] = and i32 [[TMP17]], 65535
3777; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i16
3778; CHECK-NEXT:    [[TMP20:%.*]] = insertelement <3 x i16> undef, i16 [[TMP19]], i64 0
3779; CHECK-NEXT:    [[TMP21:%.*]] = extractelement <3 x i16> [[X]], i64 1
3780; CHECK-NEXT:    [[TMP22:%.*]] = extractelement <3 x i16> [[Y]], i64 1
3781; CHECK-NEXT:    [[TMP23:%.*]] = zext i16 [[TMP21]] to i32
3782; CHECK-NEXT:    [[TMP24:%.*]] = zext i16 [[TMP22]] to i32
3783; CHECK-NEXT:    [[TMP25:%.*]] = uitofp i32 [[TMP23]] to float
3784; CHECK-NEXT:    [[TMP26:%.*]] = uitofp i32 [[TMP24]] to float
3785; CHECK-NEXT:    [[TMP27:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP26]])
3786; CHECK-NEXT:    [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]]
3787; CHECK-NEXT:    [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]])
3788; CHECK-NEXT:    [[TMP30:%.*]] = fneg fast float [[TMP29]]
3789; CHECK-NEXT:    [[TMP31:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP30]], float [[TMP26]], float [[TMP25]])
3790; CHECK-NEXT:    [[TMP32:%.*]] = fptoui float [[TMP29]] to i32
3791; CHECK-NEXT:    [[TMP33:%.*]] = call fast float @llvm.fabs.f32(float [[TMP31]])
3792; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.fabs.f32(float [[TMP26]])
3793; CHECK-NEXT:    [[TMP35:%.*]] = fcmp fast oge float [[TMP33]], [[TMP34]]
3794; CHECK-NEXT:    [[TMP36:%.*]] = select i1 [[TMP35]], i32 1, i32 0
3795; CHECK-NEXT:    [[TMP37:%.*]] = add i32 [[TMP32]], [[TMP36]]
3796; CHECK-NEXT:    [[TMP38:%.*]] = and i32 [[TMP37]], 65535
3797; CHECK-NEXT:    [[TMP39:%.*]] = trunc i32 [[TMP38]] to i16
3798; CHECK-NEXT:    [[TMP40:%.*]] = insertelement <3 x i16> [[TMP20]], i16 [[TMP39]], i64 1
3799; CHECK-NEXT:    [[TMP41:%.*]] = extractelement <3 x i16> [[X]], i64 2
3800; CHECK-NEXT:    [[TMP42:%.*]] = extractelement <3 x i16> [[Y]], i64 2
3801; CHECK-NEXT:    [[TMP43:%.*]] = zext i16 [[TMP41]] to i32
3802; CHECK-NEXT:    [[TMP44:%.*]] = zext i16 [[TMP42]] to i32
3803; CHECK-NEXT:    [[TMP45:%.*]] = uitofp i32 [[TMP43]] to float
3804; CHECK-NEXT:    [[TMP46:%.*]] = uitofp i32 [[TMP44]] to float
3805; CHECK-NEXT:    [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]])
3806; CHECK-NEXT:    [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]]
3807; CHECK-NEXT:    [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]])
3808; CHECK-NEXT:    [[TMP50:%.*]] = fneg fast float [[TMP49]]
3809; CHECK-NEXT:    [[TMP51:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP50]], float [[TMP46]], float [[TMP45]])
3810; CHECK-NEXT:    [[TMP52:%.*]] = fptoui float [[TMP49]] to i32
3811; CHECK-NEXT:    [[TMP53:%.*]] = call fast float @llvm.fabs.f32(float [[TMP51]])
3812; CHECK-NEXT:    [[TMP54:%.*]] = call fast float @llvm.fabs.f32(float [[TMP46]])
3813; CHECK-NEXT:    [[TMP55:%.*]] = fcmp fast oge float [[TMP53]], [[TMP54]]
3814; CHECK-NEXT:    [[TMP56:%.*]] = select i1 [[TMP55]], i32 1, i32 0
3815; CHECK-NEXT:    [[TMP57:%.*]] = add i32 [[TMP52]], [[TMP56]]
3816; CHECK-NEXT:    [[TMP58:%.*]] = and i32 [[TMP57]], 65535
3817; CHECK-NEXT:    [[TMP59:%.*]] = trunc i32 [[TMP58]] to i16
3818; CHECK-NEXT:    [[TMP60:%.*]] = insertelement <3 x i16> [[TMP40]], i16 [[TMP59]], i64 2
3819; CHECK-NEXT:    store <3 x i16> [[TMP60]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8
3820; CHECK-NEXT:    ret void
3821;
3822; GFX6-LABEL: udiv_v3i16:
3823; GFX6:       ; %bb.0:
3824; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
3825; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
3826; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
3827; GFX6-NEXT:    s_mov_b32 s8, 0xffff
3828; GFX6-NEXT:    s_mov_b32 s7, 0xf000
3829; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
3830; GFX6-NEXT:    s_and_b32 s6, s0, s8
3831; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s6
3832; GFX6-NEXT:    s_and_b32 s6, s2, s8
3833; GFX6-NEXT:    s_lshr_b32 s0, s0, 16
3834; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s0
3835; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s6
3836; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
3837; GFX6-NEXT:    s_lshr_b32 s0, s2, 16
3838; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s0
3839; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
3840; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
3841; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
3842; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
3843; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
3844; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
3845; GFX6-NEXT:    v_mul_f32_e32 v1, v4, v5
3846; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
3847; GFX6-NEXT:    s_and_b32 s0, s1, s8
3848; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
3849; GFX6-NEXT:    v_mad_f32 v2, -v1, v3, v4
3850; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s0
3851; GFX6-NEXT:    s_and_b32 s0, s3, s8
3852; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s0
3853; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
3854; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v4
3855; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
3856; GFX6-NEXT:    s_mov_b32 s6, -1
3857; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
3858; GFX6-NEXT:    v_mul_f32_e32 v2, v5, v6
3859; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
3860; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v2
3861; GFX6-NEXT:    v_mad_f32 v2, -v2, v4, v5
3862; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
3863; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
3864; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
3865; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
3866; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
3867; GFX6-NEXT:    buffer_store_short v2, off, s[4:7], 0 offset:4
3868; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
3869; GFX6-NEXT:    s_endpgm
3870;
3871; GFX9-LABEL: udiv_v3i16:
3872; GFX9:       ; %bb.0:
3873; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
3874; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
3875; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
3876; GFX9-NEXT:    s_mov_b32 s8, 0xffff
3877; GFX9-NEXT:    v_mov_b32_e32 v1, 0
3878; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3879; GFX9-NEXT:    s_and_b32 s0, s6, s8
3880; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s0
3881; GFX9-NEXT:    s_and_b32 s0, s4, s8
3882; GFX9-NEXT:    s_lshr_b32 s1, s6, 16
3883; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, s0
3884; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
3885; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s1
3886; GFX9-NEXT:    s_lshr_b32 s0, s4, 16
3887; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s0
3888; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
3889; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v4
3890; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
3891; GFX9-NEXT:    v_mad_f32 v2, -v3, v0, v2
3892; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
3893; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v0
3894; GFX9-NEXT:    v_mul_f32_e32 v2, v5, v6
3895; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
3896; GFX9-NEXT:    s_and_b32 s0, s7, s8
3897; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
3898; GFX9-NEXT:    v_mad_f32 v3, -v2, v4, v5
3899; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s0
3900; GFX9-NEXT:    s_and_b32 s0, s5, s8
3901; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
3902; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
3903; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v5
3904; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v4
3905; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v0
3906; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
3907; GFX9-NEXT:    v_mul_f32_e32 v3, v6, v7
3908; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
3909; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v3
3910; GFX9-NEXT:    v_mad_f32 v3, -v3, v5, v6
3911; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v5
3912; GFX9-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
3913; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
3914; GFX9-NEXT:    global_store_short v1, v3, s[2:3] offset:4
3915; GFX9-NEXT:    global_store_dword v1, v0, s[2:3]
3916; GFX9-NEXT:    s_endpgm
3917  %r = udiv <3 x i16> %x, %y
3918  store <3 x i16> %r, <3 x i16> addrspace(1)* %out
3919  ret void
3920}
3921
3922define amdgpu_kernel void @urem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x, <3 x i16> %y) {
3923; CHECK-LABEL: @urem_v3i16(
3924; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i16> [[X:%.*]], i64 0
3925; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i16> [[Y:%.*]], i64 0
3926; CHECK-NEXT:    [[TMP3:%.*]] = zext i16 [[TMP1]] to i32
3927; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[TMP2]] to i32
3928; CHECK-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float
3929; CHECK-NEXT:    [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float
3930; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])
3931; CHECK-NEXT:    [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]
3932; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])
3933; CHECK-NEXT:    [[TMP10:%.*]] = fneg fast float [[TMP9]]
3934; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])
3935; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP9]] to i32
3936; CHECK-NEXT:    [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])
3937; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])
3938; CHECK-NEXT:    [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]
3939; CHECK-NEXT:    [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 0
3940; CHECK-NEXT:    [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]
3941; CHECK-NEXT:    [[TMP18:%.*]] = mul i32 [[TMP17]], [[TMP4]]
3942; CHECK-NEXT:    [[TMP19:%.*]] = sub i32 [[TMP3]], [[TMP18]]
3943; CHECK-NEXT:    [[TMP20:%.*]] = and i32 [[TMP19]], 65535
3944; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i16
3945; CHECK-NEXT:    [[TMP22:%.*]] = insertelement <3 x i16> undef, i16 [[TMP21]], i64 0
3946; CHECK-NEXT:    [[TMP23:%.*]] = extractelement <3 x i16> [[X]], i64 1
3947; CHECK-NEXT:    [[TMP24:%.*]] = extractelement <3 x i16> [[Y]], i64 1
3948; CHECK-NEXT:    [[TMP25:%.*]] = zext i16 [[TMP23]] to i32
3949; CHECK-NEXT:    [[TMP26:%.*]] = zext i16 [[TMP24]] to i32
3950; CHECK-NEXT:    [[TMP27:%.*]] = uitofp i32 [[TMP25]] to float
3951; CHECK-NEXT:    [[TMP28:%.*]] = uitofp i32 [[TMP26]] to float
3952; CHECK-NEXT:    [[TMP29:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP28]])
3953; CHECK-NEXT:    [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]]
3954; CHECK-NEXT:    [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]])
3955; CHECK-NEXT:    [[TMP32:%.*]] = fneg fast float [[TMP31]]
3956; CHECK-NEXT:    [[TMP33:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP32]], float [[TMP28]], float [[TMP27]])
3957; CHECK-NEXT:    [[TMP34:%.*]] = fptoui float [[TMP31]] to i32
3958; CHECK-NEXT:    [[TMP35:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
3959; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.fabs.f32(float [[TMP28]])
3960; CHECK-NEXT:    [[TMP37:%.*]] = fcmp fast oge float [[TMP35]], [[TMP36]]
3961; CHECK-NEXT:    [[TMP38:%.*]] = select i1 [[TMP37]], i32 1, i32 0
3962; CHECK-NEXT:    [[TMP39:%.*]] = add i32 [[TMP34]], [[TMP38]]
3963; CHECK-NEXT:    [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP26]]
3964; CHECK-NEXT:    [[TMP41:%.*]] = sub i32 [[TMP25]], [[TMP40]]
3965; CHECK-NEXT:    [[TMP42:%.*]] = and i32 [[TMP41]], 65535
3966; CHECK-NEXT:    [[TMP43:%.*]] = trunc i32 [[TMP42]] to i16
3967; CHECK-NEXT:    [[TMP44:%.*]] = insertelement <3 x i16> [[TMP22]], i16 [[TMP43]], i64 1
3968; CHECK-NEXT:    [[TMP45:%.*]] = extractelement <3 x i16> [[X]], i64 2
3969; CHECK-NEXT:    [[TMP46:%.*]] = extractelement <3 x i16> [[Y]], i64 2
3970; CHECK-NEXT:    [[TMP47:%.*]] = zext i16 [[TMP45]] to i32
3971; CHECK-NEXT:    [[TMP48:%.*]] = zext i16 [[TMP46]] to i32
3972; CHECK-NEXT:    [[TMP49:%.*]] = uitofp i32 [[TMP47]] to float
3973; CHECK-NEXT:    [[TMP50:%.*]] = uitofp i32 [[TMP48]] to float
3974; CHECK-NEXT:    [[TMP51:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP50]])
3975; CHECK-NEXT:    [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]]
3976; CHECK-NEXT:    [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]])
3977; CHECK-NEXT:    [[TMP54:%.*]] = fneg fast float [[TMP53]]
3978; CHECK-NEXT:    [[TMP55:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP54]], float [[TMP50]], float [[TMP49]])
3979; CHECK-NEXT:    [[TMP56:%.*]] = fptoui float [[TMP53]] to i32
3980; CHECK-NEXT:    [[TMP57:%.*]] = call fast float @llvm.fabs.f32(float [[TMP55]])
3981; CHECK-NEXT:    [[TMP58:%.*]] = call fast float @llvm.fabs.f32(float [[TMP50]])
3982; CHECK-NEXT:    [[TMP59:%.*]] = fcmp fast oge float [[TMP57]], [[TMP58]]
3983; CHECK-NEXT:    [[TMP60:%.*]] = select i1 [[TMP59]], i32 1, i32 0
3984; CHECK-NEXT:    [[TMP61:%.*]] = add i32 [[TMP56]], [[TMP60]]
3985; CHECK-NEXT:    [[TMP62:%.*]] = mul i32 [[TMP61]], [[TMP48]]
3986; CHECK-NEXT:    [[TMP63:%.*]] = sub i32 [[TMP47]], [[TMP62]]
3987; CHECK-NEXT:    [[TMP64:%.*]] = and i32 [[TMP63]], 65535
3988; CHECK-NEXT:    [[TMP65:%.*]] = trunc i32 [[TMP64]] to i16
3989; CHECK-NEXT:    [[TMP66:%.*]] = insertelement <3 x i16> [[TMP44]], i16 [[TMP65]], i64 2
3990; CHECK-NEXT:    store <3 x i16> [[TMP66]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8
3991; CHECK-NEXT:    ret void
3992;
3993; GFX6-LABEL: urem_v3i16:
3994; GFX6:       ; %bb.0:
3995; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
3996; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
3997; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
3998; GFX6-NEXT:    s_mov_b32 s8, 0xffff
3999; GFX6-NEXT:    s_mov_b32 s7, 0xf000
4000; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
4001; GFX6-NEXT:    v_mov_b32_e32 v1, s2
4002; GFX6-NEXT:    s_and_b32 s6, s0, s8
4003; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s6
4004; GFX6-NEXT:    s_and_b32 s6, s2, s8
4005; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s6
4006; GFX6-NEXT:    v_mov_b32_e32 v4, s0
4007; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v0
4008; GFX6-NEXT:    v_alignbit_b32 v4, s1, v4, 16
4009; GFX6-NEXT:    v_and_b32_e32 v5, s8, v4
4010; GFX6-NEXT:    v_alignbit_b32 v1, s3, v1, 16
4011; GFX6-NEXT:    v_mul_f32_e32 v3, v2, v3
4012; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
4013; GFX6-NEXT:    v_mad_f32 v2, -v3, v0, v2
4014; GFX6-NEXT:    v_cvt_u32_f32_e32 v6, v3
4015; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v0
4016; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, v5
4017; GFX6-NEXT:    v_and_b32_e32 v3, s8, v1
4018; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v6, vcc
4019; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s0
4020; GFX6-NEXT:    s_and_b32 s0, s1, s8
4021; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, v3
4022; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v2
4023; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s0
4024; GFX6-NEXT:    s_and_b32 s0, s3, s8
4025; GFX6-NEXT:    v_cvt_f32_u32_e32 v7, s0
4026; GFX6-NEXT:    v_mul_f32_e32 v5, v3, v5
4027; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
4028; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v6
4029; GFX6-NEXT:    v_mad_f32 v3, -v5, v2, v3
4030; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v5
4031; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
4032; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v2
4033; GFX6-NEXT:    v_mul_f32_e32 v3, v7, v8
4034; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
4035; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
4036; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v4
4037; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v3
4038; GFX6-NEXT:    v_mad_f32 v3, -v3, v6, v7
4039; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v6
4040; GFX6-NEXT:    s_mov_b32 s6, -1
4041; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
4042; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s1
4043; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v2
4044; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
4045; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
4046; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s3, v3
4047; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
4048; GFX6-NEXT:    buffer_store_short v2, off, s[4:7], 0 offset:4
4049; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
4050; GFX6-NEXT:    s_endpgm
4051;
4052; GFX9-LABEL: urem_v3i16:
4053; GFX9:       ; %bb.0:
4054; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
4055; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
4056; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
4057; GFX9-NEXT:    s_mov_b32 s8, 0xffff
4058; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
4059; GFX9-NEXT:    s_and_b32 s0, s4, s8
4060; GFX9-NEXT:    s_and_b32 s1, s6, s8
4061; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s1
4062; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s0
4063; GFX9-NEXT:    s_lshr_b32 s6, s6, 16
4064; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, s6
4065; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
4066; GFX9-NEXT:    s_lshr_b32 s4, s4, 16
4067; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s4
4068; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v2
4069; GFX9-NEXT:    v_mul_f32_e32 v3, v1, v3
4070; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
4071; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v3
4072; GFX9-NEXT:    v_mad_f32 v1, -v3, v0, v1
4073; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
4074; GFX9-NEXT:    v_mul_f32_e32 v1, v4, v5
4075; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v6, vcc
4076; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s1
4077; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
4078; GFX9-NEXT:    s_and_b32 s1, s7, s8
4079; GFX9-NEXT:    v_mad_f32 v3, -v1, v2, v4
4080; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s1
4081; GFX9-NEXT:    s_and_b32 s5, s5, s8
4082; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s5
4083; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
4084; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v4
4085; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v2
4086; GFX9-NEXT:    v_sub_u32_e32 v0, s0, v0
4087; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
4088; GFX9-NEXT:    v_mul_f32_e32 v2, v5, v6
4089; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
4090; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v2
4091; GFX9-NEXT:    v_mad_f32 v2, -v2, v4, v5
4092; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
4093; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s6
4094; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v3, vcc
4095; GFX9-NEXT:    v_mul_lo_u32 v2, v2, s1
4096; GFX9-NEXT:    v_mov_b32_e32 v3, 0
4097; GFX9-NEXT:    v_sub_u32_e32 v1, s4, v1
4098; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v0
4099; GFX9-NEXT:    v_sub_u32_e32 v2, s5, v2
4100; GFX9-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
4101; GFX9-NEXT:    global_store_short v3, v2, s[2:3] offset:4
4102; GFX9-NEXT:    global_store_dword v3, v0, s[2:3]
4103; GFX9-NEXT:    s_endpgm
4104  %r = urem <3 x i16> %x, %y
4105  store <3 x i16> %r, <3 x i16> addrspace(1)* %out
4106  ret void
4107}
4108
4109define amdgpu_kernel void @sdiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x, <3 x i16> %y) {
4110; CHECK-LABEL: @sdiv_v3i16(
4111; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i16> [[X:%.*]], i64 0
4112; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i16> [[Y:%.*]], i64 0
4113; CHECK-NEXT:    [[TMP3:%.*]] = sext i16 [[TMP1]] to i32
4114; CHECK-NEXT:    [[TMP4:%.*]] = sext i16 [[TMP2]] to i32
4115; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
4116; CHECK-NEXT:    [[TMP6:%.*]] = ashr i32 [[TMP5]], 30
4117; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], 1
4118; CHECK-NEXT:    [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float
4119; CHECK-NEXT:    [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float
4120; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
4121; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]
4122; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])
4123; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
4124; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
4125; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
4126; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
4127; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
4128; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
4129; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
4130; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
4131; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 16
4132; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 16
4133; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i16
4134; CHECK-NEXT:    [[TMP24:%.*]] = insertelement <3 x i16> undef, i16 [[TMP23]], i64 0
4135; CHECK-NEXT:    [[TMP25:%.*]] = extractelement <3 x i16> [[X]], i64 1
4136; CHECK-NEXT:    [[TMP26:%.*]] = extractelement <3 x i16> [[Y]], i64 1
4137; CHECK-NEXT:    [[TMP27:%.*]] = sext i16 [[TMP25]] to i32
4138; CHECK-NEXT:    [[TMP28:%.*]] = sext i16 [[TMP26]] to i32
4139; CHECK-NEXT:    [[TMP29:%.*]] = xor i32 [[TMP27]], [[TMP28]]
4140; CHECK-NEXT:    [[TMP30:%.*]] = ashr i32 [[TMP29]], 30
4141; CHECK-NEXT:    [[TMP31:%.*]] = or i32 [[TMP30]], 1
4142; CHECK-NEXT:    [[TMP32:%.*]] = sitofp i32 [[TMP27]] to float
4143; CHECK-NEXT:    [[TMP33:%.*]] = sitofp i32 [[TMP28]] to float
4144; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])
4145; CHECK-NEXT:    [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]]
4146; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]])
4147; CHECK-NEXT:    [[TMP37:%.*]] = fneg fast float [[TMP36]]
4148; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]])
4149; CHECK-NEXT:    [[TMP39:%.*]] = fptosi float [[TMP36]] to i32
4150; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]])
4151; CHECK-NEXT:    [[TMP41:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
4152; CHECK-NEXT:    [[TMP42:%.*]] = fcmp fast oge float [[TMP40]], [[TMP41]]
4153; CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP31]], i32 0
4154; CHECK-NEXT:    [[TMP44:%.*]] = add i32 [[TMP39]], [[TMP43]]
4155; CHECK-NEXT:    [[TMP45:%.*]] = shl i32 [[TMP44]], 16
4156; CHECK-NEXT:    [[TMP46:%.*]] = ashr i32 [[TMP45]], 16
4157; CHECK-NEXT:    [[TMP47:%.*]] = trunc i32 [[TMP46]] to i16
4158; CHECK-NEXT:    [[TMP48:%.*]] = insertelement <3 x i16> [[TMP24]], i16 [[TMP47]], i64 1
4159; CHECK-NEXT:    [[TMP49:%.*]] = extractelement <3 x i16> [[X]], i64 2
4160; CHECK-NEXT:    [[TMP50:%.*]] = extractelement <3 x i16> [[Y]], i64 2
4161; CHECK-NEXT:    [[TMP51:%.*]] = sext i16 [[TMP49]] to i32
4162; CHECK-NEXT:    [[TMP52:%.*]] = sext i16 [[TMP50]] to i32
4163; CHECK-NEXT:    [[TMP53:%.*]] = xor i32 [[TMP51]], [[TMP52]]
4164; CHECK-NEXT:    [[TMP54:%.*]] = ashr i32 [[TMP53]], 30
4165; CHECK-NEXT:    [[TMP55:%.*]] = or i32 [[TMP54]], 1
4166; CHECK-NEXT:    [[TMP56:%.*]] = sitofp i32 [[TMP51]] to float
4167; CHECK-NEXT:    [[TMP57:%.*]] = sitofp i32 [[TMP52]] to float
4168; CHECK-NEXT:    [[TMP58:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP57]])
4169; CHECK-NEXT:    [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]]
4170; CHECK-NEXT:    [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]])
4171; CHECK-NEXT:    [[TMP61:%.*]] = fneg fast float [[TMP60]]
4172; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]])
4173; CHECK-NEXT:    [[TMP63:%.*]] = fptosi float [[TMP60]] to i32
4174; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]])
4175; CHECK-NEXT:    [[TMP65:%.*]] = call fast float @llvm.fabs.f32(float [[TMP57]])
4176; CHECK-NEXT:    [[TMP66:%.*]] = fcmp fast oge float [[TMP64]], [[TMP65]]
4177; CHECK-NEXT:    [[TMP67:%.*]] = select i1 [[TMP66]], i32 [[TMP55]], i32 0
4178; CHECK-NEXT:    [[TMP68:%.*]] = add i32 [[TMP63]], [[TMP67]]
4179; CHECK-NEXT:    [[TMP69:%.*]] = shl i32 [[TMP68]], 16
4180; CHECK-NEXT:    [[TMP70:%.*]] = ashr i32 [[TMP69]], 16
4181; CHECK-NEXT:    [[TMP71:%.*]] = trunc i32 [[TMP70]] to i16
4182; CHECK-NEXT:    [[TMP72:%.*]] = insertelement <3 x i16> [[TMP48]], i16 [[TMP71]], i64 2
4183; CHECK-NEXT:    store <3 x i16> [[TMP72]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8
4184; CHECK-NEXT:    ret void
4185;
4186; GFX6-LABEL: sdiv_v3i16:
4187; GFX6:       ; %bb.0:
4188; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
4189; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
4190; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
4191; GFX6-NEXT:    s_mov_b32 s7, 0xf000
4192; GFX6-NEXT:    s_mov_b32 s6, -1
4193; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
4194; GFX6-NEXT:    s_sext_i32_i16 s9, s2
4195; GFX6-NEXT:    s_sext_i32_i16 s8, s0
4196; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s8
4197; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s9
4198; GFX6-NEXT:    s_xor_b32 s8, s9, s8
4199; GFX6-NEXT:    s_ashr_i32 s0, s0, 16
4200; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
4201; GFX6-NEXT:    s_ashr_i32 s8, s8, 30
4202; GFX6-NEXT:    s_or_b32 s8, s8, 1
4203; GFX6-NEXT:    v_mov_b32_e32 v3, s8
4204; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
4205; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
4206; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
4207; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
4208; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
4209; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s0
4210; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
4211; GFX6-NEXT:    s_ashr_i32 s2, s2, 16
4212; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
4213; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s2
4214; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v1
4215; GFX6-NEXT:    s_xor_b32 s0, s2, s0
4216; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
4217; GFX6-NEXT:    s_or_b32 s0, s0, 1
4218; GFX6-NEXT:    v_mul_f32_e32 v3, v2, v3
4219; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
4220; GFX6-NEXT:    v_mad_f32 v2, -v3, v1, v2
4221; GFX6-NEXT:    v_mov_b32_e32 v4, s0
4222; GFX6-NEXT:    s_sext_i32_i16 s0, s1
4223; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
4224; GFX6-NEXT:    v_cvt_i32_f32_e32 v3, v3
4225; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s0
4226; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
4227; GFX6-NEXT:    s_sext_i32_i16 s1, s3
4228; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
4229; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s1
4230; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
4231; GFX6-NEXT:    s_xor_b32 s0, s1, s0
4232; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
4233; GFX6-NEXT:    s_or_b32 s0, s0, 1
4234; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
4235; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
4236; GFX6-NEXT:    v_mad_f32 v3, -v4, v2, v3
4237; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v4
4238; GFX6-NEXT:    v_mov_b32_e32 v5, s0
4239; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
4240; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
4241; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
4242; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
4243; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0
4244; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
4245; GFX6-NEXT:    buffer_store_short v2, off, s[4:7], 0 offset:4
4246; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
4247; GFX6-NEXT:    s_endpgm
4248;
4249; GFX9-LABEL: sdiv_v3i16:
4250; GFX9:       ; %bb.0:
4251; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
4252; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
4253; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
4254; GFX9-NEXT:    v_mov_b32_e32 v1, 0
4255; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
4256; GFX9-NEXT:    s_sext_i32_i16 s1, s4
4257; GFX9-NEXT:    s_sext_i32_i16 s0, s6
4258; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s0
4259; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s1
4260; GFX9-NEXT:    s_xor_b32 s0, s1, s0
4261; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
4262; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
4263; GFX9-NEXT:    s_or_b32 s8, s0, 1
4264; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
4265; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
4266; GFX9-NEXT:    v_mad_f32 v2, -v3, v0, v2
4267; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
4268; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
4269; GFX9-NEXT:    s_cselect_b32 s0, s8, 0
4270; GFX9-NEXT:    s_ashr_i32 s1, s6, 16
4271; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
4272; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s1
4273; GFX9-NEXT:    s_ashr_i32 s4, s4, 16
4274; GFX9-NEXT:    v_add_u32_e32 v2, s0, v3
4275; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s4
4276; GFX9-NEXT:    v_rcp_iflag_f32_e32 v4, v0
4277; GFX9-NEXT:    s_xor_b32 s0, s4, s1
4278; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
4279; GFX9-NEXT:    s_or_b32 s4, s0, 1
4280; GFX9-NEXT:    v_mul_f32_e32 v4, v3, v4
4281; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
4282; GFX9-NEXT:    v_mad_f32 v3, -v4, v0, v3
4283; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v3|, |v0|
4284; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
4285; GFX9-NEXT:    s_sext_i32_i16 s1, s7
4286; GFX9-NEXT:    v_cvt_i32_f32_e32 v4, v4
4287; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s1
4288; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
4289; GFX9-NEXT:    v_and_b32_e32 v2, 0xffff, v2
4290; GFX9-NEXT:    v_add_u32_e32 v3, s0, v4
4291; GFX9-NEXT:    s_sext_i32_i16 s0, s5
4292; GFX9-NEXT:    v_cvt_f32_i32_e32 v4, s0
4293; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v0
4294; GFX9-NEXT:    s_xor_b32 s0, s0, s1
4295; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
4296; GFX9-NEXT:    s_or_b32 s4, s0, 1
4297; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
4298; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
4299; GFX9-NEXT:    v_mad_f32 v4, -v5, v0, v4
4300; GFX9-NEXT:    v_cvt_i32_f32_e32 v5, v5
4301; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v4|, |v0|
4302; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
4303; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
4304; GFX9-NEXT:    v_add_u32_e32 v0, s0, v5
4305; GFX9-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
4306; GFX9-NEXT:    global_store_short v1, v0, s[2:3] offset:4
4307; GFX9-NEXT:    global_store_dword v1, v2, s[2:3]
4308; GFX9-NEXT:    s_endpgm
4309  %r = sdiv <3 x i16> %x, %y
4310  store <3 x i16> %r, <3 x i16> addrspace(1)* %out
4311  ret void
4312}
4313
4314define amdgpu_kernel void @srem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x, <3 x i16> %y) {
4315; CHECK-LABEL: @srem_v3i16(
4316; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i16> [[X:%.*]], i64 0
4317; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i16> [[Y:%.*]], i64 0
4318; CHECK-NEXT:    [[TMP3:%.*]] = sext i16 [[TMP1]] to i32
4319; CHECK-NEXT:    [[TMP4:%.*]] = sext i16 [[TMP2]] to i32
4320; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
4321; CHECK-NEXT:    [[TMP6:%.*]] = ashr i32 [[TMP5]], 30
4322; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], 1
4323; CHECK-NEXT:    [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float
4324; CHECK-NEXT:    [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float
4325; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
4326; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]
4327; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])
4328; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
4329; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
4330; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
4331; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
4332; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
4333; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
4334; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
4335; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
4336; CHECK-NEXT:    [[TMP21:%.*]] = mul i32 [[TMP20]], [[TMP4]]
4337; CHECK-NEXT:    [[TMP22:%.*]] = sub i32 [[TMP3]], [[TMP21]]
4338; CHECK-NEXT:    [[TMP23:%.*]] = shl i32 [[TMP22]], 16
4339; CHECK-NEXT:    [[TMP24:%.*]] = ashr i32 [[TMP23]], 16
4340; CHECK-NEXT:    [[TMP25:%.*]] = trunc i32 [[TMP24]] to i16
4341; CHECK-NEXT:    [[TMP26:%.*]] = insertelement <3 x i16> undef, i16 [[TMP25]], i64 0
4342; CHECK-NEXT:    [[TMP27:%.*]] = extractelement <3 x i16> [[X]], i64 1
4343; CHECK-NEXT:    [[TMP28:%.*]] = extractelement <3 x i16> [[Y]], i64 1
4344; CHECK-NEXT:    [[TMP29:%.*]] = sext i16 [[TMP27]] to i32
4345; CHECK-NEXT:    [[TMP30:%.*]] = sext i16 [[TMP28]] to i32
4346; CHECK-NEXT:    [[TMP31:%.*]] = xor i32 [[TMP29]], [[TMP30]]
4347; CHECK-NEXT:    [[TMP32:%.*]] = ashr i32 [[TMP31]], 30
4348; CHECK-NEXT:    [[TMP33:%.*]] = or i32 [[TMP32]], 1
4349; CHECK-NEXT:    [[TMP34:%.*]] = sitofp i32 [[TMP29]] to float
4350; CHECK-NEXT:    [[TMP35:%.*]] = sitofp i32 [[TMP30]] to float
4351; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])
4352; CHECK-NEXT:    [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]]
4353; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]])
4354; CHECK-NEXT:    [[TMP39:%.*]] = fneg fast float [[TMP38]]
4355; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]])
4356; CHECK-NEXT:    [[TMP41:%.*]] = fptosi float [[TMP38]] to i32
4357; CHECK-NEXT:    [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]])
4358; CHECK-NEXT:    [[TMP43:%.*]] = call fast float @llvm.fabs.f32(float [[TMP35]])
4359; CHECK-NEXT:    [[TMP44:%.*]] = fcmp fast oge float [[TMP42]], [[TMP43]]
4360; CHECK-NEXT:    [[TMP45:%.*]] = select i1 [[TMP44]], i32 [[TMP33]], i32 0
4361; CHECK-NEXT:    [[TMP46:%.*]] = add i32 [[TMP41]], [[TMP45]]
4362; CHECK-NEXT:    [[TMP47:%.*]] = mul i32 [[TMP46]], [[TMP30]]
4363; CHECK-NEXT:    [[TMP48:%.*]] = sub i32 [[TMP29]], [[TMP47]]
4364; CHECK-NEXT:    [[TMP49:%.*]] = shl i32 [[TMP48]], 16
4365; CHECK-NEXT:    [[TMP50:%.*]] = ashr i32 [[TMP49]], 16
4366; CHECK-NEXT:    [[TMP51:%.*]] = trunc i32 [[TMP50]] to i16
4367; CHECK-NEXT:    [[TMP52:%.*]] = insertelement <3 x i16> [[TMP26]], i16 [[TMP51]], i64 1
4368; CHECK-NEXT:    [[TMP53:%.*]] = extractelement <3 x i16> [[X]], i64 2
4369; CHECK-NEXT:    [[TMP54:%.*]] = extractelement <3 x i16> [[Y]], i64 2
4370; CHECK-NEXT:    [[TMP55:%.*]] = sext i16 [[TMP53]] to i32
4371; CHECK-NEXT:    [[TMP56:%.*]] = sext i16 [[TMP54]] to i32
4372; CHECK-NEXT:    [[TMP57:%.*]] = xor i32 [[TMP55]], [[TMP56]]
4373; CHECK-NEXT:    [[TMP58:%.*]] = ashr i32 [[TMP57]], 30
4374; CHECK-NEXT:    [[TMP59:%.*]] = or i32 [[TMP58]], 1
4375; CHECK-NEXT:    [[TMP60:%.*]] = sitofp i32 [[TMP55]] to float
4376; CHECK-NEXT:    [[TMP61:%.*]] = sitofp i32 [[TMP56]] to float
4377; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP61]])
4378; CHECK-NEXT:    [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]]
4379; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]])
4380; CHECK-NEXT:    [[TMP65:%.*]] = fneg fast float [[TMP64]]
4381; CHECK-NEXT:    [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]])
4382; CHECK-NEXT:    [[TMP67:%.*]] = fptosi float [[TMP64]] to i32
4383; CHECK-NEXT:    [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]])
4384; CHECK-NEXT:    [[TMP69:%.*]] = call fast float @llvm.fabs.f32(float [[TMP61]])
4385; CHECK-NEXT:    [[TMP70:%.*]] = fcmp fast oge float [[TMP68]], [[TMP69]]
4386; CHECK-NEXT:    [[TMP71:%.*]] = select i1 [[TMP70]], i32 [[TMP59]], i32 0
4387; CHECK-NEXT:    [[TMP72:%.*]] = add i32 [[TMP67]], [[TMP71]]
4388; CHECK-NEXT:    [[TMP73:%.*]] = mul i32 [[TMP72]], [[TMP56]]
4389; CHECK-NEXT:    [[TMP74:%.*]] = sub i32 [[TMP55]], [[TMP73]]
4390; CHECK-NEXT:    [[TMP75:%.*]] = shl i32 [[TMP74]], 16
4391; CHECK-NEXT:    [[TMP76:%.*]] = ashr i32 [[TMP75]], 16
4392; CHECK-NEXT:    [[TMP77:%.*]] = trunc i32 [[TMP76]] to i16
4393; CHECK-NEXT:    [[TMP78:%.*]] = insertelement <3 x i16> [[TMP52]], i16 [[TMP77]], i64 2
4394; CHECK-NEXT:    store <3 x i16> [[TMP78]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8
4395; CHECK-NEXT:    ret void
4396;
4397; GFX6-LABEL: srem_v3i16:
4398; GFX6:       ; %bb.0:
4399; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
4400; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
4401; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
4402; GFX6-NEXT:    s_mov_b32 s7, 0xf000
4403; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
4404; GFX6-NEXT:    s_sext_i32_i16 s8, s2
4405; GFX6-NEXT:    s_sext_i32_i16 s6, s0
4406; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s6
4407; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s8
4408; GFX6-NEXT:    s_xor_b32 s6, s8, s6
4409; GFX6-NEXT:    s_ashr_i32 s6, s6, 30
4410; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
4411; GFX6-NEXT:    s_or_b32 s6, s6, 1
4412; GFX6-NEXT:    v_mov_b32_e32 v3, s6
4413; GFX6-NEXT:    s_mov_b32 s6, -1
4414; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
4415; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
4416; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
4417; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
4418; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
4419; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
4420; GFX6-NEXT:    v_mov_b32_e32 v1, s2
4421; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
4422; GFX6-NEXT:    v_mov_b32_e32 v2, s0
4423; GFX6-NEXT:    v_alignbit_b32 v2, s1, v2, 16
4424; GFX6-NEXT:    v_bfe_i32 v3, v2, 0, 16
4425; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, v3
4426; GFX6-NEXT:    v_alignbit_b32 v1, s3, v1, 16
4427; GFX6-NEXT:    v_bfe_i32 v5, v1, 0, 16
4428; GFX6-NEXT:    v_cvt_f32_i32_e32 v6, v5
4429; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v4
4430; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s0
4431; GFX6-NEXT:    v_xor_b32_e32 v3, v5, v3
4432; GFX6-NEXT:    s_sext_i32_i16 s0, s1
4433; GFX6-NEXT:    v_mul_f32_e32 v5, v6, v7
4434; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
4435; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
4436; GFX6-NEXT:    v_mad_f32 v6, -v5, v4, v6
4437; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
4438; GFX6-NEXT:    v_ashrrev_i32_e32 v3, 30, v3
4439; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, |v4|
4440; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s0
4441; GFX6-NEXT:    v_or_b32_e32 v3, 1, v3
4442; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
4443; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
4444; GFX6-NEXT:    s_sext_i32_i16 s2, s3
4445; GFX6-NEXT:    v_mul_lo_u32 v2, v3, v2
4446; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s2
4447; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v4
4448; GFX6-NEXT:    s_xor_b32 s0, s2, s0
4449; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
4450; GFX6-NEXT:    s_or_b32 s0, s0, 1
4451; GFX6-NEXT:    v_mul_f32_e32 v5, v3, v5
4452; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
4453; GFX6-NEXT:    v_mad_f32 v3, -v5, v4, v3
4454; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
4455; GFX6-NEXT:    v_mov_b32_e32 v6, s0
4456; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v4|
4457; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v6, vcc
4458; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
4459; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s1
4460; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v2
4461; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
4462; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0
4463; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s3, v3
4464; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
4465; GFX6-NEXT:    buffer_store_short v2, off, s[4:7], 0 offset:4
4466; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
4467; GFX6-NEXT:    s_endpgm
4468;
4469; GFX9-LABEL: srem_v3i16:
4470; GFX9:       ; %bb.0:
4471; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
4472; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
4473; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x2c
4474; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
4475; GFX9-NEXT:    s_sext_i32_i16 s8, s2
4476; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s8
4477; GFX9-NEXT:    s_sext_i32_i16 s9, s6
4478; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s9
4479; GFX9-NEXT:    s_xor_b32 s0, s9, s8
4480; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
4481; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
4482; GFX9-NEXT:    s_or_b32 s10, s0, 1
4483; GFX9-NEXT:    s_sext_i32_i16 s3, s3
4484; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
4485; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
4486; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
4487; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
4488; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
4489; GFX9-NEXT:    s_cselect_b32 s0, s10, 0
4490; GFX9-NEXT:    s_ashr_i32 s2, s2, 16
4491; GFX9-NEXT:    v_cvt_i32_f32_e32 v2, v2
4492; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s2
4493; GFX9-NEXT:    s_ashr_i32 s6, s6, 16
4494; GFX9-NEXT:    v_add_u32_e32 v1, s0, v2
4495; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s6
4496; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
4497; GFX9-NEXT:    s_xor_b32 s0, s6, s2
4498; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
4499; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s8
4500; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
4501; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
4502; GFX9-NEXT:    v_mad_f32 v2, -v3, v0, v2
4503; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
4504; GFX9-NEXT:    s_or_b32 s8, s0, 1
4505; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
4506; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
4507; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s3
4508; GFX9-NEXT:    s_cselect_b32 s0, s8, 0
4509; GFX9-NEXT:    v_add_u32_e32 v0, s0, v3
4510; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s2
4511; GFX9-NEXT:    s_sext_i32_i16 s2, s7
4512; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s2
4513; GFX9-NEXT:    v_rcp_iflag_f32_e32 v4, v2
4514; GFX9-NEXT:    s_xor_b32 s0, s2, s3
4515; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
4516; GFX9-NEXT:    s_or_b32 s7, s0, 1
4517; GFX9-NEXT:    v_mul_f32_e32 v4, v3, v4
4518; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
4519; GFX9-NEXT:    v_mad_f32 v3, -v4, v2, v3
4520; GFX9-NEXT:    v_cvt_i32_f32_e32 v4, v4
4521; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v3|, |v2|
4522; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
4523; GFX9-NEXT:    s_cselect_b32 s0, s7, 0
4524; GFX9-NEXT:    v_add_u32_e32 v2, s0, v4
4525; GFX9-NEXT:    v_mul_lo_u32 v2, v2, s3
4526; GFX9-NEXT:    v_sub_u32_e32 v1, s9, v1
4527; GFX9-NEXT:    v_mov_b32_e32 v3, 0
4528; GFX9-NEXT:    v_sub_u32_e32 v0, s6, v0
4529; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff, v1
4530; GFX9-NEXT:    v_sub_u32_e32 v2, s2, v2
4531; GFX9-NEXT:    v_lshl_or_b32 v0, v0, 16, v1
4532; GFX9-NEXT:    global_store_short v3, v2, s[4:5] offset:4
4533; GFX9-NEXT:    global_store_dword v3, v0, s[4:5]
4534; GFX9-NEXT:    s_endpgm
4535  %r = srem <3 x i16> %x, %y
4536  store <3 x i16> %r, <3 x i16> addrspace(1)* %out
4537  ret void
4538}
4539
4540define amdgpu_kernel void @udiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x, <3 x i15> %y) {
4541; CHECK-LABEL: @udiv_v3i15(
4542; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i15> [[X:%.*]], i64 0
4543; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i15> [[Y:%.*]], i64 0
4544; CHECK-NEXT:    [[TMP3:%.*]] = zext i15 [[TMP1]] to i32
4545; CHECK-NEXT:    [[TMP4:%.*]] = zext i15 [[TMP2]] to i32
4546; CHECK-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float
4547; CHECK-NEXT:    [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float
4548; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])
4549; CHECK-NEXT:    [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]
4550; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])
4551; CHECK-NEXT:    [[TMP10:%.*]] = fneg fast float [[TMP9]]
4552; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])
4553; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP9]] to i32
4554; CHECK-NEXT:    [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])
4555; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])
4556; CHECK-NEXT:    [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]
4557; CHECK-NEXT:    [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 0
4558; CHECK-NEXT:    [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]
4559; CHECK-NEXT:    [[TMP18:%.*]] = and i32 [[TMP17]], 32767
4560; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i15
4561; CHECK-NEXT:    [[TMP20:%.*]] = insertelement <3 x i15> undef, i15 [[TMP19]], i64 0
4562; CHECK-NEXT:    [[TMP21:%.*]] = extractelement <3 x i15> [[X]], i64 1
4563; CHECK-NEXT:    [[TMP22:%.*]] = extractelement <3 x i15> [[Y]], i64 1
4564; CHECK-NEXT:    [[TMP23:%.*]] = zext i15 [[TMP21]] to i32
4565; CHECK-NEXT:    [[TMP24:%.*]] = zext i15 [[TMP22]] to i32
4566; CHECK-NEXT:    [[TMP25:%.*]] = uitofp i32 [[TMP23]] to float
4567; CHECK-NEXT:    [[TMP26:%.*]] = uitofp i32 [[TMP24]] to float
4568; CHECK-NEXT:    [[TMP27:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP26]])
4569; CHECK-NEXT:    [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]]
4570; CHECK-NEXT:    [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]])
4571; CHECK-NEXT:    [[TMP30:%.*]] = fneg fast float [[TMP29]]
4572; CHECK-NEXT:    [[TMP31:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP30]], float [[TMP26]], float [[TMP25]])
4573; CHECK-NEXT:    [[TMP32:%.*]] = fptoui float [[TMP29]] to i32
4574; CHECK-NEXT:    [[TMP33:%.*]] = call fast float @llvm.fabs.f32(float [[TMP31]])
4575; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.fabs.f32(float [[TMP26]])
4576; CHECK-NEXT:    [[TMP35:%.*]] = fcmp fast oge float [[TMP33]], [[TMP34]]
4577; CHECK-NEXT:    [[TMP36:%.*]] = select i1 [[TMP35]], i32 1, i32 0
4578; CHECK-NEXT:    [[TMP37:%.*]] = add i32 [[TMP32]], [[TMP36]]
4579; CHECK-NEXT:    [[TMP38:%.*]] = and i32 [[TMP37]], 32767
4580; CHECK-NEXT:    [[TMP39:%.*]] = trunc i32 [[TMP38]] to i15
4581; CHECK-NEXT:    [[TMP40:%.*]] = insertelement <3 x i15> [[TMP20]], i15 [[TMP39]], i64 1
4582; CHECK-NEXT:    [[TMP41:%.*]] = extractelement <3 x i15> [[X]], i64 2
4583; CHECK-NEXT:    [[TMP42:%.*]] = extractelement <3 x i15> [[Y]], i64 2
4584; CHECK-NEXT:    [[TMP43:%.*]] = zext i15 [[TMP41]] to i32
4585; CHECK-NEXT:    [[TMP44:%.*]] = zext i15 [[TMP42]] to i32
4586; CHECK-NEXT:    [[TMP45:%.*]] = uitofp i32 [[TMP43]] to float
4587; CHECK-NEXT:    [[TMP46:%.*]] = uitofp i32 [[TMP44]] to float
4588; CHECK-NEXT:    [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]])
4589; CHECK-NEXT:    [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]]
4590; CHECK-NEXT:    [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]])
4591; CHECK-NEXT:    [[TMP50:%.*]] = fneg fast float [[TMP49]]
4592; CHECK-NEXT:    [[TMP51:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP50]], float [[TMP46]], float [[TMP45]])
4593; CHECK-NEXT:    [[TMP52:%.*]] = fptoui float [[TMP49]] to i32
4594; CHECK-NEXT:    [[TMP53:%.*]] = call fast float @llvm.fabs.f32(float [[TMP51]])
4595; CHECK-NEXT:    [[TMP54:%.*]] = call fast float @llvm.fabs.f32(float [[TMP46]])
4596; CHECK-NEXT:    [[TMP55:%.*]] = fcmp fast oge float [[TMP53]], [[TMP54]]
4597; CHECK-NEXT:    [[TMP56:%.*]] = select i1 [[TMP55]], i32 1, i32 0
4598; CHECK-NEXT:    [[TMP57:%.*]] = add i32 [[TMP52]], [[TMP56]]
4599; CHECK-NEXT:    [[TMP58:%.*]] = and i32 [[TMP57]], 32767
4600; CHECK-NEXT:    [[TMP59:%.*]] = trunc i32 [[TMP58]] to i15
4601; CHECK-NEXT:    [[TMP60:%.*]] = insertelement <3 x i15> [[TMP40]], i15 [[TMP59]], i64 2
4602; CHECK-NEXT:    store <3 x i15> [[TMP60]], <3 x i15> addrspace(1)* [[OUT:%.*]], align 8
4603; CHECK-NEXT:    ret void
4604;
4605; GFX6-LABEL: udiv_v3i15:
4606; GFX6:       ; %bb.0:
4607; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
4608; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
4609; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
4610; GFX6-NEXT:    s_mov_b32 s7, 0xf000
4611; GFX6-NEXT:    s_mov_b32 s6, -1
4612; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
4613; GFX6-NEXT:    v_mov_b32_e32 v0, s2
4614; GFX6-NEXT:    v_alignbit_b32 v0, s3, v0, 30
4615; GFX6-NEXT:    s_movk_i32 s3, 0x7fff
4616; GFX6-NEXT:    s_and_b32 s9, s0, s3
4617; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
4618; GFX6-NEXT:    v_mov_b32_e32 v2, s0
4619; GFX6-NEXT:    s_and_b32 s8, s2, s3
4620; GFX6-NEXT:    s_bfe_u32 s0, s0, 0xf000f
4621; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s0
4622; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s8
4623; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v1
4624; GFX6-NEXT:    s_bfe_u32 s2, s2, 0xf000f
4625; GFX6-NEXT:    v_alignbit_b32 v2, s1, v2, 30
4626; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s2
4627; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
4628; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v5
4629; GFX6-NEXT:    v_and_b32_e32 v2, s3, v2
4630; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
4631; GFX6-NEXT:    v_mad_f32 v3, -v4, v1, v3
4632; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
4633; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, v2
4634; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v1
4635; GFX6-NEXT:    v_mul_f32_e32 v1, v6, v7
4636; GFX6-NEXT:    v_and_b32_e32 v0, s3, v0
4637; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
4638; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
4639; GFX6-NEXT:    v_mad_f32 v4, -v1, v5, v6
4640; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
4641; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, v0
4642; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v2
4643; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v5
4644; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
4645; GFX6-NEXT:    v_mul_f32_e32 v1, v0, v6
4646; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
4647; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v1
4648; GFX6-NEXT:    v_mad_f32 v0, -v1, v2, v0
4649; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, v2
4650; GFX6-NEXT:    v_and_b32_e32 v2, s3, v3
4651; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
4652; GFX6-NEXT:    v_and_b32_e32 v3, s3, v4
4653; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
4654; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 30
4655; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
4656; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
4657; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
4658; GFX6-NEXT:    s_waitcnt expcnt(0)
4659; GFX6-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
4660; GFX6-NEXT:    buffer_store_short v0, off, s[4:7], 0 offset:4
4661; GFX6-NEXT:    s_endpgm
4662;
4663; GFX9-LABEL: udiv_v3i15:
4664; GFX9:       ; %bb.0:
4665; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
4666; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
4667; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
4668; GFX9-NEXT:    s_movk_i32 s8, 0x7fff
4669; GFX9-NEXT:    v_mov_b32_e32 v2, 0
4670; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
4671; GFX9-NEXT:    s_and_b32 s0, s4, s8
4672; GFX9-NEXT:    s_and_b32 s1, s6, s8
4673; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s1
4674; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s0
4675; GFX9-NEXT:    s_bfe_u32 s0, s6, 0xf000f
4676; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
4677; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v1
4678; GFX9-NEXT:    v_mov_b32_e32 v3, s6
4679; GFX9-NEXT:    s_bfe_u32 s1, s4, 0xf000f
4680; GFX9-NEXT:    v_alignbit_b32 v3, s7, v3, 30
4681; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
4682; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s1
4683; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v6
4684; GFX9-NEXT:    v_and_b32_e32 v3, s8, v3
4685; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
4686; GFX9-NEXT:    v_mad_f32 v4, -v5, v1, v4
4687; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
4688; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, v3
4689; GFX9-NEXT:    v_mov_b32_e32 v0, s4
4690; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v1
4691; GFX9-NEXT:    v_alignbit_b32 v0, s5, v0, 30
4692; GFX9-NEXT:    v_mul_f32_e32 v1, v7, v8
4693; GFX9-NEXT:    v_and_b32_e32 v0, s8, v0
4694; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
4695; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
4696; GFX9-NEXT:    v_mad_f32 v5, -v1, v6, v7
4697; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
4698; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, v0
4699; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v3
4700; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v6
4701; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
4702; GFX9-NEXT:    v_mul_f32_e32 v1, v0, v7
4703; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
4704; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v1
4705; GFX9-NEXT:    v_mad_f32 v0, -v1, v3, v0
4706; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, v3
4707; GFX9-NEXT:    v_and_b32_e32 v3, s8, v4
4708; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v6, vcc
4709; GFX9-NEXT:    v_and_b32_e32 v4, s8, v5
4710; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 15, v4
4711; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 30, v[0:1]
4712; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
4713; GFX9-NEXT:    v_or_b32_e32 v0, v3, v0
4714; GFX9-NEXT:    global_store_dword v2, v0, s[2:3]
4715; GFX9-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
4716; GFX9-NEXT:    global_store_short v2, v0, s[2:3] offset:4
4717; GFX9-NEXT:    s_endpgm
4718  %r = udiv <3 x i15> %x, %y
4719  store <3 x i15> %r, <3 x i15> addrspace(1)* %out
4720  ret void
4721}
4722
4723define amdgpu_kernel void @urem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x, <3 x i15> %y) {
4724; CHECK-LABEL: @urem_v3i15(
4725; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i15> [[X:%.*]], i64 0
4726; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i15> [[Y:%.*]], i64 0
4727; CHECK-NEXT:    [[TMP3:%.*]] = zext i15 [[TMP1]] to i32
4728; CHECK-NEXT:    [[TMP4:%.*]] = zext i15 [[TMP2]] to i32
4729; CHECK-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float
4730; CHECK-NEXT:    [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float
4731; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])
4732; CHECK-NEXT:    [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]
4733; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])
4734; CHECK-NEXT:    [[TMP10:%.*]] = fneg fast float [[TMP9]]
4735; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])
4736; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP9]] to i32
4737; CHECK-NEXT:    [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])
4738; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])
4739; CHECK-NEXT:    [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]
4740; CHECK-NEXT:    [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 0
4741; CHECK-NEXT:    [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]
4742; CHECK-NEXT:    [[TMP18:%.*]] = mul i32 [[TMP17]], [[TMP4]]
4743; CHECK-NEXT:    [[TMP19:%.*]] = sub i32 [[TMP3]], [[TMP18]]
4744; CHECK-NEXT:    [[TMP20:%.*]] = and i32 [[TMP19]], 32767
4745; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i15
4746; CHECK-NEXT:    [[TMP22:%.*]] = insertelement <3 x i15> undef, i15 [[TMP21]], i64 0
4747; CHECK-NEXT:    [[TMP23:%.*]] = extractelement <3 x i15> [[X]], i64 1
4748; CHECK-NEXT:    [[TMP24:%.*]] = extractelement <3 x i15> [[Y]], i64 1
4749; CHECK-NEXT:    [[TMP25:%.*]] = zext i15 [[TMP23]] to i32
4750; CHECK-NEXT:    [[TMP26:%.*]] = zext i15 [[TMP24]] to i32
4751; CHECK-NEXT:    [[TMP27:%.*]] = uitofp i32 [[TMP25]] to float
4752; CHECK-NEXT:    [[TMP28:%.*]] = uitofp i32 [[TMP26]] to float
4753; CHECK-NEXT:    [[TMP29:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP28]])
4754; CHECK-NEXT:    [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]]
4755; CHECK-NEXT:    [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]])
4756; CHECK-NEXT:    [[TMP32:%.*]] = fneg fast float [[TMP31]]
4757; CHECK-NEXT:    [[TMP33:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP32]], float [[TMP28]], float [[TMP27]])
4758; CHECK-NEXT:    [[TMP34:%.*]] = fptoui float [[TMP31]] to i32
4759; CHECK-NEXT:    [[TMP35:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
4760; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.fabs.f32(float [[TMP28]])
4761; CHECK-NEXT:    [[TMP37:%.*]] = fcmp fast oge float [[TMP35]], [[TMP36]]
4762; CHECK-NEXT:    [[TMP38:%.*]] = select i1 [[TMP37]], i32 1, i32 0
4763; CHECK-NEXT:    [[TMP39:%.*]] = add i32 [[TMP34]], [[TMP38]]
4764; CHECK-NEXT:    [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP26]]
4765; CHECK-NEXT:    [[TMP41:%.*]] = sub i32 [[TMP25]], [[TMP40]]
4766; CHECK-NEXT:    [[TMP42:%.*]] = and i32 [[TMP41]], 32767
4767; CHECK-NEXT:    [[TMP43:%.*]] = trunc i32 [[TMP42]] to i15
4768; CHECK-NEXT:    [[TMP44:%.*]] = insertelement <3 x i15> [[TMP22]], i15 [[TMP43]], i64 1
4769; CHECK-NEXT:    [[TMP45:%.*]] = extractelement <3 x i15> [[X]], i64 2
4770; CHECK-NEXT:    [[TMP46:%.*]] = extractelement <3 x i15> [[Y]], i64 2
4771; CHECK-NEXT:    [[TMP47:%.*]] = zext i15 [[TMP45]] to i32
4772; CHECK-NEXT:    [[TMP48:%.*]] = zext i15 [[TMP46]] to i32
4773; CHECK-NEXT:    [[TMP49:%.*]] = uitofp i32 [[TMP47]] to float
4774; CHECK-NEXT:    [[TMP50:%.*]] = uitofp i32 [[TMP48]] to float
4775; CHECK-NEXT:    [[TMP51:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP50]])
4776; CHECK-NEXT:    [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]]
4777; CHECK-NEXT:    [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]])
4778; CHECK-NEXT:    [[TMP54:%.*]] = fneg fast float [[TMP53]]
4779; CHECK-NEXT:    [[TMP55:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP54]], float [[TMP50]], float [[TMP49]])
4780; CHECK-NEXT:    [[TMP56:%.*]] = fptoui float [[TMP53]] to i32
4781; CHECK-NEXT:    [[TMP57:%.*]] = call fast float @llvm.fabs.f32(float [[TMP55]])
4782; CHECK-NEXT:    [[TMP58:%.*]] = call fast float @llvm.fabs.f32(float [[TMP50]])
4783; CHECK-NEXT:    [[TMP59:%.*]] = fcmp fast oge float [[TMP57]], [[TMP58]]
4784; CHECK-NEXT:    [[TMP60:%.*]] = select i1 [[TMP59]], i32 1, i32 0
4785; CHECK-NEXT:    [[TMP61:%.*]] = add i32 [[TMP56]], [[TMP60]]
4786; CHECK-NEXT:    [[TMP62:%.*]] = mul i32 [[TMP61]], [[TMP48]]
4787; CHECK-NEXT:    [[TMP63:%.*]] = sub i32 [[TMP47]], [[TMP62]]
4788; CHECK-NEXT:    [[TMP64:%.*]] = and i32 [[TMP63]], 32767
4789; CHECK-NEXT:    [[TMP65:%.*]] = trunc i32 [[TMP64]] to i15
4790; CHECK-NEXT:    [[TMP66:%.*]] = insertelement <3 x i15> [[TMP44]], i15 [[TMP65]], i64 2
4791; CHECK-NEXT:    store <3 x i15> [[TMP66]], <3 x i15> addrspace(1)* [[OUT:%.*]], align 8
4792; CHECK-NEXT:    ret void
4793;
4794; GFX6-LABEL: urem_v3i15:
4795; GFX6:       ; %bb.0:
4796; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
4797; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
4798; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
4799; GFX6-NEXT:    s_mov_b32 s7, 0xf000
4800; GFX6-NEXT:    s_mov_b32 s6, -1
4801; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
4802; GFX6-NEXT:    v_mov_b32_e32 v0, s2
4803; GFX6-NEXT:    v_alignbit_b32 v0, s3, v0, 30
4804; GFX6-NEXT:    s_movk_i32 s3, 0x7fff
4805; GFX6-NEXT:    s_and_b32 s10, s0, s3
4806; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s10
4807; GFX6-NEXT:    s_and_b32 s9, s2, s3
4808; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s9
4809; GFX6-NEXT:    v_mov_b32_e32 v2, s0
4810; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v1
4811; GFX6-NEXT:    v_alignbit_b32 v2, s1, v2, 30
4812; GFX6-NEXT:    s_bfe_u32 s1, s0, 0xf000f
4813; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s1
4814; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
4815; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
4816; GFX6-NEXT:    v_mad_f32 v3, -v4, v1, v3
4817; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
4818; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v1
4819; GFX6-NEXT:    s_bfe_u32 s10, s2, 0xf000f
4820; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s10
4821; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v4, vcc
4822; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s0
4823; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v5
4824; GFX6-NEXT:    v_and_b32_e32 v2, s3, v2
4825; GFX6-NEXT:    v_and_b32_e32 v0, s3, v0
4826; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, s2, v1
4827; GFX6-NEXT:    v_mul_f32_e32 v1, v3, v4
4828; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, v2
4829; GFX6-NEXT:    v_cvt_f32_u32_e32 v7, v0
4830; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
4831; GFX6-NEXT:    v_mad_f32 v3, -v1, v5, v3
4832; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v4
4833; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v5
4834; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
4835; GFX6-NEXT:    s_lshr_b32 s0, s0, 15
4836; GFX6-NEXT:    v_mul_f32_e32 v3, v7, v8
4837; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
4838; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v3
4839; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
4840; GFX6-NEXT:    v_mad_f32 v3, -v3, v4, v7
4841; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v4
4842; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
4843; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s0
4844; GFX6-NEXT:    v_mul_lo_u32 v2, v3, v2
4845; GFX6-NEXT:    s_lshr_b32 s8, s2, 15
4846; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s8, v1
4847; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, v2, v0
4848; GFX6-NEXT:    v_and_b32_e32 v3, s3, v3
4849; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 30
4850; GFX6-NEXT:    v_and_b32_e32 v2, s3, v6
4851; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
4852; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
4853; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
4854; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
4855; GFX6-NEXT:    s_waitcnt expcnt(0)
4856; GFX6-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
4857; GFX6-NEXT:    buffer_store_short v0, off, s[4:7], 0 offset:4
4858; GFX6-NEXT:    s_endpgm
4859;
4860; GFX9-LABEL: urem_v3i15:
4861; GFX9:       ; %bb.0:
4862; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
4863; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
4864; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
4865; GFX9-NEXT:    s_movk_i32 s8, 0x7fff
4866; GFX9-NEXT:    v_mov_b32_e32 v2, 0
4867; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
4868; GFX9-NEXT:    v_mov_b32_e32 v0, s4
4869; GFX9-NEXT:    v_alignbit_b32 v0, s5, v0, 30
4870; GFX9-NEXT:    s_and_b32 s5, s6, s8
4871; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s5
4872; GFX9-NEXT:    s_and_b32 s0, s4, s8
4873; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s0
4874; GFX9-NEXT:    s_bfe_u32 s5, s6, 0xf000f
4875; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v1
4876; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s5
4877; GFX9-NEXT:    v_mov_b32_e32 v3, s6
4878; GFX9-NEXT:    v_alignbit_b32 v3, s7, v3, 30
4879; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
4880; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
4881; GFX9-NEXT:    v_mad_f32 v4, -v5, v1, v4
4882; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
4883; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v1
4884; GFX9-NEXT:    s_bfe_u32 s1, s4, 0xf000f
4885; GFX9-NEXT:    v_and_b32_e32 v3, s8, v3
4886; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v5, vcc
4887; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v3
4888; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s1
4889; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v6
4890; GFX9-NEXT:    v_and_b32_e32 v0, s8, v0
4891; GFX9-NEXT:    v_rcp_iflag_f32_e32 v9, v5
4892; GFX9-NEXT:    s_lshr_b32 s0, s6, 15
4893; GFX9-NEXT:    v_mul_f32_e32 v4, v7, v8
4894; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, v0
4895; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
4896; GFX9-NEXT:    v_mad_f32 v7, -v4, v6, v7
4897; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v7|, v6
4898; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
4899; GFX9-NEXT:    v_mul_f32_e32 v6, v8, v9
4900; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
4901; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v6
4902; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
4903; GFX9-NEXT:    v_mad_f32 v6, -v6, v5, v8
4904; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, v5
4905; GFX9-NEXT:    v_mul_lo_u32 v4, v4, s0
4906; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
4907; GFX9-NEXT:    v_mul_lo_u32 v3, v5, v3
4908; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s6
4909; GFX9-NEXT:    s_lshr_b32 s0, s4, 15
4910; GFX9-NEXT:    v_sub_u32_e32 v4, s0, v4
4911; GFX9-NEXT:    v_and_b32_e32 v4, s8, v4
4912; GFX9-NEXT:    v_sub_u32_e32 v5, s4, v1
4913; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v3
4914; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 30, v[0:1]
4915; GFX9-NEXT:    v_and_b32_e32 v3, s8, v5
4916; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 15, v4
4917; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
4918; GFX9-NEXT:    v_or_b32_e32 v0, v3, v0
4919; GFX9-NEXT:    global_store_dword v2, v0, s[2:3]
4920; GFX9-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
4921; GFX9-NEXT:    global_store_short v2, v0, s[2:3] offset:4
4922; GFX9-NEXT:    s_endpgm
4923  %r = urem <3 x i15> %x, %y
4924  store <3 x i15> %r, <3 x i15> addrspace(1)* %out
4925  ret void
4926}
4927
4928define amdgpu_kernel void @sdiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x, <3 x i15> %y) {
4929; CHECK-LABEL: @sdiv_v3i15(
4930; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i15> [[X:%.*]], i64 0
4931; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i15> [[Y:%.*]], i64 0
4932; CHECK-NEXT:    [[TMP3:%.*]] = sext i15 [[TMP1]] to i32
4933; CHECK-NEXT:    [[TMP4:%.*]] = sext i15 [[TMP2]] to i32
4934; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
4935; CHECK-NEXT:    [[TMP6:%.*]] = ashr i32 [[TMP5]], 30
4936; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], 1
4937; CHECK-NEXT:    [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float
4938; CHECK-NEXT:    [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float
4939; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
4940; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]
4941; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])
4942; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
4943; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
4944; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
4945; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
4946; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
4947; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
4948; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
4949; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
4950; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 17
4951; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 17
4952; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i15
4953; CHECK-NEXT:    [[TMP24:%.*]] = insertelement <3 x i15> undef, i15 [[TMP23]], i64 0
4954; CHECK-NEXT:    [[TMP25:%.*]] = extractelement <3 x i15> [[X]], i64 1
4955; CHECK-NEXT:    [[TMP26:%.*]] = extractelement <3 x i15> [[Y]], i64 1
4956; CHECK-NEXT:    [[TMP27:%.*]] = sext i15 [[TMP25]] to i32
4957; CHECK-NEXT:    [[TMP28:%.*]] = sext i15 [[TMP26]] to i32
4958; CHECK-NEXT:    [[TMP29:%.*]] = xor i32 [[TMP27]], [[TMP28]]
4959; CHECK-NEXT:    [[TMP30:%.*]] = ashr i32 [[TMP29]], 30
4960; CHECK-NEXT:    [[TMP31:%.*]] = or i32 [[TMP30]], 1
4961; CHECK-NEXT:    [[TMP32:%.*]] = sitofp i32 [[TMP27]] to float
4962; CHECK-NEXT:    [[TMP33:%.*]] = sitofp i32 [[TMP28]] to float
4963; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])
4964; CHECK-NEXT:    [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]]
4965; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]])
4966; CHECK-NEXT:    [[TMP37:%.*]] = fneg fast float [[TMP36]]
4967; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]])
4968; CHECK-NEXT:    [[TMP39:%.*]] = fptosi float [[TMP36]] to i32
4969; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]])
4970; CHECK-NEXT:    [[TMP41:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
4971; CHECK-NEXT:    [[TMP42:%.*]] = fcmp fast oge float [[TMP40]], [[TMP41]]
4972; CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP31]], i32 0
4973; CHECK-NEXT:    [[TMP44:%.*]] = add i32 [[TMP39]], [[TMP43]]
4974; CHECK-NEXT:    [[TMP45:%.*]] = shl i32 [[TMP44]], 17
4975; CHECK-NEXT:    [[TMP46:%.*]] = ashr i32 [[TMP45]], 17
4976; CHECK-NEXT:    [[TMP47:%.*]] = trunc i32 [[TMP46]] to i15
4977; CHECK-NEXT:    [[TMP48:%.*]] = insertelement <3 x i15> [[TMP24]], i15 [[TMP47]], i64 1
4978; CHECK-NEXT:    [[TMP49:%.*]] = extractelement <3 x i15> [[X]], i64 2
4979; CHECK-NEXT:    [[TMP50:%.*]] = extractelement <3 x i15> [[Y]], i64 2
4980; CHECK-NEXT:    [[TMP51:%.*]] = sext i15 [[TMP49]] to i32
4981; CHECK-NEXT:    [[TMP52:%.*]] = sext i15 [[TMP50]] to i32
4982; CHECK-NEXT:    [[TMP53:%.*]] = xor i32 [[TMP51]], [[TMP52]]
4983; CHECK-NEXT:    [[TMP54:%.*]] = ashr i32 [[TMP53]], 30
4984; CHECK-NEXT:    [[TMP55:%.*]] = or i32 [[TMP54]], 1
4985; CHECK-NEXT:    [[TMP56:%.*]] = sitofp i32 [[TMP51]] to float
4986; CHECK-NEXT:    [[TMP57:%.*]] = sitofp i32 [[TMP52]] to float
4987; CHECK-NEXT:    [[TMP58:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP57]])
4988; CHECK-NEXT:    [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]]
4989; CHECK-NEXT:    [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]])
4990; CHECK-NEXT:    [[TMP61:%.*]] = fneg fast float [[TMP60]]
4991; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]])
4992; CHECK-NEXT:    [[TMP63:%.*]] = fptosi float [[TMP60]] to i32
4993; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]])
4994; CHECK-NEXT:    [[TMP65:%.*]] = call fast float @llvm.fabs.f32(float [[TMP57]])
4995; CHECK-NEXT:    [[TMP66:%.*]] = fcmp fast oge float [[TMP64]], [[TMP65]]
4996; CHECK-NEXT:    [[TMP67:%.*]] = select i1 [[TMP66]], i32 [[TMP55]], i32 0
4997; CHECK-NEXT:    [[TMP68:%.*]] = add i32 [[TMP63]], [[TMP67]]
4998; CHECK-NEXT:    [[TMP69:%.*]] = shl i32 [[TMP68]], 17
4999; CHECK-NEXT:    [[TMP70:%.*]] = ashr i32 [[TMP69]], 17
5000; CHECK-NEXT:    [[TMP71:%.*]] = trunc i32 [[TMP70]] to i15
5001; CHECK-NEXT:    [[TMP72:%.*]] = insertelement <3 x i15> [[TMP48]], i15 [[TMP71]], i64 2
5002; CHECK-NEXT:    store <3 x i15> [[TMP72]], <3 x i15> addrspace(1)* [[OUT:%.*]], align 8
5003; CHECK-NEXT:    ret void
5004;
5005; GFX6-LABEL: sdiv_v3i15:
5006; GFX6:       ; %bb.0:
5007; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
5008; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
5009; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
5010; GFX6-NEXT:    s_mov_b32 s7, 0xf000
5011; GFX6-NEXT:    s_mov_b32 s6, -1
5012; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5013; GFX6-NEXT:    v_mov_b32_e32 v0, s2
5014; GFX6-NEXT:    v_alignbit_b32 v0, s3, v0, 30
5015; GFX6-NEXT:    s_bfe_i32 s3, s0, 0xf0000
5016; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s3
5017; GFX6-NEXT:    v_mov_b32_e32 v1, s0
5018; GFX6-NEXT:    v_alignbit_b32 v1, s1, v1, 30
5019; GFX6-NEXT:    s_bfe_i32 s1, s2, 0xf0000
5020; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s1
5021; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
5022; GFX6-NEXT:    s_xor_b32 s1, s1, s3
5023; GFX6-NEXT:    s_bfe_i32 s0, s0, 0xf000f
5024; GFX6-NEXT:    s_ashr_i32 s1, s1, 30
5025; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
5026; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
5027; GFX6-NEXT:    v_mad_f32 v3, -v4, v2, v3
5028; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
5029; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v4
5030; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s0
5031; GFX6-NEXT:    s_or_b32 s1, s1, 1
5032; GFX6-NEXT:    v_mov_b32_e32 v5, s1
5033; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
5034; GFX6-NEXT:    s_bfe_i32 s1, s2, 0xf000f
5035; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
5036; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s1
5037; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
5038; GFX6-NEXT:    s_xor_b32 s0, s1, s0
5039; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 15
5040; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
5041; GFX6-NEXT:    v_mul_f32_e32 v5, v4, v5
5042; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
5043; GFX6-NEXT:    v_mad_f32 v4, -v5, v3, v4
5044; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v3|
5045; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
5046; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, v1
5047; GFX6-NEXT:    s_or_b32 s0, s0, 1
5048; GFX6-NEXT:    v_mov_b32_e32 v6, s0
5049; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v6, vcc
5050; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 15
5051; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
5052; GFX6-NEXT:    v_cvt_f32_i32_e32 v5, v0
5053; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v4
5054; GFX6-NEXT:    v_xor_b32_e32 v0, v0, v1
5055; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
5056; GFX6-NEXT:    v_or_b32_e32 v0, 1, v0
5057; GFX6-NEXT:    v_mul_f32_e32 v1, v5, v6
5058; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
5059; GFX6-NEXT:    v_mad_f32 v5, -v1, v4, v5
5060; GFX6-NEXT:    v_cvt_i32_f32_e32 v1, v1
5061; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, |v4|
5062; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
5063; GFX6-NEXT:    s_movk_i32 s0, 0x7fff
5064; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
5065; GFX6-NEXT:    v_and_b32_e32 v3, s0, v3
5066; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 30
5067; GFX6-NEXT:    v_and_b32_e32 v2, s0, v2
5068; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
5069; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
5070; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
5071; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
5072; GFX6-NEXT:    s_waitcnt expcnt(0)
5073; GFX6-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
5074; GFX6-NEXT:    buffer_store_short v0, off, s[4:7], 0 offset:4
5075; GFX6-NEXT:    s_endpgm
5076;
5077; GFX9-LABEL: sdiv_v3i15:
5078; GFX9:       ; %bb.0:
5079; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
5080; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
5081; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
5082; GFX9-NEXT:    v_mov_b32_e32 v2, 0
5083; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5084; GFX9-NEXT:    s_bfe_i32 s1, s4, 0xf0000
5085; GFX9-NEXT:    s_bfe_i32 s0, s6, 0xf0000
5086; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s0
5087; GFX9-NEXT:    v_cvt_f32_i32_e32 v4, s1
5088; GFX9-NEXT:    s_xor_b32 s0, s1, s0
5089; GFX9-NEXT:    v_mov_b32_e32 v0, s4
5090; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v3
5091; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
5092; GFX9-NEXT:    v_alignbit_b32 v0, s5, v0, 30
5093; GFX9-NEXT:    s_or_b32 s5, s0, 1
5094; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
5095; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
5096; GFX9-NEXT:    v_mad_f32 v4, -v5, v3, v4
5097; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v4|, |v3|
5098; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
5099; GFX9-NEXT:    s_cselect_b32 s0, s5, 0
5100; GFX9-NEXT:    v_cvt_i32_f32_e32 v5, v5
5101; GFX9-NEXT:    s_bfe_i32 s1, s6, 0xf000f
5102; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s1
5103; GFX9-NEXT:    v_mov_b32_e32 v1, s6
5104; GFX9-NEXT:    v_add_u32_e32 v4, s0, v5
5105; GFX9-NEXT:    s_bfe_i32 s0, s4, 0xf000f
5106; GFX9-NEXT:    v_cvt_f32_i32_e32 v5, s0
5107; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v3
5108; GFX9-NEXT:    v_alignbit_b32 v1, s7, v1, 30
5109; GFX9-NEXT:    s_xor_b32 s0, s0, s1
5110; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
5111; GFX9-NEXT:    v_mul_f32_e32 v6, v5, v6
5112; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
5113; GFX9-NEXT:    v_mad_f32 v5, -v6, v3, v5
5114; GFX9-NEXT:    v_bfe_i32 v1, v1, 0, 15
5115; GFX9-NEXT:    s_or_b32 s4, s0, 1
5116; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v5|, |v3|
5117; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, v1
5118; GFX9-NEXT:    v_cvt_i32_f32_e32 v6, v6
5119; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
5120; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
5121; GFX9-NEXT:    v_bfe_i32 v0, v0, 0, 15
5122; GFX9-NEXT:    v_add_u32_e32 v5, s0, v6
5123; GFX9-NEXT:    v_cvt_f32_i32_e32 v6, v0
5124; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v3
5125; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v1
5126; GFX9-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
5127; GFX9-NEXT:    v_or_b32_e32 v0, 1, v0
5128; GFX9-NEXT:    v_mul_f32_e32 v1, v6, v7
5129; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
5130; GFX9-NEXT:    v_cvt_i32_f32_e32 v7, v1
5131; GFX9-NEXT:    v_mad_f32 v1, -v1, v3, v6
5132; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
5133; GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
5134; GFX9-NEXT:    s_movk_i32 s0, 0x7fff
5135; GFX9-NEXT:    v_add_u32_e32 v0, v7, v0
5136; GFX9-NEXT:    v_and_b32_e32 v3, s0, v4
5137; GFX9-NEXT:    v_and_b32_e32 v4, s0, v5
5138; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 15, v4
5139; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 30, v[0:1]
5140; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
5141; GFX9-NEXT:    v_or_b32_e32 v0, v3, v0
5142; GFX9-NEXT:    global_store_dword v2, v0, s[2:3]
5143; GFX9-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
5144; GFX9-NEXT:    global_store_short v2, v0, s[2:3] offset:4
5145; GFX9-NEXT:    s_endpgm
5146  %r = sdiv <3 x i15> %x, %y
5147  store <3 x i15> %r, <3 x i15> addrspace(1)* %out
5148  ret void
5149}
5150
5151define amdgpu_kernel void @srem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x, <3 x i15> %y) {
5152; CHECK-LABEL: @srem_v3i15(
5153; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i15> [[X:%.*]], i64 0
5154; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i15> [[Y:%.*]], i64 0
5155; CHECK-NEXT:    [[TMP3:%.*]] = sext i15 [[TMP1]] to i32
5156; CHECK-NEXT:    [[TMP4:%.*]] = sext i15 [[TMP2]] to i32
5157; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
5158; CHECK-NEXT:    [[TMP6:%.*]] = ashr i32 [[TMP5]], 30
5159; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], 1
5160; CHECK-NEXT:    [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float
5161; CHECK-NEXT:    [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float
5162; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
5163; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]
5164; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])
5165; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
5166; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
5167; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
5168; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
5169; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
5170; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
5171; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
5172; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
5173; CHECK-NEXT:    [[TMP21:%.*]] = mul i32 [[TMP20]], [[TMP4]]
5174; CHECK-NEXT:    [[TMP22:%.*]] = sub i32 [[TMP3]], [[TMP21]]
5175; CHECK-NEXT:    [[TMP23:%.*]] = shl i32 [[TMP22]], 17
5176; CHECK-NEXT:    [[TMP24:%.*]] = ashr i32 [[TMP23]], 17
5177; CHECK-NEXT:    [[TMP25:%.*]] = trunc i32 [[TMP24]] to i15
5178; CHECK-NEXT:    [[TMP26:%.*]] = insertelement <3 x i15> undef, i15 [[TMP25]], i64 0
5179; CHECK-NEXT:    [[TMP27:%.*]] = extractelement <3 x i15> [[X]], i64 1
5180; CHECK-NEXT:    [[TMP28:%.*]] = extractelement <3 x i15> [[Y]], i64 1
5181; CHECK-NEXT:    [[TMP29:%.*]] = sext i15 [[TMP27]] to i32
5182; CHECK-NEXT:    [[TMP30:%.*]] = sext i15 [[TMP28]] to i32
5183; CHECK-NEXT:    [[TMP31:%.*]] = xor i32 [[TMP29]], [[TMP30]]
5184; CHECK-NEXT:    [[TMP32:%.*]] = ashr i32 [[TMP31]], 30
5185; CHECK-NEXT:    [[TMP33:%.*]] = or i32 [[TMP32]], 1
5186; CHECK-NEXT:    [[TMP34:%.*]] = sitofp i32 [[TMP29]] to float
5187; CHECK-NEXT:    [[TMP35:%.*]] = sitofp i32 [[TMP30]] to float
5188; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])
5189; CHECK-NEXT:    [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]]
5190; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]])
5191; CHECK-NEXT:    [[TMP39:%.*]] = fneg fast float [[TMP38]]
5192; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]])
5193; CHECK-NEXT:    [[TMP41:%.*]] = fptosi float [[TMP38]] to i32
5194; CHECK-NEXT:    [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]])
5195; CHECK-NEXT:    [[TMP43:%.*]] = call fast float @llvm.fabs.f32(float [[TMP35]])
5196; CHECK-NEXT:    [[TMP44:%.*]] = fcmp fast oge float [[TMP42]], [[TMP43]]
5197; CHECK-NEXT:    [[TMP45:%.*]] = select i1 [[TMP44]], i32 [[TMP33]], i32 0
5198; CHECK-NEXT:    [[TMP46:%.*]] = add i32 [[TMP41]], [[TMP45]]
5199; CHECK-NEXT:    [[TMP47:%.*]] = mul i32 [[TMP46]], [[TMP30]]
5200; CHECK-NEXT:    [[TMP48:%.*]] = sub i32 [[TMP29]], [[TMP47]]
5201; CHECK-NEXT:    [[TMP49:%.*]] = shl i32 [[TMP48]], 17
5202; CHECK-NEXT:    [[TMP50:%.*]] = ashr i32 [[TMP49]], 17
5203; CHECK-NEXT:    [[TMP51:%.*]] = trunc i32 [[TMP50]] to i15
5204; CHECK-NEXT:    [[TMP52:%.*]] = insertelement <3 x i15> [[TMP26]], i15 [[TMP51]], i64 1
5205; CHECK-NEXT:    [[TMP53:%.*]] = extractelement <3 x i15> [[X]], i64 2
5206; CHECK-NEXT:    [[TMP54:%.*]] = extractelement <3 x i15> [[Y]], i64 2
5207; CHECK-NEXT:    [[TMP55:%.*]] = sext i15 [[TMP53]] to i32
5208; CHECK-NEXT:    [[TMP56:%.*]] = sext i15 [[TMP54]] to i32
5209; CHECK-NEXT:    [[TMP57:%.*]] = xor i32 [[TMP55]], [[TMP56]]
5210; CHECK-NEXT:    [[TMP58:%.*]] = ashr i32 [[TMP57]], 30
5211; CHECK-NEXT:    [[TMP59:%.*]] = or i32 [[TMP58]], 1
5212; CHECK-NEXT:    [[TMP60:%.*]] = sitofp i32 [[TMP55]] to float
5213; CHECK-NEXT:    [[TMP61:%.*]] = sitofp i32 [[TMP56]] to float
5214; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP61]])
5215; CHECK-NEXT:    [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]]
5216; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]])
5217; CHECK-NEXT:    [[TMP65:%.*]] = fneg fast float [[TMP64]]
5218; CHECK-NEXT:    [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]])
5219; CHECK-NEXT:    [[TMP67:%.*]] = fptosi float [[TMP64]] to i32
5220; CHECK-NEXT:    [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]])
5221; CHECK-NEXT:    [[TMP69:%.*]] = call fast float @llvm.fabs.f32(float [[TMP61]])
5222; CHECK-NEXT:    [[TMP70:%.*]] = fcmp fast oge float [[TMP68]], [[TMP69]]
5223; CHECK-NEXT:    [[TMP71:%.*]] = select i1 [[TMP70]], i32 [[TMP59]], i32 0
5224; CHECK-NEXT:    [[TMP72:%.*]] = add i32 [[TMP67]], [[TMP71]]
5225; CHECK-NEXT:    [[TMP73:%.*]] = mul i32 [[TMP72]], [[TMP56]]
5226; CHECK-NEXT:    [[TMP74:%.*]] = sub i32 [[TMP55]], [[TMP73]]
5227; CHECK-NEXT:    [[TMP75:%.*]] = shl i32 [[TMP74]], 17
5228; CHECK-NEXT:    [[TMP76:%.*]] = ashr i32 [[TMP75]], 17
5229; CHECK-NEXT:    [[TMP77:%.*]] = trunc i32 [[TMP76]] to i15
5230; CHECK-NEXT:    [[TMP78:%.*]] = insertelement <3 x i15> [[TMP52]], i15 [[TMP77]], i64 2
5231; CHECK-NEXT:    store <3 x i15> [[TMP78]], <3 x i15> addrspace(1)* [[OUT:%.*]], align 8
5232; CHECK-NEXT:    ret void
5233;
5234; GFX6-LABEL: srem_v3i15:
5235; GFX6:       ; %bb.0:
5236; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
5237; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
5238; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
5239; GFX6-NEXT:    s_mov_b32 s7, 0xf000
5240; GFX6-NEXT:    s_mov_b32 s6, -1
5241; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5242; GFX6-NEXT:    v_mov_b32_e32 v0, s2
5243; GFX6-NEXT:    v_alignbit_b32 v0, s3, v0, 30
5244; GFX6-NEXT:    s_movk_i32 s3, 0x7fff
5245; GFX6-NEXT:    s_and_b32 s11, s0, s3
5246; GFX6-NEXT:    s_bfe_i32 s11, s11, 0xf0000
5247; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s11
5248; GFX6-NEXT:    s_and_b32 s9, s2, s3
5249; GFX6-NEXT:    s_bfe_i32 s9, s9, 0xf0000
5250; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s9
5251; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
5252; GFX6-NEXT:    s_xor_b32 s9, s9, s11
5253; GFX6-NEXT:    s_ashr_i32 s9, s9, 30
5254; GFX6-NEXT:    s_or_b32 s9, s9, 1
5255; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
5256; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
5257; GFX6-NEXT:    v_mad_f32 v3, -v4, v2, v3
5258; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v4
5259; GFX6-NEXT:    v_mov_b32_e32 v5, s9
5260; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
5261; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
5262; GFX6-NEXT:    v_mov_b32_e32 v1, s0
5263; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
5264; GFX6-NEXT:    s_bfe_u32 s12, s0, 0xf000f
5265; GFX6-NEXT:    v_alignbit_b32 v1, s1, v1, 30
5266; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s0
5267; GFX6-NEXT:    s_lshr_b32 s1, s0, 15
5268; GFX6-NEXT:    s_bfe_i32 s0, s12, 0xf0000
5269; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s0
5270; GFX6-NEXT:    s_bfe_u32 s10, s2, 0xf000f
5271; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s2, v2
5272; GFX6-NEXT:    s_lshr_b32 s8, s2, 15
5273; GFX6-NEXT:    s_bfe_i32 s2, s10, 0xf0000
5274; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s2
5275; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
5276; GFX6-NEXT:    s_xor_b32 s0, s2, s0
5277; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
5278; GFX6-NEXT:    s_or_b32 s0, s0, 1
5279; GFX6-NEXT:    v_mul_f32_e32 v5, v4, v5
5280; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
5281; GFX6-NEXT:    v_mad_f32 v4, -v5, v3, v4
5282; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
5283; GFX6-NEXT:    v_and_b32_e32 v1, s3, v1
5284; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v3|
5285; GFX6-NEXT:    v_mov_b32_e32 v6, s0
5286; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v6, vcc
5287; GFX6-NEXT:    v_bfe_i32 v4, v1, 0, 15
5288; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
5289; GFX6-NEXT:    v_cvt_f32_i32_e32 v5, v4
5290; GFX6-NEXT:    v_and_b32_e32 v0, s3, v0
5291; GFX6-NEXT:    v_bfe_i32 v6, v0, 0, 15
5292; GFX6-NEXT:    v_cvt_f32_i32_e32 v7, v6
5293; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v5
5294; GFX6-NEXT:    v_xor_b32_e32 v4, v6, v4
5295; GFX6-NEXT:    v_ashrrev_i32_e32 v4, 30, v4
5296; GFX6-NEXT:    v_or_b32_e32 v4, 1, v4
5297; GFX6-NEXT:    v_mul_f32_e32 v6, v7, v8
5298; GFX6-NEXT:    v_trunc_f32_e32 v6, v6
5299; GFX6-NEXT:    v_mad_f32 v7, -v6, v5, v7
5300; GFX6-NEXT:    v_cvt_i32_f32_e32 v6, v6
5301; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v7|, |v5|
5302; GFX6-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
5303; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s1
5304; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
5305; GFX6-NEXT:    v_mul_lo_u32 v1, v4, v1
5306; GFX6-NEXT:    v_and_b32_e32 v2, s3, v2
5307; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s8, v3
5308; GFX6-NEXT:    v_and_b32_e32 v3, s3, v3
5309; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, v1, v0
5310; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
5311; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 30
5312; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
5313; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
5314; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
5315; GFX6-NEXT:    s_waitcnt expcnt(0)
5316; GFX6-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
5317; GFX6-NEXT:    buffer_store_short v0, off, s[4:7], 0 offset:4
5318; GFX6-NEXT:    s_endpgm
5319;
5320; GFX9-LABEL: srem_v3i15:
5321; GFX9:       ; %bb.0:
5322; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
5323; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
5324; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
5325; GFX9-NEXT:    s_movk_i32 s8, 0x7fff
5326; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5327; GFX9-NEXT:    s_and_b32 s0, s4, s8
5328; GFX9-NEXT:    s_and_b32 s1, s6, s8
5329; GFX9-NEXT:    s_bfe_i32 s1, s1, 0xf0000
5330; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s1
5331; GFX9-NEXT:    s_bfe_i32 s0, s0, 0xf0000
5332; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s0
5333; GFX9-NEXT:    s_xor_b32 s0, s0, s1
5334; GFX9-NEXT:    v_rcp_iflag_f32_e32 v4, v2
5335; GFX9-NEXT:    v_mov_b32_e32 v0, s4
5336; GFX9-NEXT:    v_mov_b32_e32 v1, s6
5337; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
5338; GFX9-NEXT:    v_mul_f32_e32 v4, v3, v4
5339; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
5340; GFX9-NEXT:    v_mad_f32 v3, -v4, v2, v3
5341; GFX9-NEXT:    v_cvt_i32_f32_e32 v4, v4
5342; GFX9-NEXT:    v_alignbit_b32 v0, s5, v0, 30
5343; GFX9-NEXT:    v_alignbit_b32 v1, s7, v1, 30
5344; GFX9-NEXT:    s_or_b32 s11, s0, 1
5345; GFX9-NEXT:    s_lshr_b32 s9, s4, 15
5346; GFX9-NEXT:    s_bfe_u32 s5, s4, 0xf000f
5347; GFX9-NEXT:    s_lshr_b32 s7, s6, 15
5348; GFX9-NEXT:    s_bfe_u32 s10, s6, 0xf000f
5349; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v3|, |v2|
5350; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
5351; GFX9-NEXT:    s_cselect_b32 s0, s11, 0
5352; GFX9-NEXT:    v_add_u32_e32 v2, s0, v4
5353; GFX9-NEXT:    s_bfe_i32 s0, s10, 0xf0000
5354; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s0
5355; GFX9-NEXT:    s_bfe_i32 s1, s5, 0xf0000
5356; GFX9-NEXT:    v_cvt_f32_i32_e32 v4, s1
5357; GFX9-NEXT:    s_xor_b32 s0, s1, s0
5358; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v3
5359; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
5360; GFX9-NEXT:    s_or_b32 s5, s0, 1
5361; GFX9-NEXT:    v_and_b32_e32 v1, s8, v1
5362; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
5363; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
5364; GFX9-NEXT:    v_mad_f32 v4, -v5, v3, v4
5365; GFX9-NEXT:    v_cvt_i32_f32_e32 v5, v5
5366; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v4|, |v3|
5367; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
5368; GFX9-NEXT:    s_cselect_b32 s0, s5, 0
5369; GFX9-NEXT:    v_bfe_i32 v4, v1, 0, 15
5370; GFX9-NEXT:    v_add_u32_e32 v3, s0, v5
5371; GFX9-NEXT:    v_cvt_f32_i32_e32 v5, v4
5372; GFX9-NEXT:    v_and_b32_e32 v0, s8, v0
5373; GFX9-NEXT:    v_bfe_i32 v6, v0, 0, 15
5374; GFX9-NEXT:    v_cvt_f32_i32_e32 v7, v6
5375; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v5
5376; GFX9-NEXT:    v_xor_b32_e32 v4, v6, v4
5377; GFX9-NEXT:    v_ashrrev_i32_e32 v4, 30, v4
5378; GFX9-NEXT:    v_or_b32_e32 v4, 1, v4
5379; GFX9-NEXT:    v_mul_f32_e32 v6, v7, v8
5380; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
5381; GFX9-NEXT:    v_cvt_i32_f32_e32 v8, v6
5382; GFX9-NEXT:    v_mad_f32 v6, -v6, v5, v7
5383; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, |v5|
5384; GFX9-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
5385; GFX9-NEXT:    v_mul_lo_u32 v3, v3, s7
5386; GFX9-NEXT:    v_add_u32_e32 v4, v8, v4
5387; GFX9-NEXT:    v_mul_lo_u32 v2, v2, s6
5388; GFX9-NEXT:    v_mul_lo_u32 v1, v4, v1
5389; GFX9-NEXT:    v_sub_u32_e32 v3, s9, v3
5390; GFX9-NEXT:    v_and_b32_e32 v3, s8, v3
5391; GFX9-NEXT:    v_sub_u32_e32 v2, s4, v2
5392; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v1
5393; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 30, v[0:1]
5394; GFX9-NEXT:    v_and_b32_e32 v2, s8, v2
5395; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
5396; GFX9-NEXT:    v_or_b32_e32 v2, v2, v3
5397; GFX9-NEXT:    v_mov_b32_e32 v4, 0
5398; GFX9-NEXT:    v_or_b32_e32 v0, v2, v0
5399; GFX9-NEXT:    global_store_dword v4, v0, s[2:3]
5400; GFX9-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
5401; GFX9-NEXT:    global_store_short v4, v0, s[2:3] offset:4
5402; GFX9-NEXT:    s_endpgm
5403  %r = srem <3 x i15> %x, %y
5404  store <3 x i15> %r, <3 x i15> addrspace(1)* %out
5405  ret void
5406}
5407
5408define amdgpu_kernel void @udiv_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
5409; CHECK-LABEL: @udiv_i32_oddk_denom(
5410; CHECK-NEXT:    [[R:%.*]] = udiv i32 [[X:%.*]], 1235195
5411; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
5412; CHECK-NEXT:    ret void
5413;
5414; GFX6-LABEL: udiv_i32_oddk_denom:
5415; GFX6:       ; %bb.0:
5416; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
5417; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
5418; GFX6-NEXT:    v_mov_b32_e32 v0, 0xb2a50881
5419; GFX6-NEXT:    s_mov_b32 s7, 0xf000
5420; GFX6-NEXT:    s_mov_b32 s6, -1
5421; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5422; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
5423; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s0, v0
5424; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
5425; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
5426; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 20, v0
5427; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
5428; GFX6-NEXT:    s_endpgm
5429;
5430; GFX9-LABEL: udiv_i32_oddk_denom:
5431; GFX9:       ; %bb.0:
5432; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
5433; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
5434; GFX9-NEXT:    v_mov_b32_e32 v0, 0
5435; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5436; GFX9-NEXT:    s_mul_hi_u32 s0, s4, 0xb2a50881
5437; GFX9-NEXT:    s_sub_i32 s1, s4, s0
5438; GFX9-NEXT:    s_lshr_b32 s1, s1, 1
5439; GFX9-NEXT:    s_add_i32 s1, s1, s0
5440; GFX9-NEXT:    s_lshr_b32 s0, s1, 20
5441; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5442; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
5443; GFX9-NEXT:    s_endpgm
5444  %r = udiv i32 %x, 1235195
5445  store i32 %r, i32 addrspace(1)* %out
5446  ret void
5447}
5448
5449define amdgpu_kernel void @udiv_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x) {
5450; CHECK-LABEL: @udiv_i32_pow2k_denom(
5451; CHECK-NEXT:    [[R:%.*]] = udiv i32 [[X:%.*]], 4096
5452; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
5453; CHECK-NEXT:    ret void
5454;
5455; GFX6-LABEL: udiv_i32_pow2k_denom:
5456; GFX6:       ; %bb.0:
5457; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
5458; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
5459; GFX6-NEXT:    s_mov_b32 s7, 0xf000
5460; GFX6-NEXT:    s_mov_b32 s6, -1
5461; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5462; GFX6-NEXT:    s_lshr_b32 s0, s0, 12
5463; GFX6-NEXT:    v_mov_b32_e32 v0, s0
5464; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
5465; GFX6-NEXT:    s_endpgm
5466;
5467; GFX9-LABEL: udiv_i32_pow2k_denom:
5468; GFX9:       ; %bb.0:
5469; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
5470; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
5471; GFX9-NEXT:    v_mov_b32_e32 v0, 0
5472; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5473; GFX9-NEXT:    s_lshr_b32 s0, s4, 12
5474; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5475; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
5476; GFX9-NEXT:    s_endpgm
5477  %r = udiv i32 %x, 4096
5478  store i32 %r, i32 addrspace(1)* %out
5479  ret void
5480}
5481
5482define amdgpu_kernel void @udiv_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %x, i32 %y) {
5483; CHECK-LABEL: @udiv_i32_pow2_shl_denom(
5484; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]]
5485; CHECK-NEXT:    [[R:%.*]] = udiv i32 [[X:%.*]], [[SHL_Y]]
5486; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
5487; CHECK-NEXT:    ret void
5488;
5489; GFX6-LABEL: udiv_i32_pow2_shl_denom:
5490; GFX6:       ; %bb.0:
5491; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
5492; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
5493; GFX6-NEXT:    s_mov_b32 s7, 0xf000
5494; GFX6-NEXT:    s_mov_b32 s6, -1
5495; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5496; GFX6-NEXT:    s_add_i32 s1, s1, 12
5497; GFX6-NEXT:    s_lshr_b32 s0, s0, s1
5498; GFX6-NEXT:    v_mov_b32_e32 v0, s0
5499; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
5500; GFX6-NEXT:    s_endpgm
5501;
5502; GFX9-LABEL: udiv_i32_pow2_shl_denom:
5503; GFX9:       ; %bb.0:
5504; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
5505; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
5506; GFX9-NEXT:    v_mov_b32_e32 v0, 0
5507; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5508; GFX9-NEXT:    s_add_i32 s0, s5, 12
5509; GFX9-NEXT:    s_lshr_b32 s0, s4, s0
5510; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5511; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
5512; GFX9-NEXT:    s_endpgm
5513  %shl.y = shl i32 4096, %y
5514  %r = udiv i32 %x, %shl.y
5515  store i32 %r, i32 addrspace(1)* %out
5516  ret void
5517}
5518
5519define amdgpu_kernel void @udiv_v2i32_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) {
5520; CHECK-LABEL: @udiv_v2i32_pow2k_denom(
5521; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
5522; CHECK-NEXT:    [[TMP2:%.*]] = udiv i32 [[TMP1]], 4096
5523; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0
5524; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1
5525; CHECK-NEXT:    [[TMP5:%.*]] = udiv i32 [[TMP4]], 4096
5526; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1
5527; CHECK-NEXT:    store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
5528; CHECK-NEXT:    ret void
5529;
5530; GFX6-LABEL: udiv_v2i32_pow2k_denom:
5531; GFX6:       ; %bb.0:
5532; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
5533; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
5534; GFX6-NEXT:    s_mov_b32 s7, 0xf000
5535; GFX6-NEXT:    s_mov_b32 s6, -1
5536; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5537; GFX6-NEXT:    s_lshr_b32 s0, s0, 12
5538; GFX6-NEXT:    s_lshr_b32 s1, s1, 12
5539; GFX6-NEXT:    v_mov_b32_e32 v0, s0
5540; GFX6-NEXT:    v_mov_b32_e32 v1, s1
5541; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
5542; GFX6-NEXT:    s_endpgm
5543;
5544; GFX9-LABEL: udiv_v2i32_pow2k_denom:
5545; GFX9:       ; %bb.0:
5546; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
5547; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
5548; GFX9-NEXT:    v_mov_b32_e32 v2, 0
5549; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5550; GFX9-NEXT:    s_lshr_b32 s0, s4, 12
5551; GFX9-NEXT:    s_lshr_b32 s1, s5, 12
5552; GFX9-NEXT:    v_mov_b32_e32 v0, s0
5553; GFX9-NEXT:    v_mov_b32_e32 v1, s1
5554; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
5555; GFX9-NEXT:    s_endpgm
5556  %r = udiv <2 x i32> %x, <i32 4096, i32 4096>
5557  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
5558  ret void
5559}
5560
5561define amdgpu_kernel void @udiv_v2i32_mixed_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) {
5562; CHECK-LABEL: @udiv_v2i32_mixed_pow2k_denom(
5563; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
5564; CHECK-NEXT:    [[TMP2:%.*]] = udiv i32 [[TMP1]], 4096
5565; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0
5566; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1
5567; CHECK-NEXT:    [[TMP5:%.*]] = udiv i32 [[TMP4]], 4095
5568; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1
5569; CHECK-NEXT:    store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
5570; CHECK-NEXT:    ret void
5571;
5572; GFX6-LABEL: udiv_v2i32_mixed_pow2k_denom:
5573; GFX6:       ; %bb.0:
5574; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
5575; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
5576; GFX6-NEXT:    v_mov_b32_e32 v0, 0x100101
5577; GFX6-NEXT:    s_mov_b32 s7, 0xf000
5578; GFX6-NEXT:    s_mov_b32 s6, -1
5579; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5580; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
5581; GFX6-NEXT:    s_lshr_b32 s0, s0, 12
5582; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v0
5583; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
5584; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
5585; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 11, v0
5586; GFX6-NEXT:    v_mov_b32_e32 v0, s0
5587; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
5588; GFX6-NEXT:    s_endpgm
5589;
5590; GFX9-LABEL: udiv_v2i32_mixed_pow2k_denom:
5591; GFX9:       ; %bb.0:
5592; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
5593; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
5594; GFX9-NEXT:    v_mov_b32_e32 v2, 0
5595; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5596; GFX9-NEXT:    s_mul_hi_u32 s1, s5, 0x100101
5597; GFX9-NEXT:    s_lshr_b32 s0, s4, 12
5598; GFX9-NEXT:    s_sub_i32 s4, s5, s1
5599; GFX9-NEXT:    s_lshr_b32 s4, s4, 1
5600; GFX9-NEXT:    s_add_i32 s4, s4, s1
5601; GFX9-NEXT:    s_lshr_b32 s1, s4, 11
5602; GFX9-NEXT:    v_mov_b32_e32 v0, s0
5603; GFX9-NEXT:    v_mov_b32_e32 v1, s1
5604; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
5605; GFX9-NEXT:    s_endpgm
5606  %r = udiv <2 x i32> %x, <i32 4096, i32 4095>
5607  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
5608  ret void
5609}
5610
5611define amdgpu_kernel void @udiv_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) {
5612; CHECK-LABEL: @udiv_v2i32_pow2_shl_denom(
5613; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i32> <i32 4096, i32 4096>, [[Y:%.*]]
5614; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
5615; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 0
5616; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float
5617; CHECK-NEXT:    [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])
5618; CHECK-NEXT:    [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41EFFFFFC0000000
5619; CHECK-NEXT:    [[TMP6:%.*]] = fptoui float [[TMP5]] to i32
5620; CHECK-NEXT:    [[TMP7:%.*]] = sub i32 0, [[TMP2]]
5621; CHECK-NEXT:    [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP6]]
5622; CHECK-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP6]] to i64
5623; CHECK-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP8]] to i64
5624; CHECK-NEXT:    [[TMP11:%.*]] = mul i64 [[TMP9]], [[TMP10]]
5625; CHECK-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
5626; CHECK-NEXT:    [[TMP13:%.*]] = lshr i64 [[TMP11]], 32
5627; CHECK-NEXT:    [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32
5628; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP6]], [[TMP14]]
5629; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP1]] to i64
5630; CHECK-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP15]] to i64
5631; CHECK-NEXT:    [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]
5632; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
5633; CHECK-NEXT:    [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
5634; CHECK-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
5635; CHECK-NEXT:    [[TMP22:%.*]] = mul i32 [[TMP21]], [[TMP2]]
5636; CHECK-NEXT:    [[TMP23:%.*]] = sub i32 [[TMP1]], [[TMP22]]
5637; CHECK-NEXT:    [[TMP24:%.*]] = icmp uge i32 [[TMP23]], [[TMP2]]
5638; CHECK-NEXT:    [[TMP25:%.*]] = add i32 [[TMP21]], 1
5639; CHECK-NEXT:    [[TMP26:%.*]] = select i1 [[TMP24]], i32 [[TMP25]], i32 [[TMP21]]
5640; CHECK-NEXT:    [[TMP27:%.*]] = sub i32 [[TMP23]], [[TMP2]]
5641; CHECK-NEXT:    [[TMP28:%.*]] = select i1 [[TMP24]], i32 [[TMP27]], i32 [[TMP23]]
5642; CHECK-NEXT:    [[TMP29:%.*]] = icmp uge i32 [[TMP28]], [[TMP2]]
5643; CHECK-NEXT:    [[TMP30:%.*]] = add i32 [[TMP26]], 1
5644; CHECK-NEXT:    [[TMP31:%.*]] = select i1 [[TMP29]], i32 [[TMP30]], i32 [[TMP26]]
5645; CHECK-NEXT:    [[TMP32:%.*]] = insertelement <2 x i32> undef, i32 [[TMP31]], i64 0
5646; CHECK-NEXT:    [[TMP33:%.*]] = extractelement <2 x i32> [[X]], i64 1
5647; CHECK-NEXT:    [[TMP34:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1
5648; CHECK-NEXT:    [[TMP35:%.*]] = uitofp i32 [[TMP34]] to float
5649; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])
5650; CHECK-NEXT:    [[TMP37:%.*]] = fmul fast float [[TMP36]], 0x41EFFFFFC0000000
5651; CHECK-NEXT:    [[TMP38:%.*]] = fptoui float [[TMP37]] to i32
5652; CHECK-NEXT:    [[TMP39:%.*]] = sub i32 0, [[TMP34]]
5653; CHECK-NEXT:    [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP38]]
5654; CHECK-NEXT:    [[TMP41:%.*]] = zext i32 [[TMP38]] to i64
5655; CHECK-NEXT:    [[TMP42:%.*]] = zext i32 [[TMP40]] to i64
5656; CHECK-NEXT:    [[TMP43:%.*]] = mul i64 [[TMP41]], [[TMP42]]
5657; CHECK-NEXT:    [[TMP44:%.*]] = trunc i64 [[TMP43]] to i32
5658; CHECK-NEXT:    [[TMP45:%.*]] = lshr i64 [[TMP43]], 32
5659; CHECK-NEXT:    [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32
5660; CHECK-NEXT:    [[TMP47:%.*]] = add i32 [[TMP38]], [[TMP46]]
5661; CHECK-NEXT:    [[TMP48:%.*]] = zext i32 [[TMP33]] to i64
5662; CHECK-NEXT:    [[TMP49:%.*]] = zext i32 [[TMP47]] to i64
5663; CHECK-NEXT:    [[TMP50:%.*]] = mul i64 [[TMP48]], [[TMP49]]
5664; CHECK-NEXT:    [[TMP51:%.*]] = trunc i64 [[TMP50]] to i32
5665; CHECK-NEXT:    [[TMP52:%.*]] = lshr i64 [[TMP50]], 32
5666; CHECK-NEXT:    [[TMP53:%.*]] = trunc i64 [[TMP52]] to i32
5667; CHECK-NEXT:    [[TMP54:%.*]] = mul i32 [[TMP53]], [[TMP34]]
5668; CHECK-NEXT:    [[TMP55:%.*]] = sub i32 [[TMP33]], [[TMP54]]
5669; CHECK-NEXT:    [[TMP56:%.*]] = icmp uge i32 [[TMP55]], [[TMP34]]
5670; CHECK-NEXT:    [[TMP57:%.*]] = add i32 [[TMP53]], 1
5671; CHECK-NEXT:    [[TMP58:%.*]] = select i1 [[TMP56]], i32 [[TMP57]], i32 [[TMP53]]
5672; CHECK-NEXT:    [[TMP59:%.*]] = sub i32 [[TMP55]], [[TMP34]]
5673; CHECK-NEXT:    [[TMP60:%.*]] = select i1 [[TMP56]], i32 [[TMP59]], i32 [[TMP55]]
5674; CHECK-NEXT:    [[TMP61:%.*]] = icmp uge i32 [[TMP60]], [[TMP34]]
5675; CHECK-NEXT:    [[TMP62:%.*]] = add i32 [[TMP58]], 1
5676; CHECK-NEXT:    [[TMP63:%.*]] = select i1 [[TMP61]], i32 [[TMP62]], i32 [[TMP58]]
5677; CHECK-NEXT:    [[TMP64:%.*]] = insertelement <2 x i32> [[TMP32]], i32 [[TMP63]], i64 1
5678; CHECK-NEXT:    store <2 x i32> [[TMP64]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
5679; CHECK-NEXT:    ret void
5680;
5681; GFX6-LABEL: udiv_v2i32_pow2_shl_denom:
5682; GFX6:       ; %bb.0:
5683; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
5684; GFX6-NEXT:    s_movk_i32 s4, 0x1000
5685; GFX6-NEXT:    s_mov_b32 s7, 0xf000
5686; GFX6-NEXT:    s_mov_b32 s6, -1
5687; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5688; GFX6-NEXT:    s_lshl_b32 s8, s4, s2
5689; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
5690; GFX6-NEXT:    s_lshl_b32 s9, s4, s3
5691; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
5692; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
5693; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
5694; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
5695; GFX6-NEXT:    s_mov_b32 s0, 0x4f7ffffe
5696; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
5697; GFX6-NEXT:    v_mul_f32_e32 v0, s0, v0
5698; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
5699; GFX6-NEXT:    v_mul_f32_e32 v1, s0, v1
5700; GFX6-NEXT:    s_sub_i32 s0, 0, s8
5701; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
5702; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v0
5703; GFX6-NEXT:    s_sub_i32 s0, 0, s9
5704; GFX6-NEXT:    v_mul_lo_u32 v3, s0, v1
5705; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
5706; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
5707; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
5708; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5709; GFX6-NEXT:    v_mul_hi_u32 v0, s2, v0
5710; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
5711; GFX6-NEXT:    v_mul_hi_u32 v1, s3, v1
5712; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s8
5713; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
5714; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s9
5715; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s2, v2
5716; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v2
5717; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[0:1]
5718; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v2
5719; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
5720; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
5721; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
5722; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
5723; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s3, v4
5724; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
5725; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v2
5726; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
5727; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s9, v2
5728; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
5729; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
5730; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
5731; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5732; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
5733; GFX6-NEXT:    s_endpgm
5734;
5735; GFX9-LABEL: udiv_v2i32_pow2_shl_denom:
5736; GFX9:       ; %bb.0:
5737; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
5738; GFX9-NEXT:    s_movk_i32 s4, 0x1000
5739; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5740; GFX9-NEXT:    s_lshl_b32 s7, s4, s2
5741; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s7
5742; GFX9-NEXT:    s_lshl_b32 s6, s4, s3
5743; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s6
5744; GFX9-NEXT:    s_mov_b32 s2, 0x4f7ffffe
5745; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
5746; GFX9-NEXT:    s_sub_i32 s3, 0, s6
5747; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
5748; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
5749; GFX9-NEXT:    v_mul_f32_e32 v0, s2, v0
5750; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
5751; GFX9-NEXT:    v_mul_f32_e32 v1, s2, v1
5752; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
5753; GFX9-NEXT:    s_sub_i32 s2, 0, s7
5754; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v0
5755; GFX9-NEXT:    v_mul_lo_u32 v3, s3, v1
5756; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
5757; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
5758; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
5759; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
5760; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5761; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
5762; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
5763; GFX9-NEXT:    v_mul_hi_u32 v1, s3, v1
5764; GFX9-NEXT:    v_mov_b32_e32 v2, 0
5765; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s7
5766; GFX9-NEXT:    v_add_u32_e32 v5, 1, v0
5767; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s6
5768; GFX9-NEXT:    v_add_u32_e32 v6, 1, v1
5769; GFX9-NEXT:    v_sub_u32_e32 v3, s2, v3
5770; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v3
5771; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
5772; GFX9-NEXT:    v_subrev_u32_e32 v5, s7, v3
5773; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
5774; GFX9-NEXT:    v_sub_u32_e32 v4, s3, v4
5775; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s6, v4
5776; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v3
5777; GFX9-NEXT:    v_subrev_u32_e32 v3, s6, v4
5778; GFX9-NEXT:    v_add_u32_e32 v5, 1, v0
5779; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v6, s[0:1]
5780; GFX9-NEXT:    v_cndmask_b32_e64 v3, v4, v3, s[0:1]
5781; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
5782; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
5783; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s6, v3
5784; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
5785; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
5786; GFX9-NEXT:    s_endpgm
5787  %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
5788  %r = udiv <2 x i32> %x, %shl.y
5789  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
5790  ret void
5791}
5792
5793define amdgpu_kernel void @urem_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
5794; CHECK-LABEL: @urem_i32_oddk_denom(
5795; CHECK-NEXT:    [[R:%.*]] = urem i32 [[X:%.*]], 1235195
5796; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
5797; CHECK-NEXT:    ret void
5798;
5799; GFX6-LABEL: urem_i32_oddk_denom:
5800; GFX6:       ; %bb.0:
5801; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
5802; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
5803; GFX6-NEXT:    v_mov_b32_e32 v0, 0xb2a50881
5804; GFX6-NEXT:    s_mov_b32 s7, 0xf000
5805; GFX6-NEXT:    s_mov_b32 s6, -1
5806; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5807; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
5808; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s0, v0
5809; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
5810; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
5811; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 20, v0
5812; GFX6-NEXT:    v_mul_u32_u24_e32 v0, 0x12d8fb, v0
5813; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
5814; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
5815; GFX6-NEXT:    s_endpgm
5816;
5817; GFX9-LABEL: urem_i32_oddk_denom:
5818; GFX9:       ; %bb.0:
5819; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
5820; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
5821; GFX9-NEXT:    v_mov_b32_e32 v1, 0x12d8fb
5822; GFX9-NEXT:    v_mov_b32_e32 v0, 0
5823; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5824; GFX9-NEXT:    s_mul_hi_u32 s0, s4, 0xb2a50881
5825; GFX9-NEXT:    s_sub_i32 s1, s4, s0
5826; GFX9-NEXT:    s_lshr_b32 s1, s1, 1
5827; GFX9-NEXT:    s_add_i32 s1, s1, s0
5828; GFX9-NEXT:    s_lshr_b32 s0, s1, 20
5829; GFX9-NEXT:    v_mul_u32_u24_e32 v1, s0, v1
5830; GFX9-NEXT:    v_sub_u32_e32 v1, s4, v1
5831; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
5832; GFX9-NEXT:    s_endpgm
5833  %r = urem i32 %x, 1235195
5834  store i32 %r, i32 addrspace(1)* %out
5835  ret void
5836}
5837
5838define amdgpu_kernel void @urem_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x) {
5839; CHECK-LABEL: @urem_i32_pow2k_denom(
5840; CHECK-NEXT:    [[R:%.*]] = urem i32 [[X:%.*]], 4096
5841; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
5842; CHECK-NEXT:    ret void
5843;
5844; GFX6-LABEL: urem_i32_pow2k_denom:
5845; GFX6:       ; %bb.0:
5846; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
5847; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
5848; GFX6-NEXT:    s_mov_b32 s7, 0xf000
5849; GFX6-NEXT:    s_mov_b32 s6, -1
5850; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5851; GFX6-NEXT:    s_and_b32 s0, s0, 0xfff
5852; GFX6-NEXT:    v_mov_b32_e32 v0, s0
5853; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
5854; GFX6-NEXT:    s_endpgm
5855;
5856; GFX9-LABEL: urem_i32_pow2k_denom:
5857; GFX9:       ; %bb.0:
5858; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
5859; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
5860; GFX9-NEXT:    v_mov_b32_e32 v0, 0
5861; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5862; GFX9-NEXT:    s_and_b32 s0, s4, 0xfff
5863; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5864; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
5865; GFX9-NEXT:    s_endpgm
5866  %r = urem i32 %x, 4096
5867  store i32 %r, i32 addrspace(1)* %out
5868  ret void
5869}
5870
5871define amdgpu_kernel void @urem_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %x, i32 %y) {
5872; CHECK-LABEL: @urem_i32_pow2_shl_denom(
5873; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]]
5874; CHECK-NEXT:    [[R:%.*]] = urem i32 [[X:%.*]], [[SHL_Y]]
5875; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
5876; CHECK-NEXT:    ret void
5877;
5878; GFX6-LABEL: urem_i32_pow2_shl_denom:
5879; GFX6:       ; %bb.0:
5880; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
5881; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
5882; GFX6-NEXT:    s_mov_b32 s7, 0xf000
5883; GFX6-NEXT:    s_mov_b32 s6, -1
5884; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5885; GFX6-NEXT:    s_lshl_b32 s1, 0x1000, s1
5886; GFX6-NEXT:    s_add_i32 s1, s1, -1
5887; GFX6-NEXT:    s_and_b32 s0, s0, s1
5888; GFX6-NEXT:    v_mov_b32_e32 v0, s0
5889; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
5890; GFX6-NEXT:    s_endpgm
5891;
5892; GFX9-LABEL: urem_i32_pow2_shl_denom:
5893; GFX9:       ; %bb.0:
5894; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
5895; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
5896; GFX9-NEXT:    v_mov_b32_e32 v0, 0
5897; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5898; GFX9-NEXT:    s_lshl_b32 s0, 0x1000, s5
5899; GFX9-NEXT:    s_add_i32 s0, s0, -1
5900; GFX9-NEXT:    s_and_b32 s0, s4, s0
5901; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5902; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
5903; GFX9-NEXT:    s_endpgm
5904  %shl.y = shl i32 4096, %y
5905  %r = urem i32 %x, %shl.y
5906  store i32 %r, i32 addrspace(1)* %out
5907  ret void
5908}
5909
5910define amdgpu_kernel void @urem_v2i32_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) {
5911; CHECK-LABEL: @urem_v2i32_pow2k_denom(
5912; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
5913; CHECK-NEXT:    [[TMP2:%.*]] = urem i32 [[TMP1]], 4096
5914; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0
5915; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1
5916; CHECK-NEXT:    [[TMP5:%.*]] = urem i32 [[TMP4]], 4096
5917; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1
5918; CHECK-NEXT:    store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
5919; CHECK-NEXT:    ret void
5920;
5921; GFX6-LABEL: urem_v2i32_pow2k_denom:
5922; GFX6:       ; %bb.0:
5923; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
5924; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
5925; GFX6-NEXT:    s_movk_i32 s2, 0xfff
5926; GFX6-NEXT:    s_mov_b32 s7, 0xf000
5927; GFX6-NEXT:    s_mov_b32 s6, -1
5928; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5929; GFX6-NEXT:    s_and_b32 s0, s0, s2
5930; GFX6-NEXT:    s_and_b32 s1, s1, s2
5931; GFX6-NEXT:    v_mov_b32_e32 v0, s0
5932; GFX6-NEXT:    v_mov_b32_e32 v1, s1
5933; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
5934; GFX6-NEXT:    s_endpgm
5935;
5936; GFX9-LABEL: urem_v2i32_pow2k_denom:
5937; GFX9:       ; %bb.0:
5938; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
5939; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
5940; GFX9-NEXT:    s_movk_i32 s0, 0xfff
5941; GFX9-NEXT:    v_mov_b32_e32 v2, 0
5942; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5943; GFX9-NEXT:    s_and_b32 s1, s4, s0
5944; GFX9-NEXT:    s_and_b32 s0, s5, s0
5945; GFX9-NEXT:    v_mov_b32_e32 v0, s1
5946; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5947; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
5948; GFX9-NEXT:    s_endpgm
5949  %r = urem <2 x i32> %x, <i32 4096, i32 4096>
5950  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
5951  ret void
5952}
5953
5954define amdgpu_kernel void @urem_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) {
5955; CHECK-LABEL: @urem_v2i32_pow2_shl_denom(
5956; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i32> <i32 4096, i32 4096>, [[Y:%.*]]
5957; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
5958; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 0
5959; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float
5960; CHECK-NEXT:    [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])
5961; CHECK-NEXT:    [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41EFFFFFC0000000
5962; CHECK-NEXT:    [[TMP6:%.*]] = fptoui float [[TMP5]] to i32
5963; CHECK-NEXT:    [[TMP7:%.*]] = sub i32 0, [[TMP2]]
5964; CHECK-NEXT:    [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP6]]
5965; CHECK-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP6]] to i64
5966; CHECK-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP8]] to i64
5967; CHECK-NEXT:    [[TMP11:%.*]] = mul i64 [[TMP9]], [[TMP10]]
5968; CHECK-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
5969; CHECK-NEXT:    [[TMP13:%.*]] = lshr i64 [[TMP11]], 32
5970; CHECK-NEXT:    [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32
5971; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP6]], [[TMP14]]
5972; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP1]] to i64
5973; CHECK-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP15]] to i64
5974; CHECK-NEXT:    [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]
5975; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
5976; CHECK-NEXT:    [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
5977; CHECK-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
5978; CHECK-NEXT:    [[TMP22:%.*]] = mul i32 [[TMP21]], [[TMP2]]
5979; CHECK-NEXT:    [[TMP23:%.*]] = sub i32 [[TMP1]], [[TMP22]]
5980; CHECK-NEXT:    [[TMP24:%.*]] = icmp uge i32 [[TMP23]], [[TMP2]]
5981; CHECK-NEXT:    [[TMP25:%.*]] = sub i32 [[TMP23]], [[TMP2]]
5982; CHECK-NEXT:    [[TMP26:%.*]] = select i1 [[TMP24]], i32 [[TMP25]], i32 [[TMP23]]
5983; CHECK-NEXT:    [[TMP27:%.*]] = icmp uge i32 [[TMP26]], [[TMP2]]
5984; CHECK-NEXT:    [[TMP28:%.*]] = sub i32 [[TMP26]], [[TMP2]]
5985; CHECK-NEXT:    [[TMP29:%.*]] = select i1 [[TMP27]], i32 [[TMP28]], i32 [[TMP26]]
5986; CHECK-NEXT:    [[TMP30:%.*]] = insertelement <2 x i32> undef, i32 [[TMP29]], i64 0
5987; CHECK-NEXT:    [[TMP31:%.*]] = extractelement <2 x i32> [[X]], i64 1
5988; CHECK-NEXT:    [[TMP32:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1
5989; CHECK-NEXT:    [[TMP33:%.*]] = uitofp i32 [[TMP32]] to float
5990; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])
5991; CHECK-NEXT:    [[TMP35:%.*]] = fmul fast float [[TMP34]], 0x41EFFFFFC0000000
5992; CHECK-NEXT:    [[TMP36:%.*]] = fptoui float [[TMP35]] to i32
5993; CHECK-NEXT:    [[TMP37:%.*]] = sub i32 0, [[TMP32]]
5994; CHECK-NEXT:    [[TMP38:%.*]] = mul i32 [[TMP37]], [[TMP36]]
5995; CHECK-NEXT:    [[TMP39:%.*]] = zext i32 [[TMP36]] to i64
5996; CHECK-NEXT:    [[TMP40:%.*]] = zext i32 [[TMP38]] to i64
5997; CHECK-NEXT:    [[TMP41:%.*]] = mul i64 [[TMP39]], [[TMP40]]
5998; CHECK-NEXT:    [[TMP42:%.*]] = trunc i64 [[TMP41]] to i32
5999; CHECK-NEXT:    [[TMP43:%.*]] = lshr i64 [[TMP41]], 32
6000; CHECK-NEXT:    [[TMP44:%.*]] = trunc i64 [[TMP43]] to i32
6001; CHECK-NEXT:    [[TMP45:%.*]] = add i32 [[TMP36]], [[TMP44]]
6002; CHECK-NEXT:    [[TMP46:%.*]] = zext i32 [[TMP31]] to i64
6003; CHECK-NEXT:    [[TMP47:%.*]] = zext i32 [[TMP45]] to i64
6004; CHECK-NEXT:    [[TMP48:%.*]] = mul i64 [[TMP46]], [[TMP47]]
6005; CHECK-NEXT:    [[TMP49:%.*]] = trunc i64 [[TMP48]] to i32
6006; CHECK-NEXT:    [[TMP50:%.*]] = lshr i64 [[TMP48]], 32
6007; CHECK-NEXT:    [[TMP51:%.*]] = trunc i64 [[TMP50]] to i32
6008; CHECK-NEXT:    [[TMP52:%.*]] = mul i32 [[TMP51]], [[TMP32]]
6009; CHECK-NEXT:    [[TMP53:%.*]] = sub i32 [[TMP31]], [[TMP52]]
6010; CHECK-NEXT:    [[TMP54:%.*]] = icmp uge i32 [[TMP53]], [[TMP32]]
6011; CHECK-NEXT:    [[TMP55:%.*]] = sub i32 [[TMP53]], [[TMP32]]
6012; CHECK-NEXT:    [[TMP56:%.*]] = select i1 [[TMP54]], i32 [[TMP55]], i32 [[TMP53]]
6013; CHECK-NEXT:    [[TMP57:%.*]] = icmp uge i32 [[TMP56]], [[TMP32]]
6014; CHECK-NEXT:    [[TMP58:%.*]] = sub i32 [[TMP56]], [[TMP32]]
6015; CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP57]], i32 [[TMP58]], i32 [[TMP56]]
6016; CHECK-NEXT:    [[TMP60:%.*]] = insertelement <2 x i32> [[TMP30]], i32 [[TMP59]], i64 1
6017; CHECK-NEXT:    store <2 x i32> [[TMP60]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
6018; CHECK-NEXT:    ret void
6019;
6020; GFX6-LABEL: urem_v2i32_pow2_shl_denom:
6021; GFX6:       ; %bb.0:
6022; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
6023; GFX6-NEXT:    s_movk_i32 s4, 0x1000
6024; GFX6-NEXT:    s_mov_b32 s7, 0xf000
6025; GFX6-NEXT:    s_mov_b32 s6, -1
6026; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6027; GFX6-NEXT:    s_lshl_b32 s8, s4, s2
6028; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
6029; GFX6-NEXT:    s_lshl_b32 s3, s4, s3
6030; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s3
6031; GFX6-NEXT:    s_mov_b32 s4, 0x4f7ffffe
6032; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6033; GFX6-NEXT:    s_sub_i32 s2, 0, s8
6034; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
6035; GFX6-NEXT:    v_mul_f32_e32 v0, s4, v0
6036; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
6037; GFX6-NEXT:    v_mul_f32_e32 v1, s4, v1
6038; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
6039; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
6040; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
6041; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
6042; GFX6-NEXT:    s_sub_i32 s2, 0, s3
6043; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v1
6044; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
6045; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
6046; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
6047; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6048; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
6049; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
6050; GFX6-NEXT:    v_mul_hi_u32 v1, s1, v1
6051; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s8
6052; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s3
6053; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
6054; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v0
6055; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
6056; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
6057; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v0
6058; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
6059; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
6060; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v1
6061; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v1
6062; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
6063; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
6064; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v1
6065; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
6066; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
6067; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
6068; GFX6-NEXT:    s_endpgm
6069;
6070; GFX9-LABEL: urem_v2i32_pow2_shl_denom:
6071; GFX9:       ; %bb.0:
6072; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
6073; GFX9-NEXT:    s_movk_i32 s4, 0x1000
6074; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6075; GFX9-NEXT:    s_lshl_b32 s5, s4, s3
6076; GFX9-NEXT:    s_lshl_b32 s4, s4, s2
6077; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s4
6078; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s5
6079; GFX9-NEXT:    s_mov_b32 s2, 0x4f7ffffe
6080; GFX9-NEXT:    s_sub_i32 s3, 0, s5
6081; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6082; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
6083; GFX9-NEXT:    v_mul_f32_e32 v0, s2, v0
6084; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
6085; GFX9-NEXT:    v_mul_f32_e32 v1, s2, v1
6086; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
6087; GFX9-NEXT:    s_sub_i32 s2, 0, s4
6088; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v0
6089; GFX9-NEXT:    v_mul_lo_u32 v3, s3, v1
6090; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
6091; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
6092; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
6093; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
6094; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
6095; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6096; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
6097; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
6098; GFX9-NEXT:    v_mul_hi_u32 v1, s3, v1
6099; GFX9-NEXT:    v_mov_b32_e32 v2, 0
6100; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s4
6101; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s5
6102; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
6103; GFX9-NEXT:    v_subrev_u32_e32 v3, s4, v0
6104; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v0
6105; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
6106; GFX9-NEXT:    v_sub_u32_e32 v1, s3, v1
6107; GFX9-NEXT:    v_subrev_u32_e32 v3, s4, v0
6108; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v0
6109; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
6110; GFX9-NEXT:    v_subrev_u32_e32 v4, s5, v1
6111; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v1
6112; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
6113; GFX9-NEXT:    v_subrev_u32_e32 v3, s5, v1
6114; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v1
6115; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
6116; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
6117; GFX9-NEXT:    s_endpgm
6118  %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
6119  %r = urem <2 x i32> %x, %shl.y
6120  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
6121  ret void
6122}
6123
6124define amdgpu_kernel void @sdiv_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
6125; CHECK-LABEL: @sdiv_i32_oddk_denom(
6126; CHECK-NEXT:    [[R:%.*]] = sdiv i32 [[X:%.*]], 1235195
6127; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
6128; CHECK-NEXT:    ret void
6129;
6130; GFX6-LABEL: sdiv_i32_oddk_denom:
6131; GFX6:       ; %bb.0:
6132; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
6133; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
6134; GFX6-NEXT:    v_mov_b32_e32 v0, 0xd9528441
6135; GFX6-NEXT:    s_mov_b32 s7, 0xf000
6136; GFX6-NEXT:    s_mov_b32 s6, -1
6137; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6138; GFX6-NEXT:    v_mul_hi_i32 v0, s0, v0
6139; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s0, v0
6140; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 31, v0
6141; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 20, v0
6142; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
6143; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
6144; GFX6-NEXT:    s_endpgm
6145;
6146; GFX9-LABEL: sdiv_i32_oddk_denom:
6147; GFX9:       ; %bb.0:
6148; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
6149; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
6150; GFX9-NEXT:    v_mov_b32_e32 v0, 0
6151; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6152; GFX9-NEXT:    s_mul_hi_i32 s0, s4, 0xd9528441
6153; GFX9-NEXT:    s_add_i32 s0, s0, s4
6154; GFX9-NEXT:    s_lshr_b32 s1, s0, 31
6155; GFX9-NEXT:    s_ashr_i32 s0, s0, 20
6156; GFX9-NEXT:    s_add_i32 s0, s0, s1
6157; GFX9-NEXT:    v_mov_b32_e32 v1, s0
6158; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
6159; GFX9-NEXT:    s_endpgm
6160  %r = sdiv i32 %x, 1235195
6161  store i32 %r, i32 addrspace(1)* %out
6162  ret void
6163}
6164
6165define amdgpu_kernel void @sdiv_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x) {
6166; CHECK-LABEL: @sdiv_i32_pow2k_denom(
6167; CHECK-NEXT:    [[R:%.*]] = sdiv i32 [[X:%.*]], 4096
6168; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
6169; CHECK-NEXT:    ret void
6170;
6171; GFX6-LABEL: sdiv_i32_pow2k_denom:
6172; GFX6:       ; %bb.0:
6173; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
6174; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
6175; GFX6-NEXT:    s_mov_b32 s7, 0xf000
6176; GFX6-NEXT:    s_mov_b32 s6, -1
6177; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6178; GFX6-NEXT:    s_ashr_i32 s1, s0, 31
6179; GFX6-NEXT:    s_lshr_b32 s1, s1, 20
6180; GFX6-NEXT:    s_add_i32 s0, s0, s1
6181; GFX6-NEXT:    s_ashr_i32 s0, s0, 12
6182; GFX6-NEXT:    v_mov_b32_e32 v0, s0
6183; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
6184; GFX6-NEXT:    s_endpgm
6185;
6186; GFX9-LABEL: sdiv_i32_pow2k_denom:
6187; GFX9:       ; %bb.0:
6188; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
6189; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
6190; GFX9-NEXT:    v_mov_b32_e32 v0, 0
6191; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6192; GFX9-NEXT:    s_ashr_i32 s0, s4, 31
6193; GFX9-NEXT:    s_lshr_b32 s0, s0, 20
6194; GFX9-NEXT:    s_add_i32 s4, s4, s0
6195; GFX9-NEXT:    s_ashr_i32 s0, s4, 12
6196; GFX9-NEXT:    v_mov_b32_e32 v1, s0
6197; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
6198; GFX9-NEXT:    s_endpgm
6199  %r = sdiv i32 %x, 4096
6200  store i32 %r, i32 addrspace(1)* %out
6201  ret void
6202}
6203
6204define amdgpu_kernel void @sdiv_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %x, i32 %y) {
6205; CHECK-LABEL: @sdiv_i32_pow2_shl_denom(
6206; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]]
6207; CHECK-NEXT:    [[R:%.*]] = sdiv i32 [[X:%.*]], [[SHL_Y]]
6208; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
6209; CHECK-NEXT:    ret void
6210;
6211; GFX6-LABEL: sdiv_i32_pow2_shl_denom:
6212; GFX6:       ; %bb.0:
6213; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
6214; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6215; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6216; GFX6-NEXT:    s_lshl_b32 s3, 0x1000, s3
6217; GFX6-NEXT:    s_ashr_i32 s4, s3, 31
6218; GFX6-NEXT:    s_add_i32 s3, s3, s4
6219; GFX6-NEXT:    s_xor_b32 s7, s3, s4
6220; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s7
6221; GFX6-NEXT:    s_sub_i32 s3, 0, s7
6222; GFX6-NEXT:    s_ashr_i32 s5, s2, 31
6223; GFX6-NEXT:    s_add_i32 s2, s2, s5
6224; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6225; GFX6-NEXT:    s_xor_b32 s6, s2, s5
6226; GFX6-NEXT:    s_xor_b32 s4, s5, s4
6227; GFX6-NEXT:    s_mov_b32 s2, -1
6228; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
6229; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
6230; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v0
6231; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6232; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
6233; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
6234; GFX6-NEXT:    v_mul_hi_u32 v0, s6, v0
6235; GFX6-NEXT:    v_mul_lo_u32 v1, v0, s7
6236; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
6237; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s6, v1
6238; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s7, v1
6239; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
6240; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
6241; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
6242; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
6243; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
6244; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
6245; GFX6-NEXT:    v_xor_b32_e32 v0, s4, v0
6246; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s4, v0
6247; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
6248; GFX6-NEXT:    s_endpgm
6249;
6250; GFX9-LABEL: sdiv_i32_pow2_shl_denom:
6251; GFX9:       ; %bb.0:
6252; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
6253; GFX9-NEXT:    v_mov_b32_e32 v2, 0
6254; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
6255; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6256; GFX9-NEXT:    s_lshl_b32 s3, 0x1000, s3
6257; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
6258; GFX9-NEXT:    s_add_i32 s3, s3, s4
6259; GFX9-NEXT:    s_xor_b32 s5, s3, s4
6260; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s5
6261; GFX9-NEXT:    s_sub_i32 s3, 0, s5
6262; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6263; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
6264; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
6265; GFX9-NEXT:    v_mul_lo_u32 v1, s3, v0
6266; GFX9-NEXT:    s_ashr_i32 s3, s2, 31
6267; GFX9-NEXT:    s_add_i32 s2, s2, s3
6268; GFX9-NEXT:    s_xor_b32 s2, s2, s3
6269; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
6270; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
6271; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
6272; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s5
6273; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
6274; GFX9-NEXT:    v_sub_u32_e32 v1, s2, v1
6275; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v1
6276; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
6277; GFX9-NEXT:    v_subrev_u32_e32 v3, s5, v1
6278; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
6279; GFX9-NEXT:    v_add_u32_e32 v4, 1, v0
6280; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v1
6281; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
6282; GFX9-NEXT:    s_xor_b32 s2, s3, s4
6283; GFX9-NEXT:    v_xor_b32_e32 v0, s2, v0
6284; GFX9-NEXT:    v_subrev_u32_e32 v0, s2, v0
6285; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]
6286; GFX9-NEXT:    s_endpgm
6287  %shl.y = shl i32 4096, %y
6288  %r = sdiv i32 %x, %shl.y
6289  store i32 %r, i32 addrspace(1)* %out
6290  ret void
6291}
6292
6293define amdgpu_kernel void @sdiv_v2i32_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) {
6294; CHECK-LABEL: @sdiv_v2i32_pow2k_denom(
6295; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
6296; CHECK-NEXT:    [[TMP2:%.*]] = sdiv i32 [[TMP1]], 4096
6297; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0
6298; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1
6299; CHECK-NEXT:    [[TMP5:%.*]] = sdiv i32 [[TMP4]], 4096
6300; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1
6301; CHECK-NEXT:    store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
6302; CHECK-NEXT:    ret void
6303;
6304; GFX6-LABEL: sdiv_v2i32_pow2k_denom:
6305; GFX6:       ; %bb.0:
6306; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
6307; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
6308; GFX6-NEXT:    s_mov_b32 s7, 0xf000
6309; GFX6-NEXT:    s_mov_b32 s6, -1
6310; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6311; GFX6-NEXT:    s_ashr_i32 s2, s0, 31
6312; GFX6-NEXT:    s_lshr_b32 s2, s2, 20
6313; GFX6-NEXT:    s_ashr_i32 s3, s1, 31
6314; GFX6-NEXT:    s_add_i32 s0, s0, s2
6315; GFX6-NEXT:    s_lshr_b32 s2, s3, 20
6316; GFX6-NEXT:    s_add_i32 s1, s1, s2
6317; GFX6-NEXT:    s_ashr_i32 s0, s0, 12
6318; GFX6-NEXT:    s_ashr_i32 s1, s1, 12
6319; GFX6-NEXT:    v_mov_b32_e32 v0, s0
6320; GFX6-NEXT:    v_mov_b32_e32 v1, s1
6321; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
6322; GFX6-NEXT:    s_endpgm
6323;
6324; GFX9-LABEL: sdiv_v2i32_pow2k_denom:
6325; GFX9:       ; %bb.0:
6326; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
6327; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
6328; GFX9-NEXT:    v_mov_b32_e32 v2, 0
6329; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6330; GFX9-NEXT:    s_ashr_i32 s0, s4, 31
6331; GFX9-NEXT:    s_ashr_i32 s1, s5, 31
6332; GFX9-NEXT:    s_lshr_b32 s0, s0, 20
6333; GFX9-NEXT:    s_lshr_b32 s1, s1, 20
6334; GFX9-NEXT:    s_add_i32 s0, s4, s0
6335; GFX9-NEXT:    s_add_i32 s1, s5, s1
6336; GFX9-NEXT:    s_ashr_i32 s0, s0, 12
6337; GFX9-NEXT:    s_ashr_i32 s1, s1, 12
6338; GFX9-NEXT:    v_mov_b32_e32 v0, s0
6339; GFX9-NEXT:    v_mov_b32_e32 v1, s1
6340; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
6341; GFX9-NEXT:    s_endpgm
6342  %r = sdiv <2 x i32> %x, <i32 4096, i32 4096>
6343  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
6344  ret void
6345}
6346
6347define amdgpu_kernel void @ssdiv_v2i32_mixed_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) {
6348; CHECK-LABEL: @ssdiv_v2i32_mixed_pow2k_denom(
6349; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
6350; CHECK-NEXT:    [[TMP2:%.*]] = sdiv i32 [[TMP1]], 4096
6351; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0
6352; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1
6353; CHECK-NEXT:    [[TMP5:%.*]] = sdiv i32 [[TMP4]], 4095
6354; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1
6355; CHECK-NEXT:    store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
6356; CHECK-NEXT:    ret void
6357;
6358; GFX6-LABEL: ssdiv_v2i32_mixed_pow2k_denom:
6359; GFX6:       ; %bb.0:
6360; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
6361; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
6362; GFX6-NEXT:    v_mov_b32_e32 v0, 0x80080081
6363; GFX6-NEXT:    s_mov_b32 s7, 0xf000
6364; GFX6-NEXT:    s_mov_b32 s6, -1
6365; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6366; GFX6-NEXT:    v_mul_hi_i32 v0, s1, v0
6367; GFX6-NEXT:    s_ashr_i32 s2, s0, 31
6368; GFX6-NEXT:    s_lshr_b32 s2, s2, 20
6369; GFX6-NEXT:    s_add_i32 s0, s0, s2
6370; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s1, v0
6371; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 31, v0
6372; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 11, v0
6373; GFX6-NEXT:    s_ashr_i32 s0, s0, 12
6374; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v0
6375; GFX6-NEXT:    v_mov_b32_e32 v0, s0
6376; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
6377; GFX6-NEXT:    s_endpgm
6378;
6379; GFX9-LABEL: ssdiv_v2i32_mixed_pow2k_denom:
6380; GFX9:       ; %bb.0:
6381; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
6382; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
6383; GFX9-NEXT:    v_mov_b32_e32 v2, 0
6384; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6385; GFX9-NEXT:    s_ashr_i32 s0, s4, 31
6386; GFX9-NEXT:    s_mul_hi_i32 s1, s5, 0x80080081
6387; GFX9-NEXT:    s_lshr_b32 s0, s0, 20
6388; GFX9-NEXT:    s_add_i32 s1, s1, s5
6389; GFX9-NEXT:    s_add_i32 s0, s4, s0
6390; GFX9-NEXT:    s_lshr_b32 s4, s1, 31
6391; GFX9-NEXT:    s_ashr_i32 s1, s1, 11
6392; GFX9-NEXT:    s_ashr_i32 s0, s0, 12
6393; GFX9-NEXT:    s_add_i32 s1, s1, s4
6394; GFX9-NEXT:    v_mov_b32_e32 v0, s0
6395; GFX9-NEXT:    v_mov_b32_e32 v1, s1
6396; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
6397; GFX9-NEXT:    s_endpgm
6398  %r = sdiv <2 x i32> %x, <i32 4096, i32 4095>
6399  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
6400  ret void
6401}
6402
6403define amdgpu_kernel void @sdiv_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) {
6404; CHECK-LABEL: @sdiv_v2i32_pow2_shl_denom(
6405; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i32> <i32 4096, i32 4096>, [[Y:%.*]]
6406; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
6407; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 0
6408; CHECK-NEXT:    [[TMP3:%.*]] = ashr i32 [[TMP1]], 31
6409; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP2]], 31
6410; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
6411; CHECK-NEXT:    [[TMP6:%.*]] = add i32 [[TMP1]], [[TMP3]]
6412; CHECK-NEXT:    [[TMP7:%.*]] = add i32 [[TMP2]], [[TMP4]]
6413; CHECK-NEXT:    [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP3]]
6414; CHECK-NEXT:    [[TMP9:%.*]] = xor i32 [[TMP7]], [[TMP4]]
6415; CHECK-NEXT:    [[TMP10:%.*]] = uitofp i32 [[TMP9]] to float
6416; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP10]])
6417; CHECK-NEXT:    [[TMP12:%.*]] = fmul fast float [[TMP11]], 0x41EFFFFFC0000000
6418; CHECK-NEXT:    [[TMP13:%.*]] = fptoui float [[TMP12]] to i32
6419; CHECK-NEXT:    [[TMP14:%.*]] = sub i32 0, [[TMP9]]
6420; CHECK-NEXT:    [[TMP15:%.*]] = mul i32 [[TMP14]], [[TMP13]]
6421; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP13]] to i64
6422; CHECK-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP15]] to i64
6423; CHECK-NEXT:    [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]
6424; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
6425; CHECK-NEXT:    [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
6426; CHECK-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
6427; CHECK-NEXT:    [[TMP22:%.*]] = add i32 [[TMP13]], [[TMP21]]
6428; CHECK-NEXT:    [[TMP23:%.*]] = zext i32 [[TMP8]] to i64
6429; CHECK-NEXT:    [[TMP24:%.*]] = zext i32 [[TMP22]] to i64
6430; CHECK-NEXT:    [[TMP25:%.*]] = mul i64 [[TMP23]], [[TMP24]]
6431; CHECK-NEXT:    [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32
6432; CHECK-NEXT:    [[TMP27:%.*]] = lshr i64 [[TMP25]], 32
6433; CHECK-NEXT:    [[TMP28:%.*]] = trunc i64 [[TMP27]] to i32
6434; CHECK-NEXT:    [[TMP29:%.*]] = mul i32 [[TMP28]], [[TMP9]]
6435; CHECK-NEXT:    [[TMP30:%.*]] = sub i32 [[TMP8]], [[TMP29]]
6436; CHECK-NEXT:    [[TMP31:%.*]] = icmp uge i32 [[TMP30]], [[TMP9]]
6437; CHECK-NEXT:    [[TMP32:%.*]] = add i32 [[TMP28]], 1
6438; CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP31]], i32 [[TMP32]], i32 [[TMP28]]
6439; CHECK-NEXT:    [[TMP34:%.*]] = sub i32 [[TMP30]], [[TMP9]]
6440; CHECK-NEXT:    [[TMP35:%.*]] = select i1 [[TMP31]], i32 [[TMP34]], i32 [[TMP30]]
6441; CHECK-NEXT:    [[TMP36:%.*]] = icmp uge i32 [[TMP35]], [[TMP9]]
6442; CHECK-NEXT:    [[TMP37:%.*]] = add i32 [[TMP33]], 1
6443; CHECK-NEXT:    [[TMP38:%.*]] = select i1 [[TMP36]], i32 [[TMP37]], i32 [[TMP33]]
6444; CHECK-NEXT:    [[TMP39:%.*]] = xor i32 [[TMP38]], [[TMP5]]
6445; CHECK-NEXT:    [[TMP40:%.*]] = sub i32 [[TMP39]], [[TMP5]]
6446; CHECK-NEXT:    [[TMP41:%.*]] = insertelement <2 x i32> undef, i32 [[TMP40]], i64 0
6447; CHECK-NEXT:    [[TMP42:%.*]] = extractelement <2 x i32> [[X]], i64 1
6448; CHECK-NEXT:    [[TMP43:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1
6449; CHECK-NEXT:    [[TMP44:%.*]] = ashr i32 [[TMP42]], 31
6450; CHECK-NEXT:    [[TMP45:%.*]] = ashr i32 [[TMP43]], 31
6451; CHECK-NEXT:    [[TMP46:%.*]] = xor i32 [[TMP44]], [[TMP45]]
6452; CHECK-NEXT:    [[TMP47:%.*]] = add i32 [[TMP42]], [[TMP44]]
6453; CHECK-NEXT:    [[TMP48:%.*]] = add i32 [[TMP43]], [[TMP45]]
6454; CHECK-NEXT:    [[TMP49:%.*]] = xor i32 [[TMP47]], [[TMP44]]
6455; CHECK-NEXT:    [[TMP50:%.*]] = xor i32 [[TMP48]], [[TMP45]]
6456; CHECK-NEXT:    [[TMP51:%.*]] = uitofp i32 [[TMP50]] to float
6457; CHECK-NEXT:    [[TMP52:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP51]])
6458; CHECK-NEXT:    [[TMP53:%.*]] = fmul fast float [[TMP52]], 0x41EFFFFFC0000000
6459; CHECK-NEXT:    [[TMP54:%.*]] = fptoui float [[TMP53]] to i32
6460; CHECK-NEXT:    [[TMP55:%.*]] = sub i32 0, [[TMP50]]
6461; CHECK-NEXT:    [[TMP56:%.*]] = mul i32 [[TMP55]], [[TMP54]]
6462; CHECK-NEXT:    [[TMP57:%.*]] = zext i32 [[TMP54]] to i64
6463; CHECK-NEXT:    [[TMP58:%.*]] = zext i32 [[TMP56]] to i64
6464; CHECK-NEXT:    [[TMP59:%.*]] = mul i64 [[TMP57]], [[TMP58]]
6465; CHECK-NEXT:    [[TMP60:%.*]] = trunc i64 [[TMP59]] to i32
6466; CHECK-NEXT:    [[TMP61:%.*]] = lshr i64 [[TMP59]], 32
6467; CHECK-NEXT:    [[TMP62:%.*]] = trunc i64 [[TMP61]] to i32
6468; CHECK-NEXT:    [[TMP63:%.*]] = add i32 [[TMP54]], [[TMP62]]
6469; CHECK-NEXT:    [[TMP64:%.*]] = zext i32 [[TMP49]] to i64
6470; CHECK-NEXT:    [[TMP65:%.*]] = zext i32 [[TMP63]] to i64
6471; CHECK-NEXT:    [[TMP66:%.*]] = mul i64 [[TMP64]], [[TMP65]]
6472; CHECK-NEXT:    [[TMP67:%.*]] = trunc i64 [[TMP66]] to i32
6473; CHECK-NEXT:    [[TMP68:%.*]] = lshr i64 [[TMP66]], 32
6474; CHECK-NEXT:    [[TMP69:%.*]] = trunc i64 [[TMP68]] to i32
6475; CHECK-NEXT:    [[TMP70:%.*]] = mul i32 [[TMP69]], [[TMP50]]
6476; CHECK-NEXT:    [[TMP71:%.*]] = sub i32 [[TMP49]], [[TMP70]]
6477; CHECK-NEXT:    [[TMP72:%.*]] = icmp uge i32 [[TMP71]], [[TMP50]]
6478; CHECK-NEXT:    [[TMP73:%.*]] = add i32 [[TMP69]], 1
6479; CHECK-NEXT:    [[TMP74:%.*]] = select i1 [[TMP72]], i32 [[TMP73]], i32 [[TMP69]]
6480; CHECK-NEXT:    [[TMP75:%.*]] = sub i32 [[TMP71]], [[TMP50]]
6481; CHECK-NEXT:    [[TMP76:%.*]] = select i1 [[TMP72]], i32 [[TMP75]], i32 [[TMP71]]
6482; CHECK-NEXT:    [[TMP77:%.*]] = icmp uge i32 [[TMP76]], [[TMP50]]
6483; CHECK-NEXT:    [[TMP78:%.*]] = add i32 [[TMP74]], 1
6484; CHECK-NEXT:    [[TMP79:%.*]] = select i1 [[TMP77]], i32 [[TMP78]], i32 [[TMP74]]
6485; CHECK-NEXT:    [[TMP80:%.*]] = xor i32 [[TMP79]], [[TMP46]]
6486; CHECK-NEXT:    [[TMP81:%.*]] = sub i32 [[TMP80]], [[TMP46]]
6487; CHECK-NEXT:    [[TMP82:%.*]] = insertelement <2 x i32> [[TMP41]], i32 [[TMP81]], i64 1
6488; CHECK-NEXT:    store <2 x i32> [[TMP82]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
6489; CHECK-NEXT:    ret void
6490;
6491; GFX6-LABEL: sdiv_v2i32_pow2_shl_denom:
6492; GFX6:       ; %bb.0:
6493; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
6494; GFX6-NEXT:    s_movk_i32 s10, 0x1000
6495; GFX6-NEXT:    s_mov_b32 s13, 0x4f7ffffe
6496; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
6497; GFX6-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xb
6498; GFX6-NEXT:    s_mov_b32 s7, 0xf000
6499; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6500; GFX6-NEXT:    s_lshl_b32 s2, s10, s2
6501; GFX6-NEXT:    s_ashr_i32 s11, s2, 31
6502; GFX6-NEXT:    s_add_i32 s2, s2, s11
6503; GFX6-NEXT:    s_xor_b32 s12, s2, s11
6504; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s12
6505; GFX6-NEXT:    s_lshl_b32 s0, s10, s3
6506; GFX6-NEXT:    s_sub_i32 s3, 0, s12
6507; GFX6-NEXT:    s_ashr_i32 s2, s0, 31
6508; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6509; GFX6-NEXT:    s_add_i32 s0, s0, s2
6510; GFX6-NEXT:    s_xor_b32 s10, s0, s2
6511; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s10
6512; GFX6-NEXT:    v_mul_f32_e32 v0, s13, v0
6513; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
6514; GFX6-NEXT:    s_ashr_i32 s1, s8, 31
6515; GFX6-NEXT:    s_add_i32 s0, s8, s1
6516; GFX6-NEXT:    s_xor_b32 s0, s0, s1
6517; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v0
6518; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
6519; GFX6-NEXT:    s_xor_b32 s3, s1, s11
6520; GFX6-NEXT:    s_mov_b32 s6, -1
6521; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
6522; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
6523; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
6524; GFX6-NEXT:    v_mul_f32_e32 v1, s13, v2
6525; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
6526; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s12
6527; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
6528; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s0, v2
6529; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s12, v2
6530; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[0:1]
6531; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s12, v2
6532; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
6533; GFX6-NEXT:    s_sub_i32 s0, 0, s10
6534; GFX6-NEXT:    v_mul_lo_u32 v3, s0, v1
6535; GFX6-NEXT:    s_ashr_i32 s0, s9, 31
6536; GFX6-NEXT:    s_add_i32 s1, s9, s0
6537; GFX6-NEXT:    s_xor_b32 s1, s1, s0
6538; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
6539; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
6540; GFX6-NEXT:    s_xor_b32 s2, s0, s2
6541; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
6542; GFX6-NEXT:    v_mul_hi_u32 v1, s1, v1
6543; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v2
6544; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
6545; GFX6-NEXT:    v_xor_b32_e32 v0, s3, v0
6546; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s10
6547; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
6548; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s3, v0
6549; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
6550; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v2
6551; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
6552; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s10, v2
6553; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
6554; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
6555; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
6556; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
6557; GFX6-NEXT:    v_xor_b32_e32 v1, s2, v1
6558; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s2, v1
6559; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
6560; GFX6-NEXT:    s_endpgm
6561;
6562; GFX9-LABEL: sdiv_v2i32_pow2_shl_denom:
6563; GFX9:       ; %bb.0:
6564; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
6565; GFX9-NEXT:    s_movk_i32 s8, 0x1000
6566; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
6567; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x2c
6568; GFX9-NEXT:    s_mov_b32 s11, 0x4f7ffffe
6569; GFX9-NEXT:    v_mov_b32_e32 v2, 0
6570; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6571; GFX9-NEXT:    s_lshl_b32 s2, s8, s2
6572; GFX9-NEXT:    s_ashr_i32 s9, s2, 31
6573; GFX9-NEXT:    s_add_i32 s2, s2, s9
6574; GFX9-NEXT:    s_xor_b32 s10, s2, s9
6575; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s10
6576; GFX9-NEXT:    s_lshl_b32 s0, s8, s3
6577; GFX9-NEXT:    s_ashr_i32 s1, s0, 31
6578; GFX9-NEXT:    s_add_i32 s0, s0, s1
6579; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6580; GFX9-NEXT:    s_xor_b32 s8, s0, s1
6581; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s8
6582; GFX9-NEXT:    s_sub_i32 s0, 0, s10
6583; GFX9-NEXT:    v_mul_f32_e32 v0, s11, v0
6584; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
6585; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
6586; GFX9-NEXT:    s_sub_i32 s3, 0, s8
6587; GFX9-NEXT:    v_mul_lo_u32 v3, s0, v0
6588; GFX9-NEXT:    v_mul_f32_e32 v1, s11, v1
6589; GFX9-NEXT:    s_ashr_i32 s0, s6, 31
6590; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
6591; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v3
6592; GFX9-NEXT:    s_add_i32 s2, s6, s0
6593; GFX9-NEXT:    s_xor_b32 s2, s2, s0
6594; GFX9-NEXT:    s_xor_b32 s0, s0, s9
6595; GFX9-NEXT:    v_add_u32_e32 v0, v0, v3
6596; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
6597; GFX9-NEXT:    v_mul_lo_u32 v3, s3, v1
6598; GFX9-NEXT:    s_ashr_i32 s3, s7, 31
6599; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s10
6600; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
6601; GFX9-NEXT:    v_add_u32_e32 v5, 1, v0
6602; GFX9-NEXT:    v_sub_u32_e32 v4, s2, v4
6603; GFX9-NEXT:    s_add_i32 s2, s7, s3
6604; GFX9-NEXT:    s_xor_b32 s2, s2, s3
6605; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
6606; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v4
6607; GFX9-NEXT:    v_mul_hi_u32 v1, s2, v1
6608; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
6609; GFX9-NEXT:    v_subrev_u32_e32 v5, s10, v4
6610; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
6611; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v4
6612; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
6613; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
6614; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s8
6615; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
6616; GFX9-NEXT:    v_xor_b32_e32 v0, s0, v0
6617; GFX9-NEXT:    v_subrev_u32_e32 v0, s0, v0
6618; GFX9-NEXT:    v_sub_u32_e32 v3, s2, v3
6619; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
6620; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
6621; GFX9-NEXT:    v_subrev_u32_e32 v4, s8, v3
6622; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
6623; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
6624; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
6625; GFX9-NEXT:    s_xor_b32 s0, s3, s1
6626; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
6627; GFX9-NEXT:    v_xor_b32_e32 v1, s0, v1
6628; GFX9-NEXT:    v_subrev_u32_e32 v1, s0, v1
6629; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
6630; GFX9-NEXT:    s_endpgm
6631  %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
6632  %r = sdiv <2 x i32> %x, %shl.y
6633  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
6634  ret void
6635}
6636
6637define amdgpu_kernel void @srem_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
6638; CHECK-LABEL: @srem_i32_oddk_denom(
6639; CHECK-NEXT:    [[R:%.*]] = srem i32 [[X:%.*]], 1235195
6640; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
6641; CHECK-NEXT:    ret void
6642;
6643; GFX6-LABEL: srem_i32_oddk_denom:
6644; GFX6:       ; %bb.0:
6645; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
6646; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
6647; GFX6-NEXT:    v_mov_b32_e32 v0, 0xd9528441
6648; GFX6-NEXT:    s_mov_b32 s7, 0xf000
6649; GFX6-NEXT:    s_mov_b32 s6, -1
6650; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6651; GFX6-NEXT:    v_mul_hi_i32 v0, s0, v0
6652; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s0, v0
6653; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 31, v0
6654; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 20, v0
6655; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
6656; GFX6-NEXT:    v_mul_i32_i24_e32 v0, 0x12d8fb, v0
6657; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
6658; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
6659; GFX6-NEXT:    s_endpgm
6660;
6661; GFX9-LABEL: srem_i32_oddk_denom:
6662; GFX9:       ; %bb.0:
6663; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
6664; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
6665; GFX9-NEXT:    v_mov_b32_e32 v1, 0x12d8fb
6666; GFX9-NEXT:    v_mov_b32_e32 v0, 0
6667; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6668; GFX9-NEXT:    s_mul_hi_i32 s0, s4, 0xd9528441
6669; GFX9-NEXT:    s_add_i32 s0, s0, s4
6670; GFX9-NEXT:    s_lshr_b32 s1, s0, 31
6671; GFX9-NEXT:    s_ashr_i32 s0, s0, 20
6672; GFX9-NEXT:    s_add_i32 s0, s0, s1
6673; GFX9-NEXT:    v_mul_i32_i24_e32 v1, s0, v1
6674; GFX9-NEXT:    v_sub_u32_e32 v1, s4, v1
6675; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
6676; GFX9-NEXT:    s_endpgm
6677  %r = srem i32 %x, 1235195
6678  store i32 %r, i32 addrspace(1)* %out
6679  ret void
6680}
6681
6682define amdgpu_kernel void @srem_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x) {
6683; CHECK-LABEL: @srem_i32_pow2k_denom(
6684; CHECK-NEXT:    [[R:%.*]] = srem i32 [[X:%.*]], 4096
6685; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
6686; CHECK-NEXT:    ret void
6687;
6688; GFX6-LABEL: srem_i32_pow2k_denom:
6689; GFX6:       ; %bb.0:
6690; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
6691; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
6692; GFX6-NEXT:    s_mov_b32 s7, 0xf000
6693; GFX6-NEXT:    s_mov_b32 s6, -1
6694; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6695; GFX6-NEXT:    s_ashr_i32 s1, s0, 31
6696; GFX6-NEXT:    s_lshr_b32 s1, s1, 20
6697; GFX6-NEXT:    s_add_i32 s1, s0, s1
6698; GFX6-NEXT:    s_and_b32 s1, s1, 0xfffff000
6699; GFX6-NEXT:    s_sub_i32 s0, s0, s1
6700; GFX6-NEXT:    v_mov_b32_e32 v0, s0
6701; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
6702; GFX6-NEXT:    s_endpgm
6703;
6704; GFX9-LABEL: srem_i32_pow2k_denom:
6705; GFX9:       ; %bb.0:
6706; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
6707; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
6708; GFX9-NEXT:    v_mov_b32_e32 v0, 0
6709; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6710; GFX9-NEXT:    s_ashr_i32 s0, s4, 31
6711; GFX9-NEXT:    s_lshr_b32 s0, s0, 20
6712; GFX9-NEXT:    s_add_i32 s0, s4, s0
6713; GFX9-NEXT:    s_and_b32 s0, s0, 0xfffff000
6714; GFX9-NEXT:    s_sub_i32 s0, s4, s0
6715; GFX9-NEXT:    v_mov_b32_e32 v1, s0
6716; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
6717; GFX9-NEXT:    s_endpgm
6718  %r = srem i32 %x, 4096
6719  store i32 %r, i32 addrspace(1)* %out
6720  ret void
6721}
6722
6723define amdgpu_kernel void @srem_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %x, i32 %y) {
6724; CHECK-LABEL: @srem_i32_pow2_shl_denom(
6725; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]]
6726; CHECK-NEXT:    [[R:%.*]] = srem i32 [[X:%.*]], [[SHL_Y]]
6727; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
6728; CHECK-NEXT:    ret void
6729;
6730; GFX6-LABEL: srem_i32_pow2_shl_denom:
6731; GFX6:       ; %bb.0:
6732; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
6733; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6734; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6735; GFX6-NEXT:    s_lshl_b32 s3, 0x1000, s3
6736; GFX6-NEXT:    s_ashr_i32 s4, s3, 31
6737; GFX6-NEXT:    s_add_i32 s3, s3, s4
6738; GFX6-NEXT:    s_xor_b32 s6, s3, s4
6739; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s6
6740; GFX6-NEXT:    s_sub_i32 s3, 0, s6
6741; GFX6-NEXT:    s_ashr_i32 s4, s2, 31
6742; GFX6-NEXT:    s_add_i32 s2, s2, s4
6743; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6744; GFX6-NEXT:    s_xor_b32 s5, s2, s4
6745; GFX6-NEXT:    s_mov_b32 s2, -1
6746; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
6747; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
6748; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v0
6749; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6750; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
6751; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
6752; GFX6-NEXT:    v_mul_hi_u32 v0, s5, v0
6753; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s6
6754; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
6755; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s6, v0
6756; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
6757; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
6758; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s6, v0
6759; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
6760; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
6761; GFX6-NEXT:    v_xor_b32_e32 v0, s4, v0
6762; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s4, v0
6763; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
6764; GFX6-NEXT:    s_endpgm
6765;
6766; GFX9-LABEL: srem_i32_pow2_shl_denom:
6767; GFX9:       ; %bb.0:
6768; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
6769; GFX9-NEXT:    s_nop 0
6770; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
6771; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6772; GFX9-NEXT:    s_lshl_b32 s3, 0x1000, s3
6773; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
6774; GFX9-NEXT:    s_add_i32 s3, s3, s4
6775; GFX9-NEXT:    s_xor_b32 s3, s3, s4
6776; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
6777; GFX9-NEXT:    s_sub_i32 s4, 0, s3
6778; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6779; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
6780; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
6781; GFX9-NEXT:    v_mul_lo_u32 v1, s4, v0
6782; GFX9-NEXT:    s_ashr_i32 s4, s2, 31
6783; GFX9-NEXT:    s_add_i32 s2, s2, s4
6784; GFX9-NEXT:    s_xor_b32 s2, s2, s4
6785; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
6786; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
6787; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
6788; GFX9-NEXT:    v_mov_b32_e32 v1, 0
6789; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
6790; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
6791; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v0
6792; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v0
6793; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
6794; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v0
6795; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v0
6796; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
6797; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v0
6798; GFX9-NEXT:    v_subrev_u32_e32 v0, s4, v0
6799; GFX9-NEXT:    global_store_dword v1, v0, s[0:1]
6800; GFX9-NEXT:    s_endpgm
6801  %shl.y = shl i32 4096, %y
6802  %r = srem i32 %x, %shl.y
6803  store i32 %r, i32 addrspace(1)* %out
6804  ret void
6805}
6806
6807define amdgpu_kernel void @srem_v2i32_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) {
6808; CHECK-LABEL: @srem_v2i32_pow2k_denom(
6809; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
6810; CHECK-NEXT:    [[TMP2:%.*]] = srem i32 [[TMP1]], 4096
6811; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0
6812; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1
6813; CHECK-NEXT:    [[TMP5:%.*]] = srem i32 [[TMP4]], 4096
6814; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1
6815; CHECK-NEXT:    store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
6816; CHECK-NEXT:    ret void
6817;
6818; GFX6-LABEL: srem_v2i32_pow2k_denom:
6819; GFX6:       ; %bb.0:
6820; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
6821; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
6822; GFX6-NEXT:    s_movk_i32 s2, 0xf000
6823; GFX6-NEXT:    s_mov_b32 s7, 0xf000
6824; GFX6-NEXT:    s_mov_b32 s6, -1
6825; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6826; GFX6-NEXT:    s_ashr_i32 s3, s0, 31
6827; GFX6-NEXT:    s_lshr_b32 s3, s3, 20
6828; GFX6-NEXT:    s_add_i32 s3, s0, s3
6829; GFX6-NEXT:    s_and_b32 s3, s3, s2
6830; GFX6-NEXT:    s_sub_i32 s0, s0, s3
6831; GFX6-NEXT:    s_ashr_i32 s3, s1, 31
6832; GFX6-NEXT:    s_lshr_b32 s3, s3, 20
6833; GFX6-NEXT:    s_add_i32 s3, s1, s3
6834; GFX6-NEXT:    s_and_b32 s2, s3, s2
6835; GFX6-NEXT:    s_sub_i32 s1, s1, s2
6836; GFX6-NEXT:    v_mov_b32_e32 v0, s0
6837; GFX6-NEXT:    v_mov_b32_e32 v1, s1
6838; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
6839; GFX6-NEXT:    s_endpgm
6840;
6841; GFX9-LABEL: srem_v2i32_pow2k_denom:
6842; GFX9:       ; %bb.0:
6843; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
6844; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
6845; GFX9-NEXT:    s_movk_i32 s6, 0xf000
6846; GFX9-NEXT:    v_mov_b32_e32 v2, 0
6847; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6848; GFX9-NEXT:    s_ashr_i32 s0, s4, 31
6849; GFX9-NEXT:    s_ashr_i32 s1, s5, 31
6850; GFX9-NEXT:    s_lshr_b32 s0, s0, 20
6851; GFX9-NEXT:    s_lshr_b32 s1, s1, 20
6852; GFX9-NEXT:    s_add_i32 s0, s4, s0
6853; GFX9-NEXT:    s_add_i32 s1, s5, s1
6854; GFX9-NEXT:    s_and_b32 s0, s0, s6
6855; GFX9-NEXT:    s_and_b32 s1, s1, s6
6856; GFX9-NEXT:    s_sub_i32 s0, s4, s0
6857; GFX9-NEXT:    s_sub_i32 s1, s5, s1
6858; GFX9-NEXT:    v_mov_b32_e32 v0, s0
6859; GFX9-NEXT:    v_mov_b32_e32 v1, s1
6860; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
6861; GFX9-NEXT:    s_endpgm
6862  %r = srem <2 x i32> %x, <i32 4096, i32 4096>
6863  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
6864  ret void
6865}
6866
6867define amdgpu_kernel void @srem_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) {
6868; CHECK-LABEL: @srem_v2i32_pow2_shl_denom(
6869; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i32> <i32 4096, i32 4096>, [[Y:%.*]]
6870; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
6871; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 0
6872; CHECK-NEXT:    [[TMP3:%.*]] = ashr i32 [[TMP1]], 31
6873; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP2]], 31
6874; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[TMP1]], [[TMP3]]
6875; CHECK-NEXT:    [[TMP6:%.*]] = add i32 [[TMP2]], [[TMP4]]
6876; CHECK-NEXT:    [[TMP7:%.*]] = xor i32 [[TMP5]], [[TMP3]]
6877; CHECK-NEXT:    [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP4]]
6878; CHECK-NEXT:    [[TMP9:%.*]] = uitofp i32 [[TMP8]] to float
6879; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
6880; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP10]], 0x41EFFFFFC0000000
6881; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP11]] to i32
6882; CHECK-NEXT:    [[TMP13:%.*]] = sub i32 0, [[TMP8]]
6883; CHECK-NEXT:    [[TMP14:%.*]] = mul i32 [[TMP13]], [[TMP12]]
6884; CHECK-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP12]] to i64
6885; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP14]] to i64
6886; CHECK-NEXT:    [[TMP17:%.*]] = mul i64 [[TMP15]], [[TMP16]]
6887; CHECK-NEXT:    [[TMP18:%.*]] = trunc i64 [[TMP17]] to i32
6888; CHECK-NEXT:    [[TMP19:%.*]] = lshr i64 [[TMP17]], 32
6889; CHECK-NEXT:    [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32
6890; CHECK-NEXT:    [[TMP21:%.*]] = add i32 [[TMP12]], [[TMP20]]
6891; CHECK-NEXT:    [[TMP22:%.*]] = zext i32 [[TMP7]] to i64
6892; CHECK-NEXT:    [[TMP23:%.*]] = zext i32 [[TMP21]] to i64
6893; CHECK-NEXT:    [[TMP24:%.*]] = mul i64 [[TMP22]], [[TMP23]]
6894; CHECK-NEXT:    [[TMP25:%.*]] = trunc i64 [[TMP24]] to i32
6895; CHECK-NEXT:    [[TMP26:%.*]] = lshr i64 [[TMP24]], 32
6896; CHECK-NEXT:    [[TMP27:%.*]] = trunc i64 [[TMP26]] to i32
6897; CHECK-NEXT:    [[TMP28:%.*]] = mul i32 [[TMP27]], [[TMP8]]
6898; CHECK-NEXT:    [[TMP29:%.*]] = sub i32 [[TMP7]], [[TMP28]]
6899; CHECK-NEXT:    [[TMP30:%.*]] = icmp uge i32 [[TMP29]], [[TMP8]]
6900; CHECK-NEXT:    [[TMP31:%.*]] = sub i32 [[TMP29]], [[TMP8]]
6901; CHECK-NEXT:    [[TMP32:%.*]] = select i1 [[TMP30]], i32 [[TMP31]], i32 [[TMP29]]
6902; CHECK-NEXT:    [[TMP33:%.*]] = icmp uge i32 [[TMP32]], [[TMP8]]
6903; CHECK-NEXT:    [[TMP34:%.*]] = sub i32 [[TMP32]], [[TMP8]]
6904; CHECK-NEXT:    [[TMP35:%.*]] = select i1 [[TMP33]], i32 [[TMP34]], i32 [[TMP32]]
6905; CHECK-NEXT:    [[TMP36:%.*]] = xor i32 [[TMP35]], [[TMP3]]
6906; CHECK-NEXT:    [[TMP37:%.*]] = sub i32 [[TMP36]], [[TMP3]]
6907; CHECK-NEXT:    [[TMP38:%.*]] = insertelement <2 x i32> undef, i32 [[TMP37]], i64 0
6908; CHECK-NEXT:    [[TMP39:%.*]] = extractelement <2 x i32> [[X]], i64 1
6909; CHECK-NEXT:    [[TMP40:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1
6910; CHECK-NEXT:    [[TMP41:%.*]] = ashr i32 [[TMP39]], 31
6911; CHECK-NEXT:    [[TMP42:%.*]] = ashr i32 [[TMP40]], 31
6912; CHECK-NEXT:    [[TMP43:%.*]] = add i32 [[TMP39]], [[TMP41]]
6913; CHECK-NEXT:    [[TMP44:%.*]] = add i32 [[TMP40]], [[TMP42]]
6914; CHECK-NEXT:    [[TMP45:%.*]] = xor i32 [[TMP43]], [[TMP41]]
6915; CHECK-NEXT:    [[TMP46:%.*]] = xor i32 [[TMP44]], [[TMP42]]
6916; CHECK-NEXT:    [[TMP47:%.*]] = uitofp i32 [[TMP46]] to float
6917; CHECK-NEXT:    [[TMP48:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP47]])
6918; CHECK-NEXT:    [[TMP49:%.*]] = fmul fast float [[TMP48]], 0x41EFFFFFC0000000
6919; CHECK-NEXT:    [[TMP50:%.*]] = fptoui float [[TMP49]] to i32
6920; CHECK-NEXT:    [[TMP51:%.*]] = sub i32 0, [[TMP46]]
6921; CHECK-NEXT:    [[TMP52:%.*]] = mul i32 [[TMP51]], [[TMP50]]
6922; CHECK-NEXT:    [[TMP53:%.*]] = zext i32 [[TMP50]] to i64
6923; CHECK-NEXT:    [[TMP54:%.*]] = zext i32 [[TMP52]] to i64
6924; CHECK-NEXT:    [[TMP55:%.*]] = mul i64 [[TMP53]], [[TMP54]]
6925; CHECK-NEXT:    [[TMP56:%.*]] = trunc i64 [[TMP55]] to i32
6926; CHECK-NEXT:    [[TMP57:%.*]] = lshr i64 [[TMP55]], 32
6927; CHECK-NEXT:    [[TMP58:%.*]] = trunc i64 [[TMP57]] to i32
6928; CHECK-NEXT:    [[TMP59:%.*]] = add i32 [[TMP50]], [[TMP58]]
6929; CHECK-NEXT:    [[TMP60:%.*]] = zext i32 [[TMP45]] to i64
6930; CHECK-NEXT:    [[TMP61:%.*]] = zext i32 [[TMP59]] to i64
6931; CHECK-NEXT:    [[TMP62:%.*]] = mul i64 [[TMP60]], [[TMP61]]
6932; CHECK-NEXT:    [[TMP63:%.*]] = trunc i64 [[TMP62]] to i32
6933; CHECK-NEXT:    [[TMP64:%.*]] = lshr i64 [[TMP62]], 32
6934; CHECK-NEXT:    [[TMP65:%.*]] = trunc i64 [[TMP64]] to i32
6935; CHECK-NEXT:    [[TMP66:%.*]] = mul i32 [[TMP65]], [[TMP46]]
6936; CHECK-NEXT:    [[TMP67:%.*]] = sub i32 [[TMP45]], [[TMP66]]
6937; CHECK-NEXT:    [[TMP68:%.*]] = icmp uge i32 [[TMP67]], [[TMP46]]
6938; CHECK-NEXT:    [[TMP69:%.*]] = sub i32 [[TMP67]], [[TMP46]]
6939; CHECK-NEXT:    [[TMP70:%.*]] = select i1 [[TMP68]], i32 [[TMP69]], i32 [[TMP67]]
6940; CHECK-NEXT:    [[TMP71:%.*]] = icmp uge i32 [[TMP70]], [[TMP46]]
6941; CHECK-NEXT:    [[TMP72:%.*]] = sub i32 [[TMP70]], [[TMP46]]
6942; CHECK-NEXT:    [[TMP73:%.*]] = select i1 [[TMP71]], i32 [[TMP72]], i32 [[TMP70]]
6943; CHECK-NEXT:    [[TMP74:%.*]] = xor i32 [[TMP73]], [[TMP41]]
6944; CHECK-NEXT:    [[TMP75:%.*]] = sub i32 [[TMP74]], [[TMP41]]
6945; CHECK-NEXT:    [[TMP76:%.*]] = insertelement <2 x i32> [[TMP38]], i32 [[TMP75]], i64 1
6946; CHECK-NEXT:    store <2 x i32> [[TMP76]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
6947; CHECK-NEXT:    ret void
6948;
6949; GFX6-LABEL: srem_v2i32_pow2_shl_denom:
6950; GFX6:       ; %bb.0:
6951; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
6952; GFX6-NEXT:    s_movk_i32 s6, 0x1000
6953; GFX6-NEXT:    s_mov_b32 s10, 0x4f7ffffe
6954; GFX6-NEXT:    s_mov_b32 s7, 0xf000
6955; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6956; GFX6-NEXT:    s_lshl_b32 s2, s6, s2
6957; GFX6-NEXT:    s_ashr_i32 s4, s2, 31
6958; GFX6-NEXT:    s_add_i32 s2, s2, s4
6959; GFX6-NEXT:    s_xor_b32 s9, s2, s4
6960; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s9
6961; GFX6-NEXT:    s_lshl_b32 s2, s6, s3
6962; GFX6-NEXT:    s_ashr_i32 s6, s2, 31
6963; GFX6-NEXT:    s_add_i32 s2, s2, s6
6964; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6965; GFX6-NEXT:    s_sub_i32 s8, 0, s9
6966; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
6967; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
6968; GFX6-NEXT:    v_mul_f32_e32 v0, s10, v0
6969; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
6970; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6971; GFX6-NEXT:    s_ashr_i32 s3, s0, 31
6972; GFX6-NEXT:    s_add_i32 s0, s0, s3
6973; GFX6-NEXT:    v_mul_lo_u32 v1, s8, v0
6974; GFX6-NEXT:    s_xor_b32 s8, s2, s6
6975; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s8
6976; GFX6-NEXT:    s_xor_b32 s0, s0, s3
6977; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
6978; GFX6-NEXT:    s_sub_i32 s2, 0, s8
6979; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
6980; GFX6-NEXT:    s_mov_b32 s6, -1
6981; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
6982; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
6983; GFX6-NEXT:    v_mul_f32_e32 v1, s10, v2
6984; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
6985; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s9
6986; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
6987; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
6988; GFX6-NEXT:    s_ashr_i32 s0, s1, 31
6989; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v2
6990; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s9, v0
6991; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v0
6992; GFX6-NEXT:    s_add_i32 s1, s1, s0
6993; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
6994; GFX6-NEXT:    s_xor_b32 s1, s1, s0
6995; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
6996; GFX6-NEXT:    v_mul_hi_u32 v1, s1, v1
6997; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s9, v0
6998; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v0
6999; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
7000; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s8
7001; GFX6-NEXT:    v_xor_b32_e32 v0, s3, v0
7002; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s3, v0
7003; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v1
7004; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v1
7005; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v1
7006; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
7007; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v1
7008; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v1
7009; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
7010; GFX6-NEXT:    v_xor_b32_e32 v1, s0, v1
7011; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s0, v1
7012; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
7013; GFX6-NEXT:    s_endpgm
7014;
7015; GFX9-LABEL: srem_v2i32_pow2_shl_denom:
7016; GFX9:       ; %bb.0:
7017; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
7018; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
7019; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
7020; GFX9-NEXT:    s_movk_i32 s8, 0x1000
7021; GFX9-NEXT:    s_mov_b32 s9, 0x4f7ffffe
7022; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7023; GFX9-NEXT:    s_lshl_b32 s0, s8, s6
7024; GFX9-NEXT:    s_ashr_i32 s1, s0, 31
7025; GFX9-NEXT:    s_add_i32 s0, s0, s1
7026; GFX9-NEXT:    s_xor_b32 s0, s0, s1
7027; GFX9-NEXT:    s_lshl_b32 s1, s8, s7
7028; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s0
7029; GFX9-NEXT:    s_ashr_i32 s6, s1, 31
7030; GFX9-NEXT:    s_add_i32 s1, s1, s6
7031; GFX9-NEXT:    s_xor_b32 s1, s1, s6
7032; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s1
7033; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
7034; GFX9-NEXT:    s_sub_i32 s7, 0, s0
7035; GFX9-NEXT:    s_ashr_i32 s6, s4, 31
7036; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
7037; GFX9-NEXT:    v_mul_f32_e32 v0, s9, v0
7038; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
7039; GFX9-NEXT:    s_add_i32 s4, s4, s6
7040; GFX9-NEXT:    v_mul_f32_e32 v1, s9, v1
7041; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
7042; GFX9-NEXT:    v_mul_lo_u32 v2, s7, v0
7043; GFX9-NEXT:    s_sub_i32 s7, 0, s1
7044; GFX9-NEXT:    s_xor_b32 s4, s4, s6
7045; GFX9-NEXT:    v_mul_lo_u32 v3, s7, v1
7046; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
7047; GFX9-NEXT:    s_ashr_i32 s7, s5, 31
7048; GFX9-NEXT:    s_add_i32 s5, s5, s7
7049; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
7050; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
7051; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
7052; GFX9-NEXT:    s_xor_b32 s5, s5, s7
7053; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
7054; GFX9-NEXT:    v_mul_hi_u32 v1, s5, v1
7055; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s0
7056; GFX9-NEXT:    v_mov_b32_e32 v2, 0
7057; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s1
7058; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
7059; GFX9-NEXT:    v_subrev_u32_e32 v3, s0, v0
7060; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s0, v0
7061; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
7062; GFX9-NEXT:    v_subrev_u32_e32 v3, s0, v0
7063; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s0, v0
7064; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v1
7065; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
7066; GFX9-NEXT:    v_subrev_u32_e32 v3, s1, v1
7067; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s1, v1
7068; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
7069; GFX9-NEXT:    v_subrev_u32_e32 v3, s1, v1
7070; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s1, v1
7071; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
7072; GFX9-NEXT:    v_xor_b32_e32 v0, s6, v0
7073; GFX9-NEXT:    v_xor_b32_e32 v1, s7, v1
7074; GFX9-NEXT:    v_subrev_u32_e32 v0, s6, v0
7075; GFX9-NEXT:    v_subrev_u32_e32 v1, s7, v1
7076; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
7077; GFX9-NEXT:    s_endpgm
7078  %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
7079  %r = srem <2 x i32> %x, %shl.y
7080  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
7081  ret void
7082}
7083
7084define amdgpu_kernel void @udiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
7085; CHECK-LABEL: @udiv_i64_oddk_denom(
7086; CHECK-NEXT:    [[R:%.*]] = udiv i64 [[X:%.*]], 1235195949943
7087; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
7088; CHECK-NEXT:    ret void
7089;
7090; GFX6-LABEL: udiv_i64_oddk_denom:
7091; GFX6:       ; %bb.0:
7092; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f176a73
7093; GFX6-NEXT:    v_mov_b32_e32 v1, 0x4f800000
7094; GFX6-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
7095; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
7096; GFX6-NEXT:    s_movk_i32 s2, 0xfee0
7097; GFX6-NEXT:    s_mov_b32 s3, 0x68958c89
7098; GFX6-NEXT:    v_mov_b32_e32 v8, 0
7099; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
7100; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
7101; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
7102; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
7103; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
7104; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
7105; GFX6-NEXT:    v_mov_b32_e32 v7, 0
7106; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
7107; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s2
7108; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s3
7109; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s3
7110; GFX6-NEXT:    s_mov_b32 s11, 0xf000
7111; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7112; GFX6-NEXT:    s_mov_b32 s8, s4
7113; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7114; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s3
7115; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
7116; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
7117; GFX6-NEXT:    v_mul_hi_u32 v4, v0, v2
7118; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v3
7119; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v2
7120; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
7121; GFX6-NEXT:    s_movk_i32 s4, 0x11e
7122; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
7123; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
7124; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
7125; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
7126; GFX6-NEXT:    s_mov_b32 s10, -1
7127; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
7128; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v4, v3, vcc
7129; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
7130; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7131; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
7132; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
7133; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s2
7134; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s3
7135; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
7136; GFX6-NEXT:    v_mul_lo_u32 v6, v2, s3
7137; GFX6-NEXT:    s_mov_b32 s2, 0x976a7377
7138; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
7139; GFX6-NEXT:    v_mul_lo_u32 v5, v0, s3
7140; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
7141; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v4
7142; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v4
7143; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v5
7144; GFX6-NEXT:    v_mul_hi_u32 v11, v2, v4
7145; GFX6-NEXT:    s_movk_i32 s3, 0x11f
7146; GFX6-NEXT:    s_mov_b32 s9, s5
7147; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
7148; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, v8, v10, vcc
7149; GFX6-NEXT:    v_mul_lo_u32 v10, v2, v5
7150; GFX6-NEXT:    v_mul_hi_u32 v5, v2, v5
7151; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v4
7152; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
7153; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
7154; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v11, v7, vcc
7155; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
7156; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
7157; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
7158; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
7159; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
7160; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
7161; GFX6-NEXT:    v_mul_lo_u32 v2, s6, v1
7162; GFX6-NEXT:    v_mul_hi_u32 v3, s6, v0
7163; GFX6-NEXT:    v_mul_hi_u32 v4, s6, v1
7164; GFX6-NEXT:    v_mul_hi_u32 v5, s7, v1
7165; GFX6-NEXT:    v_mul_lo_u32 v1, s7, v1
7166; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7167; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
7168; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v0
7169; GFX6-NEXT:    v_mul_hi_u32 v0, s7, v0
7170; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
7171; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
7172; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
7173; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
7174; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
7175; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s3
7176; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s2
7177; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s2
7178; GFX6-NEXT:    v_mov_b32_e32 v5, s3
7179; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7180; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s2
7181; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
7182; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s7, v2
7183; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s6, v3
7184; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
7185; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s2, v3
7186; GFX6-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
7187; GFX6-NEXT:    v_cmp_lt_u32_e64 s[0:1], s4, v4
7188; GFX6-NEXT:    s_mov_b32 s2, 0x976a7376
7189; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
7190; GFX6-NEXT:    v_cmp_lt_u32_e64 s[0:1], s2, v5
7191; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
7192; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v4
7193; GFX6-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
7194; GFX6-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
7195; GFX6-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
7196; GFX6-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
7197; GFX6-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
7198; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
7199; GFX6-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
7200; GFX6-NEXT:    v_mov_b32_e32 v6, s7
7201; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
7202; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s4, v2
7203; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
7204; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s2, v3
7205; GFX6-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
7206; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v2
7207; GFX6-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
7208; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
7209; GFX6-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
7210; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
7211; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
7212; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
7213; GFX6-NEXT:    s_endpgm
7214;
7215; GFX9-LABEL: udiv_i64_oddk_denom:
7216; GFX9:       ; %bb.0:
7217; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f176a73
7218; GFX9-NEXT:    v_mov_b32_e32 v1, 0x4f800000
7219; GFX9-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
7220; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
7221; GFX9-NEXT:    s_movk_i32 s4, 0xfee0
7222; GFX9-NEXT:    s_mov_b32 s5, 0x68958c89
7223; GFX9-NEXT:    v_mov_b32_e32 v6, 0
7224; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
7225; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
7226; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
7227; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
7228; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
7229; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
7230; GFX9-NEXT:    s_movk_i32 s8, 0x11f
7231; GFX9-NEXT:    s_mov_b32 s9, 0x976a7376
7232; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s4
7233; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s5
7234; GFX9-NEXT:    v_mul_lo_u32 v5, v1, s5
7235; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s5
7236; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
7237; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
7238; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
7239; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
7240; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
7241; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
7242; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
7243; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
7244; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
7245; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
7246; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
7247; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v7, v3
7248; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
7249; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
7250; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7251; GFX9-NEXT:    v_mov_b32_e32 v5, 0
7252; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
7253; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
7254; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
7255; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s4
7256; GFX9-NEXT:    v_mul_hi_u32 v7, v0, s5
7257; GFX9-NEXT:    v_mul_lo_u32 v8, v2, s5
7258; GFX9-NEXT:    v_mul_lo_u32 v9, v0, s5
7259; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
7260; GFX9-NEXT:    v_add_u32_e32 v4, v7, v4
7261; GFX9-NEXT:    v_add_u32_e32 v4, v4, v8
7262; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v4
7263; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v9
7264; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v4
7265; GFX9-NEXT:    v_mul_hi_u32 v11, v2, v4
7266; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
7267; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
7268; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v10, vcc
7269; GFX9-NEXT:    v_mul_lo_u32 v10, v2, v9
7270; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v9
7271; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
7272; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v10
7273; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v8, v9, vcc
7274; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v11, v6, vcc
7275; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v7, v2
7276; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v4, vcc
7277; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
7278; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
7279; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
7280; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7281; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
7282; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
7283; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
7284; GFX9-NEXT:    v_mul_hi_u32 v7, s7, v1
7285; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
7286; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7287; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
7288; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v0
7289; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
7290; GFX9-NEXT:    s_mov_b32 s2, 0x976a7377
7291; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
7292; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
7293; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
7294; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
7295; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
7296; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s8
7297; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s2
7298; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s2
7299; GFX9-NEXT:    v_mov_b32_e32 v5, s8
7300; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
7301; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s2
7302; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
7303; GFX9-NEXT:    v_sub_u32_e32 v4, s7, v2
7304; GFX9-NEXT:    v_sub_co_u32_e64 v3, s[0:1], s6, v3
7305; GFX9-NEXT:    v_subb_co_u32_e64 v4, vcc, v4, v5, s[0:1]
7306; GFX9-NEXT:    v_subrev_co_u32_e32 v5, vcc, s2, v3
7307; GFX9-NEXT:    v_subbrev_co_u32_e32 v4, vcc, 0, v4, vcc
7308; GFX9-NEXT:    s_movk_i32 s6, 0x11e
7309; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v4
7310; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
7311; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s9, v5
7312; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
7313; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s8, v4
7314; GFX9-NEXT:    v_cndmask_b32_e32 v4, v7, v5, vcc
7315; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, 2, v0
7316; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v1, vcc
7317; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 1, v0
7318; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
7319; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v4
7320; GFX9-NEXT:    v_cndmask_b32_e64 v4, v9, v7, s[2:3]
7321; GFX9-NEXT:    v_mov_b32_e32 v7, s7
7322; GFX9-NEXT:    v_subb_co_u32_e64 v2, vcc, v7, v2, s[0:1]
7323; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v2
7324; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
7325; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s9, v3
7326; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
7327; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s8, v2
7328; GFX9-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc
7329; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
7330; GFX9-NEXT:    v_cndmask_b32_e64 v2, v8, v5, s[2:3]
7331; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
7332; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
7333; GFX9-NEXT:    global_store_dwordx2 v6, v[0:1], s[4:5]
7334; GFX9-NEXT:    s_endpgm
7335  %r = udiv i64 %x, 1235195949943
7336  store i64 %r, i64 addrspace(1)* %out
7337  ret void
7338}
7339
7340define amdgpu_kernel void @udiv_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) {
7341; CHECK-LABEL: @udiv_i64_pow2k_denom(
7342; CHECK-NEXT:    [[R:%.*]] = udiv i64 [[X:%.*]], 4096
7343; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
7344; CHECK-NEXT:    ret void
7345;
7346; GFX6-LABEL: udiv_i64_pow2k_denom:
7347; GFX6:       ; %bb.0:
7348; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
7349; GFX6-NEXT:    s_mov_b32 s7, 0xf000
7350; GFX6-NEXT:    s_mov_b32 s6, -1
7351; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7352; GFX6-NEXT:    s_mov_b32 s4, s0
7353; GFX6-NEXT:    s_mov_b32 s5, s1
7354; GFX6-NEXT:    s_lshr_b64 s[0:1], s[2:3], 12
7355; GFX6-NEXT:    v_mov_b32_e32 v0, s0
7356; GFX6-NEXT:    v_mov_b32_e32 v1, s1
7357; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
7358; GFX6-NEXT:    s_endpgm
7359;
7360; GFX9-LABEL: udiv_i64_pow2k_denom:
7361; GFX9:       ; %bb.0:
7362; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
7363; GFX9-NEXT:    v_mov_b32_e32 v2, 0
7364; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7365; GFX9-NEXT:    s_lshr_b64 s[2:3], s[2:3], 12
7366; GFX9-NEXT:    v_mov_b32_e32 v0, s2
7367; GFX9-NEXT:    v_mov_b32_e32 v1, s3
7368; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
7369; GFX9-NEXT:    s_endpgm
7370  %r = udiv i64 %x, 4096
7371  store i64 %r, i64 addrspace(1)* %out
7372  ret void
7373}
7374
7375define amdgpu_kernel void @udiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %x, i64 %y) {
7376; CHECK-LABEL: @udiv_i64_pow2_shl_denom(
7377; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]]
7378; CHECK-NEXT:    [[R:%.*]] = udiv i64 [[X:%.*]], [[SHL_Y]]
7379; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
7380; CHECK-NEXT:    ret void
7381;
7382; GFX6-LABEL: udiv_i64_pow2_shl_denom:
7383; GFX6:       ; %bb.0:
7384; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
7385; GFX6-NEXT:    s_load_dword s8, s[0:1], 0xd
7386; GFX6-NEXT:    s_mov_b32 s3, 0xf000
7387; GFX6-NEXT:    s_mov_b32 s2, -1
7388; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7389; GFX6-NEXT:    s_mov_b32 s0, s4
7390; GFX6-NEXT:    s_add_i32 s8, s8, 12
7391; GFX6-NEXT:    s_mov_b32 s1, s5
7392; GFX6-NEXT:    s_lshr_b64 s[4:5], s[6:7], s8
7393; GFX6-NEXT:    v_mov_b32_e32 v0, s4
7394; GFX6-NEXT:    v_mov_b32_e32 v1, s5
7395; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
7396; GFX6-NEXT:    s_endpgm
7397;
7398; GFX9-LABEL: udiv_i64_pow2_shl_denom:
7399; GFX9:       ; %bb.0:
7400; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
7401; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x34
7402; GFX9-NEXT:    v_mov_b32_e32 v2, 0
7403; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7404; GFX9-NEXT:    s_add_i32 s2, s2, 12
7405; GFX9-NEXT:    s_lshr_b64 s[0:1], s[6:7], s2
7406; GFX9-NEXT:    v_mov_b32_e32 v0, s0
7407; GFX9-NEXT:    v_mov_b32_e32 v1, s1
7408; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
7409; GFX9-NEXT:    s_endpgm
7410  %shl.y = shl i64 4096, %y
7411  %r = udiv i64 %x, %shl.y
7412  store i64 %r, i64 addrspace(1)* %out
7413  ret void
7414}
7415
7416define amdgpu_kernel void @udiv_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
7417; CHECK-LABEL: @udiv_v2i64_pow2k_denom(
7418; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
7419; CHECK-NEXT:    [[TMP2:%.*]] = udiv i64 [[TMP1]], 4096
7420; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
7421; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
7422; CHECK-NEXT:    [[TMP5:%.*]] = udiv i64 [[TMP4]], 4096
7423; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
7424; CHECK-NEXT:    store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
7425; CHECK-NEXT:    ret void
7426;
7427; GFX6-LABEL: udiv_v2i64_pow2k_denom:
7428; GFX6:       ; %bb.0:
7429; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
7430; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
7431; GFX6-NEXT:    s_mov_b32 s7, 0xf000
7432; GFX6-NEXT:    s_mov_b32 s6, -1
7433; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7434; GFX6-NEXT:    s_lshr_b64 s[0:1], s[0:1], 12
7435; GFX6-NEXT:    s_lshr_b64 s[2:3], s[2:3], 12
7436; GFX6-NEXT:    v_mov_b32_e32 v0, s0
7437; GFX6-NEXT:    v_mov_b32_e32 v1, s1
7438; GFX6-NEXT:    v_mov_b32_e32 v2, s2
7439; GFX6-NEXT:    v_mov_b32_e32 v3, s3
7440; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
7441; GFX6-NEXT:    s_endpgm
7442;
7443; GFX9-LABEL: udiv_v2i64_pow2k_denom:
7444; GFX9:       ; %bb.0:
7445; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
7446; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
7447; GFX9-NEXT:    v_mov_b32_e32 v4, 0
7448; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7449; GFX9-NEXT:    s_lshr_b64 s[0:1], s[4:5], 12
7450; GFX9-NEXT:    s_lshr_b64 s[4:5], s[6:7], 12
7451; GFX9-NEXT:    v_mov_b32_e32 v0, s0
7452; GFX9-NEXT:    v_mov_b32_e32 v1, s1
7453; GFX9-NEXT:    v_mov_b32_e32 v2, s4
7454; GFX9-NEXT:    v_mov_b32_e32 v3, s5
7455; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
7456; GFX9-NEXT:    s_endpgm
7457  %r = udiv <2 x i64> %x, <i64 4096, i64 4096>
7458  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
7459  ret void
7460}
7461
7462define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
7463; CHECK-LABEL: @udiv_v2i64_mixed_pow2k_denom(
7464; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
7465; CHECK-NEXT:    [[TMP2:%.*]] = udiv i64 [[TMP1]], 4096
7466; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
7467; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
7468; CHECK-NEXT:    [[TMP5:%.*]] = udiv i64 [[TMP4]], 4095
7469; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
7470; CHECK-NEXT:    store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
7471; CHECK-NEXT:    ret void
7472;
7473; GFX6-LABEL: udiv_v2i64_mixed_pow2k_denom:
7474; GFX6:       ; %bb.0:
7475; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f800000
7476; GFX6-NEXT:    v_madak_f32 v0, 0, v0, 0x457ff000
7477; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
7478; GFX6-NEXT:    s_movk_i32 s6, 0xf001
7479; GFX6-NEXT:    v_mov_b32_e32 v7, 0
7480; GFX6-NEXT:    v_mov_b32_e32 v2, 0
7481; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
7482; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
7483; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
7484; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
7485; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
7486; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
7487; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
7488; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
7489; GFX6-NEXT:    s_movk_i32 s0, 0xfff
7490; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s6
7491; GFX6-NEXT:    v_mul_lo_u32 v5, v1, s6
7492; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s6
7493; GFX6-NEXT:    s_mov_b32 s7, 0xf000
7494; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, v0, v3
7495; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
7496; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v4
7497; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v3
7498; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v3
7499; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v3
7500; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
7501; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
7502; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v7, v8, vcc
7503; GFX6-NEXT:    v_mul_lo_u32 v8, v1, v4
7504; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
7505; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
7506; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v6, v4, vcc
7507; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v9, v2, vcc
7508; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
7509; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v3
7510; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
7511; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s6
7512; GFX6-NEXT:    v_addc_u32_e64 v3, vcc, v1, v4, s[2:3]
7513; GFX6-NEXT:    v_mul_lo_u32 v6, v3, s6
7514; GFX6-NEXT:    v_mul_lo_u32 v8, v0, s6
7515; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, v0, v5
7516; GFX6-NEXT:    s_mov_b32 s6, -1
7517; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
7518; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v5
7519; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v8
7520; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v5
7521; GFX6-NEXT:    v_mul_hi_u32 v11, v3, v5
7522; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
7523; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, v7, v10, vcc
7524; GFX6-NEXT:    v_mul_lo_u32 v10, v3, v8
7525; GFX6-NEXT:    v_mul_hi_u32 v8, v3, v8
7526; GFX6-NEXT:    v_mul_lo_u32 v3, v3, v5
7527; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
7528; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v9, v8, vcc
7529; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v11, v2, vcc
7530; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
7531; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
7532; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
7533; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
7534; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
7535; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
7536; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7537; GFX6-NEXT:    v_mul_lo_u32 v3, s10, v1
7538; GFX6-NEXT:    v_mul_hi_u32 v4, s10, v0
7539; GFX6-NEXT:    v_mul_hi_u32 v5, s10, v1
7540; GFX6-NEXT:    v_mul_hi_u32 v6, s11, v1
7541; GFX6-NEXT:    v_mul_lo_u32 v1, s11, v1
7542; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
7543; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
7544; GFX6-NEXT:    v_mul_lo_u32 v5, s11, v0
7545; GFX6-NEXT:    v_mul_hi_u32 v0, s11, v0
7546; GFX6-NEXT:    s_lshr_b64 s[2:3], s[8:9], 12
7547; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
7548; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
7549; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v6, v2, vcc
7550; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
7551; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v7, v2, vcc
7552; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s0
7553; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s0
7554; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s0
7555; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7556; GFX6-NEXT:    v_mov_b32_e32 v3, s11
7557; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s10, v4
7558; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v3, v2, vcc
7559; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s0, v4
7560; GFX6-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
7561; GFX6-NEXT:    s_movk_i32 s0, 0xffe
7562; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v3
7563; GFX6-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
7564; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v5
7565; GFX6-NEXT:    v_cndmask_b32_e32 v3, -1, v3, vcc
7566; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 2, v0
7567; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
7568; GFX6-NEXT:    v_add_i32_e32 v7, vcc, 1, v0
7569; GFX6-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v4
7570; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v1, vcc
7571; GFX6-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]
7572; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v2
7573; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
7574; GFX6-NEXT:    v_cndmask_b32_e64 v2, -1, v4, s[0:1]
7575; GFX6-NEXT:    v_cndmask_b32_e32 v3, v8, v6, vcc
7576; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v2
7577; GFX6-NEXT:    v_cndmask_b32_e64 v3, v1, v3, s[0:1]
7578; GFX6-NEXT:    v_cndmask_b32_e32 v1, v7, v5, vcc
7579; GFX6-NEXT:    v_cndmask_b32_e64 v2, v0, v1, s[0:1]
7580; GFX6-NEXT:    v_mov_b32_e32 v0, s2
7581; GFX6-NEXT:    v_mov_b32_e32 v1, s3
7582; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
7583; GFX6-NEXT:    s_endpgm
7584;
7585; GFX9-LABEL: udiv_v2i64_mixed_pow2k_denom:
7586; GFX9:       ; %bb.0:
7587; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f800000
7588; GFX9-NEXT:    v_madak_f32 v0, 0, v0, 0x457ff000
7589; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
7590; GFX9-NEXT:    s_movk_i32 s4, 0xf001
7591; GFX9-NEXT:    v_mov_b32_e32 v7, 0
7592; GFX9-NEXT:    v_mov_b32_e32 v5, 0
7593; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
7594; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
7595; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
7596; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
7597; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
7598; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
7599; GFX9-NEXT:    s_movk_i32 s8, 0xfff
7600; GFX9-NEXT:    v_mul_hi_u32 v2, v0, s4
7601; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s4
7602; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s4
7603; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
7604; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
7605; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v3
7606; GFX9-NEXT:    v_mul_lo_u32 v4, v0, v2
7607; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
7608; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v2
7609; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
7610; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
7611; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
7612; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v3
7613; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
7614; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v8, v4
7615; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
7616; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
7617; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7618; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
7619; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
7620; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
7621; GFX9-NEXT:    v_mul_hi_u32 v4, v0, s4
7622; GFX9-NEXT:    v_mul_lo_u32 v6, v2, s4
7623; GFX9-NEXT:    v_mul_lo_u32 v8, v0, s4
7624; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
7625; GFX9-NEXT:    v_sub_u32_e32 v4, v4, v0
7626; GFX9-NEXT:    v_add_u32_e32 v4, v4, v6
7627; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v4
7628; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v8
7629; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v4
7630; GFX9-NEXT:    v_mul_hi_u32 v11, v2, v4
7631; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
7632; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v9, v6
7633; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v7, v10, vcc
7634; GFX9-NEXT:    v_mul_lo_u32 v10, v2, v8
7635; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v8
7636; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
7637; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7638; GFX9-NEXT:    s_lshr_b64 s[4:5], s[4:5], 12
7639; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v10
7640; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v9, v8, vcc
7641; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v11, v5, vcc
7642; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v6, v2
7643; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
7644; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
7645; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
7646; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
7647; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
7648; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
7649; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
7650; GFX9-NEXT:    v_mul_hi_u32 v6, s7, v1
7651; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
7652; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7653; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
7654; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v0
7655; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
7656; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
7657; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
7658; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
7659; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
7660; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
7661; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
7662; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s8
7663; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s8
7664; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s8
7665; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, s6, v4
7666; GFX9-NEXT:    s_movk_i32 s6, 0xffe
7667; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
7668; GFX9-NEXT:    v_mov_b32_e32 v3, s7
7669; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v3, v2, vcc
7670; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s8, v4
7671; GFX9-NEXT:    v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc
7672; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v3
7673; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
7674; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v6
7675; GFX9-NEXT:    v_cndmask_b32_e32 v3, -1, v3, vcc
7676; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, 2, v0
7677; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v1, vcc
7678; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 1, v0
7679; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
7680; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v4
7681; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
7682; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
7683; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v3
7684; GFX9-NEXT:    v_cndmask_b32_e32 v2, -1, v4, vcc
7685; GFX9-NEXT:    v_cndmask_b32_e64 v3, v9, v7, s[0:1]
7686; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
7687; GFX9-NEXT:    v_cndmask_b32_e32 v3, v1, v3, vcc
7688; GFX9-NEXT:    v_cndmask_b32_e64 v1, v8, v6, s[0:1]
7689; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
7690; GFX9-NEXT:    v_mov_b32_e32 v0, s4
7691; GFX9-NEXT:    v_mov_b32_e32 v1, s5
7692; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7693; GFX9-NEXT:    global_store_dwordx4 v5, v[0:3], s[2:3]
7694; GFX9-NEXT:    s_endpgm
7695  %r = udiv <2 x i64> %x, <i64 4096, i64 4095>
7696  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
7697  ret void
7698}
7699
7700define amdgpu_kernel void @udiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
7701; CHECK-LABEL: @udiv_v2i64_pow2_shl_denom(
7702; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.*]]
7703; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
7704; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 0
7705; CHECK-NEXT:    [[TMP3:%.*]] = udiv i64 [[TMP1]], [[TMP2]]
7706; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i64 0
7707; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 1
7708; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
7709; CHECK-NEXT:    [[TMP7:%.*]] = udiv i64 [[TMP5]], [[TMP6]]
7710; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
7711; CHECK-NEXT:    store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
7712; CHECK-NEXT:    ret void
7713;
7714; GFX6-LABEL: udiv_v2i64_pow2_shl_denom:
7715; GFX6:       ; %bb.0:
7716; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
7717; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
7718; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
7719; GFX6-NEXT:    s_mov_b32 s7, 0xf000
7720; GFX6-NEXT:    s_mov_b32 s6, -1
7721; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7722; GFX6-NEXT:    s_add_i32 s0, s0, 12
7723; GFX6-NEXT:    s_add_i32 s2, s2, 12
7724; GFX6-NEXT:    s_lshr_b64 s[0:1], s[8:9], s0
7725; GFX6-NEXT:    s_lshr_b64 s[2:3], s[10:11], s2
7726; GFX6-NEXT:    v_mov_b32_e32 v0, s0
7727; GFX6-NEXT:    v_mov_b32_e32 v1, s1
7728; GFX6-NEXT:    v_mov_b32_e32 v2, s2
7729; GFX6-NEXT:    v_mov_b32_e32 v3, s3
7730; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
7731; GFX6-NEXT:    s_endpgm
7732;
7733; GFX9-LABEL: udiv_v2i64_pow2_shl_denom:
7734; GFX9:       ; %bb.0:
7735; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
7736; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
7737; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x44
7738; GFX9-NEXT:    v_mov_b32_e32 v4, 0
7739; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7740; GFX9-NEXT:    s_add_i32 s0, s8, 12
7741; GFX9-NEXT:    s_add_i32 s8, s10, 12
7742; GFX9-NEXT:    s_lshr_b64 s[0:1], s[4:5], s0
7743; GFX9-NEXT:    s_lshr_b64 s[4:5], s[6:7], s8
7744; GFX9-NEXT:    v_mov_b32_e32 v0, s0
7745; GFX9-NEXT:    v_mov_b32_e32 v1, s1
7746; GFX9-NEXT:    v_mov_b32_e32 v2, s4
7747; GFX9-NEXT:    v_mov_b32_e32 v3, s5
7748; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
7749; GFX9-NEXT:    s_endpgm
7750  %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
7751  %r = udiv <2 x i64> %x, %shl.y
7752  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
7753  ret void
7754}
7755
7756define amdgpu_kernel void @urem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
7757; CHECK-LABEL: @urem_i64_oddk_denom(
7758; CHECK-NEXT:    [[R:%.*]] = urem i64 [[X:%.*]], 1235195393993
7759; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
7760; CHECK-NEXT:    ret void
7761;
7762; GFX6-LABEL: urem_i64_oddk_denom:
7763; GFX6:       ; %bb.0:
7764; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f1761f8
7765; GFX6-NEXT:    v_mov_b32_e32 v1, 0x4f800000
7766; GFX6-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
7767; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
7768; GFX6-NEXT:    s_movk_i32 s2, 0xfee0
7769; GFX6-NEXT:    s_mov_b32 s3, 0x689e0837
7770; GFX6-NEXT:    v_mov_b32_e32 v8, 0
7771; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
7772; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
7773; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
7774; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
7775; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
7776; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
7777; GFX6-NEXT:    v_mov_b32_e32 v7, 0
7778; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
7779; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s2
7780; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s3
7781; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s3
7782; GFX6-NEXT:    s_movk_i32 s12, 0x11f
7783; GFX6-NEXT:    s_mov_b32 s13, 0x9761f7c9
7784; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7785; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s3
7786; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
7787; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
7788; GFX6-NEXT:    v_mul_hi_u32 v4, v0, v2
7789; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v3
7790; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v2
7791; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
7792; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7793; GFX6-NEXT:    s_mov_b32 s9, s5
7794; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
7795; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
7796; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
7797; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
7798; GFX6-NEXT:    s_movk_i32 s5, 0x11e
7799; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
7800; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v4, v3, vcc
7801; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
7802; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7803; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
7804; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
7805; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s2
7806; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s3
7807; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
7808; GFX6-NEXT:    v_mul_lo_u32 v6, v2, s3
7809; GFX6-NEXT:    s_mov_b32 s8, s4
7810; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
7811; GFX6-NEXT:    v_mul_lo_u32 v5, v0, s3
7812; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
7813; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v4
7814; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v4
7815; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v5
7816; GFX6-NEXT:    v_mul_hi_u32 v11, v2, v4
7817; GFX6-NEXT:    s_mov_b32 s4, 0x9761f7c8
7818; GFX6-NEXT:    s_mov_b32 s11, 0xf000
7819; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
7820; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, v8, v10, vcc
7821; GFX6-NEXT:    v_mul_lo_u32 v10, v2, v5
7822; GFX6-NEXT:    v_mul_hi_u32 v5, v2, v5
7823; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v4
7824; GFX6-NEXT:    s_mov_b32 s10, -1
7825; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
7826; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
7827; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v11, v7, vcc
7828; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
7829; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
7830; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
7831; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
7832; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
7833; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
7834; GFX6-NEXT:    v_mul_lo_u32 v2, s6, v1
7835; GFX6-NEXT:    v_mul_hi_u32 v3, s6, v0
7836; GFX6-NEXT:    v_mul_hi_u32 v4, s6, v1
7837; GFX6-NEXT:    v_mul_hi_u32 v5, s7, v1
7838; GFX6-NEXT:    v_mul_lo_u32 v1, s7, v1
7839; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7840; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
7841; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v0
7842; GFX6-NEXT:    v_mul_hi_u32 v0, s7, v0
7843; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
7844; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
7845; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
7846; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
7847; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
7848; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s12
7849; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s13
7850; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s13
7851; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s13
7852; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7853; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
7854; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s7, v1
7855; GFX6-NEXT:    v_mov_b32_e32 v3, s12
7856; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
7857; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
7858; GFX6-NEXT:    v_subrev_i32_e64 v4, s[0:1], s13, v0
7859; GFX6-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
7860; GFX6-NEXT:    v_cmp_lt_u32_e64 s[2:3], s5, v5
7861; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
7862; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
7863; GFX6-NEXT:    v_cmp_lt_u32_e64 s[2:3], s4, v4
7864; GFX6-NEXT:    v_subrev_i32_e64 v3, s[0:1], s13, v4
7865; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
7866; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s12, v5
7867; GFX6-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
7868; GFX6-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
7869; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
7870; GFX6-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
7871; GFX6-NEXT:    v_mov_b32_e32 v5, s7
7872; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
7873; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s5, v1
7874; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
7875; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s4, v0
7876; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
7877; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s12, v1
7878; GFX6-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
7879; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
7880; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
7881; GFX6-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
7882; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
7883; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
7884; GFX6-NEXT:    s_endpgm
7885;
7886; GFX9-LABEL: urem_i64_oddk_denom:
7887; GFX9:       ; %bb.0:
7888; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f1761f8
7889; GFX9-NEXT:    v_mov_b32_e32 v1, 0x4f800000
7890; GFX9-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
7891; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
7892; GFX9-NEXT:    s_movk_i32 s4, 0xfee0
7893; GFX9-NEXT:    s_mov_b32 s5, 0x689e0837
7894; GFX9-NEXT:    v_mov_b32_e32 v6, 0
7895; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
7896; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
7897; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
7898; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
7899; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
7900; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
7901; GFX9-NEXT:    s_movk_i32 s8, 0x11f
7902; GFX9-NEXT:    s_mov_b32 s9, 0x9761f7c9
7903; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s4
7904; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s5
7905; GFX9-NEXT:    v_mul_lo_u32 v5, v1, s5
7906; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s5
7907; GFX9-NEXT:    s_mov_b32 s10, 0x9761f7c8
7908; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
7909; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
7910; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
7911; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
7912; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
7913; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
7914; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
7915; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
7916; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
7917; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
7918; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
7919; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v7, v3
7920; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
7921; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
7922; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7923; GFX9-NEXT:    v_mov_b32_e32 v5, 0
7924; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
7925; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
7926; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
7927; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s4
7928; GFX9-NEXT:    v_mul_hi_u32 v7, v0, s5
7929; GFX9-NEXT:    v_mul_lo_u32 v8, v2, s5
7930; GFX9-NEXT:    v_mul_lo_u32 v9, v0, s5
7931; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
7932; GFX9-NEXT:    v_add_u32_e32 v4, v7, v4
7933; GFX9-NEXT:    v_add_u32_e32 v4, v4, v8
7934; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v4
7935; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v9
7936; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v4
7937; GFX9-NEXT:    v_mul_hi_u32 v11, v2, v4
7938; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
7939; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
7940; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v10, vcc
7941; GFX9-NEXT:    v_mul_lo_u32 v10, v2, v9
7942; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v9
7943; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
7944; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v10
7945; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v8, v9, vcc
7946; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v11, v6, vcc
7947; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v7, v2
7948; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v4, vcc
7949; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
7950; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
7951; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
7952; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7953; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
7954; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
7955; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
7956; GFX9-NEXT:    v_mul_hi_u32 v7, s7, v1
7957; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
7958; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7959; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
7960; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v0
7961; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
7962; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
7963; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
7964; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
7965; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
7966; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
7967; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s8
7968; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s9
7969; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s9
7970; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s9
7971; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
7972; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
7973; GFX9-NEXT:    v_sub_co_u32_e64 v0, s[0:1], s6, v0
7974; GFX9-NEXT:    v_sub_u32_e32 v2, s7, v1
7975; GFX9-NEXT:    v_mov_b32_e32 v3, s8
7976; GFX9-NEXT:    v_subb_co_u32_e64 v2, vcc, v2, v3, s[0:1]
7977; GFX9-NEXT:    v_subrev_co_u32_e64 v4, s[2:3], s9, v0
7978; GFX9-NEXT:    v_subbrev_co_u32_e64 v5, vcc, 0, v2, s[2:3]
7979; GFX9-NEXT:    s_movk_i32 s6, 0x11e
7980; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v5
7981; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
7982; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s10, v4
7983; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
7984; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s8, v5
7985; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
7986; GFX9-NEXT:    v_subb_co_u32_e64 v2, vcc, v2, v3, s[2:3]
7987; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s9, v4
7988; GFX9-NEXT:    v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc
7989; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v7
7990; GFX9-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[2:3]
7991; GFX9-NEXT:    v_mov_b32_e32 v5, s7
7992; GFX9-NEXT:    v_subb_co_u32_e64 v1, vcc, v5, v1, s[0:1]
7993; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v1
7994; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
7995; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s10, v0
7996; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
7997; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s8, v1
7998; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
7999; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
8000; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
8001; GFX9-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[2:3]
8002; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
8003; GFX9-NEXT:    global_store_dwordx2 v6, v[0:1], s[4:5]
8004; GFX9-NEXT:    s_endpgm
8005  %r = urem i64 %x, 1235195393993
8006  store i64 %r, i64 addrspace(1)* %out
8007  ret void
8008}
8009
8010define amdgpu_kernel void @urem_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) {
8011; CHECK-LABEL: @urem_i64_pow2k_denom(
8012; CHECK-NEXT:    [[R:%.*]] = urem i64 [[X:%.*]], 4096
8013; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
8014; CHECK-NEXT:    ret void
8015;
8016; GFX6-LABEL: urem_i64_pow2k_denom:
8017; GFX6:       ; %bb.0:
8018; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
8019; GFX6-NEXT:    s_mov_b32 s3, 0xf000
8020; GFX6-NEXT:    s_mov_b32 s2, -1
8021; GFX6-NEXT:    v_mov_b32_e32 v1, 0
8022; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8023; GFX6-NEXT:    s_mov_b32 s0, s4
8024; GFX6-NEXT:    s_and_b32 s4, s6, 0xfff
8025; GFX6-NEXT:    s_mov_b32 s1, s5
8026; GFX6-NEXT:    v_mov_b32_e32 v0, s4
8027; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
8028; GFX6-NEXT:    s_endpgm
8029;
8030; GFX9-LABEL: urem_i64_pow2k_denom:
8031; GFX9:       ; %bb.0:
8032; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
8033; GFX9-NEXT:    v_mov_b32_e32 v1, 0
8034; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8035; GFX9-NEXT:    s_and_b32 s2, s2, 0xfff
8036; GFX9-NEXT:    v_mov_b32_e32 v0, s2
8037; GFX9-NEXT:    global_store_dwordx2 v1, v[0:1], s[0:1]
8038; GFX9-NEXT:    s_endpgm
8039  %r = urem i64 %x, 4096
8040  store i64 %r, i64 addrspace(1)* %out
8041  ret void
8042}
8043
8044define amdgpu_kernel void @urem_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %x, i64 %y) {
8045; CHECK-LABEL: @urem_i64_pow2_shl_denom(
8046; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]]
8047; CHECK-NEXT:    [[R:%.*]] = urem i64 [[X:%.*]], [[SHL_Y]]
8048; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
8049; CHECK-NEXT:    ret void
8050;
8051; GFX6-LABEL: urem_i64_pow2_shl_denom:
8052; GFX6:       ; %bb.0:
8053; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
8054; GFX6-NEXT:    s_load_dword s8, s[0:1], 0xd
8055; GFX6-NEXT:    s_mov_b32 s3, 0xf000
8056; GFX6-NEXT:    s_mov_b32 s2, -1
8057; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8058; GFX6-NEXT:    s_mov_b32 s0, s4
8059; GFX6-NEXT:    s_mov_b32 s1, s5
8060; GFX6-NEXT:    s_mov_b32 s5, 0
8061; GFX6-NEXT:    s_movk_i32 s4, 0x1000
8062; GFX6-NEXT:    s_lshl_b64 s[4:5], s[4:5], s8
8063; GFX6-NEXT:    s_add_u32 s4, s4, -1
8064; GFX6-NEXT:    s_addc_u32 s5, s5, -1
8065; GFX6-NEXT:    s_and_b64 s[4:5], s[6:7], s[4:5]
8066; GFX6-NEXT:    v_mov_b32_e32 v0, s4
8067; GFX6-NEXT:    v_mov_b32_e32 v1, s5
8068; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
8069; GFX6-NEXT:    s_endpgm
8070;
8071; GFX9-LABEL: urem_i64_pow2_shl_denom:
8072; GFX9:       ; %bb.0:
8073; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
8074; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x34
8075; GFX9-NEXT:    s_mov_b32 s1, 0
8076; GFX9-NEXT:    s_movk_i32 s0, 0x1000
8077; GFX9-NEXT:    v_mov_b32_e32 v2, 0
8078; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8079; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s2
8080; GFX9-NEXT:    s_add_u32 s0, s0, -1
8081; GFX9-NEXT:    s_addc_u32 s1, s1, -1
8082; GFX9-NEXT:    s_and_b64 s[0:1], s[6:7], s[0:1]
8083; GFX9-NEXT:    v_mov_b32_e32 v0, s0
8084; GFX9-NEXT:    v_mov_b32_e32 v1, s1
8085; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
8086; GFX9-NEXT:    s_endpgm
8087  %shl.y = shl i64 4096, %y
8088  %r = urem i64 %x, %shl.y
8089  store i64 %r, i64 addrspace(1)* %out
8090  ret void
8091}
8092
8093define amdgpu_kernel void @urem_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
8094; CHECK-LABEL: @urem_v2i64_pow2k_denom(
8095; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
8096; CHECK-NEXT:    [[TMP2:%.*]] = urem i64 [[TMP1]], 4096
8097; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
8098; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
8099; CHECK-NEXT:    [[TMP5:%.*]] = urem i64 [[TMP4]], 4096
8100; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
8101; CHECK-NEXT:    store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
8102; CHECK-NEXT:    ret void
8103;
8104; GFX6-LABEL: urem_v2i64_pow2k_denom:
8105; GFX6:       ; %bb.0:
8106; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
8107; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
8108; GFX6-NEXT:    s_movk_i32 s8, 0xfff
8109; GFX6-NEXT:    v_mov_b32_e32 v1, 0
8110; GFX6-NEXT:    s_mov_b32 s7, 0xf000
8111; GFX6-NEXT:    s_mov_b32 s6, -1
8112; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8113; GFX6-NEXT:    s_and_b32 s0, s0, s8
8114; GFX6-NEXT:    s_and_b32 s1, s2, s8
8115; GFX6-NEXT:    v_mov_b32_e32 v0, s0
8116; GFX6-NEXT:    v_mov_b32_e32 v2, s1
8117; GFX6-NEXT:    v_mov_b32_e32 v3, v1
8118; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
8119; GFX6-NEXT:    s_endpgm
8120;
8121; GFX9-LABEL: urem_v2i64_pow2k_denom:
8122; GFX9:       ; %bb.0:
8123; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
8124; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
8125; GFX9-NEXT:    s_movk_i32 s0, 0xfff
8126; GFX9-NEXT:    v_mov_b32_e32 v1, 0
8127; GFX9-NEXT:    v_mov_b32_e32 v3, v1
8128; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8129; GFX9-NEXT:    s_and_b32 s1, s4, s0
8130; GFX9-NEXT:    s_and_b32 s0, s6, s0
8131; GFX9-NEXT:    v_mov_b32_e32 v0, s1
8132; GFX9-NEXT:    v_mov_b32_e32 v2, s0
8133; GFX9-NEXT:    global_store_dwordx4 v1, v[0:3], s[2:3]
8134; GFX9-NEXT:    s_endpgm
8135  %r = urem <2 x i64> %x, <i64 4096, i64 4096>
8136  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
8137  ret void
8138}
8139
8140define amdgpu_kernel void @urem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
8141; CHECK-LABEL: @urem_v2i64_pow2_shl_denom(
8142; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.*]]
8143; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
8144; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 0
8145; CHECK-NEXT:    [[TMP3:%.*]] = urem i64 [[TMP1]], [[TMP2]]
8146; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i64 0
8147; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 1
8148; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
8149; CHECK-NEXT:    [[TMP7:%.*]] = urem i64 [[TMP5]], [[TMP6]]
8150; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
8151; CHECK-NEXT:    store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
8152; CHECK-NEXT:    ret void
8153;
8154; GFX6-LABEL: urem_v2i64_pow2_shl_denom:
8155; GFX6:       ; %bb.0:
8156; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
8157; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
8158; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
8159; GFX6-NEXT:    s_mov_b32 s13, 0
8160; GFX6-NEXT:    s_movk_i32 s12, 0x1000
8161; GFX6-NEXT:    s_mov_b32 s7, 0xf000
8162; GFX6-NEXT:    s_mov_b32 s6, -1
8163; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8164; GFX6-NEXT:    s_lshl_b64 s[2:3], s[12:13], s2
8165; GFX6-NEXT:    s_lshl_b64 s[0:1], s[12:13], s0
8166; GFX6-NEXT:    s_add_u32 s0, s0, -1
8167; GFX6-NEXT:    s_addc_u32 s1, s1, -1
8168; GFX6-NEXT:    s_and_b64 s[0:1], s[8:9], s[0:1]
8169; GFX6-NEXT:    s_add_u32 s2, s2, -1
8170; GFX6-NEXT:    s_addc_u32 s3, s3, -1
8171; GFX6-NEXT:    s_and_b64 s[2:3], s[10:11], s[2:3]
8172; GFX6-NEXT:    v_mov_b32_e32 v0, s0
8173; GFX6-NEXT:    v_mov_b32_e32 v1, s1
8174; GFX6-NEXT:    v_mov_b32_e32 v2, s2
8175; GFX6-NEXT:    v_mov_b32_e32 v3, s3
8176; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
8177; GFX6-NEXT:    s_endpgm
8178;
8179; GFX9-LABEL: urem_v2i64_pow2_shl_denom:
8180; GFX9:       ; %bb.0:
8181; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
8182; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
8183; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x44
8184; GFX9-NEXT:    s_mov_b32 s1, 0
8185; GFX9-NEXT:    s_movk_i32 s0, 0x1000
8186; GFX9-NEXT:    v_mov_b32_e32 v4, 0
8187; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8188; GFX9-NEXT:    s_lshl_b64 s[10:11], s[0:1], s10
8189; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s8
8190; GFX9-NEXT:    s_add_u32 s0, s0, -1
8191; GFX9-NEXT:    s_addc_u32 s1, s1, -1
8192; GFX9-NEXT:    s_and_b64 s[0:1], s[4:5], s[0:1]
8193; GFX9-NEXT:    s_add_u32 s4, s10, -1
8194; GFX9-NEXT:    s_addc_u32 s5, s11, -1
8195; GFX9-NEXT:    s_and_b64 s[4:5], s[6:7], s[4:5]
8196; GFX9-NEXT:    v_mov_b32_e32 v0, s0
8197; GFX9-NEXT:    v_mov_b32_e32 v1, s1
8198; GFX9-NEXT:    v_mov_b32_e32 v2, s4
8199; GFX9-NEXT:    v_mov_b32_e32 v3, s5
8200; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
8201; GFX9-NEXT:    s_endpgm
8202  %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
8203  %r = urem <2 x i64> %x, %shl.y
8204  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
8205  ret void
8206}
8207
8208define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
8209; CHECK-LABEL: @sdiv_i64_oddk_denom(
8210; CHECK-NEXT:    [[R:%.*]] = sdiv i64 [[X:%.*]], 1235195
8211; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
8212; CHECK-NEXT:    ret void
8213;
8214; GFX6-LABEL: sdiv_i64_oddk_denom:
8215; GFX6:       ; %bb.0:
8216; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f800000
8217; GFX6-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
8218; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
8219; GFX6-NEXT:    s_mov_b32 s2, 0xffed2705
8220; GFX6-NEXT:    v_mov_b32_e32 v8, 0
8221; GFX6-NEXT:    v_mov_b32_e32 v7, 0
8222; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
8223; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
8224; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
8225; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
8226; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
8227; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
8228; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
8229; GFX6-NEXT:    s_mov_b32 s7, 0xf000
8230; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
8231; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s2
8232; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s2
8233; GFX6-NEXT:    s_mov_b32 s6, -1
8234; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8235; GFX6-NEXT:    s_mov_b32 s4, s8
8236; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8237; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
8238; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
8239; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v4
8240; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v2
8241; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v2
8242; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
8243; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
8244; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
8245; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
8246; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v3, vcc
8247; GFX6-NEXT:    s_mov_b32 s5, s9
8248; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
8249; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
8250; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
8251; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8252; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
8253; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
8254; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
8255; GFX6-NEXT:    v_mul_lo_u32 v4, v2, s2
8256; GFX6-NEXT:    v_mul_hi_u32 v5, s2, v0
8257; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
8258; GFX6-NEXT:    v_mul_lo_u32 v5, v0, s2
8259; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, v0, v4
8260; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v4
8261; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v4
8262; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v5
8263; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v5
8264; GFX6-NEXT:    v_mul_lo_u32 v5, v2, v5
8265; GFX6-NEXT:    v_mul_hi_u32 v6, v2, v4
8266; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
8267; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, v8, v12, vcc
8268; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v4
8269; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v10, v5
8270; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v11, v9, vcc
8271; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v6, v7, vcc
8272; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
8273; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
8274; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
8275; GFX6-NEXT:    s_ashr_i32 s2, s11, 31
8276; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
8277; GFX6-NEXT:    s_add_u32 s0, s10, s2
8278; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
8279; GFX6-NEXT:    s_mov_b32 s3, s2
8280; GFX6-NEXT:    s_addc_u32 s1, s11, s2
8281; GFX6-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
8282; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
8283; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v1
8284; GFX6-NEXT:    v_mul_hi_u32 v3, s0, v0
8285; GFX6-NEXT:    v_mul_hi_u32 v4, s0, v1
8286; GFX6-NEXT:    v_mul_hi_u32 v5, s1, v1
8287; GFX6-NEXT:    v_mul_lo_u32 v1, s1, v1
8288; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8289; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
8290; GFX6-NEXT:    v_mul_lo_u32 v4, s1, v0
8291; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
8292; GFX6-NEXT:    s_mov_b32 s3, 0x12d8fb
8293; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
8294; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
8295; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
8296; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
8297; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
8298; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s3
8299; GFX6-NEXT:    v_mul_hi_u32 v3, s3, v0
8300; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s3
8301; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8302; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s0, v4
8303; GFX6-NEXT:    v_mov_b32_e32 v3, s1
8304; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v3, v2, vcc
8305; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s3, v4
8306; GFX6-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
8307; GFX6-NEXT:    s_mov_b32 s0, 0x12d8fa
8308; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v3
8309; GFX6-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
8310; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v5
8311; GFX6-NEXT:    v_cndmask_b32_e32 v3, -1, v3, vcc
8312; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 2, v0
8313; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
8314; GFX6-NEXT:    v_add_i32_e32 v7, vcc, 1, v0
8315; GFX6-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v4
8316; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v1, vcc
8317; GFX6-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]
8318; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v2
8319; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
8320; GFX6-NEXT:    v_cndmask_b32_e64 v2, -1, v4, s[0:1]
8321; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v2
8322; GFX6-NEXT:    v_cndmask_b32_e32 v2, v7, v5, vcc
8323; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
8324; GFX6-NEXT:    v_cndmask_b32_e32 v3, v8, v6, vcc
8325; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
8326; GFX6-NEXT:    v_xor_b32_e32 v0, s2, v0
8327; GFX6-NEXT:    v_xor_b32_e32 v1, s2, v1
8328; GFX6-NEXT:    v_mov_b32_e32 v2, s2
8329; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
8330; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
8331; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
8332; GFX6-NEXT:    s_endpgm
8333;
8334; GFX9-LABEL: sdiv_i64_oddk_denom:
8335; GFX9:       ; %bb.0:
8336; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f800000
8337; GFX9-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
8338; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
8339; GFX9-NEXT:    s_mov_b32 s8, 0xffed2705
8340; GFX9-NEXT:    v_mov_b32_e32 v7, 0
8341; GFX9-NEXT:    v_mov_b32_e32 v5, 0
8342; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
8343; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
8344; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
8345; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
8346; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
8347; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
8348; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
8349; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v0
8350; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s8
8351; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s8
8352; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
8353; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
8354; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
8355; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
8356; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
8357; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v2
8358; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
8359; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
8360; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
8361; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
8362; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
8363; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
8364; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
8365; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
8366; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
8367; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
8368; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
8369; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
8370; GFX9-NEXT:    v_mul_lo_u32 v4, v2, s8
8371; GFX9-NEXT:    v_mul_hi_u32 v6, s8, v0
8372; GFX9-NEXT:    v_mul_lo_u32 v8, v0, s8
8373; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
8374; GFX9-NEXT:    v_add_u32_e32 v4, v6, v4
8375; GFX9-NEXT:    v_sub_u32_e32 v4, v4, v0
8376; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v4
8377; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v8
8378; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v4
8379; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v8
8380; GFX9-NEXT:    v_mul_lo_u32 v8, v2, v8
8381; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
8382; GFX9-NEXT:    v_mul_hi_u32 v6, v2, v4
8383; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v7, v12, vcc
8384; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
8385; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v8
8386; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v9, vcc
8387; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
8388; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v8, v2
8389; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
8390; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
8391; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8392; GFX9-NEXT:    s_ashr_i32 s2, s7, 31
8393; GFX9-NEXT:    s_add_u32 s0, s6, s2
8394; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
8395; GFX9-NEXT:    s_mov_b32 s3, s2
8396; GFX9-NEXT:    s_addc_u32 s1, s7, s2
8397; GFX9-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
8398; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
8399; GFX9-NEXT:    v_mul_lo_u32 v2, s0, v1
8400; GFX9-NEXT:    v_mul_hi_u32 v3, s0, v0
8401; GFX9-NEXT:    v_mul_hi_u32 v4, s0, v1
8402; GFX9-NEXT:    v_mul_hi_u32 v6, s1, v1
8403; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v1
8404; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
8405; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
8406; GFX9-NEXT:    v_mul_lo_u32 v4, s1, v0
8407; GFX9-NEXT:    v_mul_hi_u32 v0, s1, v0
8408; GFX9-NEXT:    s_mov_b32 s3, 0x12d8fb
8409; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
8410; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
8411; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
8412; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
8413; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
8414; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s3
8415; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s3
8416; GFX9-NEXT:    v_mul_hi_u32 v3, s3, v0
8417; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, s0, v4
8418; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
8419; GFX9-NEXT:    v_mov_b32_e32 v3, s1
8420; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v3, v2, vcc
8421; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s3, v4
8422; GFX9-NEXT:    v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc
8423; GFX9-NEXT:    s_mov_b32 s3, 0x12d8fa
8424; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s3, v3
8425; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
8426; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v6
8427; GFX9-NEXT:    v_cndmask_b32_e32 v3, -1, v3, vcc
8428; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, 2, v0
8429; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v1, vcc
8430; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 1, v0
8431; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
8432; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s3, v4
8433; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
8434; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
8435; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v3
8436; GFX9-NEXT:    v_cndmask_b32_e32 v2, -1, v4, vcc
8437; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
8438; GFX9-NEXT:    v_cndmask_b32_e64 v2, v8, v6, s[0:1]
8439; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
8440; GFX9-NEXT:    v_cndmask_b32_e64 v3, v9, v7, s[0:1]
8441; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
8442; GFX9-NEXT:    v_xor_b32_e32 v0, s2, v0
8443; GFX9-NEXT:    v_xor_b32_e32 v1, s2, v1
8444; GFX9-NEXT:    v_mov_b32_e32 v2, s2
8445; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s2, v0
8446; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
8447; GFX9-NEXT:    global_store_dwordx2 v5, v[0:1], s[4:5]
8448; GFX9-NEXT:    s_endpgm
8449  %r = sdiv i64 %x, 1235195
8450  store i64 %r, i64 addrspace(1)* %out
8451  ret void
8452}
8453
8454define amdgpu_kernel void @sdiv_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) {
8455; CHECK-LABEL: @sdiv_i64_pow2k_denom(
8456; CHECK-NEXT:    [[R:%.*]] = sdiv i64 [[X:%.*]], 4096
8457; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
8458; CHECK-NEXT:    ret void
8459;
8460; GFX6-LABEL: sdiv_i64_pow2k_denom:
8461; GFX6:       ; %bb.0:
8462; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
8463; GFX6-NEXT:    s_mov_b32 s7, 0xf000
8464; GFX6-NEXT:    s_mov_b32 s6, -1
8465; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8466; GFX6-NEXT:    s_mov_b32 s4, s0
8467; GFX6-NEXT:    s_ashr_i32 s0, s3, 31
8468; GFX6-NEXT:    s_lshr_b32 s0, s0, 20
8469; GFX6-NEXT:    s_add_u32 s0, s2, s0
8470; GFX6-NEXT:    s_mov_b32 s5, s1
8471; GFX6-NEXT:    s_addc_u32 s1, s3, 0
8472; GFX6-NEXT:    s_ashr_i64 s[0:1], s[0:1], 12
8473; GFX6-NEXT:    v_mov_b32_e32 v0, s0
8474; GFX6-NEXT:    v_mov_b32_e32 v1, s1
8475; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
8476; GFX6-NEXT:    s_endpgm
8477;
8478; GFX9-LABEL: sdiv_i64_pow2k_denom:
8479; GFX9:       ; %bb.0:
8480; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
8481; GFX9-NEXT:    v_mov_b32_e32 v2, 0
8482; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8483; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
8484; GFX9-NEXT:    s_lshr_b32 s4, s4, 20
8485; GFX9-NEXT:    s_add_u32 s2, s2, s4
8486; GFX9-NEXT:    s_addc_u32 s3, s3, 0
8487; GFX9-NEXT:    s_ashr_i64 s[2:3], s[2:3], 12
8488; GFX9-NEXT:    v_mov_b32_e32 v0, s2
8489; GFX9-NEXT:    v_mov_b32_e32 v1, s3
8490; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
8491; GFX9-NEXT:    s_endpgm
8492  %r = sdiv i64 %x, 4096
8493  store i64 %r, i64 addrspace(1)* %out
8494  ret void
8495}
8496
8497define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %x, i64 %y) {
8498; CHECK-LABEL: @sdiv_i64_pow2_shl_denom(
8499; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]]
8500; CHECK-NEXT:    [[R:%.*]] = sdiv i64 [[X:%.*]], [[SHL_Y]]
8501; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
8502; CHECK-NEXT:    ret void
8503;
8504; GFX6-LABEL: sdiv_i64_pow2_shl_denom:
8505; GFX6:       ; %bb.0:
8506; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xd
8507; GFX6-NEXT:    s_mov_b32 s3, 0
8508; GFX6-NEXT:    s_movk_i32 s2, 0x1000
8509; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
8510; GFX6-NEXT:    s_mov_b32 s7, 0xf000
8511; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8512; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
8513; GFX6-NEXT:    s_ashr_i32 s12, s3, 31
8514; GFX6-NEXT:    s_add_u32 s2, s2, s12
8515; GFX6-NEXT:    s_mov_b32 s13, s12
8516; GFX6-NEXT:    s_addc_u32 s3, s3, s12
8517; GFX6-NEXT:    s_xor_b64 s[2:3], s[2:3], s[12:13]
8518; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s2
8519; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s3
8520; GFX6-NEXT:    s_sub_u32 s4, 0, s2
8521; GFX6-NEXT:    s_subb_u32 s5, 0, s3
8522; GFX6-NEXT:    s_ashr_i32 s14, s11, 31
8523; GFX6-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
8524; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
8525; GFX6-NEXT:    s_mov_b32 s15, s14
8526; GFX6-NEXT:    s_mov_b32 s6, -1
8527; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
8528; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
8529; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
8530; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
8531; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
8532; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
8533; GFX6-NEXT:    v_mul_hi_u32 v3, s4, v0
8534; GFX6-NEXT:    v_mul_lo_u32 v2, s4, v1
8535; GFX6-NEXT:    v_mul_lo_u32 v5, s5, v0
8536; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v0
8537; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8538; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
8539; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
8540; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
8541; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
8542; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
8543; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
8544; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
8545; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
8546; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
8547; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
8548; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
8549; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
8550; GFX6-NEXT:    v_mov_b32_e32 v4, 0
8551; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
8552; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8553; GFX6-NEXT:    v_mov_b32_e32 v6, 0
8554; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
8555; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
8556; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
8557; GFX6-NEXT:    v_mul_lo_u32 v5, s4, v2
8558; GFX6-NEXT:    v_mul_hi_u32 v7, s4, v0
8559; GFX6-NEXT:    v_mul_lo_u32 v8, s5, v0
8560; GFX6-NEXT:    s_mov_b32 s5, s9
8561; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
8562; GFX6-NEXT:    v_mul_lo_u32 v7, s4, v0
8563; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
8564; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v5
8565; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v5
8566; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v7
8567; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v7
8568; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v7
8569; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v5
8570; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
8571; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
8572; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v5
8573; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
8574; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
8575; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
8576; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
8577; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
8578; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
8579; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
8580; GFX6-NEXT:    s_add_u32 s0, s10, s14
8581; GFX6-NEXT:    s_addc_u32 s1, s11, s14
8582; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
8583; GFX6-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
8584; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
8585; GFX6-NEXT:    v_mul_lo_u32 v2, s10, v1
8586; GFX6-NEXT:    v_mul_hi_u32 v3, s10, v0
8587; GFX6-NEXT:    v_mul_hi_u32 v5, s10, v1
8588; GFX6-NEXT:    v_mul_hi_u32 v7, s11, v1
8589; GFX6-NEXT:    v_mul_lo_u32 v1, s11, v1
8590; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8591; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
8592; GFX6-NEXT:    v_mul_lo_u32 v5, s11, v0
8593; GFX6-NEXT:    v_mul_hi_u32 v0, s11, v0
8594; GFX6-NEXT:    s_mov_b32 s4, s8
8595; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
8596; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
8597; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
8598; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
8599; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
8600; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
8601; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
8602; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v0
8603; GFX6-NEXT:    v_mov_b32_e32 v5, s3
8604; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8605; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v0
8606; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
8607; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s11, v2
8608; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s10, v3
8609; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
8610; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s2, v3
8611; GFX6-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
8612; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v4
8613; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
8614; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v5
8615; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
8616; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v4
8617; GFX6-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
8618; GFX6-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
8619; GFX6-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
8620; GFX6-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
8621; GFX6-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
8622; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
8623; GFX6-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
8624; GFX6-NEXT:    v_mov_b32_e32 v6, s11
8625; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
8626; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2
8627; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
8628; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
8629; GFX6-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
8630; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v2
8631; GFX6-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
8632; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
8633; GFX6-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
8634; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
8635; GFX6-NEXT:    s_xor_b64 s[0:1], s[14:15], s[12:13]
8636; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
8637; GFX6-NEXT:    v_xor_b32_e32 v0, s0, v0
8638; GFX6-NEXT:    v_xor_b32_e32 v1, s1, v1
8639; GFX6-NEXT:    v_mov_b32_e32 v2, s1
8640; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
8641; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
8642; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
8643; GFX6-NEXT:    s_endpgm
8644;
8645; GFX9-LABEL: sdiv_i64_pow2_shl_denom:
8646; GFX9:       ; %bb.0:
8647; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x34
8648; GFX9-NEXT:    s_mov_b32 s3, 0
8649; GFX9-NEXT:    s_movk_i32 s2, 0x1000
8650; GFX9-NEXT:    v_mov_b32_e32 v2, 0
8651; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8652; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
8653; GFX9-NEXT:    s_ashr_i32 s8, s3, 31
8654; GFX9-NEXT:    s_add_u32 s2, s2, s8
8655; GFX9-NEXT:    s_mov_b32 s9, s8
8656; GFX9-NEXT:    s_addc_u32 s3, s3, s8
8657; GFX9-NEXT:    s_xor_b64 s[10:11], s[2:3], s[8:9]
8658; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s10
8659; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s11
8660; GFX9-NEXT:    s_sub_u32 s12, 0, s10
8661; GFX9-NEXT:    s_subb_u32 s4, 0, s11
8662; GFX9-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
8663; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
8664; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
8665; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
8666; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
8667; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
8668; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
8669; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
8670; GFX9-NEXT:    v_mul_hi_u32 v4, s12, v0
8671; GFX9-NEXT:    v_mul_lo_u32 v3, s12, v1
8672; GFX9-NEXT:    v_mul_lo_u32 v6, s4, v0
8673; GFX9-NEXT:    v_mul_lo_u32 v5, s12, v0
8674; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
8675; GFX9-NEXT:    v_add_u32_e32 v3, v3, v6
8676; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v5
8677; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v3
8678; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v3
8679; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v5
8680; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
8681; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
8682; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v3
8683; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
8684; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
8685; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v5, v4
8686; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
8687; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v2, vcc
8688; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
8689; GFX9-NEXT:    v_mov_b32_e32 v6, 0
8690; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v3
8691; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
8692; GFX9-NEXT:    v_addc_co_u32_e64 v3, vcc, v1, v4, s[2:3]
8693; GFX9-NEXT:    v_mul_lo_u32 v5, s12, v3
8694; GFX9-NEXT:    v_mul_hi_u32 v7, s12, v0
8695; GFX9-NEXT:    v_mul_lo_u32 v8, s4, v0
8696; GFX9-NEXT:    v_mul_lo_u32 v9, s12, v0
8697; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
8698; GFX9-NEXT:    v_add_u32_e32 v5, v7, v5
8699; GFX9-NEXT:    v_add_u32_e32 v5, v5, v8
8700; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v5
8701; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v9
8702; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v5
8703; GFX9-NEXT:    v_mul_hi_u32 v8, v3, v9
8704; GFX9-NEXT:    v_mul_lo_u32 v9, v3, v9
8705; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
8706; GFX9-NEXT:    v_mul_hi_u32 v7, v3, v5
8707; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
8708; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v5
8709; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
8710; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
8711; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
8712; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
8713; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8714; GFX9-NEXT:    s_ashr_i32 s12, s7, 31
8715; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
8716; GFX9-NEXT:    v_add_u32_e32 v1, v1, v4
8717; GFX9-NEXT:    s_add_u32 s0, s6, s12
8718; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v5, s[2:3]
8719; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
8720; GFX9-NEXT:    s_mov_b32 s13, s12
8721; GFX9-NEXT:    s_addc_u32 s1, s7, s12
8722; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[12:13]
8723; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
8724; GFX9-NEXT:    v_mul_lo_u32 v3, s6, v1
8725; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v0
8726; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v1
8727; GFX9-NEXT:    v_mul_hi_u32 v7, s7, v1
8728; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
8729; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
8730; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
8731; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v0
8732; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
8733; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
8734; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v4, v0, vcc
8735; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v2, vcc
8736; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
8737; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v6, v3, vcc
8738; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v1
8739; GFX9-NEXT:    v_mul_hi_u32 v4, s10, v0
8740; GFX9-NEXT:    v_mul_lo_u32 v5, s11, v0
8741; GFX9-NEXT:    v_mov_b32_e32 v6, s11
8742; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
8743; GFX9-NEXT:    v_mul_lo_u32 v4, s10, v0
8744; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
8745; GFX9-NEXT:    v_sub_u32_e32 v5, s7, v3
8746; GFX9-NEXT:    v_sub_co_u32_e64 v4, s[0:1], s6, v4
8747; GFX9-NEXT:    v_subb_co_u32_e64 v5, vcc, v5, v6, s[0:1]
8748; GFX9-NEXT:    v_subrev_co_u32_e32 v6, vcc, s10, v4
8749; GFX9-NEXT:    v_subbrev_co_u32_e32 v5, vcc, 0, v5, vcc
8750; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v5
8751; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
8752; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v6
8753; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
8754; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v5
8755; GFX9-NEXT:    v_cndmask_b32_e32 v5, v7, v6, vcc
8756; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, 2, v0
8757; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v1, vcc
8758; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 1, v0
8759; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
8760; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v5
8761; GFX9-NEXT:    v_cndmask_b32_e64 v5, v9, v7, s[2:3]
8762; GFX9-NEXT:    v_mov_b32_e32 v7, s7
8763; GFX9-NEXT:    v_subb_co_u32_e64 v3, vcc, v7, v3, s[0:1]
8764; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
8765; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
8766; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v4
8767; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
8768; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v3
8769; GFX9-NEXT:    v_cndmask_b32_e32 v3, v7, v4, vcc
8770; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
8771; GFX9-NEXT:    v_cndmask_b32_e64 v3, v8, v6, s[2:3]
8772; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
8773; GFX9-NEXT:    s_xor_b64 s[0:1], s[12:13], s[8:9]
8774; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
8775; GFX9-NEXT:    v_xor_b32_e32 v0, s0, v0
8776; GFX9-NEXT:    v_xor_b32_e32 v1, s1, v1
8777; GFX9-NEXT:    v_mov_b32_e32 v3, s1
8778; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s0, v0
8779; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
8780; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
8781; GFX9-NEXT:    s_endpgm
8782  %shl.y = shl i64 4096, %y
8783  %r = sdiv i64 %x, %shl.y
8784  store i64 %r, i64 addrspace(1)* %out
8785  ret void
8786}
8787
8788define amdgpu_kernel void @sdiv_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
8789; CHECK-LABEL: @sdiv_v2i64_pow2k_denom(
8790; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
8791; CHECK-NEXT:    [[TMP2:%.*]] = sdiv i64 [[TMP1]], 4096
8792; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
8793; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
8794; CHECK-NEXT:    [[TMP5:%.*]] = sdiv i64 [[TMP4]], 4096
8795; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
8796; CHECK-NEXT:    store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
8797; CHECK-NEXT:    ret void
8798;
8799; GFX6-LABEL: sdiv_v2i64_pow2k_denom:
8800; GFX6:       ; %bb.0:
8801; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
8802; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
8803; GFX6-NEXT:    s_mov_b32 s7, 0xf000
8804; GFX6-NEXT:    s_mov_b32 s6, -1
8805; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8806; GFX6-NEXT:    s_ashr_i32 s8, s1, 31
8807; GFX6-NEXT:    s_lshr_b32 s8, s8, 20
8808; GFX6-NEXT:    s_add_u32 s0, s0, s8
8809; GFX6-NEXT:    s_addc_u32 s1, s1, 0
8810; GFX6-NEXT:    s_ashr_i32 s8, s3, 31
8811; GFX6-NEXT:    s_ashr_i64 s[0:1], s[0:1], 12
8812; GFX6-NEXT:    s_lshr_b32 s8, s8, 20
8813; GFX6-NEXT:    s_add_u32 s2, s2, s8
8814; GFX6-NEXT:    s_addc_u32 s3, s3, 0
8815; GFX6-NEXT:    s_ashr_i64 s[2:3], s[2:3], 12
8816; GFX6-NEXT:    v_mov_b32_e32 v0, s0
8817; GFX6-NEXT:    v_mov_b32_e32 v1, s1
8818; GFX6-NEXT:    v_mov_b32_e32 v2, s2
8819; GFX6-NEXT:    v_mov_b32_e32 v3, s3
8820; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
8821; GFX6-NEXT:    s_endpgm
8822;
8823; GFX9-LABEL: sdiv_v2i64_pow2k_denom:
8824; GFX9:       ; %bb.0:
8825; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
8826; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
8827; GFX9-NEXT:    v_mov_b32_e32 v4, 0
8828; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8829; GFX9-NEXT:    s_ashr_i32 s0, s5, 31
8830; GFX9-NEXT:    s_lshr_b32 s0, s0, 20
8831; GFX9-NEXT:    s_add_u32 s0, s4, s0
8832; GFX9-NEXT:    s_addc_u32 s1, s5, 0
8833; GFX9-NEXT:    s_ashr_i32 s4, s7, 31
8834; GFX9-NEXT:    s_ashr_i64 s[0:1], s[0:1], 12
8835; GFX9-NEXT:    s_lshr_b32 s4, s4, 20
8836; GFX9-NEXT:    s_add_u32 s4, s6, s4
8837; GFX9-NEXT:    s_addc_u32 s5, s7, 0
8838; GFX9-NEXT:    s_ashr_i64 s[4:5], s[4:5], 12
8839; GFX9-NEXT:    v_mov_b32_e32 v0, s0
8840; GFX9-NEXT:    v_mov_b32_e32 v1, s1
8841; GFX9-NEXT:    v_mov_b32_e32 v2, s4
8842; GFX9-NEXT:    v_mov_b32_e32 v3, s5
8843; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
8844; GFX9-NEXT:    s_endpgm
8845  %r = sdiv <2 x i64> %x, <i64 4096, i64 4096>
8846  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
8847  ret void
8848}
8849
8850define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
8851; CHECK-LABEL: @ssdiv_v2i64_mixed_pow2k_denom(
8852; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
8853; CHECK-NEXT:    [[TMP2:%.*]] = sdiv i64 [[TMP1]], 4096
8854; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
8855; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
8856; CHECK-NEXT:    [[TMP5:%.*]] = sdiv i64 [[TMP4]], 4095
8857; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
8858; CHECK-NEXT:    store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
8859; CHECK-NEXT:    ret void
8860;
8861; GFX6-LABEL: ssdiv_v2i64_mixed_pow2k_denom:
8862; GFX6:       ; %bb.0:
8863; GFX6-NEXT:    v_mov_b32_e32 v0, 0x457ff000
8864; GFX6-NEXT:    v_mov_b32_e32 v1, 0x4f800000
8865; GFX6-NEXT:    v_mac_f32_e32 v0, 0, v1
8866; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
8867; GFX6-NEXT:    s_movk_i32 s6, 0xf001
8868; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
8869; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
8870; GFX6-NEXT:    s_mov_b32 s7, 0xf000
8871; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
8872; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
8873; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
8874; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
8875; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
8876; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
8877; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8878; GFX6-NEXT:    s_ashr_i32 s0, s9, 31
8879; GFX6-NEXT:    s_lshr_b32 s0, s0, 20
8880; GFX6-NEXT:    v_mul_hi_u32 v2, s6, v0
8881; GFX6-NEXT:    v_mul_lo_u32 v3, v1, s6
8882; GFX6-NEXT:    s_add_u32 s2, s8, s0
8883; GFX6-NEXT:    s_addc_u32 s3, s9, 0
8884; GFX6-NEXT:    s_ashr_i32 s8, s11, 31
8885; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
8886; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s6
8887; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
8888; GFX6-NEXT:    v_mul_lo_u32 v4, v0, v2
8889; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
8890; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v3
8891; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
8892; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
8893; GFX6-NEXT:    s_ashr_i64 s[2:3], s[2:3], 12
8894; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
8895; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
8896; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
8897; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
8898; GFX6-NEXT:    s_mov_b32 s9, s8
8899; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
8900; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
8901; GFX6-NEXT:    v_mov_b32_e32 v4, 0
8902; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
8903; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8904; GFX6-NEXT:    v_mov_b32_e32 v6, 0
8905; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
8906; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
8907; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
8908; GFX6-NEXT:    v_mul_lo_u32 v5, v2, s6
8909; GFX6-NEXT:    v_mul_hi_u32 v7, s6, v0
8910; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
8911; GFX6-NEXT:    v_mul_lo_u32 v7, v0, s6
8912; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, v0, v5
8913; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v5
8914; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v5
8915; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v7
8916; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v7
8917; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v7
8918; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v5
8919; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
8920; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
8921; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v5
8922; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
8923; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
8924; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
8925; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
8926; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
8927; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
8928; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
8929; GFX6-NEXT:    s_add_u32 s0, s10, s8
8930; GFX6-NEXT:    s_addc_u32 s1, s11, s8
8931; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
8932; GFX6-NEXT:    s_xor_b64 s[0:1], s[0:1], s[8:9]
8933; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
8934; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v1
8935; GFX6-NEXT:    v_mul_hi_u32 v3, s0, v0
8936; GFX6-NEXT:    v_mul_hi_u32 v5, s0, v1
8937; GFX6-NEXT:    v_mul_hi_u32 v7, s1, v1
8938; GFX6-NEXT:    v_mul_lo_u32 v1, s1, v1
8939; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8940; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
8941; GFX6-NEXT:    v_mul_lo_u32 v5, s1, v0
8942; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
8943; GFX6-NEXT:    s_movk_i32 s9, 0xfff
8944; GFX6-NEXT:    s_mov_b32 s6, -1
8945; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
8946; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
8947; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
8948; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
8949; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
8950; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s9
8951; GFX6-NEXT:    v_mul_hi_u32 v3, s9, v0
8952; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s9
8953; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8954; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s0, v4
8955; GFX6-NEXT:    v_mov_b32_e32 v3, s1
8956; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v3, v2, vcc
8957; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s9, v4
8958; GFX6-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
8959; GFX6-NEXT:    s_movk_i32 s0, 0xffe
8960; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v3
8961; GFX6-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
8962; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v5
8963; GFX6-NEXT:    v_cndmask_b32_e32 v3, -1, v3, vcc
8964; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 2, v0
8965; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
8966; GFX6-NEXT:    v_add_i32_e32 v7, vcc, 1, v0
8967; GFX6-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v4
8968; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v1, vcc
8969; GFX6-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]
8970; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v2
8971; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
8972; GFX6-NEXT:    v_cndmask_b32_e64 v2, -1, v4, s[0:1]
8973; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v2
8974; GFX6-NEXT:    v_cndmask_b32_e32 v2, v7, v5, vcc
8975; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
8976; GFX6-NEXT:    v_cndmask_b32_e32 v3, v8, v6, vcc
8977; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
8978; GFX6-NEXT:    v_xor_b32_e32 v0, s8, v0
8979; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v0
8980; GFX6-NEXT:    v_xor_b32_e32 v1, s8, v1
8981; GFX6-NEXT:    v_mov_b32_e32 v3, s8
8982; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v1, v3, vcc
8983; GFX6-NEXT:    v_mov_b32_e32 v0, s2
8984; GFX6-NEXT:    v_mov_b32_e32 v1, s3
8985; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
8986; GFX6-NEXT:    s_endpgm
8987;
8988; GFX9-LABEL: ssdiv_v2i64_mixed_pow2k_denom:
8989; GFX9:       ; %bb.0:
8990; GFX9-NEXT:    v_mov_b32_e32 v0, 0x457ff000
8991; GFX9-NEXT:    v_mov_b32_e32 v1, 0x4f800000
8992; GFX9-NEXT:    v_mac_f32_e32 v0, 0, v1
8993; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
8994; GFX9-NEXT:    s_movk_i32 s8, 0xf001
8995; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
8996; GFX9-NEXT:    v_mov_b32_e32 v4, 0
8997; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
8998; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
8999; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
9000; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
9001; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
9002; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
9003; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
9004; GFX9-NEXT:    s_ashr_i32 s2, s5, 31
9005; GFX9-NEXT:    s_lshr_b32 s2, s2, 20
9006; GFX9-NEXT:    v_mul_hi_u32 v2, s8, v0
9007; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s8
9008; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s8
9009; GFX9-NEXT:    s_add_u32 s4, s4, s2
9010; GFX9-NEXT:    s_addc_u32 s5, s5, 0
9011; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
9012; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
9013; GFX9-NEXT:    v_mul_lo_u32 v3, v0, v2
9014; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v5
9015; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
9016; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
9017; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
9018; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v6, v3
9019; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
9020; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v5
9021; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v5
9022; GFX9-NEXT:    s_ashr_i64 s[4:5], s[4:5], 12
9023; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v7, v3
9024; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
9025; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v4, vcc
9026; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
9027; GFX9-NEXT:    v_mov_b32_e32 v6, 0
9028; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
9029; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
9030; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
9031; GFX9-NEXT:    v_mul_lo_u32 v5, v2, s8
9032; GFX9-NEXT:    v_mul_hi_u32 v7, s8, v0
9033; GFX9-NEXT:    v_mul_lo_u32 v8, v0, s8
9034; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
9035; GFX9-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
9036; GFX9-NEXT:    v_add_u32_e32 v5, v7, v5
9037; GFX9-NEXT:    v_sub_u32_e32 v5, v5, v0
9038; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v5
9039; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v8
9040; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v5
9041; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v8
9042; GFX9-NEXT:    v_mul_lo_u32 v8, v2, v8
9043; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
9044; GFX9-NEXT:    v_mul_hi_u32 v7, v2, v5
9045; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
9046; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v5
9047; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v8
9048; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v9, vcc
9049; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v4, vcc
9050; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v8, v2
9051; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
9052; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v5, s[2:3]
9053; GFX9-NEXT:    s_ashr_i32 s2, s7, 31
9054; GFX9-NEXT:    s_add_u32 s6, s6, s2
9055; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
9056; GFX9-NEXT:    s_mov_b32 s3, s2
9057; GFX9-NEXT:    s_addc_u32 s7, s7, s2
9058; GFX9-NEXT:    s_xor_b64 s[6:7], s[6:7], s[2:3]
9059; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
9060; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
9061; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
9062; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v1
9063; GFX9-NEXT:    v_mul_hi_u32 v7, s7, v1
9064; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
9065; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
9066; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
9067; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v0
9068; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
9069; GFX9-NEXT:    s_movk_i32 s3, 0xfff
9070; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v5, v2
9071; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
9072; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v4, vcc
9073; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
9074; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v6, v2, vcc
9075; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s3
9076; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s3
9077; GFX9-NEXT:    v_mul_hi_u32 v3, s3, v0
9078; GFX9-NEXT:    v_sub_co_u32_e32 v5, vcc, s6, v5
9079; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
9080; GFX9-NEXT:    v_mov_b32_e32 v3, s7
9081; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v3, v2, vcc
9082; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s3, v5
9083; GFX9-NEXT:    v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc
9084; GFX9-NEXT:    s_movk_i32 s3, 0xffe
9085; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s3, v3
9086; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
9087; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v6
9088; GFX9-NEXT:    v_cndmask_b32_e32 v3, -1, v3, vcc
9089; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, 2, v0
9090; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v1, vcc
9091; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 1, v0
9092; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
9093; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s3, v5
9094; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
9095; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
9096; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v3
9097; GFX9-NEXT:    v_cndmask_b32_e32 v2, -1, v5, vcc
9098; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
9099; GFX9-NEXT:    v_cndmask_b32_e64 v2, v8, v6, s[0:1]
9100; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
9101; GFX9-NEXT:    v_cndmask_b32_e64 v3, v9, v7, s[0:1]
9102; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
9103; GFX9-NEXT:    v_xor_b32_e32 v0, s2, v0
9104; GFX9-NEXT:    v_subrev_co_u32_e32 v2, vcc, s2, v0
9105; GFX9-NEXT:    v_xor_b32_e32 v1, s2, v1
9106; GFX9-NEXT:    v_mov_b32_e32 v3, s2
9107; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v1, v3, vcc
9108; GFX9-NEXT:    v_mov_b32_e32 v0, s4
9109; GFX9-NEXT:    v_mov_b32_e32 v1, s5
9110; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
9111; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[8:9]
9112; GFX9-NEXT:    s_endpgm
9113  %r = sdiv <2 x i64> %x, <i64 4096, i64 4095>
9114  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
9115  ret void
9116}
9117
9118define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
9119; CHECK-LABEL: @sdiv_v2i64_pow2_shl_denom(
9120; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.*]]
9121; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
9122; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 0
9123; CHECK-NEXT:    [[TMP3:%.*]] = sdiv i64 [[TMP1]], [[TMP2]]
9124; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i64 0
9125; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 1
9126; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
9127; CHECK-NEXT:    [[TMP7:%.*]] = sdiv i64 [[TMP5]], [[TMP6]]
9128; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
9129; CHECK-NEXT:    store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
9130; CHECK-NEXT:    ret void
9131;
9132; GFX6-LABEL: sdiv_v2i64_pow2_shl_denom:
9133; GFX6:       ; %bb.0:
9134; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x11
9135; GFX6-NEXT:    s_mov_b32 s3, 0
9136; GFX6-NEXT:    s_movk_i32 s2, 0x1000
9137; GFX6-NEXT:    s_mov_b32 s18, 0x4f800000
9138; GFX6-NEXT:    s_mov_b32 s19, 0x5f7ffffc
9139; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
9140; GFX6-NEXT:    s_lshl_b64 s[12:13], s[2:3], s6
9141; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
9142; GFX6-NEXT:    s_ashr_i32 s16, s3, 31
9143; GFX6-NEXT:    s_add_u32 s2, s2, s16
9144; GFX6-NEXT:    s_mov_b32 s17, s16
9145; GFX6-NEXT:    s_addc_u32 s3, s3, s16
9146; GFX6-NEXT:    s_xor_b64 s[14:15], s[2:3], s[16:17]
9147; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s14
9148; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s15
9149; GFX6-NEXT:    s_mov_b32 s20, 0x2f800000
9150; GFX6-NEXT:    s_mov_b32 s21, 0xcf800000
9151; GFX6-NEXT:    s_sub_u32 s6, 0, s14
9152; GFX6-NEXT:    v_mac_f32_e32 v0, s18, v1
9153; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
9154; GFX6-NEXT:    s_subb_u32 s7, 0, s15
9155; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
9156; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
9157; GFX6-NEXT:    v_mul_f32_e32 v0, s19, v0
9158; GFX6-NEXT:    v_mul_f32_e32 v1, s20, v0
9159; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
9160; GFX6-NEXT:    v_mac_f32_e32 v0, s21, v1
9161; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
9162; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
9163; GFX6-NEXT:    v_mul_hi_u32 v3, s6, v0
9164; GFX6-NEXT:    v_mul_lo_u32 v2, s6, v1
9165; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v0
9166; GFX6-NEXT:    v_mul_lo_u32 v5, s6, v0
9167; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9168; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
9169; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
9170; GFX6-NEXT:    v_mul_hi_u32 v4, v0, v5
9171; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
9172; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
9173; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
9174; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
9175; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v6, vcc
9176; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v5
9177; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v5
9178; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
9179; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v4, v5, vcc
9180; GFX6-NEXT:    v_mov_b32_e32 v4, 0
9181; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
9182; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9183; GFX6-NEXT:    v_mov_b32_e32 v6, 0
9184; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v2
9185; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
9186; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
9187; GFX6-NEXT:    v_mul_lo_u32 v5, s6, v2
9188; GFX6-NEXT:    v_mul_hi_u32 v7, s6, v0
9189; GFX6-NEXT:    v_mul_lo_u32 v8, s7, v0
9190; GFX6-NEXT:    s_mov_b32 s7, 0xf000
9191; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
9192; GFX6-NEXT:    v_mul_lo_u32 v7, s6, v0
9193; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
9194; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v5
9195; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v5
9196; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v7
9197; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v7
9198; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v7
9199; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v5
9200; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
9201; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
9202; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v5
9203; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
9204; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
9205; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
9206; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
9207; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
9208; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
9209; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
9210; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
9211; GFX6-NEXT:    s_ashr_i32 s2, s9, 31
9212; GFX6-NEXT:    s_add_u32 s0, s8, s2
9213; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
9214; GFX6-NEXT:    s_mov_b32 s3, s2
9215; GFX6-NEXT:    s_addc_u32 s1, s9, s2
9216; GFX6-NEXT:    s_xor_b64 s[8:9], s[0:1], s[2:3]
9217; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
9218; GFX6-NEXT:    v_mul_lo_u32 v2, s8, v1
9219; GFX6-NEXT:    v_mul_hi_u32 v3, s8, v0
9220; GFX6-NEXT:    v_mul_hi_u32 v5, s8, v1
9221; GFX6-NEXT:    v_mul_hi_u32 v7, s9, v1
9222; GFX6-NEXT:    v_mul_lo_u32 v1, s9, v1
9223; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9224; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
9225; GFX6-NEXT:    v_mul_lo_u32 v5, s9, v0
9226; GFX6-NEXT:    v_mul_hi_u32 v0, s9, v0
9227; GFX6-NEXT:    s_xor_b64 s[2:3], s[2:3], s[16:17]
9228; GFX6-NEXT:    s_mov_b32 s6, -1
9229; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
9230; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
9231; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
9232; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
9233; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
9234; GFX6-NEXT:    v_mul_lo_u32 v2, s14, v1
9235; GFX6-NEXT:    v_mul_hi_u32 v3, s14, v0
9236; GFX6-NEXT:    v_mul_lo_u32 v5, s15, v0
9237; GFX6-NEXT:    v_mov_b32_e32 v7, s15
9238; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9239; GFX6-NEXT:    v_mul_lo_u32 v3, s14, v0
9240; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
9241; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s9, v2
9242; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s8, v3
9243; GFX6-NEXT:    v_subb_u32_e64 v5, s[0:1], v5, v7, vcc
9244; GFX6-NEXT:    v_subrev_i32_e64 v7, s[0:1], s14, v3
9245; GFX6-NEXT:    v_subbrev_u32_e64 v5, s[0:1], 0, v5, s[0:1]
9246; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s15, v5
9247; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[0:1]
9248; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s14, v7
9249; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
9250; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s15, v5
9251; GFX6-NEXT:    v_cndmask_b32_e64 v5, v8, v7, s[0:1]
9252; GFX6-NEXT:    v_add_i32_e64 v7, s[0:1], 2, v0
9253; GFX6-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
9254; GFX6-NEXT:    v_add_i32_e64 v9, s[0:1], 1, v0
9255; GFX6-NEXT:    v_addc_u32_e64 v10, s[0:1], 0, v1, s[0:1]
9256; GFX6-NEXT:    s_ashr_i32 s8, s13, 31
9257; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
9258; GFX6-NEXT:    s_add_u32 s12, s12, s8
9259; GFX6-NEXT:    v_cndmask_b32_e64 v5, v10, v8, s[0:1]
9260; GFX6-NEXT:    v_mov_b32_e32 v8, s9
9261; GFX6-NEXT:    s_mov_b32 s9, s8
9262; GFX6-NEXT:    s_addc_u32 s13, s13, s8
9263; GFX6-NEXT:    s_xor_b64 s[12:13], s[12:13], s[8:9]
9264; GFX6-NEXT:    v_cvt_f32_u32_e32 v10, s12
9265; GFX6-NEXT:    v_cvt_f32_u32_e32 v11, s13
9266; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v8, v2, vcc
9267; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s15, v2
9268; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
9269; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s14, v3
9270; GFX6-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
9271; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s15, v2
9272; GFX6-NEXT:    v_mac_f32_e32 v10, s18, v11
9273; GFX6-NEXT:    v_cndmask_b32_e32 v2, v8, v3, vcc
9274; GFX6-NEXT:    v_rcp_f32_e32 v3, v10
9275; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
9276; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
9277; GFX6-NEXT:    s_sub_u32 s14, 0, s12
9278; GFX6-NEXT:    v_mul_f32_e32 v3, s19, v3
9279; GFX6-NEXT:    v_mul_f32_e32 v5, s20, v3
9280; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
9281; GFX6-NEXT:    v_mac_f32_e32 v3, s21, v5
9282; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
9283; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v5
9284; GFX6-NEXT:    v_cndmask_b32_e64 v2, v9, v7, s[0:1]
9285; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
9286; GFX6-NEXT:    v_mul_hi_u32 v2, s14, v3
9287; GFX6-NEXT:    v_mul_lo_u32 v7, s14, v5
9288; GFX6-NEXT:    s_subb_u32 s15, 0, s13
9289; GFX6-NEXT:    v_mul_lo_u32 v8, s15, v3
9290; GFX6-NEXT:    v_xor_b32_e32 v0, s2, v0
9291; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v7
9292; GFX6-NEXT:    v_mul_lo_u32 v7, s14, v3
9293; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
9294; GFX6-NEXT:    v_mul_lo_u32 v8, v3, v2
9295; GFX6-NEXT:    v_mul_hi_u32 v10, v3, v2
9296; GFX6-NEXT:    v_mul_hi_u32 v9, v3, v7
9297; GFX6-NEXT:    v_mul_hi_u32 v11, v5, v2
9298; GFX6-NEXT:    v_mul_lo_u32 v2, v5, v2
9299; GFX6-NEXT:    v_xor_b32_e32 v1, s3, v1
9300; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
9301; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
9302; GFX6-NEXT:    v_mul_lo_u32 v10, v5, v7
9303; GFX6-NEXT:    v_mul_hi_u32 v7, v5, v7
9304; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
9305; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v9, v7, vcc
9306; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v11, v4, vcc
9307; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
9308; GFX6-NEXT:    v_add_i32_e64 v2, s[0:1], v3, v2
9309; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v6, v8, vcc
9310; GFX6-NEXT:    v_addc_u32_e64 v3, vcc, v5, v7, s[0:1]
9311; GFX6-NEXT:    v_mul_lo_u32 v8, s14, v3
9312; GFX6-NEXT:    v_mul_hi_u32 v9, s14, v2
9313; GFX6-NEXT:    v_mul_lo_u32 v10, s15, v2
9314; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
9315; GFX6-NEXT:    v_mul_lo_u32 v9, s14, v2
9316; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
9317; GFX6-NEXT:    v_mul_lo_u32 v12, v2, v8
9318; GFX6-NEXT:    v_mul_hi_u32 v14, v2, v8
9319; GFX6-NEXT:    v_mul_hi_u32 v13, v2, v9
9320; GFX6-NEXT:    v_mul_hi_u32 v11, v3, v9
9321; GFX6-NEXT:    v_mul_lo_u32 v9, v3, v9
9322; GFX6-NEXT:    v_mul_hi_u32 v10, v3, v8
9323; GFX6-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
9324; GFX6-NEXT:    v_addc_u32_e32 v13, vcc, 0, v14, vcc
9325; GFX6-NEXT:    v_mul_lo_u32 v3, v3, v8
9326; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v12, v9
9327; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, v13, v11, vcc
9328; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v10, v4, vcc
9329; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v9, v3
9330; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v6, v8, vcc
9331; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
9332; GFX6-NEXT:    s_ashr_i32 s14, s11, 31
9333; GFX6-NEXT:    v_addc_u32_e64 v5, vcc, v5, v8, s[0:1]
9334; GFX6-NEXT:    s_add_u32 s0, s10, s14
9335; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
9336; GFX6-NEXT:    s_mov_b32 s15, s14
9337; GFX6-NEXT:    s_addc_u32 s1, s11, s14
9338; GFX6-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
9339; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
9340; GFX6-NEXT:    v_mul_lo_u32 v5, s10, v3
9341; GFX6-NEXT:    v_mul_hi_u32 v7, s10, v2
9342; GFX6-NEXT:    v_mul_hi_u32 v9, s10, v3
9343; GFX6-NEXT:    v_mul_hi_u32 v10, s11, v3
9344; GFX6-NEXT:    v_mul_lo_u32 v3, s11, v3
9345; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
9346; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v9, vcc
9347; GFX6-NEXT:    v_mul_lo_u32 v9, s11, v2
9348; GFX6-NEXT:    v_mul_hi_u32 v2, s11, v2
9349; GFX6-NEXT:    v_mov_b32_e32 v8, s3
9350; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
9351; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v2, vcc
9352; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v10, v4, vcc
9353; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
9354; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v4, vcc
9355; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v3
9356; GFX6-NEXT:    v_mul_hi_u32 v5, s12, v2
9357; GFX6-NEXT:    v_mul_lo_u32 v6, s13, v2
9358; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
9359; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
9360; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
9361; GFX6-NEXT:    v_mul_lo_u32 v5, s12, v2
9362; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
9363; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, s11, v4
9364; GFX6-NEXT:    v_mov_b32_e32 v7, s13
9365; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s10, v5
9366; GFX6-NEXT:    v_subb_u32_e64 v6, s[0:1], v6, v7, vcc
9367; GFX6-NEXT:    v_subrev_i32_e64 v7, s[0:1], s12, v5
9368; GFX6-NEXT:    v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1]
9369; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s13, v6
9370; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[0:1]
9371; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s12, v7
9372; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
9373; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s13, v6
9374; GFX6-NEXT:    v_cndmask_b32_e64 v6, v8, v7, s[0:1]
9375; GFX6-NEXT:    v_add_i32_e64 v7, s[0:1], 2, v2
9376; GFX6-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v3, s[0:1]
9377; GFX6-NEXT:    v_add_i32_e64 v9, s[0:1], 1, v2
9378; GFX6-NEXT:    v_addc_u32_e64 v10, s[0:1], 0, v3, s[0:1]
9379; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
9380; GFX6-NEXT:    v_cndmask_b32_e64 v6, v10, v8, s[0:1]
9381; GFX6-NEXT:    v_mov_b32_e32 v8, s11
9382; GFX6-NEXT:    v_subb_u32_e32 v4, vcc, v8, v4, vcc
9383; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s13, v4
9384; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
9385; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v5
9386; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
9387; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v4
9388; GFX6-NEXT:    v_cndmask_b32_e32 v4, v8, v5, vcc
9389; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
9390; GFX6-NEXT:    v_cndmask_b32_e64 v4, v9, v7, s[0:1]
9391; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
9392; GFX6-NEXT:    s_xor_b64 s[0:1], s[14:15], s[8:9]
9393; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
9394; GFX6-NEXT:    v_xor_b32_e32 v2, s0, v2
9395; GFX6-NEXT:    v_xor_b32_e32 v3, s1, v3
9396; GFX6-NEXT:    v_mov_b32_e32 v4, s1
9397; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s0, v2
9398; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
9399; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
9400; GFX6-NEXT:    s_endpgm
9401;
9402; GFX9-LABEL: sdiv_v2i64_pow2_shl_denom:
9403; GFX9:       ; %bb.0:
9404; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x44
9405; GFX9-NEXT:    s_mov_b32 s3, 0
9406; GFX9-NEXT:    s_movk_i32 s2, 0x1000
9407; GFX9-NEXT:    s_mov_b32 s18, 0x4f800000
9408; GFX9-NEXT:    s_mov_b32 s19, 0x5f7ffffc
9409; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
9410; GFX9-NEXT:    s_lshl_b64 s[8:9], s[2:3], s6
9411; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
9412; GFX9-NEXT:    s_ashr_i32 s12, s3, 31
9413; GFX9-NEXT:    s_add_u32 s2, s2, s12
9414; GFX9-NEXT:    s_mov_b32 s13, s12
9415; GFX9-NEXT:    s_addc_u32 s3, s3, s12
9416; GFX9-NEXT:    s_xor_b64 s[10:11], s[2:3], s[12:13]
9417; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s10
9418; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s11
9419; GFX9-NEXT:    s_mov_b32 s20, 0x2f800000
9420; GFX9-NEXT:    s_mov_b32 s21, 0xcf800000
9421; GFX9-NEXT:    s_sub_u32 s14, 0, s10
9422; GFX9-NEXT:    v_mac_f32_e32 v0, s18, v1
9423; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
9424; GFX9-NEXT:    s_subb_u32 s4, 0, s11
9425; GFX9-NEXT:    v_mov_b32_e32 v6, 0
9426; GFX9-NEXT:    v_mul_f32_e32 v0, s19, v0
9427; GFX9-NEXT:    v_mul_f32_e32 v1, s20, v0
9428; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
9429; GFX9-NEXT:    v_mac_f32_e32 v0, s21, v1
9430; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
9431; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
9432; GFX9-NEXT:    v_mul_hi_u32 v3, s14, v0
9433; GFX9-NEXT:    v_mul_lo_u32 v2, s14, v1
9434; GFX9-NEXT:    v_mul_lo_u32 v5, s4, v0
9435; GFX9-NEXT:    v_mul_lo_u32 v4, s14, v0
9436; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
9437; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
9438; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
9439; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
9440; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
9441; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
9442; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
9443; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
9444; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
9445; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
9446; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
9447; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v7, v3
9448; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
9449; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
9450; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
9451; GFX9-NEXT:    v_mov_b32_e32 v5, 0
9452; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
9453; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
9454; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
9455; GFX9-NEXT:    v_mul_lo_u32 v4, s14, v2
9456; GFX9-NEXT:    v_mul_hi_u32 v7, s14, v0
9457; GFX9-NEXT:    v_mul_lo_u32 v8, s4, v0
9458; GFX9-NEXT:    v_mul_lo_u32 v9, s14, v0
9459; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
9460; GFX9-NEXT:    v_add_u32_e32 v4, v7, v4
9461; GFX9-NEXT:    v_add_u32_e32 v4, v4, v8
9462; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v4
9463; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v9
9464; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v4
9465; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v9
9466; GFX9-NEXT:    v_mul_lo_u32 v9, v2, v9
9467; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
9468; GFX9-NEXT:    v_mul_hi_u32 v7, v2, v4
9469; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
9470; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
9471; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
9472; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
9473; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v6, vcc
9474; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v8, v2
9475; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
9476; GFX9-NEXT:    s_ashr_i32 s14, s5, 31
9477; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v4, vcc
9478; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
9479; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
9480; GFX9-NEXT:    s_add_u32 s2, s4, s14
9481; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
9482; GFX9-NEXT:    s_addc_u32 s3, s5, s14
9483; GFX9-NEXT:    s_mov_b32 s15, s14
9484; GFX9-NEXT:    s_xor_b64 s[16:17], s[2:3], s[14:15]
9485; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
9486; GFX9-NEXT:    v_mul_lo_u32 v2, s16, v1
9487; GFX9-NEXT:    v_mul_hi_u32 v3, s16, v0
9488; GFX9-NEXT:    v_mul_hi_u32 v4, s16, v1
9489; GFX9-NEXT:    v_mul_hi_u32 v7, s17, v1
9490; GFX9-NEXT:    v_mul_lo_u32 v1, s17, v1
9491; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
9492; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
9493; GFX9-NEXT:    v_mul_lo_u32 v4, s17, v0
9494; GFX9-NEXT:    v_mul_hi_u32 v0, s17, v0
9495; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
9496; GFX9-NEXT:    s_xor_b64 s[12:13], s[14:15], s[12:13]
9497; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
9498; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
9499; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
9500; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
9501; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
9502; GFX9-NEXT:    v_mul_lo_u32 v2, s10, v1
9503; GFX9-NEXT:    v_mul_hi_u32 v3, s10, v0
9504; GFX9-NEXT:    v_mul_lo_u32 v4, s11, v0
9505; GFX9-NEXT:    v_mov_b32_e32 v7, s11
9506; GFX9-NEXT:    s_ashr_i32 s14, s9, 31
9507; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
9508; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v0
9509; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
9510; GFX9-NEXT:    v_sub_u32_e32 v4, s17, v2
9511; GFX9-NEXT:    s_mov_b32 s15, s14
9512; GFX9-NEXT:    v_sub_co_u32_e64 v3, s[0:1], s16, v3
9513; GFX9-NEXT:    v_subb_co_u32_e64 v4, vcc, v4, v7, s[0:1]
9514; GFX9-NEXT:    v_subrev_co_u32_e32 v7, vcc, s10, v3
9515; GFX9-NEXT:    v_subbrev_co_u32_e32 v4, vcc, 0, v4, vcc
9516; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v4
9517; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
9518; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v7
9519; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
9520; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v4
9521; GFX9-NEXT:    v_cndmask_b32_e32 v4, v8, v7, vcc
9522; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, 2, v0
9523; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v1, vcc
9524; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, 1, v0
9525; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v1, vcc
9526; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v4
9527; GFX9-NEXT:    v_cndmask_b32_e64 v4, v10, v8, s[2:3]
9528; GFX9-NEXT:    v_mov_b32_e32 v8, s17
9529; GFX9-NEXT:    v_subb_co_u32_e64 v2, vcc, v8, v2, s[0:1]
9530; GFX9-NEXT:    s_add_u32 s0, s8, s14
9531; GFX9-NEXT:    s_addc_u32 s1, s9, s14
9532; GFX9-NEXT:    s_xor_b64 s[8:9], s[0:1], s[14:15]
9533; GFX9-NEXT:    v_cvt_f32_u32_e32 v10, s8
9534; GFX9-NEXT:    v_cvt_f32_u32_e32 v11, s9
9535; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v2
9536; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
9537; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
9538; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
9539; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v2
9540; GFX9-NEXT:    v_mac_f32_e32 v10, s18, v11
9541; GFX9-NEXT:    v_cndmask_b32_e32 v2, v8, v3, vcc
9542; GFX9-NEXT:    v_rcp_f32_e32 v3, v10
9543; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
9544; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
9545; GFX9-NEXT:    v_cndmask_b32_e64 v2, v9, v7, s[2:3]
9546; GFX9-NEXT:    v_mul_f32_e32 v3, s19, v3
9547; GFX9-NEXT:    v_mul_f32_e32 v4, s20, v3
9548; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
9549; GFX9-NEXT:    v_mac_f32_e32 v3, s21, v4
9550; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
9551; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
9552; GFX9-NEXT:    s_sub_u32 s2, 0, s8
9553; GFX9-NEXT:    s_subb_u32 s3, 0, s9
9554; GFX9-NEXT:    v_mul_hi_u32 v7, s2, v3
9555; GFX9-NEXT:    v_mul_lo_u32 v8, s2, v4
9556; GFX9-NEXT:    v_mul_lo_u32 v9, s3, v3
9557; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
9558; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v3
9559; GFX9-NEXT:    v_add_u32_e32 v7, v7, v8
9560; GFX9-NEXT:    v_add_u32_e32 v7, v7, v9
9561; GFX9-NEXT:    v_mul_lo_u32 v8, v3, v7
9562; GFX9-NEXT:    v_mul_hi_u32 v9, v3, v2
9563; GFX9-NEXT:    v_mul_hi_u32 v10, v3, v7
9564; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v7
9565; GFX9-NEXT:    v_mul_lo_u32 v7, v4, v7
9566; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
9567; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
9568; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v2
9569; GFX9-NEXT:    v_mul_hi_u32 v2, v4, v2
9570; GFX9-NEXT:    s_ashr_i32 s10, s7, 31
9571; GFX9-NEXT:    s_mov_b32 s11, s10
9572; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v8
9573; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v9, v2, vcc
9574; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v6, vcc
9575; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v7
9576; GFX9-NEXT:    v_add_co_u32_e64 v2, s[0:1], v3, v2
9577; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v5, v8, vcc
9578; GFX9-NEXT:    v_addc_co_u32_e64 v3, vcc, v4, v7, s[0:1]
9579; GFX9-NEXT:    v_mul_lo_u32 v8, s2, v3
9580; GFX9-NEXT:    v_mul_hi_u32 v9, s2, v2
9581; GFX9-NEXT:    v_mul_lo_u32 v10, s3, v2
9582; GFX9-NEXT:    v_mul_lo_u32 v11, s2, v2
9583; GFX9-NEXT:    v_add_u32_e32 v4, v4, v7
9584; GFX9-NEXT:    v_add_u32_e32 v8, v9, v8
9585; GFX9-NEXT:    v_add_u32_e32 v8, v8, v10
9586; GFX9-NEXT:    v_mul_lo_u32 v12, v2, v8
9587; GFX9-NEXT:    v_mul_hi_u32 v13, v2, v11
9588; GFX9-NEXT:    v_mul_hi_u32 v14, v2, v8
9589; GFX9-NEXT:    v_mul_hi_u32 v10, v3, v11
9590; GFX9-NEXT:    v_mul_lo_u32 v11, v3, v11
9591; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v13, v12
9592; GFX9-NEXT:    v_mul_hi_u32 v9, v3, v8
9593; GFX9-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v14, vcc
9594; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v8
9595; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v12, v11
9596; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v10, vcc
9597; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v9, v6, vcc
9598; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v10, v3
9599; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v5, v8, vcc
9600; GFX9-NEXT:    v_addc_co_u32_e64 v4, vcc, v4, v8, s[0:1]
9601; GFX9-NEXT:    s_add_u32 s0, s6, s10
9602; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
9603; GFX9-NEXT:    s_addc_u32 s1, s7, s10
9604; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[10:11]
9605; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
9606; GFX9-NEXT:    v_mul_lo_u32 v4, s6, v3
9607; GFX9-NEXT:    v_mul_hi_u32 v7, s6, v2
9608; GFX9-NEXT:    v_mul_hi_u32 v9, s6, v3
9609; GFX9-NEXT:    v_mul_hi_u32 v10, s7, v3
9610; GFX9-NEXT:    v_mul_lo_u32 v3, s7, v3
9611; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v7, v4
9612; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v9, vcc
9613; GFX9-NEXT:    v_mul_lo_u32 v9, s7, v2
9614; GFX9-NEXT:    v_mul_hi_u32 v2, s7, v2
9615; GFX9-NEXT:    v_xor_b32_e32 v0, s12, v0
9616; GFX9-NEXT:    v_xor_b32_e32 v1, s13, v1
9617; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v9, v4
9618; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v2, vcc
9619; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v6, vcc
9620; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
9621; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
9622; GFX9-NEXT:    v_mul_lo_u32 v4, s8, v3
9623; GFX9-NEXT:    v_mul_hi_u32 v5, s8, v2
9624; GFX9-NEXT:    v_mul_lo_u32 v7, s9, v2
9625; GFX9-NEXT:    v_mov_b32_e32 v8, s13
9626; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s12, v0
9627; GFX9-NEXT:    v_add_u32_e32 v4, v5, v4
9628; GFX9-NEXT:    v_mul_lo_u32 v5, s8, v2
9629; GFX9-NEXT:    v_add_u32_e32 v4, v4, v7
9630; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v8, vcc
9631; GFX9-NEXT:    v_sub_u32_e32 v7, s7, v4
9632; GFX9-NEXT:    v_mov_b32_e32 v8, s9
9633; GFX9-NEXT:    v_sub_co_u32_e64 v5, s[0:1], s6, v5
9634; GFX9-NEXT:    v_subb_co_u32_e64 v7, vcc, v7, v8, s[0:1]
9635; GFX9-NEXT:    v_subrev_co_u32_e32 v8, vcc, s8, v5
9636; GFX9-NEXT:    v_subbrev_co_u32_e32 v7, vcc, 0, v7, vcc
9637; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v7
9638; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
9639; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v8
9640; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
9641; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v7
9642; GFX9-NEXT:    v_cndmask_b32_e32 v7, v9, v8, vcc
9643; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 2, v2
9644; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v3, vcc
9645; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, 1, v2
9646; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v3, vcc
9647; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v7
9648; GFX9-NEXT:    v_cndmask_b32_e64 v7, v11, v9, s[2:3]
9649; GFX9-NEXT:    v_mov_b32_e32 v9, s7
9650; GFX9-NEXT:    v_subb_co_u32_e64 v4, vcc, v9, v4, s[0:1]
9651; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v4
9652; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
9653; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v5
9654; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
9655; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v4
9656; GFX9-NEXT:    v_cndmask_b32_e32 v4, v9, v5, vcc
9657; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
9658; GFX9-NEXT:    v_cndmask_b32_e64 v4, v10, v8, s[2:3]
9659; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
9660; GFX9-NEXT:    s_xor_b64 s[0:1], s[10:11], s[14:15]
9661; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc
9662; GFX9-NEXT:    v_xor_b32_e32 v2, s0, v2
9663; GFX9-NEXT:    v_xor_b32_e32 v3, s1, v3
9664; GFX9-NEXT:    v_mov_b32_e32 v4, s1
9665; GFX9-NEXT:    v_subrev_co_u32_e32 v2, vcc, s0, v2
9666; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v3, v4, vcc
9667; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
9668; GFX9-NEXT:    global_store_dwordx4 v6, v[0:3], s[4:5]
9669; GFX9-NEXT:    s_endpgm
9670  %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
9671  %r = sdiv <2 x i64> %x, %shl.y
9672  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
9673  ret void
9674}
9675
9676define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
9677; CHECK-LABEL: @srem_i64_oddk_denom(
9678; CHECK-NEXT:    [[R:%.*]] = srem i64 [[X:%.*]], 1235195
9679; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
9680; CHECK-NEXT:    ret void
9681;
9682; GFX6-LABEL: srem_i64_oddk_denom:
9683; GFX6:       ; %bb.0:
9684; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f800000
9685; GFX6-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
9686; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
9687; GFX6-NEXT:    s_mov_b32 s2, 0xffed2705
9688; GFX6-NEXT:    v_mov_b32_e32 v8, 0
9689; GFX6-NEXT:    v_mov_b32_e32 v7, 0
9690; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
9691; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
9692; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
9693; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
9694; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
9695; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
9696; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
9697; GFX6-NEXT:    s_mov_b32 s7, 0xf000
9698; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
9699; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s2
9700; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s2
9701; GFX6-NEXT:    s_mov_b32 s6, -1
9702; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
9703; GFX6-NEXT:    s_mov_b32 s4, s8
9704; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9705; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
9706; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
9707; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v4
9708; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v2
9709; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v2
9710; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
9711; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
9712; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
9713; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
9714; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v3, vcc
9715; GFX6-NEXT:    s_mov_b32 s5, s9
9716; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
9717; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
9718; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
9719; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9720; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
9721; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
9722; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
9723; GFX6-NEXT:    v_mul_lo_u32 v4, v2, s2
9724; GFX6-NEXT:    v_mul_hi_u32 v5, s2, v0
9725; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
9726; GFX6-NEXT:    v_mul_lo_u32 v5, v0, s2
9727; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, v0, v4
9728; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v4
9729; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v4
9730; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v5
9731; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v5
9732; GFX6-NEXT:    v_mul_lo_u32 v5, v2, v5
9733; GFX6-NEXT:    v_mul_hi_u32 v6, v2, v4
9734; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
9735; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, v8, v12, vcc
9736; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v4
9737; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v10, v5
9738; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v11, v9, vcc
9739; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v6, v7, vcc
9740; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
9741; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
9742; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
9743; GFX6-NEXT:    s_ashr_i32 s2, s11, 31
9744; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
9745; GFX6-NEXT:    s_add_u32 s0, s10, s2
9746; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
9747; GFX6-NEXT:    s_mov_b32 s3, s2
9748; GFX6-NEXT:    s_addc_u32 s1, s11, s2
9749; GFX6-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
9750; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
9751; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v1
9752; GFX6-NEXT:    v_mul_hi_u32 v3, s0, v0
9753; GFX6-NEXT:    v_mul_hi_u32 v4, s0, v1
9754; GFX6-NEXT:    v_mul_hi_u32 v5, s1, v1
9755; GFX6-NEXT:    v_mul_lo_u32 v1, s1, v1
9756; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9757; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
9758; GFX6-NEXT:    v_mul_lo_u32 v4, s1, v0
9759; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
9760; GFX6-NEXT:    s_mov_b32 s3, 0x12d8fb
9761; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
9762; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
9763; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
9764; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
9765; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
9766; GFX6-NEXT:    v_mul_hi_u32 v2, s3, v0
9767; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s3
9768; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s3
9769; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
9770; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
9771; GFX6-NEXT:    v_mov_b32_e32 v2, s1
9772; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
9773; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v0
9774; GFX6-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v1, vcc
9775; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s3, v2
9776; GFX6-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v3, vcc
9777; GFX6-NEXT:    s_mov_b32 s0, 0x12d8fa
9778; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v2
9779; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
9780; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
9781; GFX6-NEXT:    v_cndmask_b32_e32 v6, -1, v6, vcc
9782; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
9783; GFX6-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v0
9784; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
9785; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
9786; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
9787; GFX6-NEXT:    v_cndmask_b32_e64 v5, -1, v5, s[0:1]
9788; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
9789; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
9790; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
9791; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
9792; GFX6-NEXT:    v_xor_b32_e32 v0, s2, v0
9793; GFX6-NEXT:    v_xor_b32_e32 v1, s2, v1
9794; GFX6-NEXT:    v_mov_b32_e32 v2, s2
9795; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
9796; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
9797; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
9798; GFX6-NEXT:    s_endpgm
9799;
9800; GFX9-LABEL: srem_i64_oddk_denom:
9801; GFX9:       ; %bb.0:
9802; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f800000
9803; GFX9-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
9804; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
9805; GFX9-NEXT:    s_mov_b32 s8, 0xffed2705
9806; GFX9-NEXT:    v_mov_b32_e32 v7, 0
9807; GFX9-NEXT:    v_mov_b32_e32 v5, 0
9808; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
9809; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
9810; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
9811; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
9812; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
9813; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
9814; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
9815; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v0
9816; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s8
9817; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s8
9818; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
9819; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
9820; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
9821; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
9822; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
9823; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v2
9824; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
9825; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
9826; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
9827; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
9828; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
9829; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
9830; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
9831; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
9832; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
9833; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
9834; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
9835; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
9836; GFX9-NEXT:    v_mul_lo_u32 v4, v2, s8
9837; GFX9-NEXT:    v_mul_hi_u32 v6, s8, v0
9838; GFX9-NEXT:    v_mul_lo_u32 v8, v0, s8
9839; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
9840; GFX9-NEXT:    v_add_u32_e32 v4, v6, v4
9841; GFX9-NEXT:    v_sub_u32_e32 v4, v4, v0
9842; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v4
9843; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v8
9844; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v4
9845; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v8
9846; GFX9-NEXT:    v_mul_lo_u32 v8, v2, v8
9847; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
9848; GFX9-NEXT:    v_mul_hi_u32 v6, v2, v4
9849; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v7, v12, vcc
9850; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
9851; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v8
9852; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v9, vcc
9853; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
9854; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v8, v2
9855; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
9856; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
9857; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
9858; GFX9-NEXT:    s_ashr_i32 s2, s7, 31
9859; GFX9-NEXT:    s_add_u32 s0, s6, s2
9860; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
9861; GFX9-NEXT:    s_mov_b32 s3, s2
9862; GFX9-NEXT:    s_addc_u32 s1, s7, s2
9863; GFX9-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
9864; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
9865; GFX9-NEXT:    v_mul_lo_u32 v2, s0, v1
9866; GFX9-NEXT:    v_mul_hi_u32 v3, s0, v0
9867; GFX9-NEXT:    v_mul_hi_u32 v4, s0, v1
9868; GFX9-NEXT:    v_mul_hi_u32 v6, s1, v1
9869; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v1
9870; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
9871; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
9872; GFX9-NEXT:    v_mul_lo_u32 v4, s1, v0
9873; GFX9-NEXT:    v_mul_hi_u32 v0, s1, v0
9874; GFX9-NEXT:    s_mov_b32 s3, 0x12d8fb
9875; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
9876; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
9877; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
9878; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
9879; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
9880; GFX9-NEXT:    v_mul_hi_u32 v2, s3, v0
9881; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s3
9882; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
9883; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
9884; GFX9-NEXT:    v_mov_b32_e32 v2, s1
9885; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, s0, v0
9886; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v2, v1, vcc
9887; GFX9-NEXT:    v_subrev_co_u32_e32 v2, vcc, s3, v0
9888; GFX9-NEXT:    v_subbrev_co_u32_e32 v3, vcc, 0, v1, vcc
9889; GFX9-NEXT:    v_subrev_co_u32_e32 v4, vcc, s3, v2
9890; GFX9-NEXT:    v_subbrev_co_u32_e32 v6, vcc, 0, v3, vcc
9891; GFX9-NEXT:    s_mov_b32 s3, 0x12d8fa
9892; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s3, v2
9893; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
9894; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
9895; GFX9-NEXT:    v_cndmask_b32_e32 v7, -1, v7, vcc
9896; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v7
9897; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s3, v0
9898; GFX9-NEXT:    v_cndmask_b32_e64 v3, v3, v6, s[0:1]
9899; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
9900; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
9901; GFX9-NEXT:    v_cndmask_b32_e32 v6, -1, v6, vcc
9902; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
9903; GFX9-NEXT:    v_cndmask_b32_e64 v2, v2, v4, s[0:1]
9904; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
9905; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
9906; GFX9-NEXT:    v_xor_b32_e32 v0, s2, v0
9907; GFX9-NEXT:    v_xor_b32_e32 v1, s2, v1
9908; GFX9-NEXT:    v_mov_b32_e32 v2, s2
9909; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s2, v0
9910; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
9911; GFX9-NEXT:    global_store_dwordx2 v5, v[0:1], s[4:5]
9912; GFX9-NEXT:    s_endpgm
9913  %r = srem i64 %x, 1235195
9914  store i64 %r, i64 addrspace(1)* %out
9915  ret void
9916}
9917
9918define amdgpu_kernel void @srem_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) {
9919; CHECK-LABEL: @srem_i64_pow2k_denom(
9920; CHECK-NEXT:    [[R:%.*]] = srem i64 [[X:%.*]], 4096
9921; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
9922; CHECK-NEXT:    ret void
9923;
9924; GFX6-LABEL: srem_i64_pow2k_denom:
9925; GFX6:       ; %bb.0:
9926; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
9927; GFX6-NEXT:    s_mov_b32 s3, 0xf000
9928; GFX6-NEXT:    s_mov_b32 s2, -1
9929; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
9930; GFX6-NEXT:    s_mov_b32 s0, s4
9931; GFX6-NEXT:    s_ashr_i32 s4, s7, 31
9932; GFX6-NEXT:    s_lshr_b32 s4, s4, 20
9933; GFX6-NEXT:    s_add_u32 s4, s6, s4
9934; GFX6-NEXT:    s_mov_b32 s1, s5
9935; GFX6-NEXT:    s_addc_u32 s5, s7, 0
9936; GFX6-NEXT:    s_and_b32 s4, s4, 0xfffff000
9937; GFX6-NEXT:    s_sub_u32 s4, s6, s4
9938; GFX6-NEXT:    s_subb_u32 s5, s7, s5
9939; GFX6-NEXT:    v_mov_b32_e32 v0, s4
9940; GFX6-NEXT:    v_mov_b32_e32 v1, s5
9941; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
9942; GFX6-NEXT:    s_endpgm
9943;
9944; GFX9-LABEL: srem_i64_pow2k_denom:
9945; GFX9:       ; %bb.0:
9946; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
9947; GFX9-NEXT:    v_mov_b32_e32 v2, 0
9948; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
9949; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
9950; GFX9-NEXT:    s_lshr_b32 s4, s4, 20
9951; GFX9-NEXT:    s_add_u32 s4, s2, s4
9952; GFX9-NEXT:    s_addc_u32 s5, s3, 0
9953; GFX9-NEXT:    s_and_b32 s4, s4, 0xfffff000
9954; GFX9-NEXT:    s_sub_u32 s2, s2, s4
9955; GFX9-NEXT:    s_subb_u32 s3, s3, s5
9956; GFX9-NEXT:    v_mov_b32_e32 v0, s2
9957; GFX9-NEXT:    v_mov_b32_e32 v1, s3
9958; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
9959; GFX9-NEXT:    s_endpgm
9960  %r = srem i64 %x, 4096
9961  store i64 %r, i64 addrspace(1)* %out
9962  ret void
9963}
9964
9965define amdgpu_kernel void @srem_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %x, i64 %y) {
9966; CHECK-LABEL: @srem_i64_pow2_shl_denom(
9967; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]]
9968; CHECK-NEXT:    [[R:%.*]] = srem i64 [[X:%.*]], [[SHL_Y]]
9969; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
9970; CHECK-NEXT:    ret void
9971;
9972; GFX6-LABEL: srem_i64_pow2_shl_denom:
9973; GFX6:       ; %bb.0:
9974; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xd
9975; GFX6-NEXT:    s_mov_b32 s3, 0
9976; GFX6-NEXT:    s_movk_i32 s2, 0x1000
9977; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
9978; GFX6-NEXT:    s_mov_b32 s7, 0xf000
9979; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
9980; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
9981; GFX6-NEXT:    s_ashr_i32 s4, s3, 31
9982; GFX6-NEXT:    s_add_u32 s2, s2, s4
9983; GFX6-NEXT:    s_mov_b32 s5, s4
9984; GFX6-NEXT:    s_addc_u32 s3, s3, s4
9985; GFX6-NEXT:    s_xor_b64 s[12:13], s[2:3], s[4:5]
9986; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s12
9987; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s13
9988; GFX6-NEXT:    s_sub_u32 s2, 0, s12
9989; GFX6-NEXT:    s_subb_u32 s3, 0, s13
9990; GFX6-NEXT:    s_ashr_i32 s14, s11, 31
9991; GFX6-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
9992; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
9993; GFX6-NEXT:    s_mov_b32 s15, s14
9994; GFX6-NEXT:    s_mov_b32 s6, -1
9995; GFX6-NEXT:    s_mov_b32 s4, s8
9996; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
9997; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
9998; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
9999; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
10000; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
10001; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
10002; GFX6-NEXT:    s_mov_b32 s5, s9
10003; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
10004; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
10005; GFX6-NEXT:    v_mul_lo_u32 v5, s3, v0
10006; GFX6-NEXT:    v_mul_lo_u32 v4, s2, v0
10007; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
10008; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
10009; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
10010; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
10011; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
10012; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
10013; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
10014; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
10015; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
10016; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
10017; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
10018; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
10019; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
10020; GFX6-NEXT:    v_mov_b32_e32 v4, 0
10021; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
10022; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
10023; GFX6-NEXT:    v_mov_b32_e32 v6, 0
10024; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
10025; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
10026; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
10027; GFX6-NEXT:    v_mul_lo_u32 v5, s2, v2
10028; GFX6-NEXT:    v_mul_hi_u32 v7, s2, v0
10029; GFX6-NEXT:    v_mul_lo_u32 v8, s3, v0
10030; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
10031; GFX6-NEXT:    v_mul_lo_u32 v7, s2, v0
10032; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
10033; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v5
10034; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v5
10035; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v7
10036; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v7
10037; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v7
10038; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v5
10039; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
10040; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
10041; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v5
10042; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
10043; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
10044; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
10045; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
10046; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
10047; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
10048; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
10049; GFX6-NEXT:    s_add_u32 s0, s10, s14
10050; GFX6-NEXT:    s_addc_u32 s1, s11, s14
10051; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
10052; GFX6-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
10053; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
10054; GFX6-NEXT:    v_mul_lo_u32 v2, s10, v1
10055; GFX6-NEXT:    v_mul_hi_u32 v3, s10, v0
10056; GFX6-NEXT:    v_mul_hi_u32 v5, s10, v1
10057; GFX6-NEXT:    v_mul_hi_u32 v7, s11, v1
10058; GFX6-NEXT:    v_mul_lo_u32 v1, s11, v1
10059; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
10060; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
10061; GFX6-NEXT:    v_mul_lo_u32 v5, s11, v0
10062; GFX6-NEXT:    v_mul_hi_u32 v0, s11, v0
10063; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
10064; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
10065; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
10066; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
10067; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
10068; GFX6-NEXT:    v_mul_lo_u32 v1, s12, v1
10069; GFX6-NEXT:    v_mul_hi_u32 v2, s12, v0
10070; GFX6-NEXT:    v_mul_lo_u32 v3, s13, v0
10071; GFX6-NEXT:    v_mul_lo_u32 v0, s12, v0
10072; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
10073; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
10074; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
10075; GFX6-NEXT:    v_mov_b32_e32 v3, s13
10076; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
10077; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
10078; GFX6-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
10079; GFX6-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
10080; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
10081; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
10082; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
10083; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
10084; GFX6-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
10085; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
10086; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
10087; GFX6-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
10088; GFX6-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
10089; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
10090; GFX6-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
10091; GFX6-NEXT:    v_mov_b32_e32 v5, s11
10092; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
10093; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
10094; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
10095; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
10096; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
10097; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
10098; GFX6-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
10099; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
10100; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
10101; GFX6-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
10102; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
10103; GFX6-NEXT:    v_xor_b32_e32 v0, s14, v0
10104; GFX6-NEXT:    v_xor_b32_e32 v1, s14, v1
10105; GFX6-NEXT:    v_mov_b32_e32 v2, s14
10106; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s14, v0
10107; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
10108; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
10109; GFX6-NEXT:    s_endpgm
10110;
10111; GFX9-LABEL: srem_i64_pow2_shl_denom:
10112; GFX9:       ; %bb.0:
10113; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x34
10114; GFX9-NEXT:    s_mov_b32 s3, 0
10115; GFX9-NEXT:    s_movk_i32 s2, 0x1000
10116; GFX9-NEXT:    v_mov_b32_e32 v2, 0
10117; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
10118; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
10119; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
10120; GFX9-NEXT:    s_add_u32 s2, s2, s4
10121; GFX9-NEXT:    s_mov_b32 s5, s4
10122; GFX9-NEXT:    s_addc_u32 s3, s3, s4
10123; GFX9-NEXT:    s_xor_b64 s[8:9], s[2:3], s[4:5]
10124; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
10125; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
10126; GFX9-NEXT:    s_sub_u32 s10, 0, s8
10127; GFX9-NEXT:    s_subb_u32 s4, 0, s9
10128; GFX9-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
10129; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
10130; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
10131; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
10132; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
10133; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
10134; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
10135; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
10136; GFX9-NEXT:    v_mul_hi_u32 v4, s10, v0
10137; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v1
10138; GFX9-NEXT:    v_mul_lo_u32 v6, s4, v0
10139; GFX9-NEXT:    v_mul_lo_u32 v5, s10, v0
10140; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
10141; GFX9-NEXT:    v_add_u32_e32 v3, v3, v6
10142; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v5
10143; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v3
10144; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v3
10145; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v5
10146; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
10147; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
10148; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v3
10149; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
10150; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
10151; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v5, v4
10152; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
10153; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v2, vcc
10154; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
10155; GFX9-NEXT:    v_mov_b32_e32 v6, 0
10156; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v3
10157; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
10158; GFX9-NEXT:    v_addc_co_u32_e64 v3, vcc, v1, v4, s[2:3]
10159; GFX9-NEXT:    v_mul_lo_u32 v5, s10, v3
10160; GFX9-NEXT:    v_mul_hi_u32 v7, s10, v0
10161; GFX9-NEXT:    v_mul_lo_u32 v8, s4, v0
10162; GFX9-NEXT:    v_mul_lo_u32 v9, s10, v0
10163; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
10164; GFX9-NEXT:    v_add_u32_e32 v5, v7, v5
10165; GFX9-NEXT:    v_add_u32_e32 v5, v5, v8
10166; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v5
10167; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v9
10168; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v5
10169; GFX9-NEXT:    v_mul_hi_u32 v8, v3, v9
10170; GFX9-NEXT:    v_mul_lo_u32 v9, v3, v9
10171; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
10172; GFX9-NEXT:    v_mul_hi_u32 v7, v3, v5
10173; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
10174; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v5
10175; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
10176; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
10177; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
10178; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
10179; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
10180; GFX9-NEXT:    s_ashr_i32 s10, s7, 31
10181; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
10182; GFX9-NEXT:    v_add_u32_e32 v1, v1, v4
10183; GFX9-NEXT:    s_add_u32 s0, s6, s10
10184; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v5, s[2:3]
10185; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
10186; GFX9-NEXT:    s_mov_b32 s11, s10
10187; GFX9-NEXT:    s_addc_u32 s1, s7, s10
10188; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[10:11]
10189; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
10190; GFX9-NEXT:    v_mul_lo_u32 v3, s6, v1
10191; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v0
10192; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v1
10193; GFX9-NEXT:    v_mul_hi_u32 v7, s7, v1
10194; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
10195; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
10196; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
10197; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v0
10198; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
10199; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
10200; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v4, v0, vcc
10201; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v2, vcc
10202; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
10203; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v6, v3, vcc
10204; GFX9-NEXT:    v_mul_lo_u32 v1, s8, v1
10205; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v0
10206; GFX9-NEXT:    v_mul_lo_u32 v4, s9, v0
10207; GFX9-NEXT:    v_mul_lo_u32 v0, s8, v0
10208; GFX9-NEXT:    v_add_u32_e32 v1, v3, v1
10209; GFX9-NEXT:    v_add_u32_e32 v1, v1, v4
10210; GFX9-NEXT:    v_sub_co_u32_e64 v0, s[0:1], s6, v0
10211; GFX9-NEXT:    v_sub_u32_e32 v3, s7, v1
10212; GFX9-NEXT:    v_mov_b32_e32 v4, s9
10213; GFX9-NEXT:    v_subb_co_u32_e64 v3, vcc, v3, v4, s[0:1]
10214; GFX9-NEXT:    v_subrev_co_u32_e64 v5, s[2:3], s8, v0
10215; GFX9-NEXT:    v_subbrev_co_u32_e64 v6, vcc, 0, v3, s[2:3]
10216; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v6
10217; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
10218; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v5
10219; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
10220; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v6
10221; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
10222; GFX9-NEXT:    v_subb_co_u32_e64 v3, vcc, v3, v4, s[2:3]
10223; GFX9-NEXT:    v_subrev_co_u32_e32 v4, vcc, s8, v5
10224; GFX9-NEXT:    v_subbrev_co_u32_e32 v3, vcc, 0, v3, vcc
10225; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v7
10226; GFX9-NEXT:    v_cndmask_b32_e64 v3, v6, v3, s[2:3]
10227; GFX9-NEXT:    v_mov_b32_e32 v6, s7
10228; GFX9-NEXT:    v_subb_co_u32_e64 v1, vcc, v6, v1, s[0:1]
10229; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
10230; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
10231; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
10232; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
10233; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
10234; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc
10235; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
10236; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
10237; GFX9-NEXT:    v_cndmask_b32_e64 v3, v5, v4, s[2:3]
10238; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
10239; GFX9-NEXT:    v_xor_b32_e32 v0, s10, v0
10240; GFX9-NEXT:    v_xor_b32_e32 v1, s10, v1
10241; GFX9-NEXT:    v_mov_b32_e32 v3, s10
10242; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s10, v0
10243; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
10244; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
10245; GFX9-NEXT:    s_endpgm
10246  %shl.y = shl i64 4096, %y
10247  %r = srem i64 %x, %shl.y
10248  store i64 %r, i64 addrspace(1)* %out
10249  ret void
10250}
10251
10252define amdgpu_kernel void @srem_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
10253; CHECK-LABEL: @srem_v2i64_pow2k_denom(
10254; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
10255; CHECK-NEXT:    [[TMP2:%.*]] = srem i64 [[TMP1]], 4096
10256; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
10257; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
10258; CHECK-NEXT:    [[TMP5:%.*]] = srem i64 [[TMP4]], 4096
10259; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
10260; CHECK-NEXT:    store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
10261; CHECK-NEXT:    ret void
10262;
10263; GFX6-LABEL: srem_v2i64_pow2k_denom:
10264; GFX6:       ; %bb.0:
10265; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
10266; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
10267; GFX6-NEXT:    s_movk_i32 s8, 0xf000
10268; GFX6-NEXT:    s_mov_b32 s7, 0xf000
10269; GFX6-NEXT:    s_mov_b32 s6, -1
10270; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
10271; GFX6-NEXT:    s_ashr_i32 s9, s1, 31
10272; GFX6-NEXT:    s_lshr_b32 s9, s9, 20
10273; GFX6-NEXT:    s_add_u32 s9, s0, s9
10274; GFX6-NEXT:    s_addc_u32 s10, s1, 0
10275; GFX6-NEXT:    s_and_b32 s9, s9, s8
10276; GFX6-NEXT:    s_sub_u32 s0, s0, s9
10277; GFX6-NEXT:    s_subb_u32 s1, s1, s10
10278; GFX6-NEXT:    s_ashr_i32 s9, s3, 31
10279; GFX6-NEXT:    s_lshr_b32 s9, s9, 20
10280; GFX6-NEXT:    s_add_u32 s9, s2, s9
10281; GFX6-NEXT:    s_addc_u32 s10, s3, 0
10282; GFX6-NEXT:    s_and_b32 s8, s9, s8
10283; GFX6-NEXT:    s_sub_u32 s2, s2, s8
10284; GFX6-NEXT:    s_subb_u32 s3, s3, s10
10285; GFX6-NEXT:    v_mov_b32_e32 v0, s0
10286; GFX6-NEXT:    v_mov_b32_e32 v1, s1
10287; GFX6-NEXT:    v_mov_b32_e32 v2, s2
10288; GFX6-NEXT:    v_mov_b32_e32 v3, s3
10289; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
10290; GFX6-NEXT:    s_endpgm
10291;
10292; GFX9-LABEL: srem_v2i64_pow2k_denom:
10293; GFX9:       ; %bb.0:
10294; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
10295; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
10296; GFX9-NEXT:    s_movk_i32 s8, 0xf000
10297; GFX9-NEXT:    v_mov_b32_e32 v4, 0
10298; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
10299; GFX9-NEXT:    s_ashr_i32 s0, s5, 31
10300; GFX9-NEXT:    s_lshr_b32 s0, s0, 20
10301; GFX9-NEXT:    s_add_u32 s0, s4, s0
10302; GFX9-NEXT:    s_addc_u32 s1, s5, 0
10303; GFX9-NEXT:    s_and_b32 s0, s0, s8
10304; GFX9-NEXT:    s_sub_u32 s0, s4, s0
10305; GFX9-NEXT:    s_subb_u32 s1, s5, s1
10306; GFX9-NEXT:    s_ashr_i32 s4, s7, 31
10307; GFX9-NEXT:    s_lshr_b32 s4, s4, 20
10308; GFX9-NEXT:    s_add_u32 s4, s6, s4
10309; GFX9-NEXT:    s_addc_u32 s5, s7, 0
10310; GFX9-NEXT:    s_and_b32 s4, s4, s8
10311; GFX9-NEXT:    s_sub_u32 s4, s6, s4
10312; GFX9-NEXT:    s_subb_u32 s5, s7, s5
10313; GFX9-NEXT:    v_mov_b32_e32 v0, s0
10314; GFX9-NEXT:    v_mov_b32_e32 v1, s1
10315; GFX9-NEXT:    v_mov_b32_e32 v2, s4
10316; GFX9-NEXT:    v_mov_b32_e32 v3, s5
10317; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
10318; GFX9-NEXT:    s_endpgm
10319  %r = srem <2 x i64> %x, <i64 4096, i64 4096>
10320  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
10321  ret void
10322}
10323
10324define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
10325; CHECK-LABEL: @srem_v2i64_pow2_shl_denom(
10326; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.*]]
10327; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
10328; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 0
10329; CHECK-NEXT:    [[TMP3:%.*]] = srem i64 [[TMP1]], [[TMP2]]
10330; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i64 0
10331; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 1
10332; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
10333; CHECK-NEXT:    [[TMP7:%.*]] = srem i64 [[TMP5]], [[TMP6]]
10334; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
10335; CHECK-NEXT:    store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
10336; CHECK-NEXT:    ret void
10337;
10338; GFX6-LABEL: srem_v2i64_pow2_shl_denom:
10339; GFX6:       ; %bb.0:
10340; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x11
10341; GFX6-NEXT:    s_mov_b32 s3, 0
10342; GFX6-NEXT:    s_movk_i32 s2, 0x1000
10343; GFX6-NEXT:    s_mov_b32 s18, 0x4f800000
10344; GFX6-NEXT:    s_mov_b32 s19, 0x5f7ffffc
10345; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
10346; GFX6-NEXT:    s_lshl_b64 s[14:15], s[2:3], s6
10347; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
10348; GFX6-NEXT:    s_ashr_i32 s4, s3, 31
10349; GFX6-NEXT:    s_add_u32 s2, s2, s4
10350; GFX6-NEXT:    s_mov_b32 s5, s4
10351; GFX6-NEXT:    s_addc_u32 s3, s3, s4
10352; GFX6-NEXT:    s_xor_b64 s[16:17], s[2:3], s[4:5]
10353; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s16
10354; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s17
10355; GFX6-NEXT:    s_mov_b32 s20, 0x2f800000
10356; GFX6-NEXT:    s_mov_b32 s21, 0xcf800000
10357; GFX6-NEXT:    s_sub_u32 s6, 0, s16
10358; GFX6-NEXT:    v_mac_f32_e32 v0, s18, v1
10359; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
10360; GFX6-NEXT:    s_subb_u32 s7, 0, s17
10361; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
10362; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
10363; GFX6-NEXT:    v_mul_f32_e32 v0, s19, v0
10364; GFX6-NEXT:    v_mul_f32_e32 v1, s20, v0
10365; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
10366; GFX6-NEXT:    v_mac_f32_e32 v0, s21, v1
10367; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
10368; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
10369; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
10370; GFX6-NEXT:    s_ashr_i32 s12, s9, 31
10371; GFX6-NEXT:    s_add_u32 s0, s8, s12
10372; GFX6-NEXT:    v_mul_hi_u32 v3, s6, v0
10373; GFX6-NEXT:    v_mul_lo_u32 v2, s6, v1
10374; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v0
10375; GFX6-NEXT:    v_mul_lo_u32 v5, s6, v0
10376; GFX6-NEXT:    s_mov_b32 s13, s12
10377; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
10378; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
10379; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
10380; GFX6-NEXT:    v_mul_hi_u32 v4, v0, v5
10381; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
10382; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
10383; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
10384; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
10385; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v6, vcc
10386; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v5
10387; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v5
10388; GFX6-NEXT:    s_addc_u32 s1, s9, s12
10389; GFX6-NEXT:    s_xor_b64 s[8:9], s[0:1], s[12:13]
10390; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
10391; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v4, v5, vcc
10392; GFX6-NEXT:    v_mov_b32_e32 v4, 0
10393; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
10394; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
10395; GFX6-NEXT:    v_mov_b32_e32 v6, 0
10396; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v2
10397; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
10398; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
10399; GFX6-NEXT:    v_mul_lo_u32 v5, s6, v2
10400; GFX6-NEXT:    v_mul_hi_u32 v7, s6, v0
10401; GFX6-NEXT:    v_mul_lo_u32 v8, s7, v0
10402; GFX6-NEXT:    s_mov_b32 s7, 0xf000
10403; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
10404; GFX6-NEXT:    v_mul_lo_u32 v7, s6, v0
10405; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
10406; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v5
10407; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v5
10408; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v7
10409; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v7
10410; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v7
10411; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v5
10412; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
10413; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
10414; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v5
10415; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
10416; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
10417; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
10418; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
10419; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
10420; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
10421; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
10422; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
10423; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
10424; GFX6-NEXT:    v_mul_lo_u32 v2, s8, v1
10425; GFX6-NEXT:    v_mul_hi_u32 v3, s8, v0
10426; GFX6-NEXT:    v_mul_hi_u32 v5, s8, v1
10427; GFX6-NEXT:    v_mul_hi_u32 v7, s9, v1
10428; GFX6-NEXT:    v_mul_lo_u32 v1, s9, v1
10429; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
10430; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
10431; GFX6-NEXT:    v_mul_lo_u32 v5, s9, v0
10432; GFX6-NEXT:    v_mul_hi_u32 v0, s9, v0
10433; GFX6-NEXT:    s_mov_b32 s6, -1
10434; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
10435; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
10436; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
10437; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
10438; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
10439; GFX6-NEXT:    v_mul_lo_u32 v1, s16, v1
10440; GFX6-NEXT:    v_mul_hi_u32 v2, s16, v0
10441; GFX6-NEXT:    v_mul_lo_u32 v3, s17, v0
10442; GFX6-NEXT:    v_mul_lo_u32 v0, s16, v0
10443; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
10444; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
10445; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s9, v1
10446; GFX6-NEXT:    v_mov_b32_e32 v3, s17
10447; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s8, v0
10448; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
10449; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s16, v0
10450; GFX6-NEXT:    v_subbrev_u32_e64 v7, s[2:3], 0, v2, s[0:1]
10451; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s17, v7
10452; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
10453; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[2:3]
10454; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s16, v5
10455; GFX6-NEXT:    v_subrev_i32_e64 v3, s[0:1], s16, v5
10456; GFX6-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[2:3]
10457; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s17, v7
10458; GFX6-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[2:3]
10459; GFX6-NEXT:    s_ashr_i32 s2, s15, 31
10460; GFX6-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
10461; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v8
10462; GFX6-NEXT:    s_add_u32 s8, s14, s2
10463; GFX6-NEXT:    v_cndmask_b32_e64 v2, v7, v2, s[0:1]
10464; GFX6-NEXT:    v_mov_b32_e32 v7, s9
10465; GFX6-NEXT:    s_mov_b32 s3, s2
10466; GFX6-NEXT:    s_addc_u32 s9, s15, s2
10467; GFX6-NEXT:    s_xor_b64 s[8:9], s[8:9], s[2:3]
10468; GFX6-NEXT:    v_cvt_f32_u32_e32 v8, s8
10469; GFX6-NEXT:    v_cvt_f32_u32_e32 v9, s9
10470; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v7, v1, vcc
10471; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s17, v1
10472; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
10473; GFX6-NEXT:    v_mac_f32_e32 v8, s18, v9
10474; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s16, v0
10475; GFX6-NEXT:    v_rcp_f32_e32 v8, v8
10476; GFX6-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
10477; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s17, v1
10478; GFX6-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc
10479; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
10480; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
10481; GFX6-NEXT:    v_cndmask_b32_e64 v2, v5, v3, s[0:1]
10482; GFX6-NEXT:    v_mul_f32_e32 v3, s19, v8
10483; GFX6-NEXT:    v_mul_f32_e32 v5, s20, v3
10484; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
10485; GFX6-NEXT:    v_mac_f32_e32 v3, s21, v5
10486; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
10487; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v5
10488; GFX6-NEXT:    s_sub_u32 s2, 0, s8
10489; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
10490; GFX6-NEXT:    v_mul_hi_u32 v2, s2, v3
10491; GFX6-NEXT:    v_mul_lo_u32 v7, s2, v5
10492; GFX6-NEXT:    s_subb_u32 s3, 0, s9
10493; GFX6-NEXT:    v_mul_lo_u32 v8, s3, v3
10494; GFX6-NEXT:    s_ashr_i32 s14, s11, 31
10495; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v7
10496; GFX6-NEXT:    v_mul_lo_u32 v7, s2, v3
10497; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
10498; GFX6-NEXT:    v_mul_lo_u32 v8, v3, v2
10499; GFX6-NEXT:    v_mul_hi_u32 v10, v3, v2
10500; GFX6-NEXT:    v_mul_hi_u32 v9, v3, v7
10501; GFX6-NEXT:    v_mul_hi_u32 v11, v5, v2
10502; GFX6-NEXT:    v_mul_lo_u32 v2, v5, v2
10503; GFX6-NEXT:    s_mov_b32 s15, s14
10504; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
10505; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
10506; GFX6-NEXT:    v_mul_lo_u32 v10, v5, v7
10507; GFX6-NEXT:    v_mul_hi_u32 v7, v5, v7
10508; GFX6-NEXT:    v_xor_b32_e32 v0, s12, v0
10509; GFX6-NEXT:    v_xor_b32_e32 v1, s12, v1
10510; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
10511; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v9, v7, vcc
10512; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v11, v4, vcc
10513; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
10514; GFX6-NEXT:    v_add_i32_e64 v2, s[0:1], v3, v2
10515; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v6, v8, vcc
10516; GFX6-NEXT:    v_addc_u32_e64 v3, vcc, v5, v7, s[0:1]
10517; GFX6-NEXT:    v_mul_lo_u32 v8, s2, v3
10518; GFX6-NEXT:    v_mul_hi_u32 v9, s2, v2
10519; GFX6-NEXT:    v_mul_lo_u32 v10, s3, v2
10520; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
10521; GFX6-NEXT:    v_mul_lo_u32 v9, s2, v2
10522; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
10523; GFX6-NEXT:    v_mul_lo_u32 v12, v2, v8
10524; GFX6-NEXT:    v_mul_hi_u32 v14, v2, v8
10525; GFX6-NEXT:    v_mul_hi_u32 v13, v2, v9
10526; GFX6-NEXT:    v_mul_hi_u32 v11, v3, v9
10527; GFX6-NEXT:    v_mul_lo_u32 v9, v3, v9
10528; GFX6-NEXT:    v_mul_hi_u32 v10, v3, v8
10529; GFX6-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
10530; GFX6-NEXT:    v_addc_u32_e32 v13, vcc, 0, v14, vcc
10531; GFX6-NEXT:    v_mul_lo_u32 v3, v3, v8
10532; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v12, v9
10533; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, v13, v11, vcc
10534; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v10, v4, vcc
10535; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v9, v3
10536; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v6, v8, vcc
10537; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
10538; GFX6-NEXT:    v_addc_u32_e64 v5, vcc, v5, v8, s[0:1]
10539; GFX6-NEXT:    s_add_u32 s0, s10, s14
10540; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
10541; GFX6-NEXT:    s_addc_u32 s1, s11, s14
10542; GFX6-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
10543; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
10544; GFX6-NEXT:    v_mul_lo_u32 v5, s10, v3
10545; GFX6-NEXT:    v_mul_hi_u32 v7, s10, v2
10546; GFX6-NEXT:    v_mul_hi_u32 v9, s10, v3
10547; GFX6-NEXT:    v_mul_hi_u32 v10, s11, v3
10548; GFX6-NEXT:    v_mul_lo_u32 v3, s11, v3
10549; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
10550; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v9, vcc
10551; GFX6-NEXT:    v_mul_lo_u32 v9, s11, v2
10552; GFX6-NEXT:    v_mul_hi_u32 v2, s11, v2
10553; GFX6-NEXT:    v_mov_b32_e32 v8, s12
10554; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
10555; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v2, vcc
10556; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v10, v4, vcc
10557; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
10558; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v4, vcc
10559; GFX6-NEXT:    v_mul_lo_u32 v3, s8, v3
10560; GFX6-NEXT:    v_mul_hi_u32 v4, s8, v2
10561; GFX6-NEXT:    v_mul_lo_u32 v5, s9, v2
10562; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s12, v0
10563; GFX6-NEXT:    v_mul_lo_u32 v2, s8, v2
10564; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
10565; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
10566; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
10567; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s11, v3
10568; GFX6-NEXT:    v_mov_b32_e32 v5, s9
10569; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s10, v2
10570; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
10571; GFX6-NEXT:    v_subrev_i32_e64 v6, s[0:1], s8, v2
10572; GFX6-NEXT:    v_subbrev_u32_e64 v7, s[2:3], 0, v4, s[0:1]
10573; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v7
10574; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, s[0:1]
10575; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[2:3]
10576; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v6
10577; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s8, v6
10578; GFX6-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[2:3]
10579; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v7
10580; GFX6-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[2:3]
10581; GFX6-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
10582; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v8
10583; GFX6-NEXT:    v_cndmask_b32_e64 v4, v7, v4, s[0:1]
10584; GFX6-NEXT:    v_mov_b32_e32 v7, s11
10585; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v7, v3, vcc
10586; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
10587; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
10588; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
10589; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
10590; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v3
10591; GFX6-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
10592; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
10593; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
10594; GFX6-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
10595; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
10596; GFX6-NEXT:    v_xor_b32_e32 v2, s14, v2
10597; GFX6-NEXT:    v_xor_b32_e32 v3, s14, v3
10598; GFX6-NEXT:    v_mov_b32_e32 v4, s14
10599; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s14, v2
10600; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
10601; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
10602; GFX6-NEXT:    s_endpgm
10603;
10604; GFX9-LABEL: srem_v2i64_pow2_shl_denom:
10605; GFX9:       ; %bb.0:
10606; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x44
10607; GFX9-NEXT:    s_mov_b32 s3, 0
10608; GFX9-NEXT:    s_movk_i32 s2, 0x1000
10609; GFX9-NEXT:    s_mov_b32 s16, 0x4f800000
10610; GFX9-NEXT:    s_mov_b32 s17, 0x5f7ffffc
10611; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
10612; GFX9-NEXT:    s_lshl_b64 s[12:13], s[2:3], s6
10613; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
10614; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
10615; GFX9-NEXT:    s_add_u32 s2, s2, s4
10616; GFX9-NEXT:    s_mov_b32 s5, s4
10617; GFX9-NEXT:    s_addc_u32 s3, s3, s4
10618; GFX9-NEXT:    s_xor_b64 s[14:15], s[2:3], s[4:5]
10619; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s14
10620; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s15
10621; GFX9-NEXT:    s_mov_b32 s18, 0x2f800000
10622; GFX9-NEXT:    s_mov_b32 s19, 0xcf800000
10623; GFX9-NEXT:    s_sub_u32 s4, 0, s14
10624; GFX9-NEXT:    v_mac_f32_e32 v0, s16, v1
10625; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
10626; GFX9-NEXT:    s_subb_u32 s5, 0, s15
10627; GFX9-NEXT:    v_mov_b32_e32 v6, 0
10628; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
10629; GFX9-NEXT:    v_mul_f32_e32 v0, s17, v0
10630; GFX9-NEXT:    v_mul_f32_e32 v1, s18, v0
10631; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
10632; GFX9-NEXT:    v_mac_f32_e32 v0, s19, v1
10633; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
10634; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
10635; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
10636; GFX9-NEXT:    s_ashr_i32 s6, s9, 31
10637; GFX9-NEXT:    s_mov_b32 s7, s6
10638; GFX9-NEXT:    v_mul_hi_u32 v3, s4, v0
10639; GFX9-NEXT:    v_mul_lo_u32 v2, s4, v1
10640; GFX9-NEXT:    v_mul_lo_u32 v5, s5, v0
10641; GFX9-NEXT:    v_mul_lo_u32 v4, s4, v0
10642; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
10643; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
10644; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
10645; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
10646; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
10647; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
10648; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
10649; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
10650; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
10651; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
10652; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
10653; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v7, v3
10654; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
10655; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
10656; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
10657; GFX9-NEXT:    v_mov_b32_e32 v5, 0
10658; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
10659; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
10660; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
10661; GFX9-NEXT:    v_mul_lo_u32 v4, s4, v2
10662; GFX9-NEXT:    v_mul_hi_u32 v7, s4, v0
10663; GFX9-NEXT:    v_mul_lo_u32 v8, s5, v0
10664; GFX9-NEXT:    v_mul_lo_u32 v9, s4, v0
10665; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
10666; GFX9-NEXT:    v_add_u32_e32 v4, v7, v4
10667; GFX9-NEXT:    v_add_u32_e32 v4, v4, v8
10668; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v4
10669; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v9
10670; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v4
10671; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v9
10672; GFX9-NEXT:    v_mul_lo_u32 v9, v2, v9
10673; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
10674; GFX9-NEXT:    v_mul_hi_u32 v7, v2, v4
10675; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
10676; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
10677; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
10678; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
10679; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v6, vcc
10680; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v8, v2
10681; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v4, vcc
10682; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
10683; GFX9-NEXT:    s_add_u32 s2, s8, s6
10684; GFX9-NEXT:    s_addc_u32 s3, s9, s6
10685; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
10686; GFX9-NEXT:    s_xor_b64 s[8:9], s[2:3], s[6:7]
10687; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
10688; GFX9-NEXT:    v_mul_lo_u32 v2, s8, v1
10689; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v0
10690; GFX9-NEXT:    v_mul_hi_u32 v4, s8, v1
10691; GFX9-NEXT:    v_mul_hi_u32 v7, s9, v1
10692; GFX9-NEXT:    v_mul_lo_u32 v1, s9, v1
10693; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
10694; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
10695; GFX9-NEXT:    v_mul_lo_u32 v4, s9, v0
10696; GFX9-NEXT:    v_mul_hi_u32 v0, s9, v0
10697; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
10698; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
10699; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
10700; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
10701; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
10702; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
10703; GFX9-NEXT:    v_mul_lo_u32 v1, s14, v1
10704; GFX9-NEXT:    v_mul_hi_u32 v2, s14, v0
10705; GFX9-NEXT:    v_mul_lo_u32 v3, s15, v0
10706; GFX9-NEXT:    v_mul_lo_u32 v0, s14, v0
10707; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
10708; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
10709; GFX9-NEXT:    v_sub_co_u32_e64 v0, s[0:1], s8, v0
10710; GFX9-NEXT:    v_sub_u32_e32 v2, s9, v1
10711; GFX9-NEXT:    v_mov_b32_e32 v3, s15
10712; GFX9-NEXT:    v_subb_co_u32_e64 v2, vcc, v2, v3, s[0:1]
10713; GFX9-NEXT:    v_subrev_co_u32_e64 v4, s[2:3], s14, v0
10714; GFX9-NEXT:    v_subbrev_co_u32_e64 v7, vcc, 0, v2, s[2:3]
10715; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s15, v7
10716; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
10717; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s14, v4
10718; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
10719; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s15, v7
10720; GFX9-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
10721; GFX9-NEXT:    v_subb_co_u32_e64 v2, vcc, v2, v3, s[2:3]
10722; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s14, v4
10723; GFX9-NEXT:    v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc
10724; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v8
10725; GFX9-NEXT:    v_cndmask_b32_e64 v2, v7, v2, s[2:3]
10726; GFX9-NEXT:    v_mov_b32_e32 v7, s9
10727; GFX9-NEXT:    v_subb_co_u32_e64 v1, vcc, v7, v1, s[0:1]
10728; GFX9-NEXT:    s_ashr_i32 s0, s13, 31
10729; GFX9-NEXT:    s_add_u32 s8, s12, s0
10730; GFX9-NEXT:    s_mov_b32 s1, s0
10731; GFX9-NEXT:    s_addc_u32 s9, s13, s0
10732; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[0:1]
10733; GFX9-NEXT:    v_cvt_f32_u32_e32 v9, s8
10734; GFX9-NEXT:    v_cvt_f32_u32_e32 v10, s9
10735; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s15, v1
10736; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
10737; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s14, v0
10738; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
10739; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s15, v1
10740; GFX9-NEXT:    v_mac_f32_e32 v9, s16, v10
10741; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
10742; GFX9-NEXT:    v_rcp_f32_e32 v8, v9
10743; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
10744; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
10745; GFX9-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[2:3]
10746; GFX9-NEXT:    v_mul_f32_e32 v3, s17, v8
10747; GFX9-NEXT:    v_mul_f32_e32 v4, s18, v3
10748; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
10749; GFX9-NEXT:    v_mac_f32_e32 v3, s19, v4
10750; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
10751; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
10752; GFX9-NEXT:    s_sub_u32 s2, 0, s8
10753; GFX9-NEXT:    s_subb_u32 s3, 0, s9
10754; GFX9-NEXT:    v_mul_hi_u32 v7, s2, v3
10755; GFX9-NEXT:    v_mul_lo_u32 v8, s2, v4
10756; GFX9-NEXT:    v_mul_lo_u32 v9, s3, v3
10757; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
10758; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v3
10759; GFX9-NEXT:    v_add_u32_e32 v7, v7, v8
10760; GFX9-NEXT:    v_add_u32_e32 v7, v7, v9
10761; GFX9-NEXT:    v_mul_lo_u32 v8, v3, v7
10762; GFX9-NEXT:    v_mul_hi_u32 v9, v3, v2
10763; GFX9-NEXT:    v_mul_hi_u32 v10, v3, v7
10764; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v7
10765; GFX9-NEXT:    v_mul_lo_u32 v7, v4, v7
10766; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
10767; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
10768; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v2
10769; GFX9-NEXT:    v_mul_hi_u32 v2, v4, v2
10770; GFX9-NEXT:    s_ashr_i32 s12, s11, 31
10771; GFX9-NEXT:    s_mov_b32 s13, s12
10772; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v8
10773; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v9, v2, vcc
10774; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v6, vcc
10775; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v7
10776; GFX9-NEXT:    v_add_co_u32_e64 v2, s[0:1], v3, v2
10777; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v5, v8, vcc
10778; GFX9-NEXT:    v_addc_co_u32_e64 v3, vcc, v4, v7, s[0:1]
10779; GFX9-NEXT:    v_mul_lo_u32 v8, s2, v3
10780; GFX9-NEXT:    v_mul_hi_u32 v9, s2, v2
10781; GFX9-NEXT:    v_mul_lo_u32 v10, s3, v2
10782; GFX9-NEXT:    v_mul_lo_u32 v11, s2, v2
10783; GFX9-NEXT:    v_add_u32_e32 v4, v4, v7
10784; GFX9-NEXT:    v_add_u32_e32 v8, v9, v8
10785; GFX9-NEXT:    v_add_u32_e32 v8, v8, v10
10786; GFX9-NEXT:    v_mul_lo_u32 v12, v2, v8
10787; GFX9-NEXT:    v_mul_hi_u32 v13, v2, v11
10788; GFX9-NEXT:    v_mul_hi_u32 v14, v2, v8
10789; GFX9-NEXT:    v_mul_hi_u32 v10, v3, v11
10790; GFX9-NEXT:    v_mul_lo_u32 v11, v3, v11
10791; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v13, v12
10792; GFX9-NEXT:    v_mul_hi_u32 v9, v3, v8
10793; GFX9-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v14, vcc
10794; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v8
10795; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v12, v11
10796; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v10, vcc
10797; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v9, v6, vcc
10798; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v10, v3
10799; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v5, v8, vcc
10800; GFX9-NEXT:    v_addc_co_u32_e64 v4, vcc, v4, v8, s[0:1]
10801; GFX9-NEXT:    s_add_u32 s0, s10, s12
10802; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
10803; GFX9-NEXT:    s_addc_u32 s1, s11, s12
10804; GFX9-NEXT:    s_xor_b64 s[10:11], s[0:1], s[12:13]
10805; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
10806; GFX9-NEXT:    v_mul_lo_u32 v4, s10, v3
10807; GFX9-NEXT:    v_mul_hi_u32 v7, s10, v2
10808; GFX9-NEXT:    v_mul_hi_u32 v9, s10, v3
10809; GFX9-NEXT:    v_mul_hi_u32 v10, s11, v3
10810; GFX9-NEXT:    v_mul_lo_u32 v3, s11, v3
10811; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v7, v4
10812; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v9, vcc
10813; GFX9-NEXT:    v_mul_lo_u32 v9, s11, v2
10814; GFX9-NEXT:    v_mul_hi_u32 v2, s11, v2
10815; GFX9-NEXT:    v_xor_b32_e32 v0, s6, v0
10816; GFX9-NEXT:    v_xor_b32_e32 v1, s6, v1
10817; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v9, v4
10818; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v2, vcc
10819; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v6, vcc
10820; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
10821; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
10822; GFX9-NEXT:    v_mul_lo_u32 v3, s8, v3
10823; GFX9-NEXT:    v_mul_hi_u32 v4, s8, v2
10824; GFX9-NEXT:    v_mul_lo_u32 v5, s9, v2
10825; GFX9-NEXT:    v_mul_lo_u32 v2, s8, v2
10826; GFX9-NEXT:    v_mov_b32_e32 v8, s6
10827; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
10828; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
10829; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s6, v0
10830; GFX9-NEXT:    v_sub_co_u32_e64 v2, s[0:1], s10, v2
10831; GFX9-NEXT:    v_sub_u32_e32 v4, s11, v3
10832; GFX9-NEXT:    v_mov_b32_e32 v5, s9
10833; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v8, vcc
10834; GFX9-NEXT:    v_subb_co_u32_e64 v4, vcc, v4, v5, s[0:1]
10835; GFX9-NEXT:    v_subrev_co_u32_e64 v7, s[2:3], s8, v2
10836; GFX9-NEXT:    v_subbrev_co_u32_e64 v8, vcc, 0, v4, s[2:3]
10837; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v8
10838; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
10839; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v7
10840; GFX9-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
10841; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v8
10842; GFX9-NEXT:    v_cndmask_b32_e32 v9, v9, v10, vcc
10843; GFX9-NEXT:    v_subb_co_u32_e64 v4, vcc, v4, v5, s[2:3]
10844; GFX9-NEXT:    v_subrev_co_u32_e32 v5, vcc, s8, v7
10845; GFX9-NEXT:    v_subbrev_co_u32_e32 v4, vcc, 0, v4, vcc
10846; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v9
10847; GFX9-NEXT:    v_cndmask_b32_e64 v4, v8, v4, s[2:3]
10848; GFX9-NEXT:    v_mov_b32_e32 v8, s11
10849; GFX9-NEXT:    v_subb_co_u32_e64 v3, vcc, v8, v3, s[0:1]
10850; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
10851; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
10852; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
10853; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
10854; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v3
10855; GFX9-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
10856; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
10857; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
10858; GFX9-NEXT:    v_cndmask_b32_e64 v4, v7, v5, s[2:3]
10859; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
10860; GFX9-NEXT:    v_xor_b32_e32 v2, s12, v2
10861; GFX9-NEXT:    v_xor_b32_e32 v3, s12, v3
10862; GFX9-NEXT:    v_mov_b32_e32 v4, s12
10863; GFX9-NEXT:    v_subrev_co_u32_e32 v2, vcc, s12, v2
10864; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v3, v4, vcc
10865; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
10866; GFX9-NEXT:    global_store_dwordx4 v6, v[0:3], s[4:5]
10867; GFX9-NEXT:    s_endpgm
10868  %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
10869  %r = srem <2 x i64> %x, %shl.y
10870  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
10871  ret void
10872}
10873