1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --force-update
2; RUN: opt -S -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-codegenprepare -amdgpu-bypass-slow-div=0 %s | FileCheck %s
3; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-bypass-slow-div=0 < %s | FileCheck -check-prefix=GFX6 %s
4; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -amdgpu-bypass-slow-div=0 < %s | FileCheck -check-prefix=GFX9 %s
5
6define amdgpu_kernel void @udiv_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
7; CHECK-LABEL: @udiv_i32(
8; CHECK-NEXT:    [[TMP1:%.*]] = uitofp i32 [[Y:%.*]] to float
9; CHECK-NEXT:    [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]])
10; CHECK-NEXT:    [[TMP3:%.*]] = fmul fast float [[TMP2]], 0x41EFFFFFC0000000
11; CHECK-NEXT:    [[TMP4:%.*]] = fptoui float [[TMP3]] to i32
12; CHECK-NEXT:    [[TMP5:%.*]] = sub i32 0, [[Y]]
13; CHECK-NEXT:    [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP4]]
14; CHECK-NEXT:    [[TMP7:%.*]] = zext i32 [[TMP4]] to i64
15; CHECK-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP6]] to i64
16; CHECK-NEXT:    [[TMP9:%.*]] = mul i64 [[TMP7]], [[TMP8]]
17; CHECK-NEXT:    [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
18; CHECK-NEXT:    [[TMP11:%.*]] = lshr i64 [[TMP9]], 32
19; CHECK-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
20; CHECK-NEXT:    [[TMP13:%.*]] = add i32 [[TMP4]], [[TMP12]]
21; CHECK-NEXT:    [[TMP14:%.*]] = zext i32 [[X:%.*]] to i64
22; CHECK-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP13]] to i64
23; CHECK-NEXT:    [[TMP16:%.*]] = mul i64 [[TMP14]], [[TMP15]]
24; CHECK-NEXT:    [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32
25; CHECK-NEXT:    [[TMP18:%.*]] = lshr i64 [[TMP16]], 32
26; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
27; CHECK-NEXT:    [[TMP20:%.*]] = mul i32 [[TMP19]], [[Y]]
28; CHECK-NEXT:    [[TMP21:%.*]] = sub i32 [[X]], [[TMP20]]
29; CHECK-NEXT:    [[TMP22:%.*]] = icmp uge i32 [[TMP21]], [[Y]]
30; CHECK-NEXT:    [[TMP23:%.*]] = add i32 [[TMP19]], 1
31; CHECK-NEXT:    [[TMP24:%.*]] = select i1 [[TMP22]], i32 [[TMP23]], i32 [[TMP19]]
32; CHECK-NEXT:    [[TMP25:%.*]] = sub i32 [[TMP21]], [[Y]]
33; CHECK-NEXT:    [[TMP26:%.*]] = select i1 [[TMP22]], i32 [[TMP25]], i32 [[TMP21]]
34; CHECK-NEXT:    [[TMP27:%.*]] = icmp uge i32 [[TMP26]], [[Y]]
35; CHECK-NEXT:    [[TMP28:%.*]] = add i32 [[TMP24]], 1
36; CHECK-NEXT:    [[TMP29:%.*]] = select i1 [[TMP27]], i32 [[TMP28]], i32 [[TMP24]]
37; CHECK-NEXT:    store i32 [[TMP29]], i32 addrspace(1)* [[OUT:%.*]], align 4
38; CHECK-NEXT:    ret void
39;
40; GFX6-LABEL: udiv_i32:
41; GFX6:       ; %bb.0:
42; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
43; GFX6-NEXT:    s_mov_b32 s7, 0xf000
44; GFX6-NEXT:    s_mov_b32 s6, -1
45; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
46; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s3
47; GFX6-NEXT:    s_sub_i32 s4, 0, s3
48; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
49; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
50; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
51; GFX6-NEXT:    v_mul_lo_u32 v1, s4, v0
52; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
53; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
54; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
55; GFX6-NEXT:    v_mul_hi_u32 v0, s2, v0
56; GFX6-NEXT:    v_mul_lo_u32 v1, v0, s3
57; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
58; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s2, v1
59; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v1
60; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
61; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v1
62; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[0:1]
63; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
64; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
65; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
66; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
67; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
68; GFX6-NEXT:    s_endpgm
69;
70; GFX9-LABEL: udiv_i32:
71; GFX9:       ; %bb.0:
72; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
73; GFX9-NEXT:    v_mov_b32_e32 v2, 0
74; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
75; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
76; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
77; GFX9-NEXT:    s_sub_i32 s4, 0, s3
78; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
79; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
80; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
81; GFX9-NEXT:    v_mul_lo_u32 v1, s4, v0
82; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
83; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
84; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
85; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s3
86; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
87; GFX9-NEXT:    v_sub_u32_e32 v1, s2, v1
88; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
89; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
90; GFX9-NEXT:    v_subrev_u32_e32 v3, s3, v1
91; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
92; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
93; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
94; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
95; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]
96; GFX9-NEXT:    s_endpgm
97  %r = udiv i32 %x, %y
98  store i32 %r, i32 addrspace(1)* %out
99  ret void
100}
101
102define amdgpu_kernel void @urem_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
103; CHECK-LABEL: @urem_i32(
104; CHECK-NEXT:    [[TMP1:%.*]] = uitofp i32 [[Y:%.*]] to float
105; CHECK-NEXT:    [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]])
106; CHECK-NEXT:    [[TMP3:%.*]] = fmul fast float [[TMP2]], 0x41EFFFFFC0000000
107; CHECK-NEXT:    [[TMP4:%.*]] = fptoui float [[TMP3]] to i32
108; CHECK-NEXT:    [[TMP5:%.*]] = sub i32 0, [[Y]]
109; CHECK-NEXT:    [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP4]]
110; CHECK-NEXT:    [[TMP7:%.*]] = zext i32 [[TMP4]] to i64
111; CHECK-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP6]] to i64
112; CHECK-NEXT:    [[TMP9:%.*]] = mul i64 [[TMP7]], [[TMP8]]
113; CHECK-NEXT:    [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
114; CHECK-NEXT:    [[TMP11:%.*]] = lshr i64 [[TMP9]], 32
115; CHECK-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
116; CHECK-NEXT:    [[TMP13:%.*]] = add i32 [[TMP4]], [[TMP12]]
117; CHECK-NEXT:    [[TMP14:%.*]] = zext i32 [[X:%.*]] to i64
118; CHECK-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP13]] to i64
119; CHECK-NEXT:    [[TMP16:%.*]] = mul i64 [[TMP14]], [[TMP15]]
120; CHECK-NEXT:    [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32
121; CHECK-NEXT:    [[TMP18:%.*]] = lshr i64 [[TMP16]], 32
122; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
123; CHECK-NEXT:    [[TMP20:%.*]] = mul i32 [[TMP19]], [[Y]]
124; CHECK-NEXT:    [[TMP21:%.*]] = sub i32 [[X]], [[TMP20]]
125; CHECK-NEXT:    [[TMP22:%.*]] = icmp uge i32 [[TMP21]], [[Y]]
126; CHECK-NEXT:    [[TMP23:%.*]] = sub i32 [[TMP21]], [[Y]]
127; CHECK-NEXT:    [[TMP24:%.*]] = select i1 [[TMP22]], i32 [[TMP23]], i32 [[TMP21]]
128; CHECK-NEXT:    [[TMP25:%.*]] = icmp uge i32 [[TMP24]], [[Y]]
129; CHECK-NEXT:    [[TMP26:%.*]] = sub i32 [[TMP24]], [[Y]]
130; CHECK-NEXT:    [[TMP27:%.*]] = select i1 [[TMP25]], i32 [[TMP26]], i32 [[TMP24]]
131; CHECK-NEXT:    store i32 [[TMP27]], i32 addrspace(1)* [[OUT:%.*]], align 4
132; CHECK-NEXT:    ret void
133;
134; GFX6-LABEL: urem_i32:
135; GFX6:       ; %bb.0:
136; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
137; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
138; GFX6-NEXT:    s_mov_b32 s3, 0xf000
139; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
140; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s5
141; GFX6-NEXT:    s_sub_i32 s2, 0, s5
142; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
143; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
144; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
145; GFX6-NEXT:    v_mul_lo_u32 v1, s2, v0
146; GFX6-NEXT:    s_mov_b32 s2, -1
147; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
148; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
149; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
150; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s5
151; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
152; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s5, v0
153; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s5, v0
154; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
155; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s5, v0
156; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s5, v0
157; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
158; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
159; GFX6-NEXT:    s_endpgm
160;
161; GFX9-LABEL: urem_i32:
162; GFX9:       ; %bb.0:
163; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
164; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
165; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
166; GFX9-NEXT:    s_sub_i32 s4, 0, s3
167; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
168; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
169; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
170; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
171; GFX9-NEXT:    v_mul_lo_u32 v1, s4, v0
172; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
173; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
174; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
175; GFX9-NEXT:    v_mov_b32_e32 v1, 0
176; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
177; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
178; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v0
179; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v0
180; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
181; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v0
182; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v0
183; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
184; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
185; GFX9-NEXT:    global_store_dword v1, v0, s[0:1]
186; GFX9-NEXT:    s_endpgm
187  %r = urem i32 %x, %y
188  store i32 %r, i32 addrspace(1)* %out
189  ret void
190}
191
192define amdgpu_kernel void @sdiv_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
193; CHECK-LABEL: @sdiv_i32(
194; CHECK-NEXT:    [[TMP1:%.*]] = ashr i32 [[X:%.*]], 31
195; CHECK-NEXT:    [[TMP2:%.*]] = ashr i32 [[Y:%.*]], 31
196; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
197; CHECK-NEXT:    [[TMP4:%.*]] = add i32 [[X]], [[TMP1]]
198; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[Y]], [[TMP2]]
199; CHECK-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP4]], [[TMP1]]
200; CHECK-NEXT:    [[TMP7:%.*]] = xor i32 [[TMP5]], [[TMP2]]
201; CHECK-NEXT:    [[TMP8:%.*]] = uitofp i32 [[TMP7]] to float
202; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP8]])
203; CHECK-NEXT:    [[TMP10:%.*]] = fmul fast float [[TMP9]], 0x41EFFFFFC0000000
204; CHECK-NEXT:    [[TMP11:%.*]] = fptoui float [[TMP10]] to i32
205; CHECK-NEXT:    [[TMP12:%.*]] = sub i32 0, [[TMP7]]
206; CHECK-NEXT:    [[TMP13:%.*]] = mul i32 [[TMP12]], [[TMP11]]
207; CHECK-NEXT:    [[TMP14:%.*]] = zext i32 [[TMP11]] to i64
208; CHECK-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP13]] to i64
209; CHECK-NEXT:    [[TMP16:%.*]] = mul i64 [[TMP14]], [[TMP15]]
210; CHECK-NEXT:    [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32
211; CHECK-NEXT:    [[TMP18:%.*]] = lshr i64 [[TMP16]], 32
212; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
213; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP11]], [[TMP19]]
214; CHECK-NEXT:    [[TMP21:%.*]] = zext i32 [[TMP6]] to i64
215; CHECK-NEXT:    [[TMP22:%.*]] = zext i32 [[TMP20]] to i64
216; CHECK-NEXT:    [[TMP23:%.*]] = mul i64 [[TMP21]], [[TMP22]]
217; CHECK-NEXT:    [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32
218; CHECK-NEXT:    [[TMP25:%.*]] = lshr i64 [[TMP23]], 32
219; CHECK-NEXT:    [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32
220; CHECK-NEXT:    [[TMP27:%.*]] = mul i32 [[TMP26]], [[TMP7]]
221; CHECK-NEXT:    [[TMP28:%.*]] = sub i32 [[TMP6]], [[TMP27]]
222; CHECK-NEXT:    [[TMP29:%.*]] = icmp uge i32 [[TMP28]], [[TMP7]]
223; CHECK-NEXT:    [[TMP30:%.*]] = add i32 [[TMP26]], 1
224; CHECK-NEXT:    [[TMP31:%.*]] = select i1 [[TMP29]], i32 [[TMP30]], i32 [[TMP26]]
225; CHECK-NEXT:    [[TMP32:%.*]] = sub i32 [[TMP28]], [[TMP7]]
226; CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP29]], i32 [[TMP32]], i32 [[TMP28]]
227; CHECK-NEXT:    [[TMP34:%.*]] = icmp uge i32 [[TMP33]], [[TMP7]]
228; CHECK-NEXT:    [[TMP35:%.*]] = add i32 [[TMP31]], 1
229; CHECK-NEXT:    [[TMP36:%.*]] = select i1 [[TMP34]], i32 [[TMP35]], i32 [[TMP31]]
230; CHECK-NEXT:    [[TMP37:%.*]] = xor i32 [[TMP36]], [[TMP3]]
231; CHECK-NEXT:    [[TMP38:%.*]] = sub i32 [[TMP37]], [[TMP3]]
232; CHECK-NEXT:    store i32 [[TMP38]], i32 addrspace(1)* [[OUT:%.*]], align 4
233; CHECK-NEXT:    ret void
234;
235; GFX6-LABEL: sdiv_i32:
236; GFX6:       ; %bb.0:
237; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
238; GFX6-NEXT:    s_mov_b32 s7, 0xf000
239; GFX6-NEXT:    s_mov_b32 s6, -1
240; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
241; GFX6-NEXT:    s_ashr_i32 s8, s3, 31
242; GFX6-NEXT:    s_add_i32 s3, s3, s8
243; GFX6-NEXT:    s_xor_b32 s3, s3, s8
244; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s3
245; GFX6-NEXT:    s_sub_i32 s4, 0, s3
246; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
247; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
248; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
249; GFX6-NEXT:    v_mul_lo_u32 v1, s4, v0
250; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
251; GFX6-NEXT:    s_ashr_i32 s0, s2, 31
252; GFX6-NEXT:    s_add_i32 s1, s2, s0
253; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
254; GFX6-NEXT:    s_xor_b32 s1, s1, s0
255; GFX6-NEXT:    s_xor_b32 s2, s0, s8
256; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
257; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
258; GFX6-NEXT:    v_mul_lo_u32 v1, v0, s3
259; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
260; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v1
261; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v1
262; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
263; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v1
264; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[0:1]
265; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
266; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
267; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
268; GFX6-NEXT:    v_xor_b32_e32 v0, s2, v0
269; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
270; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
271; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
272; GFX6-NEXT:    s_endpgm
273;
274; GFX9-LABEL: sdiv_i32:
275; GFX9:       ; %bb.0:
276; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
277; GFX9-NEXT:    v_mov_b32_e32 v2, 0
278; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
279; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
280; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
281; GFX9-NEXT:    s_add_i32 s3, s3, s4
282; GFX9-NEXT:    s_xor_b32 s3, s3, s4
283; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
284; GFX9-NEXT:    s_sub_i32 s5, 0, s3
285; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
286; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
287; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
288; GFX9-NEXT:    v_mul_lo_u32 v1, s5, v0
289; GFX9-NEXT:    s_ashr_i32 s5, s2, 31
290; GFX9-NEXT:    s_add_i32 s2, s2, s5
291; GFX9-NEXT:    s_xor_b32 s2, s2, s5
292; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
293; GFX9-NEXT:    s_xor_b32 s4, s5, s4
294; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
295; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
296; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s3
297; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
298; GFX9-NEXT:    v_sub_u32_e32 v1, s2, v1
299; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
300; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
301; GFX9-NEXT:    v_subrev_u32_e32 v3, s3, v1
302; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
303; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
304; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
305; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
306; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v0
307; GFX9-NEXT:    v_subrev_u32_e32 v0, s4, v0
308; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]
309; GFX9-NEXT:    s_endpgm
310  %r = sdiv i32 %x, %y
311  store i32 %r, i32 addrspace(1)* %out
312  ret void
313}
314
315define amdgpu_kernel void @srem_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
316; CHECK-LABEL: @srem_i32(
317; CHECK-NEXT:    [[TMP1:%.*]] = ashr i32 [[X:%.*]], 31
318; CHECK-NEXT:    [[TMP2:%.*]] = ashr i32 [[Y:%.*]], 31
319; CHECK-NEXT:    [[TMP3:%.*]] = add i32 [[X]], [[TMP1]]
320; CHECK-NEXT:    [[TMP4:%.*]] = add i32 [[Y]], [[TMP2]]
321; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP1]]
322; CHECK-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP4]], [[TMP2]]
323; CHECK-NEXT:    [[TMP7:%.*]] = uitofp i32 [[TMP6]] to float
324; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
325; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP8]], 0x41EFFFFFC0000000
326; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP9]] to i32
327; CHECK-NEXT:    [[TMP11:%.*]] = sub i32 0, [[TMP6]]
328; CHECK-NEXT:    [[TMP12:%.*]] = mul i32 [[TMP11]], [[TMP10]]
329; CHECK-NEXT:    [[TMP13:%.*]] = zext i32 [[TMP10]] to i64
330; CHECK-NEXT:    [[TMP14:%.*]] = zext i32 [[TMP12]] to i64
331; CHECK-NEXT:    [[TMP15:%.*]] = mul i64 [[TMP13]], [[TMP14]]
332; CHECK-NEXT:    [[TMP16:%.*]] = trunc i64 [[TMP15]] to i32
333; CHECK-NEXT:    [[TMP17:%.*]] = lshr i64 [[TMP15]], 32
334; CHECK-NEXT:    [[TMP18:%.*]] = trunc i64 [[TMP17]] to i32
335; CHECK-NEXT:    [[TMP19:%.*]] = add i32 [[TMP10]], [[TMP18]]
336; CHECK-NEXT:    [[TMP20:%.*]] = zext i32 [[TMP5]] to i64
337; CHECK-NEXT:    [[TMP21:%.*]] = zext i32 [[TMP19]] to i64
338; CHECK-NEXT:    [[TMP22:%.*]] = mul i64 [[TMP20]], [[TMP21]]
339; CHECK-NEXT:    [[TMP23:%.*]] = trunc i64 [[TMP22]] to i32
340; CHECK-NEXT:    [[TMP24:%.*]] = lshr i64 [[TMP22]], 32
341; CHECK-NEXT:    [[TMP25:%.*]] = trunc i64 [[TMP24]] to i32
342; CHECK-NEXT:    [[TMP26:%.*]] = mul i32 [[TMP25]], [[TMP6]]
343; CHECK-NEXT:    [[TMP27:%.*]] = sub i32 [[TMP5]], [[TMP26]]
344; CHECK-NEXT:    [[TMP28:%.*]] = icmp uge i32 [[TMP27]], [[TMP6]]
345; CHECK-NEXT:    [[TMP29:%.*]] = sub i32 [[TMP27]], [[TMP6]]
346; CHECK-NEXT:    [[TMP30:%.*]] = select i1 [[TMP28]], i32 [[TMP29]], i32 [[TMP27]]
347; CHECK-NEXT:    [[TMP31:%.*]] = icmp uge i32 [[TMP30]], [[TMP6]]
348; CHECK-NEXT:    [[TMP32:%.*]] = sub i32 [[TMP30]], [[TMP6]]
349; CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP31]], i32 [[TMP32]], i32 [[TMP30]]
350; CHECK-NEXT:    [[TMP34:%.*]] = xor i32 [[TMP33]], [[TMP1]]
351; CHECK-NEXT:    [[TMP35:%.*]] = sub i32 [[TMP34]], [[TMP1]]
352; CHECK-NEXT:    store i32 [[TMP35]], i32 addrspace(1)* [[OUT:%.*]], align 4
353; CHECK-NEXT:    ret void
354;
355; GFX6-LABEL: srem_i32:
356; GFX6:       ; %bb.0:
357; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
358; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
359; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
360; GFX6-NEXT:    s_ashr_i32 s4, s3, 31
361; GFX6-NEXT:    s_add_i32 s3, s3, s4
362; GFX6-NEXT:    s_xor_b32 s4, s3, s4
363; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s4
364; GFX6-NEXT:    s_sub_i32 s3, 0, s4
365; GFX6-NEXT:    s_ashr_i32 s5, s2, 31
366; GFX6-NEXT:    s_add_i32 s2, s2, s5
367; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
368; GFX6-NEXT:    s_xor_b32 s6, s2, s5
369; GFX6-NEXT:    s_mov_b32 s2, -1
370; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
371; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
372; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v0
373; GFX6-NEXT:    s_mov_b32 s3, 0xf000
374; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
375; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
376; GFX6-NEXT:    v_mul_hi_u32 v0, s6, v0
377; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s4
378; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
379; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s4, v0
380; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s4, v0
381; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
382; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s4, v0
383; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s4, v0
384; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
385; GFX6-NEXT:    v_xor_b32_e32 v0, s5, v0
386; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s5, v0
387; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
388; GFX6-NEXT:    s_endpgm
389;
390; GFX9-LABEL: srem_i32:
391; GFX9:       ; %bb.0:
392; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
393; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
394; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
395; GFX9-NEXT:    s_add_i32 s3, s3, s4
396; GFX9-NEXT:    s_xor_b32 s3, s3, s4
397; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
398; GFX9-NEXT:    s_sub_i32 s4, 0, s3
399; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
400; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
401; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
402; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
403; GFX9-NEXT:    v_mul_lo_u32 v1, s4, v0
404; GFX9-NEXT:    s_ashr_i32 s4, s2, 31
405; GFX9-NEXT:    s_add_i32 s2, s2, s4
406; GFX9-NEXT:    s_xor_b32 s2, s2, s4
407; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
408; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
409; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
410; GFX9-NEXT:    v_mov_b32_e32 v1, 0
411; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
412; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
413; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v0
414; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v0
415; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
416; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v0
417; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v0
418; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
419; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v0
420; GFX9-NEXT:    v_subrev_u32_e32 v0, s4, v0
421; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
422; GFX9-NEXT:    global_store_dword v1, v0, s[0:1]
423; GFX9-NEXT:    s_endpgm
424  %r = srem i32 %x, %y
425  store i32 %r, i32 addrspace(1)* %out
426  ret void
427}
428
429define amdgpu_kernel void @udiv_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
430; CHECK-LABEL: @udiv_i16(
431; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[X:%.*]] to i32
432; CHECK-NEXT:    [[TMP2:%.*]] = zext i16 [[Y:%.*]] to i32
433; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
434; CHECK-NEXT:    [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
435; CHECK-NEXT:    [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
436; CHECK-NEXT:    [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
437; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
438; CHECK-NEXT:    [[TMP8:%.*]] = fneg fast float [[TMP7]]
439; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
440; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
441; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
442; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
443; CHECK-NEXT:    [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
444; CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
445; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
446; CHECK-NEXT:    [[TMP16:%.*]] = and i32 [[TMP15]], 65535
447; CHECK-NEXT:    [[TMP17:%.*]] = trunc i32 [[TMP16]] to i16
448; CHECK-NEXT:    store i16 [[TMP17]], i16 addrspace(1)* [[OUT:%.*]], align 2
449; CHECK-NEXT:    ret void
450;
451; GFX6-LABEL: udiv_i16:
452; GFX6:       ; %bb.0:
453; GFX6-NEXT:    s_load_dword s2, s[0:1], 0xb
454; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
455; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
456; GFX6-NEXT:    s_lshr_b32 s3, s2, 16
457; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s3
458; GFX6-NEXT:    s_and_b32 s2, s2, 0xffff
459; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s2
460; GFX6-NEXT:    s_mov_b32 s3, 0xf000
461; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
462; GFX6-NEXT:    s_mov_b32 s2, -1
463; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
464; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
465; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v2
466; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
467; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
468; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
469; GFX6-NEXT:    buffer_store_short v0, off, s[0:3], 0
470; GFX6-NEXT:    s_endpgm
471;
472; GFX9-LABEL: udiv_i16:
473; GFX9:       ; %bb.0:
474; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
475; GFX9-NEXT:    v_mov_b32_e32 v3, 0
476; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
477; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
478; GFX9-NEXT:    s_lshr_b32 s3, s2, 16
479; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
480; GFX9-NEXT:    s_and_b32 s2, s2, 0xffff
481; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s2
482; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
483; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
484; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
485; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v2
486; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
487; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
488; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v4, vcc
489; GFX9-NEXT:    global_store_short v3, v0, s[0:1]
490; GFX9-NEXT:    s_endpgm
491  %r = udiv i16 %x, %y
492  store i16 %r, i16 addrspace(1)* %out
493  ret void
494}
495
496define amdgpu_kernel void @urem_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
497; CHECK-LABEL: @urem_i16(
498; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[X:%.*]] to i32
499; CHECK-NEXT:    [[TMP2:%.*]] = zext i16 [[Y:%.*]] to i32
500; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
501; CHECK-NEXT:    [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
502; CHECK-NEXT:    [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
503; CHECK-NEXT:    [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
504; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
505; CHECK-NEXT:    [[TMP8:%.*]] = fneg fast float [[TMP7]]
506; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
507; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
508; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
509; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
510; CHECK-NEXT:    [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
511; CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
512; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
513; CHECK-NEXT:    [[TMP16:%.*]] = mul i32 [[TMP15]], [[TMP2]]
514; CHECK-NEXT:    [[TMP17:%.*]] = sub i32 [[TMP1]], [[TMP16]]
515; CHECK-NEXT:    [[TMP18:%.*]] = and i32 [[TMP17]], 65535
516; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i16
517; CHECK-NEXT:    store i16 [[TMP19]], i16 addrspace(1)* [[OUT:%.*]], align 2
518; CHECK-NEXT:    ret void
519;
520; GFX6-LABEL: urem_i16:
521; GFX6:       ; %bb.0:
522; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
523; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
524; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
525; GFX6-NEXT:    s_lshr_b32 s2, s4, 16
526; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s2
527; GFX6-NEXT:    s_and_b32 s3, s4, 0xffff
528; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s3
529; GFX6-NEXT:    s_mov_b32 s3, 0xf000
530; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
531; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
532; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
533; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v2
534; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
535; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
536; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
537; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
538; GFX6-NEXT:    s_mov_b32 s2, -1
539; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
540; GFX6-NEXT:    buffer_store_short v0, off, s[0:3], 0
541; GFX6-NEXT:    s_endpgm
542;
543; GFX9-LABEL: urem_i16:
544; GFX9:       ; %bb.0:
545; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
546; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
547; GFX9-NEXT:    s_lshr_b32 s3, s2, 16
548; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
549; GFX9-NEXT:    s_and_b32 s4, s2, 0xffff
550; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s4
551; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
552; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
553; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
554; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
555; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v2
556; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
557; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
558; GFX9-NEXT:    v_mov_b32_e32 v1, 0
559; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
560; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
561; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
562; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
563; GFX9-NEXT:    global_store_short v1, v0, s[0:1]
564; GFX9-NEXT:    s_endpgm
565  %r = urem i16 %x, %y
566  store i16 %r, i16 addrspace(1)* %out
567  ret void
568}
569
570define amdgpu_kernel void @sdiv_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
571; CHECK-LABEL: @sdiv_i16(
572; CHECK-NEXT:    [[TMP1:%.*]] = sext i16 [[X:%.*]] to i32
573; CHECK-NEXT:    [[TMP2:%.*]] = sext i16 [[Y:%.*]] to i32
574; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
575; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
576; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP4]], 1
577; CHECK-NEXT:    [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
578; CHECK-NEXT:    [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
579; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
580; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
581; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
582; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
583; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
584; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
585; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
586; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
587; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
588; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
589; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
590; CHECK-NEXT:    [[TMP19:%.*]] = shl i32 [[TMP18]], 16
591; CHECK-NEXT:    [[TMP20:%.*]] = ashr i32 [[TMP19]], 16
592; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i16
593; CHECK-NEXT:    store i16 [[TMP21]], i16 addrspace(1)* [[OUT:%.*]], align 2
594; CHECK-NEXT:    ret void
595;
596; GFX6-LABEL: sdiv_i16:
597; GFX6:       ; %bb.0:
598; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
599; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
600; GFX6-NEXT:    s_mov_b32 s3, 0xf000
601; GFX6-NEXT:    s_mov_b32 s2, -1
602; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
603; GFX6-NEXT:    s_ashr_i32 s5, s4, 16
604; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s5
605; GFX6-NEXT:    s_sext_i32_i16 s4, s4
606; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s4
607; GFX6-NEXT:    s_xor_b32 s4, s4, s5
608; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
609; GFX6-NEXT:    s_ashr_i32 s4, s4, 30
610; GFX6-NEXT:    s_or_b32 s4, s4, 1
611; GFX6-NEXT:    v_mov_b32_e32 v3, s4
612; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
613; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
614; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
615; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
616; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
617; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
618; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
619; GFX6-NEXT:    buffer_store_short v0, off, s[0:3], 0
620; GFX6-NEXT:    s_endpgm
621;
622; GFX9-LABEL: sdiv_i16:
623; GFX9:       ; %bb.0:
624; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
625; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
626; GFX9-NEXT:    v_mov_b32_e32 v1, 0
627; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
628; GFX9-NEXT:    s_ashr_i32 s0, s4, 16
629; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s0
630; GFX9-NEXT:    s_sext_i32_i16 s1, s4
631; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s1
632; GFX9-NEXT:    s_xor_b32 s0, s1, s0
633; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
634; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
635; GFX9-NEXT:    s_or_b32 s4, s0, 1
636; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
637; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
638; GFX9-NEXT:    v_mad_f32 v2, -v3, v0, v2
639; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
640; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
641; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
642; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
643; GFX9-NEXT:    v_add_u32_e32 v0, s0, v3
644; GFX9-NEXT:    global_store_short v1, v0, s[2:3]
645; GFX9-NEXT:    s_endpgm
646  %r = sdiv i16 %x, %y
647  store i16 %r, i16 addrspace(1)* %out
648  ret void
649}
650
651define amdgpu_kernel void @srem_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
652; CHECK-LABEL: @srem_i16(
653; CHECK-NEXT:    [[TMP1:%.*]] = sext i16 [[X:%.*]] to i32
654; CHECK-NEXT:    [[TMP2:%.*]] = sext i16 [[Y:%.*]] to i32
655; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
656; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
657; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP4]], 1
658; CHECK-NEXT:    [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
659; CHECK-NEXT:    [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
660; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
661; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
662; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
663; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
664; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
665; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
666; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
667; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
668; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
669; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
670; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
671; CHECK-NEXT:    [[TMP19:%.*]] = mul i32 [[TMP18]], [[TMP2]]
672; CHECK-NEXT:    [[TMP20:%.*]] = sub i32 [[TMP1]], [[TMP19]]
673; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 16
674; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 16
675; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i16
676; CHECK-NEXT:    store i16 [[TMP23]], i16 addrspace(1)* [[OUT:%.*]], align 2
677; CHECK-NEXT:    ret void
678;
679; GFX6-LABEL: srem_i16:
680; GFX6:       ; %bb.0:
681; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
682; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
683; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
684; GFX6-NEXT:    s_ashr_i32 s2, s4, 16
685; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s2
686; GFX6-NEXT:    s_sext_i32_i16 s3, s4
687; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s3
688; GFX6-NEXT:    s_xor_b32 s3, s3, s2
689; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
690; GFX6-NEXT:    s_ashr_i32 s3, s3, 30
691; GFX6-NEXT:    s_or_b32 s3, s3, 1
692; GFX6-NEXT:    v_mov_b32_e32 v3, s3
693; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
694; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
695; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
696; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
697; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
698; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
699; GFX6-NEXT:    s_mov_b32 s3, 0xf000
700; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
701; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
702; GFX6-NEXT:    s_mov_b32 s2, -1
703; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
704; GFX6-NEXT:    buffer_store_short v0, off, s[0:3], 0
705; GFX6-NEXT:    s_endpgm
706;
707; GFX9-LABEL: srem_i16:
708; GFX9:       ; %bb.0:
709; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
710; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
711; GFX9-NEXT:    s_ashr_i32 s5, s4, 16
712; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s5
713; GFX9-NEXT:    s_sext_i32_i16 s2, s4
714; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s2
715; GFX9-NEXT:    s_xor_b32 s2, s2, s5
716; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
717; GFX9-NEXT:    s_ashr_i32 s2, s2, 30
718; GFX9-NEXT:    s_or_b32 s6, s2, 1
719; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
720; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
721; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
722; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
723; GFX9-NEXT:    v_cvt_i32_f32_e32 v2, v2
724; GFX9-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|
725; GFX9-NEXT:    s_and_b64 s[2:3], s[2:3], exec
726; GFX9-NEXT:    s_cselect_b32 s2, s6, 0
727; GFX9-NEXT:    v_add_u32_e32 v0, s2, v2
728; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s5
729; GFX9-NEXT:    v_mov_b32_e32 v1, 0
730; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
731; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
732; GFX9-NEXT:    global_store_short v1, v0, s[0:1]
733; GFX9-NEXT:    s_endpgm
734  %r = srem i16 %x, %y
735  store i16 %r, i16 addrspace(1)* %out
736  ret void
737}
738
739define amdgpu_kernel void @udiv_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
740; CHECK-LABEL: @udiv_i8(
741; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[X:%.*]] to i32
742; CHECK-NEXT:    [[TMP2:%.*]] = zext i8 [[Y:%.*]] to i32
743; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
744; CHECK-NEXT:    [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
745; CHECK-NEXT:    [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
746; CHECK-NEXT:    [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
747; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
748; CHECK-NEXT:    [[TMP8:%.*]] = fneg fast float [[TMP7]]
749; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
750; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
751; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
752; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
753; CHECK-NEXT:    [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
754; CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
755; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
756; CHECK-NEXT:    [[TMP16:%.*]] = and i32 [[TMP15]], 255
757; CHECK-NEXT:    [[TMP17:%.*]] = trunc i32 [[TMP16]] to i8
758; CHECK-NEXT:    store i8 [[TMP17]], i8 addrspace(1)* [[OUT:%.*]], align 1
759; CHECK-NEXT:    ret void
760;
761; GFX6-LABEL: udiv_i8:
762; GFX6:       ; %bb.0:
763; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
764; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
765; GFX6-NEXT:    s_mov_b32 s3, 0xf000
766; GFX6-NEXT:    s_mov_b32 s2, -1
767; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
768; GFX6-NEXT:    v_cvt_f32_ubyte1_e32 v0, s4
769; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v0
770; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v2, s4
771; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1
772; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
773; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v1
774; GFX6-NEXT:    v_mad_f32 v1, -v1, v0, v2
775; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
776; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
777; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
778; GFX6-NEXT:    s_endpgm
779;
780; GFX9-LABEL: udiv_i8:
781; GFX9:       ; %bb.0:
782; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
783; GFX9-NEXT:    v_mov_b32_e32 v2, 0
784; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
785; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
786; GFX9-NEXT:    v_cvt_f32_ubyte1_e32 v0, s2
787; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
788; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v3, s2
789; GFX9-NEXT:    v_mul_f32_e32 v1, v3, v1
790; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
791; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v1
792; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v3
793; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
794; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v4, vcc
795; GFX9-NEXT:    global_store_byte v2, v0, s[0:1]
796; GFX9-NEXT:    s_endpgm
797  %r = udiv i8 %x, %y
798  store i8 %r, i8 addrspace(1)* %out
799  ret void
800}
801
802define amdgpu_kernel void @urem_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
803; CHECK-LABEL: @urem_i8(
804; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[X:%.*]] to i32
805; CHECK-NEXT:    [[TMP2:%.*]] = zext i8 [[Y:%.*]] to i32
806; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
807; CHECK-NEXT:    [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
808; CHECK-NEXT:    [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
809; CHECK-NEXT:    [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
810; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
811; CHECK-NEXT:    [[TMP8:%.*]] = fneg fast float [[TMP7]]
812; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
813; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
814; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
815; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
816; CHECK-NEXT:    [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
817; CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
818; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
819; CHECK-NEXT:    [[TMP16:%.*]] = mul i32 [[TMP15]], [[TMP2]]
820; CHECK-NEXT:    [[TMP17:%.*]] = sub i32 [[TMP1]], [[TMP16]]
821; CHECK-NEXT:    [[TMP18:%.*]] = and i32 [[TMP17]], 255
822; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i8
823; CHECK-NEXT:    store i8 [[TMP19]], i8 addrspace(1)* [[OUT:%.*]], align 1
824; CHECK-NEXT:    ret void
825;
826; GFX6-LABEL: urem_i8:
827; GFX6:       ; %bb.0:
828; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
829; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
830; GFX6-NEXT:    s_mov_b32 s3, 0xf000
831; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
832; GFX6-NEXT:    v_cvt_f32_ubyte1_e32 v0, s4
833; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v0
834; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v2, s4
835; GFX6-NEXT:    s_lshr_b32 s2, s4, 8
836; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1
837; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
838; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v1
839; GFX6-NEXT:    v_mad_f32 v1, -v1, v0, v2
840; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
841; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
842; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
843; GFX6-NEXT:    s_mov_b32 s2, -1
844; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
845; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
846; GFX6-NEXT:    s_endpgm
847;
848; GFX9-LABEL: urem_i8:
849; GFX9:       ; %bb.0:
850; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
851; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
852; GFX9-NEXT:    v_cvt_f32_ubyte1_e32 v0, s2
853; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
854; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v2, s2
855; GFX9-NEXT:    s_lshr_b32 s3, s2, 8
856; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
857; GFX9-NEXT:    v_mul_f32_e32 v1, v2, v1
858; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
859; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v1
860; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v2
861; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
862; GFX9-NEXT:    v_mov_b32_e32 v1, 0
863; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
864; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
865; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
866; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
867; GFX9-NEXT:    global_store_byte v1, v0, s[0:1]
868; GFX9-NEXT:    s_endpgm
869  %r = urem i8 %x, %y
870  store i8 %r, i8 addrspace(1)* %out
871  ret void
872}
873
874define amdgpu_kernel void @sdiv_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
875; CHECK-LABEL: @sdiv_i8(
876; CHECK-NEXT:    [[TMP1:%.*]] = sext i8 [[X:%.*]] to i32
877; CHECK-NEXT:    [[TMP2:%.*]] = sext i8 [[Y:%.*]] to i32
878; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
879; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
880; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP4]], 1
881; CHECK-NEXT:    [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
882; CHECK-NEXT:    [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
883; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
884; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
885; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
886; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
887; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
888; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
889; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
890; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
891; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
892; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
893; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
894; CHECK-NEXT:    [[TMP19:%.*]] = shl i32 [[TMP18]], 24
895; CHECK-NEXT:    [[TMP20:%.*]] = ashr i32 [[TMP19]], 24
896; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i8
897; CHECK-NEXT:    store i8 [[TMP21]], i8 addrspace(1)* [[OUT:%.*]], align 1
898; CHECK-NEXT:    ret void
899;
900; GFX6-LABEL: sdiv_i8:
901; GFX6:       ; %bb.0:
902; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
903; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
904; GFX6-NEXT:    s_mov_b32 s3, 0xf000
905; GFX6-NEXT:    s_mov_b32 s2, -1
906; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
907; GFX6-NEXT:    s_bfe_i32 s5, s4, 0x80008
908; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s5
909; GFX6-NEXT:    s_sext_i32_i8 s4, s4
910; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s4
911; GFX6-NEXT:    s_xor_b32 s4, s4, s5
912; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
913; GFX6-NEXT:    s_ashr_i32 s4, s4, 30
914; GFX6-NEXT:    s_or_b32 s4, s4, 1
915; GFX6-NEXT:    v_mov_b32_e32 v3, s4
916; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
917; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
918; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
919; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
920; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
921; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
922; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
923; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
924; GFX6-NEXT:    s_endpgm
925;
926; GFX9-LABEL: sdiv_i8:
927; GFX9:       ; %bb.0:
928; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
929; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
930; GFX9-NEXT:    v_mov_b32_e32 v1, 0
931; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
932; GFX9-NEXT:    s_bfe_i32 s0, s4, 0x80008
933; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s0
934; GFX9-NEXT:    s_sext_i32_i8 s1, s4
935; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s1
936; GFX9-NEXT:    s_xor_b32 s0, s1, s0
937; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
938; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
939; GFX9-NEXT:    s_or_b32 s4, s0, 1
940; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
941; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
942; GFX9-NEXT:    v_mad_f32 v2, -v3, v0, v2
943; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
944; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
945; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
946; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
947; GFX9-NEXT:    v_add_u32_e32 v0, s0, v3
948; GFX9-NEXT:    global_store_byte v1, v0, s[2:3]
949; GFX9-NEXT:    s_endpgm
950  %r = sdiv i8 %x, %y
951  store i8 %r, i8 addrspace(1)* %out
952  ret void
953}
954
955define amdgpu_kernel void @srem_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
956; CHECK-LABEL: @srem_i8(
957; CHECK-NEXT:    [[TMP1:%.*]] = sext i8 [[X:%.*]] to i32
958; CHECK-NEXT:    [[TMP2:%.*]] = sext i8 [[Y:%.*]] to i32
959; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
960; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
961; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP4]], 1
962; CHECK-NEXT:    [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
963; CHECK-NEXT:    [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
964; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
965; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
966; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
967; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
968; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
969; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
970; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
971; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
972; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
973; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
974; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
975; CHECK-NEXT:    [[TMP19:%.*]] = mul i32 [[TMP18]], [[TMP2]]
976; CHECK-NEXT:    [[TMP20:%.*]] = sub i32 [[TMP1]], [[TMP19]]
977; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 24
978; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 24
979; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i8
980; CHECK-NEXT:    store i8 [[TMP23]], i8 addrspace(1)* [[OUT:%.*]], align 1
981; CHECK-NEXT:    ret void
982;
983; GFX6-LABEL: srem_i8:
984; GFX6:       ; %bb.0:
985; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
986; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
987; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
988; GFX6-NEXT:    s_bfe_i32 s2, s4, 0x80008
989; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s2
990; GFX6-NEXT:    s_sext_i32_i8 s5, s4
991; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s5
992; GFX6-NEXT:    s_xor_b32 s2, s5, s2
993; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
994; GFX6-NEXT:    s_ashr_i32 s2, s2, 30
995; GFX6-NEXT:    s_or_b32 s2, s2, 1
996; GFX6-NEXT:    v_mov_b32_e32 v3, s2
997; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
998; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
999; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
1000; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
1001; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
1002; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
1003; GFX6-NEXT:    s_lshr_b32 s3, s4, 8
1004; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1005; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s3
1006; GFX6-NEXT:    s_mov_b32 s3, 0xf000
1007; GFX6-NEXT:    s_mov_b32 s2, -1
1008; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
1009; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
1010; GFX6-NEXT:    s_endpgm
1011;
1012; GFX9-LABEL: srem_i8:
1013; GFX9:       ; %bb.0:
1014; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
1015; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
1016; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1017; GFX9-NEXT:    s_bfe_i32 s0, s4, 0x80008
1018; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s0
1019; GFX9-NEXT:    s_sext_i32_i8 s1, s4
1020; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s1
1021; GFX9-NEXT:    s_xor_b32 s0, s1, s0
1022; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
1023; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
1024; GFX9-NEXT:    s_lshr_b32 s5, s4, 8
1025; GFX9-NEXT:    s_or_b32 s6, s0, 1
1026; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
1027; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
1028; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
1029; GFX9-NEXT:    v_cvt_i32_f32_e32 v2, v2
1030; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
1031; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
1032; GFX9-NEXT:    s_cselect_b32 s0, s6, 0
1033; GFX9-NEXT:    v_add_u32_e32 v0, s0, v2
1034; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s5
1035; GFX9-NEXT:    v_mov_b32_e32 v1, 0
1036; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
1037; GFX9-NEXT:    global_store_byte v1, v0, s[2:3]
1038; GFX9-NEXT:    s_endpgm
1039  %r = srem i8 %x, %y
1040  store i8 %r, i8 addrspace(1)* %out
1041  ret void
1042}
1043
1044define amdgpu_kernel void @udiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
1045; CHECK-LABEL: @udiv_v4i32(
1046; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i64 0
1047; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 0
1048; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float
1049; CHECK-NEXT:    [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])
1050; CHECK-NEXT:    [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41EFFFFFC0000000
1051; CHECK-NEXT:    [[TMP6:%.*]] = fptoui float [[TMP5]] to i32
1052; CHECK-NEXT:    [[TMP7:%.*]] = sub i32 0, [[TMP2]]
1053; CHECK-NEXT:    [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP6]]
1054; CHECK-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP6]] to i64
1055; CHECK-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP8]] to i64
1056; CHECK-NEXT:    [[TMP11:%.*]] = mul i64 [[TMP9]], [[TMP10]]
1057; CHECK-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
1058; CHECK-NEXT:    [[TMP13:%.*]] = lshr i64 [[TMP11]], 32
1059; CHECK-NEXT:    [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32
1060; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP6]], [[TMP14]]
1061; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP1]] to i64
1062; CHECK-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP15]] to i64
1063; CHECK-NEXT:    [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]
1064; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
1065; CHECK-NEXT:    [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
1066; CHECK-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
1067; CHECK-NEXT:    [[TMP22:%.*]] = mul i32 [[TMP21]], [[TMP2]]
1068; CHECK-NEXT:    [[TMP23:%.*]] = sub i32 [[TMP1]], [[TMP22]]
1069; CHECK-NEXT:    [[TMP24:%.*]] = icmp uge i32 [[TMP23]], [[TMP2]]
1070; CHECK-NEXT:    [[TMP25:%.*]] = add i32 [[TMP21]], 1
1071; CHECK-NEXT:    [[TMP26:%.*]] = select i1 [[TMP24]], i32 [[TMP25]], i32 [[TMP21]]
1072; CHECK-NEXT:    [[TMP27:%.*]] = sub i32 [[TMP23]], [[TMP2]]
1073; CHECK-NEXT:    [[TMP28:%.*]] = select i1 [[TMP24]], i32 [[TMP27]], i32 [[TMP23]]
1074; CHECK-NEXT:    [[TMP29:%.*]] = icmp uge i32 [[TMP28]], [[TMP2]]
1075; CHECK-NEXT:    [[TMP30:%.*]] = add i32 [[TMP26]], 1
1076; CHECK-NEXT:    [[TMP31:%.*]] = select i1 [[TMP29]], i32 [[TMP30]], i32 [[TMP26]]
1077; CHECK-NEXT:    [[TMP32:%.*]] = insertelement <4 x i32> undef, i32 [[TMP31]], i64 0
1078; CHECK-NEXT:    [[TMP33:%.*]] = extractelement <4 x i32> [[X]], i64 1
1079; CHECK-NEXT:    [[TMP34:%.*]] = extractelement <4 x i32> [[Y]], i64 1
1080; CHECK-NEXT:    [[TMP35:%.*]] = uitofp i32 [[TMP34]] to float
1081; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])
1082; CHECK-NEXT:    [[TMP37:%.*]] = fmul fast float [[TMP36]], 0x41EFFFFFC0000000
1083; CHECK-NEXT:    [[TMP38:%.*]] = fptoui float [[TMP37]] to i32
1084; CHECK-NEXT:    [[TMP39:%.*]] = sub i32 0, [[TMP34]]
1085; CHECK-NEXT:    [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP38]]
1086; CHECK-NEXT:    [[TMP41:%.*]] = zext i32 [[TMP38]] to i64
1087; CHECK-NEXT:    [[TMP42:%.*]] = zext i32 [[TMP40]] to i64
1088; CHECK-NEXT:    [[TMP43:%.*]] = mul i64 [[TMP41]], [[TMP42]]
1089; CHECK-NEXT:    [[TMP44:%.*]] = trunc i64 [[TMP43]] to i32
1090; CHECK-NEXT:    [[TMP45:%.*]] = lshr i64 [[TMP43]], 32
1091; CHECK-NEXT:    [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32
1092; CHECK-NEXT:    [[TMP47:%.*]] = add i32 [[TMP38]], [[TMP46]]
1093; CHECK-NEXT:    [[TMP48:%.*]] = zext i32 [[TMP33]] to i64
1094; CHECK-NEXT:    [[TMP49:%.*]] = zext i32 [[TMP47]] to i64
1095; CHECK-NEXT:    [[TMP50:%.*]] = mul i64 [[TMP48]], [[TMP49]]
1096; CHECK-NEXT:    [[TMP51:%.*]] = trunc i64 [[TMP50]] to i32
1097; CHECK-NEXT:    [[TMP52:%.*]] = lshr i64 [[TMP50]], 32
1098; CHECK-NEXT:    [[TMP53:%.*]] = trunc i64 [[TMP52]] to i32
1099; CHECK-NEXT:    [[TMP54:%.*]] = mul i32 [[TMP53]], [[TMP34]]
1100; CHECK-NEXT:    [[TMP55:%.*]] = sub i32 [[TMP33]], [[TMP54]]
1101; CHECK-NEXT:    [[TMP56:%.*]] = icmp uge i32 [[TMP55]], [[TMP34]]
1102; CHECK-NEXT:    [[TMP57:%.*]] = add i32 [[TMP53]], 1
1103; CHECK-NEXT:    [[TMP58:%.*]] = select i1 [[TMP56]], i32 [[TMP57]], i32 [[TMP53]]
1104; CHECK-NEXT:    [[TMP59:%.*]] = sub i32 [[TMP55]], [[TMP34]]
1105; CHECK-NEXT:    [[TMP60:%.*]] = select i1 [[TMP56]], i32 [[TMP59]], i32 [[TMP55]]
1106; CHECK-NEXT:    [[TMP61:%.*]] = icmp uge i32 [[TMP60]], [[TMP34]]
1107; CHECK-NEXT:    [[TMP62:%.*]] = add i32 [[TMP58]], 1
1108; CHECK-NEXT:    [[TMP63:%.*]] = select i1 [[TMP61]], i32 [[TMP62]], i32 [[TMP58]]
1109; CHECK-NEXT:    [[TMP64:%.*]] = insertelement <4 x i32> [[TMP32]], i32 [[TMP63]], i64 1
1110; CHECK-NEXT:    [[TMP65:%.*]] = extractelement <4 x i32> [[X]], i64 2
1111; CHECK-NEXT:    [[TMP66:%.*]] = extractelement <4 x i32> [[Y]], i64 2
1112; CHECK-NEXT:    [[TMP67:%.*]] = uitofp i32 [[TMP66]] to float
1113; CHECK-NEXT:    [[TMP68:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP67]])
1114; CHECK-NEXT:    [[TMP69:%.*]] = fmul fast float [[TMP68]], 0x41EFFFFFC0000000
1115; CHECK-NEXT:    [[TMP70:%.*]] = fptoui float [[TMP69]] to i32
1116; CHECK-NEXT:    [[TMP71:%.*]] = sub i32 0, [[TMP66]]
1117; CHECK-NEXT:    [[TMP72:%.*]] = mul i32 [[TMP71]], [[TMP70]]
1118; CHECK-NEXT:    [[TMP73:%.*]] = zext i32 [[TMP70]] to i64
1119; CHECK-NEXT:    [[TMP74:%.*]] = zext i32 [[TMP72]] to i64
1120; CHECK-NEXT:    [[TMP75:%.*]] = mul i64 [[TMP73]], [[TMP74]]
1121; CHECK-NEXT:    [[TMP76:%.*]] = trunc i64 [[TMP75]] to i32
1122; CHECK-NEXT:    [[TMP77:%.*]] = lshr i64 [[TMP75]], 32
1123; CHECK-NEXT:    [[TMP78:%.*]] = trunc i64 [[TMP77]] to i32
1124; CHECK-NEXT:    [[TMP79:%.*]] = add i32 [[TMP70]], [[TMP78]]
1125; CHECK-NEXT:    [[TMP80:%.*]] = zext i32 [[TMP65]] to i64
1126; CHECK-NEXT:    [[TMP81:%.*]] = zext i32 [[TMP79]] to i64
1127; CHECK-NEXT:    [[TMP82:%.*]] = mul i64 [[TMP80]], [[TMP81]]
1128; CHECK-NEXT:    [[TMP83:%.*]] = trunc i64 [[TMP82]] to i32
1129; CHECK-NEXT:    [[TMP84:%.*]] = lshr i64 [[TMP82]], 32
1130; CHECK-NEXT:    [[TMP85:%.*]] = trunc i64 [[TMP84]] to i32
1131; CHECK-NEXT:    [[TMP86:%.*]] = mul i32 [[TMP85]], [[TMP66]]
1132; CHECK-NEXT:    [[TMP87:%.*]] = sub i32 [[TMP65]], [[TMP86]]
1133; CHECK-NEXT:    [[TMP88:%.*]] = icmp uge i32 [[TMP87]], [[TMP66]]
1134; CHECK-NEXT:    [[TMP89:%.*]] = add i32 [[TMP85]], 1
1135; CHECK-NEXT:    [[TMP90:%.*]] = select i1 [[TMP88]], i32 [[TMP89]], i32 [[TMP85]]
1136; CHECK-NEXT:    [[TMP91:%.*]] = sub i32 [[TMP87]], [[TMP66]]
1137; CHECK-NEXT:    [[TMP92:%.*]] = select i1 [[TMP88]], i32 [[TMP91]], i32 [[TMP87]]
1138; CHECK-NEXT:    [[TMP93:%.*]] = icmp uge i32 [[TMP92]], [[TMP66]]
1139; CHECK-NEXT:    [[TMP94:%.*]] = add i32 [[TMP90]], 1
1140; CHECK-NEXT:    [[TMP95:%.*]] = select i1 [[TMP93]], i32 [[TMP94]], i32 [[TMP90]]
1141; CHECK-NEXT:    [[TMP96:%.*]] = insertelement <4 x i32> [[TMP64]], i32 [[TMP95]], i64 2
1142; CHECK-NEXT:    [[TMP97:%.*]] = extractelement <4 x i32> [[X]], i64 3
1143; CHECK-NEXT:    [[TMP98:%.*]] = extractelement <4 x i32> [[Y]], i64 3
1144; CHECK-NEXT:    [[TMP99:%.*]] = uitofp i32 [[TMP98]] to float
1145; CHECK-NEXT:    [[TMP100:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP99]])
1146; CHECK-NEXT:    [[TMP101:%.*]] = fmul fast float [[TMP100]], 0x41EFFFFFC0000000
1147; CHECK-NEXT:    [[TMP102:%.*]] = fptoui float [[TMP101]] to i32
1148; CHECK-NEXT:    [[TMP103:%.*]] = sub i32 0, [[TMP98]]
1149; CHECK-NEXT:    [[TMP104:%.*]] = mul i32 [[TMP103]], [[TMP102]]
1150; CHECK-NEXT:    [[TMP105:%.*]] = zext i32 [[TMP102]] to i64
1151; CHECK-NEXT:    [[TMP106:%.*]] = zext i32 [[TMP104]] to i64
1152; CHECK-NEXT:    [[TMP107:%.*]] = mul i64 [[TMP105]], [[TMP106]]
1153; CHECK-NEXT:    [[TMP108:%.*]] = trunc i64 [[TMP107]] to i32
1154; CHECK-NEXT:    [[TMP109:%.*]] = lshr i64 [[TMP107]], 32
1155; CHECK-NEXT:    [[TMP110:%.*]] = trunc i64 [[TMP109]] to i32
1156; CHECK-NEXT:    [[TMP111:%.*]] = add i32 [[TMP102]], [[TMP110]]
1157; CHECK-NEXT:    [[TMP112:%.*]] = zext i32 [[TMP97]] to i64
1158; CHECK-NEXT:    [[TMP113:%.*]] = zext i32 [[TMP111]] to i64
1159; CHECK-NEXT:    [[TMP114:%.*]] = mul i64 [[TMP112]], [[TMP113]]
1160; CHECK-NEXT:    [[TMP115:%.*]] = trunc i64 [[TMP114]] to i32
1161; CHECK-NEXT:    [[TMP116:%.*]] = lshr i64 [[TMP114]], 32
1162; CHECK-NEXT:    [[TMP117:%.*]] = trunc i64 [[TMP116]] to i32
1163; CHECK-NEXT:    [[TMP118:%.*]] = mul i32 [[TMP117]], [[TMP98]]
1164; CHECK-NEXT:    [[TMP119:%.*]] = sub i32 [[TMP97]], [[TMP118]]
1165; CHECK-NEXT:    [[TMP120:%.*]] = icmp uge i32 [[TMP119]], [[TMP98]]
1166; CHECK-NEXT:    [[TMP121:%.*]] = add i32 [[TMP117]], 1
1167; CHECK-NEXT:    [[TMP122:%.*]] = select i1 [[TMP120]], i32 [[TMP121]], i32 [[TMP117]]
1168; CHECK-NEXT:    [[TMP123:%.*]] = sub i32 [[TMP119]], [[TMP98]]
1169; CHECK-NEXT:    [[TMP124:%.*]] = select i1 [[TMP120]], i32 [[TMP123]], i32 [[TMP119]]
1170; CHECK-NEXT:    [[TMP125:%.*]] = icmp uge i32 [[TMP124]], [[TMP98]]
1171; CHECK-NEXT:    [[TMP126:%.*]] = add i32 [[TMP122]], 1
1172; CHECK-NEXT:    [[TMP127:%.*]] = select i1 [[TMP125]], i32 [[TMP126]], i32 [[TMP122]]
1173; CHECK-NEXT:    [[TMP128:%.*]] = insertelement <4 x i32> [[TMP96]], i32 [[TMP127]], i64 3
1174; CHECK-NEXT:    store <4 x i32> [[TMP128]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16
1175; CHECK-NEXT:    ret void
1176;
1177; GFX6-LABEL: udiv_v4i32:
1178; GFX6:       ; %bb.0:
1179; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
1180; GFX6-NEXT:    s_mov_b32 s3, 0x4f7ffffe
1181; GFX6-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x9
1182; GFX6-NEXT:    s_mov_b32 s15, 0xf000
1183; GFX6-NEXT:    s_mov_b32 s14, -1
1184; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
1185; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
1186; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
1187; GFX6-NEXT:    s_sub_i32 s2, 0, s8
1188; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s10
1189; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1190; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1191; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s11
1192; GFX6-NEXT:    v_mul_f32_e32 v0, s3, v0
1193; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
1194; GFX6-NEXT:    v_mul_f32_e32 v1, s3, v1
1195; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
1196; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
1197; GFX6-NEXT:    s_sub_i32 s2, 0, s9
1198; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v1
1199; GFX6-NEXT:    s_sub_i32 s2, 0, s10
1200; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
1201; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
1202; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1203; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
1204; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
1205; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
1206; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s8
1207; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
1208; GFX6-NEXT:    v_mul_lo_u32 v5, v1, s9
1209; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s4, v2
1210; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v2
1211; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[0:1]
1212; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v2
1213; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
1214; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
1215; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
1216; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v4
1217; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1218; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s5, v5
1219; GFX6-NEXT:    v_mul_f32_e32 v2, s3, v2
1220; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
1221; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v1
1222; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v3
1223; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[0:1]
1224; GFX6-NEXT:    v_mul_lo_u32 v4, s2, v2
1225; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s9, v3
1226; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
1227; GFX6-NEXT:    v_mul_hi_u32 v4, v2, v4
1228; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v1
1229; GFX6-NEXT:    s_sub_i32 s0, 0, s11
1230; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
1231; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v6
1232; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
1233; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
1234; GFX6-NEXT:    v_mul_hi_u32 v2, s6, v2
1235; GFX6-NEXT:    v_mul_f32_e32 v4, s3, v4
1236; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
1237; GFX6-NEXT:    v_mul_lo_u32 v3, v2, s10
1238; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
1239; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v4
1240; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s6, v3
1241; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v3
1242; GFX6-NEXT:    v_mul_hi_u32 v5, v4, v5
1243; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v6, s[0:1]
1244; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, s10, v3
1245; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1246; GFX6-NEXT:    v_mul_hi_u32 v4, s7, v4
1247; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v6, s[0:1]
1248; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v2
1249; GFX6-NEXT:    v_mul_lo_u32 v6, v4, s11
1250; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
1251; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
1252; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
1253; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s7, v6
1254; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v3
1255; GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]
1256; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s11, v3
1257; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
1258; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
1259; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
1260; GFX6-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc
1261; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[12:15], 0
1262; GFX6-NEXT:    s_endpgm
1263;
1264; GFX9-LABEL: udiv_v4i32:
1265; GFX9:       ; %bb.0:
1266; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
1267; GFX9-NEXT:    s_mov_b32 s12, 0x4f7ffffe
1268; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
1269; GFX9-NEXT:    v_mov_b32_e32 v4, 0
1270; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1271; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
1272; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
1273; GFX9-NEXT:    s_sub_i32 s2, 0, s8
1274; GFX9-NEXT:    s_sub_i32 s3, 0, s9
1275; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1276; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1277; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s10
1278; GFX9-NEXT:    v_mul_f32_e32 v0, s12, v0
1279; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
1280; GFX9-NEXT:    v_mul_f32_e32 v1, s12, v1
1281; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
1282; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v5
1283; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v0
1284; GFX9-NEXT:    s_sub_i32 s2, 0, s10
1285; GFX9-NEXT:    v_mul_lo_u32 v3, s3, v1
1286; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
1287; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
1288; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
1289; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
1290; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
1291; GFX9-NEXT:    v_mul_f32_e32 v3, s12, v5
1292; GFX9-NEXT:    v_mul_hi_u32 v1, s5, v1
1293; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s8
1294; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, s11
1295; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
1296; GFX9-NEXT:    v_add_u32_e32 v7, 1, v0
1297; GFX9-NEXT:    v_sub_u32_e32 v5, s4, v5
1298; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v5
1299; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v7, vcc
1300; GFX9-NEXT:    v_subrev_u32_e32 v7, s8, v5
1301; GFX9-NEXT:    v_mul_lo_u32 v6, v1, s9
1302; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
1303; GFX9-NEXT:    v_add_u32_e32 v7, 1, v0
1304; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v5
1305; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v2
1306; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v7, vcc
1307; GFX9-NEXT:    v_mul_lo_u32 v7, s2, v3
1308; GFX9-NEXT:    v_sub_u32_e32 v6, s5, v6
1309; GFX9-NEXT:    v_add_u32_e32 v5, 1, v1
1310; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v6
1311; GFX9-NEXT:    v_mul_f32_e32 v2, s12, v2
1312; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
1313; GFX9-NEXT:    v_mul_hi_u32 v5, v3, v7
1314; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
1315; GFX9-NEXT:    s_sub_i32 s2, 0, s11
1316; GFX9-NEXT:    v_subrev_u32_e32 v7, s9, v6
1317; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
1318; GFX9-NEXT:    v_mul_lo_u32 v5, s2, v2
1319; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v3
1320; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc
1321; GFX9-NEXT:    v_add_u32_e32 v7, 1, v1
1322; GFX9-NEXT:    v_mul_hi_u32 v5, v2, v5
1323; GFX9-NEXT:    v_mul_lo_u32 v8, v3, s10
1324; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v6
1325; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
1326; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
1327; GFX9-NEXT:    v_mul_hi_u32 v5, s7, v2
1328; GFX9-NEXT:    v_sub_u32_e32 v6, s6, v8
1329; GFX9-NEXT:    v_add_u32_e32 v7, 1, v3
1330; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v6
1331; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v7, vcc
1332; GFX9-NEXT:    v_subrev_u32_e32 v3, s10, v6
1333; GFX9-NEXT:    v_cndmask_b32_e32 v3, v6, v3, vcc
1334; GFX9-NEXT:    v_mul_lo_u32 v6, v5, s11
1335; GFX9-NEXT:    v_add_u32_e32 v7, 1, v2
1336; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
1337; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v7, vcc
1338; GFX9-NEXT:    v_sub_u32_e32 v3, s7, v6
1339; GFX9-NEXT:    v_add_u32_e32 v6, 1, v5
1340; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
1341; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
1342; GFX9-NEXT:    v_subrev_u32_e32 v6, s11, v3
1343; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
1344; GFX9-NEXT:    v_add_u32_e32 v6, 1, v5
1345; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
1346; GFX9-NEXT:    v_cndmask_b32_e32 v3, v5, v6, vcc
1347; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
1348; GFX9-NEXT:    s_endpgm
1349  %r = udiv <4 x i32> %x, %y
1350  store <4 x i32> %r, <4 x i32> addrspace(1)* %out
1351  ret void
1352}
1353
1354define amdgpu_kernel void @urem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
1355; CHECK-LABEL: @urem_v4i32(
1356; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i64 0
1357; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 0
1358; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float
1359; CHECK-NEXT:    [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])
1360; CHECK-NEXT:    [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41EFFFFFC0000000
1361; CHECK-NEXT:    [[TMP6:%.*]] = fptoui float [[TMP5]] to i32
1362; CHECK-NEXT:    [[TMP7:%.*]] = sub i32 0, [[TMP2]]
1363; CHECK-NEXT:    [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP6]]
1364; CHECK-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP6]] to i64
1365; CHECK-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP8]] to i64
1366; CHECK-NEXT:    [[TMP11:%.*]] = mul i64 [[TMP9]], [[TMP10]]
1367; CHECK-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
1368; CHECK-NEXT:    [[TMP13:%.*]] = lshr i64 [[TMP11]], 32
1369; CHECK-NEXT:    [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32
1370; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP6]], [[TMP14]]
1371; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP1]] to i64
1372; CHECK-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP15]] to i64
1373; CHECK-NEXT:    [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]
1374; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
1375; CHECK-NEXT:    [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
1376; CHECK-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
1377; CHECK-NEXT:    [[TMP22:%.*]] = mul i32 [[TMP21]], [[TMP2]]
1378; CHECK-NEXT:    [[TMP23:%.*]] = sub i32 [[TMP1]], [[TMP22]]
1379; CHECK-NEXT:    [[TMP24:%.*]] = icmp uge i32 [[TMP23]], [[TMP2]]
1380; CHECK-NEXT:    [[TMP25:%.*]] = sub i32 [[TMP23]], [[TMP2]]
1381; CHECK-NEXT:    [[TMP26:%.*]] = select i1 [[TMP24]], i32 [[TMP25]], i32 [[TMP23]]
1382; CHECK-NEXT:    [[TMP27:%.*]] = icmp uge i32 [[TMP26]], [[TMP2]]
1383; CHECK-NEXT:    [[TMP28:%.*]] = sub i32 [[TMP26]], [[TMP2]]
1384; CHECK-NEXT:    [[TMP29:%.*]] = select i1 [[TMP27]], i32 [[TMP28]], i32 [[TMP26]]
1385; CHECK-NEXT:    [[TMP30:%.*]] = insertelement <4 x i32> undef, i32 [[TMP29]], i64 0
1386; CHECK-NEXT:    [[TMP31:%.*]] = extractelement <4 x i32> [[X]], i64 1
1387; CHECK-NEXT:    [[TMP32:%.*]] = extractelement <4 x i32> [[Y]], i64 1
1388; CHECK-NEXT:    [[TMP33:%.*]] = uitofp i32 [[TMP32]] to float
1389; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])
1390; CHECK-NEXT:    [[TMP35:%.*]] = fmul fast float [[TMP34]], 0x41EFFFFFC0000000
1391; CHECK-NEXT:    [[TMP36:%.*]] = fptoui float [[TMP35]] to i32
1392; CHECK-NEXT:    [[TMP37:%.*]] = sub i32 0, [[TMP32]]
1393; CHECK-NEXT:    [[TMP38:%.*]] = mul i32 [[TMP37]], [[TMP36]]
1394; CHECK-NEXT:    [[TMP39:%.*]] = zext i32 [[TMP36]] to i64
1395; CHECK-NEXT:    [[TMP40:%.*]] = zext i32 [[TMP38]] to i64
1396; CHECK-NEXT:    [[TMP41:%.*]] = mul i64 [[TMP39]], [[TMP40]]
1397; CHECK-NEXT:    [[TMP42:%.*]] = trunc i64 [[TMP41]] to i32
1398; CHECK-NEXT:    [[TMP43:%.*]] = lshr i64 [[TMP41]], 32
1399; CHECK-NEXT:    [[TMP44:%.*]] = trunc i64 [[TMP43]] to i32
1400; CHECK-NEXT:    [[TMP45:%.*]] = add i32 [[TMP36]], [[TMP44]]
1401; CHECK-NEXT:    [[TMP46:%.*]] = zext i32 [[TMP31]] to i64
1402; CHECK-NEXT:    [[TMP47:%.*]] = zext i32 [[TMP45]] to i64
1403; CHECK-NEXT:    [[TMP48:%.*]] = mul i64 [[TMP46]], [[TMP47]]
1404; CHECK-NEXT:    [[TMP49:%.*]] = trunc i64 [[TMP48]] to i32
1405; CHECK-NEXT:    [[TMP50:%.*]] = lshr i64 [[TMP48]], 32
1406; CHECK-NEXT:    [[TMP51:%.*]] = trunc i64 [[TMP50]] to i32
1407; CHECK-NEXT:    [[TMP52:%.*]] = mul i32 [[TMP51]], [[TMP32]]
1408; CHECK-NEXT:    [[TMP53:%.*]] = sub i32 [[TMP31]], [[TMP52]]
1409; CHECK-NEXT:    [[TMP54:%.*]] = icmp uge i32 [[TMP53]], [[TMP32]]
1410; CHECK-NEXT:    [[TMP55:%.*]] = sub i32 [[TMP53]], [[TMP32]]
1411; CHECK-NEXT:    [[TMP56:%.*]] = select i1 [[TMP54]], i32 [[TMP55]], i32 [[TMP53]]
1412; CHECK-NEXT:    [[TMP57:%.*]] = icmp uge i32 [[TMP56]], [[TMP32]]
1413; CHECK-NEXT:    [[TMP58:%.*]] = sub i32 [[TMP56]], [[TMP32]]
1414; CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP57]], i32 [[TMP58]], i32 [[TMP56]]
1415; CHECK-NEXT:    [[TMP60:%.*]] = insertelement <4 x i32> [[TMP30]], i32 [[TMP59]], i64 1
1416; CHECK-NEXT:    [[TMP61:%.*]] = extractelement <4 x i32> [[X]], i64 2
1417; CHECK-NEXT:    [[TMP62:%.*]] = extractelement <4 x i32> [[Y]], i64 2
1418; CHECK-NEXT:    [[TMP63:%.*]] = uitofp i32 [[TMP62]] to float
1419; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP63]])
1420; CHECK-NEXT:    [[TMP65:%.*]] = fmul fast float [[TMP64]], 0x41EFFFFFC0000000
1421; CHECK-NEXT:    [[TMP66:%.*]] = fptoui float [[TMP65]] to i32
1422; CHECK-NEXT:    [[TMP67:%.*]] = sub i32 0, [[TMP62]]
1423; CHECK-NEXT:    [[TMP68:%.*]] = mul i32 [[TMP67]], [[TMP66]]
1424; CHECK-NEXT:    [[TMP69:%.*]] = zext i32 [[TMP66]] to i64
1425; CHECK-NEXT:    [[TMP70:%.*]] = zext i32 [[TMP68]] to i64
1426; CHECK-NEXT:    [[TMP71:%.*]] = mul i64 [[TMP69]], [[TMP70]]
1427; CHECK-NEXT:    [[TMP72:%.*]] = trunc i64 [[TMP71]] to i32
1428; CHECK-NEXT:    [[TMP73:%.*]] = lshr i64 [[TMP71]], 32
1429; CHECK-NEXT:    [[TMP74:%.*]] = trunc i64 [[TMP73]] to i32
1430; CHECK-NEXT:    [[TMP75:%.*]] = add i32 [[TMP66]], [[TMP74]]
1431; CHECK-NEXT:    [[TMP76:%.*]] = zext i32 [[TMP61]] to i64
1432; CHECK-NEXT:    [[TMP77:%.*]] = zext i32 [[TMP75]] to i64
1433; CHECK-NEXT:    [[TMP78:%.*]] = mul i64 [[TMP76]], [[TMP77]]
1434; CHECK-NEXT:    [[TMP79:%.*]] = trunc i64 [[TMP78]] to i32
1435; CHECK-NEXT:    [[TMP80:%.*]] = lshr i64 [[TMP78]], 32
1436; CHECK-NEXT:    [[TMP81:%.*]] = trunc i64 [[TMP80]] to i32
1437; CHECK-NEXT:    [[TMP82:%.*]] = mul i32 [[TMP81]], [[TMP62]]
1438; CHECK-NEXT:    [[TMP83:%.*]] = sub i32 [[TMP61]], [[TMP82]]
1439; CHECK-NEXT:    [[TMP84:%.*]] = icmp uge i32 [[TMP83]], [[TMP62]]
1440; CHECK-NEXT:    [[TMP85:%.*]] = sub i32 [[TMP83]], [[TMP62]]
1441; CHECK-NEXT:    [[TMP86:%.*]] = select i1 [[TMP84]], i32 [[TMP85]], i32 [[TMP83]]
1442; CHECK-NEXT:    [[TMP87:%.*]] = icmp uge i32 [[TMP86]], [[TMP62]]
1443; CHECK-NEXT:    [[TMP88:%.*]] = sub i32 [[TMP86]], [[TMP62]]
1444; CHECK-NEXT:    [[TMP89:%.*]] = select i1 [[TMP87]], i32 [[TMP88]], i32 [[TMP86]]
1445; CHECK-NEXT:    [[TMP90:%.*]] = insertelement <4 x i32> [[TMP60]], i32 [[TMP89]], i64 2
1446; CHECK-NEXT:    [[TMP91:%.*]] = extractelement <4 x i32> [[X]], i64 3
1447; CHECK-NEXT:    [[TMP92:%.*]] = extractelement <4 x i32> [[Y]], i64 3
1448; CHECK-NEXT:    [[TMP93:%.*]] = uitofp i32 [[TMP92]] to float
1449; CHECK-NEXT:    [[TMP94:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP93]])
1450; CHECK-NEXT:    [[TMP95:%.*]] = fmul fast float [[TMP94]], 0x41EFFFFFC0000000
1451; CHECK-NEXT:    [[TMP96:%.*]] = fptoui float [[TMP95]] to i32
1452; CHECK-NEXT:    [[TMP97:%.*]] = sub i32 0, [[TMP92]]
1453; CHECK-NEXT:    [[TMP98:%.*]] = mul i32 [[TMP97]], [[TMP96]]
1454; CHECK-NEXT:    [[TMP99:%.*]] = zext i32 [[TMP96]] to i64
1455; CHECK-NEXT:    [[TMP100:%.*]] = zext i32 [[TMP98]] to i64
1456; CHECK-NEXT:    [[TMP101:%.*]] = mul i64 [[TMP99]], [[TMP100]]
1457; CHECK-NEXT:    [[TMP102:%.*]] = trunc i64 [[TMP101]] to i32
1458; CHECK-NEXT:    [[TMP103:%.*]] = lshr i64 [[TMP101]], 32
1459; CHECK-NEXT:    [[TMP104:%.*]] = trunc i64 [[TMP103]] to i32
1460; CHECK-NEXT:    [[TMP105:%.*]] = add i32 [[TMP96]], [[TMP104]]
1461; CHECK-NEXT:    [[TMP106:%.*]] = zext i32 [[TMP91]] to i64
1462; CHECK-NEXT:    [[TMP107:%.*]] = zext i32 [[TMP105]] to i64
1463; CHECK-NEXT:    [[TMP108:%.*]] = mul i64 [[TMP106]], [[TMP107]]
1464; CHECK-NEXT:    [[TMP109:%.*]] = trunc i64 [[TMP108]] to i32
1465; CHECK-NEXT:    [[TMP110:%.*]] = lshr i64 [[TMP108]], 32
1466; CHECK-NEXT:    [[TMP111:%.*]] = trunc i64 [[TMP110]] to i32
1467; CHECK-NEXT:    [[TMP112:%.*]] = mul i32 [[TMP111]], [[TMP92]]
1468; CHECK-NEXT:    [[TMP113:%.*]] = sub i32 [[TMP91]], [[TMP112]]
1469; CHECK-NEXT:    [[TMP114:%.*]] = icmp uge i32 [[TMP113]], [[TMP92]]
1470; CHECK-NEXT:    [[TMP115:%.*]] = sub i32 [[TMP113]], [[TMP92]]
1471; CHECK-NEXT:    [[TMP116:%.*]] = select i1 [[TMP114]], i32 [[TMP115]], i32 [[TMP113]]
1472; CHECK-NEXT:    [[TMP117:%.*]] = icmp uge i32 [[TMP116]], [[TMP92]]
1473; CHECK-NEXT:    [[TMP118:%.*]] = sub i32 [[TMP116]], [[TMP92]]
1474; CHECK-NEXT:    [[TMP119:%.*]] = select i1 [[TMP117]], i32 [[TMP118]], i32 [[TMP116]]
1475; CHECK-NEXT:    [[TMP120:%.*]] = insertelement <4 x i32> [[TMP90]], i32 [[TMP119]], i64 3
1476; CHECK-NEXT:    store <4 x i32> [[TMP120]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16
1477; CHECK-NEXT:    ret void
1478;
1479; GFX6-LABEL: urem_v4i32:
1480; GFX6:       ; %bb.0:
1481; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
1482; GFX6-NEXT:    s_mov_b32 s13, 0x4f7ffffe
1483; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
1484; GFX6-NEXT:    s_mov_b32 s3, 0xf000
1485; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
1486; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
1487; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
1488; GFX6-NEXT:    s_sub_i32 s2, 0, s8
1489; GFX6-NEXT:    s_sub_i32 s12, 0, s9
1490; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1491; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1492; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s10
1493; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s11
1494; GFX6-NEXT:    v_mul_f32_e32 v0, s13, v0
1495; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
1496; GFX6-NEXT:    v_mul_f32_e32 v1, s13, v1
1497; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
1498; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1499; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
1500; GFX6-NEXT:    s_mov_b32 s2, -1
1501; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v1
1502; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
1503; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
1504; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1505; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
1506; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
1507; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
1508; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s8
1509; GFX6-NEXT:    v_mul_f32_e32 v2, s13, v3
1510; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
1511; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s9
1512; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
1513; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v0
1514; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1515; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1516; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v0
1517; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1518; GFX6-NEXT:    s_sub_i32 s4, 0, s10
1519; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1520; GFX6-NEXT:    v_mul_lo_u32 v3, s4, v2
1521; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
1522; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s9, v1
1523; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1524; GFX6-NEXT:    v_mul_hi_u32 v3, v2, v3
1525; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
1526; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v5
1527; GFX6-NEXT:    s_sub_i32 s4, 0, s11
1528; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1529; GFX6-NEXT:    v_mul_f32_e32 v3, s13, v4
1530; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
1531; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s9, v1
1532; GFX6-NEXT:    v_mul_hi_u32 v2, s6, v2
1533; GFX6-NEXT:    v_mul_lo_u32 v5, s4, v3
1534; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1535; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
1536; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s10
1537; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v5
1538; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s6, v2
1539; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1540; GFX6-NEXT:    v_mul_hi_u32 v3, s7, v3
1541; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s10, v2
1542; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
1543; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s11
1544; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
1545; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s10, v2
1546; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
1547; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
1548; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s7, v3
1549; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s11, v3
1550; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
1551; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
1552; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s11, v3
1553; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
1554; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
1555; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1556; GFX6-NEXT:    s_endpgm
1557;
1558; GFX9-LABEL: urem_v4i32:
1559; GFX9:       ; %bb.0:
1560; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
1561; GFX9-NEXT:    s_mov_b32 s12, 0x4f7ffffe
1562; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
1563; GFX9-NEXT:    v_mov_b32_e32 v4, 0
1564; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1565; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
1566; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
1567; GFX9-NEXT:    s_sub_i32 s2, 0, s8
1568; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s10
1569; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1570; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1571; GFX9-NEXT:    s_sub_i32 s3, 0, s9
1572; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v5
1573; GFX9-NEXT:    v_mul_f32_e32 v0, s12, v0
1574; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
1575; GFX9-NEXT:    v_mul_f32_e32 v1, s12, v1
1576; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
1577; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s11
1578; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v0
1579; GFX9-NEXT:    s_sub_i32 s2, 0, s10
1580; GFX9-NEXT:    v_mul_lo_u32 v3, s3, v1
1581; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
1582; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
1583; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
1584; GFX9-NEXT:    v_mul_f32_e32 v2, s12, v5
1585; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
1586; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
1587; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v6
1588; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
1589; GFX9-NEXT:    v_mul_lo_u32 v5, s2, v2
1590; GFX9-NEXT:    s_sub_i32 s2, 0, s11
1591; GFX9-NEXT:    v_mul_f32_e32 v3, s12, v3
1592; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
1593; GFX9-NEXT:    v_mul_hi_u32 v5, v2, v5
1594; GFX9-NEXT:    v_mul_hi_u32 v1, s5, v1
1595; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s8
1596; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
1597; GFX9-NEXT:    v_mul_lo_u32 v5, s2, v3
1598; GFX9-NEXT:    v_mul_hi_u32 v2, s6, v2
1599; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s9
1600; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
1601; GFX9-NEXT:    v_mul_hi_u32 v5, v3, v5
1602; GFX9-NEXT:    v_subrev_u32_e32 v6, s8, v0
1603; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1604; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
1605; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
1606; GFX9-NEXT:    v_mul_hi_u32 v3, s7, v3
1607; GFX9-NEXT:    v_mul_lo_u32 v2, v2, s10
1608; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v1
1609; GFX9-NEXT:    v_subrev_u32_e32 v6, s8, v0
1610; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1611; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
1612; GFX9-NEXT:    v_subrev_u32_e32 v6, s9, v1
1613; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1614; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc
1615; GFX9-NEXT:    v_mul_lo_u32 v3, v3, s11
1616; GFX9-NEXT:    v_subrev_u32_e32 v6, s9, v1
1617; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1618; GFX9-NEXT:    v_sub_u32_e32 v2, s6, v2
1619; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc
1620; GFX9-NEXT:    v_subrev_u32_e32 v5, s10, v2
1621; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
1622; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
1623; GFX9-NEXT:    v_subrev_u32_e32 v5, s10, v2
1624; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
1625; GFX9-NEXT:    v_sub_u32_e32 v3, s7, v3
1626; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
1627; GFX9-NEXT:    v_subrev_u32_e32 v5, s11, v3
1628; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
1629; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
1630; GFX9-NEXT:    v_subrev_u32_e32 v5, s11, v3
1631; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
1632; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
1633; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
1634; GFX9-NEXT:    s_endpgm
1635  %r = urem <4 x i32> %x, %y
1636  store <4 x i32> %r, <4 x i32> addrspace(1)* %out
1637  ret void
1638}
1639
1640define amdgpu_kernel void @sdiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
1641; CHECK-LABEL: @sdiv_v4i32(
1642; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i64 0
1643; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 0
1644; CHECK-NEXT:    [[TMP3:%.*]] = ashr i32 [[TMP1]], 31
1645; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP2]], 31
1646; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
1647; CHECK-NEXT:    [[TMP6:%.*]] = add i32 [[TMP1]], [[TMP3]]
1648; CHECK-NEXT:    [[TMP7:%.*]] = add i32 [[TMP2]], [[TMP4]]
1649; CHECK-NEXT:    [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP3]]
1650; CHECK-NEXT:    [[TMP9:%.*]] = xor i32 [[TMP7]], [[TMP4]]
1651; CHECK-NEXT:    [[TMP10:%.*]] = uitofp i32 [[TMP9]] to float
1652; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP10]])
1653; CHECK-NEXT:    [[TMP12:%.*]] = fmul fast float [[TMP11]], 0x41EFFFFFC0000000
1654; CHECK-NEXT:    [[TMP13:%.*]] = fptoui float [[TMP12]] to i32
1655; CHECK-NEXT:    [[TMP14:%.*]] = sub i32 0, [[TMP9]]
1656; CHECK-NEXT:    [[TMP15:%.*]] = mul i32 [[TMP14]], [[TMP13]]
1657; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP13]] to i64
1658; CHECK-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP15]] to i64
1659; CHECK-NEXT:    [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]
1660; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
1661; CHECK-NEXT:    [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
1662; CHECK-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
1663; CHECK-NEXT:    [[TMP22:%.*]] = add i32 [[TMP13]], [[TMP21]]
1664; CHECK-NEXT:    [[TMP23:%.*]] = zext i32 [[TMP8]] to i64
1665; CHECK-NEXT:    [[TMP24:%.*]] = zext i32 [[TMP22]] to i64
1666; CHECK-NEXT:    [[TMP25:%.*]] = mul i64 [[TMP23]], [[TMP24]]
1667; CHECK-NEXT:    [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32
1668; CHECK-NEXT:    [[TMP27:%.*]] = lshr i64 [[TMP25]], 32
1669; CHECK-NEXT:    [[TMP28:%.*]] = trunc i64 [[TMP27]] to i32
1670; CHECK-NEXT:    [[TMP29:%.*]] = mul i32 [[TMP28]], [[TMP9]]
1671; CHECK-NEXT:    [[TMP30:%.*]] = sub i32 [[TMP8]], [[TMP29]]
1672; CHECK-NEXT:    [[TMP31:%.*]] = icmp uge i32 [[TMP30]], [[TMP9]]
1673; CHECK-NEXT:    [[TMP32:%.*]] = add i32 [[TMP28]], 1
1674; CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP31]], i32 [[TMP32]], i32 [[TMP28]]
1675; CHECK-NEXT:    [[TMP34:%.*]] = sub i32 [[TMP30]], [[TMP9]]
1676; CHECK-NEXT:    [[TMP35:%.*]] = select i1 [[TMP31]], i32 [[TMP34]], i32 [[TMP30]]
1677; CHECK-NEXT:    [[TMP36:%.*]] = icmp uge i32 [[TMP35]], [[TMP9]]
1678; CHECK-NEXT:    [[TMP37:%.*]] = add i32 [[TMP33]], 1
1679; CHECK-NEXT:    [[TMP38:%.*]] = select i1 [[TMP36]], i32 [[TMP37]], i32 [[TMP33]]
1680; CHECK-NEXT:    [[TMP39:%.*]] = xor i32 [[TMP38]], [[TMP5]]
1681; CHECK-NEXT:    [[TMP40:%.*]] = sub i32 [[TMP39]], [[TMP5]]
1682; CHECK-NEXT:    [[TMP41:%.*]] = insertelement <4 x i32> undef, i32 [[TMP40]], i64 0
1683; CHECK-NEXT:    [[TMP42:%.*]] = extractelement <4 x i32> [[X]], i64 1
1684; CHECK-NEXT:    [[TMP43:%.*]] = extractelement <4 x i32> [[Y]], i64 1
1685; CHECK-NEXT:    [[TMP44:%.*]] = ashr i32 [[TMP42]], 31
1686; CHECK-NEXT:    [[TMP45:%.*]] = ashr i32 [[TMP43]], 31
1687; CHECK-NEXT:    [[TMP46:%.*]] = xor i32 [[TMP44]], [[TMP45]]
1688; CHECK-NEXT:    [[TMP47:%.*]] = add i32 [[TMP42]], [[TMP44]]
1689; CHECK-NEXT:    [[TMP48:%.*]] = add i32 [[TMP43]], [[TMP45]]
1690; CHECK-NEXT:    [[TMP49:%.*]] = xor i32 [[TMP47]], [[TMP44]]
1691; CHECK-NEXT:    [[TMP50:%.*]] = xor i32 [[TMP48]], [[TMP45]]
1692; CHECK-NEXT:    [[TMP51:%.*]] = uitofp i32 [[TMP50]] to float
1693; CHECK-NEXT:    [[TMP52:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP51]])
1694; CHECK-NEXT:    [[TMP53:%.*]] = fmul fast float [[TMP52]], 0x41EFFFFFC0000000
1695; CHECK-NEXT:    [[TMP54:%.*]] = fptoui float [[TMP53]] to i32
1696; CHECK-NEXT:    [[TMP55:%.*]] = sub i32 0, [[TMP50]]
1697; CHECK-NEXT:    [[TMP56:%.*]] = mul i32 [[TMP55]], [[TMP54]]
1698; CHECK-NEXT:    [[TMP57:%.*]] = zext i32 [[TMP54]] to i64
1699; CHECK-NEXT:    [[TMP58:%.*]] = zext i32 [[TMP56]] to i64
1700; CHECK-NEXT:    [[TMP59:%.*]] = mul i64 [[TMP57]], [[TMP58]]
1701; CHECK-NEXT:    [[TMP60:%.*]] = trunc i64 [[TMP59]] to i32
1702; CHECK-NEXT:    [[TMP61:%.*]] = lshr i64 [[TMP59]], 32
1703; CHECK-NEXT:    [[TMP62:%.*]] = trunc i64 [[TMP61]] to i32
1704; CHECK-NEXT:    [[TMP63:%.*]] = add i32 [[TMP54]], [[TMP62]]
1705; CHECK-NEXT:    [[TMP64:%.*]] = zext i32 [[TMP49]] to i64
1706; CHECK-NEXT:    [[TMP65:%.*]] = zext i32 [[TMP63]] to i64
1707; CHECK-NEXT:    [[TMP66:%.*]] = mul i64 [[TMP64]], [[TMP65]]
1708; CHECK-NEXT:    [[TMP67:%.*]] = trunc i64 [[TMP66]] to i32
1709; CHECK-NEXT:    [[TMP68:%.*]] = lshr i64 [[TMP66]], 32
1710; CHECK-NEXT:    [[TMP69:%.*]] = trunc i64 [[TMP68]] to i32
1711; CHECK-NEXT:    [[TMP70:%.*]] = mul i32 [[TMP69]], [[TMP50]]
1712; CHECK-NEXT:    [[TMP71:%.*]] = sub i32 [[TMP49]], [[TMP70]]
1713; CHECK-NEXT:    [[TMP72:%.*]] = icmp uge i32 [[TMP71]], [[TMP50]]
1714; CHECK-NEXT:    [[TMP73:%.*]] = add i32 [[TMP69]], 1
1715; CHECK-NEXT:    [[TMP74:%.*]] = select i1 [[TMP72]], i32 [[TMP73]], i32 [[TMP69]]
1716; CHECK-NEXT:    [[TMP75:%.*]] = sub i32 [[TMP71]], [[TMP50]]
1717; CHECK-NEXT:    [[TMP76:%.*]] = select i1 [[TMP72]], i32 [[TMP75]], i32 [[TMP71]]
1718; CHECK-NEXT:    [[TMP77:%.*]] = icmp uge i32 [[TMP76]], [[TMP50]]
1719; CHECK-NEXT:    [[TMP78:%.*]] = add i32 [[TMP74]], 1
1720; CHECK-NEXT:    [[TMP79:%.*]] = select i1 [[TMP77]], i32 [[TMP78]], i32 [[TMP74]]
1721; CHECK-NEXT:    [[TMP80:%.*]] = xor i32 [[TMP79]], [[TMP46]]
1722; CHECK-NEXT:    [[TMP81:%.*]] = sub i32 [[TMP80]], [[TMP46]]
1723; CHECK-NEXT:    [[TMP82:%.*]] = insertelement <4 x i32> [[TMP41]], i32 [[TMP81]], i64 1
1724; CHECK-NEXT:    [[TMP83:%.*]] = extractelement <4 x i32> [[X]], i64 2
1725; CHECK-NEXT:    [[TMP84:%.*]] = extractelement <4 x i32> [[Y]], i64 2
1726; CHECK-NEXT:    [[TMP85:%.*]] = ashr i32 [[TMP83]], 31
1727; CHECK-NEXT:    [[TMP86:%.*]] = ashr i32 [[TMP84]], 31
1728; CHECK-NEXT:    [[TMP87:%.*]] = xor i32 [[TMP85]], [[TMP86]]
1729; CHECK-NEXT:    [[TMP88:%.*]] = add i32 [[TMP83]], [[TMP85]]
1730; CHECK-NEXT:    [[TMP89:%.*]] = add i32 [[TMP84]], [[TMP86]]
1731; CHECK-NEXT:    [[TMP90:%.*]] = xor i32 [[TMP88]], [[TMP85]]
1732; CHECK-NEXT:    [[TMP91:%.*]] = xor i32 [[TMP89]], [[TMP86]]
1733; CHECK-NEXT:    [[TMP92:%.*]] = uitofp i32 [[TMP91]] to float
1734; CHECK-NEXT:    [[TMP93:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP92]])
1735; CHECK-NEXT:    [[TMP94:%.*]] = fmul fast float [[TMP93]], 0x41EFFFFFC0000000
1736; CHECK-NEXT:    [[TMP95:%.*]] = fptoui float [[TMP94]] to i32
1737; CHECK-NEXT:    [[TMP96:%.*]] = sub i32 0, [[TMP91]]
1738; CHECK-NEXT:    [[TMP97:%.*]] = mul i32 [[TMP96]], [[TMP95]]
1739; CHECK-NEXT:    [[TMP98:%.*]] = zext i32 [[TMP95]] to i64
1740; CHECK-NEXT:    [[TMP99:%.*]] = zext i32 [[TMP97]] to i64
1741; CHECK-NEXT:    [[TMP100:%.*]] = mul i64 [[TMP98]], [[TMP99]]
1742; CHECK-NEXT:    [[TMP101:%.*]] = trunc i64 [[TMP100]] to i32
1743; CHECK-NEXT:    [[TMP102:%.*]] = lshr i64 [[TMP100]], 32
1744; CHECK-NEXT:    [[TMP103:%.*]] = trunc i64 [[TMP102]] to i32
1745; CHECK-NEXT:    [[TMP104:%.*]] = add i32 [[TMP95]], [[TMP103]]
1746; CHECK-NEXT:    [[TMP105:%.*]] = zext i32 [[TMP90]] to i64
1747; CHECK-NEXT:    [[TMP106:%.*]] = zext i32 [[TMP104]] to i64
1748; CHECK-NEXT:    [[TMP107:%.*]] = mul i64 [[TMP105]], [[TMP106]]
1749; CHECK-NEXT:    [[TMP108:%.*]] = trunc i64 [[TMP107]] to i32
1750; CHECK-NEXT:    [[TMP109:%.*]] = lshr i64 [[TMP107]], 32
1751; CHECK-NEXT:    [[TMP110:%.*]] = trunc i64 [[TMP109]] to i32
1752; CHECK-NEXT:    [[TMP111:%.*]] = mul i32 [[TMP110]], [[TMP91]]
1753; CHECK-NEXT:    [[TMP112:%.*]] = sub i32 [[TMP90]], [[TMP111]]
1754; CHECK-NEXT:    [[TMP113:%.*]] = icmp uge i32 [[TMP112]], [[TMP91]]
1755; CHECK-NEXT:    [[TMP114:%.*]] = add i32 [[TMP110]], 1
1756; CHECK-NEXT:    [[TMP115:%.*]] = select i1 [[TMP113]], i32 [[TMP114]], i32 [[TMP110]]
1757; CHECK-NEXT:    [[TMP116:%.*]] = sub i32 [[TMP112]], [[TMP91]]
1758; CHECK-NEXT:    [[TMP117:%.*]] = select i1 [[TMP113]], i32 [[TMP116]], i32 [[TMP112]]
1759; CHECK-NEXT:    [[TMP118:%.*]] = icmp uge i32 [[TMP117]], [[TMP91]]
1760; CHECK-NEXT:    [[TMP119:%.*]] = add i32 [[TMP115]], 1
1761; CHECK-NEXT:    [[TMP120:%.*]] = select i1 [[TMP118]], i32 [[TMP119]], i32 [[TMP115]]
1762; CHECK-NEXT:    [[TMP121:%.*]] = xor i32 [[TMP120]], [[TMP87]]
1763; CHECK-NEXT:    [[TMP122:%.*]] = sub i32 [[TMP121]], [[TMP87]]
1764; CHECK-NEXT:    [[TMP123:%.*]] = insertelement <4 x i32> [[TMP82]], i32 [[TMP122]], i64 2
1765; CHECK-NEXT:    [[TMP124:%.*]] = extractelement <4 x i32> [[X]], i64 3
1766; CHECK-NEXT:    [[TMP125:%.*]] = extractelement <4 x i32> [[Y]], i64 3
1767; CHECK-NEXT:    [[TMP126:%.*]] = ashr i32 [[TMP124]], 31
1768; CHECK-NEXT:    [[TMP127:%.*]] = ashr i32 [[TMP125]], 31
1769; CHECK-NEXT:    [[TMP128:%.*]] = xor i32 [[TMP126]], [[TMP127]]
1770; CHECK-NEXT:    [[TMP129:%.*]] = add i32 [[TMP124]], [[TMP126]]
1771; CHECK-NEXT:    [[TMP130:%.*]] = add i32 [[TMP125]], [[TMP127]]
1772; CHECK-NEXT:    [[TMP131:%.*]] = xor i32 [[TMP129]], [[TMP126]]
1773; CHECK-NEXT:    [[TMP132:%.*]] = xor i32 [[TMP130]], [[TMP127]]
1774; CHECK-NEXT:    [[TMP133:%.*]] = uitofp i32 [[TMP132]] to float
1775; CHECK-NEXT:    [[TMP134:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP133]])
1776; CHECK-NEXT:    [[TMP135:%.*]] = fmul fast float [[TMP134]], 0x41EFFFFFC0000000
1777; CHECK-NEXT:    [[TMP136:%.*]] = fptoui float [[TMP135]] to i32
1778; CHECK-NEXT:    [[TMP137:%.*]] = sub i32 0, [[TMP132]]
1779; CHECK-NEXT:    [[TMP138:%.*]] = mul i32 [[TMP137]], [[TMP136]]
1780; CHECK-NEXT:    [[TMP139:%.*]] = zext i32 [[TMP136]] to i64
1781; CHECK-NEXT:    [[TMP140:%.*]] = zext i32 [[TMP138]] to i64
1782; CHECK-NEXT:    [[TMP141:%.*]] = mul i64 [[TMP139]], [[TMP140]]
1783; CHECK-NEXT:    [[TMP142:%.*]] = trunc i64 [[TMP141]] to i32
1784; CHECK-NEXT:    [[TMP143:%.*]] = lshr i64 [[TMP141]], 32
1785; CHECK-NEXT:    [[TMP144:%.*]] = trunc i64 [[TMP143]] to i32
1786; CHECK-NEXT:    [[TMP145:%.*]] = add i32 [[TMP136]], [[TMP144]]
1787; CHECK-NEXT:    [[TMP146:%.*]] = zext i32 [[TMP131]] to i64
1788; CHECK-NEXT:    [[TMP147:%.*]] = zext i32 [[TMP145]] to i64
1789; CHECK-NEXT:    [[TMP148:%.*]] = mul i64 [[TMP146]], [[TMP147]]
1790; CHECK-NEXT:    [[TMP149:%.*]] = trunc i64 [[TMP148]] to i32
1791; CHECK-NEXT:    [[TMP150:%.*]] = lshr i64 [[TMP148]], 32
1792; CHECK-NEXT:    [[TMP151:%.*]] = trunc i64 [[TMP150]] to i32
1793; CHECK-NEXT:    [[TMP152:%.*]] = mul i32 [[TMP151]], [[TMP132]]
1794; CHECK-NEXT:    [[TMP153:%.*]] = sub i32 [[TMP131]], [[TMP152]]
1795; CHECK-NEXT:    [[TMP154:%.*]] = icmp uge i32 [[TMP153]], [[TMP132]]
1796; CHECK-NEXT:    [[TMP155:%.*]] = add i32 [[TMP151]], 1
1797; CHECK-NEXT:    [[TMP156:%.*]] = select i1 [[TMP154]], i32 [[TMP155]], i32 [[TMP151]]
1798; CHECK-NEXT:    [[TMP157:%.*]] = sub i32 [[TMP153]], [[TMP132]]
1799; CHECK-NEXT:    [[TMP158:%.*]] = select i1 [[TMP154]], i32 [[TMP157]], i32 [[TMP153]]
1800; CHECK-NEXT:    [[TMP159:%.*]] = icmp uge i32 [[TMP158]], [[TMP132]]
1801; CHECK-NEXT:    [[TMP160:%.*]] = add i32 [[TMP156]], 1
1802; CHECK-NEXT:    [[TMP161:%.*]] = select i1 [[TMP159]], i32 [[TMP160]], i32 [[TMP156]]
1803; CHECK-NEXT:    [[TMP162:%.*]] = xor i32 [[TMP161]], [[TMP128]]
1804; CHECK-NEXT:    [[TMP163:%.*]] = sub i32 [[TMP162]], [[TMP128]]
1805; CHECK-NEXT:    [[TMP164:%.*]] = insertelement <4 x i32> [[TMP123]], i32 [[TMP163]], i64 3
1806; CHECK-NEXT:    store <4 x i32> [[TMP164]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16
1807; CHECK-NEXT:    ret void
1808;
1809; GFX6-LABEL: sdiv_v4i32:
1810; GFX6:       ; %bb.0:
1811; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
1812; GFX6-NEXT:    s_mov_b32 s16, 0x4f7ffffe
1813; GFX6-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x9
1814; GFX6-NEXT:    s_mov_b32 s15, 0xf000
1815; GFX6-NEXT:    s_mov_b32 s14, -1
1816; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
1817; GFX6-NEXT:    s_ashr_i32 s2, s8, 31
1818; GFX6-NEXT:    s_add_i32 s3, s8, s2
1819; GFX6-NEXT:    s_xor_b32 s3, s3, s2
1820; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s3
1821; GFX6-NEXT:    s_ashr_i32 s8, s9, 31
1822; GFX6-NEXT:    s_add_i32 s0, s9, s8
1823; GFX6-NEXT:    s_xor_b32 s9, s0, s8
1824; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1825; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
1826; GFX6-NEXT:    s_sub_i32 s1, 0, s3
1827; GFX6-NEXT:    s_ashr_i32 s0, s4, 31
1828; GFX6-NEXT:    v_mul_f32_e32 v0, s16, v0
1829; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
1830; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1831; GFX6-NEXT:    s_xor_b32 s2, s0, s2
1832; GFX6-NEXT:    v_mul_lo_u32 v2, s1, v0
1833; GFX6-NEXT:    s_add_i32 s1, s4, s0
1834; GFX6-NEXT:    v_mul_f32_e32 v1, s16, v1
1835; GFX6-NEXT:    s_xor_b32 s1, s1, s0
1836; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
1837; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
1838; GFX6-NEXT:    s_sub_i32 s0, 0, s9
1839; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1840; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
1841; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v1
1842; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s3
1843; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v2
1844; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
1845; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s1, v3
1846; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v3
1847; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
1848; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s3, v3
1849; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[0:1]
1850; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
1851; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1852; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v3
1853; GFX6-NEXT:    s_ashr_i32 s0, s5, 31
1854; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
1855; GFX6-NEXT:    s_add_i32 s1, s5, s0
1856; GFX6-NEXT:    v_xor_b32_e32 v0, s2, v0
1857; GFX6-NEXT:    s_ashr_i32 s3, s10, 31
1858; GFX6-NEXT:    s_xor_b32 s1, s1, s0
1859; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
1860; GFX6-NEXT:    s_xor_b32 s2, s0, s8
1861; GFX6-NEXT:    s_add_i32 s0, s10, s3
1862; GFX6-NEXT:    s_xor_b32 s4, s0, s3
1863; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s4
1864; GFX6-NEXT:    v_mul_hi_u32 v1, s1, v1
1865; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1866; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s9
1867; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v1
1868; GFX6-NEXT:    v_mul_f32_e32 v3, s16, v3
1869; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
1870; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
1871; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v2
1872; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[0:1]
1873; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s9, v2
1874; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v4, s[0:1]
1875; GFX6-NEXT:    s_sub_i32 s0, 0, s4
1876; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v3
1877; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v1
1878; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
1879; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
1880; GFX6-NEXT:    v_mul_hi_u32 v2, v3, v5
1881; GFX6-NEXT:    v_xor_b32_e32 v1, s2, v1
1882; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s2, v1
1883; GFX6-NEXT:    s_ashr_i32 s2, s11, 31
1884; GFX6-NEXT:    s_ashr_i32 s0, s6, 31
1885; GFX6-NEXT:    s_add_i32 s5, s11, s2
1886; GFX6-NEXT:    s_add_i32 s1, s6, s0
1887; GFX6-NEXT:    s_xor_b32 s5, s5, s2
1888; GFX6-NEXT:    s_xor_b32 s1, s1, s0
1889; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
1890; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s5
1891; GFX6-NEXT:    v_mul_hi_u32 v2, s1, v2
1892; GFX6-NEXT:    s_xor_b32 s3, s0, s3
1893; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v4
1894; GFX6-NEXT:    v_mul_lo_u32 v3, v2, s4
1895; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v2
1896; GFX6-NEXT:    v_mul_f32_e32 v4, s16, v4
1897; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s1, v3
1898; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
1899; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s4, v3
1900; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v5, s[0:1]
1901; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s4, v3
1902; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
1903; GFX6-NEXT:    s_sub_i32 s0, 0, s5
1904; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v4
1905; GFX6-NEXT:    s_ashr_i32 s0, s7, 31
1906; GFX6-NEXT:    s_add_i32 s1, s7, s0
1907; GFX6-NEXT:    s_xor_b32 s1, s1, s0
1908; GFX6-NEXT:    v_mul_hi_u32 v5, v4, v5
1909; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
1910; GFX6-NEXT:    s_xor_b32 s2, s0, s2
1911; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1912; GFX6-NEXT:    v_mul_hi_u32 v4, s1, v4
1913; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s4, v3
1914; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
1915; GFX6-NEXT:    v_xor_b32_e32 v2, s3, v2
1916; GFX6-NEXT:    v_mul_lo_u32 v3, v4, s5
1917; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
1918; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v2
1919; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s1, v3
1920; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s5, v3
1921; GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]
1922; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s5, v3
1923; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
1924; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
1925; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s5, v3
1926; GFX6-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc
1927; GFX6-NEXT:    v_xor_b32_e32 v3, s2, v3
1928; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s2, v3
1929; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[12:15], 0
1930; GFX6-NEXT:    s_endpgm
1931;
1932; GFX9-LABEL: sdiv_v4i32:
1933; GFX9:       ; %bb.0:
1934; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
1935; GFX9-NEXT:    s_mov_b32 s15, 0x4f7ffffe
1936; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
1937; GFX9-NEXT:    v_mov_b32_e32 v4, 0
1938; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1939; GFX9-NEXT:    s_ashr_i32 s2, s8, 31
1940; GFX9-NEXT:    s_add_i32 s3, s8, s2
1941; GFX9-NEXT:    s_xor_b32 s3, s3, s2
1942; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
1943; GFX9-NEXT:    s_ashr_i32 s12, s9, 31
1944; GFX9-NEXT:    s_add_i32 s9, s9, s12
1945; GFX9-NEXT:    s_xor_b32 s9, s9, s12
1946; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1947; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
1948; GFX9-NEXT:    s_sub_i32 s14, 0, s3
1949; GFX9-NEXT:    s_ashr_i32 s8, s4, 31
1950; GFX9-NEXT:    v_mul_f32_e32 v0, s15, v0
1951; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
1952; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1953; GFX9-NEXT:    s_add_i32 s4, s4, s8
1954; GFX9-NEXT:    s_xor_b32 s4, s4, s8
1955; GFX9-NEXT:    v_mul_lo_u32 v2, s14, v0
1956; GFX9-NEXT:    v_mul_f32_e32 v1, s15, v1
1957; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
1958; GFX9-NEXT:    s_sub_i32 s14, 0, s9
1959; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
1960; GFX9-NEXT:    s_ashr_i32 s13, s5, 31
1961; GFX9-NEXT:    v_mul_lo_u32 v3, s14, v1
1962; GFX9-NEXT:    s_add_i32 s5, s5, s13
1963; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
1964; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
1965; GFX9-NEXT:    v_mul_hi_u32 v2, v1, v3
1966; GFX9-NEXT:    s_xor_b32 s5, s5, s13
1967; GFX9-NEXT:    s_xor_b32 s2, s8, s2
1968; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s3
1969; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
1970; GFX9-NEXT:    v_add_u32_e32 v2, 1, v0
1971; GFX9-NEXT:    v_mul_hi_u32 v1, s5, v1
1972; GFX9-NEXT:    v_sub_u32_e32 v3, s4, v3
1973; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v3
1974; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1975; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v3
1976; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
1977; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2
1978; GFX9-NEXT:    s_ashr_i32 s3, s10, 31
1979; GFX9-NEXT:    s_add_i32 s4, s10, s3
1980; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
1981; GFX9-NEXT:    s_xor_b32 s4, s4, s3
1982; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1983; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, s4
1984; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s9
1985; GFX9-NEXT:    v_add_u32_e32 v5, 1, v1
1986; GFX9-NEXT:    s_ashr_i32 s8, s11, 31
1987; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1988; GFX9-NEXT:    v_sub_u32_e32 v2, s5, v2
1989; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
1990; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
1991; GFX9-NEXT:    v_mul_f32_e32 v3, s15, v3
1992; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
1993; GFX9-NEXT:    v_subrev_u32_e32 v5, s9, v2
1994; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
1995; GFX9-NEXT:    s_sub_i32 s5, 0, s4
1996; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
1997; GFX9-NEXT:    v_mul_lo_u32 v2, s5, v3
1998; GFX9-NEXT:    s_add_i32 s9, s11, s8
1999; GFX9-NEXT:    v_add_u32_e32 v5, 1, v1
2000; GFX9-NEXT:    s_xor_b32 s9, s9, s8
2001; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
2002; GFX9-NEXT:    v_mul_hi_u32 v2, v3, v2
2003; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s9
2004; GFX9-NEXT:    s_ashr_i32 s5, s6, 31
2005; GFX9-NEXT:    s_add_i32 s6, s6, s5
2006; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
2007; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v5
2008; GFX9-NEXT:    s_xor_b32 s6, s6, s5
2009; GFX9-NEXT:    v_mul_hi_u32 v2, s6, v2
2010; GFX9-NEXT:    v_xor_b32_e32 v0, s2, v0
2011; GFX9-NEXT:    v_mul_f32_e32 v3, s15, v3
2012; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
2013; GFX9-NEXT:    v_subrev_u32_e32 v0, s2, v0
2014; GFX9-NEXT:    s_xor_b32 s2, s13, s12
2015; GFX9-NEXT:    v_mul_lo_u32 v5, v2, s4
2016; GFX9-NEXT:    v_xor_b32_e32 v1, s2, v1
2017; GFX9-NEXT:    v_subrev_u32_e32 v1, s2, v1
2018; GFX9-NEXT:    s_xor_b32 s2, s5, s3
2019; GFX9-NEXT:    s_sub_i32 s3, 0, s9
2020; GFX9-NEXT:    v_mul_lo_u32 v7, s3, v3
2021; GFX9-NEXT:    v_sub_u32_e32 v5, s6, v5
2022; GFX9-NEXT:    v_add_u32_e32 v6, 1, v2
2023; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v5
2024; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
2025; GFX9-NEXT:    v_subrev_u32_e32 v6, s4, v5
2026; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
2027; GFX9-NEXT:    v_mul_hi_u32 v6, v3, v7
2028; GFX9-NEXT:    s_ashr_i32 s3, s7, 31
2029; GFX9-NEXT:    s_add_i32 s5, s7, s3
2030; GFX9-NEXT:    s_xor_b32 s5, s5, s3
2031; GFX9-NEXT:    v_add_u32_e32 v3, v3, v6
2032; GFX9-NEXT:    v_mul_hi_u32 v3, s5, v3
2033; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v5
2034; GFX9-NEXT:    v_add_u32_e32 v6, 1, v2
2035; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
2036; GFX9-NEXT:    v_mul_lo_u32 v5, v3, s9
2037; GFX9-NEXT:    v_add_u32_e32 v6, 1, v3
2038; GFX9-NEXT:    v_xor_b32_e32 v2, s2, v2
2039; GFX9-NEXT:    v_subrev_u32_e32 v2, s2, v2
2040; GFX9-NEXT:    v_sub_u32_e32 v5, s5, v5
2041; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v5
2042; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
2043; GFX9-NEXT:    v_subrev_u32_e32 v6, s9, v5
2044; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
2045; GFX9-NEXT:    v_add_u32_e32 v6, 1, v3
2046; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v5
2047; GFX9-NEXT:    s_xor_b32 s2, s3, s8
2048; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
2049; GFX9-NEXT:    v_xor_b32_e32 v3, s2, v3
2050; GFX9-NEXT:    v_subrev_u32_e32 v3, s2, v3
2051; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
2052; GFX9-NEXT:    s_endpgm
2053  %r = sdiv <4 x i32> %x, %y
2054  store <4 x i32> %r, <4 x i32> addrspace(1)* %out
2055  ret void
2056}
2057
2058define amdgpu_kernel void @srem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
2059; CHECK-LABEL: @srem_v4i32(
2060; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i64 0
2061; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 0
2062; CHECK-NEXT:    [[TMP3:%.*]] = ashr i32 [[TMP1]], 31
2063; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP2]], 31
2064; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[TMP1]], [[TMP3]]
2065; CHECK-NEXT:    [[TMP6:%.*]] = add i32 [[TMP2]], [[TMP4]]
2066; CHECK-NEXT:    [[TMP7:%.*]] = xor i32 [[TMP5]], [[TMP3]]
2067; CHECK-NEXT:    [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP4]]
2068; CHECK-NEXT:    [[TMP9:%.*]] = uitofp i32 [[TMP8]] to float
2069; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
2070; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP10]], 0x41EFFFFFC0000000
2071; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP11]] to i32
2072; CHECK-NEXT:    [[TMP13:%.*]] = sub i32 0, [[TMP8]]
2073; CHECK-NEXT:    [[TMP14:%.*]] = mul i32 [[TMP13]], [[TMP12]]
2074; CHECK-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP12]] to i64
2075; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP14]] to i64
2076; CHECK-NEXT:    [[TMP17:%.*]] = mul i64 [[TMP15]], [[TMP16]]
2077; CHECK-NEXT:    [[TMP18:%.*]] = trunc i64 [[TMP17]] to i32
2078; CHECK-NEXT:    [[TMP19:%.*]] = lshr i64 [[TMP17]], 32
2079; CHECK-NEXT:    [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32
2080; CHECK-NEXT:    [[TMP21:%.*]] = add i32 [[TMP12]], [[TMP20]]
2081; CHECK-NEXT:    [[TMP22:%.*]] = zext i32 [[TMP7]] to i64
2082; CHECK-NEXT:    [[TMP23:%.*]] = zext i32 [[TMP21]] to i64
2083; CHECK-NEXT:    [[TMP24:%.*]] = mul i64 [[TMP22]], [[TMP23]]
2084; CHECK-NEXT:    [[TMP25:%.*]] = trunc i64 [[TMP24]] to i32
2085; CHECK-NEXT:    [[TMP26:%.*]] = lshr i64 [[TMP24]], 32
2086; CHECK-NEXT:    [[TMP27:%.*]] = trunc i64 [[TMP26]] to i32
2087; CHECK-NEXT:    [[TMP28:%.*]] = mul i32 [[TMP27]], [[TMP8]]
2088; CHECK-NEXT:    [[TMP29:%.*]] = sub i32 [[TMP7]], [[TMP28]]
2089; CHECK-NEXT:    [[TMP30:%.*]] = icmp uge i32 [[TMP29]], [[TMP8]]
2090; CHECK-NEXT:    [[TMP31:%.*]] = sub i32 [[TMP29]], [[TMP8]]
2091; CHECK-NEXT:    [[TMP32:%.*]] = select i1 [[TMP30]], i32 [[TMP31]], i32 [[TMP29]]
2092; CHECK-NEXT:    [[TMP33:%.*]] = icmp uge i32 [[TMP32]], [[TMP8]]
2093; CHECK-NEXT:    [[TMP34:%.*]] = sub i32 [[TMP32]], [[TMP8]]
2094; CHECK-NEXT:    [[TMP35:%.*]] = select i1 [[TMP33]], i32 [[TMP34]], i32 [[TMP32]]
2095; CHECK-NEXT:    [[TMP36:%.*]] = xor i32 [[TMP35]], [[TMP3]]
2096; CHECK-NEXT:    [[TMP37:%.*]] = sub i32 [[TMP36]], [[TMP3]]
2097; CHECK-NEXT:    [[TMP38:%.*]] = insertelement <4 x i32> undef, i32 [[TMP37]], i64 0
2098; CHECK-NEXT:    [[TMP39:%.*]] = extractelement <4 x i32> [[X]], i64 1
2099; CHECK-NEXT:    [[TMP40:%.*]] = extractelement <4 x i32> [[Y]], i64 1
2100; CHECK-NEXT:    [[TMP41:%.*]] = ashr i32 [[TMP39]], 31
2101; CHECK-NEXT:    [[TMP42:%.*]] = ashr i32 [[TMP40]], 31
2102; CHECK-NEXT:    [[TMP43:%.*]] = add i32 [[TMP39]], [[TMP41]]
2103; CHECK-NEXT:    [[TMP44:%.*]] = add i32 [[TMP40]], [[TMP42]]
2104; CHECK-NEXT:    [[TMP45:%.*]] = xor i32 [[TMP43]], [[TMP41]]
2105; CHECK-NEXT:    [[TMP46:%.*]] = xor i32 [[TMP44]], [[TMP42]]
2106; CHECK-NEXT:    [[TMP47:%.*]] = uitofp i32 [[TMP46]] to float
2107; CHECK-NEXT:    [[TMP48:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP47]])
2108; CHECK-NEXT:    [[TMP49:%.*]] = fmul fast float [[TMP48]], 0x41EFFFFFC0000000
2109; CHECK-NEXT:    [[TMP50:%.*]] = fptoui float [[TMP49]] to i32
2110; CHECK-NEXT:    [[TMP51:%.*]] = sub i32 0, [[TMP46]]
2111; CHECK-NEXT:    [[TMP52:%.*]] = mul i32 [[TMP51]], [[TMP50]]
2112; CHECK-NEXT:    [[TMP53:%.*]] = zext i32 [[TMP50]] to i64
2113; CHECK-NEXT:    [[TMP54:%.*]] = zext i32 [[TMP52]] to i64
2114; CHECK-NEXT:    [[TMP55:%.*]] = mul i64 [[TMP53]], [[TMP54]]
2115; CHECK-NEXT:    [[TMP56:%.*]] = trunc i64 [[TMP55]] to i32
2116; CHECK-NEXT:    [[TMP57:%.*]] = lshr i64 [[TMP55]], 32
2117; CHECK-NEXT:    [[TMP58:%.*]] = trunc i64 [[TMP57]] to i32
2118; CHECK-NEXT:    [[TMP59:%.*]] = add i32 [[TMP50]], [[TMP58]]
2119; CHECK-NEXT:    [[TMP60:%.*]] = zext i32 [[TMP45]] to i64
2120; CHECK-NEXT:    [[TMP61:%.*]] = zext i32 [[TMP59]] to i64
2121; CHECK-NEXT:    [[TMP62:%.*]] = mul i64 [[TMP60]], [[TMP61]]
2122; CHECK-NEXT:    [[TMP63:%.*]] = trunc i64 [[TMP62]] to i32
2123; CHECK-NEXT:    [[TMP64:%.*]] = lshr i64 [[TMP62]], 32
2124; CHECK-NEXT:    [[TMP65:%.*]] = trunc i64 [[TMP64]] to i32
2125; CHECK-NEXT:    [[TMP66:%.*]] = mul i32 [[TMP65]], [[TMP46]]
2126; CHECK-NEXT:    [[TMP67:%.*]] = sub i32 [[TMP45]], [[TMP66]]
2127; CHECK-NEXT:    [[TMP68:%.*]] = icmp uge i32 [[TMP67]], [[TMP46]]
2128; CHECK-NEXT:    [[TMP69:%.*]] = sub i32 [[TMP67]], [[TMP46]]
2129; CHECK-NEXT:    [[TMP70:%.*]] = select i1 [[TMP68]], i32 [[TMP69]], i32 [[TMP67]]
2130; CHECK-NEXT:    [[TMP71:%.*]] = icmp uge i32 [[TMP70]], [[TMP46]]
2131; CHECK-NEXT:    [[TMP72:%.*]] = sub i32 [[TMP70]], [[TMP46]]
2132; CHECK-NEXT:    [[TMP73:%.*]] = select i1 [[TMP71]], i32 [[TMP72]], i32 [[TMP70]]
2133; CHECK-NEXT:    [[TMP74:%.*]] = xor i32 [[TMP73]], [[TMP41]]
2134; CHECK-NEXT:    [[TMP75:%.*]] = sub i32 [[TMP74]], [[TMP41]]
2135; CHECK-NEXT:    [[TMP76:%.*]] = insertelement <4 x i32> [[TMP38]], i32 [[TMP75]], i64 1
2136; CHECK-NEXT:    [[TMP77:%.*]] = extractelement <4 x i32> [[X]], i64 2
2137; CHECK-NEXT:    [[TMP78:%.*]] = extractelement <4 x i32> [[Y]], i64 2
2138; CHECK-NEXT:    [[TMP79:%.*]] = ashr i32 [[TMP77]], 31
2139; CHECK-NEXT:    [[TMP80:%.*]] = ashr i32 [[TMP78]], 31
2140; CHECK-NEXT:    [[TMP81:%.*]] = add i32 [[TMP77]], [[TMP79]]
2141; CHECK-NEXT:    [[TMP82:%.*]] = add i32 [[TMP78]], [[TMP80]]
2142; CHECK-NEXT:    [[TMP83:%.*]] = xor i32 [[TMP81]], [[TMP79]]
2143; CHECK-NEXT:    [[TMP84:%.*]] = xor i32 [[TMP82]], [[TMP80]]
2144; CHECK-NEXT:    [[TMP85:%.*]] = uitofp i32 [[TMP84]] to float
2145; CHECK-NEXT:    [[TMP86:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP85]])
2146; CHECK-NEXT:    [[TMP87:%.*]] = fmul fast float [[TMP86]], 0x41EFFFFFC0000000
2147; CHECK-NEXT:    [[TMP88:%.*]] = fptoui float [[TMP87]] to i32
2148; CHECK-NEXT:    [[TMP89:%.*]] = sub i32 0, [[TMP84]]
2149; CHECK-NEXT:    [[TMP90:%.*]] = mul i32 [[TMP89]], [[TMP88]]
2150; CHECK-NEXT:    [[TMP91:%.*]] = zext i32 [[TMP88]] to i64
2151; CHECK-NEXT:    [[TMP92:%.*]] = zext i32 [[TMP90]] to i64
2152; CHECK-NEXT:    [[TMP93:%.*]] = mul i64 [[TMP91]], [[TMP92]]
2153; CHECK-NEXT:    [[TMP94:%.*]] = trunc i64 [[TMP93]] to i32
2154; CHECK-NEXT:    [[TMP95:%.*]] = lshr i64 [[TMP93]], 32
2155; CHECK-NEXT:    [[TMP96:%.*]] = trunc i64 [[TMP95]] to i32
2156; CHECK-NEXT:    [[TMP97:%.*]] = add i32 [[TMP88]], [[TMP96]]
2157; CHECK-NEXT:    [[TMP98:%.*]] = zext i32 [[TMP83]] to i64
2158; CHECK-NEXT:    [[TMP99:%.*]] = zext i32 [[TMP97]] to i64
2159; CHECK-NEXT:    [[TMP100:%.*]] = mul i64 [[TMP98]], [[TMP99]]
2160; CHECK-NEXT:    [[TMP101:%.*]] = trunc i64 [[TMP100]] to i32
2161; CHECK-NEXT:    [[TMP102:%.*]] = lshr i64 [[TMP100]], 32
2162; CHECK-NEXT:    [[TMP103:%.*]] = trunc i64 [[TMP102]] to i32
2163; CHECK-NEXT:    [[TMP104:%.*]] = mul i32 [[TMP103]], [[TMP84]]
2164; CHECK-NEXT:    [[TMP105:%.*]] = sub i32 [[TMP83]], [[TMP104]]
2165; CHECK-NEXT:    [[TMP106:%.*]] = icmp uge i32 [[TMP105]], [[TMP84]]
2166; CHECK-NEXT:    [[TMP107:%.*]] = sub i32 [[TMP105]], [[TMP84]]
2167; CHECK-NEXT:    [[TMP108:%.*]] = select i1 [[TMP106]], i32 [[TMP107]], i32 [[TMP105]]
2168; CHECK-NEXT:    [[TMP109:%.*]] = icmp uge i32 [[TMP108]], [[TMP84]]
2169; CHECK-NEXT:    [[TMP110:%.*]] = sub i32 [[TMP108]], [[TMP84]]
2170; CHECK-NEXT:    [[TMP111:%.*]] = select i1 [[TMP109]], i32 [[TMP110]], i32 [[TMP108]]
2171; CHECK-NEXT:    [[TMP112:%.*]] = xor i32 [[TMP111]], [[TMP79]]
2172; CHECK-NEXT:    [[TMP113:%.*]] = sub i32 [[TMP112]], [[TMP79]]
2173; CHECK-NEXT:    [[TMP114:%.*]] = insertelement <4 x i32> [[TMP76]], i32 [[TMP113]], i64 2
2174; CHECK-NEXT:    [[TMP115:%.*]] = extractelement <4 x i32> [[X]], i64 3
2175; CHECK-NEXT:    [[TMP116:%.*]] = extractelement <4 x i32> [[Y]], i64 3
2176; CHECK-NEXT:    [[TMP117:%.*]] = ashr i32 [[TMP115]], 31
2177; CHECK-NEXT:    [[TMP118:%.*]] = ashr i32 [[TMP116]], 31
2178; CHECK-NEXT:    [[TMP119:%.*]] = add i32 [[TMP115]], [[TMP117]]
2179; CHECK-NEXT:    [[TMP120:%.*]] = add i32 [[TMP116]], [[TMP118]]
2180; CHECK-NEXT:    [[TMP121:%.*]] = xor i32 [[TMP119]], [[TMP117]]
2181; CHECK-NEXT:    [[TMP122:%.*]] = xor i32 [[TMP120]], [[TMP118]]
2182; CHECK-NEXT:    [[TMP123:%.*]] = uitofp i32 [[TMP122]] to float
2183; CHECK-NEXT:    [[TMP124:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP123]])
2184; CHECK-NEXT:    [[TMP125:%.*]] = fmul fast float [[TMP124]], 0x41EFFFFFC0000000
2185; CHECK-NEXT:    [[TMP126:%.*]] = fptoui float [[TMP125]] to i32
2186; CHECK-NEXT:    [[TMP127:%.*]] = sub i32 0, [[TMP122]]
2187; CHECK-NEXT:    [[TMP128:%.*]] = mul i32 [[TMP127]], [[TMP126]]
2188; CHECK-NEXT:    [[TMP129:%.*]] = zext i32 [[TMP126]] to i64
2189; CHECK-NEXT:    [[TMP130:%.*]] = zext i32 [[TMP128]] to i64
2190; CHECK-NEXT:    [[TMP131:%.*]] = mul i64 [[TMP129]], [[TMP130]]
2191; CHECK-NEXT:    [[TMP132:%.*]] = trunc i64 [[TMP131]] to i32
2192; CHECK-NEXT:    [[TMP133:%.*]] = lshr i64 [[TMP131]], 32
2193; CHECK-NEXT:    [[TMP134:%.*]] = trunc i64 [[TMP133]] to i32
2194; CHECK-NEXT:    [[TMP135:%.*]] = add i32 [[TMP126]], [[TMP134]]
2195; CHECK-NEXT:    [[TMP136:%.*]] = zext i32 [[TMP121]] to i64
2196; CHECK-NEXT:    [[TMP137:%.*]] = zext i32 [[TMP135]] to i64
2197; CHECK-NEXT:    [[TMP138:%.*]] = mul i64 [[TMP136]], [[TMP137]]
2198; CHECK-NEXT:    [[TMP139:%.*]] = trunc i64 [[TMP138]] to i32
2199; CHECK-NEXT:    [[TMP140:%.*]] = lshr i64 [[TMP138]], 32
2200; CHECK-NEXT:    [[TMP141:%.*]] = trunc i64 [[TMP140]] to i32
2201; CHECK-NEXT:    [[TMP142:%.*]] = mul i32 [[TMP141]], [[TMP122]]
2202; CHECK-NEXT:    [[TMP143:%.*]] = sub i32 [[TMP121]], [[TMP142]]
2203; CHECK-NEXT:    [[TMP144:%.*]] = icmp uge i32 [[TMP143]], [[TMP122]]
2204; CHECK-NEXT:    [[TMP145:%.*]] = sub i32 [[TMP143]], [[TMP122]]
2205; CHECK-NEXT:    [[TMP146:%.*]] = select i1 [[TMP144]], i32 [[TMP145]], i32 [[TMP143]]
2206; CHECK-NEXT:    [[TMP147:%.*]] = icmp uge i32 [[TMP146]], [[TMP122]]
2207; CHECK-NEXT:    [[TMP148:%.*]] = sub i32 [[TMP146]], [[TMP122]]
2208; CHECK-NEXT:    [[TMP149:%.*]] = select i1 [[TMP147]], i32 [[TMP148]], i32 [[TMP146]]
2209; CHECK-NEXT:    [[TMP150:%.*]] = xor i32 [[TMP149]], [[TMP117]]
2210; CHECK-NEXT:    [[TMP151:%.*]] = sub i32 [[TMP150]], [[TMP117]]
2211; CHECK-NEXT:    [[TMP152:%.*]] = insertelement <4 x i32> [[TMP114]], i32 [[TMP151]], i64 3
2212; CHECK-NEXT:    store <4 x i32> [[TMP152]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16
2213; CHECK-NEXT:    ret void
2214;
2215; GFX6-LABEL: srem_v4i32:
2216; GFX6:       ; %bb.0:
2217; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
2218; GFX6-NEXT:    s_mov_b32 s14, 0x4f7ffffe
2219; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
2220; GFX6-NEXT:    s_mov_b32 s3, 0xf000
2221; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
2222; GFX6-NEXT:    s_ashr_i32 s2, s8, 31
2223; GFX6-NEXT:    s_add_i32 s8, s8, s2
2224; GFX6-NEXT:    s_xor_b32 s8, s8, s2
2225; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
2226; GFX6-NEXT:    s_ashr_i32 s12, s9, 31
2227; GFX6-NEXT:    s_add_i32 s9, s9, s12
2228; GFX6-NEXT:    s_xor_b32 s9, s9, s12
2229; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
2230; GFX6-NEXT:    s_sub_i32 s13, 0, s8
2231; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
2232; GFX6-NEXT:    s_ashr_i32 s12, s4, 31
2233; GFX6-NEXT:    v_mul_f32_e32 v0, s14, v0
2234; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
2235; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
2236; GFX6-NEXT:    s_add_i32 s4, s4, s12
2237; GFX6-NEXT:    s_xor_b32 s4, s4, s12
2238; GFX6-NEXT:    v_mul_lo_u32 v2, s13, v0
2239; GFX6-NEXT:    v_mul_f32_e32 v1, s14, v1
2240; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
2241; GFX6-NEXT:    s_sub_i32 s13, 0, s9
2242; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
2243; GFX6-NEXT:    s_mov_b32 s2, -1
2244; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2245; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
2246; GFX6-NEXT:    v_mul_lo_u32 v2, s13, v1
2247; GFX6-NEXT:    s_ashr_i32 s13, s5, 31
2248; GFX6-NEXT:    s_add_i32 s5, s5, s13
2249; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s8
2250; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v2
2251; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
2252; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v0
2253; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
2254; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
2255; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v0
2256; GFX6-NEXT:    s_xor_b32 s4, s5, s13
2257; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2258; GFX6-NEXT:    s_ashr_i32 s5, s10, 31
2259; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
2260; GFX6-NEXT:    s_add_i32 s8, s10, s5
2261; GFX6-NEXT:    s_xor_b32 s5, s8, s5
2262; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s5
2263; GFX6-NEXT:    v_mul_hi_u32 v1, s4, v1
2264; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
2265; GFX6-NEXT:    v_xor_b32_e32 v0, s12, v0
2266; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
2267; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s9
2268; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s12, v0
2269; GFX6-NEXT:    v_mul_f32_e32 v2, s14, v2
2270; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
2271; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s4, v1
2272; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s9, v1
2273; GFX6-NEXT:    s_sub_i32 s4, 0, s5
2274; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
2275; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v2
2276; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
2277; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s9, v1
2278; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
2279; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
2280; GFX6-NEXT:    v_mul_hi_u32 v3, v2, v4
2281; GFX6-NEXT:    s_ashr_i32 s8, s11, 31
2282; GFX6-NEXT:    s_add_i32 s9, s11, s8
2283; GFX6-NEXT:    s_ashr_i32 s4, s6, 31
2284; GFX6-NEXT:    s_xor_b32 s8, s9, s8
2285; GFX6-NEXT:    s_add_i32 s6, s6, s4
2286; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
2287; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s8
2288; GFX6-NEXT:    s_xor_b32 s6, s6, s4
2289; GFX6-NEXT:    v_mul_hi_u32 v2, s6, v2
2290; GFX6-NEXT:    v_xor_b32_e32 v1, s13, v1
2291; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
2292; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s13, v1
2293; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s5
2294; GFX6-NEXT:    v_mul_f32_e32 v3, s14, v3
2295; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
2296; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s6, v2
2297; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s5, v2
2298; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s5, v2
2299; GFX6-NEXT:    s_sub_i32 s6, 0, s8
2300; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2301; GFX6-NEXT:    v_mul_lo_u32 v4, s6, v3
2302; GFX6-NEXT:    s_ashr_i32 s6, s7, 31
2303; GFX6-NEXT:    s_add_i32 s7, s7, s6
2304; GFX6-NEXT:    s_xor_b32 s7, s7, s6
2305; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v4
2306; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s5, v2
2307; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
2308; GFX6-NEXT:    v_mul_hi_u32 v3, s7, v3
2309; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s5, v2
2310; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
2311; GFX6-NEXT:    v_xor_b32_e32 v2, s4, v2
2312; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s8
2313; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s4, v2
2314; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s7, v3
2315; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s8, v3
2316; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
2317; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
2318; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s8, v3
2319; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
2320; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
2321; GFX6-NEXT:    v_xor_b32_e32 v3, s6, v3
2322; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s6, v3
2323; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
2324; GFX6-NEXT:    s_endpgm
2325;
2326; GFX9-LABEL: srem_v4i32:
2327; GFX9:       ; %bb.0:
2328; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
2329; GFX9-NEXT:    s_mov_b32 s13, 0x4f7ffffe
2330; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
2331; GFX9-NEXT:    v_mov_b32_e32 v4, 0
2332; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
2333; GFX9-NEXT:    s_ashr_i32 s2, s8, 31
2334; GFX9-NEXT:    s_add_i32 s8, s8, s2
2335; GFX9-NEXT:    s_xor_b32 s2, s8, s2
2336; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s2
2337; GFX9-NEXT:    s_ashr_i32 s3, s9, 31
2338; GFX9-NEXT:    s_sub_i32 s12, 0, s2
2339; GFX9-NEXT:    s_add_i32 s8, s9, s3
2340; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
2341; GFX9-NEXT:    s_xor_b32 s3, s8, s3
2342; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s3
2343; GFX9-NEXT:    s_ashr_i32 s8, s4, 31
2344; GFX9-NEXT:    v_mul_f32_e32 v0, s13, v0
2345; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
2346; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
2347; GFX9-NEXT:    s_add_i32 s4, s4, s8
2348; GFX9-NEXT:    s_xor_b32 s4, s4, s8
2349; GFX9-NEXT:    v_mul_lo_u32 v2, s12, v0
2350; GFX9-NEXT:    v_mul_f32_e32 v1, s13, v1
2351; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
2352; GFX9-NEXT:    s_sub_i32 s12, 0, s3
2353; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
2354; GFX9-NEXT:    s_ashr_i32 s9, s5, 31
2355; GFX9-NEXT:    v_mul_lo_u32 v3, s12, v1
2356; GFX9-NEXT:    s_add_i32 s5, s5, s9
2357; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
2358; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
2359; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
2360; GFX9-NEXT:    s_xor_b32 s5, s5, s9
2361; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s2
2362; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
2363; GFX9-NEXT:    v_mul_hi_u32 v1, s5, v1
2364; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
2365; GFX9-NEXT:    v_subrev_u32_e32 v2, s2, v0
2366; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v0
2367; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
2368; GFX9-NEXT:    v_subrev_u32_e32 v2, s2, v0
2369; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v0
2370; GFX9-NEXT:    s_ashr_i32 s2, s10, 31
2371; GFX9-NEXT:    s_add_i32 s4, s10, s2
2372; GFX9-NEXT:    s_xor_b32 s2, s4, s2
2373; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
2374; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, s2
2375; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s3
2376; GFX9-NEXT:    v_xor_b32_e32 v0, s8, v0
2377; GFX9-NEXT:    v_subrev_u32_e32 v0, s8, v0
2378; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v2
2379; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v1
2380; GFX9-NEXT:    v_subrev_u32_e32 v3, s3, v1
2381; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
2382; GFX9-NEXT:    v_mul_f32_e32 v2, s13, v2
2383; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
2384; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
2385; GFX9-NEXT:    v_subrev_u32_e32 v3, s3, v1
2386; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
2387; GFX9-NEXT:    s_sub_i32 s3, 0, s2
2388; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
2389; GFX9-NEXT:    v_mul_lo_u32 v3, s3, v2
2390; GFX9-NEXT:    s_ashr_i32 s3, s11, 31
2391; GFX9-NEXT:    s_add_i32 s4, s11, s3
2392; GFX9-NEXT:    s_xor_b32 s3, s4, s3
2393; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s3
2394; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v3
2395; GFX9-NEXT:    s_ashr_i32 s4, s6, 31
2396; GFX9-NEXT:    s_add_i32 s5, s6, s4
2397; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v5
2398; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
2399; GFX9-NEXT:    s_xor_b32 s5, s5, s4
2400; GFX9-NEXT:    v_mul_hi_u32 v2, s5, v2
2401; GFX9-NEXT:    v_mul_f32_e32 v3, s13, v5
2402; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
2403; GFX9-NEXT:    s_sub_i32 s6, 0, s3
2404; GFX9-NEXT:    v_mul_lo_u32 v2, v2, s2
2405; GFX9-NEXT:    v_xor_b32_e32 v1, s9, v1
2406; GFX9-NEXT:    v_mul_lo_u32 v5, s6, v3
2407; GFX9-NEXT:    v_subrev_u32_e32 v1, s9, v1
2408; GFX9-NEXT:    v_sub_u32_e32 v2, s5, v2
2409; GFX9-NEXT:    s_ashr_i32 s5, s7, 31
2410; GFX9-NEXT:    v_mul_hi_u32 v5, v3, v5
2411; GFX9-NEXT:    s_add_i32 s6, s7, s5
2412; GFX9-NEXT:    s_xor_b32 s6, s6, s5
2413; GFX9-NEXT:    v_subrev_u32_e32 v6, s2, v2
2414; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
2415; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v3
2416; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v2
2417; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
2418; GFX9-NEXT:    v_subrev_u32_e32 v5, s2, v2
2419; GFX9-NEXT:    v_mul_lo_u32 v3, v3, s3
2420; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v2
2421; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
2422; GFX9-NEXT:    v_xor_b32_e32 v2, s4, v2
2423; GFX9-NEXT:    v_sub_u32_e32 v3, s6, v3
2424; GFX9-NEXT:    v_subrev_u32_e32 v5, s3, v3
2425; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v3
2426; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
2427; GFX9-NEXT:    v_subrev_u32_e32 v5, s3, v3
2428; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v3
2429; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
2430; GFX9-NEXT:    v_xor_b32_e32 v3, s5, v3
2431; GFX9-NEXT:    v_subrev_u32_e32 v2, s4, v2
2432; GFX9-NEXT:    v_subrev_u32_e32 v3, s5, v3
2433; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
2434; GFX9-NEXT:    s_endpgm
2435  %r = srem <4 x i32> %x, %y
2436  store <4 x i32> %r, <4 x i32> addrspace(1)* %out
2437  ret void
2438}
2439
2440define amdgpu_kernel void @udiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x, <4 x i16> %y) {
2441; CHECK-LABEL: @udiv_v4i16(
2442; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i16> [[X:%.*]], i64 0
2443; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i16> [[Y:%.*]], i64 0
2444; CHECK-NEXT:    [[TMP3:%.*]] = zext i16 [[TMP1]] to i32
2445; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[TMP2]] to i32
2446; CHECK-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float
2447; CHECK-NEXT:    [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float
2448; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])
2449; CHECK-NEXT:    [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]
2450; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])
2451; CHECK-NEXT:    [[TMP10:%.*]] = fneg fast float [[TMP9]]
2452; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])
2453; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP9]] to i32
2454; CHECK-NEXT:    [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])
2455; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])
2456; CHECK-NEXT:    [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]
2457; CHECK-NEXT:    [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 0
2458; CHECK-NEXT:    [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]
2459; CHECK-NEXT:    [[TMP18:%.*]] = and i32 [[TMP17]], 65535
2460; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i16
2461; CHECK-NEXT:    [[TMP20:%.*]] = insertelement <4 x i16> undef, i16 [[TMP19]], i64 0
2462; CHECK-NEXT:    [[TMP21:%.*]] = extractelement <4 x i16> [[X]], i64 1
2463; CHECK-NEXT:    [[TMP22:%.*]] = extractelement <4 x i16> [[Y]], i64 1
2464; CHECK-NEXT:    [[TMP23:%.*]] = zext i16 [[TMP21]] to i32
2465; CHECK-NEXT:    [[TMP24:%.*]] = zext i16 [[TMP22]] to i32
2466; CHECK-NEXT:    [[TMP25:%.*]] = uitofp i32 [[TMP23]] to float
2467; CHECK-NEXT:    [[TMP26:%.*]] = uitofp i32 [[TMP24]] to float
2468; CHECK-NEXT:    [[TMP27:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP26]])
2469; CHECK-NEXT:    [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]]
2470; CHECK-NEXT:    [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]])
2471; CHECK-NEXT:    [[TMP30:%.*]] = fneg fast float [[TMP29]]
2472; CHECK-NEXT:    [[TMP31:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP30]], float [[TMP26]], float [[TMP25]])
2473; CHECK-NEXT:    [[TMP32:%.*]] = fptoui float [[TMP29]] to i32
2474; CHECK-NEXT:    [[TMP33:%.*]] = call fast float @llvm.fabs.f32(float [[TMP31]])
2475; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.fabs.f32(float [[TMP26]])
2476; CHECK-NEXT:    [[TMP35:%.*]] = fcmp fast oge float [[TMP33]], [[TMP34]]
2477; CHECK-NEXT:    [[TMP36:%.*]] = select i1 [[TMP35]], i32 1, i32 0
2478; CHECK-NEXT:    [[TMP37:%.*]] = add i32 [[TMP32]], [[TMP36]]
2479; CHECK-NEXT:    [[TMP38:%.*]] = and i32 [[TMP37]], 65535
2480; CHECK-NEXT:    [[TMP39:%.*]] = trunc i32 [[TMP38]] to i16
2481; CHECK-NEXT:    [[TMP40:%.*]] = insertelement <4 x i16> [[TMP20]], i16 [[TMP39]], i64 1
2482; CHECK-NEXT:    [[TMP41:%.*]] = extractelement <4 x i16> [[X]], i64 2
2483; CHECK-NEXT:    [[TMP42:%.*]] = extractelement <4 x i16> [[Y]], i64 2
2484; CHECK-NEXT:    [[TMP43:%.*]] = zext i16 [[TMP41]] to i32
2485; CHECK-NEXT:    [[TMP44:%.*]] = zext i16 [[TMP42]] to i32
2486; CHECK-NEXT:    [[TMP45:%.*]] = uitofp i32 [[TMP43]] to float
2487; CHECK-NEXT:    [[TMP46:%.*]] = uitofp i32 [[TMP44]] to float
2488; CHECK-NEXT:    [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]])
2489; CHECK-NEXT:    [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]]
2490; CHECK-NEXT:    [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]])
2491; CHECK-NEXT:    [[TMP50:%.*]] = fneg fast float [[TMP49]]
2492; CHECK-NEXT:    [[TMP51:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP50]], float [[TMP46]], float [[TMP45]])
2493; CHECK-NEXT:    [[TMP52:%.*]] = fptoui float [[TMP49]] to i32
2494; CHECK-NEXT:    [[TMP53:%.*]] = call fast float @llvm.fabs.f32(float [[TMP51]])
2495; CHECK-NEXT:    [[TMP54:%.*]] = call fast float @llvm.fabs.f32(float [[TMP46]])
2496; CHECK-NEXT:    [[TMP55:%.*]] = fcmp fast oge float [[TMP53]], [[TMP54]]
2497; CHECK-NEXT:    [[TMP56:%.*]] = select i1 [[TMP55]], i32 1, i32 0
2498; CHECK-NEXT:    [[TMP57:%.*]] = add i32 [[TMP52]], [[TMP56]]
2499; CHECK-NEXT:    [[TMP58:%.*]] = and i32 [[TMP57]], 65535
2500; CHECK-NEXT:    [[TMP59:%.*]] = trunc i32 [[TMP58]] to i16
2501; CHECK-NEXT:    [[TMP60:%.*]] = insertelement <4 x i16> [[TMP40]], i16 [[TMP59]], i64 2
2502; CHECK-NEXT:    [[TMP61:%.*]] = extractelement <4 x i16> [[X]], i64 3
2503; CHECK-NEXT:    [[TMP62:%.*]] = extractelement <4 x i16> [[Y]], i64 3
2504; CHECK-NEXT:    [[TMP63:%.*]] = zext i16 [[TMP61]] to i32
2505; CHECK-NEXT:    [[TMP64:%.*]] = zext i16 [[TMP62]] to i32
2506; CHECK-NEXT:    [[TMP65:%.*]] = uitofp i32 [[TMP63]] to float
2507; CHECK-NEXT:    [[TMP66:%.*]] = uitofp i32 [[TMP64]] to float
2508; CHECK-NEXT:    [[TMP67:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP66]])
2509; CHECK-NEXT:    [[TMP68:%.*]] = fmul fast float [[TMP65]], [[TMP67]]
2510; CHECK-NEXT:    [[TMP69:%.*]] = call fast float @llvm.trunc.f32(float [[TMP68]])
2511; CHECK-NEXT:    [[TMP70:%.*]] = fneg fast float [[TMP69]]
2512; CHECK-NEXT:    [[TMP71:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP70]], float [[TMP66]], float [[TMP65]])
2513; CHECK-NEXT:    [[TMP72:%.*]] = fptoui float [[TMP69]] to i32
2514; CHECK-NEXT:    [[TMP73:%.*]] = call fast float @llvm.fabs.f32(float [[TMP71]])
2515; CHECK-NEXT:    [[TMP74:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]])
2516; CHECK-NEXT:    [[TMP75:%.*]] = fcmp fast oge float [[TMP73]], [[TMP74]]
2517; CHECK-NEXT:    [[TMP76:%.*]] = select i1 [[TMP75]], i32 1, i32 0
2518; CHECK-NEXT:    [[TMP77:%.*]] = add i32 [[TMP72]], [[TMP76]]
2519; CHECK-NEXT:    [[TMP78:%.*]] = and i32 [[TMP77]], 65535
2520; CHECK-NEXT:    [[TMP79:%.*]] = trunc i32 [[TMP78]] to i16
2521; CHECK-NEXT:    [[TMP80:%.*]] = insertelement <4 x i16> [[TMP60]], i16 [[TMP79]], i64 3
2522; CHECK-NEXT:    store <4 x i16> [[TMP80]], <4 x i16> addrspace(1)* [[OUT:%.*]], align 8
2523; CHECK-NEXT:    ret void
2524;
2525; GFX6-LABEL: udiv_v4i16:
2526; GFX6:       ; %bb.0:
2527; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
2528; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
2529; GFX6-NEXT:    s_mov_b32 s8, 0xffff
2530; GFX6-NEXT:    s_mov_b32 s3, 0xf000
2531; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
2532; GFX6-NEXT:    s_and_b32 s2, s6, s8
2533; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s2
2534; GFX6-NEXT:    s_and_b32 s9, s4, s8
2535; GFX6-NEXT:    s_lshr_b32 s6, s6, 16
2536; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
2537; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
2538; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s6
2539; GFX6-NEXT:    s_lshr_b32 s4, s4, 16
2540; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s4
2541; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
2542; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
2543; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
2544; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
2545; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
2546; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
2547; GFX6-NEXT:    v_mul_f32_e32 v1, v4, v5
2548; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
2549; GFX6-NEXT:    s_and_b32 s4, s7, s8
2550; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
2551; GFX6-NEXT:    v_mad_f32 v2, -v1, v3, v4
2552; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s4
2553; GFX6-NEXT:    s_and_b32 s4, s5, s8
2554; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
2555; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s4
2556; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v4
2557; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
2558; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v1, vcc
2559; GFX6-NEXT:    v_mul_f32_e32 v1, v5, v6
2560; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
2561; GFX6-NEXT:    s_lshr_b32 s4, s7, 16
2562; GFX6-NEXT:    v_mad_f32 v3, -v1, v4, v5
2563; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s4
2564; GFX6-NEXT:    s_lshr_b32 s4, s5, 16
2565; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s4
2566; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
2567; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v5
2568; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v4
2569; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
2570; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
2571; GFX6-NEXT:    v_mul_f32_e32 v3, v6, v7
2572; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
2573; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v3
2574; GFX6-NEXT:    v_mad_f32 v3, -v3, v5, v6
2575; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v5
2576; GFX6-NEXT:    v_and_b32_e32 v1, s8, v1
2577; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
2578; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
2579; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
2580; GFX6-NEXT:    s_mov_b32 s2, -1
2581; GFX6-NEXT:    v_or_b32_e32 v1, v1, v3
2582; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
2583; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2584; GFX6-NEXT:    s_endpgm
2585;
2586; GFX9-LABEL: udiv_v4i16:
2587; GFX9:       ; %bb.0:
2588; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
2589; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
2590; GFX9-NEXT:    s_mov_b32 s0, 0xffff
2591; GFX9-NEXT:    v_mov_b32_e32 v2, 0
2592; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
2593; GFX9-NEXT:    s_and_b32 s8, s6, s0
2594; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
2595; GFX9-NEXT:    s_lshr_b32 s6, s6, 16
2596; GFX9-NEXT:    s_and_b32 s1, s4, s0
2597; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, s6
2598; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s1
2599; GFX9-NEXT:    v_rcp_iflag_f32_e32 v4, v0
2600; GFX9-NEXT:    s_lshr_b32 s1, s4, 16
2601; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s1
2602; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v3
2603; GFX9-NEXT:    v_mul_f32_e32 v4, v1, v4
2604; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
2605; GFX9-NEXT:    v_mad_f32 v1, -v4, v0, v1
2606; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
2607; GFX9-NEXT:    v_mul_f32_e32 v1, v5, v6
2608; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
2609; GFX9-NEXT:    s_and_b32 s1, s7, s0
2610; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v4
2611; GFX9-NEXT:    v_mad_f32 v4, -v1, v3, v5
2612; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s1
2613; GFX9-NEXT:    s_and_b32 s0, s5, s0
2614; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v7, vcc
2615; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
2616; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
2617; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v5
2618; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v3
2619; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
2620; GFX9-NEXT:    v_mul_f32_e32 v1, v6, v7
2621; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
2622; GFX9-NEXT:    s_lshr_b32 s0, s7, 16
2623; GFX9-NEXT:    v_mad_f32 v4, -v1, v5, v6
2624; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
2625; GFX9-NEXT:    s_lshr_b32 s0, s5, 16
2626; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s0
2627; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
2628; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v6
2629; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v5
2630; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
2631; GFX9-NEXT:    v_mul_f32_e32 v4, v7, v8
2632; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
2633; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v4
2634; GFX9-NEXT:    v_mad_f32 v4, -v4, v6, v7
2635; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v6
2636; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
2637; GFX9-NEXT:    v_mov_b32_e32 v5, 0xffff
2638; GFX9-NEXT:    v_and_b32_e32 v1, v5, v1
2639; GFX9-NEXT:    v_and_b32_e32 v0, v5, v0
2640; GFX9-NEXT:    v_lshl_or_b32 v1, v4, 16, v1
2641; GFX9-NEXT:    v_lshl_or_b32 v0, v3, 16, v0
2642; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
2643; GFX9-NEXT:    s_endpgm
2644  %r = udiv <4 x i16> %x, %y
2645  store <4 x i16> %r, <4 x i16> addrspace(1)* %out
2646  ret void
2647}
2648
2649define amdgpu_kernel void @urem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x, <4 x i16> %y) {
2650; CHECK-LABEL: @urem_v4i16(
2651; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i16> [[X:%.*]], i64 0
2652; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i16> [[Y:%.*]], i64 0
2653; CHECK-NEXT:    [[TMP3:%.*]] = zext i16 [[TMP1]] to i32
2654; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[TMP2]] to i32
2655; CHECK-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float
2656; CHECK-NEXT:    [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float
2657; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])
2658; CHECK-NEXT:    [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]
2659; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])
2660; CHECK-NEXT:    [[TMP10:%.*]] = fneg fast float [[TMP9]]
2661; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])
2662; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP9]] to i32
2663; CHECK-NEXT:    [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])
2664; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])
2665; CHECK-NEXT:    [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]
2666; CHECK-NEXT:    [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 0
2667; CHECK-NEXT:    [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]
2668; CHECK-NEXT:    [[TMP18:%.*]] = mul i32 [[TMP17]], [[TMP4]]
2669; CHECK-NEXT:    [[TMP19:%.*]] = sub i32 [[TMP3]], [[TMP18]]
2670; CHECK-NEXT:    [[TMP20:%.*]] = and i32 [[TMP19]], 65535
2671; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i16
2672; CHECK-NEXT:    [[TMP22:%.*]] = insertelement <4 x i16> undef, i16 [[TMP21]], i64 0
2673; CHECK-NEXT:    [[TMP23:%.*]] = extractelement <4 x i16> [[X]], i64 1
2674; CHECK-NEXT:    [[TMP24:%.*]] = extractelement <4 x i16> [[Y]], i64 1
2675; CHECK-NEXT:    [[TMP25:%.*]] = zext i16 [[TMP23]] to i32
2676; CHECK-NEXT:    [[TMP26:%.*]] = zext i16 [[TMP24]] to i32
2677; CHECK-NEXT:    [[TMP27:%.*]] = uitofp i32 [[TMP25]] to float
2678; CHECK-NEXT:    [[TMP28:%.*]] = uitofp i32 [[TMP26]] to float
2679; CHECK-NEXT:    [[TMP29:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP28]])
2680; CHECK-NEXT:    [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]]
2681; CHECK-NEXT:    [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]])
2682; CHECK-NEXT:    [[TMP32:%.*]] = fneg fast float [[TMP31]]
2683; CHECK-NEXT:    [[TMP33:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP32]], float [[TMP28]], float [[TMP27]])
2684; CHECK-NEXT:    [[TMP34:%.*]] = fptoui float [[TMP31]] to i32
2685; CHECK-NEXT:    [[TMP35:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
2686; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.fabs.f32(float [[TMP28]])
2687; CHECK-NEXT:    [[TMP37:%.*]] = fcmp fast oge float [[TMP35]], [[TMP36]]
2688; CHECK-NEXT:    [[TMP38:%.*]] = select i1 [[TMP37]], i32 1, i32 0
2689; CHECK-NEXT:    [[TMP39:%.*]] = add i32 [[TMP34]], [[TMP38]]
2690; CHECK-NEXT:    [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP26]]
2691; CHECK-NEXT:    [[TMP41:%.*]] = sub i32 [[TMP25]], [[TMP40]]
2692; CHECK-NEXT:    [[TMP42:%.*]] = and i32 [[TMP41]], 65535
2693; CHECK-NEXT:    [[TMP43:%.*]] = trunc i32 [[TMP42]] to i16
2694; CHECK-NEXT:    [[TMP44:%.*]] = insertelement <4 x i16> [[TMP22]], i16 [[TMP43]], i64 1
2695; CHECK-NEXT:    [[TMP45:%.*]] = extractelement <4 x i16> [[X]], i64 2
2696; CHECK-NEXT:    [[TMP46:%.*]] = extractelement <4 x i16> [[Y]], i64 2
2697; CHECK-NEXT:    [[TMP47:%.*]] = zext i16 [[TMP45]] to i32
2698; CHECK-NEXT:    [[TMP48:%.*]] = zext i16 [[TMP46]] to i32
2699; CHECK-NEXT:    [[TMP49:%.*]] = uitofp i32 [[TMP47]] to float
2700; CHECK-NEXT:    [[TMP50:%.*]] = uitofp i32 [[TMP48]] to float
2701; CHECK-NEXT:    [[TMP51:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP50]])
2702; CHECK-NEXT:    [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]]
2703; CHECK-NEXT:    [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]])
2704; CHECK-NEXT:    [[TMP54:%.*]] = fneg fast float [[TMP53]]
2705; CHECK-NEXT:    [[TMP55:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP54]], float [[TMP50]], float [[TMP49]])
2706; CHECK-NEXT:    [[TMP56:%.*]] = fptoui float [[TMP53]] to i32
2707; CHECK-NEXT:    [[TMP57:%.*]] = call fast float @llvm.fabs.f32(float [[TMP55]])
2708; CHECK-NEXT:    [[TMP58:%.*]] = call fast float @llvm.fabs.f32(float [[TMP50]])
2709; CHECK-NEXT:    [[TMP59:%.*]] = fcmp fast oge float [[TMP57]], [[TMP58]]
2710; CHECK-NEXT:    [[TMP60:%.*]] = select i1 [[TMP59]], i32 1, i32 0
2711; CHECK-NEXT:    [[TMP61:%.*]] = add i32 [[TMP56]], [[TMP60]]
2712; CHECK-NEXT:    [[TMP62:%.*]] = mul i32 [[TMP61]], [[TMP48]]
2713; CHECK-NEXT:    [[TMP63:%.*]] = sub i32 [[TMP47]], [[TMP62]]
2714; CHECK-NEXT:    [[TMP64:%.*]] = and i32 [[TMP63]], 65535
2715; CHECK-NEXT:    [[TMP65:%.*]] = trunc i32 [[TMP64]] to i16
2716; CHECK-NEXT:    [[TMP66:%.*]] = insertelement <4 x i16> [[TMP44]], i16 [[TMP65]], i64 2
2717; CHECK-NEXT:    [[TMP67:%.*]] = extractelement <4 x i16> [[X]], i64 3
2718; CHECK-NEXT:    [[TMP68:%.*]] = extractelement <4 x i16> [[Y]], i64 3
2719; CHECK-NEXT:    [[TMP69:%.*]] = zext i16 [[TMP67]] to i32
2720; CHECK-NEXT:    [[TMP70:%.*]] = zext i16 [[TMP68]] to i32
2721; CHECK-NEXT:    [[TMP71:%.*]] = uitofp i32 [[TMP69]] to float
2722; CHECK-NEXT:    [[TMP72:%.*]] = uitofp i32 [[TMP70]] to float
2723; CHECK-NEXT:    [[TMP73:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP72]])
2724; CHECK-NEXT:    [[TMP74:%.*]] = fmul fast float [[TMP71]], [[TMP73]]
2725; CHECK-NEXT:    [[TMP75:%.*]] = call fast float @llvm.trunc.f32(float [[TMP74]])
2726; CHECK-NEXT:    [[TMP76:%.*]] = fneg fast float [[TMP75]]
2727; CHECK-NEXT:    [[TMP77:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP76]], float [[TMP72]], float [[TMP71]])
2728; CHECK-NEXT:    [[TMP78:%.*]] = fptoui float [[TMP75]] to i32
2729; CHECK-NEXT:    [[TMP79:%.*]] = call fast float @llvm.fabs.f32(float [[TMP77]])
2730; CHECK-NEXT:    [[TMP80:%.*]] = call fast float @llvm.fabs.f32(float [[TMP72]])
2731; CHECK-NEXT:    [[TMP81:%.*]] = fcmp fast oge float [[TMP79]], [[TMP80]]
2732; CHECK-NEXT:    [[TMP82:%.*]] = select i1 [[TMP81]], i32 1, i32 0
2733; CHECK-NEXT:    [[TMP83:%.*]] = add i32 [[TMP78]], [[TMP82]]
2734; CHECK-NEXT:    [[TMP84:%.*]] = mul i32 [[TMP83]], [[TMP70]]
2735; CHECK-NEXT:    [[TMP85:%.*]] = sub i32 [[TMP69]], [[TMP84]]
2736; CHECK-NEXT:    [[TMP86:%.*]] = and i32 [[TMP85]], 65535
2737; CHECK-NEXT:    [[TMP87:%.*]] = trunc i32 [[TMP86]] to i16
2738; CHECK-NEXT:    [[TMP88:%.*]] = insertelement <4 x i16> [[TMP66]], i16 [[TMP87]], i64 3
2739; CHECK-NEXT:    store <4 x i16> [[TMP88]], <4 x i16> addrspace(1)* [[OUT:%.*]], align 8
2740; CHECK-NEXT:    ret void
2741;
2742; GFX6-LABEL: urem_v4i16:
2743; GFX6:       ; %bb.0:
2744; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
2745; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
2746; GFX6-NEXT:    s_mov_b32 s8, 0xffff
2747; GFX6-NEXT:    s_mov_b32 s3, 0xf000
2748; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
2749; GFX6-NEXT:    s_and_b32 s2, s6, s8
2750; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s2
2751; GFX6-NEXT:    v_mov_b32_e32 v4, s6
2752; GFX6-NEXT:    v_alignbit_b32 v4, s7, v4, 16
2753; GFX6-NEXT:    s_and_b32 s9, s4, s8
2754; GFX6-NEXT:    v_and_b32_e32 v5, s8, v4
2755; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
2756; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
2757; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, v5
2758; GFX6-NEXT:    v_mov_b32_e32 v3, s4
2759; GFX6-NEXT:    v_alignbit_b32 v3, s5, v3, 16
2760; GFX6-NEXT:    v_and_b32_e32 v6, s8, v3
2761; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
2762; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, v6
2763; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v5
2764; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
2765; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
2766; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
2767; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
2768; GFX6-NEXT:    v_mul_f32_e32 v1, v6, v7
2769; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
2770; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
2771; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v1
2772; GFX6-NEXT:    v_mad_f32 v1, -v1, v5, v6
2773; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s6
2774; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v5
2775; GFX6-NEXT:    s_and_b32 s6, s7, s8
2776; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
2777; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s6
2778; GFX6-NEXT:    s_and_b32 s6, s5, s8
2779; GFX6-NEXT:    v_mul_lo_u32 v1, v1, v4
2780; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s6
2781; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v2
2782; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
2783; GFX6-NEXT:    s_lshr_b32 s4, s7, 16
2784; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, v3, v1
2785; GFX6-NEXT:    v_mul_f32_e32 v1, v4, v5
2786; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s4
2787; GFX6-NEXT:    s_lshr_b32 s6, s5, 16
2788; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s6
2789; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
2790; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v5
2791; GFX6-NEXT:    v_mad_f32 v4, -v1, v2, v4
2792; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
2793; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v2
2794; GFX6-NEXT:    v_mul_f32_e32 v2, v6, v7
2795; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
2796; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v2
2797; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
2798; GFX6-NEXT:    v_mad_f32 v2, -v2, v5, v6
2799; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v5
2800; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v4, vcc
2801; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s7
2802; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s4
2803; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
2804; GFX6-NEXT:    s_mov_b32 s2, -1
2805; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
2806; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s6, v2
2807; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
2808; GFX6-NEXT:    v_and_b32_e32 v1, s8, v1
2809; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
2810; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
2811; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
2812; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2813; GFX6-NEXT:    s_endpgm
2814;
2815; GFX9-LABEL: urem_v4i16:
2816; GFX9:       ; %bb.0:
2817; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
2818; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
2819; GFX9-NEXT:    s_mov_b32 s0, 0xffff
2820; GFX9-NEXT:    v_mov_b32_e32 v2, 0
2821; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
2822; GFX9-NEXT:    s_and_b32 s8, s6, s0
2823; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
2824; GFX9-NEXT:    s_and_b32 s1, s4, s0
2825; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s1
2826; GFX9-NEXT:    s_lshr_b32 s6, s6, 16
2827; GFX9-NEXT:    v_rcp_iflag_f32_e32 v4, v0
2828; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, s6
2829; GFX9-NEXT:    s_lshr_b32 s4, s4, 16
2830; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s4
2831; GFX9-NEXT:    v_mul_f32_e32 v4, v1, v4
2832; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
2833; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v3
2834; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v4
2835; GFX9-NEXT:    v_mad_f32 v1, -v4, v0, v1
2836; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
2837; GFX9-NEXT:    v_mul_f32_e32 v1, v5, v6
2838; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v7, vcc
2839; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s8
2840; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
2841; GFX9-NEXT:    s_and_b32 s8, s7, s0
2842; GFX9-NEXT:    v_mad_f32 v4, -v1, v3, v5
2843; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s8
2844; GFX9-NEXT:    s_and_b32 s0, s5, s0
2845; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
2846; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
2847; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v5
2848; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v3
2849; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
2850; GFX9-NEXT:    v_mul_f32_e32 v3, v6, v7
2851; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s6
2852; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
2853; GFX9-NEXT:    s_lshr_b32 s6, s7, 16
2854; GFX9-NEXT:    v_mad_f32 v4, -v3, v5, v6
2855; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s6
2856; GFX9-NEXT:    s_lshr_b32 s5, s5, 16
2857; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s5
2858; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
2859; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v6
2860; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v5
2861; GFX9-NEXT:    v_sub_u32_e32 v0, s1, v0
2862; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
2863; GFX9-NEXT:    v_mul_f32_e32 v4, v7, v8
2864; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
2865; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v4
2866; GFX9-NEXT:    v_mad_f32 v4, -v4, v6, v7
2867; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v6
2868; GFX9-NEXT:    v_mul_lo_u32 v3, v3, s8
2869; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
2870; GFX9-NEXT:    v_mul_lo_u32 v4, v4, s6
2871; GFX9-NEXT:    v_sub_u32_e32 v5, s4, v1
2872; GFX9-NEXT:    v_sub_u32_e32 v1, s0, v3
2873; GFX9-NEXT:    v_sub_u32_e32 v3, s5, v4
2874; GFX9-NEXT:    v_mov_b32_e32 v4, 0xffff
2875; GFX9-NEXT:    v_and_b32_e32 v1, v4, v1
2876; GFX9-NEXT:    v_and_b32_e32 v0, v4, v0
2877; GFX9-NEXT:    v_lshl_or_b32 v1, v3, 16, v1
2878; GFX9-NEXT:    v_lshl_or_b32 v0, v5, 16, v0
2879; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
2880; GFX9-NEXT:    s_endpgm
2881  %r = urem <4 x i16> %x, %y
2882  store <4 x i16> %r, <4 x i16> addrspace(1)* %out
2883  ret void
2884}
2885
2886define amdgpu_kernel void @sdiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x, <4 x i16> %y) {
2887; CHECK-LABEL: @sdiv_v4i16(
2888; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i16> [[X:%.*]], i64 0
2889; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i16> [[Y:%.*]], i64 0
2890; CHECK-NEXT:    [[TMP3:%.*]] = sext i16 [[TMP1]] to i32
2891; CHECK-NEXT:    [[TMP4:%.*]] = sext i16 [[TMP2]] to i32
2892; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
2893; CHECK-NEXT:    [[TMP6:%.*]] = ashr i32 [[TMP5]], 30
2894; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], 1
2895; CHECK-NEXT:    [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float
2896; CHECK-NEXT:    [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float
2897; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
2898; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]
2899; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])
2900; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
2901; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
2902; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
2903; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
2904; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
2905; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
2906; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
2907; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
2908; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 16
2909; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 16
2910; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i16
2911; CHECK-NEXT:    [[TMP24:%.*]] = insertelement <4 x i16> undef, i16 [[TMP23]], i64 0
2912; CHECK-NEXT:    [[TMP25:%.*]] = extractelement <4 x i16> [[X]], i64 1
2913; CHECK-NEXT:    [[TMP26:%.*]] = extractelement <4 x i16> [[Y]], i64 1
2914; CHECK-NEXT:    [[TMP27:%.*]] = sext i16 [[TMP25]] to i32
2915; CHECK-NEXT:    [[TMP28:%.*]] = sext i16 [[TMP26]] to i32
2916; CHECK-NEXT:    [[TMP29:%.*]] = xor i32 [[TMP27]], [[TMP28]]
2917; CHECK-NEXT:    [[TMP30:%.*]] = ashr i32 [[TMP29]], 30
2918; CHECK-NEXT:    [[TMP31:%.*]] = or i32 [[TMP30]], 1
2919; CHECK-NEXT:    [[TMP32:%.*]] = sitofp i32 [[TMP27]] to float
2920; CHECK-NEXT:    [[TMP33:%.*]] = sitofp i32 [[TMP28]] to float
2921; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])
2922; CHECK-NEXT:    [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]]
2923; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]])
2924; CHECK-NEXT:    [[TMP37:%.*]] = fneg fast float [[TMP36]]
2925; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]])
2926; CHECK-NEXT:    [[TMP39:%.*]] = fptosi float [[TMP36]] to i32
2927; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]])
2928; CHECK-NEXT:    [[TMP41:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
2929; CHECK-NEXT:    [[TMP42:%.*]] = fcmp fast oge float [[TMP40]], [[TMP41]]
2930; CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP31]], i32 0
2931; CHECK-NEXT:    [[TMP44:%.*]] = add i32 [[TMP39]], [[TMP43]]
2932; CHECK-NEXT:    [[TMP45:%.*]] = shl i32 [[TMP44]], 16
2933; CHECK-NEXT:    [[TMP46:%.*]] = ashr i32 [[TMP45]], 16
2934; CHECK-NEXT:    [[TMP47:%.*]] = trunc i32 [[TMP46]] to i16
2935; CHECK-NEXT:    [[TMP48:%.*]] = insertelement <4 x i16> [[TMP24]], i16 [[TMP47]], i64 1
2936; CHECK-NEXT:    [[TMP49:%.*]] = extractelement <4 x i16> [[X]], i64 2
2937; CHECK-NEXT:    [[TMP50:%.*]] = extractelement <4 x i16> [[Y]], i64 2
2938; CHECK-NEXT:    [[TMP51:%.*]] = sext i16 [[TMP49]] to i32
2939; CHECK-NEXT:    [[TMP52:%.*]] = sext i16 [[TMP50]] to i32
2940; CHECK-NEXT:    [[TMP53:%.*]] = xor i32 [[TMP51]], [[TMP52]]
2941; CHECK-NEXT:    [[TMP54:%.*]] = ashr i32 [[TMP53]], 30
2942; CHECK-NEXT:    [[TMP55:%.*]] = or i32 [[TMP54]], 1
2943; CHECK-NEXT:    [[TMP56:%.*]] = sitofp i32 [[TMP51]] to float
2944; CHECK-NEXT:    [[TMP57:%.*]] = sitofp i32 [[TMP52]] to float
2945; CHECK-NEXT:    [[TMP58:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP57]])
2946; CHECK-NEXT:    [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]]
2947; CHECK-NEXT:    [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]])
2948; CHECK-NEXT:    [[TMP61:%.*]] = fneg fast float [[TMP60]]
2949; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]])
2950; CHECK-NEXT:    [[TMP63:%.*]] = fptosi float [[TMP60]] to i32
2951; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]])
2952; CHECK-NEXT:    [[TMP65:%.*]] = call fast float @llvm.fabs.f32(float [[TMP57]])
2953; CHECK-NEXT:    [[TMP66:%.*]] = fcmp fast oge float [[TMP64]], [[TMP65]]
2954; CHECK-NEXT:    [[TMP67:%.*]] = select i1 [[TMP66]], i32 [[TMP55]], i32 0
2955; CHECK-NEXT:    [[TMP68:%.*]] = add i32 [[TMP63]], [[TMP67]]
2956; CHECK-NEXT:    [[TMP69:%.*]] = shl i32 [[TMP68]], 16
2957; CHECK-NEXT:    [[TMP70:%.*]] = ashr i32 [[TMP69]], 16
2958; CHECK-NEXT:    [[TMP71:%.*]] = trunc i32 [[TMP70]] to i16
2959; CHECK-NEXT:    [[TMP72:%.*]] = insertelement <4 x i16> [[TMP48]], i16 [[TMP71]], i64 2
2960; CHECK-NEXT:    [[TMP73:%.*]] = extractelement <4 x i16> [[X]], i64 3
2961; CHECK-NEXT:    [[TMP74:%.*]] = extractelement <4 x i16> [[Y]], i64 3
2962; CHECK-NEXT:    [[TMP75:%.*]] = sext i16 [[TMP73]] to i32
2963; CHECK-NEXT:    [[TMP76:%.*]] = sext i16 [[TMP74]] to i32
2964; CHECK-NEXT:    [[TMP77:%.*]] = xor i32 [[TMP75]], [[TMP76]]
2965; CHECK-NEXT:    [[TMP78:%.*]] = ashr i32 [[TMP77]], 30
2966; CHECK-NEXT:    [[TMP79:%.*]] = or i32 [[TMP78]], 1
2967; CHECK-NEXT:    [[TMP80:%.*]] = sitofp i32 [[TMP75]] to float
2968; CHECK-NEXT:    [[TMP81:%.*]] = sitofp i32 [[TMP76]] to float
2969; CHECK-NEXT:    [[TMP82:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP81]])
2970; CHECK-NEXT:    [[TMP83:%.*]] = fmul fast float [[TMP80]], [[TMP82]]
2971; CHECK-NEXT:    [[TMP84:%.*]] = call fast float @llvm.trunc.f32(float [[TMP83]])
2972; CHECK-NEXT:    [[TMP85:%.*]] = fneg fast float [[TMP84]]
2973; CHECK-NEXT:    [[TMP86:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP85]], float [[TMP81]], float [[TMP80]])
2974; CHECK-NEXT:    [[TMP87:%.*]] = fptosi float [[TMP84]] to i32
2975; CHECK-NEXT:    [[TMP88:%.*]] = call fast float @llvm.fabs.f32(float [[TMP86]])
2976; CHECK-NEXT:    [[TMP89:%.*]] = call fast float @llvm.fabs.f32(float [[TMP81]])
2977; CHECK-NEXT:    [[TMP90:%.*]] = fcmp fast oge float [[TMP88]], [[TMP89]]
2978; CHECK-NEXT:    [[TMP91:%.*]] = select i1 [[TMP90]], i32 [[TMP79]], i32 0
2979; CHECK-NEXT:    [[TMP92:%.*]] = add i32 [[TMP87]], [[TMP91]]
2980; CHECK-NEXT:    [[TMP93:%.*]] = shl i32 [[TMP92]], 16
2981; CHECK-NEXT:    [[TMP94:%.*]] = ashr i32 [[TMP93]], 16
2982; CHECK-NEXT:    [[TMP95:%.*]] = trunc i32 [[TMP94]] to i16
2983; CHECK-NEXT:    [[TMP96:%.*]] = insertelement <4 x i16> [[TMP72]], i16 [[TMP95]], i64 3
2984; CHECK-NEXT:    store <4 x i16> [[TMP96]], <4 x i16> addrspace(1)* [[OUT:%.*]], align 8
2985; CHECK-NEXT:    ret void
2986;
2987; GFX6-LABEL: sdiv_v4i16:
2988; GFX6:       ; %bb.0:
2989; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
2990; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
2991; GFX6-NEXT:    s_mov_b32 s3, 0xf000
2992; GFX6-NEXT:    s_mov_b32 s2, -1
2993; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
2994; GFX6-NEXT:    s_sext_i32_i16 s8, s6
2995; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s8
2996; GFX6-NEXT:    s_sext_i32_i16 s9, s4
2997; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s9
2998; GFX6-NEXT:    s_xor_b32 s8, s9, s8
2999; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
3000; GFX6-NEXT:    s_ashr_i32 s6, s6, 16
3001; GFX6-NEXT:    s_ashr_i32 s8, s8, 30
3002; GFX6-NEXT:    s_or_b32 s8, s8, 1
3003; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
3004; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
3005; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
3006; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
3007; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
3008; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s6
3009; GFX6-NEXT:    v_mov_b32_e32 v3, s8
3010; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
3011; GFX6-NEXT:    s_ashr_i32 s4, s4, 16
3012; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
3013; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s4
3014; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v1
3015; GFX6-NEXT:    s_xor_b32 s4, s4, s6
3016; GFX6-NEXT:    s_ashr_i32 s4, s4, 30
3017; GFX6-NEXT:    s_or_b32 s4, s4, 1
3018; GFX6-NEXT:    v_mul_f32_e32 v3, v2, v3
3019; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
3020; GFX6-NEXT:    v_mad_f32 v2, -v3, v1, v2
3021; GFX6-NEXT:    v_mov_b32_e32 v4, s4
3022; GFX6-NEXT:    s_sext_i32_i16 s4, s7
3023; GFX6-NEXT:    v_cvt_i32_f32_e32 v3, v3
3024; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
3025; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s4
3026; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
3027; GFX6-NEXT:    s_sext_i32_i16 s6, s5
3028; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v1, v3
3029; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s6
3030; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
3031; GFX6-NEXT:    s_xor_b32 s4, s6, s4
3032; GFX6-NEXT:    s_ashr_i32 s4, s4, 30
3033; GFX6-NEXT:    s_or_b32 s4, s4, 1
3034; GFX6-NEXT:    v_mul_f32_e32 v4, v1, v4
3035; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
3036; GFX6-NEXT:    v_mad_f32 v1, -v4, v2, v1
3037; GFX6-NEXT:    v_mov_b32_e32 v5, s4
3038; GFX6-NEXT:    s_ashr_i32 s4, s7, 16
3039; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v4
3040; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v2|
3041; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s4
3042; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
3043; GFX6-NEXT:    s_ashr_i32 s5, s5, 16
3044; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
3045; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s5
3046; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v2
3047; GFX6-NEXT:    s_xor_b32 s4, s5, s4
3048; GFX6-NEXT:    s_ashr_i32 s4, s4, 30
3049; GFX6-NEXT:    s_or_b32 s4, s4, 1
3050; GFX6-NEXT:    v_mul_f32_e32 v5, v4, v5
3051; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
3052; GFX6-NEXT:    v_mad_f32 v4, -v5, v2, v4
3053; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
3054; GFX6-NEXT:    v_mov_b32_e32 v6, s4
3055; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v2|
3056; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v6, vcc
3057; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
3058; GFX6-NEXT:    s_mov_b32 s4, 0xffff
3059; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
3060; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
3061; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
3062; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
3063; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
3064; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
3065; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
3066; GFX6-NEXT:    s_endpgm
3067;
3068; GFX9-LABEL: sdiv_v4i16:
3069; GFX9:       ; %bb.0:
3070; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
3071; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
3072; GFX9-NEXT:    v_mov_b32_e32 v2, 0
3073; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3074; GFX9-NEXT:    s_sext_i32_i16 s0, s6
3075; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s0
3076; GFX9-NEXT:    s_sext_i32_i16 s1, s4
3077; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s1
3078; GFX9-NEXT:    s_xor_b32 s0, s1, s0
3079; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
3080; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3081; GFX9-NEXT:    s_or_b32 s8, s0, 1
3082; GFX9-NEXT:    v_mul_f32_e32 v3, v1, v3
3083; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
3084; GFX9-NEXT:    v_mad_f32 v1, -v3, v0, v1
3085; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
3086; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
3087; GFX9-NEXT:    s_cselect_b32 s0, s8, 0
3088; GFX9-NEXT:    s_ashr_i32 s1, s6, 16
3089; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s1
3090; GFX9-NEXT:    s_ashr_i32 s4, s4, 16
3091; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s4
3092; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
3093; GFX9-NEXT:    v_rcp_iflag_f32_e32 v4, v0
3094; GFX9-NEXT:    v_add_u32_e32 v3, s0, v3
3095; GFX9-NEXT:    v_mul_f32_e32 v4, v1, v4
3096; GFX9-NEXT:    s_xor_b32 s0, s4, s1
3097; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
3098; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3099; GFX9-NEXT:    v_mad_f32 v1, -v4, v0, v1
3100; GFX9-NEXT:    s_or_b32 s4, s0, 1
3101; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
3102; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
3103; GFX9-NEXT:    v_cvt_i32_f32_e32 v4, v4
3104; GFX9-NEXT:    s_sext_i32_i16 s1, s7
3105; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s1
3106; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
3107; GFX9-NEXT:    v_add_u32_e32 v4, s0, v4
3108; GFX9-NEXT:    s_sext_i32_i16 s0, s5
3109; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s0
3110; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v0
3111; GFX9-NEXT:    s_xor_b32 s0, s0, s1
3112; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3113; GFX9-NEXT:    s_or_b32 s4, s0, 1
3114; GFX9-NEXT:    v_mul_f32_e32 v5, v1, v5
3115; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
3116; GFX9-NEXT:    v_mad_f32 v1, -v5, v0, v1
3117; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
3118; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
3119; GFX9-NEXT:    v_cvt_i32_f32_e32 v5, v5
3120; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
3121; GFX9-NEXT:    s_ashr_i32 s1, s7, 16
3122; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s1
3123; GFX9-NEXT:    v_add_u32_e32 v1, s0, v5
3124; GFX9-NEXT:    s_ashr_i32 s0, s5, 16
3125; GFX9-NEXT:    v_cvt_f32_i32_e32 v5, s0
3126; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v0
3127; GFX9-NEXT:    s_xor_b32 s0, s0, s1
3128; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3129; GFX9-NEXT:    s_or_b32 s4, s0, 1
3130; GFX9-NEXT:    v_mul_f32_e32 v6, v5, v6
3131; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
3132; GFX9-NEXT:    v_mad_f32 v5, -v6, v0, v5
3133; GFX9-NEXT:    v_cvt_i32_f32_e32 v6, v6
3134; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v5|, |v0|
3135; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
3136; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
3137; GFX9-NEXT:    v_mov_b32_e32 v5, 0xffff
3138; GFX9-NEXT:    v_add_u32_e32 v0, s0, v6
3139; GFX9-NEXT:    v_and_b32_e32 v1, v5, v1
3140; GFX9-NEXT:    v_lshl_or_b32 v1, v0, 16, v1
3141; GFX9-NEXT:    v_and_b32_e32 v0, v5, v3
3142; GFX9-NEXT:    v_lshl_or_b32 v0, v4, 16, v0
3143; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
3144; GFX9-NEXT:    s_endpgm
3145  %r = sdiv <4 x i16> %x, %y
3146  store <4 x i16> %r, <4 x i16> addrspace(1)* %out
3147  ret void
3148}
3149
3150define amdgpu_kernel void @srem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x, <4 x i16> %y) {
3151; CHECK-LABEL: @srem_v4i16(
3152; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i16> [[X:%.*]], i64 0
3153; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i16> [[Y:%.*]], i64 0
3154; CHECK-NEXT:    [[TMP3:%.*]] = sext i16 [[TMP1]] to i32
3155; CHECK-NEXT:    [[TMP4:%.*]] = sext i16 [[TMP2]] to i32
3156; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
3157; CHECK-NEXT:    [[TMP6:%.*]] = ashr i32 [[TMP5]], 30
3158; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], 1
3159; CHECK-NEXT:    [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float
3160; CHECK-NEXT:    [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float
3161; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
3162; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]
3163; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])
3164; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
3165; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
3166; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
3167; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
3168; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
3169; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
3170; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
3171; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
3172; CHECK-NEXT:    [[TMP21:%.*]] = mul i32 [[TMP20]], [[TMP4]]
3173; CHECK-NEXT:    [[TMP22:%.*]] = sub i32 [[TMP3]], [[TMP21]]
3174; CHECK-NEXT:    [[TMP23:%.*]] = shl i32 [[TMP22]], 16
3175; CHECK-NEXT:    [[TMP24:%.*]] = ashr i32 [[TMP23]], 16
3176; CHECK-NEXT:    [[TMP25:%.*]] = trunc i32 [[TMP24]] to i16
3177; CHECK-NEXT:    [[TMP26:%.*]] = insertelement <4 x i16> undef, i16 [[TMP25]], i64 0
3178; CHECK-NEXT:    [[TMP27:%.*]] = extractelement <4 x i16> [[X]], i64 1
3179; CHECK-NEXT:    [[TMP28:%.*]] = extractelement <4 x i16> [[Y]], i64 1
3180; CHECK-NEXT:    [[TMP29:%.*]] = sext i16 [[TMP27]] to i32
3181; CHECK-NEXT:    [[TMP30:%.*]] = sext i16 [[TMP28]] to i32
3182; CHECK-NEXT:    [[TMP31:%.*]] = xor i32 [[TMP29]], [[TMP30]]
3183; CHECK-NEXT:    [[TMP32:%.*]] = ashr i32 [[TMP31]], 30
3184; CHECK-NEXT:    [[TMP33:%.*]] = or i32 [[TMP32]], 1
3185; CHECK-NEXT:    [[TMP34:%.*]] = sitofp i32 [[TMP29]] to float
3186; CHECK-NEXT:    [[TMP35:%.*]] = sitofp i32 [[TMP30]] to float
3187; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])
3188; CHECK-NEXT:    [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]]
3189; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]])
3190; CHECK-NEXT:    [[TMP39:%.*]] = fneg fast float [[TMP38]]
3191; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]])
3192; CHECK-NEXT:    [[TMP41:%.*]] = fptosi float [[TMP38]] to i32
3193; CHECK-NEXT:    [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]])
3194; CHECK-NEXT:    [[TMP43:%.*]] = call fast float @llvm.fabs.f32(float [[TMP35]])
3195; CHECK-NEXT:    [[TMP44:%.*]] = fcmp fast oge float [[TMP42]], [[TMP43]]
3196; CHECK-NEXT:    [[TMP45:%.*]] = select i1 [[TMP44]], i32 [[TMP33]], i32 0
3197; CHECK-NEXT:    [[TMP46:%.*]] = add i32 [[TMP41]], [[TMP45]]
3198; CHECK-NEXT:    [[TMP47:%.*]] = mul i32 [[TMP46]], [[TMP30]]
3199; CHECK-NEXT:    [[TMP48:%.*]] = sub i32 [[TMP29]], [[TMP47]]
3200; CHECK-NEXT:    [[TMP49:%.*]] = shl i32 [[TMP48]], 16
3201; CHECK-NEXT:    [[TMP50:%.*]] = ashr i32 [[TMP49]], 16
3202; CHECK-NEXT:    [[TMP51:%.*]] = trunc i32 [[TMP50]] to i16
3203; CHECK-NEXT:    [[TMP52:%.*]] = insertelement <4 x i16> [[TMP26]], i16 [[TMP51]], i64 1
3204; CHECK-NEXT:    [[TMP53:%.*]] = extractelement <4 x i16> [[X]], i64 2
3205; CHECK-NEXT:    [[TMP54:%.*]] = extractelement <4 x i16> [[Y]], i64 2
3206; CHECK-NEXT:    [[TMP55:%.*]] = sext i16 [[TMP53]] to i32
3207; CHECK-NEXT:    [[TMP56:%.*]] = sext i16 [[TMP54]] to i32
3208; CHECK-NEXT:    [[TMP57:%.*]] = xor i32 [[TMP55]], [[TMP56]]
3209; CHECK-NEXT:    [[TMP58:%.*]] = ashr i32 [[TMP57]], 30
3210; CHECK-NEXT:    [[TMP59:%.*]] = or i32 [[TMP58]], 1
3211; CHECK-NEXT:    [[TMP60:%.*]] = sitofp i32 [[TMP55]] to float
3212; CHECK-NEXT:    [[TMP61:%.*]] = sitofp i32 [[TMP56]] to float
3213; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP61]])
3214; CHECK-NEXT:    [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]]
3215; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]])
3216; CHECK-NEXT:    [[TMP65:%.*]] = fneg fast float [[TMP64]]
3217; CHECK-NEXT:    [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]])
3218; CHECK-NEXT:    [[TMP67:%.*]] = fptosi float [[TMP64]] to i32
3219; CHECK-NEXT:    [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]])
3220; CHECK-NEXT:    [[TMP69:%.*]] = call fast float @llvm.fabs.f32(float [[TMP61]])
3221; CHECK-NEXT:    [[TMP70:%.*]] = fcmp fast oge float [[TMP68]], [[TMP69]]
3222; CHECK-NEXT:    [[TMP71:%.*]] = select i1 [[TMP70]], i32 [[TMP59]], i32 0
3223; CHECK-NEXT:    [[TMP72:%.*]] = add i32 [[TMP67]], [[TMP71]]
3224; CHECK-NEXT:    [[TMP73:%.*]] = mul i32 [[TMP72]], [[TMP56]]
3225; CHECK-NEXT:    [[TMP74:%.*]] = sub i32 [[TMP55]], [[TMP73]]
3226; CHECK-NEXT:    [[TMP75:%.*]] = shl i32 [[TMP74]], 16
3227; CHECK-NEXT:    [[TMP76:%.*]] = ashr i32 [[TMP75]], 16
3228; CHECK-NEXT:    [[TMP77:%.*]] = trunc i32 [[TMP76]] to i16
3229; CHECK-NEXT:    [[TMP78:%.*]] = insertelement <4 x i16> [[TMP52]], i16 [[TMP77]], i64 2
3230; CHECK-NEXT:    [[TMP79:%.*]] = extractelement <4 x i16> [[X]], i64 3
3231; CHECK-NEXT:    [[TMP80:%.*]] = extractelement <4 x i16> [[Y]], i64 3
3232; CHECK-NEXT:    [[TMP81:%.*]] = sext i16 [[TMP79]] to i32
3233; CHECK-NEXT:    [[TMP82:%.*]] = sext i16 [[TMP80]] to i32
3234; CHECK-NEXT:    [[TMP83:%.*]] = xor i32 [[TMP81]], [[TMP82]]
3235; CHECK-NEXT:    [[TMP84:%.*]] = ashr i32 [[TMP83]], 30
3236; CHECK-NEXT:    [[TMP85:%.*]] = or i32 [[TMP84]], 1
3237; CHECK-NEXT:    [[TMP86:%.*]] = sitofp i32 [[TMP81]] to float
3238; CHECK-NEXT:    [[TMP87:%.*]] = sitofp i32 [[TMP82]] to float
3239; CHECK-NEXT:    [[TMP88:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP87]])
3240; CHECK-NEXT:    [[TMP89:%.*]] = fmul fast float [[TMP86]], [[TMP88]]
3241; CHECK-NEXT:    [[TMP90:%.*]] = call fast float @llvm.trunc.f32(float [[TMP89]])
3242; CHECK-NEXT:    [[TMP91:%.*]] = fneg fast float [[TMP90]]
3243; CHECK-NEXT:    [[TMP92:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP91]], float [[TMP87]], float [[TMP86]])
3244; CHECK-NEXT:    [[TMP93:%.*]] = fptosi float [[TMP90]] to i32
3245; CHECK-NEXT:    [[TMP94:%.*]] = call fast float @llvm.fabs.f32(float [[TMP92]])
3246; CHECK-NEXT:    [[TMP95:%.*]] = call fast float @llvm.fabs.f32(float [[TMP87]])
3247; CHECK-NEXT:    [[TMP96:%.*]] = fcmp fast oge float [[TMP94]], [[TMP95]]
3248; CHECK-NEXT:    [[TMP97:%.*]] = select i1 [[TMP96]], i32 [[TMP85]], i32 0
3249; CHECK-NEXT:    [[TMP98:%.*]] = add i32 [[TMP93]], [[TMP97]]
3250; CHECK-NEXT:    [[TMP99:%.*]] = mul i32 [[TMP98]], [[TMP82]]
3251; CHECK-NEXT:    [[TMP100:%.*]] = sub i32 [[TMP81]], [[TMP99]]
3252; CHECK-NEXT:    [[TMP101:%.*]] = shl i32 [[TMP100]], 16
3253; CHECK-NEXT:    [[TMP102:%.*]] = ashr i32 [[TMP101]], 16
3254; CHECK-NEXT:    [[TMP103:%.*]] = trunc i32 [[TMP102]] to i16
3255; CHECK-NEXT:    [[TMP104:%.*]] = insertelement <4 x i16> [[TMP78]], i16 [[TMP103]], i64 3
3256; CHECK-NEXT:    store <4 x i16> [[TMP104]], <4 x i16> addrspace(1)* [[OUT:%.*]], align 8
3257; CHECK-NEXT:    ret void
3258;
3259; GFX6-LABEL: srem_v4i16:
3260; GFX6:       ; %bb.0:
3261; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
3262; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
3263; GFX6-NEXT:    s_mov_b32 s3, 0xf000
3264; GFX6-NEXT:    s_mov_b32 s2, -1
3265; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
3266; GFX6-NEXT:    s_sext_i32_i16 s8, s6
3267; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s8
3268; GFX6-NEXT:    s_sext_i32_i16 s9, s4
3269; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s9
3270; GFX6-NEXT:    s_xor_b32 s8, s9, s8
3271; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
3272; GFX6-NEXT:    s_ashr_i32 s8, s8, 30
3273; GFX6-NEXT:    s_or_b32 s8, s8, 1
3274; GFX6-NEXT:    v_mov_b32_e32 v3, s8
3275; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
3276; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
3277; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
3278; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
3279; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
3280; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
3281; GFX6-NEXT:    v_mov_b32_e32 v1, s4
3282; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
3283; GFX6-NEXT:    v_mov_b32_e32 v2, s6
3284; GFX6-NEXT:    v_alignbit_b32 v2, s7, v2, 16
3285; GFX6-NEXT:    v_bfe_i32 v3, v2, 0, 16
3286; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, v3
3287; GFX6-NEXT:    v_alignbit_b32 v1, s5, v1, 16
3288; GFX6-NEXT:    v_bfe_i32 v5, v1, 0, 16
3289; GFX6-NEXT:    v_cvt_f32_i32_e32 v6, v5
3290; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v4
3291; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s6
3292; GFX6-NEXT:    v_xor_b32_e32 v3, v5, v3
3293; GFX6-NEXT:    v_ashrrev_i32_e32 v3, 30, v3
3294; GFX6-NEXT:    v_mul_f32_e32 v5, v6, v7
3295; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
3296; GFX6-NEXT:    v_mad_f32 v6, -v5, v4, v6
3297; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
3298; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
3299; GFX6-NEXT:    v_or_b32_e32 v3, 1, v3
3300; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, |v4|
3301; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
3302; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
3303; GFX6-NEXT:    s_sext_i32_i16 s4, s7
3304; GFX6-NEXT:    v_mul_lo_u32 v2, v3, v2
3305; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s4
3306; GFX6-NEXT:    s_sext_i32_i16 s6, s5
3307; GFX6-NEXT:    s_xor_b32 s4, s6, s4
3308; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v2
3309; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s6
3310; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v3
3311; GFX6-NEXT:    s_ashr_i32 s4, s4, 30
3312; GFX6-NEXT:    s_or_b32 s4, s4, 1
3313; GFX6-NEXT:    v_mov_b32_e32 v5, s4
3314; GFX6-NEXT:    v_mul_f32_e32 v4, v2, v4
3315; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
3316; GFX6-NEXT:    v_mad_f32 v2, -v4, v3, v2
3317; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v4
3318; GFX6-NEXT:    s_ashr_i32 s4, s7, 16
3319; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v3|
3320; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s4
3321; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
3322; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
3323; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s7
3324; GFX6-NEXT:    s_lshr_b32 s6, s7, 16
3325; GFX6-NEXT:    s_ashr_i32 s7, s5, 16
3326; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s7
3327; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
3328; GFX6-NEXT:    s_xor_b32 s4, s7, s4
3329; GFX6-NEXT:    s_ashr_i32 s4, s4, 30
3330; GFX6-NEXT:    s_or_b32 s4, s4, 1
3331; GFX6-NEXT:    v_mul_f32_e32 v5, v4, v5
3332; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
3333; GFX6-NEXT:    v_mad_f32 v4, -v5, v3, v4
3334; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
3335; GFX6-NEXT:    v_mov_b32_e32 v6, s4
3336; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v3|
3337; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v6, vcc
3338; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
3339; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s6
3340; GFX6-NEXT:    s_lshr_b32 s4, s5, 16
3341; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s5, v2
3342; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s4, v3
3343; GFX6-NEXT:    s_mov_b32 s4, 0xffff
3344; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
3345; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
3346; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
3347; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v3
3348; GFX6-NEXT:    v_and_b32_e32 v2, s4, v2
3349; GFX6-NEXT:    v_or_b32_e32 v1, v2, v1
3350; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
3351; GFX6-NEXT:    s_endpgm
3352;
3353; GFX9-LABEL: srem_v4i16:
3354; GFX9:       ; %bb.0:
3355; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
3356; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
3357; GFX9-NEXT:    v_mov_b32_e32 v2, 0
3358; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3359; GFX9-NEXT:    s_sext_i32_i16 s8, s6
3360; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s8
3361; GFX9-NEXT:    s_sext_i32_i16 s9, s4
3362; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s9
3363; GFX9-NEXT:    s_xor_b32 s0, s9, s8
3364; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
3365; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3366; GFX9-NEXT:    s_or_b32 s10, s0, 1
3367; GFX9-NEXT:    v_mul_f32_e32 v3, v1, v3
3368; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
3369; GFX9-NEXT:    v_mad_f32 v1, -v3, v0, v1
3370; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
3371; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
3372; GFX9-NEXT:    s_cselect_b32 s0, s10, 0
3373; GFX9-NEXT:    s_ashr_i32 s6, s6, 16
3374; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
3375; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s6
3376; GFX9-NEXT:    s_ashr_i32 s4, s4, 16
3377; GFX9-NEXT:    v_add_u32_e32 v1, s0, v3
3378; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s4
3379; GFX9-NEXT:    v_rcp_iflag_f32_e32 v4, v0
3380; GFX9-NEXT:    s_xor_b32 s0, s4, s6
3381; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3382; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s8
3383; GFX9-NEXT:    v_mul_f32_e32 v4, v3, v4
3384; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
3385; GFX9-NEXT:    v_mad_f32 v3, -v4, v0, v3
3386; GFX9-NEXT:    s_or_b32 s8, s0, 1
3387; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v3|, |v0|
3388; GFX9-NEXT:    v_cvt_i32_f32_e32 v4, v4
3389; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
3390; GFX9-NEXT:    s_cselect_b32 s0, s8, 0
3391; GFX9-NEXT:    s_sext_i32_i16 s8, s7
3392; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s8
3393; GFX9-NEXT:    v_add_u32_e32 v0, s0, v4
3394; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s6
3395; GFX9-NEXT:    s_sext_i32_i16 s6, s5
3396; GFX9-NEXT:    v_cvt_f32_i32_e32 v4, s6
3397; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v3
3398; GFX9-NEXT:    s_xor_b32 s0, s6, s8
3399; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3400; GFX9-NEXT:    s_or_b32 s10, s0, 1
3401; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
3402; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
3403; GFX9-NEXT:    v_mad_f32 v4, -v5, v3, v4
3404; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v4|, |v3|
3405; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
3406; GFX9-NEXT:    s_cselect_b32 s0, s10, 0
3407; GFX9-NEXT:    s_ashr_i32 s7, s7, 16
3408; GFX9-NEXT:    v_cvt_i32_f32_e32 v5, v5
3409; GFX9-NEXT:    v_cvt_f32_i32_e32 v4, s7
3410; GFX9-NEXT:    s_ashr_i32 s5, s5, 16
3411; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
3412; GFX9-NEXT:    v_add_u32_e32 v3, s0, v5
3413; GFX9-NEXT:    v_cvt_f32_i32_e32 v5, s5
3414; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v4
3415; GFX9-NEXT:    s_xor_b32 s0, s5, s7
3416; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3417; GFX9-NEXT:    v_mul_lo_u32 v3, v3, s8
3418; GFX9-NEXT:    v_mul_f32_e32 v6, v5, v6
3419; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
3420; GFX9-NEXT:    v_mad_f32 v5, -v6, v4, v5
3421; GFX9-NEXT:    v_cvt_i32_f32_e32 v6, v6
3422; GFX9-NEXT:    s_or_b32 s8, s0, 1
3423; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v5|, |v4|
3424; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
3425; GFX9-NEXT:    s_cselect_b32 s0, s8, 0
3426; GFX9-NEXT:    v_add_u32_e32 v4, s0, v6
3427; GFX9-NEXT:    v_mul_lo_u32 v4, v4, s7
3428; GFX9-NEXT:    v_sub_u32_e32 v5, s9, v1
3429; GFX9-NEXT:    v_sub_u32_e32 v1, s6, v3
3430; GFX9-NEXT:    v_sub_u32_e32 v3, s5, v4
3431; GFX9-NEXT:    v_mov_b32_e32 v4, 0xffff
3432; GFX9-NEXT:    v_and_b32_e32 v1, v4, v1
3433; GFX9-NEXT:    v_lshl_or_b32 v1, v3, 16, v1
3434; GFX9-NEXT:    v_and_b32_e32 v3, v4, v5
3435; GFX9-NEXT:    v_lshl_or_b32 v0, v0, 16, v3
3436; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
3437; GFX9-NEXT:    s_endpgm
3438  %r = srem <4 x i16> %x, %y
3439  store <4 x i16> %r, <4 x i16> addrspace(1)* %out
3440  ret void
3441}
3442
3443define amdgpu_kernel void @udiv_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) {
3444; CHECK-LABEL: @udiv_i3(
3445; CHECK-NEXT:    [[TMP1:%.*]] = zext i3 [[X:%.*]] to i32
3446; CHECK-NEXT:    [[TMP2:%.*]] = zext i3 [[Y:%.*]] to i32
3447; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
3448; CHECK-NEXT:    [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
3449; CHECK-NEXT:    [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
3450; CHECK-NEXT:    [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
3451; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
3452; CHECK-NEXT:    [[TMP8:%.*]] = fneg fast float [[TMP7]]
3453; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
3454; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
3455; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
3456; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
3457; CHECK-NEXT:    [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
3458; CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
3459; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
3460; CHECK-NEXT:    [[TMP16:%.*]] = and i32 [[TMP15]], 7
3461; CHECK-NEXT:    [[TMP17:%.*]] = trunc i32 [[TMP16]] to i3
3462; CHECK-NEXT:    store i3 [[TMP17]], i3 addrspace(1)* [[OUT:%.*]], align 1
3463; CHECK-NEXT:    ret void
3464;
3465; GFX6-LABEL: udiv_i3:
3466; GFX6:       ; %bb.0:
3467; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
3468; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
3469; GFX6-NEXT:    s_mov_b32 s3, 0xf000
3470; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
3471; GFX6-NEXT:    s_bfe_u32 s2, s4, 0x30008
3472; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v0, s2
3473; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v0
3474; GFX6-NEXT:    s_and_b32 s4, s4, 7
3475; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v2, s4
3476; GFX6-NEXT:    s_mov_b32 s2, -1
3477; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1
3478; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
3479; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v1
3480; GFX6-NEXT:    v_mad_f32 v1, -v1, v0, v2
3481; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
3482; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
3483; GFX6-NEXT:    v_and_b32_e32 v0, 7, v0
3484; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
3485; GFX6-NEXT:    s_endpgm
3486;
3487; GFX9-LABEL: udiv_i3:
3488; GFX9:       ; %bb.0:
3489; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
3490; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
3491; GFX9-NEXT:    v_mov_b32_e32 v2, 0
3492; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3493; GFX9-NEXT:    s_bfe_u32 s0, s4, 0x30008
3494; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, s0
3495; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
3496; GFX9-NEXT:    s_and_b32 s0, s4, 7
3497; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v3, s0
3498; GFX9-NEXT:    v_mul_f32_e32 v1, v3, v1
3499; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
3500; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v1
3501; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v3
3502; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
3503; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v4, vcc
3504; GFX9-NEXT:    v_and_b32_e32 v0, 7, v0
3505; GFX9-NEXT:    global_store_byte v2, v0, s[2:3]
3506; GFX9-NEXT:    s_endpgm
3507  %r = udiv i3 %x, %y
3508  store i3 %r, i3 addrspace(1)* %out
3509  ret void
3510}
3511
3512define amdgpu_kernel void @urem_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) {
3513; CHECK-LABEL: @urem_i3(
3514; CHECK-NEXT:    [[TMP1:%.*]] = zext i3 [[X:%.*]] to i32
3515; CHECK-NEXT:    [[TMP2:%.*]] = zext i3 [[Y:%.*]] to i32
3516; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
3517; CHECK-NEXT:    [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
3518; CHECK-NEXT:    [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
3519; CHECK-NEXT:    [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
3520; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
3521; CHECK-NEXT:    [[TMP8:%.*]] = fneg fast float [[TMP7]]
3522; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
3523; CHECK-NEXT:    [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
3524; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
3525; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
3526; CHECK-NEXT:    [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
3527; CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
3528; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
3529; CHECK-NEXT:    [[TMP16:%.*]] = mul i32 [[TMP15]], [[TMP2]]
3530; CHECK-NEXT:    [[TMP17:%.*]] = sub i32 [[TMP1]], [[TMP16]]
3531; CHECK-NEXT:    [[TMP18:%.*]] = and i32 [[TMP17]], 7
3532; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i3
3533; CHECK-NEXT:    store i3 [[TMP19]], i3 addrspace(1)* [[OUT:%.*]], align 1
3534; CHECK-NEXT:    ret void
3535;
3536; GFX6-LABEL: urem_i3:
3537; GFX6:       ; %bb.0:
3538; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
3539; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
3540; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
3541; GFX6-NEXT:    s_bfe_u32 s2, s4, 0x30008
3542; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v0, s2
3543; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v0
3544; GFX6-NEXT:    s_and_b32 s3, s4, 7
3545; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v2, s3
3546; GFX6-NEXT:    s_lshr_b32 s2, s4, 8
3547; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1
3548; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
3549; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v1
3550; GFX6-NEXT:    v_mad_f32 v1, -v1, v0, v2
3551; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
3552; GFX6-NEXT:    s_mov_b32 s3, 0xf000
3553; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
3554; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
3555; GFX6-NEXT:    s_mov_b32 s2, -1
3556; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
3557; GFX6-NEXT:    v_and_b32_e32 v0, 7, v0
3558; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
3559; GFX6-NEXT:    s_endpgm
3560;
3561; GFX9-LABEL: urem_i3:
3562; GFX9:       ; %bb.0:
3563; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
3564; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3565; GFX9-NEXT:    s_bfe_u32 s3, s2, 0x30008
3566; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, s3
3567; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
3568; GFX9-NEXT:    s_and_b32 s4, s2, 7
3569; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v2, s4
3570; GFX9-NEXT:    s_lshr_b32 s3, s2, 8
3571; GFX9-NEXT:    v_mul_f32_e32 v1, v2, v1
3572; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
3573; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v1
3574; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v2
3575; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
3576; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
3577; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
3578; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
3579; GFX9-NEXT:    v_mov_b32_e32 v1, 0
3580; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
3581; GFX9-NEXT:    v_and_b32_e32 v0, 7, v0
3582; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3583; GFX9-NEXT:    global_store_byte v1, v0, s[0:1]
3584; GFX9-NEXT:    s_endpgm
3585  %r = urem i3 %x, %y
3586  store i3 %r, i3 addrspace(1)* %out
3587  ret void
3588}
3589
3590define amdgpu_kernel void @sdiv_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) {
3591; CHECK-LABEL: @sdiv_i3(
3592; CHECK-NEXT:    [[TMP1:%.*]] = sext i3 [[X:%.*]] to i32
3593; CHECK-NEXT:    [[TMP2:%.*]] = sext i3 [[Y:%.*]] to i32
3594; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
3595; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
3596; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP4]], 1
3597; CHECK-NEXT:    [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
3598; CHECK-NEXT:    [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
3599; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
3600; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
3601; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
3602; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
3603; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
3604; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
3605; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
3606; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
3607; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
3608; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
3609; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
3610; CHECK-NEXT:    [[TMP19:%.*]] = shl i32 [[TMP18]], 29
3611; CHECK-NEXT:    [[TMP20:%.*]] = ashr i32 [[TMP19]], 29
3612; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i3
3613; CHECK-NEXT:    store i3 [[TMP21]], i3 addrspace(1)* [[OUT:%.*]], align 1
3614; CHECK-NEXT:    ret void
3615;
3616; GFX6-LABEL: sdiv_i3:
3617; GFX6:       ; %bb.0:
3618; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
3619; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
3620; GFX6-NEXT:    s_mov_b32 s3, 0xf000
3621; GFX6-NEXT:    s_mov_b32 s2, -1
3622; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
3623; GFX6-NEXT:    s_bfe_i32 s5, s4, 0x30008
3624; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s5
3625; GFX6-NEXT:    s_bfe_i32 s4, s4, 0x30000
3626; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s4
3627; GFX6-NEXT:    s_xor_b32 s4, s4, s5
3628; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
3629; GFX6-NEXT:    s_ashr_i32 s4, s4, 30
3630; GFX6-NEXT:    s_or_b32 s4, s4, 1
3631; GFX6-NEXT:    v_mov_b32_e32 v3, s4
3632; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
3633; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
3634; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
3635; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
3636; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
3637; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
3638; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
3639; GFX6-NEXT:    v_and_b32_e32 v0, 7, v0
3640; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
3641; GFX6-NEXT:    s_endpgm
3642;
3643; GFX9-LABEL: sdiv_i3:
3644; GFX9:       ; %bb.0:
3645; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
3646; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
3647; GFX9-NEXT:    v_mov_b32_e32 v1, 0
3648; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3649; GFX9-NEXT:    s_bfe_i32 s0, s4, 0x30008
3650; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s0
3651; GFX9-NEXT:    s_bfe_i32 s1, s4, 0x30000
3652; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s1
3653; GFX9-NEXT:    s_xor_b32 s0, s1, s0
3654; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
3655; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
3656; GFX9-NEXT:    s_or_b32 s4, s0, 1
3657; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
3658; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
3659; GFX9-NEXT:    v_mad_f32 v2, -v3, v0, v2
3660; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
3661; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
3662; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
3663; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
3664; GFX9-NEXT:    v_add_u32_e32 v0, s0, v3
3665; GFX9-NEXT:    v_and_b32_e32 v0, 7, v0
3666; GFX9-NEXT:    global_store_byte v1, v0, s[2:3]
3667; GFX9-NEXT:    s_endpgm
3668  %r = sdiv i3 %x, %y
3669  store i3 %r, i3 addrspace(1)* %out
3670  ret void
3671}
3672
3673define amdgpu_kernel void @srem_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) {
3674; CHECK-LABEL: @srem_i3(
3675; CHECK-NEXT:    [[TMP1:%.*]] = sext i3 [[X:%.*]] to i32
3676; CHECK-NEXT:    [[TMP2:%.*]] = sext i3 [[Y:%.*]] to i32
3677; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
3678; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
3679; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP4]], 1
3680; CHECK-NEXT:    [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
3681; CHECK-NEXT:    [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
3682; CHECK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
3683; CHECK-NEXT:    [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
3684; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
3685; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
3686; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
3687; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
3688; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
3689; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
3690; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
3691; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
3692; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
3693; CHECK-NEXT:    [[TMP19:%.*]] = mul i32 [[TMP18]], [[TMP2]]
3694; CHECK-NEXT:    [[TMP20:%.*]] = sub i32 [[TMP1]], [[TMP19]]
3695; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 29
3696; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 29
3697; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i3
3698; CHECK-NEXT:    store i3 [[TMP23]], i3 addrspace(1)* [[OUT:%.*]], align 1
3699; CHECK-NEXT:    ret void
3700;
3701; GFX6-LABEL: srem_i3:
3702; GFX6:       ; %bb.0:
3703; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
3704; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
3705; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
3706; GFX6-NEXT:    s_bfe_i32 s2, s4, 0x30008
3707; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s2
3708; GFX6-NEXT:    s_bfe_i32 s5, s4, 0x30000
3709; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s5
3710; GFX6-NEXT:    s_xor_b32 s2, s5, s2
3711; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
3712; GFX6-NEXT:    s_ashr_i32 s2, s2, 30
3713; GFX6-NEXT:    s_or_b32 s2, s2, 1
3714; GFX6-NEXT:    v_mov_b32_e32 v3, s2
3715; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
3716; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
3717; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
3718; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
3719; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
3720; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
3721; GFX6-NEXT:    s_lshr_b32 s3, s4, 8
3722; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
3723; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s3
3724; GFX6-NEXT:    s_mov_b32 s3, 0xf000
3725; GFX6-NEXT:    s_mov_b32 s2, -1
3726; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
3727; GFX6-NEXT:    v_and_b32_e32 v0, 7, v0
3728; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
3729; GFX6-NEXT:    s_endpgm
3730;
3731; GFX9-LABEL: srem_i3:
3732; GFX9:       ; %bb.0:
3733; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
3734; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3735; GFX9-NEXT:    s_bfe_i32 s2, s4, 0x30008
3736; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s2
3737; GFX9-NEXT:    s_bfe_i32 s3, s4, 0x30000
3738; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s3
3739; GFX9-NEXT:    s_xor_b32 s2, s3, s2
3740; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
3741; GFX9-NEXT:    s_ashr_i32 s2, s2, 30
3742; GFX9-NEXT:    s_lshr_b32 s5, s4, 8
3743; GFX9-NEXT:    s_or_b32 s6, s2, 1
3744; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
3745; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
3746; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
3747; GFX9-NEXT:    v_cvt_i32_f32_e32 v2, v2
3748; GFX9-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|
3749; GFX9-NEXT:    s_and_b64 s[2:3], s[2:3], exec
3750; GFX9-NEXT:    s_cselect_b32 s2, s6, 0
3751; GFX9-NEXT:    v_add_u32_e32 v0, s2, v2
3752; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s5
3753; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
3754; GFX9-NEXT:    v_mov_b32_e32 v1, 0
3755; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
3756; GFX9-NEXT:    v_and_b32_e32 v0, 7, v0
3757; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3758; GFX9-NEXT:    global_store_byte v1, v0, s[0:1]
3759; GFX9-NEXT:    s_endpgm
3760  %r = srem i3 %x, %y
3761  store i3 %r, i3 addrspace(1)* %out
3762  ret void
3763}
3764
3765define amdgpu_kernel void @udiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x, <3 x i16> %y) {
3766; CHECK-LABEL: @udiv_v3i16(
3767; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i16> [[X:%.*]], i64 0
3768; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i16> [[Y:%.*]], i64 0
3769; CHECK-NEXT:    [[TMP3:%.*]] = zext i16 [[TMP1]] to i32
3770; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[TMP2]] to i32
3771; CHECK-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float
3772; CHECK-NEXT:    [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float
3773; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])
3774; CHECK-NEXT:    [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]
3775; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])
3776; CHECK-NEXT:    [[TMP10:%.*]] = fneg fast float [[TMP9]]
3777; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])
3778; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP9]] to i32
3779; CHECK-NEXT:    [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])
3780; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])
3781; CHECK-NEXT:    [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]
3782; CHECK-NEXT:    [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 0
3783; CHECK-NEXT:    [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]
3784; CHECK-NEXT:    [[TMP18:%.*]] = and i32 [[TMP17]], 65535
3785; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i16
3786; CHECK-NEXT:    [[TMP20:%.*]] = insertelement <3 x i16> undef, i16 [[TMP19]], i64 0
3787; CHECK-NEXT:    [[TMP21:%.*]] = extractelement <3 x i16> [[X]], i64 1
3788; CHECK-NEXT:    [[TMP22:%.*]] = extractelement <3 x i16> [[Y]], i64 1
3789; CHECK-NEXT:    [[TMP23:%.*]] = zext i16 [[TMP21]] to i32
3790; CHECK-NEXT:    [[TMP24:%.*]] = zext i16 [[TMP22]] to i32
3791; CHECK-NEXT:    [[TMP25:%.*]] = uitofp i32 [[TMP23]] to float
3792; CHECK-NEXT:    [[TMP26:%.*]] = uitofp i32 [[TMP24]] to float
3793; CHECK-NEXT:    [[TMP27:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP26]])
3794; CHECK-NEXT:    [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]]
3795; CHECK-NEXT:    [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]])
3796; CHECK-NEXT:    [[TMP30:%.*]] = fneg fast float [[TMP29]]
3797; CHECK-NEXT:    [[TMP31:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP30]], float [[TMP26]], float [[TMP25]])
3798; CHECK-NEXT:    [[TMP32:%.*]] = fptoui float [[TMP29]] to i32
3799; CHECK-NEXT:    [[TMP33:%.*]] = call fast float @llvm.fabs.f32(float [[TMP31]])
3800; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.fabs.f32(float [[TMP26]])
3801; CHECK-NEXT:    [[TMP35:%.*]] = fcmp fast oge float [[TMP33]], [[TMP34]]
3802; CHECK-NEXT:    [[TMP36:%.*]] = select i1 [[TMP35]], i32 1, i32 0
3803; CHECK-NEXT:    [[TMP37:%.*]] = add i32 [[TMP32]], [[TMP36]]
3804; CHECK-NEXT:    [[TMP38:%.*]] = and i32 [[TMP37]], 65535
3805; CHECK-NEXT:    [[TMP39:%.*]] = trunc i32 [[TMP38]] to i16
3806; CHECK-NEXT:    [[TMP40:%.*]] = insertelement <3 x i16> [[TMP20]], i16 [[TMP39]], i64 1
3807; CHECK-NEXT:    [[TMP41:%.*]] = extractelement <3 x i16> [[X]], i64 2
3808; CHECK-NEXT:    [[TMP42:%.*]] = extractelement <3 x i16> [[Y]], i64 2
3809; CHECK-NEXT:    [[TMP43:%.*]] = zext i16 [[TMP41]] to i32
3810; CHECK-NEXT:    [[TMP44:%.*]] = zext i16 [[TMP42]] to i32
3811; CHECK-NEXT:    [[TMP45:%.*]] = uitofp i32 [[TMP43]] to float
3812; CHECK-NEXT:    [[TMP46:%.*]] = uitofp i32 [[TMP44]] to float
3813; CHECK-NEXT:    [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]])
3814; CHECK-NEXT:    [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]]
3815; CHECK-NEXT:    [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]])
3816; CHECK-NEXT:    [[TMP50:%.*]] = fneg fast float [[TMP49]]
3817; CHECK-NEXT:    [[TMP51:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP50]], float [[TMP46]], float [[TMP45]])
3818; CHECK-NEXT:    [[TMP52:%.*]] = fptoui float [[TMP49]] to i32
3819; CHECK-NEXT:    [[TMP53:%.*]] = call fast float @llvm.fabs.f32(float [[TMP51]])
3820; CHECK-NEXT:    [[TMP54:%.*]] = call fast float @llvm.fabs.f32(float [[TMP46]])
3821; CHECK-NEXT:    [[TMP55:%.*]] = fcmp fast oge float [[TMP53]], [[TMP54]]
3822; CHECK-NEXT:    [[TMP56:%.*]] = select i1 [[TMP55]], i32 1, i32 0
3823; CHECK-NEXT:    [[TMP57:%.*]] = add i32 [[TMP52]], [[TMP56]]
3824; CHECK-NEXT:    [[TMP58:%.*]] = and i32 [[TMP57]], 65535
3825; CHECK-NEXT:    [[TMP59:%.*]] = trunc i32 [[TMP58]] to i16
3826; CHECK-NEXT:    [[TMP60:%.*]] = insertelement <3 x i16> [[TMP40]], i16 [[TMP59]], i64 2
3827; CHECK-NEXT:    store <3 x i16> [[TMP60]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8
3828; CHECK-NEXT:    ret void
3829;
3830; GFX6-LABEL: udiv_v3i16:
3831; GFX6:       ; %bb.0:
3832; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
3833; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
3834; GFX6-NEXT:    s_mov_b32 s8, 0xffff
3835; GFX6-NEXT:    s_mov_b32 s3, 0xf000
3836; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
3837; GFX6-NEXT:    s_and_b32 s2, s6, s8
3838; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s2
3839; GFX6-NEXT:    s_and_b32 s9, s4, s8
3840; GFX6-NEXT:    s_lshr_b32 s6, s6, 16
3841; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
3842; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
3843; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s6
3844; GFX6-NEXT:    s_lshr_b32 s4, s4, 16
3845; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s4
3846; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
3847; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
3848; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
3849; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
3850; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
3851; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
3852; GFX6-NEXT:    v_mul_f32_e32 v1, v4, v5
3853; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
3854; GFX6-NEXT:    s_and_b32 s4, s7, s8
3855; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
3856; GFX6-NEXT:    v_mad_f32 v2, -v1, v3, v4
3857; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s4
3858; GFX6-NEXT:    s_and_b32 s4, s5, s8
3859; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s4
3860; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
3861; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v4
3862; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
3863; GFX6-NEXT:    s_mov_b32 s2, -1
3864; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
3865; GFX6-NEXT:    v_mul_f32_e32 v2, v5, v6
3866; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
3867; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v2
3868; GFX6-NEXT:    v_mad_f32 v2, -v2, v4, v5
3869; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
3870; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
3871; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
3872; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
3873; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
3874; GFX6-NEXT:    buffer_store_short v2, off, s[0:3], 0 offset:4
3875; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
3876; GFX6-NEXT:    s_endpgm
3877;
3878; GFX9-LABEL: udiv_v3i16:
3879; GFX9:       ; %bb.0:
3880; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
3881; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
3882; GFX9-NEXT:    s_mov_b32 s0, 0xffff
3883; GFX9-NEXT:    v_mov_b32_e32 v0, 0
3884; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3885; GFX9-NEXT:    s_and_b32 s8, s6, s0
3886; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s8
3887; GFX9-NEXT:    s_lshr_b32 s6, s6, 16
3888; GFX9-NEXT:    s_and_b32 s1, s4, s0
3889; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, s6
3890; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, s1
3891; GFX9-NEXT:    v_rcp_iflag_f32_e32 v4, v1
3892; GFX9-NEXT:    s_lshr_b32 s1, s4, 16
3893; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s1
3894; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v3
3895; GFX9-NEXT:    v_mul_f32_e32 v4, v2, v4
3896; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
3897; GFX9-NEXT:    v_mad_f32 v2, -v4, v1, v2
3898; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
3899; GFX9-NEXT:    v_mul_f32_e32 v2, v5, v6
3900; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
3901; GFX9-NEXT:    s_and_b32 s1, s7, s0
3902; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v4
3903; GFX9-NEXT:    v_mad_f32 v4, -v2, v3, v5
3904; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s1
3905; GFX9-NEXT:    s_and_b32 s0, s5, s0
3906; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v7, vcc
3907; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
3908; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v5
3909; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
3910; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v3
3911; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff, v1
3912; GFX9-NEXT:    v_mul_f32_e32 v3, v6, v7
3913; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
3914; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v3
3915; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
3916; GFX9-NEXT:    v_mad_f32 v3, -v3, v5, v6
3917; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v5
3918; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
3919; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
3920; GFX9-NEXT:    global_store_short v0, v3, s[2:3] offset:4
3921; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
3922; GFX9-NEXT:    s_endpgm
3923  %r = udiv <3 x i16> %x, %y
3924  store <3 x i16> %r, <3 x i16> addrspace(1)* %out
3925  ret void
3926}
3927
3928define amdgpu_kernel void @urem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x, <3 x i16> %y) {
3929; CHECK-LABEL: @urem_v3i16(
3930; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i16> [[X:%.*]], i64 0
3931; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i16> [[Y:%.*]], i64 0
3932; CHECK-NEXT:    [[TMP3:%.*]] = zext i16 [[TMP1]] to i32
3933; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[TMP2]] to i32
3934; CHECK-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float
3935; CHECK-NEXT:    [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float
3936; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])
3937; CHECK-NEXT:    [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]
3938; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])
3939; CHECK-NEXT:    [[TMP10:%.*]] = fneg fast float [[TMP9]]
3940; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])
3941; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP9]] to i32
3942; CHECK-NEXT:    [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])
3943; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])
3944; CHECK-NEXT:    [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]
3945; CHECK-NEXT:    [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 0
3946; CHECK-NEXT:    [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]
3947; CHECK-NEXT:    [[TMP18:%.*]] = mul i32 [[TMP17]], [[TMP4]]
3948; CHECK-NEXT:    [[TMP19:%.*]] = sub i32 [[TMP3]], [[TMP18]]
3949; CHECK-NEXT:    [[TMP20:%.*]] = and i32 [[TMP19]], 65535
3950; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i16
3951; CHECK-NEXT:    [[TMP22:%.*]] = insertelement <3 x i16> undef, i16 [[TMP21]], i64 0
3952; CHECK-NEXT:    [[TMP23:%.*]] = extractelement <3 x i16> [[X]], i64 1
3953; CHECK-NEXT:    [[TMP24:%.*]] = extractelement <3 x i16> [[Y]], i64 1
3954; CHECK-NEXT:    [[TMP25:%.*]] = zext i16 [[TMP23]] to i32
3955; CHECK-NEXT:    [[TMP26:%.*]] = zext i16 [[TMP24]] to i32
3956; CHECK-NEXT:    [[TMP27:%.*]] = uitofp i32 [[TMP25]] to float
3957; CHECK-NEXT:    [[TMP28:%.*]] = uitofp i32 [[TMP26]] to float
3958; CHECK-NEXT:    [[TMP29:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP28]])
3959; CHECK-NEXT:    [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]]
3960; CHECK-NEXT:    [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]])
3961; CHECK-NEXT:    [[TMP32:%.*]] = fneg fast float [[TMP31]]
3962; CHECK-NEXT:    [[TMP33:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP32]], float [[TMP28]], float [[TMP27]])
3963; CHECK-NEXT:    [[TMP34:%.*]] = fptoui float [[TMP31]] to i32
3964; CHECK-NEXT:    [[TMP35:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
3965; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.fabs.f32(float [[TMP28]])
3966; CHECK-NEXT:    [[TMP37:%.*]] = fcmp fast oge float [[TMP35]], [[TMP36]]
3967; CHECK-NEXT:    [[TMP38:%.*]] = select i1 [[TMP37]], i32 1, i32 0
3968; CHECK-NEXT:    [[TMP39:%.*]] = add i32 [[TMP34]], [[TMP38]]
3969; CHECK-NEXT:    [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP26]]
3970; CHECK-NEXT:    [[TMP41:%.*]] = sub i32 [[TMP25]], [[TMP40]]
3971; CHECK-NEXT:    [[TMP42:%.*]] = and i32 [[TMP41]], 65535
3972; CHECK-NEXT:    [[TMP43:%.*]] = trunc i32 [[TMP42]] to i16
3973; CHECK-NEXT:    [[TMP44:%.*]] = insertelement <3 x i16> [[TMP22]], i16 [[TMP43]], i64 1
3974; CHECK-NEXT:    [[TMP45:%.*]] = extractelement <3 x i16> [[X]], i64 2
3975; CHECK-NEXT:    [[TMP46:%.*]] = extractelement <3 x i16> [[Y]], i64 2
3976; CHECK-NEXT:    [[TMP47:%.*]] = zext i16 [[TMP45]] to i32
3977; CHECK-NEXT:    [[TMP48:%.*]] = zext i16 [[TMP46]] to i32
3978; CHECK-NEXT:    [[TMP49:%.*]] = uitofp i32 [[TMP47]] to float
3979; CHECK-NEXT:    [[TMP50:%.*]] = uitofp i32 [[TMP48]] to float
3980; CHECK-NEXT:    [[TMP51:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP50]])
3981; CHECK-NEXT:    [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]]
3982; CHECK-NEXT:    [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]])
3983; CHECK-NEXT:    [[TMP54:%.*]] = fneg fast float [[TMP53]]
3984; CHECK-NEXT:    [[TMP55:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP54]], float [[TMP50]], float [[TMP49]])
3985; CHECK-NEXT:    [[TMP56:%.*]] = fptoui float [[TMP53]] to i32
3986; CHECK-NEXT:    [[TMP57:%.*]] = call fast float @llvm.fabs.f32(float [[TMP55]])
3987; CHECK-NEXT:    [[TMP58:%.*]] = call fast float @llvm.fabs.f32(float [[TMP50]])
3988; CHECK-NEXT:    [[TMP59:%.*]] = fcmp fast oge float [[TMP57]], [[TMP58]]
3989; CHECK-NEXT:    [[TMP60:%.*]] = select i1 [[TMP59]], i32 1, i32 0
3990; CHECK-NEXT:    [[TMP61:%.*]] = add i32 [[TMP56]], [[TMP60]]
3991; CHECK-NEXT:    [[TMP62:%.*]] = mul i32 [[TMP61]], [[TMP48]]
3992; CHECK-NEXT:    [[TMP63:%.*]] = sub i32 [[TMP47]], [[TMP62]]
3993; CHECK-NEXT:    [[TMP64:%.*]] = and i32 [[TMP63]], 65535
3994; CHECK-NEXT:    [[TMP65:%.*]] = trunc i32 [[TMP64]] to i16
3995; CHECK-NEXT:    [[TMP66:%.*]] = insertelement <3 x i16> [[TMP44]], i16 [[TMP65]], i64 2
3996; CHECK-NEXT:    store <3 x i16> [[TMP66]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8
3997; CHECK-NEXT:    ret void
3998;
3999; GFX6-LABEL: urem_v3i16:
4000; GFX6:       ; %bb.0:
4001; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
4002; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
4003; GFX6-NEXT:    s_mov_b32 s8, 0xffff
4004; GFX6-NEXT:    s_mov_b32 s3, 0xf000
4005; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
4006; GFX6-NEXT:    s_and_b32 s9, s6, s8
4007; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s9
4008; GFX6-NEXT:    s_and_b32 s2, s4, s8
4009; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s2
4010; GFX6-NEXT:    v_mov_b32_e32 v2, s6
4011; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v0
4012; GFX6-NEXT:    v_alignbit_b32 v2, s7, v2, 16
4013; GFX6-NEXT:    v_and_b32_e32 v5, s8, v2
4014; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, v5
4015; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
4016; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
4017; GFX6-NEXT:    v_cvt_u32_f32_e32 v6, v4
4018; GFX6-NEXT:    v_mad_f32 v3, -v4, v0, v3
4019; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v0
4020; GFX6-NEXT:    v_mov_b32_e32 v1, s4
4021; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v6, vcc
4022; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s6
4023; GFX6-NEXT:    v_alignbit_b32 v1, s5, v1, 16
4024; GFX6-NEXT:    v_and_b32_e32 v3, s8, v1
4025; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, v3
4026; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v5
4027; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
4028; GFX6-NEXT:    s_and_b32 s4, s7, s8
4029; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s4
4030; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
4031; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
4032; GFX6-NEXT:    v_mad_f32 v3, -v4, v5, v3
4033; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
4034; GFX6-NEXT:    s_and_b32 s4, s5, s8
4035; GFX6-NEXT:    v_cvt_f32_u32_e32 v7, s4
4036; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v6
4037; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v5
4038; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
4039; GFX6-NEXT:    v_mul_lo_u32 v2, v3, v2
4040; GFX6-NEXT:    v_mul_f32_e32 v3, v7, v8
4041; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
4042; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v3
4043; GFX6-NEXT:    v_mad_f32 v3, -v3, v6, v7
4044; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v6
4045; GFX6-NEXT:    s_mov_b32 s2, -1
4046; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
4047; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s7
4048; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v2
4049; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
4050; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s5, v3
4051; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
4052; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
4053; GFX6-NEXT:    buffer_store_short v2, off, s[0:3], 0 offset:4
4054; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
4055; GFX6-NEXT:    s_endpgm
4056;
4057; GFX9-LABEL: urem_v3i16:
4058; GFX9:       ; %bb.0:
4059; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
4060; GFX9-NEXT:    s_mov_b32 s2, 0xffff
4061; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
4062; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
4063; GFX9-NEXT:    s_and_b32 s8, s6, s2
4064; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
4065; GFX9-NEXT:    s_and_b32 s3, s4, s2
4066; GFX9-NEXT:    s_lshr_b32 s6, s6, 16
4067; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s6
4068; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, s3
4069; GFX9-NEXT:    v_rcp_iflag_f32_e32 v4, v0
4070; GFX9-NEXT:    s_lshr_b32 s4, s4, 16
4071; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, s4
4072; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v1
4073; GFX9-NEXT:    v_mul_f32_e32 v4, v2, v4
4074; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
4075; GFX9-NEXT:    s_and_b32 s7, s7, s2
4076; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v4
4077; GFX9-NEXT:    v_mad_f32 v2, -v4, v0, v2
4078; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s7
4079; GFX9-NEXT:    v_mul_f32_e32 v5, v3, v5
4080; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v0
4081; GFX9-NEXT:    v_trunc_f32_e32 v2, v5
4082; GFX9-NEXT:    s_and_b32 s2, s5, s2
4083; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v6, vcc
4084; GFX9-NEXT:    v_mad_f32 v3, -v2, v1, v3
4085; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
4086; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s2
4087; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v4
4088; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v1
4089; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
4090; GFX9-NEXT:    v_mul_f32_e32 v2, v5, v6
4091; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
4092; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v2
4093; GFX9-NEXT:    v_mad_f32 v2, -v2, v4, v5
4094; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
4095; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s8
4096; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v3, vcc
4097; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s6
4098; GFX9-NEXT:    v_mul_lo_u32 v2, v2, s7
4099; GFX9-NEXT:    v_sub_u32_e32 v0, s3, v0
4100; GFX9-NEXT:    v_mov_b32_e32 v3, 0
4101; GFX9-NEXT:    v_sub_u32_e32 v1, s4, v1
4102; GFX9-NEXT:    v_sub_u32_e32 v2, s2, v2
4103; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v0
4104; GFX9-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
4105; GFX9-NEXT:    global_store_short v3, v2, s[0:1] offset:4
4106; GFX9-NEXT:    global_store_dword v3, v0, s[0:1]
4107; GFX9-NEXT:    s_endpgm
4108  %r = urem <3 x i16> %x, %y
4109  store <3 x i16> %r, <3 x i16> addrspace(1)* %out
4110  ret void
4111}
4112
4113define amdgpu_kernel void @sdiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x, <3 x i16> %y) {
4114; CHECK-LABEL: @sdiv_v3i16(
4115; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i16> [[X:%.*]], i64 0
4116; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i16> [[Y:%.*]], i64 0
4117; CHECK-NEXT:    [[TMP3:%.*]] = sext i16 [[TMP1]] to i32
4118; CHECK-NEXT:    [[TMP4:%.*]] = sext i16 [[TMP2]] to i32
4119; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
4120; CHECK-NEXT:    [[TMP6:%.*]] = ashr i32 [[TMP5]], 30
4121; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], 1
4122; CHECK-NEXT:    [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float
4123; CHECK-NEXT:    [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float
4124; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
4125; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]
4126; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])
4127; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
4128; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
4129; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
4130; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
4131; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
4132; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
4133; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
4134; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
4135; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 16
4136; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 16
4137; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i16
4138; CHECK-NEXT:    [[TMP24:%.*]] = insertelement <3 x i16> undef, i16 [[TMP23]], i64 0
4139; CHECK-NEXT:    [[TMP25:%.*]] = extractelement <3 x i16> [[X]], i64 1
4140; CHECK-NEXT:    [[TMP26:%.*]] = extractelement <3 x i16> [[Y]], i64 1
4141; CHECK-NEXT:    [[TMP27:%.*]] = sext i16 [[TMP25]] to i32
4142; CHECK-NEXT:    [[TMP28:%.*]] = sext i16 [[TMP26]] to i32
4143; CHECK-NEXT:    [[TMP29:%.*]] = xor i32 [[TMP27]], [[TMP28]]
4144; CHECK-NEXT:    [[TMP30:%.*]] = ashr i32 [[TMP29]], 30
4145; CHECK-NEXT:    [[TMP31:%.*]] = or i32 [[TMP30]], 1
4146; CHECK-NEXT:    [[TMP32:%.*]] = sitofp i32 [[TMP27]] to float
4147; CHECK-NEXT:    [[TMP33:%.*]] = sitofp i32 [[TMP28]] to float
4148; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])
4149; CHECK-NEXT:    [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]]
4150; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]])
4151; CHECK-NEXT:    [[TMP37:%.*]] = fneg fast float [[TMP36]]
4152; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]])
4153; CHECK-NEXT:    [[TMP39:%.*]] = fptosi float [[TMP36]] to i32
4154; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]])
4155; CHECK-NEXT:    [[TMP41:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
4156; CHECK-NEXT:    [[TMP42:%.*]] = fcmp fast oge float [[TMP40]], [[TMP41]]
4157; CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP31]], i32 0
4158; CHECK-NEXT:    [[TMP44:%.*]] = add i32 [[TMP39]], [[TMP43]]
4159; CHECK-NEXT:    [[TMP45:%.*]] = shl i32 [[TMP44]], 16
4160; CHECK-NEXT:    [[TMP46:%.*]] = ashr i32 [[TMP45]], 16
4161; CHECK-NEXT:    [[TMP47:%.*]] = trunc i32 [[TMP46]] to i16
4162; CHECK-NEXT:    [[TMP48:%.*]] = insertelement <3 x i16> [[TMP24]], i16 [[TMP47]], i64 1
4163; CHECK-NEXT:    [[TMP49:%.*]] = extractelement <3 x i16> [[X]], i64 2
4164; CHECK-NEXT:    [[TMP50:%.*]] = extractelement <3 x i16> [[Y]], i64 2
4165; CHECK-NEXT:    [[TMP51:%.*]] = sext i16 [[TMP49]] to i32
4166; CHECK-NEXT:    [[TMP52:%.*]] = sext i16 [[TMP50]] to i32
4167; CHECK-NEXT:    [[TMP53:%.*]] = xor i32 [[TMP51]], [[TMP52]]
4168; CHECK-NEXT:    [[TMP54:%.*]] = ashr i32 [[TMP53]], 30
4169; CHECK-NEXT:    [[TMP55:%.*]] = or i32 [[TMP54]], 1
4170; CHECK-NEXT:    [[TMP56:%.*]] = sitofp i32 [[TMP51]] to float
4171; CHECK-NEXT:    [[TMP57:%.*]] = sitofp i32 [[TMP52]] to float
4172; CHECK-NEXT:    [[TMP58:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP57]])
4173; CHECK-NEXT:    [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]]
4174; CHECK-NEXT:    [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]])
4175; CHECK-NEXT:    [[TMP61:%.*]] = fneg fast float [[TMP60]]
4176; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]])
4177; CHECK-NEXT:    [[TMP63:%.*]] = fptosi float [[TMP60]] to i32
4178; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]])
4179; CHECK-NEXT:    [[TMP65:%.*]] = call fast float @llvm.fabs.f32(float [[TMP57]])
4180; CHECK-NEXT:    [[TMP66:%.*]] = fcmp fast oge float [[TMP64]], [[TMP65]]
4181; CHECK-NEXT:    [[TMP67:%.*]] = select i1 [[TMP66]], i32 [[TMP55]], i32 0
4182; CHECK-NEXT:    [[TMP68:%.*]] = add i32 [[TMP63]], [[TMP67]]
4183; CHECK-NEXT:    [[TMP69:%.*]] = shl i32 [[TMP68]], 16
4184; CHECK-NEXT:    [[TMP70:%.*]] = ashr i32 [[TMP69]], 16
4185; CHECK-NEXT:    [[TMP71:%.*]] = trunc i32 [[TMP70]] to i16
4186; CHECK-NEXT:    [[TMP72:%.*]] = insertelement <3 x i16> [[TMP48]], i16 [[TMP71]], i64 2
4187; CHECK-NEXT:    store <3 x i16> [[TMP72]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8
4188; CHECK-NEXT:    ret void
4189;
4190; GFX6-LABEL: sdiv_v3i16:
4191; GFX6:       ; %bb.0:
4192; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
4193; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
4194; GFX6-NEXT:    s_mov_b32 s3, 0xf000
4195; GFX6-NEXT:    s_mov_b32 s2, -1
4196; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
4197; GFX6-NEXT:    s_sext_i32_i16 s8, s6
4198; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s8
4199; GFX6-NEXT:    s_sext_i32_i16 s9, s4
4200; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s9
4201; GFX6-NEXT:    s_xor_b32 s8, s9, s8
4202; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
4203; GFX6-NEXT:    s_ashr_i32 s6, s6, 16
4204; GFX6-NEXT:    s_ashr_i32 s8, s8, 30
4205; GFX6-NEXT:    s_or_b32 s8, s8, 1
4206; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
4207; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
4208; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
4209; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
4210; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
4211; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s6
4212; GFX6-NEXT:    v_mov_b32_e32 v3, s8
4213; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
4214; GFX6-NEXT:    s_ashr_i32 s4, s4, 16
4215; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
4216; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s4
4217; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v1
4218; GFX6-NEXT:    s_xor_b32 s4, s4, s6
4219; GFX6-NEXT:    s_ashr_i32 s4, s4, 30
4220; GFX6-NEXT:    s_or_b32 s4, s4, 1
4221; GFX6-NEXT:    v_mul_f32_e32 v3, v2, v3
4222; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
4223; GFX6-NEXT:    v_mad_f32 v2, -v3, v1, v2
4224; GFX6-NEXT:    v_mov_b32_e32 v4, s4
4225; GFX6-NEXT:    s_sext_i32_i16 s4, s7
4226; GFX6-NEXT:    v_cvt_i32_f32_e32 v3, v3
4227; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
4228; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s4
4229; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
4230; GFX6-NEXT:    s_sext_i32_i16 s5, s5
4231; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
4232; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s5
4233; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
4234; GFX6-NEXT:    s_xor_b32 s4, s5, s4
4235; GFX6-NEXT:    s_ashr_i32 s4, s4, 30
4236; GFX6-NEXT:    s_or_b32 s4, s4, 1
4237; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
4238; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
4239; GFX6-NEXT:    v_mad_f32 v3, -v4, v2, v3
4240; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v4
4241; GFX6-NEXT:    v_mov_b32_e32 v5, s4
4242; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
4243; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
4244; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
4245; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
4246; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0
4247; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
4248; GFX6-NEXT:    buffer_store_short v2, off, s[0:3], 0 offset:4
4249; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
4250; GFX6-NEXT:    s_endpgm
4251;
4252; GFX9-LABEL: sdiv_v3i16:
4253; GFX9:       ; %bb.0:
4254; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
4255; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
4256; GFX9-NEXT:    v_mov_b32_e32 v1, 0
4257; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
4258; GFX9-NEXT:    s_sext_i32_i16 s0, s6
4259; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s0
4260; GFX9-NEXT:    s_sext_i32_i16 s1, s4
4261; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s1
4262; GFX9-NEXT:    s_xor_b32 s0, s1, s0
4263; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
4264; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
4265; GFX9-NEXT:    s_or_b32 s8, s0, 1
4266; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
4267; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
4268; GFX9-NEXT:    v_mad_f32 v2, -v3, v0, v2
4269; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
4270; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
4271; GFX9-NEXT:    s_cselect_b32 s0, s8, 0
4272; GFX9-NEXT:    s_ashr_i32 s1, s6, 16
4273; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
4274; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s1
4275; GFX9-NEXT:    s_ashr_i32 s4, s4, 16
4276; GFX9-NEXT:    v_add_u32_e32 v2, s0, v3
4277; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s4
4278; GFX9-NEXT:    v_rcp_iflag_f32_e32 v4, v0
4279; GFX9-NEXT:    s_xor_b32 s0, s4, s1
4280; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
4281; GFX9-NEXT:    s_or_b32 s4, s0, 1
4282; GFX9-NEXT:    v_mul_f32_e32 v4, v3, v4
4283; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
4284; GFX9-NEXT:    v_mad_f32 v3, -v4, v0, v3
4285; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v3|, |v0|
4286; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
4287; GFX9-NEXT:    v_cvt_i32_f32_e32 v4, v4
4288; GFX9-NEXT:    s_sext_i32_i16 s1, s7
4289; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s1
4290; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
4291; GFX9-NEXT:    v_add_u32_e32 v3, s0, v4
4292; GFX9-NEXT:    s_sext_i32_i16 s0, s5
4293; GFX9-NEXT:    v_cvt_f32_i32_e32 v4, s0
4294; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v0
4295; GFX9-NEXT:    s_xor_b32 s0, s0, s1
4296; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
4297; GFX9-NEXT:    s_or_b32 s4, s0, 1
4298; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
4299; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
4300; GFX9-NEXT:    v_mad_f32 v4, -v5, v0, v4
4301; GFX9-NEXT:    v_cvt_i32_f32_e32 v5, v5
4302; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v4|, |v0|
4303; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
4304; GFX9-NEXT:    s_cselect_b32 s0, s4, 0
4305; GFX9-NEXT:    v_add_u32_e32 v0, s0, v5
4306; GFX9-NEXT:    v_and_b32_e32 v2, 0xffff, v2
4307; GFX9-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
4308; GFX9-NEXT:    global_store_short v1, v0, s[2:3] offset:4
4309; GFX9-NEXT:    global_store_dword v1, v2, s[2:3]
4310; GFX9-NEXT:    s_endpgm
4311  %r = sdiv <3 x i16> %x, %y
4312  store <3 x i16> %r, <3 x i16> addrspace(1)* %out
4313  ret void
4314}
4315
4316define amdgpu_kernel void @srem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x, <3 x i16> %y) {
4317; CHECK-LABEL: @srem_v3i16(
4318; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i16> [[X:%.*]], i64 0
4319; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i16> [[Y:%.*]], i64 0
4320; CHECK-NEXT:    [[TMP3:%.*]] = sext i16 [[TMP1]] to i32
4321; CHECK-NEXT:    [[TMP4:%.*]] = sext i16 [[TMP2]] to i32
4322; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
4323; CHECK-NEXT:    [[TMP6:%.*]] = ashr i32 [[TMP5]], 30
4324; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], 1
4325; CHECK-NEXT:    [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float
4326; CHECK-NEXT:    [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float
4327; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
4328; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]
4329; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])
4330; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
4331; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
4332; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
4333; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
4334; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
4335; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
4336; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
4337; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
4338; CHECK-NEXT:    [[TMP21:%.*]] = mul i32 [[TMP20]], [[TMP4]]
4339; CHECK-NEXT:    [[TMP22:%.*]] = sub i32 [[TMP3]], [[TMP21]]
4340; CHECK-NEXT:    [[TMP23:%.*]] = shl i32 [[TMP22]], 16
4341; CHECK-NEXT:    [[TMP24:%.*]] = ashr i32 [[TMP23]], 16
4342; CHECK-NEXT:    [[TMP25:%.*]] = trunc i32 [[TMP24]] to i16
4343; CHECK-NEXT:    [[TMP26:%.*]] = insertelement <3 x i16> undef, i16 [[TMP25]], i64 0
4344; CHECK-NEXT:    [[TMP27:%.*]] = extractelement <3 x i16> [[X]], i64 1
4345; CHECK-NEXT:    [[TMP28:%.*]] = extractelement <3 x i16> [[Y]], i64 1
4346; CHECK-NEXT:    [[TMP29:%.*]] = sext i16 [[TMP27]] to i32
4347; CHECK-NEXT:    [[TMP30:%.*]] = sext i16 [[TMP28]] to i32
4348; CHECK-NEXT:    [[TMP31:%.*]] = xor i32 [[TMP29]], [[TMP30]]
4349; CHECK-NEXT:    [[TMP32:%.*]] = ashr i32 [[TMP31]], 30
4350; CHECK-NEXT:    [[TMP33:%.*]] = or i32 [[TMP32]], 1
4351; CHECK-NEXT:    [[TMP34:%.*]] = sitofp i32 [[TMP29]] to float
4352; CHECK-NEXT:    [[TMP35:%.*]] = sitofp i32 [[TMP30]] to float
4353; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])
4354; CHECK-NEXT:    [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]]
4355; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]])
4356; CHECK-NEXT:    [[TMP39:%.*]] = fneg fast float [[TMP38]]
4357; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]])
4358; CHECK-NEXT:    [[TMP41:%.*]] = fptosi float [[TMP38]] to i32
4359; CHECK-NEXT:    [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]])
4360; CHECK-NEXT:    [[TMP43:%.*]] = call fast float @llvm.fabs.f32(float [[TMP35]])
4361; CHECK-NEXT:    [[TMP44:%.*]] = fcmp fast oge float [[TMP42]], [[TMP43]]
4362; CHECK-NEXT:    [[TMP45:%.*]] = select i1 [[TMP44]], i32 [[TMP33]], i32 0
4363; CHECK-NEXT:    [[TMP46:%.*]] = add i32 [[TMP41]], [[TMP45]]
4364; CHECK-NEXT:    [[TMP47:%.*]] = mul i32 [[TMP46]], [[TMP30]]
4365; CHECK-NEXT:    [[TMP48:%.*]] = sub i32 [[TMP29]], [[TMP47]]
4366; CHECK-NEXT:    [[TMP49:%.*]] = shl i32 [[TMP48]], 16
4367; CHECK-NEXT:    [[TMP50:%.*]] = ashr i32 [[TMP49]], 16
4368; CHECK-NEXT:    [[TMP51:%.*]] = trunc i32 [[TMP50]] to i16
4369; CHECK-NEXT:    [[TMP52:%.*]] = insertelement <3 x i16> [[TMP26]], i16 [[TMP51]], i64 1
4370; CHECK-NEXT:    [[TMP53:%.*]] = extractelement <3 x i16> [[X]], i64 2
4371; CHECK-NEXT:    [[TMP54:%.*]] = extractelement <3 x i16> [[Y]], i64 2
4372; CHECK-NEXT:    [[TMP55:%.*]] = sext i16 [[TMP53]] to i32
4373; CHECK-NEXT:    [[TMP56:%.*]] = sext i16 [[TMP54]] to i32
4374; CHECK-NEXT:    [[TMP57:%.*]] = xor i32 [[TMP55]], [[TMP56]]
4375; CHECK-NEXT:    [[TMP58:%.*]] = ashr i32 [[TMP57]], 30
4376; CHECK-NEXT:    [[TMP59:%.*]] = or i32 [[TMP58]], 1
4377; CHECK-NEXT:    [[TMP60:%.*]] = sitofp i32 [[TMP55]] to float
4378; CHECK-NEXT:    [[TMP61:%.*]] = sitofp i32 [[TMP56]] to float
4379; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP61]])
4380; CHECK-NEXT:    [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]]
4381; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]])
4382; CHECK-NEXT:    [[TMP65:%.*]] = fneg fast float [[TMP64]]
4383; CHECK-NEXT:    [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]])
4384; CHECK-NEXT:    [[TMP67:%.*]] = fptosi float [[TMP64]] to i32
4385; CHECK-NEXT:    [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]])
4386; CHECK-NEXT:    [[TMP69:%.*]] = call fast float @llvm.fabs.f32(float [[TMP61]])
4387; CHECK-NEXT:    [[TMP70:%.*]] = fcmp fast oge float [[TMP68]], [[TMP69]]
4388; CHECK-NEXT:    [[TMP71:%.*]] = select i1 [[TMP70]], i32 [[TMP59]], i32 0
4389; CHECK-NEXT:    [[TMP72:%.*]] = add i32 [[TMP67]], [[TMP71]]
4390; CHECK-NEXT:    [[TMP73:%.*]] = mul i32 [[TMP72]], [[TMP56]]
4391; CHECK-NEXT:    [[TMP74:%.*]] = sub i32 [[TMP55]], [[TMP73]]
4392; CHECK-NEXT:    [[TMP75:%.*]] = shl i32 [[TMP74]], 16
4393; CHECK-NEXT:    [[TMP76:%.*]] = ashr i32 [[TMP75]], 16
4394; CHECK-NEXT:    [[TMP77:%.*]] = trunc i32 [[TMP76]] to i16
4395; CHECK-NEXT:    [[TMP78:%.*]] = insertelement <3 x i16> [[TMP52]], i16 [[TMP77]], i64 2
4396; CHECK-NEXT:    store <3 x i16> [[TMP78]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8
4397; CHECK-NEXT:    ret void
4398;
4399; GFX6-LABEL: srem_v3i16:
4400; GFX6:       ; %bb.0:
4401; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
4402; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
4403; GFX6-NEXT:    s_mov_b32 s3, 0xf000
4404; GFX6-NEXT:    s_mov_b32 s2, -1
4405; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
4406; GFX6-NEXT:    s_sext_i32_i16 s8, s6
4407; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s8
4408; GFX6-NEXT:    s_sext_i32_i16 s9, s4
4409; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s9
4410; GFX6-NEXT:    s_xor_b32 s8, s9, s8
4411; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
4412; GFX6-NEXT:    s_ashr_i32 s8, s8, 30
4413; GFX6-NEXT:    s_or_b32 s8, s8, 1
4414; GFX6-NEXT:    v_mov_b32_e32 v3, s8
4415; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
4416; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
4417; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
4418; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
4419; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
4420; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
4421; GFX6-NEXT:    v_mov_b32_e32 v1, s4
4422; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
4423; GFX6-NEXT:    v_mov_b32_e32 v2, s6
4424; GFX6-NEXT:    v_alignbit_b32 v2, s7, v2, 16
4425; GFX6-NEXT:    v_bfe_i32 v3, v2, 0, 16
4426; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, v3
4427; GFX6-NEXT:    v_alignbit_b32 v1, s5, v1, 16
4428; GFX6-NEXT:    v_bfe_i32 v5, v1, 0, 16
4429; GFX6-NEXT:    v_cvt_f32_i32_e32 v6, v5
4430; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v4
4431; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s6
4432; GFX6-NEXT:    v_xor_b32_e32 v3, v5, v3
4433; GFX6-NEXT:    v_ashrrev_i32_e32 v3, 30, v3
4434; GFX6-NEXT:    v_mul_f32_e32 v5, v6, v7
4435; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
4436; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
4437; GFX6-NEXT:    v_mad_f32 v6, -v5, v4, v6
4438; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
4439; GFX6-NEXT:    s_sext_i32_i16 s4, s7
4440; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, |v4|
4441; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s4
4442; GFX6-NEXT:    v_or_b32_e32 v3, 1, v3
4443; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
4444; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
4445; GFX6-NEXT:    s_sext_i32_i16 s6, s5
4446; GFX6-NEXT:    v_mul_lo_u32 v2, v3, v2
4447; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s6
4448; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v4
4449; GFX6-NEXT:    s_xor_b32 s4, s6, s4
4450; GFX6-NEXT:    s_ashr_i32 s4, s4, 30
4451; GFX6-NEXT:    s_or_b32 s4, s4, 1
4452; GFX6-NEXT:    v_mul_f32_e32 v5, v3, v5
4453; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
4454; GFX6-NEXT:    v_mad_f32 v3, -v5, v4, v3
4455; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
4456; GFX6-NEXT:    v_mov_b32_e32 v6, s4
4457; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v4|
4458; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v6, vcc
4459; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
4460; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s7
4461; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v2
4462; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
4463; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s5, v3
4464; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0
4465; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
4466; GFX6-NEXT:    buffer_store_short v2, off, s[0:3], 0 offset:4
4467; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
4468; GFX6-NEXT:    s_endpgm
4469;
4470; GFX9-LABEL: srem_v3i16:
4471; GFX9:       ; %bb.0:
4472; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
4473; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
4474; GFX9-NEXT:    s_sext_i32_i16 s8, s6
4475; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s8
4476; GFX9-NEXT:    s_sext_i32_i16 s9, s4
4477; GFX9-NEXT:    v_cvt_f32_i32_e32 v1, s9
4478; GFX9-NEXT:    s_xor_b32 s2, s9, s8
4479; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
4480; GFX9-NEXT:    s_ashr_i32 s2, s2, 30
4481; GFX9-NEXT:    s_or_b32 s10, s2, 1
4482; GFX9-NEXT:    s_sext_i32_i16 s7, s7
4483; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
4484; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
4485; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
4486; GFX9-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|
4487; GFX9-NEXT:    s_and_b64 s[2:3], s[2:3], exec
4488; GFX9-NEXT:    s_cselect_b32 s2, s10, 0
4489; GFX9-NEXT:    s_ashr_i32 s6, s6, 16
4490; GFX9-NEXT:    v_cvt_i32_f32_e32 v2, v2
4491; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s6
4492; GFX9-NEXT:    s_ashr_i32 s4, s4, 16
4493; GFX9-NEXT:    s_sext_i32_i16 s5, s5
4494; GFX9-NEXT:    v_add_u32_e32 v1, s2, v2
4495; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s4
4496; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
4497; GFX9-NEXT:    s_xor_b32 s2, s4, s6
4498; GFX9-NEXT:    s_ashr_i32 s2, s2, 30
4499; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s8
4500; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
4501; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
4502; GFX9-NEXT:    v_mad_f32 v2, -v3, v0, v2
4503; GFX9-NEXT:    s_or_b32 s8, s2, 1
4504; GFX9-NEXT:    v_cvt_i32_f32_e32 v3, v3
4505; GFX9-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v2|, |v0|
4506; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s7
4507; GFX9-NEXT:    s_and_b64 s[2:3], s[2:3], exec
4508; GFX9-NEXT:    s_cselect_b32 s2, s8, 0
4509; GFX9-NEXT:    v_add_u32_e32 v0, s2, v3
4510; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s5
4511; GFX9-NEXT:    v_rcp_iflag_f32_e32 v4, v2
4512; GFX9-NEXT:    s_xor_b32 s2, s5, s7
4513; GFX9-NEXT:    s_ashr_i32 s2, s2, 30
4514; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s6
4515; GFX9-NEXT:    v_mul_f32_e32 v4, v3, v4
4516; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
4517; GFX9-NEXT:    v_mad_f32 v3, -v4, v2, v3
4518; GFX9-NEXT:    v_cvt_i32_f32_e32 v4, v4
4519; GFX9-NEXT:    s_or_b32 s6, s2, 1
4520; GFX9-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v3|, |v2|
4521; GFX9-NEXT:    s_and_b64 s[2:3], s[2:3], exec
4522; GFX9-NEXT:    s_cselect_b32 s2, s6, 0
4523; GFX9-NEXT:    v_add_u32_e32 v2, s2, v4
4524; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
4525; GFX9-NEXT:    v_mul_lo_u32 v2, v2, s7
4526; GFX9-NEXT:    v_sub_u32_e32 v1, s9, v1
4527; GFX9-NEXT:    v_mov_b32_e32 v3, 0
4528; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
4529; GFX9-NEXT:    v_sub_u32_e32 v2, s5, v2
4530; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff, v1
4531; GFX9-NEXT:    v_lshl_or_b32 v0, v0, 16, v1
4532; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
4533; GFX9-NEXT:    global_store_short v3, v2, s[0:1] offset:4
4534; GFX9-NEXT:    global_store_dword v3, v0, s[0:1]
4535; GFX9-NEXT:    s_endpgm
4536  %r = srem <3 x i16> %x, %y
4537  store <3 x i16> %r, <3 x i16> addrspace(1)* %out
4538  ret void
4539}
4540
4541define amdgpu_kernel void @udiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x, <3 x i15> %y) {
4542; CHECK-LABEL: @udiv_v3i15(
4543; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i15> [[X:%.*]], i64 0
4544; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i15> [[Y:%.*]], i64 0
4545; CHECK-NEXT:    [[TMP3:%.*]] = zext i15 [[TMP1]] to i32
4546; CHECK-NEXT:    [[TMP4:%.*]] = zext i15 [[TMP2]] to i32
4547; CHECK-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float
4548; CHECK-NEXT:    [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float
4549; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])
4550; CHECK-NEXT:    [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]
4551; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])
4552; CHECK-NEXT:    [[TMP10:%.*]] = fneg fast float [[TMP9]]
4553; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])
4554; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP9]] to i32
4555; CHECK-NEXT:    [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])
4556; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])
4557; CHECK-NEXT:    [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]
4558; CHECK-NEXT:    [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 0
4559; CHECK-NEXT:    [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]
4560; CHECK-NEXT:    [[TMP18:%.*]] = and i32 [[TMP17]], 32767
4561; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i15
4562; CHECK-NEXT:    [[TMP20:%.*]] = insertelement <3 x i15> undef, i15 [[TMP19]], i64 0
4563; CHECK-NEXT:    [[TMP21:%.*]] = extractelement <3 x i15> [[X]], i64 1
4564; CHECK-NEXT:    [[TMP22:%.*]] = extractelement <3 x i15> [[Y]], i64 1
4565; CHECK-NEXT:    [[TMP23:%.*]] = zext i15 [[TMP21]] to i32
4566; CHECK-NEXT:    [[TMP24:%.*]] = zext i15 [[TMP22]] to i32
4567; CHECK-NEXT:    [[TMP25:%.*]] = uitofp i32 [[TMP23]] to float
4568; CHECK-NEXT:    [[TMP26:%.*]] = uitofp i32 [[TMP24]] to float
4569; CHECK-NEXT:    [[TMP27:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP26]])
4570; CHECK-NEXT:    [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]]
4571; CHECK-NEXT:    [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]])
4572; CHECK-NEXT:    [[TMP30:%.*]] = fneg fast float [[TMP29]]
4573; CHECK-NEXT:    [[TMP31:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP30]], float [[TMP26]], float [[TMP25]])
4574; CHECK-NEXT:    [[TMP32:%.*]] = fptoui float [[TMP29]] to i32
4575; CHECK-NEXT:    [[TMP33:%.*]] = call fast float @llvm.fabs.f32(float [[TMP31]])
4576; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.fabs.f32(float [[TMP26]])
4577; CHECK-NEXT:    [[TMP35:%.*]] = fcmp fast oge float [[TMP33]], [[TMP34]]
4578; CHECK-NEXT:    [[TMP36:%.*]] = select i1 [[TMP35]], i32 1, i32 0
4579; CHECK-NEXT:    [[TMP37:%.*]] = add i32 [[TMP32]], [[TMP36]]
4580; CHECK-NEXT:    [[TMP38:%.*]] = and i32 [[TMP37]], 32767
4581; CHECK-NEXT:    [[TMP39:%.*]] = trunc i32 [[TMP38]] to i15
4582; CHECK-NEXT:    [[TMP40:%.*]] = insertelement <3 x i15> [[TMP20]], i15 [[TMP39]], i64 1
4583; CHECK-NEXT:    [[TMP41:%.*]] = extractelement <3 x i15> [[X]], i64 2
4584; CHECK-NEXT:    [[TMP42:%.*]] = extractelement <3 x i15> [[Y]], i64 2
4585; CHECK-NEXT:    [[TMP43:%.*]] = zext i15 [[TMP41]] to i32
4586; CHECK-NEXT:    [[TMP44:%.*]] = zext i15 [[TMP42]] to i32
4587; CHECK-NEXT:    [[TMP45:%.*]] = uitofp i32 [[TMP43]] to float
4588; CHECK-NEXT:    [[TMP46:%.*]] = uitofp i32 [[TMP44]] to float
4589; CHECK-NEXT:    [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]])
4590; CHECK-NEXT:    [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]]
4591; CHECK-NEXT:    [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]])
4592; CHECK-NEXT:    [[TMP50:%.*]] = fneg fast float [[TMP49]]
4593; CHECK-NEXT:    [[TMP51:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP50]], float [[TMP46]], float [[TMP45]])
4594; CHECK-NEXT:    [[TMP52:%.*]] = fptoui float [[TMP49]] to i32
4595; CHECK-NEXT:    [[TMP53:%.*]] = call fast float @llvm.fabs.f32(float [[TMP51]])
4596; CHECK-NEXT:    [[TMP54:%.*]] = call fast float @llvm.fabs.f32(float [[TMP46]])
4597; CHECK-NEXT:    [[TMP55:%.*]] = fcmp fast oge float [[TMP53]], [[TMP54]]
4598; CHECK-NEXT:    [[TMP56:%.*]] = select i1 [[TMP55]], i32 1, i32 0
4599; CHECK-NEXT:    [[TMP57:%.*]] = add i32 [[TMP52]], [[TMP56]]
4600; CHECK-NEXT:    [[TMP58:%.*]] = and i32 [[TMP57]], 32767
4601; CHECK-NEXT:    [[TMP59:%.*]] = trunc i32 [[TMP58]] to i15
4602; CHECK-NEXT:    [[TMP60:%.*]] = insertelement <3 x i15> [[TMP40]], i15 [[TMP59]], i64 2
4603; CHECK-NEXT:    store <3 x i15> [[TMP60]], <3 x i15> addrspace(1)* [[OUT:%.*]], align 8
4604; CHECK-NEXT:    ret void
4605;
4606; GFX6-LABEL: udiv_v3i15:
4607; GFX6:       ; %bb.0:
4608; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
4609; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
4610; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
4611; GFX6-NEXT:    s_mov_b32 s7, 0xf000
4612; GFX6-NEXT:    s_mov_b32 s6, -1
4613; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
4614; GFX6-NEXT:    v_mov_b32_e32 v0, s2
4615; GFX6-NEXT:    v_alignbit_b32 v0, s3, v0, 30
4616; GFX6-NEXT:    s_movk_i32 s3, 0x7fff
4617; GFX6-NEXT:    s_and_b32 s9, s0, s3
4618; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
4619; GFX6-NEXT:    s_and_b32 s8, s2, s3
4620; GFX6-NEXT:    v_mov_b32_e32 v2, s0
4621; GFX6-NEXT:    s_bfe_u32 s0, s0, 0xf000f
4622; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s8
4623; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v1
4624; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s0
4625; GFX6-NEXT:    s_bfe_u32 s2, s2, 0xf000f
4626; GFX6-NEXT:    v_alignbit_b32 v2, s1, v2, 30
4627; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
4628; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s2
4629; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v5
4630; GFX6-NEXT:    v_and_b32_e32 v2, s3, v2
4631; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
4632; GFX6-NEXT:    v_mad_f32 v3, -v4, v1, v3
4633; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
4634; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, v2
4635; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v1
4636; GFX6-NEXT:    v_mul_f32_e32 v1, v6, v7
4637; GFX6-NEXT:    v_and_b32_e32 v0, s3, v0
4638; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
4639; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
4640; GFX6-NEXT:    v_mad_f32 v4, -v1, v5, v6
4641; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
4642; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, v0
4643; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v2
4644; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v5
4645; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
4646; GFX6-NEXT:    v_mul_f32_e32 v1, v0, v6
4647; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
4648; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v1
4649; GFX6-NEXT:    v_mad_f32 v0, -v1, v2, v0
4650; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, v2
4651; GFX6-NEXT:    v_and_b32_e32 v2, s3, v3
4652; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
4653; GFX6-NEXT:    v_and_b32_e32 v3, s3, v4
4654; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 30
4655; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
4656; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
4657; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
4658; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
4659; GFX6-NEXT:    s_waitcnt expcnt(0)
4660; GFX6-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
4661; GFX6-NEXT:    buffer_store_short v0, off, s[4:7], 0 offset:4
4662; GFX6-NEXT:    s_endpgm
4663;
4664; GFX9-LABEL: udiv_v3i15:
4665; GFX9:       ; %bb.0:
4666; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
4667; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
4668; GFX9-NEXT:    s_movk_i32 s6, 0x7fff
4669; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
4670; GFX9-NEXT:    v_mov_b32_e32 v2, 0
4671; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
4672; GFX9-NEXT:    v_mov_b32_e32 v0, s2
4673; GFX9-NEXT:    v_alignbit_b32 v0, s3, v0, 30
4674; GFX9-NEXT:    s_and_b32 s3, s2, s6
4675; GFX9-NEXT:    s_and_b32 s7, s0, s6
4676; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s7
4677; GFX9-NEXT:    v_mov_b32_e32 v3, s0
4678; GFX9-NEXT:    s_bfe_u32 s0, s0, 0xf000f
4679; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s3
4680; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v1
4681; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
4682; GFX9-NEXT:    s_bfe_u32 s2, s2, 0xf000f
4683; GFX9-NEXT:    v_alignbit_b32 v3, s1, v3, 30
4684; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
4685; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s2
4686; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v6
4687; GFX9-NEXT:    v_and_b32_e32 v3, s6, v3
4688; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
4689; GFX9-NEXT:    v_mad_f32 v4, -v5, v1, v4
4690; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
4691; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, v3
4692; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v1
4693; GFX9-NEXT:    v_mul_f32_e32 v1, v7, v8
4694; GFX9-NEXT:    v_and_b32_e32 v0, s6, v0
4695; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
4696; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
4697; GFX9-NEXT:    v_mad_f32 v5, -v1, v6, v7
4698; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
4699; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, v0
4700; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v3
4701; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v6
4702; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
4703; GFX9-NEXT:    v_mul_f32_e32 v1, v0, v7
4704; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
4705; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v1
4706; GFX9-NEXT:    v_mad_f32 v0, -v1, v3, v0
4707; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, v3
4708; GFX9-NEXT:    v_and_b32_e32 v3, s6, v4
4709; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v6, vcc
4710; GFX9-NEXT:    v_and_b32_e32 v4, s6, v5
4711; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 30, v[0:1]
4712; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 15, v4
4713; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
4714; GFX9-NEXT:    v_or_b32_e32 v0, v3, v0
4715; GFX9-NEXT:    global_store_dword v2, v0, s[4:5]
4716; GFX9-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
4717; GFX9-NEXT:    global_store_short v2, v0, s[4:5] offset:4
4718; GFX9-NEXT:    s_endpgm
4719  %r = udiv <3 x i15> %x, %y
4720  store <3 x i15> %r, <3 x i15> addrspace(1)* %out
4721  ret void
4722}
4723
4724define amdgpu_kernel void @urem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x, <3 x i15> %y) {
4725; CHECK-LABEL: @urem_v3i15(
4726; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i15> [[X:%.*]], i64 0
4727; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i15> [[Y:%.*]], i64 0
4728; CHECK-NEXT:    [[TMP3:%.*]] = zext i15 [[TMP1]] to i32
4729; CHECK-NEXT:    [[TMP4:%.*]] = zext i15 [[TMP2]] to i32
4730; CHECK-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float
4731; CHECK-NEXT:    [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float
4732; CHECK-NEXT:    [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])
4733; CHECK-NEXT:    [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]
4734; CHECK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])
4735; CHECK-NEXT:    [[TMP10:%.*]] = fneg fast float [[TMP9]]
4736; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])
4737; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP9]] to i32
4738; CHECK-NEXT:    [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])
4739; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])
4740; CHECK-NEXT:    [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]
4741; CHECK-NEXT:    [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 0
4742; CHECK-NEXT:    [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]
4743; CHECK-NEXT:    [[TMP18:%.*]] = mul i32 [[TMP17]], [[TMP4]]
4744; CHECK-NEXT:    [[TMP19:%.*]] = sub i32 [[TMP3]], [[TMP18]]
4745; CHECK-NEXT:    [[TMP20:%.*]] = and i32 [[TMP19]], 32767
4746; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i15
4747; CHECK-NEXT:    [[TMP22:%.*]] = insertelement <3 x i15> undef, i15 [[TMP21]], i64 0
4748; CHECK-NEXT:    [[TMP23:%.*]] = extractelement <3 x i15> [[X]], i64 1
4749; CHECK-NEXT:    [[TMP24:%.*]] = extractelement <3 x i15> [[Y]], i64 1
4750; CHECK-NEXT:    [[TMP25:%.*]] = zext i15 [[TMP23]] to i32
4751; CHECK-NEXT:    [[TMP26:%.*]] = zext i15 [[TMP24]] to i32
4752; CHECK-NEXT:    [[TMP27:%.*]] = uitofp i32 [[TMP25]] to float
4753; CHECK-NEXT:    [[TMP28:%.*]] = uitofp i32 [[TMP26]] to float
4754; CHECK-NEXT:    [[TMP29:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP28]])
4755; CHECK-NEXT:    [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]]
4756; CHECK-NEXT:    [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]])
4757; CHECK-NEXT:    [[TMP32:%.*]] = fneg fast float [[TMP31]]
4758; CHECK-NEXT:    [[TMP33:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP32]], float [[TMP28]], float [[TMP27]])
4759; CHECK-NEXT:    [[TMP34:%.*]] = fptoui float [[TMP31]] to i32
4760; CHECK-NEXT:    [[TMP35:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
4761; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.fabs.f32(float [[TMP28]])
4762; CHECK-NEXT:    [[TMP37:%.*]] = fcmp fast oge float [[TMP35]], [[TMP36]]
4763; CHECK-NEXT:    [[TMP38:%.*]] = select i1 [[TMP37]], i32 1, i32 0
4764; CHECK-NEXT:    [[TMP39:%.*]] = add i32 [[TMP34]], [[TMP38]]
4765; CHECK-NEXT:    [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP26]]
4766; CHECK-NEXT:    [[TMP41:%.*]] = sub i32 [[TMP25]], [[TMP40]]
4767; CHECK-NEXT:    [[TMP42:%.*]] = and i32 [[TMP41]], 32767
4768; CHECK-NEXT:    [[TMP43:%.*]] = trunc i32 [[TMP42]] to i15
4769; CHECK-NEXT:    [[TMP44:%.*]] = insertelement <3 x i15> [[TMP22]], i15 [[TMP43]], i64 1
4770; CHECK-NEXT:    [[TMP45:%.*]] = extractelement <3 x i15> [[X]], i64 2
4771; CHECK-NEXT:    [[TMP46:%.*]] = extractelement <3 x i15> [[Y]], i64 2
4772; CHECK-NEXT:    [[TMP47:%.*]] = zext i15 [[TMP45]] to i32
4773; CHECK-NEXT:    [[TMP48:%.*]] = zext i15 [[TMP46]] to i32
4774; CHECK-NEXT:    [[TMP49:%.*]] = uitofp i32 [[TMP47]] to float
4775; CHECK-NEXT:    [[TMP50:%.*]] = uitofp i32 [[TMP48]] to float
4776; CHECK-NEXT:    [[TMP51:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP50]])
4777; CHECK-NEXT:    [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]]
4778; CHECK-NEXT:    [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]])
4779; CHECK-NEXT:    [[TMP54:%.*]] = fneg fast float [[TMP53]]
4780; CHECK-NEXT:    [[TMP55:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP54]], float [[TMP50]], float [[TMP49]])
4781; CHECK-NEXT:    [[TMP56:%.*]] = fptoui float [[TMP53]] to i32
4782; CHECK-NEXT:    [[TMP57:%.*]] = call fast float @llvm.fabs.f32(float [[TMP55]])
4783; CHECK-NEXT:    [[TMP58:%.*]] = call fast float @llvm.fabs.f32(float [[TMP50]])
4784; CHECK-NEXT:    [[TMP59:%.*]] = fcmp fast oge float [[TMP57]], [[TMP58]]
4785; CHECK-NEXT:    [[TMP60:%.*]] = select i1 [[TMP59]], i32 1, i32 0
4786; CHECK-NEXT:    [[TMP61:%.*]] = add i32 [[TMP56]], [[TMP60]]
4787; CHECK-NEXT:    [[TMP62:%.*]] = mul i32 [[TMP61]], [[TMP48]]
4788; CHECK-NEXT:    [[TMP63:%.*]] = sub i32 [[TMP47]], [[TMP62]]
4789; CHECK-NEXT:    [[TMP64:%.*]] = and i32 [[TMP63]], 32767
4790; CHECK-NEXT:    [[TMP65:%.*]] = trunc i32 [[TMP64]] to i15
4791; CHECK-NEXT:    [[TMP66:%.*]] = insertelement <3 x i15> [[TMP44]], i15 [[TMP65]], i64 2
4792; CHECK-NEXT:    store <3 x i15> [[TMP66]], <3 x i15> addrspace(1)* [[OUT:%.*]], align 8
4793; CHECK-NEXT:    ret void
4794;
4795; GFX6-LABEL: urem_v3i15:
4796; GFX6:       ; %bb.0:
4797; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
4798; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
4799; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
4800; GFX6-NEXT:    s_mov_b32 s7, 0xf000
4801; GFX6-NEXT:    s_mov_b32 s6, -1
4802; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
4803; GFX6-NEXT:    v_mov_b32_e32 v0, s2
4804; GFX6-NEXT:    v_alignbit_b32 v0, s3, v0, 30
4805; GFX6-NEXT:    s_movk_i32 s3, 0x7fff
4806; GFX6-NEXT:    s_and_b32 s10, s0, s3
4807; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s10
4808; GFX6-NEXT:    s_and_b32 s9, s2, s3
4809; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s9
4810; GFX6-NEXT:    v_mov_b32_e32 v2, s0
4811; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v1
4812; GFX6-NEXT:    v_alignbit_b32 v2, s1, v2, 30
4813; GFX6-NEXT:    s_bfe_u32 s1, s0, 0xf000f
4814; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s1
4815; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
4816; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
4817; GFX6-NEXT:    v_mad_f32 v3, -v4, v1, v3
4818; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
4819; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v1
4820; GFX6-NEXT:    s_bfe_u32 s10, s2, 0xf000f
4821; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s10
4822; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v4, vcc
4823; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s0
4824; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v5
4825; GFX6-NEXT:    v_and_b32_e32 v2, s3, v2
4826; GFX6-NEXT:    v_and_b32_e32 v0, s3, v0
4827; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, s2, v1
4828; GFX6-NEXT:    v_mul_f32_e32 v1, v3, v4
4829; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, v2
4830; GFX6-NEXT:    v_cvt_f32_u32_e32 v7, v0
4831; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
4832; GFX6-NEXT:    v_mad_f32 v3, -v1, v5, v3
4833; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v4
4834; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
4835; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v5
4836; GFX6-NEXT:    s_lshr_b32 s0, s0, 15
4837; GFX6-NEXT:    v_mul_f32_e32 v3, v7, v8
4838; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
4839; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v3
4840; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
4841; GFX6-NEXT:    v_mad_f32 v3, -v3, v4, v7
4842; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v4
4843; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s0
4844; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
4845; GFX6-NEXT:    v_mul_lo_u32 v2, v3, v2
4846; GFX6-NEXT:    s_lshr_b32 s8, s2, 15
4847; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s8, v1
4848; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, v2, v0
4849; GFX6-NEXT:    v_and_b32_e32 v3, s3, v3
4850; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 30
4851; GFX6-NEXT:    v_and_b32_e32 v2, s3, v6
4852; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
4853; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
4854; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
4855; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
4856; GFX6-NEXT:    s_waitcnt expcnt(0)
4857; GFX6-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
4858; GFX6-NEXT:    buffer_store_short v0, off, s[4:7], 0 offset:4
4859; GFX6-NEXT:    s_endpgm
4860;
4861; GFX9-LABEL: urem_v3i15:
4862; GFX9:       ; %bb.0:
4863; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
4864; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
4865; GFX9-NEXT:    s_movk_i32 s6, 0x7fff
4866; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
4867; GFX9-NEXT:    v_mov_b32_e32 v2, 0
4868; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
4869; GFX9-NEXT:    v_mov_b32_e32 v0, s2
4870; GFX9-NEXT:    v_alignbit_b32 v0, s3, v0, 30
4871; GFX9-NEXT:    s_and_b32 s3, s2, s6
4872; GFX9-NEXT:    s_and_b32 s8, s0, s6
4873; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s8
4874; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s3
4875; GFX9-NEXT:    s_bfe_u32 s3, s0, 0xf000f
4876; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s3
4877; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v1
4878; GFX9-NEXT:    v_mov_b32_e32 v3, s0
4879; GFX9-NEXT:    v_alignbit_b32 v3, s1, v3, 30
4880; GFX9-NEXT:    s_bfe_u32 s7, s2, 0xf000f
4881; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
4882; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
4883; GFX9-NEXT:    v_mad_f32 v4, -v5, v1, v4
4884; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
4885; GFX9-NEXT:    v_and_b32_e32 v3, s6, v3
4886; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v1
4887; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s7
4888; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v6
4889; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v5, vcc
4890; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v3
4891; GFX9-NEXT:    v_and_b32_e32 v0, s6, v0
4892; GFX9-NEXT:    v_mul_f32_e32 v4, v7, v8
4893; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, v0
4894; GFX9-NEXT:    v_rcp_iflag_f32_e32 v9, v5
4895; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
4896; GFX9-NEXT:    v_mad_f32 v7, -v4, v6, v7
4897; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
4898; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v7|, v6
4899; GFX9-NEXT:    v_mul_f32_e32 v6, v8, v9
4900; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
4901; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v6
4902; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
4903; GFX9-NEXT:    v_mad_f32 v6, -v6, v5, v8
4904; GFX9-NEXT:    s_lshr_b32 s1, s0, 15
4905; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, v5
4906; GFX9-NEXT:    v_mul_lo_u32 v4, v4, s1
4907; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
4908; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s0
4909; GFX9-NEXT:    v_mul_lo_u32 v3, v5, v3
4910; GFX9-NEXT:    s_lshr_b32 s0, s2, 15
4911; GFX9-NEXT:    v_sub_u32_e32 v4, s0, v4
4912; GFX9-NEXT:    v_sub_u32_e32 v5, s2, v1
4913; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v3
4914; GFX9-NEXT:    v_and_b32_e32 v4, s6, v4
4915; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 30, v[0:1]
4916; GFX9-NEXT:    v_and_b32_e32 v3, s6, v5
4917; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 15, v4
4918; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
4919; GFX9-NEXT:    v_or_b32_e32 v0, v3, v0
4920; GFX9-NEXT:    global_store_dword v2, v0, s[4:5]
4921; GFX9-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
4922; GFX9-NEXT:    global_store_short v2, v0, s[4:5] offset:4
4923; GFX9-NEXT:    s_endpgm
4924  %r = urem <3 x i15> %x, %y
4925  store <3 x i15> %r, <3 x i15> addrspace(1)* %out
4926  ret void
4927}
4928
4929define amdgpu_kernel void @sdiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x, <3 x i15> %y) {
4930; CHECK-LABEL: @sdiv_v3i15(
4931; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i15> [[X:%.*]], i64 0
4932; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i15> [[Y:%.*]], i64 0
4933; CHECK-NEXT:    [[TMP3:%.*]] = sext i15 [[TMP1]] to i32
4934; CHECK-NEXT:    [[TMP4:%.*]] = sext i15 [[TMP2]] to i32
4935; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
4936; CHECK-NEXT:    [[TMP6:%.*]] = ashr i32 [[TMP5]], 30
4937; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], 1
4938; CHECK-NEXT:    [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float
4939; CHECK-NEXT:    [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float
4940; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
4941; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]
4942; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])
4943; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
4944; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
4945; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
4946; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
4947; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
4948; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
4949; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
4950; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
4951; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 17
4952; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 17
4953; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i15
4954; CHECK-NEXT:    [[TMP24:%.*]] = insertelement <3 x i15> undef, i15 [[TMP23]], i64 0
4955; CHECK-NEXT:    [[TMP25:%.*]] = extractelement <3 x i15> [[X]], i64 1
4956; CHECK-NEXT:    [[TMP26:%.*]] = extractelement <3 x i15> [[Y]], i64 1
4957; CHECK-NEXT:    [[TMP27:%.*]] = sext i15 [[TMP25]] to i32
4958; CHECK-NEXT:    [[TMP28:%.*]] = sext i15 [[TMP26]] to i32
4959; CHECK-NEXT:    [[TMP29:%.*]] = xor i32 [[TMP27]], [[TMP28]]
4960; CHECK-NEXT:    [[TMP30:%.*]] = ashr i32 [[TMP29]], 30
4961; CHECK-NEXT:    [[TMP31:%.*]] = or i32 [[TMP30]], 1
4962; CHECK-NEXT:    [[TMP32:%.*]] = sitofp i32 [[TMP27]] to float
4963; CHECK-NEXT:    [[TMP33:%.*]] = sitofp i32 [[TMP28]] to float
4964; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])
4965; CHECK-NEXT:    [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]]
4966; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]])
4967; CHECK-NEXT:    [[TMP37:%.*]] = fneg fast float [[TMP36]]
4968; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]])
4969; CHECK-NEXT:    [[TMP39:%.*]] = fptosi float [[TMP36]] to i32
4970; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]])
4971; CHECK-NEXT:    [[TMP41:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
4972; CHECK-NEXT:    [[TMP42:%.*]] = fcmp fast oge float [[TMP40]], [[TMP41]]
4973; CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP31]], i32 0
4974; CHECK-NEXT:    [[TMP44:%.*]] = add i32 [[TMP39]], [[TMP43]]
4975; CHECK-NEXT:    [[TMP45:%.*]] = shl i32 [[TMP44]], 17
4976; CHECK-NEXT:    [[TMP46:%.*]] = ashr i32 [[TMP45]], 17
4977; CHECK-NEXT:    [[TMP47:%.*]] = trunc i32 [[TMP46]] to i15
4978; CHECK-NEXT:    [[TMP48:%.*]] = insertelement <3 x i15> [[TMP24]], i15 [[TMP47]], i64 1
4979; CHECK-NEXT:    [[TMP49:%.*]] = extractelement <3 x i15> [[X]], i64 2
4980; CHECK-NEXT:    [[TMP50:%.*]] = extractelement <3 x i15> [[Y]], i64 2
4981; CHECK-NEXT:    [[TMP51:%.*]] = sext i15 [[TMP49]] to i32
4982; CHECK-NEXT:    [[TMP52:%.*]] = sext i15 [[TMP50]] to i32
4983; CHECK-NEXT:    [[TMP53:%.*]] = xor i32 [[TMP51]], [[TMP52]]
4984; CHECK-NEXT:    [[TMP54:%.*]] = ashr i32 [[TMP53]], 30
4985; CHECK-NEXT:    [[TMP55:%.*]] = or i32 [[TMP54]], 1
4986; CHECK-NEXT:    [[TMP56:%.*]] = sitofp i32 [[TMP51]] to float
4987; CHECK-NEXT:    [[TMP57:%.*]] = sitofp i32 [[TMP52]] to float
4988; CHECK-NEXT:    [[TMP58:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP57]])
4989; CHECK-NEXT:    [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]]
4990; CHECK-NEXT:    [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]])
4991; CHECK-NEXT:    [[TMP61:%.*]] = fneg fast float [[TMP60]]
4992; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]])
4993; CHECK-NEXT:    [[TMP63:%.*]] = fptosi float [[TMP60]] to i32
4994; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]])
4995; CHECK-NEXT:    [[TMP65:%.*]] = call fast float @llvm.fabs.f32(float [[TMP57]])
4996; CHECK-NEXT:    [[TMP66:%.*]] = fcmp fast oge float [[TMP64]], [[TMP65]]
4997; CHECK-NEXT:    [[TMP67:%.*]] = select i1 [[TMP66]], i32 [[TMP55]], i32 0
4998; CHECK-NEXT:    [[TMP68:%.*]] = add i32 [[TMP63]], [[TMP67]]
4999; CHECK-NEXT:    [[TMP69:%.*]] = shl i32 [[TMP68]], 17
5000; CHECK-NEXT:    [[TMP70:%.*]] = ashr i32 [[TMP69]], 17
5001; CHECK-NEXT:    [[TMP71:%.*]] = trunc i32 [[TMP70]] to i15
5002; CHECK-NEXT:    [[TMP72:%.*]] = insertelement <3 x i15> [[TMP48]], i15 [[TMP71]], i64 2
5003; CHECK-NEXT:    store <3 x i15> [[TMP72]], <3 x i15> addrspace(1)* [[OUT:%.*]], align 8
5004; CHECK-NEXT:    ret void
5005;
5006; GFX6-LABEL: sdiv_v3i15:
5007; GFX6:       ; %bb.0:
5008; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
5009; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
5010; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
5011; GFX6-NEXT:    s_mov_b32 s7, 0xf000
5012; GFX6-NEXT:    s_mov_b32 s6, -1
5013; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5014; GFX6-NEXT:    v_mov_b32_e32 v0, s2
5015; GFX6-NEXT:    v_alignbit_b32 v0, s3, v0, 30
5016; GFX6-NEXT:    s_bfe_i32 s3, s0, 0xf0000
5017; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s3
5018; GFX6-NEXT:    v_mov_b32_e32 v1, s0
5019; GFX6-NEXT:    v_alignbit_b32 v1, s1, v1, 30
5020; GFX6-NEXT:    s_bfe_i32 s1, s2, 0xf0000
5021; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s1
5022; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
5023; GFX6-NEXT:    s_xor_b32 s1, s1, s3
5024; GFX6-NEXT:    s_bfe_i32 s0, s0, 0xf000f
5025; GFX6-NEXT:    s_ashr_i32 s1, s1, 30
5026; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
5027; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
5028; GFX6-NEXT:    v_mad_f32 v3, -v4, v2, v3
5029; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v4
5030; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
5031; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s0
5032; GFX6-NEXT:    s_or_b32 s1, s1, 1
5033; GFX6-NEXT:    v_mov_b32_e32 v5, s1
5034; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
5035; GFX6-NEXT:    s_bfe_i32 s1, s2, 0xf000f
5036; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
5037; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s1
5038; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
5039; GFX6-NEXT:    s_xor_b32 s0, s1, s0
5040; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 15
5041; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
5042; GFX6-NEXT:    v_mul_f32_e32 v5, v4, v5
5043; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
5044; GFX6-NEXT:    v_mad_f32 v4, -v5, v3, v4
5045; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
5046; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v3|
5047; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, v1
5048; GFX6-NEXT:    s_or_b32 s0, s0, 1
5049; GFX6-NEXT:    v_mov_b32_e32 v6, s0
5050; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v6, vcc
5051; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 15
5052; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
5053; GFX6-NEXT:    v_cvt_f32_i32_e32 v5, v0
5054; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v4
5055; GFX6-NEXT:    v_xor_b32_e32 v0, v0, v1
5056; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
5057; GFX6-NEXT:    v_or_b32_e32 v0, 1, v0
5058; GFX6-NEXT:    v_mul_f32_e32 v1, v5, v6
5059; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
5060; GFX6-NEXT:    v_mad_f32 v5, -v1, v4, v5
5061; GFX6-NEXT:    v_cvt_i32_f32_e32 v1, v1
5062; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, |v4|
5063; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
5064; GFX6-NEXT:    s_movk_i32 s0, 0x7fff
5065; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
5066; GFX6-NEXT:    v_and_b32_e32 v3, s0, v3
5067; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 30
5068; GFX6-NEXT:    v_and_b32_e32 v2, s0, v2
5069; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
5070; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
5071; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
5072; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
5073; GFX6-NEXT:    s_waitcnt expcnt(0)
5074; GFX6-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
5075; GFX6-NEXT:    buffer_store_short v0, off, s[4:7], 0 offset:4
5076; GFX6-NEXT:    s_endpgm
5077;
5078; GFX9-LABEL: sdiv_v3i15:
5079; GFX9:       ; %bb.0:
5080; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
5081; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
5082; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x24
5083; GFX9-NEXT:    v_mov_b32_e32 v2, 0
5084; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5085; GFX9-NEXT:    s_bfe_i32 s1, s2, 0xf0000
5086; GFX9-NEXT:    s_bfe_i32 s0, s4, 0xf0000
5087; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s0
5088; GFX9-NEXT:    v_cvt_f32_i32_e32 v4, s1
5089; GFX9-NEXT:    s_xor_b32 s0, s1, s0
5090; GFX9-NEXT:    v_mov_b32_e32 v0, s2
5091; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v3
5092; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
5093; GFX9-NEXT:    v_alignbit_b32 v0, s3, v0, 30
5094; GFX9-NEXT:    s_or_b32 s3, s0, 1
5095; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
5096; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
5097; GFX9-NEXT:    v_mad_f32 v4, -v5, v3, v4
5098; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v4|, |v3|
5099; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
5100; GFX9-NEXT:    v_cvt_i32_f32_e32 v5, v5
5101; GFX9-NEXT:    s_cselect_b32 s0, s3, 0
5102; GFX9-NEXT:    s_bfe_i32 s1, s4, 0xf000f
5103; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, s1
5104; GFX9-NEXT:    v_add_u32_e32 v4, s0, v5
5105; GFX9-NEXT:    s_bfe_i32 s0, s2, 0xf000f
5106; GFX9-NEXT:    v_cvt_f32_i32_e32 v5, s0
5107; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v3
5108; GFX9-NEXT:    v_mov_b32_e32 v1, s4
5109; GFX9-NEXT:    v_alignbit_b32 v1, s5, v1, 30
5110; GFX9-NEXT:    s_xor_b32 s0, s0, s1
5111; GFX9-NEXT:    v_mul_f32_e32 v6, v5, v6
5112; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
5113; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
5114; GFX9-NEXT:    v_mad_f32 v5, -v6, v3, v5
5115; GFX9-NEXT:    v_bfe_i32 v1, v1, 0, 15
5116; GFX9-NEXT:    s_or_b32 s2, s0, 1
5117; GFX9-NEXT:    v_cvt_i32_f32_e32 v6, v6
5118; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v5|, |v3|
5119; GFX9-NEXT:    v_cvt_f32_i32_e32 v3, v1
5120; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
5121; GFX9-NEXT:    s_cselect_b32 s0, s2, 0
5122; GFX9-NEXT:    v_bfe_i32 v0, v0, 0, 15
5123; GFX9-NEXT:    v_add_u32_e32 v5, s0, v6
5124; GFX9-NEXT:    v_cvt_f32_i32_e32 v6, v0
5125; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v3
5126; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v1
5127; GFX9-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
5128; GFX9-NEXT:    v_or_b32_e32 v0, 1, v0
5129; GFX9-NEXT:    v_mul_f32_e32 v1, v6, v7
5130; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
5131; GFX9-NEXT:    v_cvt_i32_f32_e32 v7, v1
5132; GFX9-NEXT:    v_mad_f32 v1, -v1, v3, v6
5133; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
5134; GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
5135; GFX9-NEXT:    s_movk_i32 s0, 0x7fff
5136; GFX9-NEXT:    v_add_u32_e32 v0, v7, v0
5137; GFX9-NEXT:    v_and_b32_e32 v3, s0, v4
5138; GFX9-NEXT:    v_and_b32_e32 v4, s0, v5
5139; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 30, v[0:1]
5140; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 15, v4
5141; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
5142; GFX9-NEXT:    v_or_b32_e32 v0, v3, v0
5143; GFX9-NEXT:    global_store_dword v2, v0, s[6:7]
5144; GFX9-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
5145; GFX9-NEXT:    global_store_short v2, v0, s[6:7] offset:4
5146; GFX9-NEXT:    s_endpgm
5147  %r = sdiv <3 x i15> %x, %y
5148  store <3 x i15> %r, <3 x i15> addrspace(1)* %out
5149  ret void
5150}
5151
5152define amdgpu_kernel void @srem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x, <3 x i15> %y) {
5153; CHECK-LABEL: @srem_v3i15(
5154; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <3 x i15> [[X:%.*]], i64 0
5155; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i15> [[Y:%.*]], i64 0
5156; CHECK-NEXT:    [[TMP3:%.*]] = sext i15 [[TMP1]] to i32
5157; CHECK-NEXT:    [[TMP4:%.*]] = sext i15 [[TMP2]] to i32
5158; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
5159; CHECK-NEXT:    [[TMP6:%.*]] = ashr i32 [[TMP5]], 30
5160; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], 1
5161; CHECK-NEXT:    [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float
5162; CHECK-NEXT:    [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float
5163; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
5164; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]
5165; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])
5166; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
5167; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
5168; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
5169; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
5170; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
5171; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
5172; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
5173; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
5174; CHECK-NEXT:    [[TMP21:%.*]] = mul i32 [[TMP20]], [[TMP4]]
5175; CHECK-NEXT:    [[TMP22:%.*]] = sub i32 [[TMP3]], [[TMP21]]
5176; CHECK-NEXT:    [[TMP23:%.*]] = shl i32 [[TMP22]], 17
5177; CHECK-NEXT:    [[TMP24:%.*]] = ashr i32 [[TMP23]], 17
5178; CHECK-NEXT:    [[TMP25:%.*]] = trunc i32 [[TMP24]] to i15
5179; CHECK-NEXT:    [[TMP26:%.*]] = insertelement <3 x i15> undef, i15 [[TMP25]], i64 0
5180; CHECK-NEXT:    [[TMP27:%.*]] = extractelement <3 x i15> [[X]], i64 1
5181; CHECK-NEXT:    [[TMP28:%.*]] = extractelement <3 x i15> [[Y]], i64 1
5182; CHECK-NEXT:    [[TMP29:%.*]] = sext i15 [[TMP27]] to i32
5183; CHECK-NEXT:    [[TMP30:%.*]] = sext i15 [[TMP28]] to i32
5184; CHECK-NEXT:    [[TMP31:%.*]] = xor i32 [[TMP29]], [[TMP30]]
5185; CHECK-NEXT:    [[TMP32:%.*]] = ashr i32 [[TMP31]], 30
5186; CHECK-NEXT:    [[TMP33:%.*]] = or i32 [[TMP32]], 1
5187; CHECK-NEXT:    [[TMP34:%.*]] = sitofp i32 [[TMP29]] to float
5188; CHECK-NEXT:    [[TMP35:%.*]] = sitofp i32 [[TMP30]] to float
5189; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])
5190; CHECK-NEXT:    [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]]
5191; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]])
5192; CHECK-NEXT:    [[TMP39:%.*]] = fneg fast float [[TMP38]]
5193; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]])
5194; CHECK-NEXT:    [[TMP41:%.*]] = fptosi float [[TMP38]] to i32
5195; CHECK-NEXT:    [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]])
5196; CHECK-NEXT:    [[TMP43:%.*]] = call fast float @llvm.fabs.f32(float [[TMP35]])
5197; CHECK-NEXT:    [[TMP44:%.*]] = fcmp fast oge float [[TMP42]], [[TMP43]]
5198; CHECK-NEXT:    [[TMP45:%.*]] = select i1 [[TMP44]], i32 [[TMP33]], i32 0
5199; CHECK-NEXT:    [[TMP46:%.*]] = add i32 [[TMP41]], [[TMP45]]
5200; CHECK-NEXT:    [[TMP47:%.*]] = mul i32 [[TMP46]], [[TMP30]]
5201; CHECK-NEXT:    [[TMP48:%.*]] = sub i32 [[TMP29]], [[TMP47]]
5202; CHECK-NEXT:    [[TMP49:%.*]] = shl i32 [[TMP48]], 17
5203; CHECK-NEXT:    [[TMP50:%.*]] = ashr i32 [[TMP49]], 17
5204; CHECK-NEXT:    [[TMP51:%.*]] = trunc i32 [[TMP50]] to i15
5205; CHECK-NEXT:    [[TMP52:%.*]] = insertelement <3 x i15> [[TMP26]], i15 [[TMP51]], i64 1
5206; CHECK-NEXT:    [[TMP53:%.*]] = extractelement <3 x i15> [[X]], i64 2
5207; CHECK-NEXT:    [[TMP54:%.*]] = extractelement <3 x i15> [[Y]], i64 2
5208; CHECK-NEXT:    [[TMP55:%.*]] = sext i15 [[TMP53]] to i32
5209; CHECK-NEXT:    [[TMP56:%.*]] = sext i15 [[TMP54]] to i32
5210; CHECK-NEXT:    [[TMP57:%.*]] = xor i32 [[TMP55]], [[TMP56]]
5211; CHECK-NEXT:    [[TMP58:%.*]] = ashr i32 [[TMP57]], 30
5212; CHECK-NEXT:    [[TMP59:%.*]] = or i32 [[TMP58]], 1
5213; CHECK-NEXT:    [[TMP60:%.*]] = sitofp i32 [[TMP55]] to float
5214; CHECK-NEXT:    [[TMP61:%.*]] = sitofp i32 [[TMP56]] to float
5215; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP61]])
5216; CHECK-NEXT:    [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]]
5217; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]])
5218; CHECK-NEXT:    [[TMP65:%.*]] = fneg fast float [[TMP64]]
5219; CHECK-NEXT:    [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]])
5220; CHECK-NEXT:    [[TMP67:%.*]] = fptosi float [[TMP64]] to i32
5221; CHECK-NEXT:    [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]])
5222; CHECK-NEXT:    [[TMP69:%.*]] = call fast float @llvm.fabs.f32(float [[TMP61]])
5223; CHECK-NEXT:    [[TMP70:%.*]] = fcmp fast oge float [[TMP68]], [[TMP69]]
5224; CHECK-NEXT:    [[TMP71:%.*]] = select i1 [[TMP70]], i32 [[TMP59]], i32 0
5225; CHECK-NEXT:    [[TMP72:%.*]] = add i32 [[TMP67]], [[TMP71]]
5226; CHECK-NEXT:    [[TMP73:%.*]] = mul i32 [[TMP72]], [[TMP56]]
5227; CHECK-NEXT:    [[TMP74:%.*]] = sub i32 [[TMP55]], [[TMP73]]
5228; CHECK-NEXT:    [[TMP75:%.*]] = shl i32 [[TMP74]], 17
5229; CHECK-NEXT:    [[TMP76:%.*]] = ashr i32 [[TMP75]], 17
5230; CHECK-NEXT:    [[TMP77:%.*]] = trunc i32 [[TMP76]] to i15
5231; CHECK-NEXT:    [[TMP78:%.*]] = insertelement <3 x i15> [[TMP52]], i15 [[TMP77]], i64 2
5232; CHECK-NEXT:    store <3 x i15> [[TMP78]], <3 x i15> addrspace(1)* [[OUT:%.*]], align 8
5233; CHECK-NEXT:    ret void
5234;
5235; GFX6-LABEL: srem_v3i15:
5236; GFX6:       ; %bb.0:
5237; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
5238; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
5239; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
5240; GFX6-NEXT:    s_mov_b32 s7, 0xf000
5241; GFX6-NEXT:    s_mov_b32 s6, -1
5242; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5243; GFX6-NEXT:    s_bfe_i32 s10, s2, 0xf0000
5244; GFX6-NEXT:    v_cvt_f32_i32_e32 v5, s10
5245; GFX6-NEXT:    v_mov_b32_e32 v2, s0
5246; GFX6-NEXT:    v_alignbit_b32 v2, s1, v2, 30
5247; GFX6-NEXT:    s_bfe_i32 s1, s0, 0xf0000
5248; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s1
5249; GFX6-NEXT:    s_xor_b32 s1, s10, s1
5250; GFX6-NEXT:    s_ashr_i32 s1, s1, 30
5251; GFX6-NEXT:    s_or_b32 s1, s1, 1
5252; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v4
5253; GFX6-NEXT:    v_mov_b32_e32 v7, s1
5254; GFX6-NEXT:    s_lshr_b32 s9, s0, 15
5255; GFX6-NEXT:    s_bfe_i32 s1, s2, 0xf000f
5256; GFX6-NEXT:    v_mul_f32_e32 v6, v5, v6
5257; GFX6-NEXT:    v_trunc_f32_e32 v6, v6
5258; GFX6-NEXT:    v_mad_f32 v5, -v6, v4, v5
5259; GFX6-NEXT:    v_cvt_i32_f32_e32 v6, v6
5260; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, |v4|
5261; GFX6-NEXT:    v_cndmask_b32_e32 v4, 0, v7, vcc
5262; GFX6-NEXT:    v_mov_b32_e32 v0, s2
5263; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
5264; GFX6-NEXT:    v_mul_lo_u32 v4, v4, s0
5265; GFX6-NEXT:    s_bfe_i32 s0, s0, 0xf000f
5266; GFX6-NEXT:    v_cvt_f32_i32_e32 v5, s0
5267; GFX6-NEXT:    v_cvt_f32_i32_e32 v6, s1
5268; GFX6-NEXT:    v_alignbit_b32 v0, s3, v0, 30
5269; GFX6-NEXT:    s_movk_i32 s3, 0x7fff
5270; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v5
5271; GFX6-NEXT:    v_and_b32_e32 v3, s3, v2
5272; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s2, v4
5273; GFX6-NEXT:    v_mul_f32_e32 v7, v6, v7
5274; GFX6-NEXT:    v_trunc_f32_e32 v7, v7
5275; GFX6-NEXT:    s_xor_b32 s0, s1, s0
5276; GFX6-NEXT:    v_mad_f32 v6, -v7, v5, v6
5277; GFX6-NEXT:    v_bfe_i32 v2, v2, 0, 15
5278; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
5279; GFX6-NEXT:    v_cvt_i32_f32_e32 v7, v7
5280; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, |v5|
5281; GFX6-NEXT:    v_cvt_f32_i32_e32 v6, v2
5282; GFX6-NEXT:    s_or_b32 s0, s0, 1
5283; GFX6-NEXT:    v_mov_b32_e32 v8, s0
5284; GFX6-NEXT:    v_and_b32_e32 v1, s3, v0
5285; GFX6-NEXT:    v_cndmask_b32_e32 v5, 0, v8, vcc
5286; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 15
5287; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
5288; GFX6-NEXT:    v_cvt_f32_i32_e32 v7, v0
5289; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v6
5290; GFX6-NEXT:    v_xor_b32_e32 v0, v0, v2
5291; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
5292; GFX6-NEXT:    v_or_b32_e32 v0, 1, v0
5293; GFX6-NEXT:    v_mul_f32_e32 v2, v7, v8
5294; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
5295; GFX6-NEXT:    v_mad_f32 v7, -v2, v6, v7
5296; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
5297; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v7|, |v6|
5298; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
5299; GFX6-NEXT:    v_mul_lo_u32 v5, v5, s9
5300; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
5301; GFX6-NEXT:    v_mul_lo_u32 v0, v0, v3
5302; GFX6-NEXT:    s_lshr_b32 s8, s2, 15
5303; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s8, v5
5304; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, v0, v1
5305; GFX6-NEXT:    v_and_b32_e32 v2, s3, v2
5306; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 30
5307; GFX6-NEXT:    v_and_b32_e32 v3, s3, v4
5308; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 15, v2
5309; GFX6-NEXT:    v_or_b32_e32 v2, v3, v2
5310; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
5311; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
5312; GFX6-NEXT:    s_waitcnt expcnt(0)
5313; GFX6-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
5314; GFX6-NEXT:    buffer_store_short v0, off, s[4:7], 0 offset:4
5315; GFX6-NEXT:    s_endpgm
5316;
5317; GFX9-LABEL: srem_v3i15:
5318; GFX9:       ; %bb.0:
5319; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
5320; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
5321; GFX9-NEXT:    s_movk_i32 s8, 0x7fff
5322; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
5323; GFX9-NEXT:    v_mov_b32_e32 v2, 0
5324; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5325; GFX9-NEXT:    s_bfe_i32 s6, s2, 0xf0000
5326; GFX9-NEXT:    v_cvt_f32_i32_e32 v5, s6
5327; GFX9-NEXT:    v_mov_b32_e32 v0, s2
5328; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5329; GFX9-NEXT:    v_alignbit_b32 v1, s1, v1, 30
5330; GFX9-NEXT:    s_bfe_i32 s1, s0, 0xf0000
5331; GFX9-NEXT:    v_cvt_f32_i32_e32 v4, s1
5332; GFX9-NEXT:    s_xor_b32 s1, s6, s1
5333; GFX9-NEXT:    s_ashr_i32 s1, s1, 30
5334; GFX9-NEXT:    v_alignbit_b32 v0, s3, v0, 30
5335; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v4
5336; GFX9-NEXT:    s_lshr_b32 s3, s2, 15
5337; GFX9-NEXT:    s_lshr_b32 s9, s0, 15
5338; GFX9-NEXT:    s_or_b32 s1, s1, 1
5339; GFX9-NEXT:    v_mul_f32_e32 v6, v5, v6
5340; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
5341; GFX9-NEXT:    v_mad_f32 v5, -v6, v4, v5
5342; GFX9-NEXT:    v_cvt_i32_f32_e32 v6, v6
5343; GFX9-NEXT:    v_cmp_ge_f32_e64 s[6:7], |v5|, |v4|
5344; GFX9-NEXT:    s_and_b64 s[6:7], s[6:7], exec
5345; GFX9-NEXT:    s_cselect_b32 s1, s1, 0
5346; GFX9-NEXT:    v_add_u32_e32 v4, s1, v6
5347; GFX9-NEXT:    s_bfe_i32 s1, s0, 0xf000f
5348; GFX9-NEXT:    v_cvt_f32_i32_e32 v5, s1
5349; GFX9-NEXT:    v_mul_lo_u32 v4, v4, s0
5350; GFX9-NEXT:    s_bfe_i32 s0, s2, 0xf000f
5351; GFX9-NEXT:    v_cvt_f32_i32_e32 v6, s0
5352; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v5
5353; GFX9-NEXT:    s_xor_b32 s0, s0, s1
5354; GFX9-NEXT:    v_and_b32_e32 v3, s8, v1
5355; GFX9-NEXT:    s_ashr_i32 s0, s0, 30
5356; GFX9-NEXT:    v_mul_f32_e32 v7, v6, v7
5357; GFX9-NEXT:    v_trunc_f32_e32 v7, v7
5358; GFX9-NEXT:    v_mad_f32 v6, -v7, v5, v6
5359; GFX9-NEXT:    v_cvt_i32_f32_e32 v7, v7
5360; GFX9-NEXT:    v_bfe_i32 v1, v1, 0, 15
5361; GFX9-NEXT:    s_or_b32 s6, s0, 1
5362; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v6|, |v5|
5363; GFX9-NEXT:    v_cvt_f32_i32_e32 v6, v1
5364; GFX9-NEXT:    s_and_b64 s[0:1], s[0:1], exec
5365; GFX9-NEXT:    s_cselect_b32 s0, s6, 0
5366; GFX9-NEXT:    v_add_u32_e32 v5, s0, v7
5367; GFX9-NEXT:    v_bfe_i32 v7, v0, 0, 15
5368; GFX9-NEXT:    v_cvt_f32_i32_e32 v8, v7
5369; GFX9-NEXT:    v_rcp_iflag_f32_e32 v9, v6
5370; GFX9-NEXT:    v_xor_b32_e32 v1, v7, v1
5371; GFX9-NEXT:    v_ashrrev_i32_e32 v1, 30, v1
5372; GFX9-NEXT:    v_or_b32_e32 v1, 1, v1
5373; GFX9-NEXT:    v_mul_f32_e32 v7, v8, v9
5374; GFX9-NEXT:    v_trunc_f32_e32 v7, v7
5375; GFX9-NEXT:    v_cvt_i32_f32_e32 v9, v7
5376; GFX9-NEXT:    v_mad_f32 v7, -v7, v6, v8
5377; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v7|, |v6|
5378; GFX9-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
5379; GFX9-NEXT:    v_mul_lo_u32 v5, v5, s9
5380; GFX9-NEXT:    v_add_u32_e32 v1, v9, v1
5381; GFX9-NEXT:    v_mul_lo_u32 v1, v1, v3
5382; GFX9-NEXT:    v_and_b32_e32 v0, s8, v0
5383; GFX9-NEXT:    v_sub_u32_e32 v3, s2, v4
5384; GFX9-NEXT:    v_sub_u32_e32 v4, s3, v5
5385; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v1
5386; GFX9-NEXT:    v_and_b32_e32 v4, s8, v4
5387; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 30, v[0:1]
5388; GFX9-NEXT:    v_and_b32_e32 v3, s8, v3
5389; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 15, v4
5390; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
5391; GFX9-NEXT:    v_or_b32_e32 v0, v3, v0
5392; GFX9-NEXT:    global_store_dword v2, v0, s[4:5]
5393; GFX9-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
5394; GFX9-NEXT:    global_store_short v2, v0, s[4:5] offset:4
5395; GFX9-NEXT:    s_endpgm
5396  %r = srem <3 x i15> %x, %y
5397  store <3 x i15> %r, <3 x i15> addrspace(1)* %out
5398  ret void
5399}
5400
5401define amdgpu_kernel void @udiv_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
5402; CHECK-LABEL: @udiv_i32_oddk_denom(
5403; CHECK-NEXT:    [[R:%.*]] = udiv i32 [[X:%.*]], 1235195
5404; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
5405; CHECK-NEXT:    ret void
5406;
5407; GFX6-LABEL: udiv_i32_oddk_denom:
5408; GFX6:       ; %bb.0:
5409; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
5410; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
5411; GFX6-NEXT:    v_mov_b32_e32 v0, 0xb2a50881
5412; GFX6-NEXT:    s_mov_b32 s3, 0xf000
5413; GFX6-NEXT:    s_mov_b32 s2, -1
5414; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5415; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
5416; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s4, v0
5417; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
5418; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
5419; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 20, v0
5420; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
5421; GFX6-NEXT:    s_endpgm
5422;
5423; GFX9-LABEL: udiv_i32_oddk_denom:
5424; GFX9:       ; %bb.0:
5425; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
5426; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
5427; GFX9-NEXT:    v_mov_b32_e32 v0, 0
5428; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5429; GFX9-NEXT:    s_mul_hi_u32 s0, s4, 0xb2a50881
5430; GFX9-NEXT:    s_sub_i32 s1, s4, s0
5431; GFX9-NEXT:    s_lshr_b32 s1, s1, 1
5432; GFX9-NEXT:    s_add_i32 s1, s1, s0
5433; GFX9-NEXT:    s_lshr_b32 s0, s1, 20
5434; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5435; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
5436; GFX9-NEXT:    s_endpgm
5437  %r = udiv i32 %x, 1235195
5438  store i32 %r, i32 addrspace(1)* %out
5439  ret void
5440}
5441
5442define amdgpu_kernel void @udiv_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x) {
5443; CHECK-LABEL: @udiv_i32_pow2k_denom(
5444; CHECK-NEXT:    [[R:%.*]] = udiv i32 [[X:%.*]], 4096
5445; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
5446; CHECK-NEXT:    ret void
5447;
5448; GFX6-LABEL: udiv_i32_pow2k_denom:
5449; GFX6:       ; %bb.0:
5450; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
5451; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
5452; GFX6-NEXT:    s_mov_b32 s3, 0xf000
5453; GFX6-NEXT:    s_mov_b32 s2, -1
5454; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5455; GFX6-NEXT:    s_lshr_b32 s4, s4, 12
5456; GFX6-NEXT:    v_mov_b32_e32 v0, s4
5457; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
5458; GFX6-NEXT:    s_endpgm
5459;
5460; GFX9-LABEL: udiv_i32_pow2k_denom:
5461; GFX9:       ; %bb.0:
5462; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
5463; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
5464; GFX9-NEXT:    v_mov_b32_e32 v0, 0
5465; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5466; GFX9-NEXT:    s_lshr_b32 s0, s4, 12
5467; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5468; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
5469; GFX9-NEXT:    s_endpgm
5470  %r = udiv i32 %x, 4096
5471  store i32 %r, i32 addrspace(1)* %out
5472  ret void
5473}
5474
5475define amdgpu_kernel void @udiv_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %x, i32 %y) {
5476; CHECK-LABEL: @udiv_i32_pow2_shl_denom(
5477; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]]
5478; CHECK-NEXT:    [[R:%.*]] = udiv i32 [[X:%.*]], [[SHL_Y]]
5479; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
5480; CHECK-NEXT:    ret void
5481;
5482; GFX6-LABEL: udiv_i32_pow2_shl_denom:
5483; GFX6:       ; %bb.0:
5484; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
5485; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
5486; GFX6-NEXT:    s_mov_b32 s3, 0xf000
5487; GFX6-NEXT:    s_mov_b32 s2, -1
5488; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5489; GFX6-NEXT:    s_add_i32 s5, s5, 12
5490; GFX6-NEXT:    s_lshr_b32 s4, s4, s5
5491; GFX6-NEXT:    v_mov_b32_e32 v0, s4
5492; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
5493; GFX6-NEXT:    s_endpgm
5494;
5495; GFX9-LABEL: udiv_i32_pow2_shl_denom:
5496; GFX9:       ; %bb.0:
5497; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
5498; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
5499; GFX9-NEXT:    v_mov_b32_e32 v0, 0
5500; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5501; GFX9-NEXT:    s_add_i32 s0, s3, 12
5502; GFX9-NEXT:    s_lshr_b32 s0, s2, s0
5503; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5504; GFX9-NEXT:    global_store_dword v0, v1, s[4:5]
5505; GFX9-NEXT:    s_endpgm
5506  %shl.y = shl i32 4096, %y
5507  %r = udiv i32 %x, %shl.y
5508  store i32 %r, i32 addrspace(1)* %out
5509  ret void
5510}
5511
5512define amdgpu_kernel void @udiv_v2i32_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) {
5513; CHECK-LABEL: @udiv_v2i32_pow2k_denom(
5514; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
5515; CHECK-NEXT:    [[TMP2:%.*]] = udiv i32 [[TMP1]], 4096
5516; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0
5517; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1
5518; CHECK-NEXT:    [[TMP5:%.*]] = udiv i32 [[TMP4]], 4096
5519; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1
5520; CHECK-NEXT:    store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
5521; CHECK-NEXT:    ret void
5522;
5523; GFX6-LABEL: udiv_v2i32_pow2k_denom:
5524; GFX6:       ; %bb.0:
5525; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
5526; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
5527; GFX6-NEXT:    s_mov_b32 s3, 0xf000
5528; GFX6-NEXT:    s_mov_b32 s2, -1
5529; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5530; GFX6-NEXT:    s_lshr_b32 s4, s4, 12
5531; GFX6-NEXT:    s_lshr_b32 s5, s5, 12
5532; GFX6-NEXT:    v_mov_b32_e32 v0, s4
5533; GFX6-NEXT:    v_mov_b32_e32 v1, s5
5534; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
5535; GFX6-NEXT:    s_endpgm
5536;
5537; GFX9-LABEL: udiv_v2i32_pow2k_denom:
5538; GFX9:       ; %bb.0:
5539; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
5540; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
5541; GFX9-NEXT:    v_mov_b32_e32 v2, 0
5542; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5543; GFX9-NEXT:    s_lshr_b32 s0, s2, 12
5544; GFX9-NEXT:    s_lshr_b32 s1, s3, 12
5545; GFX9-NEXT:    v_mov_b32_e32 v0, s0
5546; GFX9-NEXT:    v_mov_b32_e32 v1, s1
5547; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
5548; GFX9-NEXT:    s_endpgm
5549  %r = udiv <2 x i32> %x, <i32 4096, i32 4096>
5550  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
5551  ret void
5552}
5553
5554define amdgpu_kernel void @udiv_v2i32_mixed_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) {
5555; CHECK-LABEL: @udiv_v2i32_mixed_pow2k_denom(
5556; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
5557; CHECK-NEXT:    [[TMP2:%.*]] = udiv i32 [[TMP1]], 4096
5558; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0
5559; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1
5560; CHECK-NEXT:    [[TMP5:%.*]] = udiv i32 [[TMP4]], 4095
5561; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1
5562; CHECK-NEXT:    store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
5563; CHECK-NEXT:    ret void
5564;
5565; GFX6-LABEL: udiv_v2i32_mixed_pow2k_denom:
5566; GFX6:       ; %bb.0:
5567; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
5568; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
5569; GFX6-NEXT:    v_mov_b32_e32 v0, 0x100101
5570; GFX6-NEXT:    s_mov_b32 s3, 0xf000
5571; GFX6-NEXT:    s_mov_b32 s2, -1
5572; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5573; GFX6-NEXT:    v_mul_hi_u32 v0, s5, v0
5574; GFX6-NEXT:    s_lshr_b32 s4, s4, 12
5575; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v0
5576; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
5577; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
5578; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 11, v0
5579; GFX6-NEXT:    v_mov_b32_e32 v0, s4
5580; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
5581; GFX6-NEXT:    s_endpgm
5582;
5583; GFX9-LABEL: udiv_v2i32_mixed_pow2k_denom:
5584; GFX9:       ; %bb.0:
5585; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
5586; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
5587; GFX9-NEXT:    v_mov_b32_e32 v2, 0
5588; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5589; GFX9-NEXT:    s_mul_hi_u32 s1, s3, 0x100101
5590; GFX9-NEXT:    s_lshr_b32 s0, s2, 12
5591; GFX9-NEXT:    s_sub_i32 s2, s3, s1
5592; GFX9-NEXT:    s_lshr_b32 s2, s2, 1
5593; GFX9-NEXT:    s_add_i32 s2, s2, s1
5594; GFX9-NEXT:    s_lshr_b32 s1, s2, 11
5595; GFX9-NEXT:    v_mov_b32_e32 v0, s0
5596; GFX9-NEXT:    v_mov_b32_e32 v1, s1
5597; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
5598; GFX9-NEXT:    s_endpgm
5599  %r = udiv <2 x i32> %x, <i32 4096, i32 4095>
5600  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
5601  ret void
5602}
5603
5604define amdgpu_kernel void @udiv_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) {
5605; CHECK-LABEL: @udiv_v2i32_pow2_shl_denom(
5606; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i32> <i32 4096, i32 4096>, [[Y:%.*]]
5607; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
5608; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 0
5609; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float
5610; CHECK-NEXT:    [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])
5611; CHECK-NEXT:    [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41EFFFFFC0000000
5612; CHECK-NEXT:    [[TMP6:%.*]] = fptoui float [[TMP5]] to i32
5613; CHECK-NEXT:    [[TMP7:%.*]] = sub i32 0, [[TMP2]]
5614; CHECK-NEXT:    [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP6]]
5615; CHECK-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP6]] to i64
5616; CHECK-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP8]] to i64
5617; CHECK-NEXT:    [[TMP11:%.*]] = mul i64 [[TMP9]], [[TMP10]]
5618; CHECK-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
5619; CHECK-NEXT:    [[TMP13:%.*]] = lshr i64 [[TMP11]], 32
5620; CHECK-NEXT:    [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32
5621; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP6]], [[TMP14]]
5622; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP1]] to i64
5623; CHECK-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP15]] to i64
5624; CHECK-NEXT:    [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]
5625; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
5626; CHECK-NEXT:    [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
5627; CHECK-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
5628; CHECK-NEXT:    [[TMP22:%.*]] = mul i32 [[TMP21]], [[TMP2]]
5629; CHECK-NEXT:    [[TMP23:%.*]] = sub i32 [[TMP1]], [[TMP22]]
5630; CHECK-NEXT:    [[TMP24:%.*]] = icmp uge i32 [[TMP23]], [[TMP2]]
5631; CHECK-NEXT:    [[TMP25:%.*]] = add i32 [[TMP21]], 1
5632; CHECK-NEXT:    [[TMP26:%.*]] = select i1 [[TMP24]], i32 [[TMP25]], i32 [[TMP21]]
5633; CHECK-NEXT:    [[TMP27:%.*]] = sub i32 [[TMP23]], [[TMP2]]
5634; CHECK-NEXT:    [[TMP28:%.*]] = select i1 [[TMP24]], i32 [[TMP27]], i32 [[TMP23]]
5635; CHECK-NEXT:    [[TMP29:%.*]] = icmp uge i32 [[TMP28]], [[TMP2]]
5636; CHECK-NEXT:    [[TMP30:%.*]] = add i32 [[TMP26]], 1
5637; CHECK-NEXT:    [[TMP31:%.*]] = select i1 [[TMP29]], i32 [[TMP30]], i32 [[TMP26]]
5638; CHECK-NEXT:    [[TMP32:%.*]] = insertelement <2 x i32> undef, i32 [[TMP31]], i64 0
5639; CHECK-NEXT:    [[TMP33:%.*]] = extractelement <2 x i32> [[X]], i64 1
5640; CHECK-NEXT:    [[TMP34:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1
5641; CHECK-NEXT:    [[TMP35:%.*]] = uitofp i32 [[TMP34]] to float
5642; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])
5643; CHECK-NEXT:    [[TMP37:%.*]] = fmul fast float [[TMP36]], 0x41EFFFFFC0000000
5644; CHECK-NEXT:    [[TMP38:%.*]] = fptoui float [[TMP37]] to i32
5645; CHECK-NEXT:    [[TMP39:%.*]] = sub i32 0, [[TMP34]]
5646; CHECK-NEXT:    [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP38]]
5647; CHECK-NEXT:    [[TMP41:%.*]] = zext i32 [[TMP38]] to i64
5648; CHECK-NEXT:    [[TMP42:%.*]] = zext i32 [[TMP40]] to i64
5649; CHECK-NEXT:    [[TMP43:%.*]] = mul i64 [[TMP41]], [[TMP42]]
5650; CHECK-NEXT:    [[TMP44:%.*]] = trunc i64 [[TMP43]] to i32
5651; CHECK-NEXT:    [[TMP45:%.*]] = lshr i64 [[TMP43]], 32
5652; CHECK-NEXT:    [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32
5653; CHECK-NEXT:    [[TMP47:%.*]] = add i32 [[TMP38]], [[TMP46]]
5654; CHECK-NEXT:    [[TMP48:%.*]] = zext i32 [[TMP33]] to i64
5655; CHECK-NEXT:    [[TMP49:%.*]] = zext i32 [[TMP47]] to i64
5656; CHECK-NEXT:    [[TMP50:%.*]] = mul i64 [[TMP48]], [[TMP49]]
5657; CHECK-NEXT:    [[TMP51:%.*]] = trunc i64 [[TMP50]] to i32
5658; CHECK-NEXT:    [[TMP52:%.*]] = lshr i64 [[TMP50]], 32
5659; CHECK-NEXT:    [[TMP53:%.*]] = trunc i64 [[TMP52]] to i32
5660; CHECK-NEXT:    [[TMP54:%.*]] = mul i32 [[TMP53]], [[TMP34]]
5661; CHECK-NEXT:    [[TMP55:%.*]] = sub i32 [[TMP33]], [[TMP54]]
5662; CHECK-NEXT:    [[TMP56:%.*]] = icmp uge i32 [[TMP55]], [[TMP34]]
5663; CHECK-NEXT:    [[TMP57:%.*]] = add i32 [[TMP53]], 1
5664; CHECK-NEXT:    [[TMP58:%.*]] = select i1 [[TMP56]], i32 [[TMP57]], i32 [[TMP53]]
5665; CHECK-NEXT:    [[TMP59:%.*]] = sub i32 [[TMP55]], [[TMP34]]
5666; CHECK-NEXT:    [[TMP60:%.*]] = select i1 [[TMP56]], i32 [[TMP59]], i32 [[TMP55]]
5667; CHECK-NEXT:    [[TMP61:%.*]] = icmp uge i32 [[TMP60]], [[TMP34]]
5668; CHECK-NEXT:    [[TMP62:%.*]] = add i32 [[TMP58]], 1
5669; CHECK-NEXT:    [[TMP63:%.*]] = select i1 [[TMP61]], i32 [[TMP62]], i32 [[TMP58]]
5670; CHECK-NEXT:    [[TMP64:%.*]] = insertelement <2 x i32> [[TMP32]], i32 [[TMP63]], i64 1
5671; CHECK-NEXT:    store <2 x i32> [[TMP64]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
5672; CHECK-NEXT:    ret void
5673;
5674; GFX6-LABEL: udiv_v2i32_pow2_shl_denom:
5675; GFX6:       ; %bb.0:
5676; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
5677; GFX6-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x9
5678; GFX6-NEXT:    s_movk_i32 s2, 0x1000
5679; GFX6-NEXT:    s_mov_b32 s0, 0x4f7ffffe
5680; GFX6-NEXT:    s_mov_b32 s11, 0xf000
5681; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5682; GFX6-NEXT:    s_lshl_b32 s3, s2, s6
5683; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s3
5684; GFX6-NEXT:    s_lshl_b32 s2, s2, s7
5685; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s2
5686; GFX6-NEXT:    s_mov_b32 s10, -1
5687; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
5688; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
5689; GFX6-NEXT:    v_mul_f32_e32 v0, s0, v0
5690; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
5691; GFX6-NEXT:    v_mul_f32_e32 v1, s0, v1
5692; GFX6-NEXT:    s_sub_i32 s0, 0, s3
5693; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
5694; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v0
5695; GFX6-NEXT:    s_sub_i32 s0, 0, s2
5696; GFX6-NEXT:    v_mul_lo_u32 v3, s0, v1
5697; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
5698; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
5699; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
5700; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
5701; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
5702; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
5703; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s3
5704; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
5705; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s2
5706; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s4, v2
5707; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v2
5708; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[0:1]
5709; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s3, v2
5710; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
5711; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
5712; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2
5713; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
5714; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s5, v4
5715; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
5716; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v2
5717; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
5718; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s2, v2
5719; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
5720; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
5721; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s2, v2
5722; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5723; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
5724; GFX6-NEXT:    s_endpgm
5725;
5726; GFX9-LABEL: udiv_v2i32_pow2_shl_denom:
5727; GFX9:       ; %bb.0:
5728; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
5729; GFX9-NEXT:    s_movk_i32 s2, 0x1000
5730; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5731; GFX9-NEXT:    s_lshl_b32 s6, s2, s6
5732; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s6
5733; GFX9-NEXT:    s_lshl_b32 s7, s2, s7
5734; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s7
5735; GFX9-NEXT:    s_mov_b32 s2, 0x4f7ffffe
5736; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
5737; GFX9-NEXT:    s_sub_i32 s3, 0, s7
5738; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
5739; GFX9-NEXT:    v_mul_f32_e32 v0, s2, v0
5740; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
5741; GFX9-NEXT:    v_mul_f32_e32 v1, s2, v1
5742; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
5743; GFX9-NEXT:    s_sub_i32 s2, 0, s6
5744; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v0
5745; GFX9-NEXT:    v_mul_lo_u32 v3, s3, v1
5746; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
5747; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
5748; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
5749; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
5750; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
5751; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
5752; GFX9-NEXT:    v_mul_hi_u32 v1, s5, v1
5753; GFX9-NEXT:    v_mov_b32_e32 v2, 0
5754; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s6
5755; GFX9-NEXT:    v_add_u32_e32 v5, 1, v0
5756; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s7
5757; GFX9-NEXT:    v_add_u32_e32 v6, 1, v1
5758; GFX9-NEXT:    v_sub_u32_e32 v3, s4, v3
5759; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s6, v3
5760; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
5761; GFX9-NEXT:    v_subrev_u32_e32 v5, s6, v3
5762; GFX9-NEXT:    v_sub_u32_e32 v4, s5, v4
5763; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
5764; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s7, v4
5765; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s6, v3
5766; GFX9-NEXT:    v_subrev_u32_e32 v3, s7, v4
5767; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v6, s[0:1]
5768; GFX9-NEXT:    v_add_u32_e32 v5, 1, v0
5769; GFX9-NEXT:    v_cndmask_b32_e64 v3, v4, v3, s[0:1]
5770; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
5771; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
5772; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v3
5773; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
5774; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5775; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
5776; GFX9-NEXT:    s_endpgm
5777  %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
5778  %r = udiv <2 x i32> %x, %shl.y
5779  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
5780  ret void
5781}
5782
5783define amdgpu_kernel void @urem_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
5784; CHECK-LABEL: @urem_i32_oddk_denom(
5785; CHECK-NEXT:    [[R:%.*]] = urem i32 [[X:%.*]], 1235195
5786; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
5787; CHECK-NEXT:    ret void
5788;
5789; GFX6-LABEL: urem_i32_oddk_denom:
5790; GFX6:       ; %bb.0:
5791; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
5792; GFX6-NEXT:    v_mov_b32_e32 v0, 0xb2a50881
5793; GFX6-NEXT:    s_mov_b32 s2, 0x12d8fb
5794; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
5795; GFX6-NEXT:    s_mov_b32 s3, 0xf000
5796; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5797; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
5798; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s4, v0
5799; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
5800; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
5801; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 20, v0
5802; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
5803; GFX6-NEXT:    s_mov_b32 s2, -1
5804; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
5805; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
5806; GFX6-NEXT:    s_endpgm
5807;
5808; GFX9-LABEL: urem_i32_oddk_denom:
5809; GFX9:       ; %bb.0:
5810; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
5811; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
5812; GFX9-NEXT:    v_mov_b32_e32 v0, 0
5813; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5814; GFX9-NEXT:    s_mul_hi_u32 s0, s4, 0xb2a50881
5815; GFX9-NEXT:    s_sub_i32 s1, s4, s0
5816; GFX9-NEXT:    s_lshr_b32 s1, s1, 1
5817; GFX9-NEXT:    s_add_i32 s1, s1, s0
5818; GFX9-NEXT:    s_lshr_b32 s0, s1, 20
5819; GFX9-NEXT:    s_mul_i32 s0, s0, 0x12d8fb
5820; GFX9-NEXT:    s_sub_i32 s0, s4, s0
5821; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5822; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
5823; GFX9-NEXT:    s_endpgm
5824  %r = urem i32 %x, 1235195
5825  store i32 %r, i32 addrspace(1)* %out
5826  ret void
5827}
5828
5829define amdgpu_kernel void @urem_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x) {
5830; CHECK-LABEL: @urem_i32_pow2k_denom(
5831; CHECK-NEXT:    [[R:%.*]] = urem i32 [[X:%.*]], 4096
5832; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
5833; CHECK-NEXT:    ret void
5834;
5835; GFX6-LABEL: urem_i32_pow2k_denom:
5836; GFX6:       ; %bb.0:
5837; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
5838; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
5839; GFX6-NEXT:    s_mov_b32 s3, 0xf000
5840; GFX6-NEXT:    s_mov_b32 s2, -1
5841; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5842; GFX6-NEXT:    s_and_b32 s4, s4, 0xfff
5843; GFX6-NEXT:    v_mov_b32_e32 v0, s4
5844; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
5845; GFX6-NEXT:    s_endpgm
5846;
5847; GFX9-LABEL: urem_i32_pow2k_denom:
5848; GFX9:       ; %bb.0:
5849; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
5850; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
5851; GFX9-NEXT:    v_mov_b32_e32 v0, 0
5852; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5853; GFX9-NEXT:    s_and_b32 s0, s4, 0xfff
5854; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5855; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
5856; GFX9-NEXT:    s_endpgm
5857  %r = urem i32 %x, 4096
5858  store i32 %r, i32 addrspace(1)* %out
5859  ret void
5860}
5861
5862define amdgpu_kernel void @urem_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %x, i32 %y) {
5863; CHECK-LABEL: @urem_i32_pow2_shl_denom(
5864; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]]
5865; CHECK-NEXT:    [[R:%.*]] = urem i32 [[X:%.*]], [[SHL_Y]]
5866; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
5867; CHECK-NEXT:    ret void
5868;
5869; GFX6-LABEL: urem_i32_pow2_shl_denom:
5870; GFX6:       ; %bb.0:
5871; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
5872; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
5873; GFX6-NEXT:    s_mov_b32 s3, 0xf000
5874; GFX6-NEXT:    s_mov_b32 s2, -1
5875; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5876; GFX6-NEXT:    s_lshl_b32 s5, 0x1000, s5
5877; GFX6-NEXT:    s_add_i32 s5, s5, -1
5878; GFX6-NEXT:    s_and_b32 s4, s4, s5
5879; GFX6-NEXT:    v_mov_b32_e32 v0, s4
5880; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
5881; GFX6-NEXT:    s_endpgm
5882;
5883; GFX9-LABEL: urem_i32_pow2_shl_denom:
5884; GFX9:       ; %bb.0:
5885; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
5886; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
5887; GFX9-NEXT:    v_mov_b32_e32 v0, 0
5888; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5889; GFX9-NEXT:    s_lshl_b32 s0, 0x1000, s3
5890; GFX9-NEXT:    s_add_i32 s0, s0, -1
5891; GFX9-NEXT:    s_and_b32 s0, s2, s0
5892; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5893; GFX9-NEXT:    global_store_dword v0, v1, s[4:5]
5894; GFX9-NEXT:    s_endpgm
5895  %shl.y = shl i32 4096, %y
5896  %r = urem i32 %x, %shl.y
5897  store i32 %r, i32 addrspace(1)* %out
5898  ret void
5899}
5900
5901define amdgpu_kernel void @urem_v2i32_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) {
5902; CHECK-LABEL: @urem_v2i32_pow2k_denom(
5903; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
5904; CHECK-NEXT:    [[TMP2:%.*]] = urem i32 [[TMP1]], 4096
5905; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0
5906; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1
5907; CHECK-NEXT:    [[TMP5:%.*]] = urem i32 [[TMP4]], 4096
5908; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1
5909; CHECK-NEXT:    store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
5910; CHECK-NEXT:    ret void
5911;
5912; GFX6-LABEL: urem_v2i32_pow2k_denom:
5913; GFX6:       ; %bb.0:
5914; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
5915; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
5916; GFX6-NEXT:    s_movk_i32 s6, 0xfff
5917; GFX6-NEXT:    s_mov_b32 s3, 0xf000
5918; GFX6-NEXT:    s_mov_b32 s2, -1
5919; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
5920; GFX6-NEXT:    s_and_b32 s4, s4, s6
5921; GFX6-NEXT:    s_and_b32 s5, s5, s6
5922; GFX6-NEXT:    v_mov_b32_e32 v0, s4
5923; GFX6-NEXT:    v_mov_b32_e32 v1, s5
5924; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
5925; GFX6-NEXT:    s_endpgm
5926;
5927; GFX9-LABEL: urem_v2i32_pow2k_denom:
5928; GFX9:       ; %bb.0:
5929; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
5930; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
5931; GFX9-NEXT:    s_movk_i32 s0, 0xfff
5932; GFX9-NEXT:    v_mov_b32_e32 v2, 0
5933; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
5934; GFX9-NEXT:    s_and_b32 s1, s2, s0
5935; GFX9-NEXT:    s_and_b32 s0, s3, s0
5936; GFX9-NEXT:    v_mov_b32_e32 v0, s1
5937; GFX9-NEXT:    v_mov_b32_e32 v1, s0
5938; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
5939; GFX9-NEXT:    s_endpgm
5940  %r = urem <2 x i32> %x, <i32 4096, i32 4096>
5941  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
5942  ret void
5943}
5944
5945define amdgpu_kernel void @urem_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) {
5946; CHECK-LABEL: @urem_v2i32_pow2_shl_denom(
5947; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i32> <i32 4096, i32 4096>, [[Y:%.*]]
5948; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
5949; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 0
5950; CHECK-NEXT:    [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float
5951; CHECK-NEXT:    [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])
5952; CHECK-NEXT:    [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41EFFFFFC0000000
5953; CHECK-NEXT:    [[TMP6:%.*]] = fptoui float [[TMP5]] to i32
5954; CHECK-NEXT:    [[TMP7:%.*]] = sub i32 0, [[TMP2]]
5955; CHECK-NEXT:    [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP6]]
5956; CHECK-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP6]] to i64
5957; CHECK-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP8]] to i64
5958; CHECK-NEXT:    [[TMP11:%.*]] = mul i64 [[TMP9]], [[TMP10]]
5959; CHECK-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
5960; CHECK-NEXT:    [[TMP13:%.*]] = lshr i64 [[TMP11]], 32
5961; CHECK-NEXT:    [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32
5962; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP6]], [[TMP14]]
5963; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP1]] to i64
5964; CHECK-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP15]] to i64
5965; CHECK-NEXT:    [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]
5966; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
5967; CHECK-NEXT:    [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
5968; CHECK-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
5969; CHECK-NEXT:    [[TMP22:%.*]] = mul i32 [[TMP21]], [[TMP2]]
5970; CHECK-NEXT:    [[TMP23:%.*]] = sub i32 [[TMP1]], [[TMP22]]
5971; CHECK-NEXT:    [[TMP24:%.*]] = icmp uge i32 [[TMP23]], [[TMP2]]
5972; CHECK-NEXT:    [[TMP25:%.*]] = sub i32 [[TMP23]], [[TMP2]]
5973; CHECK-NEXT:    [[TMP26:%.*]] = select i1 [[TMP24]], i32 [[TMP25]], i32 [[TMP23]]
5974; CHECK-NEXT:    [[TMP27:%.*]] = icmp uge i32 [[TMP26]], [[TMP2]]
5975; CHECK-NEXT:    [[TMP28:%.*]] = sub i32 [[TMP26]], [[TMP2]]
5976; CHECK-NEXT:    [[TMP29:%.*]] = select i1 [[TMP27]], i32 [[TMP28]], i32 [[TMP26]]
5977; CHECK-NEXT:    [[TMP30:%.*]] = insertelement <2 x i32> undef, i32 [[TMP29]], i64 0
5978; CHECK-NEXT:    [[TMP31:%.*]] = extractelement <2 x i32> [[X]], i64 1
5979; CHECK-NEXT:    [[TMP32:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1
5980; CHECK-NEXT:    [[TMP33:%.*]] = uitofp i32 [[TMP32]] to float
5981; CHECK-NEXT:    [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])
5982; CHECK-NEXT:    [[TMP35:%.*]] = fmul fast float [[TMP34]], 0x41EFFFFFC0000000
5983; CHECK-NEXT:    [[TMP36:%.*]] = fptoui float [[TMP35]] to i32
5984; CHECK-NEXT:    [[TMP37:%.*]] = sub i32 0, [[TMP32]]
5985; CHECK-NEXT:    [[TMP38:%.*]] = mul i32 [[TMP37]], [[TMP36]]
5986; CHECK-NEXT:    [[TMP39:%.*]] = zext i32 [[TMP36]] to i64
5987; CHECK-NEXT:    [[TMP40:%.*]] = zext i32 [[TMP38]] to i64
5988; CHECK-NEXT:    [[TMP41:%.*]] = mul i64 [[TMP39]], [[TMP40]]
5989; CHECK-NEXT:    [[TMP42:%.*]] = trunc i64 [[TMP41]] to i32
5990; CHECK-NEXT:    [[TMP43:%.*]] = lshr i64 [[TMP41]], 32
5991; CHECK-NEXT:    [[TMP44:%.*]] = trunc i64 [[TMP43]] to i32
5992; CHECK-NEXT:    [[TMP45:%.*]] = add i32 [[TMP36]], [[TMP44]]
5993; CHECK-NEXT:    [[TMP46:%.*]] = zext i32 [[TMP31]] to i64
5994; CHECK-NEXT:    [[TMP47:%.*]] = zext i32 [[TMP45]] to i64
5995; CHECK-NEXT:    [[TMP48:%.*]] = mul i64 [[TMP46]], [[TMP47]]
5996; CHECK-NEXT:    [[TMP49:%.*]] = trunc i64 [[TMP48]] to i32
5997; CHECK-NEXT:    [[TMP50:%.*]] = lshr i64 [[TMP48]], 32
5998; CHECK-NEXT:    [[TMP51:%.*]] = trunc i64 [[TMP50]] to i32
5999; CHECK-NEXT:    [[TMP52:%.*]] = mul i32 [[TMP51]], [[TMP32]]
6000; CHECK-NEXT:    [[TMP53:%.*]] = sub i32 [[TMP31]], [[TMP52]]
6001; CHECK-NEXT:    [[TMP54:%.*]] = icmp uge i32 [[TMP53]], [[TMP32]]
6002; CHECK-NEXT:    [[TMP55:%.*]] = sub i32 [[TMP53]], [[TMP32]]
6003; CHECK-NEXT:    [[TMP56:%.*]] = select i1 [[TMP54]], i32 [[TMP55]], i32 [[TMP53]]
6004; CHECK-NEXT:    [[TMP57:%.*]] = icmp uge i32 [[TMP56]], [[TMP32]]
6005; CHECK-NEXT:    [[TMP58:%.*]] = sub i32 [[TMP56]], [[TMP32]]
6006; CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP57]], i32 [[TMP58]], i32 [[TMP56]]
6007; CHECK-NEXT:    [[TMP60:%.*]] = insertelement <2 x i32> [[TMP30]], i32 [[TMP59]], i64 1
6008; CHECK-NEXT:    store <2 x i32> [[TMP60]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
6009; CHECK-NEXT:    ret void
6010;
6011; GFX6-LABEL: urem_v2i32_pow2_shl_denom:
6012; GFX6:       ; %bb.0:
6013; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
6014; GFX6-NEXT:    s_movk_i32 s2, 0x1000
6015; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6016; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6017; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6018; GFX6-NEXT:    s_lshl_b32 s6, s2, s6
6019; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s6
6020; GFX6-NEXT:    s_lshl_b32 s7, s2, s7
6021; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s7
6022; GFX6-NEXT:    s_mov_b32 s2, 0x4f7ffffe
6023; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6024; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
6025; GFX6-NEXT:    v_mul_f32_e32 v0, s2, v0
6026; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
6027; GFX6-NEXT:    v_mul_f32_e32 v1, s2, v1
6028; GFX6-NEXT:    s_sub_i32 s2, 0, s6
6029; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
6030; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
6031; GFX6-NEXT:    s_sub_i32 s2, 0, s7
6032; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v1
6033; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
6034; GFX6-NEXT:    s_mov_b32 s2, -1
6035; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
6036; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
6037; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
6038; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
6039; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
6040; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s6
6041; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s7
6042; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
6043; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s6, v0
6044; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
6045; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
6046; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s6, v0
6047; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
6048; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
6049; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
6050; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s7, v1
6051; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
6052; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
6053; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s7, v1
6054; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
6055; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
6056; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
6057; GFX6-NEXT:    s_endpgm
6058;
6059; GFX9-LABEL: urem_v2i32_pow2_shl_denom:
6060; GFX9:       ; %bb.0:
6061; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
6062; GFX9-NEXT:    s_movk_i32 s2, 0x1000
6063; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
6064; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6065; GFX9-NEXT:    s_lshl_b32 s3, s2, s7
6066; GFX9-NEXT:    s_lshl_b32 s2, s2, s6
6067; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s2
6068; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s3
6069; GFX9-NEXT:    s_mov_b32 s6, 0x4f7ffffe
6070; GFX9-NEXT:    s_sub_i32 s7, 0, s3
6071; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6072; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
6073; GFX9-NEXT:    v_mul_f32_e32 v0, s6, v0
6074; GFX9-NEXT:    v_mul_f32_e32 v1, s6, v1
6075; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
6076; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
6077; GFX9-NEXT:    s_sub_i32 s6, 0, s2
6078; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v0
6079; GFX9-NEXT:    v_mul_lo_u32 v3, s7, v1
6080; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
6081; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
6082; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
6083; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
6084; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
6085; GFX9-NEXT:    v_mul_hi_u32 v1, s5, v1
6086; GFX9-NEXT:    v_mov_b32_e32 v2, 0
6087; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s2
6088; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s3
6089; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
6090; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v1
6091; GFX9-NEXT:    v_subrev_u32_e32 v3, s2, v0
6092; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v0
6093; GFX9-NEXT:    v_subrev_u32_e32 v4, s3, v1
6094; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
6095; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
6096; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
6097; GFX9-NEXT:    v_subrev_u32_e32 v3, s2, v0
6098; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v0
6099; GFX9-NEXT:    v_subrev_u32_e32 v4, s3, v1
6100; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
6101; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
6102; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
6103; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
6104; GFX9-NEXT:    s_endpgm
6105  %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
6106  %r = urem <2 x i32> %x, %shl.y
6107  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
6108  ret void
6109}
6110
6111define amdgpu_kernel void @sdiv_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
6112; CHECK-LABEL: @sdiv_i32_oddk_denom(
6113; CHECK-NEXT:    [[R:%.*]] = sdiv i32 [[X:%.*]], 1235195
6114; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
6115; CHECK-NEXT:    ret void
6116;
6117; GFX6-LABEL: sdiv_i32_oddk_denom:
6118; GFX6:       ; %bb.0:
6119; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
6120; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6121; GFX6-NEXT:    v_mov_b32_e32 v0, 0xd9528441
6122; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6123; GFX6-NEXT:    s_mov_b32 s2, -1
6124; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6125; GFX6-NEXT:    v_mul_hi_i32 v0, s4, v0
6126; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s4, v0
6127; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 31, v0
6128; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 20, v0
6129; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
6130; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
6131; GFX6-NEXT:    s_endpgm
6132;
6133; GFX9-LABEL: sdiv_i32_oddk_denom:
6134; GFX9:       ; %bb.0:
6135; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
6136; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
6137; GFX9-NEXT:    v_mov_b32_e32 v0, 0
6138; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6139; GFX9-NEXT:    s_mul_hi_i32 s0, s4, 0xd9528441
6140; GFX9-NEXT:    s_add_i32 s0, s0, s4
6141; GFX9-NEXT:    s_lshr_b32 s1, s0, 31
6142; GFX9-NEXT:    s_ashr_i32 s0, s0, 20
6143; GFX9-NEXT:    s_add_i32 s0, s0, s1
6144; GFX9-NEXT:    v_mov_b32_e32 v1, s0
6145; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
6146; GFX9-NEXT:    s_endpgm
6147  %r = sdiv i32 %x, 1235195
6148  store i32 %r, i32 addrspace(1)* %out
6149  ret void
6150}
6151
6152define amdgpu_kernel void @sdiv_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x) {
6153; CHECK-LABEL: @sdiv_i32_pow2k_denom(
6154; CHECK-NEXT:    [[R:%.*]] = sdiv i32 [[X:%.*]], 4096
6155; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
6156; CHECK-NEXT:    ret void
6157;
6158; GFX6-LABEL: sdiv_i32_pow2k_denom:
6159; GFX6:       ; %bb.0:
6160; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
6161; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6162; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6163; GFX6-NEXT:    s_mov_b32 s2, -1
6164; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6165; GFX6-NEXT:    s_ashr_i32 s5, s4, 31
6166; GFX6-NEXT:    s_lshr_b32 s5, s5, 20
6167; GFX6-NEXT:    s_add_i32 s4, s4, s5
6168; GFX6-NEXT:    s_ashr_i32 s4, s4, 12
6169; GFX6-NEXT:    v_mov_b32_e32 v0, s4
6170; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
6171; GFX6-NEXT:    s_endpgm
6172;
6173; GFX9-LABEL: sdiv_i32_pow2k_denom:
6174; GFX9:       ; %bb.0:
6175; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
6176; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
6177; GFX9-NEXT:    v_mov_b32_e32 v0, 0
6178; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6179; GFX9-NEXT:    s_ashr_i32 s0, s4, 31
6180; GFX9-NEXT:    s_lshr_b32 s0, s0, 20
6181; GFX9-NEXT:    s_add_i32 s4, s4, s0
6182; GFX9-NEXT:    s_ashr_i32 s0, s4, 12
6183; GFX9-NEXT:    v_mov_b32_e32 v1, s0
6184; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
6185; GFX9-NEXT:    s_endpgm
6186  %r = sdiv i32 %x, 4096
6187  store i32 %r, i32 addrspace(1)* %out
6188  ret void
6189}
6190
6191define amdgpu_kernel void @sdiv_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %x, i32 %y) {
6192; CHECK-LABEL: @sdiv_i32_pow2_shl_denom(
6193; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]]
6194; CHECK-NEXT:    [[R:%.*]] = sdiv i32 [[X:%.*]], [[SHL_Y]]
6195; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
6196; CHECK-NEXT:    ret void
6197;
6198; GFX6-LABEL: sdiv_i32_pow2_shl_denom:
6199; GFX6:       ; %bb.0:
6200; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
6201; GFX6-NEXT:    s_mov_b32 s7, 0xf000
6202; GFX6-NEXT:    s_mov_b32 s6, -1
6203; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6204; GFX6-NEXT:    s_lshl_b32 s3, 0x1000, s3
6205; GFX6-NEXT:    s_ashr_i32 s8, s3, 31
6206; GFX6-NEXT:    s_add_i32 s3, s3, s8
6207; GFX6-NEXT:    s_xor_b32 s3, s3, s8
6208; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s3
6209; GFX6-NEXT:    s_sub_i32 s4, 0, s3
6210; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6211; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
6212; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
6213; GFX6-NEXT:    v_mul_lo_u32 v1, s4, v0
6214; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
6215; GFX6-NEXT:    s_ashr_i32 s0, s2, 31
6216; GFX6-NEXT:    s_add_i32 s1, s2, s0
6217; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
6218; GFX6-NEXT:    s_xor_b32 s1, s1, s0
6219; GFX6-NEXT:    s_xor_b32 s2, s0, s8
6220; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
6221; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
6222; GFX6-NEXT:    v_mul_lo_u32 v1, v0, s3
6223; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
6224; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v1
6225; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v1
6226; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
6227; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v1
6228; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
6229; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[0:1]
6230; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
6231; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
6232; GFX6-NEXT:    v_xor_b32_e32 v0, s2, v0
6233; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
6234; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6235; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
6236; GFX6-NEXT:    s_endpgm
6237;
6238; GFX9-LABEL: sdiv_i32_pow2_shl_denom:
6239; GFX9:       ; %bb.0:
6240; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
6241; GFX9-NEXT:    v_mov_b32_e32 v2, 0
6242; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
6243; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6244; GFX9-NEXT:    s_lshl_b32 s3, 0x1000, s3
6245; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
6246; GFX9-NEXT:    s_add_i32 s3, s3, s4
6247; GFX9-NEXT:    s_xor_b32 s3, s3, s4
6248; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
6249; GFX9-NEXT:    s_sub_i32 s5, 0, s3
6250; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6251; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
6252; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
6253; GFX9-NEXT:    v_mul_lo_u32 v1, s5, v0
6254; GFX9-NEXT:    s_ashr_i32 s5, s2, 31
6255; GFX9-NEXT:    s_add_i32 s2, s2, s5
6256; GFX9-NEXT:    s_xor_b32 s2, s2, s5
6257; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
6258; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
6259; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
6260; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s3
6261; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
6262; GFX9-NEXT:    v_sub_u32_e32 v1, s2, v1
6263; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
6264; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
6265; GFX9-NEXT:    v_subrev_u32_e32 v3, s3, v1
6266; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
6267; GFX9-NEXT:    v_add_u32_e32 v4, 1, v0
6268; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
6269; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
6270; GFX9-NEXT:    s_xor_b32 s2, s5, s4
6271; GFX9-NEXT:    v_xor_b32_e32 v0, s2, v0
6272; GFX9-NEXT:    v_subrev_u32_e32 v0, s2, v0
6273; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]
6274; GFX9-NEXT:    s_endpgm
6275  %shl.y = shl i32 4096, %y
6276  %r = sdiv i32 %x, %shl.y
6277  store i32 %r, i32 addrspace(1)* %out
6278  ret void
6279}
6280
6281define amdgpu_kernel void @sdiv_v2i32_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) {
6282; CHECK-LABEL: @sdiv_v2i32_pow2k_denom(
6283; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
6284; CHECK-NEXT:    [[TMP2:%.*]] = sdiv i32 [[TMP1]], 4096
6285; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0
6286; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1
6287; CHECK-NEXT:    [[TMP5:%.*]] = sdiv i32 [[TMP4]], 4096
6288; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1
6289; CHECK-NEXT:    store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
6290; CHECK-NEXT:    ret void
6291;
6292; GFX6-LABEL: sdiv_v2i32_pow2k_denom:
6293; GFX6:       ; %bb.0:
6294; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
6295; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6296; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6297; GFX6-NEXT:    s_mov_b32 s2, -1
6298; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6299; GFX6-NEXT:    s_ashr_i32 s6, s4, 31
6300; GFX6-NEXT:    s_ashr_i32 s7, s5, 31
6301; GFX6-NEXT:    s_lshr_b32 s6, s6, 20
6302; GFX6-NEXT:    s_add_i32 s4, s4, s6
6303; GFX6-NEXT:    s_lshr_b32 s6, s7, 20
6304; GFX6-NEXT:    s_add_i32 s5, s5, s6
6305; GFX6-NEXT:    s_ashr_i32 s4, s4, 12
6306; GFX6-NEXT:    s_ashr_i32 s5, s5, 12
6307; GFX6-NEXT:    v_mov_b32_e32 v0, s4
6308; GFX6-NEXT:    v_mov_b32_e32 v1, s5
6309; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
6310; GFX6-NEXT:    s_endpgm
6311;
6312; GFX9-LABEL: sdiv_v2i32_pow2k_denom:
6313; GFX9:       ; %bb.0:
6314; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
6315; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
6316; GFX9-NEXT:    v_mov_b32_e32 v2, 0
6317; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6318; GFX9-NEXT:    s_ashr_i32 s0, s2, 31
6319; GFX9-NEXT:    s_ashr_i32 s1, s3, 31
6320; GFX9-NEXT:    s_lshr_b32 s0, s0, 20
6321; GFX9-NEXT:    s_lshr_b32 s1, s1, 20
6322; GFX9-NEXT:    s_add_i32 s0, s2, s0
6323; GFX9-NEXT:    s_add_i32 s1, s3, s1
6324; GFX9-NEXT:    s_ashr_i32 s0, s0, 12
6325; GFX9-NEXT:    s_ashr_i32 s1, s1, 12
6326; GFX9-NEXT:    v_mov_b32_e32 v0, s0
6327; GFX9-NEXT:    v_mov_b32_e32 v1, s1
6328; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
6329; GFX9-NEXT:    s_endpgm
6330  %r = sdiv <2 x i32> %x, <i32 4096, i32 4096>
6331  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
6332  ret void
6333}
6334
6335define amdgpu_kernel void @ssdiv_v2i32_mixed_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) {
6336; CHECK-LABEL: @ssdiv_v2i32_mixed_pow2k_denom(
6337; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
6338; CHECK-NEXT:    [[TMP2:%.*]] = sdiv i32 [[TMP1]], 4096
6339; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0
6340; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1
6341; CHECK-NEXT:    [[TMP5:%.*]] = sdiv i32 [[TMP4]], 4095
6342; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1
6343; CHECK-NEXT:    store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
6344; CHECK-NEXT:    ret void
6345;
6346; GFX6-LABEL: ssdiv_v2i32_mixed_pow2k_denom:
6347; GFX6:       ; %bb.0:
6348; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
6349; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6350; GFX6-NEXT:    v_mov_b32_e32 v0, 0x80080081
6351; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6352; GFX6-NEXT:    s_mov_b32 s2, -1
6353; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6354; GFX6-NEXT:    v_mul_hi_i32 v0, s5, v0
6355; GFX6-NEXT:    s_ashr_i32 s6, s4, 31
6356; GFX6-NEXT:    s_lshr_b32 s6, s6, 20
6357; GFX6-NEXT:    s_add_i32 s4, s4, s6
6358; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s5, v0
6359; GFX6-NEXT:    s_ashr_i32 s4, s4, 12
6360; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 31, v0
6361; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 11, v0
6362; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v0
6363; GFX6-NEXT:    v_mov_b32_e32 v0, s4
6364; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
6365; GFX6-NEXT:    s_endpgm
6366;
6367; GFX9-LABEL: ssdiv_v2i32_mixed_pow2k_denom:
6368; GFX9:       ; %bb.0:
6369; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
6370; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
6371; GFX9-NEXT:    v_mov_b32_e32 v2, 0
6372; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6373; GFX9-NEXT:    s_ashr_i32 s0, s2, 31
6374; GFX9-NEXT:    s_mul_hi_i32 s1, s3, 0x80080081
6375; GFX9-NEXT:    s_lshr_b32 s0, s0, 20
6376; GFX9-NEXT:    s_add_i32 s1, s1, s3
6377; GFX9-NEXT:    s_add_i32 s0, s2, s0
6378; GFX9-NEXT:    s_lshr_b32 s2, s1, 31
6379; GFX9-NEXT:    s_ashr_i32 s1, s1, 11
6380; GFX9-NEXT:    s_ashr_i32 s0, s0, 12
6381; GFX9-NEXT:    s_add_i32 s1, s1, s2
6382; GFX9-NEXT:    v_mov_b32_e32 v0, s0
6383; GFX9-NEXT:    v_mov_b32_e32 v1, s1
6384; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
6385; GFX9-NEXT:    s_endpgm
6386  %r = sdiv <2 x i32> %x, <i32 4096, i32 4095>
6387  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
6388  ret void
6389}
6390
6391define amdgpu_kernel void @sdiv_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) {
6392; CHECK-LABEL: @sdiv_v2i32_pow2_shl_denom(
6393; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i32> <i32 4096, i32 4096>, [[Y:%.*]]
6394; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
6395; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 0
6396; CHECK-NEXT:    [[TMP3:%.*]] = ashr i32 [[TMP1]], 31
6397; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP2]], 31
6398; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
6399; CHECK-NEXT:    [[TMP6:%.*]] = add i32 [[TMP1]], [[TMP3]]
6400; CHECK-NEXT:    [[TMP7:%.*]] = add i32 [[TMP2]], [[TMP4]]
6401; CHECK-NEXT:    [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP3]]
6402; CHECK-NEXT:    [[TMP9:%.*]] = xor i32 [[TMP7]], [[TMP4]]
6403; CHECK-NEXT:    [[TMP10:%.*]] = uitofp i32 [[TMP9]] to float
6404; CHECK-NEXT:    [[TMP11:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP10]])
6405; CHECK-NEXT:    [[TMP12:%.*]] = fmul fast float [[TMP11]], 0x41EFFFFFC0000000
6406; CHECK-NEXT:    [[TMP13:%.*]] = fptoui float [[TMP12]] to i32
6407; CHECK-NEXT:    [[TMP14:%.*]] = sub i32 0, [[TMP9]]
6408; CHECK-NEXT:    [[TMP15:%.*]] = mul i32 [[TMP14]], [[TMP13]]
6409; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP13]] to i64
6410; CHECK-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP15]] to i64
6411; CHECK-NEXT:    [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]
6412; CHECK-NEXT:    [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
6413; CHECK-NEXT:    [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
6414; CHECK-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
6415; CHECK-NEXT:    [[TMP22:%.*]] = add i32 [[TMP13]], [[TMP21]]
6416; CHECK-NEXT:    [[TMP23:%.*]] = zext i32 [[TMP8]] to i64
6417; CHECK-NEXT:    [[TMP24:%.*]] = zext i32 [[TMP22]] to i64
6418; CHECK-NEXT:    [[TMP25:%.*]] = mul i64 [[TMP23]], [[TMP24]]
6419; CHECK-NEXT:    [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32
6420; CHECK-NEXT:    [[TMP27:%.*]] = lshr i64 [[TMP25]], 32
6421; CHECK-NEXT:    [[TMP28:%.*]] = trunc i64 [[TMP27]] to i32
6422; CHECK-NEXT:    [[TMP29:%.*]] = mul i32 [[TMP28]], [[TMP9]]
6423; CHECK-NEXT:    [[TMP30:%.*]] = sub i32 [[TMP8]], [[TMP29]]
6424; CHECK-NEXT:    [[TMP31:%.*]] = icmp uge i32 [[TMP30]], [[TMP9]]
6425; CHECK-NEXT:    [[TMP32:%.*]] = add i32 [[TMP28]], 1
6426; CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP31]], i32 [[TMP32]], i32 [[TMP28]]
6427; CHECK-NEXT:    [[TMP34:%.*]] = sub i32 [[TMP30]], [[TMP9]]
6428; CHECK-NEXT:    [[TMP35:%.*]] = select i1 [[TMP31]], i32 [[TMP34]], i32 [[TMP30]]
6429; CHECK-NEXT:    [[TMP36:%.*]] = icmp uge i32 [[TMP35]], [[TMP9]]
6430; CHECK-NEXT:    [[TMP37:%.*]] = add i32 [[TMP33]], 1
6431; CHECK-NEXT:    [[TMP38:%.*]] = select i1 [[TMP36]], i32 [[TMP37]], i32 [[TMP33]]
6432; CHECK-NEXT:    [[TMP39:%.*]] = xor i32 [[TMP38]], [[TMP5]]
6433; CHECK-NEXT:    [[TMP40:%.*]] = sub i32 [[TMP39]], [[TMP5]]
6434; CHECK-NEXT:    [[TMP41:%.*]] = insertelement <2 x i32> undef, i32 [[TMP40]], i64 0
6435; CHECK-NEXT:    [[TMP42:%.*]] = extractelement <2 x i32> [[X]], i64 1
6436; CHECK-NEXT:    [[TMP43:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1
6437; CHECK-NEXT:    [[TMP44:%.*]] = ashr i32 [[TMP42]], 31
6438; CHECK-NEXT:    [[TMP45:%.*]] = ashr i32 [[TMP43]], 31
6439; CHECK-NEXT:    [[TMP46:%.*]] = xor i32 [[TMP44]], [[TMP45]]
6440; CHECK-NEXT:    [[TMP47:%.*]] = add i32 [[TMP42]], [[TMP44]]
6441; CHECK-NEXT:    [[TMP48:%.*]] = add i32 [[TMP43]], [[TMP45]]
6442; CHECK-NEXT:    [[TMP49:%.*]] = xor i32 [[TMP47]], [[TMP44]]
6443; CHECK-NEXT:    [[TMP50:%.*]] = xor i32 [[TMP48]], [[TMP45]]
6444; CHECK-NEXT:    [[TMP51:%.*]] = uitofp i32 [[TMP50]] to float
6445; CHECK-NEXT:    [[TMP52:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP51]])
6446; CHECK-NEXT:    [[TMP53:%.*]] = fmul fast float [[TMP52]], 0x41EFFFFFC0000000
6447; CHECK-NEXT:    [[TMP54:%.*]] = fptoui float [[TMP53]] to i32
6448; CHECK-NEXT:    [[TMP55:%.*]] = sub i32 0, [[TMP50]]
6449; CHECK-NEXT:    [[TMP56:%.*]] = mul i32 [[TMP55]], [[TMP54]]
6450; CHECK-NEXT:    [[TMP57:%.*]] = zext i32 [[TMP54]] to i64
6451; CHECK-NEXT:    [[TMP58:%.*]] = zext i32 [[TMP56]] to i64
6452; CHECK-NEXT:    [[TMP59:%.*]] = mul i64 [[TMP57]], [[TMP58]]
6453; CHECK-NEXT:    [[TMP60:%.*]] = trunc i64 [[TMP59]] to i32
6454; CHECK-NEXT:    [[TMP61:%.*]] = lshr i64 [[TMP59]], 32
6455; CHECK-NEXT:    [[TMP62:%.*]] = trunc i64 [[TMP61]] to i32
6456; CHECK-NEXT:    [[TMP63:%.*]] = add i32 [[TMP54]], [[TMP62]]
6457; CHECK-NEXT:    [[TMP64:%.*]] = zext i32 [[TMP49]] to i64
6458; CHECK-NEXT:    [[TMP65:%.*]] = zext i32 [[TMP63]] to i64
6459; CHECK-NEXT:    [[TMP66:%.*]] = mul i64 [[TMP64]], [[TMP65]]
6460; CHECK-NEXT:    [[TMP67:%.*]] = trunc i64 [[TMP66]] to i32
6461; CHECK-NEXT:    [[TMP68:%.*]] = lshr i64 [[TMP66]], 32
6462; CHECK-NEXT:    [[TMP69:%.*]] = trunc i64 [[TMP68]] to i32
6463; CHECK-NEXT:    [[TMP70:%.*]] = mul i32 [[TMP69]], [[TMP50]]
6464; CHECK-NEXT:    [[TMP71:%.*]] = sub i32 [[TMP49]], [[TMP70]]
6465; CHECK-NEXT:    [[TMP72:%.*]] = icmp uge i32 [[TMP71]], [[TMP50]]
6466; CHECK-NEXT:    [[TMP73:%.*]] = add i32 [[TMP69]], 1
6467; CHECK-NEXT:    [[TMP74:%.*]] = select i1 [[TMP72]], i32 [[TMP73]], i32 [[TMP69]]
6468; CHECK-NEXT:    [[TMP75:%.*]] = sub i32 [[TMP71]], [[TMP50]]
6469; CHECK-NEXT:    [[TMP76:%.*]] = select i1 [[TMP72]], i32 [[TMP75]], i32 [[TMP71]]
6470; CHECK-NEXT:    [[TMP77:%.*]] = icmp uge i32 [[TMP76]], [[TMP50]]
6471; CHECK-NEXT:    [[TMP78:%.*]] = add i32 [[TMP74]], 1
6472; CHECK-NEXT:    [[TMP79:%.*]] = select i1 [[TMP77]], i32 [[TMP78]], i32 [[TMP74]]
6473; CHECK-NEXT:    [[TMP80:%.*]] = xor i32 [[TMP79]], [[TMP46]]
6474; CHECK-NEXT:    [[TMP81:%.*]] = sub i32 [[TMP80]], [[TMP46]]
6475; CHECK-NEXT:    [[TMP82:%.*]] = insertelement <2 x i32> [[TMP41]], i32 [[TMP81]], i64 1
6476; CHECK-NEXT:    store <2 x i32> [[TMP82]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
6477; CHECK-NEXT:    ret void
6478;
6479; GFX6-LABEL: sdiv_v2i32_pow2_shl_denom:
6480; GFX6:       ; %bb.0:
6481; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
6482; GFX6-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x9
6483; GFX6-NEXT:    s_movk_i32 s2, 0x1000
6484; GFX6-NEXT:    s_mov_b32 s12, 0x4f7ffffe
6485; GFX6-NEXT:    s_mov_b32 s11, 0xf000
6486; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6487; GFX6-NEXT:    s_lshl_b32 s3, s2, s6
6488; GFX6-NEXT:    s_ashr_i32 s6, s3, 31
6489; GFX6-NEXT:    s_add_i32 s3, s3, s6
6490; GFX6-NEXT:    s_xor_b32 s3, s3, s6
6491; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s3
6492; GFX6-NEXT:    s_lshl_b32 s0, s2, s7
6493; GFX6-NEXT:    s_sub_i32 s7, 0, s3
6494; GFX6-NEXT:    s_ashr_i32 s2, s0, 31
6495; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6496; GFX6-NEXT:    s_add_i32 s0, s0, s2
6497; GFX6-NEXT:    s_ashr_i32 s1, s4, 31
6498; GFX6-NEXT:    s_mov_b32 s10, -1
6499; GFX6-NEXT:    v_mul_f32_e32 v0, s12, v0
6500; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
6501; GFX6-NEXT:    v_mul_lo_u32 v1, s7, v0
6502; GFX6-NEXT:    s_xor_b32 s7, s0, s2
6503; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s7
6504; GFX6-NEXT:    s_add_i32 s0, s4, s1
6505; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
6506; GFX6-NEXT:    s_xor_b32 s0, s0, s1
6507; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
6508; GFX6-NEXT:    s_xor_b32 s4, s1, s6
6509; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
6510; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
6511; GFX6-NEXT:    v_mul_f32_e32 v1, s12, v2
6512; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
6513; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s3
6514; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
6515; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s0, v2
6516; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v2
6517; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[0:1]
6518; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s3, v2
6519; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
6520; GFX6-NEXT:    s_sub_i32 s0, 0, s7
6521; GFX6-NEXT:    v_mul_lo_u32 v3, s0, v1
6522; GFX6-NEXT:    s_ashr_i32 s0, s5, 31
6523; GFX6-NEXT:    s_add_i32 s1, s5, s0
6524; GFX6-NEXT:    s_xor_b32 s1, s1, s0
6525; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
6526; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
6527; GFX6-NEXT:    s_xor_b32 s2, s0, s2
6528; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
6529; GFX6-NEXT:    v_mul_hi_u32 v1, s1, v1
6530; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2
6531; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
6532; GFX6-NEXT:    v_xor_b32_e32 v0, s4, v0
6533; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s7
6534; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
6535; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s4, v0
6536; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
6537; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s7, v2
6538; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
6539; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s7, v2
6540; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
6541; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
6542; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s7, v2
6543; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
6544; GFX6-NEXT:    v_xor_b32_e32 v1, s2, v1
6545; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s2, v1
6546; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
6547; GFX6-NEXT:    s_endpgm
6548;
6549; GFX9-LABEL: sdiv_v2i32_pow2_shl_denom:
6550; GFX9:       ; %bb.0:
6551; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
6552; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
6553; GFX9-NEXT:    s_movk_i32 s0, 0x1000
6554; GFX9-NEXT:    s_mov_b32 s10, 0x4f7ffffe
6555; GFX9-NEXT:    v_mov_b32_e32 v2, 0
6556; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6557; GFX9-NEXT:    s_lshl_b32 s1, s0, s6
6558; GFX9-NEXT:    s_ashr_i32 s6, s1, 31
6559; GFX9-NEXT:    s_add_i32 s1, s1, s6
6560; GFX9-NEXT:    s_xor_b32 s1, s1, s6
6561; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s1
6562; GFX9-NEXT:    s_lshl_b32 s0, s0, s7
6563; GFX9-NEXT:    s_ashr_i32 s8, s0, 31
6564; GFX9-NEXT:    s_add_i32 s0, s0, s8
6565; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6566; GFX9-NEXT:    s_xor_b32 s0, s0, s8
6567; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s0
6568; GFX9-NEXT:    s_sub_i32 s9, 0, s1
6569; GFX9-NEXT:    v_mul_f32_e32 v0, s10, v0
6570; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
6571; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
6572; GFX9-NEXT:    s_ashr_i32 s7, s4, 31
6573; GFX9-NEXT:    s_add_i32 s4, s4, s7
6574; GFX9-NEXT:    v_mul_lo_u32 v3, s9, v0
6575; GFX9-NEXT:    v_mul_f32_e32 v1, s10, v1
6576; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
6577; GFX9-NEXT:    s_xor_b32 s4, s4, s7
6578; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v3
6579; GFX9-NEXT:    s_sub_i32 s10, 0, s0
6580; GFX9-NEXT:    s_ashr_i32 s9, s5, 31
6581; GFX9-NEXT:    s_add_i32 s5, s5, s9
6582; GFX9-NEXT:    v_add_u32_e32 v0, v0, v3
6583; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
6584; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v1
6585; GFX9-NEXT:    s_xor_b32 s6, s7, s6
6586; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s1
6587; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
6588; GFX9-NEXT:    v_add_u32_e32 v5, 1, v0
6589; GFX9-NEXT:    v_sub_u32_e32 v4, s4, v4
6590; GFX9-NEXT:    s_xor_b32 s4, s5, s9
6591; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
6592; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s1, v4
6593; GFX9-NEXT:    v_mul_hi_u32 v1, s4, v1
6594; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
6595; GFX9-NEXT:    v_subrev_u32_e32 v5, s1, v4
6596; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
6597; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
6598; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s1, v4
6599; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
6600; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s0
6601; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
6602; GFX9-NEXT:    s_xor_b32 s1, s9, s8
6603; GFX9-NEXT:    v_xor_b32_e32 v0, s6, v0
6604; GFX9-NEXT:    v_sub_u32_e32 v3, s4, v3
6605; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s0, v3
6606; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
6607; GFX9-NEXT:    v_subrev_u32_e32 v4, s0, v3
6608; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
6609; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
6610; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s0, v3
6611; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
6612; GFX9-NEXT:    v_xor_b32_e32 v1, s1, v1
6613; GFX9-NEXT:    v_subrev_u32_e32 v0, s6, v0
6614; GFX9-NEXT:    v_subrev_u32_e32 v1, s1, v1
6615; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
6616; GFX9-NEXT:    s_endpgm
6617  %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
6618  %r = sdiv <2 x i32> %x, %shl.y
6619  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
6620  ret void
6621}
6622
6623define amdgpu_kernel void @srem_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
6624; CHECK-LABEL: @srem_i32_oddk_denom(
6625; CHECK-NEXT:    [[R:%.*]] = srem i32 [[X:%.*]], 1235195
6626; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
6627; CHECK-NEXT:    ret void
6628;
6629; GFX6-LABEL: srem_i32_oddk_denom:
6630; GFX6:       ; %bb.0:
6631; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
6632; GFX6-NEXT:    v_mov_b32_e32 v0, 0xd9528441
6633; GFX6-NEXT:    s_mov_b32 s2, 0x12d8fb
6634; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6635; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6636; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6637; GFX6-NEXT:    v_mul_hi_i32 v0, s4, v0
6638; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s4, v0
6639; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 31, v0
6640; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 20, v0
6641; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
6642; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
6643; GFX6-NEXT:    s_mov_b32 s2, -1
6644; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
6645; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
6646; GFX6-NEXT:    s_endpgm
6647;
6648; GFX9-LABEL: srem_i32_oddk_denom:
6649; GFX9:       ; %bb.0:
6650; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
6651; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
6652; GFX9-NEXT:    v_mov_b32_e32 v0, 0
6653; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6654; GFX9-NEXT:    s_mul_hi_i32 s0, s4, 0xd9528441
6655; GFX9-NEXT:    s_add_i32 s0, s0, s4
6656; GFX9-NEXT:    s_lshr_b32 s1, s0, 31
6657; GFX9-NEXT:    s_ashr_i32 s0, s0, 20
6658; GFX9-NEXT:    s_add_i32 s0, s0, s1
6659; GFX9-NEXT:    s_mul_i32 s0, s0, 0x12d8fb
6660; GFX9-NEXT:    s_sub_i32 s0, s4, s0
6661; GFX9-NEXT:    v_mov_b32_e32 v1, s0
6662; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
6663; GFX9-NEXT:    s_endpgm
6664  %r = srem i32 %x, 1235195
6665  store i32 %r, i32 addrspace(1)* %out
6666  ret void
6667}
6668
6669define amdgpu_kernel void @srem_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x) {
6670; CHECK-LABEL: @srem_i32_pow2k_denom(
6671; CHECK-NEXT:    [[R:%.*]] = srem i32 [[X:%.*]], 4096
6672; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
6673; CHECK-NEXT:    ret void
6674;
6675; GFX6-LABEL: srem_i32_pow2k_denom:
6676; GFX6:       ; %bb.0:
6677; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
6678; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6679; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6680; GFX6-NEXT:    s_mov_b32 s2, -1
6681; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6682; GFX6-NEXT:    s_ashr_i32 s5, s4, 31
6683; GFX6-NEXT:    s_lshr_b32 s5, s5, 20
6684; GFX6-NEXT:    s_add_i32 s5, s4, s5
6685; GFX6-NEXT:    s_and_b32 s5, s5, 0xfffff000
6686; GFX6-NEXT:    s_sub_i32 s4, s4, s5
6687; GFX6-NEXT:    v_mov_b32_e32 v0, s4
6688; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
6689; GFX6-NEXT:    s_endpgm
6690;
6691; GFX9-LABEL: srem_i32_pow2k_denom:
6692; GFX9:       ; %bb.0:
6693; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
6694; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
6695; GFX9-NEXT:    v_mov_b32_e32 v0, 0
6696; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6697; GFX9-NEXT:    s_ashr_i32 s0, s4, 31
6698; GFX9-NEXT:    s_lshr_b32 s0, s0, 20
6699; GFX9-NEXT:    s_add_i32 s0, s4, s0
6700; GFX9-NEXT:    s_and_b32 s0, s0, 0xfffff000
6701; GFX9-NEXT:    s_sub_i32 s0, s4, s0
6702; GFX9-NEXT:    v_mov_b32_e32 v1, s0
6703; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
6704; GFX9-NEXT:    s_endpgm
6705  %r = srem i32 %x, 4096
6706  store i32 %r, i32 addrspace(1)* %out
6707  ret void
6708}
6709
6710define amdgpu_kernel void @srem_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %x, i32 %y) {
6711; CHECK-LABEL: @srem_i32_pow2_shl_denom(
6712; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]]
6713; CHECK-NEXT:    [[R:%.*]] = srem i32 [[X:%.*]], [[SHL_Y]]
6714; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
6715; CHECK-NEXT:    ret void
6716;
6717; GFX6-LABEL: srem_i32_pow2_shl_denom:
6718; GFX6:       ; %bb.0:
6719; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
6720; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6721; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6722; GFX6-NEXT:    s_lshl_b32 s3, 0x1000, s3
6723; GFX6-NEXT:    s_ashr_i32 s4, s3, 31
6724; GFX6-NEXT:    s_add_i32 s3, s3, s4
6725; GFX6-NEXT:    s_xor_b32 s4, s3, s4
6726; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s4
6727; GFX6-NEXT:    s_sub_i32 s3, 0, s4
6728; GFX6-NEXT:    s_ashr_i32 s5, s2, 31
6729; GFX6-NEXT:    s_add_i32 s2, s2, s5
6730; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6731; GFX6-NEXT:    s_xor_b32 s6, s2, s5
6732; GFX6-NEXT:    s_mov_b32 s2, -1
6733; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
6734; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
6735; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v0
6736; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6737; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
6738; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
6739; GFX6-NEXT:    v_mul_hi_u32 v0, s6, v0
6740; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s4
6741; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
6742; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s4, v0
6743; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s4, v0
6744; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
6745; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s4, v0
6746; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s4, v0
6747; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
6748; GFX6-NEXT:    v_xor_b32_e32 v0, s5, v0
6749; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s5, v0
6750; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
6751; GFX6-NEXT:    s_endpgm
6752;
6753; GFX9-LABEL: srem_i32_pow2_shl_denom:
6754; GFX9:       ; %bb.0:
6755; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
6756; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6757; GFX9-NEXT:    s_lshl_b32 s3, 0x1000, s3
6758; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
6759; GFX9-NEXT:    s_add_i32 s3, s3, s4
6760; GFX9-NEXT:    s_xor_b32 s3, s3, s4
6761; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
6762; GFX9-NEXT:    s_sub_i32 s4, 0, s3
6763; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
6764; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6765; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
6766; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
6767; GFX9-NEXT:    v_mul_lo_u32 v1, s4, v0
6768; GFX9-NEXT:    s_ashr_i32 s4, s2, 31
6769; GFX9-NEXT:    s_add_i32 s2, s2, s4
6770; GFX9-NEXT:    s_xor_b32 s2, s2, s4
6771; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
6772; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
6773; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
6774; GFX9-NEXT:    v_mov_b32_e32 v1, 0
6775; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
6776; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
6777; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v0
6778; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v0
6779; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
6780; GFX9-NEXT:    v_subrev_u32_e32 v2, s3, v0
6781; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v0
6782; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
6783; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v0
6784; GFX9-NEXT:    v_subrev_u32_e32 v0, s4, v0
6785; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6786; GFX9-NEXT:    global_store_dword v1, v0, s[0:1]
6787; GFX9-NEXT:    s_endpgm
6788  %shl.y = shl i32 4096, %y
6789  %r = srem i32 %x, %shl.y
6790  store i32 %r, i32 addrspace(1)* %out
6791  ret void
6792}
6793
6794define amdgpu_kernel void @srem_v2i32_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) {
6795; CHECK-LABEL: @srem_v2i32_pow2k_denom(
6796; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
6797; CHECK-NEXT:    [[TMP2:%.*]] = srem i32 [[TMP1]], 4096
6798; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0
6799; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1
6800; CHECK-NEXT:    [[TMP5:%.*]] = srem i32 [[TMP4]], 4096
6801; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1
6802; CHECK-NEXT:    store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
6803; CHECK-NEXT:    ret void
6804;
6805; GFX6-LABEL: srem_v2i32_pow2k_denom:
6806; GFX6:       ; %bb.0:
6807; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
6808; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6809; GFX6-NEXT:    s_movk_i32 s6, 0xf000
6810; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6811; GFX6-NEXT:    s_mov_b32 s2, -1
6812; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6813; GFX6-NEXT:    s_ashr_i32 s7, s4, 31
6814; GFX6-NEXT:    s_lshr_b32 s7, s7, 20
6815; GFX6-NEXT:    s_add_i32 s7, s4, s7
6816; GFX6-NEXT:    s_and_b32 s7, s7, s6
6817; GFX6-NEXT:    s_sub_i32 s4, s4, s7
6818; GFX6-NEXT:    s_ashr_i32 s7, s5, 31
6819; GFX6-NEXT:    s_lshr_b32 s7, s7, 20
6820; GFX6-NEXT:    s_add_i32 s7, s5, s7
6821; GFX6-NEXT:    s_and_b32 s6, s7, s6
6822; GFX6-NEXT:    s_sub_i32 s5, s5, s6
6823; GFX6-NEXT:    v_mov_b32_e32 v0, s4
6824; GFX6-NEXT:    v_mov_b32_e32 v1, s5
6825; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
6826; GFX6-NEXT:    s_endpgm
6827;
6828; GFX9-LABEL: srem_v2i32_pow2k_denom:
6829; GFX9:       ; %bb.0:
6830; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
6831; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
6832; GFX9-NEXT:    s_movk_i32 s0, 0xf000
6833; GFX9-NEXT:    v_mov_b32_e32 v2, 0
6834; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
6835; GFX9-NEXT:    s_ashr_i32 s1, s2, 31
6836; GFX9-NEXT:    s_lshr_b32 s1, s1, 20
6837; GFX9-NEXT:    s_add_i32 s1, s2, s1
6838; GFX9-NEXT:    s_ashr_i32 s6, s3, 31
6839; GFX9-NEXT:    s_and_b32 s1, s1, s0
6840; GFX9-NEXT:    s_sub_i32 s1, s2, s1
6841; GFX9-NEXT:    s_lshr_b32 s2, s6, 20
6842; GFX9-NEXT:    s_add_i32 s2, s3, s2
6843; GFX9-NEXT:    s_and_b32 s0, s2, s0
6844; GFX9-NEXT:    s_sub_i32 s0, s3, s0
6845; GFX9-NEXT:    v_mov_b32_e32 v0, s1
6846; GFX9-NEXT:    v_mov_b32_e32 v1, s0
6847; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
6848; GFX9-NEXT:    s_endpgm
6849  %r = srem <2 x i32> %x, <i32 4096, i32 4096>
6850  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
6851  ret void
6852}
6853
6854define amdgpu_kernel void @srem_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) {
6855; CHECK-LABEL: @srem_v2i32_pow2_shl_denom(
6856; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i32> <i32 4096, i32 4096>, [[Y:%.*]]
6857; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0
6858; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 0
6859; CHECK-NEXT:    [[TMP3:%.*]] = ashr i32 [[TMP1]], 31
6860; CHECK-NEXT:    [[TMP4:%.*]] = ashr i32 [[TMP2]], 31
6861; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[TMP1]], [[TMP3]]
6862; CHECK-NEXT:    [[TMP6:%.*]] = add i32 [[TMP2]], [[TMP4]]
6863; CHECK-NEXT:    [[TMP7:%.*]] = xor i32 [[TMP5]], [[TMP3]]
6864; CHECK-NEXT:    [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP4]]
6865; CHECK-NEXT:    [[TMP9:%.*]] = uitofp i32 [[TMP8]] to float
6866; CHECK-NEXT:    [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
6867; CHECK-NEXT:    [[TMP11:%.*]] = fmul fast float [[TMP10]], 0x41EFFFFFC0000000
6868; CHECK-NEXT:    [[TMP12:%.*]] = fptoui float [[TMP11]] to i32
6869; CHECK-NEXT:    [[TMP13:%.*]] = sub i32 0, [[TMP8]]
6870; CHECK-NEXT:    [[TMP14:%.*]] = mul i32 [[TMP13]], [[TMP12]]
6871; CHECK-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP12]] to i64
6872; CHECK-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP14]] to i64
6873; CHECK-NEXT:    [[TMP17:%.*]] = mul i64 [[TMP15]], [[TMP16]]
6874; CHECK-NEXT:    [[TMP18:%.*]] = trunc i64 [[TMP17]] to i32
6875; CHECK-NEXT:    [[TMP19:%.*]] = lshr i64 [[TMP17]], 32
6876; CHECK-NEXT:    [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32
6877; CHECK-NEXT:    [[TMP21:%.*]] = add i32 [[TMP12]], [[TMP20]]
6878; CHECK-NEXT:    [[TMP22:%.*]] = zext i32 [[TMP7]] to i64
6879; CHECK-NEXT:    [[TMP23:%.*]] = zext i32 [[TMP21]] to i64
6880; CHECK-NEXT:    [[TMP24:%.*]] = mul i64 [[TMP22]], [[TMP23]]
6881; CHECK-NEXT:    [[TMP25:%.*]] = trunc i64 [[TMP24]] to i32
6882; CHECK-NEXT:    [[TMP26:%.*]] = lshr i64 [[TMP24]], 32
6883; CHECK-NEXT:    [[TMP27:%.*]] = trunc i64 [[TMP26]] to i32
6884; CHECK-NEXT:    [[TMP28:%.*]] = mul i32 [[TMP27]], [[TMP8]]
6885; CHECK-NEXT:    [[TMP29:%.*]] = sub i32 [[TMP7]], [[TMP28]]
6886; CHECK-NEXT:    [[TMP30:%.*]] = icmp uge i32 [[TMP29]], [[TMP8]]
6887; CHECK-NEXT:    [[TMP31:%.*]] = sub i32 [[TMP29]], [[TMP8]]
6888; CHECK-NEXT:    [[TMP32:%.*]] = select i1 [[TMP30]], i32 [[TMP31]], i32 [[TMP29]]
6889; CHECK-NEXT:    [[TMP33:%.*]] = icmp uge i32 [[TMP32]], [[TMP8]]
6890; CHECK-NEXT:    [[TMP34:%.*]] = sub i32 [[TMP32]], [[TMP8]]
6891; CHECK-NEXT:    [[TMP35:%.*]] = select i1 [[TMP33]], i32 [[TMP34]], i32 [[TMP32]]
6892; CHECK-NEXT:    [[TMP36:%.*]] = xor i32 [[TMP35]], [[TMP3]]
6893; CHECK-NEXT:    [[TMP37:%.*]] = sub i32 [[TMP36]], [[TMP3]]
6894; CHECK-NEXT:    [[TMP38:%.*]] = insertelement <2 x i32> undef, i32 [[TMP37]], i64 0
6895; CHECK-NEXT:    [[TMP39:%.*]] = extractelement <2 x i32> [[X]], i64 1
6896; CHECK-NEXT:    [[TMP40:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1
6897; CHECK-NEXT:    [[TMP41:%.*]] = ashr i32 [[TMP39]], 31
6898; CHECK-NEXT:    [[TMP42:%.*]] = ashr i32 [[TMP40]], 31
6899; CHECK-NEXT:    [[TMP43:%.*]] = add i32 [[TMP39]], [[TMP41]]
6900; CHECK-NEXT:    [[TMP44:%.*]] = add i32 [[TMP40]], [[TMP42]]
6901; CHECK-NEXT:    [[TMP45:%.*]] = xor i32 [[TMP43]], [[TMP41]]
6902; CHECK-NEXT:    [[TMP46:%.*]] = xor i32 [[TMP44]], [[TMP42]]
6903; CHECK-NEXT:    [[TMP47:%.*]] = uitofp i32 [[TMP46]] to float
6904; CHECK-NEXT:    [[TMP48:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP47]])
6905; CHECK-NEXT:    [[TMP49:%.*]] = fmul fast float [[TMP48]], 0x41EFFFFFC0000000
6906; CHECK-NEXT:    [[TMP50:%.*]] = fptoui float [[TMP49]] to i32
6907; CHECK-NEXT:    [[TMP51:%.*]] = sub i32 0, [[TMP46]]
6908; CHECK-NEXT:    [[TMP52:%.*]] = mul i32 [[TMP51]], [[TMP50]]
6909; CHECK-NEXT:    [[TMP53:%.*]] = zext i32 [[TMP50]] to i64
6910; CHECK-NEXT:    [[TMP54:%.*]] = zext i32 [[TMP52]] to i64
6911; CHECK-NEXT:    [[TMP55:%.*]] = mul i64 [[TMP53]], [[TMP54]]
6912; CHECK-NEXT:    [[TMP56:%.*]] = trunc i64 [[TMP55]] to i32
6913; CHECK-NEXT:    [[TMP57:%.*]] = lshr i64 [[TMP55]], 32
6914; CHECK-NEXT:    [[TMP58:%.*]] = trunc i64 [[TMP57]] to i32
6915; CHECK-NEXT:    [[TMP59:%.*]] = add i32 [[TMP50]], [[TMP58]]
6916; CHECK-NEXT:    [[TMP60:%.*]] = zext i32 [[TMP45]] to i64
6917; CHECK-NEXT:    [[TMP61:%.*]] = zext i32 [[TMP59]] to i64
6918; CHECK-NEXT:    [[TMP62:%.*]] = mul i64 [[TMP60]], [[TMP61]]
6919; CHECK-NEXT:    [[TMP63:%.*]] = trunc i64 [[TMP62]] to i32
6920; CHECK-NEXT:    [[TMP64:%.*]] = lshr i64 [[TMP62]], 32
6921; CHECK-NEXT:    [[TMP65:%.*]] = trunc i64 [[TMP64]] to i32
6922; CHECK-NEXT:    [[TMP66:%.*]] = mul i32 [[TMP65]], [[TMP46]]
6923; CHECK-NEXT:    [[TMP67:%.*]] = sub i32 [[TMP45]], [[TMP66]]
6924; CHECK-NEXT:    [[TMP68:%.*]] = icmp uge i32 [[TMP67]], [[TMP46]]
6925; CHECK-NEXT:    [[TMP69:%.*]] = sub i32 [[TMP67]], [[TMP46]]
6926; CHECK-NEXT:    [[TMP70:%.*]] = select i1 [[TMP68]], i32 [[TMP69]], i32 [[TMP67]]
6927; CHECK-NEXT:    [[TMP71:%.*]] = icmp uge i32 [[TMP70]], [[TMP46]]
6928; CHECK-NEXT:    [[TMP72:%.*]] = sub i32 [[TMP70]], [[TMP46]]
6929; CHECK-NEXT:    [[TMP73:%.*]] = select i1 [[TMP71]], i32 [[TMP72]], i32 [[TMP70]]
6930; CHECK-NEXT:    [[TMP74:%.*]] = xor i32 [[TMP73]], [[TMP41]]
6931; CHECK-NEXT:    [[TMP75:%.*]] = sub i32 [[TMP74]], [[TMP41]]
6932; CHECK-NEXT:    [[TMP76:%.*]] = insertelement <2 x i32> [[TMP38]], i32 [[TMP75]], i64 1
6933; CHECK-NEXT:    store <2 x i32> [[TMP76]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
6934; CHECK-NEXT:    ret void
6935;
6936; GFX6-LABEL: srem_v2i32_pow2_shl_denom:
6937; GFX6:       ; %bb.0:
6938; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
6939; GFX6-NEXT:    s_movk_i32 s8, 0x1000
6940; GFX6-NEXT:    s_mov_b32 s11, 0x4f7ffffe
6941; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
6942; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
6943; GFX6-NEXT:    s_lshl_b32 s2, s8, s6
6944; GFX6-NEXT:    s_ashr_i32 s3, s2, 31
6945; GFX6-NEXT:    s_add_i32 s2, s2, s3
6946; GFX6-NEXT:    s_xor_b32 s6, s2, s3
6947; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s6
6948; GFX6-NEXT:    s_lshl_b32 s7, s8, s7
6949; GFX6-NEXT:    s_ashr_i32 s9, s7, 31
6950; GFX6-NEXT:    s_add_i32 s7, s7, s9
6951; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
6952; GFX6-NEXT:    s_sub_i32 s10, 0, s6
6953; GFX6-NEXT:    s_xor_b32 s7, s7, s9
6954; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s7
6955; GFX6-NEXT:    v_mul_f32_e32 v0, s11, v0
6956; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
6957; GFX6-NEXT:    s_ashr_i32 s8, s4, 31
6958; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
6959; GFX6-NEXT:    s_add_i32 s4, s4, s8
6960; GFX6-NEXT:    v_mul_lo_u32 v1, s10, v0
6961; GFX6-NEXT:    s_xor_b32 s4, s4, s8
6962; GFX6-NEXT:    s_sub_i32 s10, 0, s7
6963; GFX6-NEXT:    s_ashr_i32 s9, s5, 31
6964; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
6965; GFX6-NEXT:    s_mov_b32 s3, 0xf000
6966; GFX6-NEXT:    s_mov_b32 s2, -1
6967; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
6968; GFX6-NEXT:    v_mul_f32_e32 v1, s11, v2
6969; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
6970; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
6971; GFX6-NEXT:    v_mul_lo_u32 v2, s10, v1
6972; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s6
6973; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v2
6974; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
6975; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s6, v0
6976; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
6977; GFX6-NEXT:    s_add_i32 s4, s5, s9
6978; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
6979; GFX6-NEXT:    s_xor_b32 s4, s4, s9
6980; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
6981; GFX6-NEXT:    v_mul_hi_u32 v1, s4, v1
6982; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s6, v0
6983; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
6984; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s7
6985; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
6986; GFX6-NEXT:    v_xor_b32_e32 v0, s8, v0
6987; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v0
6988; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s4, v1
6989; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s7, v1
6990; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
6991; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
6992; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s7, v1
6993; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
6994; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
6995; GFX6-NEXT:    v_xor_b32_e32 v1, s9, v1
6996; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s9, v1
6997; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
6998; GFX6-NEXT:    s_endpgm
6999;
7000; GFX9-LABEL: srem_v2i32_pow2_shl_denom:
7001; GFX9:       ; %bb.0:
7002; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
7003; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
7004; GFX9-NEXT:    s_movk_i32 s0, 0x1000
7005; GFX9-NEXT:    s_mov_b32 s8, 0x4f7ffffe
7006; GFX9-NEXT:    v_mov_b32_e32 v2, 0
7007; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7008; GFX9-NEXT:    s_lshl_b32 s1, s0, s6
7009; GFX9-NEXT:    s_ashr_i32 s6, s1, 31
7010; GFX9-NEXT:    s_add_i32 s1, s1, s6
7011; GFX9-NEXT:    s_xor_b32 s1, s1, s6
7012; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s1
7013; GFX9-NEXT:    s_lshl_b32 s0, s0, s7
7014; GFX9-NEXT:    s_ashr_i32 s6, s0, 31
7015; GFX9-NEXT:    s_add_i32 s0, s0, s6
7016; GFX9-NEXT:    s_xor_b32 s0, s0, s6
7017; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
7018; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s0
7019; GFX9-NEXT:    s_sub_i32 s7, 0, s1
7020; GFX9-NEXT:    s_ashr_i32 s6, s4, 31
7021; GFX9-NEXT:    v_mul_f32_e32 v0, s8, v0
7022; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
7023; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
7024; GFX9-NEXT:    s_add_i32 s4, s4, s6
7025; GFX9-NEXT:    s_xor_b32 s4, s4, s6
7026; GFX9-NEXT:    v_mul_f32_e32 v1, s8, v1
7027; GFX9-NEXT:    v_mul_lo_u32 v3, s7, v0
7028; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
7029; GFX9-NEXT:    s_sub_i32 s7, 0, s0
7030; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v3
7031; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v1
7032; GFX9-NEXT:    s_ashr_i32 s7, s5, 31
7033; GFX9-NEXT:    s_add_i32 s5, s5, s7
7034; GFX9-NEXT:    v_add_u32_e32 v0, v0, v3
7035; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v4
7036; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
7037; GFX9-NEXT:    s_xor_b32 s5, s5, s7
7038; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
7039; GFX9-NEXT:    v_mul_hi_u32 v1, s5, v1
7040; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s1
7041; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s0
7042; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
7043; GFX9-NEXT:    v_subrev_u32_e32 v3, s1, v0
7044; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s1, v0
7045; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
7046; GFX9-NEXT:    v_subrev_u32_e32 v3, s1, v0
7047; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s1, v0
7048; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v1
7049; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
7050; GFX9-NEXT:    v_subrev_u32_e32 v3, s0, v1
7051; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s0, v1
7052; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
7053; GFX9-NEXT:    v_subrev_u32_e32 v3, s0, v1
7054; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s0, v1
7055; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
7056; GFX9-NEXT:    v_xor_b32_e32 v0, s6, v0
7057; GFX9-NEXT:    v_xor_b32_e32 v1, s7, v1
7058; GFX9-NEXT:    v_subrev_u32_e32 v0, s6, v0
7059; GFX9-NEXT:    v_subrev_u32_e32 v1, s7, v1
7060; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
7061; GFX9-NEXT:    s_endpgm
7062  %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
7063  %r = srem <2 x i32> %x, %shl.y
7064  store <2 x i32> %r, <2 x i32> addrspace(1)* %out
7065  ret void
7066}
7067
7068define amdgpu_kernel void @udiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
7069; CHECK-LABEL: @udiv_i64_oddk_denom(
7070; CHECK-NEXT:    [[R:%.*]] = udiv i64 [[X:%.*]], 1235195949943
7071; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
7072; CHECK-NEXT:    ret void
7073;
7074; GFX6-LABEL: udiv_i64_oddk_denom:
7075; GFX6:       ; %bb.0:
7076; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f176a73
7077; GFX6-NEXT:    v_mov_b32_e32 v1, 0x4f800000
7078; GFX6-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
7079; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
7080; GFX6-NEXT:    s_movk_i32 s4, 0xfee0
7081; GFX6-NEXT:    s_mov_b32 s5, 0x68958c89
7082; GFX6-NEXT:    v_mov_b32_e32 v7, 0
7083; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
7084; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
7085; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
7086; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
7087; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
7088; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
7089; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
7090; GFX6-NEXT:    s_movk_i32 s8, 0x11f
7091; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s4
7092; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s5
7093; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s5
7094; GFX6-NEXT:    s_mov_b32 s9, 0x976a7377
7095; GFX6-NEXT:    s_mov_b32 s7, 0xf000
7096; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7097; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s5
7098; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
7099; GFX6-NEXT:    v_mul_lo_u32 v4, v0, v2
7100; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v3
7101; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
7102; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
7103; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
7104; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
7105; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
7106; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
7107; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
7108; GFX6-NEXT:    s_mov_b32 s6, -1
7109; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
7110; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
7111; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
7112; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7113; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
7114; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
7115; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
7116; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s4
7117; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s5
7118; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s5
7119; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7120; GFX6-NEXT:    s_mov_b32 s4, s0
7121; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7122; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s5
7123; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
7124; GFX6-NEXT:    v_mul_lo_u32 v4, v0, v2
7125; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v3
7126; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
7127; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
7128; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
7129; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
7130; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
7131; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
7132; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
7133; GFX6-NEXT:    s_mov_b32 s5, s1
7134; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
7135; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
7136; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
7137; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7138; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
7139; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
7140; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
7141; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
7142; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
7143; GFX6-NEXT:    v_mul_hi_u32 v4, s2, v1
7144; GFX6-NEXT:    v_mul_hi_u32 v5, s3, v1
7145; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v1
7146; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7147; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
7148; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v0
7149; GFX6-NEXT:    v_mul_hi_u32 v0, s3, v0
7150; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
7151; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
7152; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
7153; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
7154; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
7155; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s8
7156; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s9
7157; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s9
7158; GFX6-NEXT:    v_mov_b32_e32 v5, s8
7159; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7160; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s9
7161; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
7162; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s3, v2
7163; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s2, v3
7164; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
7165; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s9, v3
7166; GFX6-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
7167; GFX6-NEXT:    s_movk_i32 s2, 0x11e
7168; GFX6-NEXT:    v_cmp_lt_u32_e64 s[0:1], s2, v4
7169; GFX6-NEXT:    s_mov_b32 s9, 0x976a7376
7170; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
7171; GFX6-NEXT:    v_cmp_lt_u32_e64 s[0:1], s9, v5
7172; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
7173; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s8, v4
7174; GFX6-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
7175; GFX6-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
7176; GFX6-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
7177; GFX6-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
7178; GFX6-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
7179; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
7180; GFX6-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
7181; GFX6-NEXT:    v_mov_b32_e32 v6, s3
7182; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
7183; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s2, v2
7184; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
7185; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s9, v3
7186; GFX6-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
7187; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s8, v2
7188; GFX6-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
7189; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
7190; GFX6-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
7191; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
7192; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
7193; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
7194; GFX6-NEXT:    s_endpgm
7195;
7196; GFX9-LABEL: udiv_i64_oddk_denom:
7197; GFX9:       ; %bb.0:
7198; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f176a73
7199; GFX9-NEXT:    v_mov_b32_e32 v1, 0x4f800000
7200; GFX9-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
7201; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
7202; GFX9-NEXT:    s_movk_i32 s2, 0xfee0
7203; GFX9-NEXT:    s_mov_b32 s3, 0x68958c89
7204; GFX9-NEXT:    v_mov_b32_e32 v6, 0
7205; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
7206; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
7207; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
7208; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
7209; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
7210; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
7211; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
7212; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s2
7213; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s3
7214; GFX9-NEXT:    v_mul_lo_u32 v5, v1, s3
7215; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s3
7216; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
7217; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
7218; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
7219; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
7220; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
7221; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
7222; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
7223; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
7224; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
7225; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
7226; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
7227; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
7228; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
7229; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
7230; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7231; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
7232; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
7233; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
7234; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s2
7235; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s3
7236; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s3
7237; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s3
7238; GFX9-NEXT:    s_movk_i32 s2, 0x11f
7239; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
7240; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
7241; GFX9-NEXT:    v_mul_lo_u32 v3, v0, v2
7242; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v5
7243; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
7244; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
7245; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
7246; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
7247; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v7, vcc
7248; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v5
7249; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v5
7250; GFX9-NEXT:    s_mov_b32 s3, 0x976a7377
7251; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
7252; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v4, v5, vcc
7253; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
7254; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7255; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
7256; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
7257; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
7258; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7259; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
7260; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
7261; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
7262; GFX9-NEXT:    v_mul_hi_u32 v5, s7, v1
7263; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
7264; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7265; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
7266; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v0
7267; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
7268; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
7269; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
7270; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v5, v6, vcc
7271; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
7272; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
7273; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s2
7274; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s3
7275; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s3
7276; GFX9-NEXT:    v_mov_b32_e32 v5, s2
7277; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
7278; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s3
7279; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
7280; GFX9-NEXT:    v_sub_u32_e32 v4, s7, v2
7281; GFX9-NEXT:    v_sub_co_u32_e32 v3, vcc, s6, v3
7282; GFX9-NEXT:    v_subb_co_u32_e64 v4, s[0:1], v4, v5, vcc
7283; GFX9-NEXT:    v_subrev_co_u32_e64 v5, s[0:1], s3, v3
7284; GFX9-NEXT:    v_subbrev_co_u32_e64 v4, s[0:1], 0, v4, s[0:1]
7285; GFX9-NEXT:    s_movk_i32 s3, 0x11e
7286; GFX9-NEXT:    v_cmp_lt_u32_e64 s[0:1], s3, v4
7287; GFX9-NEXT:    s_mov_b32 s6, 0x976a7376
7288; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
7289; GFX9-NEXT:    v_cmp_lt_u32_e64 s[0:1], s6, v5
7290; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
7291; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s2, v4
7292; GFX9-NEXT:    v_cndmask_b32_e64 v4, v7, v5, s[0:1]
7293; GFX9-NEXT:    v_add_co_u32_e64 v5, s[0:1], 2, v0
7294; GFX9-NEXT:    v_addc_co_u32_e64 v7, s[0:1], 0, v1, s[0:1]
7295; GFX9-NEXT:    v_add_co_u32_e64 v8, s[0:1], 1, v0
7296; GFX9-NEXT:    v_addc_co_u32_e64 v9, s[0:1], 0, v1, s[0:1]
7297; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
7298; GFX9-NEXT:    v_cndmask_b32_e64 v4, v9, v7, s[0:1]
7299; GFX9-NEXT:    v_mov_b32_e32 v7, s7
7300; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v7, v2, vcc
7301; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s3, v2
7302; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
7303; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v3
7304; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
7305; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v2
7306; GFX9-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc
7307; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
7308; GFX9-NEXT:    v_cndmask_b32_e64 v2, v8, v5, s[0:1]
7309; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
7310; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
7311; GFX9-NEXT:    global_store_dwordx2 v6, v[0:1], s[4:5]
7312; GFX9-NEXT:    s_endpgm
7313  %r = udiv i64 %x, 1235195949943
7314  store i64 %r, i64 addrspace(1)* %out
7315  ret void
7316}
7317
7318define amdgpu_kernel void @udiv_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) {
7319; CHECK-LABEL: @udiv_i64_pow2k_denom(
7320; CHECK-NEXT:    [[R:%.*]] = udiv i64 [[X:%.*]], 4096
7321; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
7322; CHECK-NEXT:    ret void
7323;
7324; GFX6-LABEL: udiv_i64_pow2k_denom:
7325; GFX6:       ; %bb.0:
7326; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
7327; GFX6-NEXT:    s_mov_b32 s7, 0xf000
7328; GFX6-NEXT:    s_mov_b32 s6, -1
7329; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7330; GFX6-NEXT:    s_mov_b32 s4, s0
7331; GFX6-NEXT:    s_mov_b32 s5, s1
7332; GFX6-NEXT:    s_lshr_b64 s[0:1], s[2:3], 12
7333; GFX6-NEXT:    v_mov_b32_e32 v0, s0
7334; GFX6-NEXT:    v_mov_b32_e32 v1, s1
7335; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
7336; GFX6-NEXT:    s_endpgm
7337;
7338; GFX9-LABEL: udiv_i64_pow2k_denom:
7339; GFX9:       ; %bb.0:
7340; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
7341; GFX9-NEXT:    v_mov_b32_e32 v2, 0
7342; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7343; GFX9-NEXT:    s_lshr_b64 s[2:3], s[2:3], 12
7344; GFX9-NEXT:    v_mov_b32_e32 v0, s2
7345; GFX9-NEXT:    v_mov_b32_e32 v1, s3
7346; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
7347; GFX9-NEXT:    s_endpgm
7348  %r = udiv i64 %x, 4096
7349  store i64 %r, i64 addrspace(1)* %out
7350  ret void
7351}
7352
7353define amdgpu_kernel void @udiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %x, i64 %y) {
7354; CHECK-LABEL: @udiv_i64_pow2_shl_denom(
7355; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]]
7356; CHECK-NEXT:    [[R:%.*]] = udiv i64 [[X:%.*]], [[SHL_Y]]
7357; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
7358; CHECK-NEXT:    ret void
7359;
7360; GFX6-LABEL: udiv_i64_pow2_shl_denom:
7361; GFX6:       ; %bb.0:
7362; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
7363; GFX6-NEXT:    s_load_dword s8, s[0:1], 0xd
7364; GFX6-NEXT:    s_mov_b32 s3, 0xf000
7365; GFX6-NEXT:    s_mov_b32 s2, -1
7366; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7367; GFX6-NEXT:    s_mov_b32 s0, s4
7368; GFX6-NEXT:    s_add_i32 s8, s8, 12
7369; GFX6-NEXT:    s_mov_b32 s1, s5
7370; GFX6-NEXT:    s_lshr_b64 s[4:5], s[6:7], s8
7371; GFX6-NEXT:    v_mov_b32_e32 v0, s4
7372; GFX6-NEXT:    v_mov_b32_e32 v1, s5
7373; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
7374; GFX6-NEXT:    s_endpgm
7375;
7376; GFX9-LABEL: udiv_i64_pow2_shl_denom:
7377; GFX9:       ; %bb.0:
7378; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x34
7379; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
7380; GFX9-NEXT:    v_mov_b32_e32 v2, 0
7381; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7382; GFX9-NEXT:    s_add_i32 s2, s2, 12
7383; GFX9-NEXT:    s_lshr_b64 s[0:1], s[6:7], s2
7384; GFX9-NEXT:    v_mov_b32_e32 v0, s0
7385; GFX9-NEXT:    v_mov_b32_e32 v1, s1
7386; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
7387; GFX9-NEXT:    s_endpgm
7388  %shl.y = shl i64 4096, %y
7389  %r = udiv i64 %x, %shl.y
7390  store i64 %r, i64 addrspace(1)* %out
7391  ret void
7392}
7393
7394define amdgpu_kernel void @udiv_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
7395; CHECK-LABEL: @udiv_v2i64_pow2k_denom(
7396; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
7397; CHECK-NEXT:    [[TMP2:%.*]] = udiv i64 [[TMP1]], 4096
7398; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
7399; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
7400; CHECK-NEXT:    [[TMP5:%.*]] = udiv i64 [[TMP4]], 4096
7401; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
7402; CHECK-NEXT:    store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
7403; CHECK-NEXT:    ret void
7404;
7405; GFX6-LABEL: udiv_v2i64_pow2k_denom:
7406; GFX6:       ; %bb.0:
7407; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
7408; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
7409; GFX6-NEXT:    s_mov_b32 s3, 0xf000
7410; GFX6-NEXT:    s_mov_b32 s2, -1
7411; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7412; GFX6-NEXT:    s_lshr_b64 s[4:5], s[4:5], 12
7413; GFX6-NEXT:    s_lshr_b64 s[6:7], s[6:7], 12
7414; GFX6-NEXT:    v_mov_b32_e32 v0, s4
7415; GFX6-NEXT:    v_mov_b32_e32 v1, s5
7416; GFX6-NEXT:    v_mov_b32_e32 v2, s6
7417; GFX6-NEXT:    v_mov_b32_e32 v3, s7
7418; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
7419; GFX6-NEXT:    s_endpgm
7420;
7421; GFX9-LABEL: udiv_v2i64_pow2k_denom:
7422; GFX9:       ; %bb.0:
7423; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
7424; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
7425; GFX9-NEXT:    v_mov_b32_e32 v4, 0
7426; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7427; GFX9-NEXT:    s_lshr_b64 s[0:1], s[4:5], 12
7428; GFX9-NEXT:    s_lshr_b64 s[4:5], s[6:7], 12
7429; GFX9-NEXT:    v_mov_b32_e32 v0, s0
7430; GFX9-NEXT:    v_mov_b32_e32 v1, s1
7431; GFX9-NEXT:    v_mov_b32_e32 v2, s4
7432; GFX9-NEXT:    v_mov_b32_e32 v3, s5
7433; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
7434; GFX9-NEXT:    s_endpgm
7435  %r = udiv <2 x i64> %x, <i64 4096, i64 4096>
7436  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
7437  ret void
7438}
7439
7440define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
7441; CHECK-LABEL: @udiv_v2i64_mixed_pow2k_denom(
7442; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
7443; CHECK-NEXT:    [[TMP2:%.*]] = udiv i64 [[TMP1]], 4096
7444; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
7445; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
7446; CHECK-NEXT:    [[TMP5:%.*]] = udiv i64 [[TMP4]], 4095
7447; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
7448; CHECK-NEXT:    store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
7449; CHECK-NEXT:    ret void
7450;
7451; GFX6-LABEL: udiv_v2i64_mixed_pow2k_denom:
7452; GFX6:       ; %bb.0:
7453; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f800000
7454; GFX6-NEXT:    v_madak_f32 v0, 0, v0, 0x457ff000
7455; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
7456; GFX6-NEXT:    s_movk_i32 s6, 0xf001
7457; GFX6-NEXT:    v_mov_b32_e32 v7, 0
7458; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
7459; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
7460; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
7461; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
7462; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
7463; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
7464; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
7465; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
7466; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7467; GFX6-NEXT:    s_lshr_b64 s[8:9], s[0:1], 12
7468; GFX6-NEXT:    s_movk_i32 s0, 0xfff
7469; GFX6-NEXT:    v_mul_hi_u32 v2, v0, s6
7470; GFX6-NEXT:    v_mul_lo_u32 v3, v1, s6
7471; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s6
7472; GFX6-NEXT:    s_mov_b32 s7, 0xf000
7473; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
7474; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7475; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
7476; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v4
7477; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
7478; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
7479; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
7480; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
7481; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
7482; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
7483; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
7484; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
7485; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
7486; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
7487; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7488; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
7489; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
7490; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
7491; GFX6-NEXT:    v_mul_hi_u32 v2, v0, s6
7492; GFX6-NEXT:    v_mul_lo_u32 v3, v1, s6
7493; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s6
7494; GFX6-NEXT:    s_mov_b32 s6, -1
7495; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
7496; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
7497; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
7498; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v4
7499; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
7500; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
7501; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
7502; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
7503; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
7504; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
7505; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
7506; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
7507; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
7508; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
7509; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7510; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
7511; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
7512; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
7513; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
7514; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
7515; GFX6-NEXT:    v_mul_hi_u32 v4, s2, v1
7516; GFX6-NEXT:    v_mul_hi_u32 v5, s3, v1
7517; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v1
7518; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7519; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
7520; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v0
7521; GFX6-NEXT:    v_mul_hi_u32 v0, s3, v0
7522; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
7523; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
7524; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
7525; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
7526; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
7527; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s0
7528; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s0
7529; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 2, v0
7530; GFX6-NEXT:    v_mul_lo_u32 v8, v0, s0
7531; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
7532; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v0
7533; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v1, vcc
7534; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
7535; GFX6-NEXT:    v_mov_b32_e32 v5, s3
7536; GFX6-NEXT:    v_sub_i32_e32 v8, vcc, s2, v8
7537; GFX6-NEXT:    v_subb_u32_e32 v4, vcc, v5, v4, vcc
7538; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s0, v8
7539; GFX6-NEXT:    v_subbrev_u32_e32 v9, vcc, 0, v4, vcc
7540; GFX6-NEXT:    s_movk_i32 s0, 0xffe
7541; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v5
7542; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
7543; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v9
7544; GFX6-NEXT:    v_cndmask_b32_e32 v5, -1, v5, vcc
7545; GFX6-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v8
7546; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
7547; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
7548; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v4
7549; GFX6-NEXT:    v_cndmask_b32_e64 v4, -1, v5, s[0:1]
7550; GFX6-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
7551; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
7552; GFX6-NEXT:    v_cndmask_b32_e64 v3, v1, v3, s[0:1]
7553; GFX6-NEXT:    v_cndmask_b32_e32 v1, v6, v2, vcc
7554; GFX6-NEXT:    v_cndmask_b32_e64 v2, v0, v1, s[0:1]
7555; GFX6-NEXT:    v_mov_b32_e32 v0, s8
7556; GFX6-NEXT:    v_mov_b32_e32 v1, s9
7557; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
7558; GFX6-NEXT:    s_endpgm
7559;
7560; GFX9-LABEL: udiv_v2i64_mixed_pow2k_denom:
7561; GFX9:       ; %bb.0:
7562; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f800000
7563; GFX9-NEXT:    v_madak_f32 v0, 0, v0, 0x457ff000
7564; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
7565; GFX9-NEXT:    s_movk_i32 s2, 0xf001
7566; GFX9-NEXT:    v_mov_b32_e32 v5, 0
7567; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
7568; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
7569; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
7570; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
7571; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
7572; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
7573; GFX9-NEXT:    v_mul_hi_u32 v2, v0, s2
7574; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s2
7575; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s2
7576; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
7577; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
7578; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v3
7579; GFX9-NEXT:    v_mul_lo_u32 v4, v0, v2
7580; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
7581; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v3
7582; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
7583; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
7584; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
7585; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
7586; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
7587; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v7
7588; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
7589; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
7590; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7591; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
7592; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
7593; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
7594; GFX9-NEXT:    v_mul_hi_u32 v2, v0, s2
7595; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s2
7596; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s2
7597; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
7598; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
7599; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
7600; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
7601; GFX9-NEXT:    v_mul_lo_u32 v3, v0, v2
7602; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v4
7603; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
7604; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
7605; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
7606; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v6, v3
7607; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
7608; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
7609; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
7610; GFX9-NEXT:    s_movk_i32 s0, 0xfff
7611; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7612; GFX9-NEXT:    s_lshr_b64 s[4:5], s[4:5], 12
7613; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
7614; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
7615; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
7616; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7617; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
7618; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
7619; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
7620; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
7621; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
7622; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
7623; GFX9-NEXT:    v_mul_hi_u32 v6, s7, v1
7624; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
7625; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7626; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
7627; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v0
7628; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
7629; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
7630; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
7631; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
7632; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
7633; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
7634; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, 2, v0
7635; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s0
7636; GFX9-NEXT:    v_mul_hi_u32 v6, v0, s0
7637; GFX9-NEXT:    v_mul_lo_u32 v9, v0, s0
7638; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
7639; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, 1, v0
7640; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v1, vcc
7641; GFX9-NEXT:    v_add_u32_e32 v4, v6, v4
7642; GFX9-NEXT:    v_mov_b32_e32 v6, s7
7643; GFX9-NEXT:    v_sub_co_u32_e32 v9, vcc, s6, v9
7644; GFX9-NEXT:    v_subb_co_u32_e32 v4, vcc, v6, v4, vcc
7645; GFX9-NEXT:    v_subrev_co_u32_e32 v6, vcc, s0, v9
7646; GFX9-NEXT:    v_subbrev_co_u32_e32 v10, vcc, 0, v4, vcc
7647; GFX9-NEXT:    s_movk_i32 s0, 0xffe
7648; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v6
7649; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
7650; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v10
7651; GFX9-NEXT:    v_cndmask_b32_e32 v6, -1, v6, vcc
7652; GFX9-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v9
7653; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
7654; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
7655; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v4
7656; GFX9-NEXT:    v_cndmask_b32_e64 v4, -1, v6, s[0:1]
7657; GFX9-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
7658; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
7659; GFX9-NEXT:    v_cndmask_b32_e64 v3, v1, v3, s[0:1]
7660; GFX9-NEXT:    v_cndmask_b32_e32 v1, v7, v2, vcc
7661; GFX9-NEXT:    v_cndmask_b32_e64 v2, v0, v1, s[0:1]
7662; GFX9-NEXT:    v_mov_b32_e32 v0, s4
7663; GFX9-NEXT:    v_mov_b32_e32 v1, s5
7664; GFX9-NEXT:    global_store_dwordx4 v5, v[0:3], s[2:3]
7665; GFX9-NEXT:    s_endpgm
7666  %r = udiv <2 x i64> %x, <i64 4096, i64 4095>
7667  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
7668  ret void
7669}
7670
7671define amdgpu_kernel void @udiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
7672; CHECK-LABEL: @udiv_v2i64_pow2_shl_denom(
7673; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.*]]
7674; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
7675; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 0
7676; CHECK-NEXT:    [[TMP3:%.*]] = udiv i64 [[TMP1]], [[TMP2]]
7677; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i64 0
7678; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 1
7679; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
7680; CHECK-NEXT:    [[TMP7:%.*]] = udiv i64 [[TMP5]], [[TMP6]]
7681; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
7682; CHECK-NEXT:    store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
7683; CHECK-NEXT:    ret void
7684;
7685; GFX6-LABEL: udiv_v2i64_pow2_shl_denom:
7686; GFX6:       ; %bb.0:
7687; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
7688; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
7689; GFX6-NEXT:    s_mov_b32 s3, 0xf000
7690; GFX6-NEXT:    s_mov_b32 s2, -1
7691; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7692; GFX6-NEXT:    s_add_i32 s8, s8, 12
7693; GFX6-NEXT:    s_add_i32 s9, s10, 12
7694; GFX6-NEXT:    s_lshr_b64 s[4:5], s[4:5], s8
7695; GFX6-NEXT:    s_lshr_b64 s[6:7], s[6:7], s9
7696; GFX6-NEXT:    v_mov_b32_e32 v0, s4
7697; GFX6-NEXT:    v_mov_b32_e32 v1, s5
7698; GFX6-NEXT:    v_mov_b32_e32 v2, s6
7699; GFX6-NEXT:    v_mov_b32_e32 v3, s7
7700; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
7701; GFX6-NEXT:    s_endpgm
7702;
7703; GFX9-LABEL: udiv_v2i64_pow2_shl_denom:
7704; GFX9:       ; %bb.0:
7705; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
7706; GFX9-NEXT:    v_mov_b32_e32 v4, 0
7707; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
7708; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7709; GFX9-NEXT:    s_add_i32 s2, s8, 12
7710; GFX9-NEXT:    s_add_i32 s8, s10, 12
7711; GFX9-NEXT:    s_lshr_b64 s[2:3], s[4:5], s2
7712; GFX9-NEXT:    s_lshr_b64 s[4:5], s[6:7], s8
7713; GFX9-NEXT:    v_mov_b32_e32 v0, s2
7714; GFX9-NEXT:    v_mov_b32_e32 v1, s3
7715; GFX9-NEXT:    v_mov_b32_e32 v2, s4
7716; GFX9-NEXT:    v_mov_b32_e32 v3, s5
7717; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
7718; GFX9-NEXT:    s_endpgm
7719  %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
7720  %r = udiv <2 x i64> %x, %shl.y
7721  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
7722  ret void
7723}
7724
7725define amdgpu_kernel void @urem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
7726; CHECK-LABEL: @urem_i64_oddk_denom(
7727; CHECK-NEXT:    [[R:%.*]] = urem i64 [[X:%.*]], 1235195393993
7728; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
7729; CHECK-NEXT:    ret void
7730;
7731; GFX6-LABEL: urem_i64_oddk_denom:
7732; GFX6:       ; %bb.0:
7733; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f1761f8
7734; GFX6-NEXT:    v_mov_b32_e32 v1, 0x4f800000
7735; GFX6-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
7736; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
7737; GFX6-NEXT:    s_movk_i32 s2, 0xfee0
7738; GFX6-NEXT:    s_mov_b32 s3, 0x689e0837
7739; GFX6-NEXT:    v_mov_b32_e32 v7, 0
7740; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
7741; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
7742; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
7743; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
7744; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
7745; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
7746; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
7747; GFX6-NEXT:    s_mov_b32 s12, 0x9761f7c9
7748; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s2
7749; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s3
7750; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s3
7751; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7752; GFX6-NEXT:    s_mov_b32 s8, s4
7753; GFX6-NEXT:    s_movk_i32 s4, 0x11f
7754; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7755; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s3
7756; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
7757; GFX6-NEXT:    v_mul_lo_u32 v4, v0, v2
7758; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v3
7759; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
7760; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
7761; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
7762; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
7763; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
7764; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
7765; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
7766; GFX6-NEXT:    s_mov_b32 s9, s5
7767; GFX6-NEXT:    s_movk_i32 s5, 0x11e
7768; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
7769; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
7770; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
7771; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7772; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
7773; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
7774; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
7775; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s2
7776; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s3
7777; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s3
7778; GFX6-NEXT:    s_mov_b32 s11, 0xf000
7779; GFX6-NEXT:    s_mov_b32 s10, -1
7780; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7781; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s3
7782; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
7783; GFX6-NEXT:    v_mul_lo_u32 v4, v0, v2
7784; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v3
7785; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
7786; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
7787; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
7788; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
7789; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
7790; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
7791; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
7792; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
7793; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
7794; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
7795; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7796; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
7797; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
7798; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
7799; GFX6-NEXT:    v_mul_lo_u32 v2, s6, v1
7800; GFX6-NEXT:    v_mul_hi_u32 v3, s6, v0
7801; GFX6-NEXT:    v_mul_hi_u32 v4, s6, v1
7802; GFX6-NEXT:    v_mul_hi_u32 v5, s7, v1
7803; GFX6-NEXT:    v_mul_lo_u32 v1, s7, v1
7804; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7805; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
7806; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v0
7807; GFX6-NEXT:    v_mul_hi_u32 v0, s7, v0
7808; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
7809; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
7810; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
7811; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
7812; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
7813; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s4
7814; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s12
7815; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s12
7816; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s12
7817; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
7818; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
7819; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s7, v1
7820; GFX6-NEXT:    v_mov_b32_e32 v3, s4
7821; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
7822; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
7823; GFX6-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
7824; GFX6-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
7825; GFX6-NEXT:    v_cmp_lt_u32_e64 s[2:3], s5, v5
7826; GFX6-NEXT:    s_mov_b32 s6, 0x9761f7c8
7827; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
7828; GFX6-NEXT:    v_cmp_lt_u32_e64 s[2:3], s6, v4
7829; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
7830; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
7831; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s4, v5
7832; GFX6-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
7833; GFX6-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
7834; GFX6-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
7835; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
7836; GFX6-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
7837; GFX6-NEXT:    v_mov_b32_e32 v5, s7
7838; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
7839; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s5, v1
7840; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
7841; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v0
7842; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
7843; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v1
7844; GFX6-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
7845; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
7846; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
7847; GFX6-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
7848; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
7849; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
7850; GFX6-NEXT:    s_endpgm
7851;
7852; GFX9-LABEL: urem_i64_oddk_denom:
7853; GFX9:       ; %bb.0:
7854; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f1761f8
7855; GFX9-NEXT:    v_mov_b32_e32 v1, 0x4f800000
7856; GFX9-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
7857; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
7858; GFX9-NEXT:    s_movk_i32 s2, 0xfee0
7859; GFX9-NEXT:    s_mov_b32 s3, 0x689e0837
7860; GFX9-NEXT:    v_mov_b32_e32 v6, 0
7861; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
7862; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
7863; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
7864; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
7865; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
7866; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
7867; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
7868; GFX9-NEXT:    s_movk_i32 s8, 0x11f
7869; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s2
7870; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s3
7871; GFX9-NEXT:    v_mul_lo_u32 v5, v1, s3
7872; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s3
7873; GFX9-NEXT:    s_mov_b32 s9, 0x9761f7c9
7874; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
7875; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
7876; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
7877; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
7878; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
7879; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
7880; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
7881; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
7882; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
7883; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
7884; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
7885; GFX9-NEXT:    s_mov_b32 s10, 0x9761f7c8
7886; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
7887; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
7888; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
7889; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7890; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
7891; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
7892; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
7893; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s2
7894; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s3
7895; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s3
7896; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s3
7897; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
7898; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
7899; GFX9-NEXT:    v_mul_lo_u32 v3, v0, v2
7900; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v5
7901; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
7902; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
7903; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
7904; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
7905; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v7, vcc
7906; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v5
7907; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v5
7908; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
7909; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v4, v5, vcc
7910; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
7911; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7912; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
7913; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
7914; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
7915; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7916; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
7917; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
7918; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
7919; GFX9-NEXT:    v_mul_hi_u32 v5, s7, v1
7920; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
7921; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
7922; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
7923; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v0
7924; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
7925; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
7926; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
7927; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v5, v6, vcc
7928; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
7929; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
7930; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s8
7931; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s9
7932; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s9
7933; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s9
7934; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
7935; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
7936; GFX9-NEXT:    v_sub_u32_e32 v2, s7, v1
7937; GFX9-NEXT:    v_mov_b32_e32 v3, s8
7938; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, s6, v0
7939; GFX9-NEXT:    v_subb_co_u32_e64 v2, s[0:1], v2, v3, vcc
7940; GFX9-NEXT:    v_subrev_co_u32_e64 v4, s[0:1], s9, v0
7941; GFX9-NEXT:    v_subbrev_co_u32_e64 v5, s[2:3], 0, v2, s[0:1]
7942; GFX9-NEXT:    s_movk_i32 s6, 0x11e
7943; GFX9-NEXT:    v_cmp_lt_u32_e64 s[2:3], s6, v5
7944; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
7945; GFX9-NEXT:    v_cmp_lt_u32_e64 s[2:3], s10, v4
7946; GFX9-NEXT:    v_subb_co_u32_e64 v2, s[0:1], v2, v3, s[0:1]
7947; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[2:3]
7948; GFX9-NEXT:    v_cmp_eq_u32_e64 s[2:3], s8, v5
7949; GFX9-NEXT:    v_subrev_co_u32_e64 v3, s[0:1], s9, v4
7950; GFX9-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[2:3]
7951; GFX9-NEXT:    v_subbrev_co_u32_e64 v2, s[0:1], 0, v2, s[0:1]
7952; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v7
7953; GFX9-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
7954; GFX9-NEXT:    v_mov_b32_e32 v5, s7
7955; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v5, v1, vcc
7956; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v1
7957; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
7958; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s10, v0
7959; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
7960; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s8, v1
7961; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
7962; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
7963; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
7964; GFX9-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
7965; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
7966; GFX9-NEXT:    global_store_dwordx2 v6, v[0:1], s[4:5]
7967; GFX9-NEXT:    s_endpgm
7968  %r = urem i64 %x, 1235195393993
7969  store i64 %r, i64 addrspace(1)* %out
7970  ret void
7971}
7972
7973define amdgpu_kernel void @urem_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) {
7974; CHECK-LABEL: @urem_i64_pow2k_denom(
7975; CHECK-NEXT:    [[R:%.*]] = urem i64 [[X:%.*]], 4096
7976; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
7977; CHECK-NEXT:    ret void
7978;
7979; GFX6-LABEL: urem_i64_pow2k_denom:
7980; GFX6:       ; %bb.0:
7981; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
7982; GFX6-NEXT:    s_mov_b32 s7, 0xf000
7983; GFX6-NEXT:    s_mov_b32 s6, -1
7984; GFX6-NEXT:    v_mov_b32_e32 v1, 0
7985; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
7986; GFX6-NEXT:    s_mov_b32 s4, s0
7987; GFX6-NEXT:    s_and_b32 s0, s2, 0xfff
7988; GFX6-NEXT:    s_mov_b32 s5, s1
7989; GFX6-NEXT:    v_mov_b32_e32 v0, s0
7990; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
7991; GFX6-NEXT:    s_endpgm
7992;
7993; GFX9-LABEL: urem_i64_pow2k_denom:
7994; GFX9:       ; %bb.0:
7995; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
7996; GFX9-NEXT:    v_mov_b32_e32 v1, 0
7997; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
7998; GFX9-NEXT:    s_and_b32 s2, s2, 0xfff
7999; GFX9-NEXT:    v_mov_b32_e32 v0, s2
8000; GFX9-NEXT:    global_store_dwordx2 v1, v[0:1], s[0:1]
8001; GFX9-NEXT:    s_endpgm
8002  %r = urem i64 %x, 4096
8003  store i64 %r, i64 addrspace(1)* %out
8004  ret void
8005}
8006
8007define amdgpu_kernel void @urem_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %x, i64 %y) {
8008; CHECK-LABEL: @urem_i64_pow2_shl_denom(
8009; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]]
8010; CHECK-NEXT:    [[R:%.*]] = urem i64 [[X:%.*]], [[SHL_Y]]
8011; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
8012; CHECK-NEXT:    ret void
8013;
8014; GFX6-LABEL: urem_i64_pow2_shl_denom:
8015; GFX6:       ; %bb.0:
8016; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
8017; GFX6-NEXT:    s_load_dword s8, s[0:1], 0xd
8018; GFX6-NEXT:    s_mov_b32 s3, 0xf000
8019; GFX6-NEXT:    s_mov_b32 s2, -1
8020; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8021; GFX6-NEXT:    s_mov_b32 s0, s4
8022; GFX6-NEXT:    s_mov_b32 s1, s5
8023; GFX6-NEXT:    s_mov_b64 s[4:5], 0x1000
8024; GFX6-NEXT:    s_lshl_b64 s[4:5], s[4:5], s8
8025; GFX6-NEXT:    s_add_u32 s4, s4, -1
8026; GFX6-NEXT:    s_addc_u32 s5, s5, -1
8027; GFX6-NEXT:    s_and_b64 s[4:5], s[6:7], s[4:5]
8028; GFX6-NEXT:    v_mov_b32_e32 v0, s4
8029; GFX6-NEXT:    v_mov_b32_e32 v1, s5
8030; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
8031; GFX6-NEXT:    s_endpgm
8032;
8033; GFX9-LABEL: urem_i64_pow2_shl_denom:
8034; GFX9:       ; %bb.0:
8035; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x34
8036; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
8037; GFX9-NEXT:    s_mov_b64 s[0:1], 0x1000
8038; GFX9-NEXT:    v_mov_b32_e32 v2, 0
8039; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8040; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s2
8041; GFX9-NEXT:    s_add_u32 s0, s0, -1
8042; GFX9-NEXT:    s_addc_u32 s1, s1, -1
8043; GFX9-NEXT:    s_and_b64 s[0:1], s[6:7], s[0:1]
8044; GFX9-NEXT:    v_mov_b32_e32 v0, s0
8045; GFX9-NEXT:    v_mov_b32_e32 v1, s1
8046; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
8047; GFX9-NEXT:    s_endpgm
8048  %shl.y = shl i64 4096, %y
8049  %r = urem i64 %x, %shl.y
8050  store i64 %r, i64 addrspace(1)* %out
8051  ret void
8052}
8053
8054define amdgpu_kernel void @urem_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
8055; CHECK-LABEL: @urem_v2i64_pow2k_denom(
8056; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
8057; CHECK-NEXT:    [[TMP2:%.*]] = urem i64 [[TMP1]], 4096
8058; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
8059; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
8060; CHECK-NEXT:    [[TMP5:%.*]] = urem i64 [[TMP4]], 4096
8061; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
8062; CHECK-NEXT:    store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
8063; CHECK-NEXT:    ret void
8064;
8065; GFX6-LABEL: urem_v2i64_pow2k_denom:
8066; GFX6:       ; %bb.0:
8067; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
8068; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
8069; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8070; GFX6-NEXT:    s_movk_i32 s5, 0xfff
8071; GFX6-NEXT:    v_mov_b32_e32 v1, 0
8072; GFX6-NEXT:    s_mov_b32 s3, 0xf000
8073; GFX6-NEXT:    s_and_b32 s4, s4, s5
8074; GFX6-NEXT:    s_and_b32 s5, s6, s5
8075; GFX6-NEXT:    s_mov_b32 s2, -1
8076; GFX6-NEXT:    v_mov_b32_e32 v0, s4
8077; GFX6-NEXT:    v_mov_b32_e32 v2, s5
8078; GFX6-NEXT:    v_mov_b32_e32 v3, v1
8079; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
8080; GFX6-NEXT:    s_endpgm
8081;
8082; GFX9-LABEL: urem_v2i64_pow2k_denom:
8083; GFX9:       ; %bb.0:
8084; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
8085; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
8086; GFX9-NEXT:    s_movk_i32 s0, 0xfff
8087; GFX9-NEXT:    v_mov_b32_e32 v1, 0
8088; GFX9-NEXT:    v_mov_b32_e32 v3, v1
8089; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8090; GFX9-NEXT:    s_and_b32 s1, s4, s0
8091; GFX9-NEXT:    s_and_b32 s0, s6, s0
8092; GFX9-NEXT:    v_mov_b32_e32 v0, s1
8093; GFX9-NEXT:    v_mov_b32_e32 v2, s0
8094; GFX9-NEXT:    global_store_dwordx4 v1, v[0:3], s[2:3]
8095; GFX9-NEXT:    s_endpgm
8096  %r = urem <2 x i64> %x, <i64 4096, i64 4096>
8097  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
8098  ret void
8099}
8100
8101define amdgpu_kernel void @urem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
8102; CHECK-LABEL: @urem_v2i64_pow2_shl_denom(
8103; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.*]]
8104; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
8105; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 0
8106; CHECK-NEXT:    [[TMP3:%.*]] = urem i64 [[TMP1]], [[TMP2]]
8107; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i64 0
8108; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 1
8109; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
8110; CHECK-NEXT:    [[TMP7:%.*]] = urem i64 [[TMP5]], [[TMP6]]
8111; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
8112; CHECK-NEXT:    store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
8113; CHECK-NEXT:    ret void
8114;
8115; GFX6-LABEL: urem_v2i64_pow2_shl_denom:
8116; GFX6:       ; %bb.0:
8117; GFX6-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x9
8118; GFX6-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0xd
8119; GFX6-NEXT:    s_mov_b64 s[12:13], 0x1000
8120; GFX6-NEXT:    s_mov_b32 s11, 0xf000
8121; GFX6-NEXT:    s_mov_b32 s10, -1
8122; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8123; GFX6-NEXT:    s_lshl_b64 s[6:7], s[12:13], s6
8124; GFX6-NEXT:    s_lshl_b64 s[4:5], s[12:13], s4
8125; GFX6-NEXT:    s_add_u32 s4, s4, -1
8126; GFX6-NEXT:    s_addc_u32 s5, s5, -1
8127; GFX6-NEXT:    s_and_b64 s[0:1], s[0:1], s[4:5]
8128; GFX6-NEXT:    s_add_u32 s4, s6, -1
8129; GFX6-NEXT:    s_addc_u32 s5, s7, -1
8130; GFX6-NEXT:    s_and_b64 s[2:3], s[2:3], s[4:5]
8131; GFX6-NEXT:    v_mov_b32_e32 v0, s0
8132; GFX6-NEXT:    v_mov_b32_e32 v1, s1
8133; GFX6-NEXT:    v_mov_b32_e32 v2, s2
8134; GFX6-NEXT:    v_mov_b32_e32 v3, s3
8135; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
8136; GFX6-NEXT:    s_endpgm
8137;
8138; GFX9-LABEL: urem_v2i64_pow2_shl_denom:
8139; GFX9:       ; %bb.0:
8140; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
8141; GFX9-NEXT:    s_mov_b64 s[2:3], 0x1000
8142; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
8143; GFX9-NEXT:    v_mov_b32_e32 v4, 0
8144; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8145; GFX9-NEXT:    s_lshl_b64 s[10:11], s[2:3], s10
8146; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s8
8147; GFX9-NEXT:    s_add_u32 s2, s2, -1
8148; GFX9-NEXT:    s_addc_u32 s3, s3, -1
8149; GFX9-NEXT:    s_and_b64 s[2:3], s[4:5], s[2:3]
8150; GFX9-NEXT:    s_add_u32 s4, s10, -1
8151; GFX9-NEXT:    s_addc_u32 s5, s11, -1
8152; GFX9-NEXT:    s_and_b64 s[4:5], s[6:7], s[4:5]
8153; GFX9-NEXT:    v_mov_b32_e32 v0, s2
8154; GFX9-NEXT:    v_mov_b32_e32 v1, s3
8155; GFX9-NEXT:    v_mov_b32_e32 v2, s4
8156; GFX9-NEXT:    v_mov_b32_e32 v3, s5
8157; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
8158; GFX9-NEXT:    s_endpgm
8159  %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
8160  %r = urem <2 x i64> %x, %shl.y
8161  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
8162  ret void
8163}
8164
8165define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
8166; CHECK-LABEL: @sdiv_i64_oddk_denom(
8167; CHECK-NEXT:    [[R:%.*]] = sdiv i64 [[X:%.*]], 1235195
8168; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
8169; CHECK-NEXT:    ret void
8170;
8171; GFX6-LABEL: sdiv_i64_oddk_denom:
8172; GFX6:       ; %bb.0:
8173; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f800000
8174; GFX6-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
8175; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
8176; GFX6-NEXT:    s_mov_b32 s5, 0xffed2705
8177; GFX6-NEXT:    v_mov_b32_e32 v7, 0
8178; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
8179; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
8180; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
8181; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
8182; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
8183; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
8184; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
8185; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8186; GFX6-NEXT:    s_ashr_i32 s8, s3, 31
8187; GFX6-NEXT:    s_add_u32 s2, s2, s8
8188; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s5
8189; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s5
8190; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s5
8191; GFX6-NEXT:    s_mov_b32 s9, s8
8192; GFX6-NEXT:    s_addc_u32 s3, s3, s8
8193; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8194; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
8195; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
8196; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v4
8197; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
8198; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
8199; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
8200; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
8201; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
8202; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
8203; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
8204; GFX6-NEXT:    s_xor_b64 s[2:3], s[2:3], s[8:9]
8205; GFX6-NEXT:    s_mov_b32 s4, s0
8206; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
8207; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
8208; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
8209; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8210; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
8211; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
8212; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
8213; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s5
8214; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s5
8215; GFX6-NEXT:    s_mov_b32 s0, 0x12d8fb
8216; GFX6-NEXT:    s_mov_b32 s7, 0xf000
8217; GFX6-NEXT:    s_mov_b32 s6, -1
8218; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8219; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s5
8220; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
8221; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v2
8222; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v3
8223; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v2
8224; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v3
8225; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
8226; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v2
8227; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
8228; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
8229; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
8230; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
8231; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v5, vcc
8232; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v4, v7, vcc
8233; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8234; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
8235; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
8236; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
8237; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
8238; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
8239; GFX6-NEXT:    v_mul_hi_u32 v4, s2, v1
8240; GFX6-NEXT:    v_mul_hi_u32 v5, s3, v1
8241; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v1
8242; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8243; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
8244; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v0
8245; GFX6-NEXT:    v_mul_hi_u32 v0, s3, v0
8246; GFX6-NEXT:    s_mov_b32 s5, s1
8247; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
8248; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
8249; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
8250; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
8251; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
8252; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s0
8253; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s0
8254; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 2, v0
8255; GFX6-NEXT:    v_mul_lo_u32 v8, v0, s0
8256; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
8257; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v0
8258; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v1, vcc
8259; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
8260; GFX6-NEXT:    v_mov_b32_e32 v5, s3
8261; GFX6-NEXT:    v_sub_i32_e32 v8, vcc, s2, v8
8262; GFX6-NEXT:    v_subb_u32_e32 v4, vcc, v5, v4, vcc
8263; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s0, v8
8264; GFX6-NEXT:    v_subbrev_u32_e32 v9, vcc, 0, v4, vcc
8265; GFX6-NEXT:    s_mov_b32 s0, 0x12d8fa
8266; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v5
8267; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
8268; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v9
8269; GFX6-NEXT:    v_cndmask_b32_e32 v5, -1, v5, vcc
8270; GFX6-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v8
8271; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
8272; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
8273; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v4
8274; GFX6-NEXT:    v_cndmask_b32_e64 v4, -1, v5, s[0:1]
8275; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
8276; GFX6-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
8277; GFX6-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
8278; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
8279; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
8280; GFX6-NEXT:    v_xor_b32_e32 v0, s8, v0
8281; GFX6-NEXT:    v_xor_b32_e32 v1, s8, v1
8282; GFX6-NEXT:    v_mov_b32_e32 v2, s8
8283; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v0
8284; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
8285; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
8286; GFX6-NEXT:    s_endpgm
8287;
8288; GFX9-LABEL: sdiv_i64_oddk_denom:
8289; GFX9:       ; %bb.0:
8290; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f800000
8291; GFX9-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
8292; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
8293; GFX9-NEXT:    s_mov_b32 s2, 0xffed2705
8294; GFX9-NEXT:    v_mov_b32_e32 v5, 0
8295; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
8296; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
8297; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
8298; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
8299; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
8300; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
8301; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
8302; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s2
8303; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s2
8304; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s2
8305; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
8306; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
8307; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
8308; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
8309; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
8310; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
8311; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
8312; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
8313; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
8314; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
8315; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
8316; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
8317; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
8318; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
8319; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
8320; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
8321; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
8322; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
8323; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s2
8324; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s2
8325; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s2
8326; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8327; GFX9-NEXT:    s_ashr_i32 s2, s7, 31
8328; GFX9-NEXT:    s_add_u32 s0, s6, s2
8329; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
8330; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
8331; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v2
8332; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v4
8333; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v2
8334; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v4
8335; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v4
8336; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v2
8337; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
8338; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
8339; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
8340; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v7, v4
8341; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
8342; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v5, vcc
8343; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
8344; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
8345; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
8346; GFX9-NEXT:    s_mov_b32 s3, s2
8347; GFX9-NEXT:    s_addc_u32 s1, s7, s2
8348; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
8349; GFX9-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
8350; GFX9-NEXT:    v_mul_lo_u32 v2, s0, v1
8351; GFX9-NEXT:    v_mul_hi_u32 v3, s0, v0
8352; GFX9-NEXT:    v_mul_hi_u32 v4, s0, v1
8353; GFX9-NEXT:    v_mul_hi_u32 v6, s1, v1
8354; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v1
8355; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
8356; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
8357; GFX9-NEXT:    v_mul_lo_u32 v4, s1, v0
8358; GFX9-NEXT:    v_mul_hi_u32 v0, s1, v0
8359; GFX9-NEXT:    s_mov_b32 s3, 0x12d8fb
8360; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
8361; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
8362; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
8363; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
8364; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
8365; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, 2, v0
8366; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s3
8367; GFX9-NEXT:    v_mul_hi_u32 v6, v0, s3
8368; GFX9-NEXT:    v_mul_lo_u32 v9, v0, s3
8369; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
8370; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, 1, v0
8371; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v1, vcc
8372; GFX9-NEXT:    v_add_u32_e32 v4, v6, v4
8373; GFX9-NEXT:    v_mov_b32_e32 v6, s1
8374; GFX9-NEXT:    v_sub_co_u32_e32 v9, vcc, s0, v9
8375; GFX9-NEXT:    v_subb_co_u32_e32 v4, vcc, v6, v4, vcc
8376; GFX9-NEXT:    v_subrev_co_u32_e32 v6, vcc, s3, v9
8377; GFX9-NEXT:    v_subbrev_co_u32_e32 v10, vcc, 0, v4, vcc
8378; GFX9-NEXT:    s_mov_b32 s0, 0x12d8fa
8379; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v6
8380; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
8381; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v10
8382; GFX9-NEXT:    v_cndmask_b32_e32 v6, -1, v6, vcc
8383; GFX9-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v9
8384; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
8385; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
8386; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v4
8387; GFX9-NEXT:    v_cndmask_b32_e64 v4, -1, v6, s[0:1]
8388; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
8389; GFX9-NEXT:    v_cndmask_b32_e32 v2, v7, v2, vcc
8390; GFX9-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
8391; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
8392; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
8393; GFX9-NEXT:    v_xor_b32_e32 v0, s2, v0
8394; GFX9-NEXT:    v_xor_b32_e32 v1, s2, v1
8395; GFX9-NEXT:    v_mov_b32_e32 v2, s2
8396; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s2, v0
8397; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
8398; GFX9-NEXT:    global_store_dwordx2 v5, v[0:1], s[4:5]
8399; GFX9-NEXT:    s_endpgm
8400  %r = sdiv i64 %x, 1235195
8401  store i64 %r, i64 addrspace(1)* %out
8402  ret void
8403}
8404
8405define amdgpu_kernel void @sdiv_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) {
8406; CHECK-LABEL: @sdiv_i64_pow2k_denom(
8407; CHECK-NEXT:    [[R:%.*]] = sdiv i64 [[X:%.*]], 4096
8408; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
8409; CHECK-NEXT:    ret void
8410;
8411; GFX6-LABEL: sdiv_i64_pow2k_denom:
8412; GFX6:       ; %bb.0:
8413; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
8414; GFX6-NEXT:    s_mov_b32 s7, 0xf000
8415; GFX6-NEXT:    s_mov_b32 s6, -1
8416; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8417; GFX6-NEXT:    s_mov_b32 s4, s0
8418; GFX6-NEXT:    s_ashr_i32 s0, s3, 31
8419; GFX6-NEXT:    s_lshr_b32 s0, s0, 20
8420; GFX6-NEXT:    s_add_u32 s0, s2, s0
8421; GFX6-NEXT:    s_mov_b32 s5, s1
8422; GFX6-NEXT:    s_addc_u32 s1, s3, 0
8423; GFX6-NEXT:    s_ashr_i64 s[0:1], s[0:1], 12
8424; GFX6-NEXT:    v_mov_b32_e32 v0, s0
8425; GFX6-NEXT:    v_mov_b32_e32 v1, s1
8426; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
8427; GFX6-NEXT:    s_endpgm
8428;
8429; GFX9-LABEL: sdiv_i64_pow2k_denom:
8430; GFX9:       ; %bb.0:
8431; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
8432; GFX9-NEXT:    v_mov_b32_e32 v2, 0
8433; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8434; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
8435; GFX9-NEXT:    s_lshr_b32 s4, s4, 20
8436; GFX9-NEXT:    s_add_u32 s2, s2, s4
8437; GFX9-NEXT:    s_addc_u32 s3, s3, 0
8438; GFX9-NEXT:    s_ashr_i64 s[2:3], s[2:3], 12
8439; GFX9-NEXT:    v_mov_b32_e32 v0, s2
8440; GFX9-NEXT:    v_mov_b32_e32 v1, s3
8441; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
8442; GFX9-NEXT:    s_endpgm
8443  %r = sdiv i64 %x, 4096
8444  store i64 %r, i64 addrspace(1)* %out
8445  ret void
8446}
8447
8448define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %x, i64 %y) {
8449; CHECK-LABEL: @sdiv_i64_pow2_shl_denom(
8450; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]]
8451; CHECK-NEXT:    [[R:%.*]] = sdiv i64 [[X:%.*]], [[SHL_Y]]
8452; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
8453; CHECK-NEXT:    ret void
8454;
8455; GFX6-LABEL: sdiv_i64_pow2_shl_denom:
8456; GFX6:       ; %bb.0:
8457; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xd
8458; GFX6-NEXT:    s_mov_b64 s[2:3], 0x1000
8459; GFX6-NEXT:    s_mov_b32 s7, 0xf000
8460; GFX6-NEXT:    s_mov_b32 s6, -1
8461; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8462; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
8463; GFX6-NEXT:    s_ashr_i32 s8, s3, 31
8464; GFX6-NEXT:    s_add_u32 s2, s2, s8
8465; GFX6-NEXT:    s_mov_b32 s9, s8
8466; GFX6-NEXT:    s_addc_u32 s3, s3, s8
8467; GFX6-NEXT:    s_xor_b64 s[10:11], s[2:3], s[8:9]
8468; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s10
8469; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s11
8470; GFX6-NEXT:    s_sub_u32 s4, 0, s10
8471; GFX6-NEXT:    s_subb_u32 s5, 0, s11
8472; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
8473; GFX6-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
8474; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
8475; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8476; GFX6-NEXT:    s_ashr_i32 s12, s3, 31
8477; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
8478; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
8479; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
8480; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
8481; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
8482; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
8483; GFX6-NEXT:    s_add_u32 s2, s2, s12
8484; GFX6-NEXT:    s_mov_b32 s13, s12
8485; GFX6-NEXT:    v_mul_lo_u32 v2, s4, v1
8486; GFX6-NEXT:    v_mul_hi_u32 v3, s4, v0
8487; GFX6-NEXT:    v_mul_lo_u32 v5, s5, v0
8488; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v0
8489; GFX6-NEXT:    s_addc_u32 s3, s3, s12
8490; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8491; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
8492; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
8493; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
8494; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
8495; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
8496; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
8497; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
8498; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
8499; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
8500; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
8501; GFX6-NEXT:    s_xor_b64 s[2:3], s[2:3], s[12:13]
8502; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
8503; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
8504; GFX6-NEXT:    v_mov_b32_e32 v4, 0
8505; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
8506; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8507; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
8508; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
8509; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
8510; GFX6-NEXT:    v_mul_lo_u32 v2, s4, v1
8511; GFX6-NEXT:    v_mul_hi_u32 v3, s4, v0
8512; GFX6-NEXT:    v_mul_lo_u32 v5, s5, v0
8513; GFX6-NEXT:    s_mov_b32 s5, s1
8514; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8515; GFX6-NEXT:    v_mul_lo_u32 v3, s4, v0
8516; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
8517; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v2
8518; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v3
8519; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v2
8520; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v3
8521; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
8522; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v2
8523; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
8524; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
8525; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
8526; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
8527; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v6, vcc
8528; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v5, v4, vcc
8529; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8530; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
8531; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
8532; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
8533; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
8534; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
8535; GFX6-NEXT:    v_mul_hi_u32 v5, s2, v1
8536; GFX6-NEXT:    v_mul_hi_u32 v6, s3, v1
8537; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v1
8538; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8539; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
8540; GFX6-NEXT:    v_mul_lo_u32 v5, s3, v0
8541; GFX6-NEXT:    v_mul_hi_u32 v0, s3, v0
8542; GFX6-NEXT:    s_mov_b32 s4, s0
8543; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
8544; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
8545; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v6, v4, vcc
8546; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
8547; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
8548; GFX6-NEXT:    v_mul_lo_u32 v2, s10, v1
8549; GFX6-NEXT:    v_mul_hi_u32 v3, s10, v0
8550; GFX6-NEXT:    v_mul_lo_u32 v4, s11, v0
8551; GFX6-NEXT:    v_mov_b32_e32 v5, s11
8552; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8553; GFX6-NEXT:    v_mul_lo_u32 v3, s10, v0
8554; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
8555; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s3, v2
8556; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s2, v3
8557; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
8558; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s10, v3
8559; GFX6-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
8560; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v4
8561; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
8562; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v5
8563; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
8564; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v4
8565; GFX6-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
8566; GFX6-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
8567; GFX6-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
8568; GFX6-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
8569; GFX6-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
8570; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
8571; GFX6-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
8572; GFX6-NEXT:    v_mov_b32_e32 v6, s3
8573; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
8574; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v2
8575; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
8576; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
8577; GFX6-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
8578; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v2
8579; GFX6-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
8580; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
8581; GFX6-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
8582; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
8583; GFX6-NEXT:    s_xor_b64 s[0:1], s[12:13], s[8:9]
8584; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
8585; GFX6-NEXT:    v_xor_b32_e32 v0, s0, v0
8586; GFX6-NEXT:    v_xor_b32_e32 v1, s1, v1
8587; GFX6-NEXT:    v_mov_b32_e32 v2, s1
8588; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
8589; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
8590; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
8591; GFX6-NEXT:    s_endpgm
8592;
8593; GFX9-LABEL: sdiv_i64_pow2_shl_denom:
8594; GFX9:       ; %bb.0:
8595; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x34
8596; GFX9-NEXT:    s_mov_b64 s[2:3], 0x1000
8597; GFX9-NEXT:    v_mov_b32_e32 v2, 0
8598; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8599; GFX9-NEXT:    s_lshl_b64 s[4:5], s[2:3], s4
8600; GFX9-NEXT:    s_ashr_i32 s2, s5, 31
8601; GFX9-NEXT:    s_add_u32 s4, s4, s2
8602; GFX9-NEXT:    s_mov_b32 s3, s2
8603; GFX9-NEXT:    s_addc_u32 s5, s5, s2
8604; GFX9-NEXT:    s_xor_b64 s[8:9], s[4:5], s[2:3]
8605; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
8606; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
8607; GFX9-NEXT:    s_sub_u32 s10, 0, s8
8608; GFX9-NEXT:    s_subb_u32 s4, 0, s9
8609; GFX9-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
8610; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
8611; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
8612; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
8613; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
8614; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
8615; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
8616; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
8617; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v1
8618; GFX9-NEXT:    v_mul_hi_u32 v4, s10, v0
8619; GFX9-NEXT:    v_mul_lo_u32 v6, s4, v0
8620; GFX9-NEXT:    v_mul_lo_u32 v5, s10, v0
8621; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
8622; GFX9-NEXT:    v_add_u32_e32 v3, v3, v6
8623; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v5
8624; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v3
8625; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v3
8626; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v5
8627; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
8628; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v3
8629; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
8630; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
8631; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
8632; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v5
8633; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
8634; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v2, vcc
8635; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
8636; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
8637; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
8638; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
8639; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v1
8640; GFX9-NEXT:    v_mul_hi_u32 v4, s10, v0
8641; GFX9-NEXT:    v_mul_lo_u32 v5, s4, v0
8642; GFX9-NEXT:    v_mul_lo_u32 v6, s10, v0
8643; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
8644; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
8645; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
8646; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v3
8647; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v6
8648; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v3
8649; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v6
8650; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
8651; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v3
8652; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
8653; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
8654; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
8655; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
8656; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v5, vcc
8657; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v2, vcc
8658; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
8659; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8660; GFX9-NEXT:    s_ashr_i32 s10, s7, 31
8661; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
8662; GFX9-NEXT:    s_add_u32 s0, s6, s10
8663; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
8664; GFX9-NEXT:    s_mov_b32 s11, s10
8665; GFX9-NEXT:    s_addc_u32 s1, s7, s10
8666; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
8667; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[10:11]
8668; GFX9-NEXT:    v_mul_lo_u32 v3, s6, v1
8669; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v0
8670; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v1
8671; GFX9-NEXT:    v_mul_hi_u32 v6, s7, v1
8672; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
8673; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
8674; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
8675; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v0
8676; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
8677; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
8678; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v4, v0, vcc
8679; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v2, vcc
8680; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
8681; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
8682; GFX9-NEXT:    v_mul_lo_u32 v3, s8, v1
8683; GFX9-NEXT:    v_mul_hi_u32 v4, s8, v0
8684; GFX9-NEXT:    v_mul_lo_u32 v5, s9, v0
8685; GFX9-NEXT:    v_mov_b32_e32 v6, s9
8686; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
8687; GFX9-NEXT:    v_mul_lo_u32 v4, s8, v0
8688; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
8689; GFX9-NEXT:    v_sub_u32_e32 v5, s7, v3
8690; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, s6, v4
8691; GFX9-NEXT:    v_subb_co_u32_e64 v5, s[0:1], v5, v6, vcc
8692; GFX9-NEXT:    v_subrev_co_u32_e64 v6, s[0:1], s8, v4
8693; GFX9-NEXT:    v_subbrev_co_u32_e64 v5, s[0:1], 0, v5, s[0:1]
8694; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v5
8695; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
8696; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v6
8697; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
8698; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v5
8699; GFX9-NEXT:    v_cndmask_b32_e64 v5, v7, v6, s[0:1]
8700; GFX9-NEXT:    v_add_co_u32_e64 v6, s[0:1], 2, v0
8701; GFX9-NEXT:    v_addc_co_u32_e64 v7, s[0:1], 0, v1, s[0:1]
8702; GFX9-NEXT:    v_add_co_u32_e64 v8, s[0:1], 1, v0
8703; GFX9-NEXT:    v_addc_co_u32_e64 v9, s[0:1], 0, v1, s[0:1]
8704; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
8705; GFX9-NEXT:    v_cndmask_b32_e64 v5, v9, v7, s[0:1]
8706; GFX9-NEXT:    v_mov_b32_e32 v7, s7
8707; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v7, v3, vcc
8708; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
8709; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
8710; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v4
8711; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
8712; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v3
8713; GFX9-NEXT:    v_cndmask_b32_e32 v3, v7, v4, vcc
8714; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
8715; GFX9-NEXT:    v_cndmask_b32_e64 v3, v8, v6, s[0:1]
8716; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
8717; GFX9-NEXT:    s_xor_b64 s[0:1], s[10:11], s[2:3]
8718; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
8719; GFX9-NEXT:    v_xor_b32_e32 v0, s0, v0
8720; GFX9-NEXT:    v_xor_b32_e32 v1, s1, v1
8721; GFX9-NEXT:    v_mov_b32_e32 v3, s1
8722; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s0, v0
8723; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
8724; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
8725; GFX9-NEXT:    s_endpgm
8726  %shl.y = shl i64 4096, %y
8727  %r = sdiv i64 %x, %shl.y
8728  store i64 %r, i64 addrspace(1)* %out
8729  ret void
8730}
8731
8732define amdgpu_kernel void @sdiv_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
8733; CHECK-LABEL: @sdiv_v2i64_pow2k_denom(
8734; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
8735; CHECK-NEXT:    [[TMP2:%.*]] = sdiv i64 [[TMP1]], 4096
8736; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
8737; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
8738; CHECK-NEXT:    [[TMP5:%.*]] = sdiv i64 [[TMP4]], 4096
8739; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
8740; CHECK-NEXT:    store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
8741; CHECK-NEXT:    ret void
8742;
8743; GFX6-LABEL: sdiv_v2i64_pow2k_denom:
8744; GFX6:       ; %bb.0:
8745; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
8746; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
8747; GFX6-NEXT:    s_mov_b32 s3, 0xf000
8748; GFX6-NEXT:    s_mov_b32 s2, -1
8749; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8750; GFX6-NEXT:    s_ashr_i32 s8, s5, 31
8751; GFX6-NEXT:    s_lshr_b32 s8, s8, 20
8752; GFX6-NEXT:    s_add_u32 s4, s4, s8
8753; GFX6-NEXT:    s_addc_u32 s5, s5, 0
8754; GFX6-NEXT:    s_ashr_i32 s8, s7, 31
8755; GFX6-NEXT:    s_ashr_i64 s[4:5], s[4:5], 12
8756; GFX6-NEXT:    s_lshr_b32 s8, s8, 20
8757; GFX6-NEXT:    s_add_u32 s6, s6, s8
8758; GFX6-NEXT:    s_addc_u32 s7, s7, 0
8759; GFX6-NEXT:    s_ashr_i64 s[6:7], s[6:7], 12
8760; GFX6-NEXT:    v_mov_b32_e32 v0, s4
8761; GFX6-NEXT:    v_mov_b32_e32 v1, s5
8762; GFX6-NEXT:    v_mov_b32_e32 v2, s6
8763; GFX6-NEXT:    v_mov_b32_e32 v3, s7
8764; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
8765; GFX6-NEXT:    s_endpgm
8766;
8767; GFX9-LABEL: sdiv_v2i64_pow2k_denom:
8768; GFX9:       ; %bb.0:
8769; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
8770; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
8771; GFX9-NEXT:    v_mov_b32_e32 v4, 0
8772; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8773; GFX9-NEXT:    s_ashr_i32 s0, s5, 31
8774; GFX9-NEXT:    s_lshr_b32 s0, s0, 20
8775; GFX9-NEXT:    s_add_u32 s0, s4, s0
8776; GFX9-NEXT:    s_addc_u32 s1, s5, 0
8777; GFX9-NEXT:    s_ashr_i32 s4, s7, 31
8778; GFX9-NEXT:    s_ashr_i64 s[0:1], s[0:1], 12
8779; GFX9-NEXT:    s_lshr_b32 s4, s4, 20
8780; GFX9-NEXT:    s_add_u32 s4, s6, s4
8781; GFX9-NEXT:    s_addc_u32 s5, s7, 0
8782; GFX9-NEXT:    s_ashr_i64 s[4:5], s[4:5], 12
8783; GFX9-NEXT:    v_mov_b32_e32 v0, s0
8784; GFX9-NEXT:    v_mov_b32_e32 v1, s1
8785; GFX9-NEXT:    v_mov_b32_e32 v2, s4
8786; GFX9-NEXT:    v_mov_b32_e32 v3, s5
8787; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
8788; GFX9-NEXT:    s_endpgm
8789  %r = sdiv <2 x i64> %x, <i64 4096, i64 4096>
8790  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
8791  ret void
8792}
8793
8794define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
8795; CHECK-LABEL: @ssdiv_v2i64_mixed_pow2k_denom(
8796; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
8797; CHECK-NEXT:    [[TMP2:%.*]] = sdiv i64 [[TMP1]], 4096
8798; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
8799; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
8800; CHECK-NEXT:    [[TMP5:%.*]] = sdiv i64 [[TMP4]], 4095
8801; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
8802; CHECK-NEXT:    store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
8803; CHECK-NEXT:    ret void
8804;
8805; GFX6-LABEL: ssdiv_v2i64_mixed_pow2k_denom:
8806; GFX6:       ; %bb.0:
8807; GFX6-NEXT:    v_mov_b32_e32 v0, 0x457ff000
8808; GFX6-NEXT:    v_mov_b32_e32 v1, 0x4f800000
8809; GFX6-NEXT:    v_mac_f32_e32 v0, 0, v1
8810; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
8811; GFX6-NEXT:    s_movk_i32 s6, 0xf001
8812; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
8813; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
8814; GFX6-NEXT:    s_mov_b32 s7, 0xf000
8815; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
8816; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
8817; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
8818; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
8819; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
8820; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
8821; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
8822; GFX6-NEXT:    s_ashr_i32 s8, s1, 31
8823; GFX6-NEXT:    s_lshr_b32 s8, s8, 20
8824; GFX6-NEXT:    v_mul_hi_u32 v2, v0, s6
8825; GFX6-NEXT:    v_mul_lo_u32 v3, v1, s6
8826; GFX6-NEXT:    s_add_u32 s0, s0, s8
8827; GFX6-NEXT:    s_addc_u32 s1, s1, 0
8828; GFX6-NEXT:    s_ashr_i64 s[8:9], s[0:1], 12
8829; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
8830; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s6
8831; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
8832; GFX6-NEXT:    v_mul_lo_u32 v4, v0, v2
8833; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v3
8834; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
8835; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
8836; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
8837; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
8838; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
8839; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
8840; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
8841; GFX6-NEXT:    s_ashr_i32 s10, s3, 31
8842; GFX6-NEXT:    s_add_u32 s0, s2, s10
8843; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
8844; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
8845; GFX6-NEXT:    v_mov_b32_e32 v4, 0
8846; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
8847; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8848; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
8849; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
8850; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
8851; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s6
8852; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s6
8853; GFX6-NEXT:    s_mov_b32 s11, s10
8854; GFX6-NEXT:    s_addc_u32 s1, s3, s10
8855; GFX6-NEXT:    s_xor_b64 s[0:1], s[0:1], s[10:11]
8856; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8857; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s6
8858; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
8859; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v2
8860; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v3
8861; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v2
8862; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v3
8863; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
8864; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v2
8865; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
8866; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
8867; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
8868; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
8869; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v6, vcc
8870; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v5, v4, vcc
8871; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8872; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
8873; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
8874; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
8875; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v1
8876; GFX6-NEXT:    v_mul_hi_u32 v3, s0, v0
8877; GFX6-NEXT:    v_mul_hi_u32 v5, s0, v1
8878; GFX6-NEXT:    v_mul_hi_u32 v6, s1, v1
8879; GFX6-NEXT:    v_mul_lo_u32 v1, s1, v1
8880; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
8881; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
8882; GFX6-NEXT:    v_mul_lo_u32 v5, s1, v0
8883; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
8884; GFX6-NEXT:    s_movk_i32 s2, 0xfff
8885; GFX6-NEXT:    s_mov_b32 s6, -1
8886; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
8887; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
8888; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v6, v4, vcc
8889; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
8890; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
8891; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s2
8892; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s2
8893; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 2, v0
8894; GFX6-NEXT:    v_mul_lo_u32 v8, v0, s2
8895; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
8896; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v0
8897; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v1, vcc
8898; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
8899; GFX6-NEXT:    v_mov_b32_e32 v5, s1
8900; GFX6-NEXT:    v_sub_i32_e32 v8, vcc, s0, v8
8901; GFX6-NEXT:    v_subb_u32_e32 v4, vcc, v5, v4, vcc
8902; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s2, v8
8903; GFX6-NEXT:    v_subbrev_u32_e32 v9, vcc, 0, v4, vcc
8904; GFX6-NEXT:    s_movk_i32 s0, 0xffe
8905; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v5
8906; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
8907; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v9
8908; GFX6-NEXT:    v_cndmask_b32_e32 v5, -1, v5, vcc
8909; GFX6-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v8
8910; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
8911; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
8912; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v4
8913; GFX6-NEXT:    v_cndmask_b32_e64 v4, -1, v5, s[0:1]
8914; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
8915; GFX6-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
8916; GFX6-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
8917; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
8918; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
8919; GFX6-NEXT:    v_xor_b32_e32 v0, s10, v0
8920; GFX6-NEXT:    v_xor_b32_e32 v1, s10, v1
8921; GFX6-NEXT:    v_mov_b32_e32 v3, s10
8922; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s10, v0
8923; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v1, v3, vcc
8924; GFX6-NEXT:    v_mov_b32_e32 v0, s8
8925; GFX6-NEXT:    v_mov_b32_e32 v1, s9
8926; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
8927; GFX6-NEXT:    s_endpgm
8928;
8929; GFX9-LABEL: ssdiv_v2i64_mixed_pow2k_denom:
8930; GFX9:       ; %bb.0:
8931; GFX9-NEXT:    v_mov_b32_e32 v0, 0x457ff000
8932; GFX9-NEXT:    v_mov_b32_e32 v1, 0x4f800000
8933; GFX9-NEXT:    v_mac_f32_e32 v0, 0, v1
8934; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
8935; GFX9-NEXT:    s_movk_i32 s8, 0xf001
8936; GFX9-NEXT:    v_mov_b32_e32 v4, 0
8937; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
8938; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
8939; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
8940; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
8941; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
8942; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
8943; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
8944; GFX9-NEXT:    v_mul_hi_u32 v2, v0, s8
8945; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s8
8946; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s8
8947; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
8948; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
8949; GFX9-NEXT:    v_mul_lo_u32 v3, v0, v2
8950; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v5
8951; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
8952; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
8953; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
8954; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v6, v3
8955; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
8956; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v5
8957; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v5
8958; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
8959; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
8960; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v4, vcc
8961; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
8962; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
8963; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
8964; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
8965; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s8
8966; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s8
8967; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s8
8968; GFX9-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
8969; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
8970; GFX9-NEXT:    s_ashr_i32 s2, s5, 31
8971; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
8972; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
8973; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v2
8974; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v5
8975; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v2
8976; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v5
8977; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
8978; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v2
8979; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
8980; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
8981; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
8982; GFX9-NEXT:    s_lshr_b32 s2, s2, 20
8983; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
8984; GFX9-NEXT:    s_add_u32 s2, s4, s2
8985; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v6, vcc
8986; GFX9-NEXT:    s_addc_u32 s3, s5, 0
8987; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
8988; GFX9-NEXT:    s_ashr_i64 s[2:3], s[2:3], 12
8989; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v5, v2
8990; GFX9-NEXT:    s_ashr_i32 s4, s7, 31
8991; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
8992; GFX9-NEXT:    s_add_u32 s6, s6, s4
8993; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
8994; GFX9-NEXT:    s_mov_b32 s5, s4
8995; GFX9-NEXT:    s_addc_u32 s7, s7, s4
8996; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
8997; GFX9-NEXT:    s_xor_b64 s[6:7], s[6:7], s[4:5]
8998; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
8999; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
9000; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v1
9001; GFX9-NEXT:    v_mul_hi_u32 v6, s7, v1
9002; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
9003; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
9004; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
9005; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v0
9006; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
9007; GFX9-NEXT:    s_movk_i32 s0, 0xfff
9008; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v5
9009; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
9010; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v4, vcc
9011; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
9012; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
9013; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, 2, v0
9014; GFX9-NEXT:    v_mul_lo_u32 v5, v1, s0
9015; GFX9-NEXT:    v_mul_hi_u32 v6, v0, s0
9016; GFX9-NEXT:    v_mul_lo_u32 v9, v0, s0
9017; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
9018; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, 1, v0
9019; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v1, vcc
9020; GFX9-NEXT:    v_add_u32_e32 v5, v6, v5
9021; GFX9-NEXT:    v_mov_b32_e32 v6, s7
9022; GFX9-NEXT:    v_sub_co_u32_e32 v9, vcc, s6, v9
9023; GFX9-NEXT:    v_subb_co_u32_e32 v5, vcc, v6, v5, vcc
9024; GFX9-NEXT:    v_subrev_co_u32_e32 v6, vcc, s0, v9
9025; GFX9-NEXT:    v_subbrev_co_u32_e32 v10, vcc, 0, v5, vcc
9026; GFX9-NEXT:    s_movk_i32 s0, 0xffe
9027; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v6
9028; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
9029; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v10
9030; GFX9-NEXT:    v_cndmask_b32_e32 v6, -1, v6, vcc
9031; GFX9-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v9
9032; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
9033; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
9034; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v5
9035; GFX9-NEXT:    v_cndmask_b32_e64 v5, -1, v6, s[0:1]
9036; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
9037; GFX9-NEXT:    v_cndmask_b32_e32 v2, v7, v2, vcc
9038; GFX9-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
9039; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
9040; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
9041; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v0
9042; GFX9-NEXT:    v_xor_b32_e32 v1, s4, v1
9043; GFX9-NEXT:    v_mov_b32_e32 v3, s4
9044; GFX9-NEXT:    v_subrev_co_u32_e32 v2, vcc, s4, v0
9045; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v1, v3, vcc
9046; GFX9-NEXT:    v_mov_b32_e32 v0, s2
9047; GFX9-NEXT:    v_mov_b32_e32 v1, s3
9048; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[8:9]
9049; GFX9-NEXT:    s_endpgm
9050  %r = sdiv <2 x i64> %x, <i64 4096, i64 4095>
9051  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
9052  ret void
9053}
9054
9055define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
9056; CHECK-LABEL: @sdiv_v2i64_pow2_shl_denom(
9057; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.*]]
9058; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
9059; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 0
9060; CHECK-NEXT:    [[TMP3:%.*]] = sdiv i64 [[TMP1]], [[TMP2]]
9061; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i64 0
9062; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 1
9063; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
9064; CHECK-NEXT:    [[TMP7:%.*]] = sdiv i64 [[TMP5]], [[TMP6]]
9065; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
9066; CHECK-NEXT:    store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
9067; CHECK-NEXT:    ret void
9068;
9069; GFX6-LABEL: sdiv_v2i64_pow2_shl_denom:
9070; GFX6:       ; %bb.0:
9071; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
9072; GFX6-NEXT:    s_mov_b64 s[12:13], 0x1000
9073; GFX6-NEXT:    s_mov_b32 s18, 0x4f800000
9074; GFX6-NEXT:    s_mov_b32 s19, 0x5f7ffffc
9075; GFX6-NEXT:    s_mov_b32 s20, 0x2f800000
9076; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
9077; GFX6-NEXT:    s_lshl_b64 s[8:9], s[12:13], s8
9078; GFX6-NEXT:    s_lshl_b64 s[2:3], s[12:13], s10
9079; GFX6-NEXT:    s_ashr_i32 s14, s9, 31
9080; GFX6-NEXT:    s_add_u32 s8, s8, s14
9081; GFX6-NEXT:    s_mov_b32 s15, s14
9082; GFX6-NEXT:    s_addc_u32 s9, s9, s14
9083; GFX6-NEXT:    s_xor_b64 s[12:13], s[8:9], s[14:15]
9084; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s12
9085; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s13
9086; GFX6-NEXT:    s_mov_b32 s21, 0xcf800000
9087; GFX6-NEXT:    s_sub_u32 s10, 0, s12
9088; GFX6-NEXT:    s_subb_u32 s11, 0, s13
9089; GFX6-NEXT:    v_mac_f32_e32 v0, s18, v1
9090; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
9091; GFX6-NEXT:    s_ashr_i32 s16, s5, 31
9092; GFX6-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x9
9093; GFX6-NEXT:    s_add_u32 s0, s4, s16
9094; GFX6-NEXT:    v_mul_f32_e32 v0, s19, v0
9095; GFX6-NEXT:    v_mul_f32_e32 v1, s20, v0
9096; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
9097; GFX6-NEXT:    v_mac_f32_e32 v0, s21, v1
9098; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
9099; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v0
9100; GFX6-NEXT:    s_mov_b32 s17, s16
9101; GFX6-NEXT:    s_addc_u32 s1, s5, s16
9102; GFX6-NEXT:    v_mul_lo_u32 v0, s10, v1
9103; GFX6-NEXT:    v_mul_hi_u32 v3, s10, v2
9104; GFX6-NEXT:    v_mul_lo_u32 v4, s11, v2
9105; GFX6-NEXT:    v_mul_lo_u32 v5, s10, v2
9106; GFX6-NEXT:    s_xor_b64 s[4:5], s[0:1], s[16:17]
9107; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
9108; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v0, v4
9109; GFX6-NEXT:    v_mul_lo_u32 v0, v2, v3
9110; GFX6-NEXT:    v_mul_hi_u32 v4, v2, v5
9111; GFX6-NEXT:    v_mul_hi_u32 v6, v2, v3
9112; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v3
9113; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
9114; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v4, v0
9115; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v6, vcc
9116; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v5
9117; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v5
9118; GFX6-NEXT:    s_xor_b64 s[14:15], s[16:17], s[14:15]
9119; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
9120; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v4, v5, vcc
9121; GFX6-NEXT:    v_mov_b32_e32 v0, 0
9122; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v0, vcc
9123; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
9124; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
9125; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
9126; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
9127; GFX6-NEXT:    v_mul_lo_u32 v3, s10, v1
9128; GFX6-NEXT:    v_mul_hi_u32 v4, s10, v2
9129; GFX6-NEXT:    v_mul_lo_u32 v5, s11, v2
9130; GFX6-NEXT:    s_mov_b32 s11, 0xf000
9131; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
9132; GFX6-NEXT:    v_mul_lo_u32 v4, s10, v2
9133; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
9134; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v3
9135; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v4
9136; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v3
9137; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v4
9138; GFX6-NEXT:    v_mul_lo_u32 v4, v1, v4
9139; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v3
9140; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
9141; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
9142; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
9143; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
9144; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
9145; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v5, v0, vcc
9146; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
9147; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
9148; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
9149; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
9150; GFX6-NEXT:    v_mul_lo_u32 v3, s4, v1
9151; GFX6-NEXT:    v_mul_hi_u32 v4, s4, v2
9152; GFX6-NEXT:    v_mul_hi_u32 v5, s4, v1
9153; GFX6-NEXT:    v_mul_hi_u32 v6, s5, v1
9154; GFX6-NEXT:    v_mul_lo_u32 v1, s5, v1
9155; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
9156; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
9157; GFX6-NEXT:    v_mul_lo_u32 v5, s5, v2
9158; GFX6-NEXT:    v_mul_hi_u32 v2, s5, v2
9159; GFX6-NEXT:    s_mov_b32 s10, -1
9160; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
9161; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v4, v2, vcc
9162; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v0, vcc
9163; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
9164; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
9165; GFX6-NEXT:    v_mul_lo_u32 v3, s12, v2
9166; GFX6-NEXT:    v_mul_hi_u32 v4, s12, v1
9167; GFX6-NEXT:    v_mul_lo_u32 v5, s13, v1
9168; GFX6-NEXT:    v_mov_b32_e32 v6, s13
9169; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
9170; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v1
9171; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
9172; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s5, v3
9173; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s4, v4
9174; GFX6-NEXT:    v_subb_u32_e64 v5, s[0:1], v5, v6, vcc
9175; GFX6-NEXT:    v_subrev_i32_e64 v6, s[0:1], s12, v4
9176; GFX6-NEXT:    v_subbrev_u32_e64 v5, s[0:1], 0, v5, s[0:1]
9177; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s13, v5
9178; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
9179; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s12, v6
9180; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
9181; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s13, v5
9182; GFX6-NEXT:    v_cndmask_b32_e64 v5, v7, v6, s[0:1]
9183; GFX6-NEXT:    v_add_i32_e64 v6, s[0:1], 2, v1
9184; GFX6-NEXT:    v_addc_u32_e64 v7, s[0:1], 0, v2, s[0:1]
9185; GFX6-NEXT:    v_add_i32_e64 v8, s[0:1], 1, v1
9186; GFX6-NEXT:    v_addc_u32_e64 v9, s[0:1], 0, v2, s[0:1]
9187; GFX6-NEXT:    s_ashr_i32 s4, s3, 31
9188; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
9189; GFX6-NEXT:    s_add_u32 s2, s2, s4
9190; GFX6-NEXT:    v_cndmask_b32_e64 v5, v9, v7, s[0:1]
9191; GFX6-NEXT:    v_mov_b32_e32 v7, s5
9192; GFX6-NEXT:    s_mov_b32 s5, s4
9193; GFX6-NEXT:    s_addc_u32 s3, s3, s4
9194; GFX6-NEXT:    s_xor_b64 s[2:3], s[2:3], s[4:5]
9195; GFX6-NEXT:    v_cvt_f32_u32_e32 v9, s2
9196; GFX6-NEXT:    v_cvt_f32_u32_e32 v10, s3
9197; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v7, v3, vcc
9198; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s13, v3
9199; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
9200; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v4
9201; GFX6-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
9202; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v3
9203; GFX6-NEXT:    v_mac_f32_e32 v9, s18, v10
9204; GFX6-NEXT:    v_cndmask_b32_e32 v3, v7, v4, vcc
9205; GFX6-NEXT:    v_rcp_f32_e32 v4, v9
9206; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
9207; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
9208; GFX6-NEXT:    v_cndmask_b32_e64 v3, v8, v6, s[0:1]
9209; GFX6-NEXT:    v_mul_f32_e32 v4, s19, v4
9210; GFX6-NEXT:    v_mul_f32_e32 v5, s20, v4
9211; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
9212; GFX6-NEXT:    v_mac_f32_e32 v4, s21, v5
9213; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
9214; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v5
9215; GFX6-NEXT:    s_sub_u32 s0, 0, s2
9216; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
9217; GFX6-NEXT:    v_mul_hi_u32 v3, s0, v4
9218; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v5
9219; GFX6-NEXT:    s_subb_u32 s1, 0, s3
9220; GFX6-NEXT:    v_mul_lo_u32 v7, s1, v4
9221; GFX6-NEXT:    s_ashr_i32 s12, s7, 31
9222; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
9223; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v4
9224; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
9225; GFX6-NEXT:    v_mul_lo_u32 v7, v4, v3
9226; GFX6-NEXT:    v_mul_hi_u32 v8, v4, v6
9227; GFX6-NEXT:    v_mul_hi_u32 v9, v4, v3
9228; GFX6-NEXT:    v_mul_hi_u32 v10, v5, v3
9229; GFX6-NEXT:    v_mul_lo_u32 v3, v5, v3
9230; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
9231; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
9232; GFX6-NEXT:    v_mul_lo_u32 v9, v5, v6
9233; GFX6-NEXT:    v_mul_hi_u32 v6, v5, v6
9234; GFX6-NEXT:    s_mov_b32 s13, s12
9235; GFX6-NEXT:    v_xor_b32_e32 v1, s14, v1
9236; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
9237; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v8, v6, vcc
9238; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v10, v0, vcc
9239; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
9240; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
9241; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
9242; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v5, v6, vcc
9243; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v4
9244; GFX6-NEXT:    v_mul_hi_u32 v6, s0, v3
9245; GFX6-NEXT:    v_mul_lo_u32 v7, s1, v3
9246; GFX6-NEXT:    v_xor_b32_e32 v2, s15, v2
9247; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
9248; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v3
9249; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
9250; GFX6-NEXT:    v_mul_lo_u32 v9, v3, v5
9251; GFX6-NEXT:    v_mul_hi_u32 v10, v3, v6
9252; GFX6-NEXT:    v_mul_hi_u32 v11, v3, v5
9253; GFX6-NEXT:    v_mul_hi_u32 v8, v4, v6
9254; GFX6-NEXT:    v_mul_lo_u32 v6, v4, v6
9255; GFX6-NEXT:    v_mul_hi_u32 v7, v4, v5
9256; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
9257; GFX6-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
9258; GFX6-NEXT:    v_mul_lo_u32 v5, v4, v5
9259; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
9260; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v10, v8, vcc
9261; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v7, v0, vcc
9262; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
9263; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
9264; GFX6-NEXT:    s_add_u32 s0, s6, s12
9265; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
9266; GFX6-NEXT:    s_addc_u32 s1, s7, s12
9267; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
9268; GFX6-NEXT:    s_xor_b64 s[6:7], s[0:1], s[12:13]
9269; GFX6-NEXT:    v_mul_lo_u32 v5, s6, v4
9270; GFX6-NEXT:    v_mul_hi_u32 v6, s6, v3
9271; GFX6-NEXT:    v_mul_hi_u32 v8, s6, v4
9272; GFX6-NEXT:    v_mul_hi_u32 v9, s7, v4
9273; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v4
9274; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
9275; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
9276; GFX6-NEXT:    v_mul_lo_u32 v8, s7, v3
9277; GFX6-NEXT:    v_mul_hi_u32 v3, s7, v3
9278; GFX6-NEXT:    v_mov_b32_e32 v7, s15
9279; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
9280; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v3, vcc
9281; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v9, v0, vcc
9282; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
9283; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v0, vcc
9284; GFX6-NEXT:    v_mul_lo_u32 v5, s2, v4
9285; GFX6-NEXT:    v_mul_hi_u32 v6, s2, v3
9286; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s14, v1
9287; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v2, v7, vcc
9288; GFX6-NEXT:    v_mul_lo_u32 v2, s3, v3
9289; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
9290; GFX6-NEXT:    v_mov_b32_e32 v7, s3
9291; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
9292; GFX6-NEXT:    v_mul_lo_u32 v5, s2, v3
9293; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, s7, v2
9294; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s6, v5
9295; GFX6-NEXT:    v_subb_u32_e64 v6, s[0:1], v6, v7, vcc
9296; GFX6-NEXT:    v_subrev_i32_e64 v7, s[0:1], s2, v5
9297; GFX6-NEXT:    v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1]
9298; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v6
9299; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[0:1]
9300; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v7
9301; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
9302; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v6
9303; GFX6-NEXT:    v_cndmask_b32_e64 v6, v8, v7, s[0:1]
9304; GFX6-NEXT:    v_add_i32_e64 v7, s[0:1], 2, v3
9305; GFX6-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v4, s[0:1]
9306; GFX6-NEXT:    v_add_i32_e64 v9, s[0:1], 1, v3
9307; GFX6-NEXT:    v_addc_u32_e64 v10, s[0:1], 0, v4, s[0:1]
9308; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
9309; GFX6-NEXT:    v_cndmask_b32_e64 v6, v10, v8, s[0:1]
9310; GFX6-NEXT:    v_mov_b32_e32 v8, s7
9311; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v8, v2, vcc
9312; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2
9313; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
9314; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s2, v5
9315; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
9316; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v2
9317; GFX6-NEXT:    v_cndmask_b32_e32 v2, v8, v5, vcc
9318; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
9319; GFX6-NEXT:    v_cndmask_b32_e32 v2, v4, v6, vcc
9320; GFX6-NEXT:    v_cndmask_b32_e64 v4, v9, v7, s[0:1]
9321; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
9322; GFX6-NEXT:    s_xor_b64 s[0:1], s[12:13], s[4:5]
9323; GFX6-NEXT:    v_xor_b32_e32 v3, s0, v3
9324; GFX6-NEXT:    v_xor_b32_e32 v4, s1, v2
9325; GFX6-NEXT:    v_mov_b32_e32 v5, s1
9326; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s0, v3
9327; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v4, v5, vcc
9328; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
9329; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
9330; GFX6-NEXT:    s_endpgm
9331;
9332; GFX9-LABEL: sdiv_v2i64_pow2_shl_denom:
9333; GFX9:       ; %bb.0:
9334; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
9335; GFX9-NEXT:    s_mov_b64 s[2:3], 0x1000
9336; GFX9-NEXT:    s_mov_b32 s16, 0x4f800000
9337; GFX9-NEXT:    s_mov_b32 s17, 0x5f7ffffc
9338; GFX9-NEXT:    s_mov_b32 s18, 0x2f800000
9339; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
9340; GFX9-NEXT:    s_lshl_b64 s[10:11], s[2:3], s10
9341; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s8
9342; GFX9-NEXT:    s_ashr_i32 s12, s3, 31
9343; GFX9-NEXT:    s_add_u32 s2, s2, s12
9344; GFX9-NEXT:    s_mov_b32 s13, s12
9345; GFX9-NEXT:    s_addc_u32 s3, s3, s12
9346; GFX9-NEXT:    s_xor_b64 s[8:9], s[2:3], s[12:13]
9347; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
9348; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
9349; GFX9-NEXT:    s_mov_b32 s19, 0xcf800000
9350; GFX9-NEXT:    s_sub_u32 s2, 0, s8
9351; GFX9-NEXT:    s_subb_u32 s3, 0, s9
9352; GFX9-NEXT:    v_mac_f32_e32 v0, s16, v1
9353; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
9354; GFX9-NEXT:    s_ashr_i32 s14, s5, 31
9355; GFX9-NEXT:    s_mov_b32 s15, s14
9356; GFX9-NEXT:    v_mul_f32_e32 v0, s17, v0
9357; GFX9-NEXT:    v_mul_f32_e32 v1, s18, v0
9358; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
9359; GFX9-NEXT:    v_mac_f32_e32 v0, s19, v1
9360; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
9361; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v0
9362; GFX9-NEXT:    v_mul_lo_u32 v0, s2, v1
9363; GFX9-NEXT:    v_mul_hi_u32 v3, s2, v2
9364; GFX9-NEXT:    v_mul_lo_u32 v5, s3, v2
9365; GFX9-NEXT:    v_mul_lo_u32 v4, s2, v2
9366; GFX9-NEXT:    v_add_u32_e32 v0, v3, v0
9367; GFX9-NEXT:    v_add_u32_e32 v5, v0, v5
9368; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v4
9369; GFX9-NEXT:    v_mul_lo_u32 v6, v2, v5
9370; GFX9-NEXT:    v_mul_hi_u32 v7, v2, v5
9371; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v5
9372; GFX9-NEXT:    v_mov_b32_e32 v0, 0
9373; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
9374; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
9375; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
9376; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
9377; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
9378; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
9379; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v5
9380; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v0, vcc
9381; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v4
9382; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
9383; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
9384; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
9385; GFX9-NEXT:    v_mul_lo_u32 v3, s2, v1
9386; GFX9-NEXT:    v_mul_hi_u32 v4, s2, v2
9387; GFX9-NEXT:    v_mul_lo_u32 v5, s3, v2
9388; GFX9-NEXT:    v_mul_lo_u32 v6, s2, v2
9389; GFX9-NEXT:    s_add_u32 s2, s4, s14
9390; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
9391; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
9392; GFX9-NEXT:    v_mul_lo_u32 v7, v2, v3
9393; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v6
9394; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v3
9395; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v6
9396; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
9397; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v3
9398; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
9399; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
9400; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
9401; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
9402; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v5, vcc
9403; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v0, vcc
9404; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
9405; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
9406; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
9407; GFX9-NEXT:    s_addc_u32 s3, s5, s14
9408; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
9409; GFX9-NEXT:    s_xor_b64 s[4:5], s[2:3], s[14:15]
9410; GFX9-NEXT:    v_mul_lo_u32 v3, s4, v1
9411; GFX9-NEXT:    v_mul_hi_u32 v4, s4, v2
9412; GFX9-NEXT:    v_mul_hi_u32 v5, s4, v1
9413; GFX9-NEXT:    v_mul_hi_u32 v6, s5, v1
9414; GFX9-NEXT:    v_mul_lo_u32 v1, s5, v1
9415; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
9416; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
9417; GFX9-NEXT:    v_mul_lo_u32 v5, s5, v2
9418; GFX9-NEXT:    v_mul_hi_u32 v2, s5, v2
9419; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
9420; GFX9-NEXT:    s_xor_b64 s[12:13], s[14:15], s[12:13]
9421; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
9422; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v4, v2, vcc
9423; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v0, vcc
9424; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v2, v1
9425; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v3, vcc
9426; GFX9-NEXT:    v_mul_lo_u32 v3, s8, v2
9427; GFX9-NEXT:    v_mul_hi_u32 v4, s8, v1
9428; GFX9-NEXT:    v_mul_lo_u32 v5, s9, v1
9429; GFX9-NEXT:    v_mov_b32_e32 v6, s9
9430; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
9431; GFX9-NEXT:    v_mul_lo_u32 v4, s8, v1
9432; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
9433; GFX9-NEXT:    v_sub_u32_e32 v5, s5, v3
9434; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, s4, v4
9435; GFX9-NEXT:    v_subb_co_u32_e64 v5, s[0:1], v5, v6, vcc
9436; GFX9-NEXT:    v_subrev_co_u32_e64 v6, s[0:1], s8, v4
9437; GFX9-NEXT:    v_subbrev_co_u32_e64 v5, s[0:1], 0, v5, s[0:1]
9438; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v5
9439; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
9440; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v6
9441; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
9442; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v5
9443; GFX9-NEXT:    v_cndmask_b32_e64 v5, v7, v6, s[0:1]
9444; GFX9-NEXT:    v_add_co_u32_e64 v6, s[0:1], 2, v1
9445; GFX9-NEXT:    v_addc_co_u32_e64 v7, s[0:1], 0, v2, s[0:1]
9446; GFX9-NEXT:    v_add_co_u32_e64 v8, s[0:1], 1, v1
9447; GFX9-NEXT:    v_addc_co_u32_e64 v9, s[0:1], 0, v2, s[0:1]
9448; GFX9-NEXT:    s_ashr_i32 s4, s11, 31
9449; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
9450; GFX9-NEXT:    s_add_u32 s10, s10, s4
9451; GFX9-NEXT:    v_cndmask_b32_e64 v5, v9, v7, s[0:1]
9452; GFX9-NEXT:    v_mov_b32_e32 v7, s5
9453; GFX9-NEXT:    s_mov_b32 s5, s4
9454; GFX9-NEXT:    s_addc_u32 s11, s11, s4
9455; GFX9-NEXT:    s_xor_b64 s[10:11], s[10:11], s[4:5]
9456; GFX9-NEXT:    v_cvt_f32_u32_e32 v9, s10
9457; GFX9-NEXT:    v_cvt_f32_u32_e32 v10, s11
9458; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v7, v3, vcc
9459; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
9460; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
9461; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v4
9462; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
9463; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v3
9464; GFX9-NEXT:    v_mac_f32_e32 v9, s16, v10
9465; GFX9-NEXT:    v_cndmask_b32_e32 v3, v7, v4, vcc
9466; GFX9-NEXT:    v_rcp_f32_e32 v4, v9
9467; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
9468; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
9469; GFX9-NEXT:    v_cndmask_b32_e64 v3, v8, v6, s[0:1]
9470; GFX9-NEXT:    v_mul_f32_e32 v4, s17, v4
9471; GFX9-NEXT:    v_mul_f32_e32 v5, s18, v4
9472; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
9473; GFX9-NEXT:    v_mac_f32_e32 v4, s19, v5
9474; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
9475; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
9476; GFX9-NEXT:    s_sub_u32 s0, 0, s10
9477; GFX9-NEXT:    s_subb_u32 s1, 0, s11
9478; GFX9-NEXT:    v_mul_hi_u32 v6, s0, v4
9479; GFX9-NEXT:    v_mul_lo_u32 v7, s0, v5
9480; GFX9-NEXT:    v_mul_lo_u32 v8, s1, v4
9481; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
9482; GFX9-NEXT:    v_mul_lo_u32 v3, s0, v4
9483; GFX9-NEXT:    v_add_u32_e32 v6, v6, v7
9484; GFX9-NEXT:    v_add_u32_e32 v6, v6, v8
9485; GFX9-NEXT:    v_mul_lo_u32 v7, v4, v6
9486; GFX9-NEXT:    v_mul_hi_u32 v8, v4, v3
9487; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v6
9488; GFX9-NEXT:    v_mul_hi_u32 v10, v5, v6
9489; GFX9-NEXT:    v_mul_lo_u32 v6, v5, v6
9490; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
9491; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
9492; GFX9-NEXT:    v_mul_lo_u32 v9, v5, v3
9493; GFX9-NEXT:    v_mul_hi_u32 v3, v5, v3
9494; GFX9-NEXT:    s_ashr_i32 s8, s7, 31
9495; GFX9-NEXT:    s_mov_b32 s9, s8
9496; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v9
9497; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v8, v3, vcc
9498; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v10, v0, vcc
9499; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
9500; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
9501; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
9502; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v6, vcc
9503; GFX9-NEXT:    v_mul_lo_u32 v5, s0, v4
9504; GFX9-NEXT:    v_mul_hi_u32 v6, s0, v3
9505; GFX9-NEXT:    v_mul_lo_u32 v7, s1, v3
9506; GFX9-NEXT:    v_mul_lo_u32 v8, s0, v3
9507; GFX9-NEXT:    s_add_u32 s0, s6, s8
9508; GFX9-NEXT:    v_add_u32_e32 v5, v6, v5
9509; GFX9-NEXT:    v_add_u32_e32 v5, v5, v7
9510; GFX9-NEXT:    v_mul_lo_u32 v9, v3, v5
9511; GFX9-NEXT:    v_mul_hi_u32 v10, v3, v8
9512; GFX9-NEXT:    v_mul_hi_u32 v11, v3, v5
9513; GFX9-NEXT:    v_mul_hi_u32 v7, v4, v8
9514; GFX9-NEXT:    v_mul_lo_u32 v8, v4, v8
9515; GFX9-NEXT:    v_mul_hi_u32 v6, v4, v5
9516; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
9517; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
9518; GFX9-NEXT:    v_mul_lo_u32 v5, v4, v5
9519; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
9520; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v10, v7, vcc
9521; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v6, v0, vcc
9522; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
9523; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
9524; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
9525; GFX9-NEXT:    s_addc_u32 s1, s7, s8
9526; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v6, vcc
9527; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[8:9]
9528; GFX9-NEXT:    v_mul_lo_u32 v5, s6, v4
9529; GFX9-NEXT:    v_mul_hi_u32 v6, s6, v3
9530; GFX9-NEXT:    v_mul_hi_u32 v8, s6, v4
9531; GFX9-NEXT:    v_mul_hi_u32 v9, s7, v4
9532; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v4
9533; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v6, v5
9534; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
9535; GFX9-NEXT:    v_mul_lo_u32 v8, s7, v3
9536; GFX9-NEXT:    v_mul_hi_u32 v3, s7, v3
9537; GFX9-NEXT:    v_xor_b32_e32 v1, s12, v1
9538; GFX9-NEXT:    v_xor_b32_e32 v2, s13, v2
9539; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v8
9540; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
9541; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v0, vcc
9542; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v4
9543; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
9544; GFX9-NEXT:    v_mul_lo_u32 v5, s10, v4
9545; GFX9-NEXT:    v_mul_hi_u32 v6, s10, v3
9546; GFX9-NEXT:    v_mul_lo_u32 v8, s11, v3
9547; GFX9-NEXT:    v_mov_b32_e32 v7, s13
9548; GFX9-NEXT:    v_subrev_co_u32_e32 v1, vcc, s12, v1
9549; GFX9-NEXT:    v_add_u32_e32 v5, v6, v5
9550; GFX9-NEXT:    v_mul_lo_u32 v6, s10, v3
9551; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v2, v7, vcc
9552; GFX9-NEXT:    v_add_u32_e32 v5, v5, v8
9553; GFX9-NEXT:    v_sub_u32_e32 v7, s7, v5
9554; GFX9-NEXT:    v_mov_b32_e32 v8, s11
9555; GFX9-NEXT:    v_sub_co_u32_e32 v6, vcc, s6, v6
9556; GFX9-NEXT:    v_subb_co_u32_e64 v7, s[0:1], v7, v8, vcc
9557; GFX9-NEXT:    v_subrev_co_u32_e64 v8, s[0:1], s10, v6
9558; GFX9-NEXT:    v_subbrev_co_u32_e64 v7, s[0:1], 0, v7, s[0:1]
9559; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v7
9560; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[0:1]
9561; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v8
9562; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[0:1]
9563; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v7
9564; GFX9-NEXT:    v_cndmask_b32_e64 v7, v9, v8, s[0:1]
9565; GFX9-NEXT:    v_add_co_u32_e64 v8, s[0:1], 2, v3
9566; GFX9-NEXT:    v_addc_co_u32_e64 v9, s[0:1], 0, v4, s[0:1]
9567; GFX9-NEXT:    v_add_co_u32_e64 v10, s[0:1], 1, v3
9568; GFX9-NEXT:    v_addc_co_u32_e64 v11, s[0:1], 0, v4, s[0:1]
9569; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v7
9570; GFX9-NEXT:    v_cndmask_b32_e64 v7, v11, v9, s[0:1]
9571; GFX9-NEXT:    v_mov_b32_e32 v9, s7
9572; GFX9-NEXT:    v_subb_co_u32_e32 v5, vcc, v9, v5, vcc
9573; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v5
9574; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
9575; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v6
9576; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
9577; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v5
9578; GFX9-NEXT:    v_cndmask_b32_e32 v5, v9, v6, vcc
9579; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
9580; GFX9-NEXT:    v_cndmask_b32_e64 v5, v10, v8, s[0:1]
9581; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
9582; GFX9-NEXT:    s_xor_b64 s[0:1], s[8:9], s[4:5]
9583; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v7, vcc
9584; GFX9-NEXT:    v_xor_b32_e32 v3, s0, v3
9585; GFX9-NEXT:    v_xor_b32_e32 v4, s1, v4
9586; GFX9-NEXT:    v_mov_b32_e32 v5, s1
9587; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s0, v3
9588; GFX9-NEXT:    v_subb_co_u32_e32 v4, vcc, v4, v5, vcc
9589; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
9590; GFX9-NEXT:    global_store_dwordx4 v0, v[1:4], s[2:3]
9591; GFX9-NEXT:    s_endpgm
9592  %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
9593  %r = sdiv <2 x i64> %x, %shl.y
9594  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
9595  ret void
9596}
9597
9598define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
9599; CHECK-LABEL: @srem_i64_oddk_denom(
9600; CHECK-NEXT:    [[R:%.*]] = srem i64 [[X:%.*]], 1235195
9601; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
9602; CHECK-NEXT:    ret void
9603;
9604; GFX6-LABEL: srem_i64_oddk_denom:
9605; GFX6:       ; %bb.0:
9606; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f800000
9607; GFX6-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
9608; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
9609; GFX6-NEXT:    s_mov_b32 s4, 0xffed2705
9610; GFX6-NEXT:    v_mov_b32_e32 v5, 0
9611; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
9612; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
9613; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
9614; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
9615; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
9616; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
9617; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
9618; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
9619; GFX6-NEXT:    s_ashr_i32 s8, s3, 31
9620; GFX6-NEXT:    s_add_u32 s2, s2, s8
9621; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s4
9622; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s4
9623; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s4
9624; GFX6-NEXT:    s_mov_b32 s9, s8
9625; GFX6-NEXT:    s_addc_u32 s3, s3, s8
9626; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9627; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
9628; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
9629; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v2
9630; GFX6-NEXT:    v_mul_hi_u32 v7, v0, v2
9631; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
9632; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
9633; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
9634; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
9635; GFX6-NEXT:    v_mul_lo_u32 v7, v1, v4
9636; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
9637; GFX6-NEXT:    s_xor_b64 s[2:3], s[2:3], s[8:9]
9638; GFX6-NEXT:    s_mov_b32 s5, s1
9639; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
9640; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v4, vcc
9641; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v5, vcc
9642; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9643; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
9644; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
9645; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
9646; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s4
9647; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s4
9648; GFX6-NEXT:    s_mov_b32 s7, 0xf000
9649; GFX6-NEXT:    s_mov_b32 s6, -1
9650; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9651; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s4
9652; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
9653; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v2
9654; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v3
9655; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v2
9656; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v3
9657; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
9658; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v2
9659; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
9660; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
9661; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
9662; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
9663; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v6, vcc
9664; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v4, v5, vcc
9665; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9666; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
9667; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
9668; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
9669; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
9670; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
9671; GFX6-NEXT:    v_mul_hi_u32 v4, s2, v1
9672; GFX6-NEXT:    v_mul_hi_u32 v6, s3, v1
9673; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v1
9674; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9675; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
9676; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v0
9677; GFX6-NEXT:    v_mul_hi_u32 v0, s3, v0
9678; GFX6-NEXT:    s_mov_b32 s4, s0
9679; GFX6-NEXT:    s_mov_b32 s0, 0x12d8fb
9680; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
9681; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
9682; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v6, v5, vcc
9683; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
9684; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
9685; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s0
9686; GFX6-NEXT:    v_mul_hi_u32 v2, v0, s0
9687; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s0
9688; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
9689; GFX6-NEXT:    v_mov_b32_e32 v2, s3
9690; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
9691; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
9692; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s0, v0
9693; GFX6-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v1, vcc
9694; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s0, v2
9695; GFX6-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v3, vcc
9696; GFX6-NEXT:    s_mov_b32 s0, 0x12d8fa
9697; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v2
9698; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
9699; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
9700; GFX6-NEXT:    v_cndmask_b32_e32 v6, -1, v6, vcc
9701; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
9702; GFX6-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v0
9703; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
9704; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
9705; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
9706; GFX6-NEXT:    v_cndmask_b32_e64 v5, -1, v5, s[0:1]
9707; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
9708; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
9709; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
9710; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
9711; GFX6-NEXT:    v_xor_b32_e32 v0, s8, v0
9712; GFX6-NEXT:    v_xor_b32_e32 v1, s8, v1
9713; GFX6-NEXT:    v_mov_b32_e32 v2, s8
9714; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v0
9715; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
9716; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
9717; GFX6-NEXT:    s_endpgm
9718;
9719; GFX9-LABEL: srem_i64_oddk_denom:
9720; GFX9:       ; %bb.0:
9721; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f800000
9722; GFX9-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
9723; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
9724; GFX9-NEXT:    s_mov_b32 s2, 0xffed2705
9725; GFX9-NEXT:    v_mov_b32_e32 v5, 0
9726; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
9727; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
9728; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
9729; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
9730; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
9731; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
9732; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
9733; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s2
9734; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s2
9735; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s2
9736; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
9737; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
9738; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
9739; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
9740; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
9741; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
9742; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
9743; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
9744; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
9745; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
9746; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
9747; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
9748; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
9749; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
9750; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
9751; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
9752; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
9753; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
9754; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s2
9755; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s2
9756; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s2
9757; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
9758; GFX9-NEXT:    s_ashr_i32 s2, s7, 31
9759; GFX9-NEXT:    s_add_u32 s0, s6, s2
9760; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
9761; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
9762; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v2
9763; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v4
9764; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v2
9765; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v4
9766; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v4
9767; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v2
9768; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
9769; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
9770; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
9771; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v7, v4
9772; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
9773; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v5, vcc
9774; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
9775; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
9776; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
9777; GFX9-NEXT:    s_mov_b32 s3, s2
9778; GFX9-NEXT:    s_addc_u32 s1, s7, s2
9779; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
9780; GFX9-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
9781; GFX9-NEXT:    v_mul_lo_u32 v2, s0, v1
9782; GFX9-NEXT:    v_mul_hi_u32 v3, s0, v0
9783; GFX9-NEXT:    v_mul_hi_u32 v4, s0, v1
9784; GFX9-NEXT:    v_mul_hi_u32 v6, s1, v1
9785; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v1
9786; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
9787; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
9788; GFX9-NEXT:    v_mul_lo_u32 v4, s1, v0
9789; GFX9-NEXT:    v_mul_hi_u32 v0, s1, v0
9790; GFX9-NEXT:    s_mov_b32 s3, 0x12d8fb
9791; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
9792; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
9793; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
9794; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
9795; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
9796; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s3
9797; GFX9-NEXT:    v_mul_hi_u32 v2, v0, s3
9798; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
9799; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
9800; GFX9-NEXT:    v_mov_b32_e32 v2, s1
9801; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, s0, v0
9802; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v2, v1, vcc
9803; GFX9-NEXT:    v_subrev_co_u32_e32 v2, vcc, s3, v0
9804; GFX9-NEXT:    v_subbrev_co_u32_e32 v3, vcc, 0, v1, vcc
9805; GFX9-NEXT:    v_subrev_co_u32_e32 v4, vcc, s3, v2
9806; GFX9-NEXT:    v_subbrev_co_u32_e32 v6, vcc, 0, v3, vcc
9807; GFX9-NEXT:    s_mov_b32 s0, 0x12d8fa
9808; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v2
9809; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
9810; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
9811; GFX9-NEXT:    v_cndmask_b32_e32 v7, -1, v7, vcc
9812; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
9813; GFX9-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v0
9814; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
9815; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
9816; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
9817; GFX9-NEXT:    v_cndmask_b32_e64 v6, -1, v6, s[0:1]
9818; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
9819; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
9820; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
9821; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
9822; GFX9-NEXT:    v_xor_b32_e32 v0, s2, v0
9823; GFX9-NEXT:    v_xor_b32_e32 v1, s2, v1
9824; GFX9-NEXT:    v_mov_b32_e32 v2, s2
9825; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s2, v0
9826; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
9827; GFX9-NEXT:    global_store_dwordx2 v5, v[0:1], s[4:5]
9828; GFX9-NEXT:    s_endpgm
9829  %r = srem i64 %x, 1235195
9830  store i64 %r, i64 addrspace(1)* %out
9831  ret void
9832}
9833
9834define amdgpu_kernel void @srem_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) {
9835; CHECK-LABEL: @srem_i64_pow2k_denom(
9836; CHECK-NEXT:    [[R:%.*]] = srem i64 [[X:%.*]], 4096
9837; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
9838; CHECK-NEXT:    ret void
9839;
9840; GFX6-LABEL: srem_i64_pow2k_denom:
9841; GFX6:       ; %bb.0:
9842; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
9843; GFX6-NEXT:    s_mov_b32 s7, 0xf000
9844; GFX6-NEXT:    s_mov_b32 s6, -1
9845; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
9846; GFX6-NEXT:    s_mov_b32 s4, s0
9847; GFX6-NEXT:    s_ashr_i32 s0, s3, 31
9848; GFX6-NEXT:    s_lshr_b32 s0, s0, 20
9849; GFX6-NEXT:    s_add_u32 s0, s2, s0
9850; GFX6-NEXT:    s_mov_b32 s5, s1
9851; GFX6-NEXT:    s_addc_u32 s1, s3, 0
9852; GFX6-NEXT:    s_and_b32 s0, s0, 0xfffff000
9853; GFX6-NEXT:    s_sub_u32 s0, s2, s0
9854; GFX6-NEXT:    s_subb_u32 s1, s3, s1
9855; GFX6-NEXT:    v_mov_b32_e32 v0, s0
9856; GFX6-NEXT:    v_mov_b32_e32 v1, s1
9857; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
9858; GFX6-NEXT:    s_endpgm
9859;
9860; GFX9-LABEL: srem_i64_pow2k_denom:
9861; GFX9:       ; %bb.0:
9862; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
9863; GFX9-NEXT:    v_mov_b32_e32 v2, 0
9864; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
9865; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
9866; GFX9-NEXT:    s_lshr_b32 s4, s4, 20
9867; GFX9-NEXT:    s_add_u32 s4, s2, s4
9868; GFX9-NEXT:    s_addc_u32 s5, s3, 0
9869; GFX9-NEXT:    s_and_b32 s4, s4, 0xfffff000
9870; GFX9-NEXT:    s_sub_u32 s2, s2, s4
9871; GFX9-NEXT:    s_subb_u32 s3, s3, s5
9872; GFX9-NEXT:    v_mov_b32_e32 v0, s2
9873; GFX9-NEXT:    v_mov_b32_e32 v1, s3
9874; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
9875; GFX9-NEXT:    s_endpgm
9876  %r = srem i64 %x, 4096
9877  store i64 %r, i64 addrspace(1)* %out
9878  ret void
9879}
9880
9881define amdgpu_kernel void @srem_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %x, i64 %y) {
9882; CHECK-LABEL: @srem_i64_pow2_shl_denom(
9883; CHECK-NEXT:    [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]]
9884; CHECK-NEXT:    [[R:%.*]] = srem i64 [[X:%.*]], [[SHL_Y]]
9885; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
9886; CHECK-NEXT:    ret void
9887;
9888; GFX6-LABEL: srem_i64_pow2_shl_denom:
9889; GFX6:       ; %bb.0:
9890; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xd
9891; GFX6-NEXT:    s_mov_b64 s[2:3], 0x1000
9892; GFX6-NEXT:    s_mov_b32 s7, 0xf000
9893; GFX6-NEXT:    s_mov_b32 s6, -1
9894; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
9895; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
9896; GFX6-NEXT:    s_ashr_i32 s4, s3, 31
9897; GFX6-NEXT:    s_add_u32 s2, s2, s4
9898; GFX6-NEXT:    s_mov_b32 s5, s4
9899; GFX6-NEXT:    s_addc_u32 s3, s3, s4
9900; GFX6-NEXT:    s_xor_b64 s[8:9], s[2:3], s[4:5]
9901; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
9902; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
9903; GFX6-NEXT:    s_sub_u32 s4, 0, s8
9904; GFX6-NEXT:    s_subb_u32 s5, 0, s9
9905; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
9906; GFX6-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
9907; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
9908; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
9909; GFX6-NEXT:    s_ashr_i32 s10, s3, 31
9910; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
9911; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
9912; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
9913; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
9914; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
9915; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
9916; GFX6-NEXT:    s_add_u32 s2, s2, s10
9917; GFX6-NEXT:    s_mov_b32 s11, s10
9918; GFX6-NEXT:    v_mul_lo_u32 v2, s4, v1
9919; GFX6-NEXT:    v_mul_hi_u32 v3, s4, v0
9920; GFX6-NEXT:    v_mul_lo_u32 v5, s5, v0
9921; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v0
9922; GFX6-NEXT:    s_addc_u32 s3, s3, s10
9923; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9924; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
9925; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
9926; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
9927; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
9928; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
9929; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
9930; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
9931; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
9932; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
9933; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
9934; GFX6-NEXT:    s_xor_b64 s[12:13], s[2:3], s[10:11]
9935; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
9936; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
9937; GFX6-NEXT:    v_mov_b32_e32 v4, 0
9938; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
9939; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9940; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
9941; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
9942; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
9943; GFX6-NEXT:    v_mul_lo_u32 v2, s4, v1
9944; GFX6-NEXT:    v_mul_hi_u32 v3, s4, v0
9945; GFX6-NEXT:    v_mul_lo_u32 v5, s5, v0
9946; GFX6-NEXT:    s_mov_b32 s5, s1
9947; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9948; GFX6-NEXT:    v_mul_lo_u32 v3, s4, v0
9949; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
9950; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v2
9951; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v3
9952; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v2
9953; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v3
9954; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
9955; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v2
9956; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
9957; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
9958; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
9959; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
9960; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v6, vcc
9961; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v5, v4, vcc
9962; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9963; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
9964; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
9965; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
9966; GFX6-NEXT:    v_mul_lo_u32 v2, s12, v1
9967; GFX6-NEXT:    v_mul_hi_u32 v3, s12, v0
9968; GFX6-NEXT:    v_mul_hi_u32 v5, s12, v1
9969; GFX6-NEXT:    v_mul_hi_u32 v6, s13, v1
9970; GFX6-NEXT:    v_mul_lo_u32 v1, s13, v1
9971; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
9972; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
9973; GFX6-NEXT:    v_mul_lo_u32 v5, s13, v0
9974; GFX6-NEXT:    v_mul_hi_u32 v0, s13, v0
9975; GFX6-NEXT:    s_mov_b32 s4, s0
9976; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
9977; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
9978; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v6, v4, vcc
9979; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
9980; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
9981; GFX6-NEXT:    v_mul_lo_u32 v1, s8, v1
9982; GFX6-NEXT:    v_mul_hi_u32 v2, s8, v0
9983; GFX6-NEXT:    v_mul_lo_u32 v3, s9, v0
9984; GFX6-NEXT:    v_mul_lo_u32 v0, s8, v0
9985; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
9986; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
9987; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s13, v1
9988; GFX6-NEXT:    v_mov_b32_e32 v3, s9
9989; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s12, v0
9990; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
9991; GFX6-NEXT:    v_subrev_i32_e64 v4, s[0:1], s8, v0
9992; GFX6-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
9993; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v5
9994; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
9995; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v4
9996; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
9997; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
9998; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v5
9999; GFX6-NEXT:    v_subrev_i32_e64 v3, s[0:1], s8, v4
10000; GFX6-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
10001; GFX6-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
10002; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
10003; GFX6-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
10004; GFX6-NEXT:    v_mov_b32_e32 v5, s13
10005; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
10006; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
10007; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
10008; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
10009; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
10010; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
10011; GFX6-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
10012; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
10013; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
10014; GFX6-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
10015; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
10016; GFX6-NEXT:    v_xor_b32_e32 v0, s10, v0
10017; GFX6-NEXT:    v_xor_b32_e32 v1, s10, v1
10018; GFX6-NEXT:    v_mov_b32_e32 v2, s10
10019; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s10, v0
10020; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
10021; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
10022; GFX6-NEXT:    s_endpgm
10023;
10024; GFX9-LABEL: srem_i64_pow2_shl_denom:
10025; GFX9:       ; %bb.0:
10026; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x34
10027; GFX9-NEXT:    s_mov_b64 s[2:3], 0x1000
10028; GFX9-NEXT:    v_mov_b32_e32 v2, 0
10029; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
10030; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
10031; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
10032; GFX9-NEXT:    s_add_u32 s2, s2, s4
10033; GFX9-NEXT:    s_mov_b32 s5, s4
10034; GFX9-NEXT:    s_addc_u32 s3, s3, s4
10035; GFX9-NEXT:    s_xor_b64 s[8:9], s[2:3], s[4:5]
10036; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
10037; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
10038; GFX9-NEXT:    s_sub_u32 s2, 0, s8
10039; GFX9-NEXT:    s_subb_u32 s3, 0, s9
10040; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
10041; GFX9-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
10042; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
10043; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
10044; GFX9-NEXT:    s_ashr_i32 s10, s7, 31
10045; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
10046; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
10047; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
10048; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
10049; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
10050; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
10051; GFX9-NEXT:    s_add_u32 s0, s6, s10
10052; GFX9-NEXT:    s_mov_b32 s11, s10
10053; GFX9-NEXT:    v_mul_lo_u32 v3, s2, v1
10054; GFX9-NEXT:    v_mul_hi_u32 v4, s2, v0
10055; GFX9-NEXT:    v_mul_lo_u32 v6, s3, v0
10056; GFX9-NEXT:    v_mul_lo_u32 v5, s2, v0
10057; GFX9-NEXT:    s_addc_u32 s1, s7, s10
10058; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
10059; GFX9-NEXT:    v_add_u32_e32 v3, v3, v6
10060; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v5
10061; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v3
10062; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v3
10063; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v5
10064; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
10065; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v3
10066; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
10067; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
10068; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
10069; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v5
10070; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
10071; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v2, vcc
10072; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
10073; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
10074; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
10075; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
10076; GFX9-NEXT:    v_mul_lo_u32 v3, s2, v1
10077; GFX9-NEXT:    v_mul_hi_u32 v4, s2, v0
10078; GFX9-NEXT:    v_mul_lo_u32 v5, s3, v0
10079; GFX9-NEXT:    v_mul_lo_u32 v6, s2, v0
10080; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[10:11]
10081; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
10082; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
10083; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v3
10084; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v6
10085; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v3
10086; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v6
10087; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
10088; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v3
10089; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
10090; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
10091; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
10092; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
10093; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v5, vcc
10094; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v2, vcc
10095; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
10096; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
10097; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
10098; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
10099; GFX9-NEXT:    v_mul_lo_u32 v3, s6, v1
10100; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v0
10101; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v1
10102; GFX9-NEXT:    v_mul_hi_u32 v6, s7, v1
10103; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
10104; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
10105; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
10106; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v0
10107; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
10108; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
10109; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v4, v0, vcc
10110; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v2, vcc
10111; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
10112; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
10113; GFX9-NEXT:    v_mul_lo_u32 v1, s8, v1
10114; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v0
10115; GFX9-NEXT:    v_mul_lo_u32 v4, s9, v0
10116; GFX9-NEXT:    v_mul_lo_u32 v0, s8, v0
10117; GFX9-NEXT:    v_add_u32_e32 v1, v3, v1
10118; GFX9-NEXT:    v_add_u32_e32 v1, v1, v4
10119; GFX9-NEXT:    v_sub_u32_e32 v3, s7, v1
10120; GFX9-NEXT:    v_mov_b32_e32 v4, s9
10121; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, s6, v0
10122; GFX9-NEXT:    v_subb_co_u32_e64 v3, s[0:1], v3, v4, vcc
10123; GFX9-NEXT:    v_subrev_co_u32_e64 v5, s[0:1], s8, v0
10124; GFX9-NEXT:    v_subbrev_co_u32_e64 v6, s[2:3], 0, v3, s[0:1]
10125; GFX9-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v6
10126; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
10127; GFX9-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v5
10128; GFX9-NEXT:    v_subb_co_u32_e64 v3, s[0:1], v3, v4, s[0:1]
10129; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[2:3]
10130; GFX9-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v6
10131; GFX9-NEXT:    v_subrev_co_u32_e64 v4, s[0:1], s8, v5
10132; GFX9-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[2:3]
10133; GFX9-NEXT:    v_subbrev_co_u32_e64 v3, s[0:1], 0, v3, s[0:1]
10134; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v7
10135; GFX9-NEXT:    v_cndmask_b32_e64 v3, v6, v3, s[0:1]
10136; GFX9-NEXT:    v_mov_b32_e32 v6, s7
10137; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v6, v1, vcc
10138; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
10139; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
10140; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
10141; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
10142; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
10143; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc
10144; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
10145; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
10146; GFX9-NEXT:    v_cndmask_b32_e64 v3, v5, v4, s[0:1]
10147; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
10148; GFX9-NEXT:    v_xor_b32_e32 v0, s10, v0
10149; GFX9-NEXT:    v_xor_b32_e32 v1, s10, v1
10150; GFX9-NEXT:    v_mov_b32_e32 v3, s10
10151; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s10, v0
10152; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
10153; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
10154; GFX9-NEXT:    s_endpgm
10155  %shl.y = shl i64 4096, %y
10156  %r = srem i64 %x, %shl.y
10157  store i64 %r, i64 addrspace(1)* %out
10158  ret void
10159}
10160
10161define amdgpu_kernel void @srem_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
10162; CHECK-LABEL: @srem_v2i64_pow2k_denom(
10163; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
10164; CHECK-NEXT:    [[TMP2:%.*]] = srem i64 [[TMP1]], 4096
10165; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
10166; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
10167; CHECK-NEXT:    [[TMP5:%.*]] = srem i64 [[TMP4]], 4096
10168; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
10169; CHECK-NEXT:    store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
10170; CHECK-NEXT:    ret void
10171;
10172; GFX6-LABEL: srem_v2i64_pow2k_denom:
10173; GFX6:       ; %bb.0:
10174; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
10175; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
10176; GFX6-NEXT:    s_movk_i32 s8, 0xf000
10177; GFX6-NEXT:    s_mov_b32 s3, 0xf000
10178; GFX6-NEXT:    s_mov_b32 s2, -1
10179; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
10180; GFX6-NEXT:    s_ashr_i32 s9, s5, 31
10181; GFX6-NEXT:    s_lshr_b32 s9, s9, 20
10182; GFX6-NEXT:    s_add_u32 s9, s4, s9
10183; GFX6-NEXT:    s_addc_u32 s10, s5, 0
10184; GFX6-NEXT:    s_and_b32 s9, s9, s8
10185; GFX6-NEXT:    s_sub_u32 s4, s4, s9
10186; GFX6-NEXT:    s_subb_u32 s5, s5, s10
10187; GFX6-NEXT:    s_ashr_i32 s9, s7, 31
10188; GFX6-NEXT:    s_lshr_b32 s9, s9, 20
10189; GFX6-NEXT:    s_add_u32 s9, s6, s9
10190; GFX6-NEXT:    s_addc_u32 s10, s7, 0
10191; GFX6-NEXT:    s_and_b32 s8, s9, s8
10192; GFX6-NEXT:    s_sub_u32 s6, s6, s8
10193; GFX6-NEXT:    s_subb_u32 s7, s7, s10
10194; GFX6-NEXT:    v_mov_b32_e32 v0, s4
10195; GFX6-NEXT:    v_mov_b32_e32 v1, s5
10196; GFX6-NEXT:    v_mov_b32_e32 v2, s6
10197; GFX6-NEXT:    v_mov_b32_e32 v3, s7
10198; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
10199; GFX6-NEXT:    s_endpgm
10200;
10201; GFX9-LABEL: srem_v2i64_pow2k_denom:
10202; GFX9:       ; %bb.0:
10203; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
10204; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
10205; GFX9-NEXT:    s_movk_i32 s0, 0xf000
10206; GFX9-NEXT:    v_mov_b32_e32 v4, 0
10207; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
10208; GFX9-NEXT:    s_ashr_i32 s1, s5, 31
10209; GFX9-NEXT:    s_lshr_b32 s1, s1, 20
10210; GFX9-NEXT:    s_add_u32 s1, s4, s1
10211; GFX9-NEXT:    s_addc_u32 s8, s5, 0
10212; GFX9-NEXT:    s_and_b32 s1, s1, s0
10213; GFX9-NEXT:    s_sub_u32 s1, s4, s1
10214; GFX9-NEXT:    s_subb_u32 s4, s5, s8
10215; GFX9-NEXT:    s_ashr_i32 s5, s7, 31
10216; GFX9-NEXT:    s_lshr_b32 s5, s5, 20
10217; GFX9-NEXT:    s_add_u32 s5, s6, s5
10218; GFX9-NEXT:    s_addc_u32 s8, s7, 0
10219; GFX9-NEXT:    s_and_b32 s0, s5, s0
10220; GFX9-NEXT:    s_sub_u32 s0, s6, s0
10221; GFX9-NEXT:    s_subb_u32 s5, s7, s8
10222; GFX9-NEXT:    v_mov_b32_e32 v0, s1
10223; GFX9-NEXT:    v_mov_b32_e32 v1, s4
10224; GFX9-NEXT:    v_mov_b32_e32 v2, s0
10225; GFX9-NEXT:    v_mov_b32_e32 v3, s5
10226; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
10227; GFX9-NEXT:    s_endpgm
10228  %r = srem <2 x i64> %x, <i64 4096, i64 4096>
10229  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
10230  ret void
10231}
10232
10233define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
10234; CHECK-LABEL: @srem_v2i64_pow2_shl_denom(
10235; CHECK-NEXT:    [[SHL_Y:%.*]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.*]]
10236; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
10237; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 0
10238; CHECK-NEXT:    [[TMP3:%.*]] = srem i64 [[TMP1]], [[TMP2]]
10239; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i64 0
10240; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 1
10241; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
10242; CHECK-NEXT:    [[TMP7:%.*]] = srem i64 [[TMP5]], [[TMP6]]
10243; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
10244; CHECK-NEXT:    store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
10245; CHECK-NEXT:    ret void
10246;
10247; GFX6-LABEL: srem_v2i64_pow2_shl_denom:
10248; GFX6:       ; %bb.0:
10249; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
10250; GFX6-NEXT:    s_mov_b64 s[2:3], 0x1000
10251; GFX6-NEXT:    s_mov_b32 s18, 0x4f800000
10252; GFX6-NEXT:    s_mov_b32 s19, 0x5f7ffffc
10253; GFX6-NEXT:    s_mov_b32 s20, 0x2f800000
10254; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
10255; GFX6-NEXT:    s_lshl_b64 s[14:15], s[2:3], s10
10256; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s8
10257; GFX6-NEXT:    s_ashr_i32 s8, s3, 31
10258; GFX6-NEXT:    s_add_u32 s2, s2, s8
10259; GFX6-NEXT:    s_mov_b32 s9, s8
10260; GFX6-NEXT:    s_addc_u32 s3, s3, s8
10261; GFX6-NEXT:    s_xor_b64 s[16:17], s[2:3], s[8:9]
10262; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s16
10263; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s17
10264; GFX6-NEXT:    s_mov_b32 s21, 0xcf800000
10265; GFX6-NEXT:    s_sub_u32 s2, 0, s16
10266; GFX6-NEXT:    s_subb_u32 s3, 0, s17
10267; GFX6-NEXT:    v_mac_f32_e32 v0, s18, v1
10268; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
10269; GFX6-NEXT:    s_ashr_i32 s12, s5, 31
10270; GFX6-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x9
10271; GFX6-NEXT:    s_add_u32 s0, s4, s12
10272; GFX6-NEXT:    v_mul_f32_e32 v0, s19, v0
10273; GFX6-NEXT:    v_mul_f32_e32 v1, s20, v0
10274; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
10275; GFX6-NEXT:    v_mac_f32_e32 v0, s21, v1
10276; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
10277; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v0
10278; GFX6-NEXT:    s_mov_b32 s13, s12
10279; GFX6-NEXT:    s_addc_u32 s1, s5, s12
10280; GFX6-NEXT:    v_mul_lo_u32 v0, s2, v1
10281; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v2
10282; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v2
10283; GFX6-NEXT:    v_mul_lo_u32 v5, s2, v2
10284; GFX6-NEXT:    s_xor_b64 s[4:5], s[0:1], s[12:13]
10285; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
10286; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v0, v4
10287; GFX6-NEXT:    v_mul_lo_u32 v0, v2, v3
10288; GFX6-NEXT:    v_mul_hi_u32 v4, v2, v5
10289; GFX6-NEXT:    v_mul_hi_u32 v6, v2, v3
10290; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v3
10291; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
10292; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v4, v0
10293; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v6, vcc
10294; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v5
10295; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v5
10296; GFX6-NEXT:    s_mov_b32 s11, 0xf000
10297; GFX6-NEXT:    s_mov_b32 s10, -1
10298; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
10299; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v4, v5, vcc
10300; GFX6-NEXT:    v_mov_b32_e32 v0, 0
10301; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v0, vcc
10302; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
10303; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
10304; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
10305; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
10306; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v1
10307; GFX6-NEXT:    v_mul_hi_u32 v4, s2, v2
10308; GFX6-NEXT:    v_mul_lo_u32 v5, s3, v2
10309; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
10310; GFX6-NEXT:    v_mul_lo_u32 v4, s2, v2
10311; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
10312; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v3
10313; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v4
10314; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v3
10315; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v4
10316; GFX6-NEXT:    v_mul_lo_u32 v4, v1, v4
10317; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v3
10318; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
10319; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
10320; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
10321; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
10322; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
10323; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v5, v0, vcc
10324; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
10325; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
10326; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
10327; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
10328; GFX6-NEXT:    v_mul_lo_u32 v3, s4, v1
10329; GFX6-NEXT:    v_mul_hi_u32 v4, s4, v2
10330; GFX6-NEXT:    v_mul_hi_u32 v5, s4, v1
10331; GFX6-NEXT:    v_mul_hi_u32 v6, s5, v1
10332; GFX6-NEXT:    v_mul_lo_u32 v1, s5, v1
10333; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
10334; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
10335; GFX6-NEXT:    v_mul_lo_u32 v5, s5, v2
10336; GFX6-NEXT:    v_mul_hi_u32 v2, s5, v2
10337; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
10338; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v4, v2, vcc
10339; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v0, vcc
10340; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
10341; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
10342; GFX6-NEXT:    v_mul_lo_u32 v2, s16, v2
10343; GFX6-NEXT:    v_mul_hi_u32 v3, s16, v1
10344; GFX6-NEXT:    v_mul_lo_u32 v4, s17, v1
10345; GFX6-NEXT:    v_mul_lo_u32 v1, s16, v1
10346; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
10347; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
10348; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s5, v2
10349; GFX6-NEXT:    v_mov_b32_e32 v4, s17
10350; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s4, v1
10351; GFX6-NEXT:    v_subb_u32_e64 v3, s[0:1], v3, v4, vcc
10352; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s16, v1
10353; GFX6-NEXT:    v_subbrev_u32_e64 v6, s[2:3], 0, v3, s[0:1]
10354; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s17, v6
10355; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
10356; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s16, v5
10357; GFX6-NEXT:    v_subb_u32_e64 v3, s[0:1], v3, v4, s[0:1]
10358; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[2:3]
10359; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s17, v6
10360; GFX6-NEXT:    v_subrev_i32_e64 v4, s[0:1], s16, v5
10361; GFX6-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[2:3]
10362; GFX6-NEXT:    v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]
10363; GFX6-NEXT:    s_ashr_i32 s2, s15, 31
10364; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v7
10365; GFX6-NEXT:    s_add_u32 s4, s14, s2
10366; GFX6-NEXT:    v_cndmask_b32_e64 v3, v6, v3, s[0:1]
10367; GFX6-NEXT:    v_mov_b32_e32 v6, s5
10368; GFX6-NEXT:    s_mov_b32 s3, s2
10369; GFX6-NEXT:    s_addc_u32 s5, s15, s2
10370; GFX6-NEXT:    s_xor_b64 s[4:5], s[4:5], s[2:3]
10371; GFX6-NEXT:    v_cvt_f32_u32_e32 v7, s4
10372; GFX6-NEXT:    v_cvt_f32_u32_e32 v8, s5
10373; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
10374; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s17, v2
10375; GFX6-NEXT:    v_mac_f32_e32 v7, s18, v8
10376; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
10377; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s16, v1
10378; GFX6-NEXT:    v_rcp_f32_e32 v7, v7
10379; GFX6-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
10380; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s17, v2
10381; GFX6-NEXT:    v_cndmask_b32_e32 v6, v6, v9, vcc
10382; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
10383; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
10384; GFX6-NEXT:    v_cndmask_b32_e64 v3, v5, v4, s[0:1]
10385; GFX6-NEXT:    v_mul_f32_e32 v4, s19, v7
10386; GFX6-NEXT:    v_mul_f32_e32 v5, s20, v4
10387; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
10388; GFX6-NEXT:    v_mac_f32_e32 v4, s21, v5
10389; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
10390; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v5
10391; GFX6-NEXT:    s_sub_u32 s0, 0, s4
10392; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
10393; GFX6-NEXT:    v_mul_hi_u32 v3, s0, v4
10394; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v5
10395; GFX6-NEXT:    s_subb_u32 s1, 0, s5
10396; GFX6-NEXT:    v_mul_lo_u32 v7, s1, v4
10397; GFX6-NEXT:    s_ashr_i32 s14, s7, 31
10398; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
10399; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v4
10400; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
10401; GFX6-NEXT:    v_mul_lo_u32 v7, v4, v3
10402; GFX6-NEXT:    v_mul_hi_u32 v8, v4, v6
10403; GFX6-NEXT:    v_mul_hi_u32 v9, v4, v3
10404; GFX6-NEXT:    v_mul_hi_u32 v10, v5, v3
10405; GFX6-NEXT:    v_mul_lo_u32 v3, v5, v3
10406; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
10407; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
10408; GFX6-NEXT:    v_mul_lo_u32 v9, v5, v6
10409; GFX6-NEXT:    v_mul_hi_u32 v6, v5, v6
10410; GFX6-NEXT:    s_mov_b32 s15, s14
10411; GFX6-NEXT:    v_xor_b32_e32 v1, s12, v1
10412; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
10413; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v8, v6, vcc
10414; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v10, v0, vcc
10415; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
10416; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
10417; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
10418; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v5, v6, vcc
10419; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v4
10420; GFX6-NEXT:    v_mul_hi_u32 v6, s0, v3
10421; GFX6-NEXT:    v_mul_lo_u32 v7, s1, v3
10422; GFX6-NEXT:    v_xor_b32_e32 v2, s12, v2
10423; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
10424; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v3
10425; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
10426; GFX6-NEXT:    v_mul_lo_u32 v9, v3, v5
10427; GFX6-NEXT:    v_mul_hi_u32 v10, v3, v6
10428; GFX6-NEXT:    v_mul_hi_u32 v11, v3, v5
10429; GFX6-NEXT:    v_mul_hi_u32 v8, v4, v6
10430; GFX6-NEXT:    v_mul_lo_u32 v6, v4, v6
10431; GFX6-NEXT:    v_mul_hi_u32 v7, v4, v5
10432; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
10433; GFX6-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
10434; GFX6-NEXT:    v_mul_lo_u32 v5, v4, v5
10435; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
10436; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v10, v8, vcc
10437; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v7, v0, vcc
10438; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
10439; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
10440; GFX6-NEXT:    s_add_u32 s0, s6, s14
10441; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
10442; GFX6-NEXT:    s_addc_u32 s1, s7, s14
10443; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
10444; GFX6-NEXT:    s_xor_b64 s[6:7], s[0:1], s[14:15]
10445; GFX6-NEXT:    v_mul_lo_u32 v5, s6, v4
10446; GFX6-NEXT:    v_mul_hi_u32 v6, s6, v3
10447; GFX6-NEXT:    v_mul_hi_u32 v8, s6, v4
10448; GFX6-NEXT:    v_mul_hi_u32 v9, s7, v4
10449; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v4
10450; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
10451; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
10452; GFX6-NEXT:    v_mul_lo_u32 v8, s7, v3
10453; GFX6-NEXT:    v_mul_hi_u32 v3, s7, v3
10454; GFX6-NEXT:    v_mov_b32_e32 v7, s12
10455; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
10456; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v3, vcc
10457; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v9, v0, vcc
10458; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
10459; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v0, vcc
10460; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v0
10461; GFX6-NEXT:    v_mul_hi_u32 v5, s4, v3
10462; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s12, v1
10463; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v2, v7, vcc
10464; GFX6-NEXT:    v_mul_lo_u32 v2, s5, v3
10465; GFX6-NEXT:    v_mul_lo_u32 v3, s4, v3
10466; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
10467; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
10468; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s7, v2
10469; GFX6-NEXT:    v_mov_b32_e32 v5, s5
10470; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s6, v3
10471; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
10472; GFX6-NEXT:    v_subrev_i32_e64 v6, s[0:1], s4, v3
10473; GFX6-NEXT:    v_subbrev_u32_e64 v7, s[2:3], 0, v4, s[0:1]
10474; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s5, v7
10475; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[2:3]
10476; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s4, v6
10477; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, s[0:1]
10478; GFX6-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[2:3]
10479; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s5, v7
10480; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s4, v6
10481; GFX6-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[2:3]
10482; GFX6-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
10483; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v8
10484; GFX6-NEXT:    v_cndmask_b32_e64 v4, v7, v4, s[0:1]
10485; GFX6-NEXT:    v_mov_b32_e32 v7, s7
10486; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v7, v2, vcc
10487; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s5, v2
10488; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
10489; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s4, v3
10490; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
10491; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s5, v2
10492; GFX6-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
10493; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
10494; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
10495; GFX6-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
10496; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
10497; GFX6-NEXT:    v_xor_b32_e32 v3, s14, v3
10498; GFX6-NEXT:    v_xor_b32_e32 v4, s14, v2
10499; GFX6-NEXT:    v_mov_b32_e32 v5, s14
10500; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s14, v3
10501; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v4, v5, vcc
10502; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
10503; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
10504; GFX6-NEXT:    s_endpgm
10505;
10506; GFX9-LABEL: srem_v2i64_pow2_shl_denom:
10507; GFX9:       ; %bb.0:
10508; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
10509; GFX9-NEXT:    s_mov_b64 s[2:3], 0x1000
10510; GFX9-NEXT:    s_mov_b32 s16, 0x4f800000
10511; GFX9-NEXT:    s_mov_b32 s17, 0x5f7ffffc
10512; GFX9-NEXT:    s_mov_b32 s18, 0x2f800000
10513; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
10514; GFX9-NEXT:    s_lshl_b64 s[10:11], s[2:3], s10
10515; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s8
10516; GFX9-NEXT:    s_ashr_i32 s8, s3, 31
10517; GFX9-NEXT:    s_add_u32 s2, s2, s8
10518; GFX9-NEXT:    s_mov_b32 s9, s8
10519; GFX9-NEXT:    s_addc_u32 s3, s3, s8
10520; GFX9-NEXT:    s_xor_b64 s[12:13], s[2:3], s[8:9]
10521; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s12
10522; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s13
10523; GFX9-NEXT:    s_mov_b32 s19, 0xcf800000
10524; GFX9-NEXT:    s_sub_u32 s2, 0, s12
10525; GFX9-NEXT:    s_subb_u32 s3, 0, s13
10526; GFX9-NEXT:    v_mac_f32_e32 v0, s16, v1
10527; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
10528; GFX9-NEXT:    s_ashr_i32 s8, s5, 31
10529; GFX9-NEXT:    s_mov_b32 s9, s8
10530; GFX9-NEXT:    v_mul_f32_e32 v0, s17, v0
10531; GFX9-NEXT:    v_mul_f32_e32 v1, s18, v0
10532; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
10533; GFX9-NEXT:    v_mac_f32_e32 v0, s19, v1
10534; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
10535; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v0
10536; GFX9-NEXT:    v_mul_lo_u32 v0, s2, v1
10537; GFX9-NEXT:    v_mul_hi_u32 v3, s2, v2
10538; GFX9-NEXT:    v_mul_lo_u32 v5, s3, v2
10539; GFX9-NEXT:    v_mul_lo_u32 v4, s2, v2
10540; GFX9-NEXT:    v_add_u32_e32 v0, v3, v0
10541; GFX9-NEXT:    v_add_u32_e32 v5, v0, v5
10542; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v4
10543; GFX9-NEXT:    v_mul_lo_u32 v6, v2, v5
10544; GFX9-NEXT:    v_mul_hi_u32 v7, v2, v5
10545; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v5
10546; GFX9-NEXT:    v_mov_b32_e32 v0, 0
10547; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
10548; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
10549; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
10550; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
10551; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
10552; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
10553; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v5
10554; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v0, vcc
10555; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v4
10556; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
10557; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
10558; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
10559; GFX9-NEXT:    v_mul_lo_u32 v3, s2, v1
10560; GFX9-NEXT:    v_mul_hi_u32 v4, s2, v2
10561; GFX9-NEXT:    v_mul_lo_u32 v5, s3, v2
10562; GFX9-NEXT:    v_mul_lo_u32 v6, s2, v2
10563; GFX9-NEXT:    s_add_u32 s2, s4, s8
10564; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
10565; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
10566; GFX9-NEXT:    v_mul_lo_u32 v7, v2, v3
10567; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v6
10568; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v3
10569; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v6
10570; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
10571; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v3
10572; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
10573; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
10574; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
10575; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
10576; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v5, vcc
10577; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v0, vcc
10578; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
10579; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
10580; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
10581; GFX9-NEXT:    s_addc_u32 s3, s5, s8
10582; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
10583; GFX9-NEXT:    s_xor_b64 s[14:15], s[2:3], s[8:9]
10584; GFX9-NEXT:    v_mul_lo_u32 v3, s14, v1
10585; GFX9-NEXT:    v_mul_hi_u32 v4, s14, v2
10586; GFX9-NEXT:    v_mul_hi_u32 v5, s14, v1
10587; GFX9-NEXT:    v_mul_hi_u32 v6, s15, v1
10588; GFX9-NEXT:    v_mul_lo_u32 v1, s15, v1
10589; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
10590; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
10591; GFX9-NEXT:    v_mul_lo_u32 v5, s15, v2
10592; GFX9-NEXT:    v_mul_hi_u32 v2, s15, v2
10593; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
10594; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
10595; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v4, v2, vcc
10596; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v0, vcc
10597; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v2, v1
10598; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v3, vcc
10599; GFX9-NEXT:    v_mul_lo_u32 v2, s12, v2
10600; GFX9-NEXT:    v_mul_hi_u32 v3, s12, v1
10601; GFX9-NEXT:    v_mul_lo_u32 v4, s13, v1
10602; GFX9-NEXT:    v_mul_lo_u32 v1, s12, v1
10603; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
10604; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
10605; GFX9-NEXT:    v_sub_u32_e32 v3, s15, v2
10606; GFX9-NEXT:    v_mov_b32_e32 v4, s13
10607; GFX9-NEXT:    v_sub_co_u32_e32 v1, vcc, s14, v1
10608; GFX9-NEXT:    v_subb_co_u32_e64 v3, s[0:1], v3, v4, vcc
10609; GFX9-NEXT:    v_subrev_co_u32_e64 v5, s[0:1], s12, v1
10610; GFX9-NEXT:    v_subbrev_co_u32_e64 v6, s[2:3], 0, v3, s[0:1]
10611; GFX9-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v6
10612; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
10613; GFX9-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v5
10614; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[2:3]
10615; GFX9-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v6
10616; GFX9-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[2:3]
10617; GFX9-NEXT:    s_ashr_i32 s2, s11, 31
10618; GFX9-NEXT:    v_subb_co_u32_e64 v3, s[0:1], v3, v4, s[0:1]
10619; GFX9-NEXT:    s_add_u32 s10, s10, s2
10620; GFX9-NEXT:    v_subrev_co_u32_e64 v4, s[0:1], s12, v5
10621; GFX9-NEXT:    s_mov_b32 s3, s2
10622; GFX9-NEXT:    s_addc_u32 s11, s11, s2
10623; GFX9-NEXT:    v_subbrev_co_u32_e64 v3, s[0:1], 0, v3, s[0:1]
10624; GFX9-NEXT:    s_xor_b64 s[10:11], s[10:11], s[2:3]
10625; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v7
10626; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s10
10627; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, s11
10628; GFX9-NEXT:    v_cndmask_b32_e64 v3, v6, v3, s[0:1]
10629; GFX9-NEXT:    v_mov_b32_e32 v6, s15
10630; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v6, v2, vcc
10631; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s13, v2
10632; GFX9-NEXT:    v_mac_f32_e32 v7, s16, v8
10633; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
10634; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s12, v1
10635; GFX9-NEXT:    v_rcp_f32_e32 v7, v7
10636; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
10637; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v2
10638; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v9, vcc
10639; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
10640; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
10641; GFX9-NEXT:    v_cndmask_b32_e64 v3, v5, v4, s[0:1]
10642; GFX9-NEXT:    v_mul_f32_e32 v4, s17, v7
10643; GFX9-NEXT:    v_mul_f32_e32 v5, s18, v4
10644; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
10645; GFX9-NEXT:    v_mac_f32_e32 v4, s19, v5
10646; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
10647; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
10648; GFX9-NEXT:    s_sub_u32 s0, 0, s10
10649; GFX9-NEXT:    s_subb_u32 s1, 0, s11
10650; GFX9-NEXT:    v_mul_hi_u32 v6, s0, v4
10651; GFX9-NEXT:    v_mul_lo_u32 v7, s0, v5
10652; GFX9-NEXT:    v_mul_lo_u32 v8, s1, v4
10653; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
10654; GFX9-NEXT:    v_mul_lo_u32 v3, s0, v4
10655; GFX9-NEXT:    v_add_u32_e32 v6, v6, v7
10656; GFX9-NEXT:    v_add_u32_e32 v6, v6, v8
10657; GFX9-NEXT:    v_mul_lo_u32 v7, v4, v6
10658; GFX9-NEXT:    v_mul_hi_u32 v8, v4, v3
10659; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v6
10660; GFX9-NEXT:    v_mul_hi_u32 v10, v5, v6
10661; GFX9-NEXT:    v_mul_lo_u32 v6, v5, v6
10662; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
10663; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
10664; GFX9-NEXT:    v_mul_lo_u32 v9, v5, v3
10665; GFX9-NEXT:    v_mul_hi_u32 v3, v5, v3
10666; GFX9-NEXT:    s_ashr_i32 s12, s7, 31
10667; GFX9-NEXT:    s_mov_b32 s13, s12
10668; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v9
10669; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v8, v3, vcc
10670; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v10, v0, vcc
10671; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
10672; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
10673; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
10674; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v6, vcc
10675; GFX9-NEXT:    v_mul_lo_u32 v5, s0, v4
10676; GFX9-NEXT:    v_mul_hi_u32 v6, s0, v3
10677; GFX9-NEXT:    v_mul_lo_u32 v7, s1, v3
10678; GFX9-NEXT:    v_mul_lo_u32 v8, s0, v3
10679; GFX9-NEXT:    s_add_u32 s0, s6, s12
10680; GFX9-NEXT:    v_add_u32_e32 v5, v6, v5
10681; GFX9-NEXT:    v_add_u32_e32 v5, v5, v7
10682; GFX9-NEXT:    v_mul_lo_u32 v9, v3, v5
10683; GFX9-NEXT:    v_mul_hi_u32 v10, v3, v8
10684; GFX9-NEXT:    v_mul_hi_u32 v11, v3, v5
10685; GFX9-NEXT:    v_mul_hi_u32 v7, v4, v8
10686; GFX9-NEXT:    v_mul_lo_u32 v8, v4, v8
10687; GFX9-NEXT:    v_mul_hi_u32 v6, v4, v5
10688; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
10689; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
10690; GFX9-NEXT:    v_mul_lo_u32 v5, v4, v5
10691; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
10692; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v10, v7, vcc
10693; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v6, v0, vcc
10694; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
10695; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
10696; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
10697; GFX9-NEXT:    s_addc_u32 s1, s7, s12
10698; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v6, vcc
10699; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[12:13]
10700; GFX9-NEXT:    v_mul_lo_u32 v5, s6, v4
10701; GFX9-NEXT:    v_mul_hi_u32 v6, s6, v3
10702; GFX9-NEXT:    v_mul_hi_u32 v8, s6, v4
10703; GFX9-NEXT:    v_mul_hi_u32 v9, s7, v4
10704; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v4
10705; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v6, v5
10706; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
10707; GFX9-NEXT:    v_mul_lo_u32 v8, s7, v3
10708; GFX9-NEXT:    v_mul_hi_u32 v3, s7, v3
10709; GFX9-NEXT:    v_xor_b32_e32 v1, s8, v1
10710; GFX9-NEXT:    v_xor_b32_e32 v2, s8, v2
10711; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v8
10712; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
10713; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v0, vcc
10714; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v4
10715; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
10716; GFX9-NEXT:    v_mul_lo_u32 v4, s10, v4
10717; GFX9-NEXT:    v_mul_hi_u32 v5, s10, v3
10718; GFX9-NEXT:    v_mul_lo_u32 v6, s11, v3
10719; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v3
10720; GFX9-NEXT:    v_mov_b32_e32 v7, s8
10721; GFX9-NEXT:    v_subrev_co_u32_e32 v1, vcc, s8, v1
10722; GFX9-NEXT:    v_add_u32_e32 v4, v5, v4
10723; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v2, v7, vcc
10724; GFX9-NEXT:    v_add_u32_e32 v4, v4, v6
10725; GFX9-NEXT:    v_sub_u32_e32 v5, s7, v4
10726; GFX9-NEXT:    v_mov_b32_e32 v6, s11
10727; GFX9-NEXT:    v_sub_co_u32_e32 v3, vcc, s6, v3
10728; GFX9-NEXT:    v_subb_co_u32_e64 v5, s[0:1], v5, v6, vcc
10729; GFX9-NEXT:    v_subrev_co_u32_e64 v7, s[0:1], s10, v3
10730; GFX9-NEXT:    v_subbrev_co_u32_e64 v8, s[2:3], 0, v5, s[0:1]
10731; GFX9-NEXT:    v_cmp_le_u32_e64 s[2:3], s11, v8
10732; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[2:3]
10733; GFX9-NEXT:    v_cmp_le_u32_e64 s[2:3], s10, v7
10734; GFX9-NEXT:    v_subb_co_u32_e64 v5, s[0:1], v5, v6, s[0:1]
10735; GFX9-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[2:3]
10736; GFX9-NEXT:    v_cmp_eq_u32_e64 s[2:3], s11, v8
10737; GFX9-NEXT:    v_subrev_co_u32_e64 v6, s[0:1], s10, v7
10738; GFX9-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[2:3]
10739; GFX9-NEXT:    v_subbrev_co_u32_e64 v5, s[0:1], 0, v5, s[0:1]
10740; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v9
10741; GFX9-NEXT:    v_cndmask_b32_e64 v5, v8, v5, s[0:1]
10742; GFX9-NEXT:    v_mov_b32_e32 v8, s7
10743; GFX9-NEXT:    v_subb_co_u32_e32 v4, vcc, v8, v4, vcc
10744; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v4
10745; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
10746; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
10747; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
10748; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v4
10749; GFX9-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
10750; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
10751; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
10752; GFX9-NEXT:    v_cndmask_b32_e64 v5, v7, v6, s[0:1]
10753; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
10754; GFX9-NEXT:    v_xor_b32_e32 v3, s12, v3
10755; GFX9-NEXT:    v_xor_b32_e32 v4, s12, v4
10756; GFX9-NEXT:    v_mov_b32_e32 v5, s12
10757; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s12, v3
10758; GFX9-NEXT:    v_subb_co_u32_e32 v4, vcc, v4, v5, vcc
10759; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
10760; GFX9-NEXT:    global_store_dwordx4 v0, v[1:4], s[4:5]
10761; GFX9-NEXT:    s_endpgm
10762  %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
10763  %r = srem <2 x i64> %x, %shl.y
10764  store <2 x i64> %r, <2 x i64> addrspace(1)* %out
10765  ret void
10766}
10767