1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -amdgpu-codegenprepare %s | FileCheck -check-prefix=IR %s
3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s
4
5define i32 @select_sdiv_lhs_const_i32(i1 %cond) {
6; IR-LABEL: @select_sdiv_lhs_const_i32(
7; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], i32 200000, i32 125000
8; IR-NEXT:    ret i32 [[OP]]
9;
10; GCN-LABEL: select_sdiv_lhs_const_i32:
11; GCN:       ; %bb.0:
12; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
13; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
14; GCN-NEXT:    v_mov_b32_e32 v1, 0x1e848
15; GCN-NEXT:    v_mov_b32_e32 v2, 0x30d40
16; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
17; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
18; GCN-NEXT:    s_setpc_b64 s[30:31]
19  %select = select i1 %cond, i32 5, i32 8
20  %op = sdiv i32 1000000, %select
21  ret i32 %op
22}
23
24define i32 @select_sdiv_rhs_const_i32(i1 %cond) {
25; IR-LABEL: @select_sdiv_rhs_const_i32(
26; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], i32 1000, i32 10000
27; IR-NEXT:    ret i32 [[OP]]
28;
29; GCN-LABEL: select_sdiv_rhs_const_i32:
30; GCN:       ; %bb.0:
31; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
32; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
33; GCN-NEXT:    v_mov_b32_e32 v1, 0x2710
34; GCN-NEXT:    v_mov_b32_e32 v2, 0x3e8
35; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
36; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
37; GCN-NEXT:    s_setpc_b64 s[30:31]
38  %select = select i1 %cond, i32 42000, i32 420000
39  %op = sdiv i32 %select, 42
40  ret i32 %op
41}
42
43define <2 x i32> @select_sdiv_lhs_const_v2i32(i1 %cond) {
44; IR-LABEL: @select_sdiv_lhs_const_v2i32(
45; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], <2 x i32> <i32 666, i32 undef>, <2 x i32> <i32 555, i32 1428>
46; IR-NEXT:    ret <2 x i32> [[OP]]
47;
48; GCN-LABEL: select_sdiv_lhs_const_v2i32:
49; GCN:       ; %bb.0:
50; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
51; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
52; GCN-NEXT:    v_mov_b32_e32 v1, 0x22b
53; GCN-NEXT:    v_mov_b32_e32 v2, 0x29a
54; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
55; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
56; GCN-NEXT:    v_mov_b32_e32 v1, 0x594
57; GCN-NEXT:    s_setpc_b64 s[30:31]
58  %select = select i1 %cond, <2 x i32> <i32 5, i32 undef>, <2 x i32> <i32 6, i32 7>
59  %op = sdiv <2 x i32> <i32 3333, i32 9999>, %select
60  ret <2 x i32> %op
61}
62
63define <2 x i32> @select_sdiv_rhs_const_v2i32(i1 %cond) {
64; IR-LABEL: @select_sdiv_rhs_const_v2i32(
65; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], <2 x i32> <i32 198621, i32 20855308>, <2 x i32> <i32 222748, i32 2338858>
66; IR-NEXT:    ret <2 x i32> [[OP]]
67;
68; GCN-LABEL: select_sdiv_rhs_const_v2i32:
69; GCN:       ; %bb.0:
70; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
71; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
72; GCN-NEXT:    v_mov_b32_e32 v1, 0x3661c
73; GCN-NEXT:    v_mov_b32_e32 v2, 0x307dd
74; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
75; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
76; GCN-NEXT:    v_mov_b32_e32 v1, 0x23b02a
77; GCN-NEXT:    v_mov_b32_e32 v2, 0x13e3a0c
78; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
79; GCN-NEXT:    s_setpc_b64 s[30:31]
80  %select = select i1 %cond, <2 x i32> <i32 8342123, i32 834212353>, <2 x i32> <i32 9355456, i32 93554321>
81  %op = sdiv <2 x i32> %select, <i32 42, i32 40>
82  ret <2 x i32> %op
83}
84
85@gv = external addrspace(1) global i32
86
87define i32 @select_sdiv_lhs_opaque_const0_i32(i1 %cond) {
88; IR-LABEL: @select_sdiv_lhs_opaque_const0_i32(
89; IR-NEXT:    [[SELECT:%.*]] = select i1 [[COND:%.*]], i32 ptrtoint (i32 addrspace(1)* @gv to i32), i32 5
90; IR-NEXT:    [[TMP1:%.*]] = ashr i32 [[SELECT]], 31
91; IR-NEXT:    [[TMP2:%.*]] = xor i32 0, [[TMP1]]
92; IR-NEXT:    [[TMP3:%.*]] = add i32 [[SELECT]], [[TMP1]]
93; IR-NEXT:    [[TMP4:%.*]] = xor i32 [[TMP3]], [[TMP1]]
94; IR-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP4]] to float
95; IR-NEXT:    [[TMP6:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP5]])
96; IR-NEXT:    [[TMP7:%.*]] = fmul fast float [[TMP6]], 0x41F0000000000000
97; IR-NEXT:    [[TMP8:%.*]] = fptoui float [[TMP7]] to i32
98; IR-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
99; IR-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP4]] to i64
100; IR-NEXT:    [[TMP11:%.*]] = mul i64 [[TMP9]], [[TMP10]]
101; IR-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
102; IR-NEXT:    [[TMP13:%.*]] = lshr i64 [[TMP11]], 32
103; IR-NEXT:    [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32
104; IR-NEXT:    [[TMP15:%.*]] = sub i32 0, [[TMP12]]
105; IR-NEXT:    [[TMP16:%.*]] = icmp eq i32 [[TMP14]], 0
106; IR-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP15]], i32 [[TMP12]]
107; IR-NEXT:    [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
108; IR-NEXT:    [[TMP19:%.*]] = zext i32 [[TMP8]] to i64
109; IR-NEXT:    [[TMP20:%.*]] = mul i64 [[TMP18]], [[TMP19]]
110; IR-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
111; IR-NEXT:    [[TMP22:%.*]] = lshr i64 [[TMP20]], 32
112; IR-NEXT:    [[TMP23:%.*]] = trunc i64 [[TMP22]] to i32
113; IR-NEXT:    [[TMP24:%.*]] = add i32 [[TMP8]], [[TMP23]]
114; IR-NEXT:    [[TMP25:%.*]] = sub i32 [[TMP8]], [[TMP23]]
115; IR-NEXT:    [[TMP26:%.*]] = select i1 [[TMP16]], i32 [[TMP24]], i32 [[TMP25]]
116; IR-NEXT:    [[TMP27:%.*]] = zext i32 [[TMP26]] to i64
117; IR-NEXT:    [[TMP28:%.*]] = mul i64 [[TMP27]], 1000000
118; IR-NEXT:    [[TMP29:%.*]] = trunc i64 [[TMP28]] to i32
119; IR-NEXT:    [[TMP30:%.*]] = lshr i64 [[TMP28]], 32
120; IR-NEXT:    [[TMP31:%.*]] = trunc i64 [[TMP30]] to i32
121; IR-NEXT:    [[TMP32:%.*]] = mul i32 [[TMP31]], [[TMP4]]
122; IR-NEXT:    [[TMP33:%.*]] = sub i32 1000000, [[TMP32]]
123; IR-NEXT:    [[TMP34:%.*]] = icmp uge i32 [[TMP33]], [[TMP4]]
124; IR-NEXT:    [[TMP35:%.*]] = icmp uge i32 1000000, [[TMP32]]
125; IR-NEXT:    [[TMP36:%.*]] = and i1 [[TMP34]], [[TMP35]]
126; IR-NEXT:    [[TMP37:%.*]] = add i32 [[TMP31]], 1
127; IR-NEXT:    [[TMP38:%.*]] = sub i32 [[TMP31]], 1
128; IR-NEXT:    [[TMP39:%.*]] = select i1 [[TMP36]], i32 [[TMP37]], i32 [[TMP31]]
129; IR-NEXT:    [[TMP40:%.*]] = select i1 [[TMP35]], i32 [[TMP39]], i32 [[TMP38]]
130; IR-NEXT:    [[TMP41:%.*]] = xor i32 [[TMP40]], [[TMP2]]
131; IR-NEXT:    [[TMP42:%.*]] = sub i32 [[TMP41]], [[TMP2]]
132; IR-NEXT:    ret i32 [[TMP42]]
133;
134; GCN-LABEL: select_sdiv_lhs_opaque_const0_i32:
135; GCN:       ; %bb.0:
136; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
137; GCN-NEXT:    s_getpc_b64 s[4:5]
138; GCN-NEXT:    s_add_u32 s4, s4, gv@gotpcrel32@lo+4
139; GCN-NEXT:    s_addc_u32 s5, s5, gv@gotpcrel32@hi+4
140; GCN-NEXT:    s_load_dword s4, s[4:5], 0x0
141; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
142; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
143; GCN-NEXT:    s_mov_b32 s6, 0xf4240
144; GCN-NEXT:    s_waitcnt lgkmcnt(0)
145; GCN-NEXT:    v_mov_b32_e32 v1, s4
146; GCN-NEXT:    v_cndmask_b32_e32 v0, 5, v1, vcc
147; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
148; GCN-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
149; GCN-NEXT:    v_xor_b32_e32 v0, v0, v1
150; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
151; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v2
152; GCN-NEXT:    v_mul_f32_e32 v2, 0x4f800000, v2
153; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
154; GCN-NEXT:    v_mul_lo_u32 v3, v2, v0
155; GCN-NEXT:    v_mul_hi_u32 v4, v2, v0
156; GCN-NEXT:    v_sub_u32_e32 v5, vcc, 0, v3
157; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v4
158; GCN-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
159; GCN-NEXT:    v_mul_hi_u32 v3, v3, v2
160; GCN-NEXT:    v_add_u32_e64 v4, s[4:5], v2, v3
161; GCN-NEXT:    v_sub_u32_e64 v2, s[4:5], v2, v3
162; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
163; GCN-NEXT:    v_mul_hi_u32 v2, v2, s6
164; GCN-NEXT:    s_mov_b32 s4, 0xf4241
165; GCN-NEXT:    v_mul_lo_u32 v3, v2, v0
166; GCN-NEXT:    v_add_u32_e32 v4, vcc, 1, v2
167; GCN-NEXT:    v_add_u32_e32 v5, vcc, -1, v2
168; GCN-NEXT:    v_sub_u32_e32 v6, vcc, s6, v3
169; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, s4, v3
170; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v0
171; GCN-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
172; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v4, s[4:5]
173; GCN-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
174; GCN-NEXT:    v_xor_b32_e32 v0, v0, v1
175; GCN-NEXT:    v_sub_u32_e32 v0, vcc, v0, v1
176; GCN-NEXT:    s_setpc_b64 s[30:31]
177  %select = select i1 %cond, i32 ptrtoint (i32 addrspace(1)* @gv to i32), i32 5
178  %op = sdiv i32 1000000, %select
179  ret i32 %op
180}
181
182define i32 @select_sdiv_lhs_opaque_const1_i32(i1 %cond) {
183; IR-LABEL: @select_sdiv_lhs_opaque_const1_i32(
184; IR-NEXT:    [[SELECT:%.*]] = select i1 [[COND:%.*]], i32 5, i32 ptrtoint (i32 addrspace(1)* @gv to i32)
185; IR-NEXT:    [[TMP1:%.*]] = ashr i32 [[SELECT]], 31
186; IR-NEXT:    [[TMP2:%.*]] = xor i32 0, [[TMP1]]
187; IR-NEXT:    [[TMP3:%.*]] = add i32 [[SELECT]], [[TMP1]]
188; IR-NEXT:    [[TMP4:%.*]] = xor i32 [[TMP3]], [[TMP1]]
189; IR-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP4]] to float
190; IR-NEXT:    [[TMP6:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP5]])
191; IR-NEXT:    [[TMP7:%.*]] = fmul fast float [[TMP6]], 0x41F0000000000000
192; IR-NEXT:    [[TMP8:%.*]] = fptoui float [[TMP7]] to i32
193; IR-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
194; IR-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP4]] to i64
195; IR-NEXT:    [[TMP11:%.*]] = mul i64 [[TMP9]], [[TMP10]]
196; IR-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
197; IR-NEXT:    [[TMP13:%.*]] = lshr i64 [[TMP11]], 32
198; IR-NEXT:    [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32
199; IR-NEXT:    [[TMP15:%.*]] = sub i32 0, [[TMP12]]
200; IR-NEXT:    [[TMP16:%.*]] = icmp eq i32 [[TMP14]], 0
201; IR-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP15]], i32 [[TMP12]]
202; IR-NEXT:    [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
203; IR-NEXT:    [[TMP19:%.*]] = zext i32 [[TMP8]] to i64
204; IR-NEXT:    [[TMP20:%.*]] = mul i64 [[TMP18]], [[TMP19]]
205; IR-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
206; IR-NEXT:    [[TMP22:%.*]] = lshr i64 [[TMP20]], 32
207; IR-NEXT:    [[TMP23:%.*]] = trunc i64 [[TMP22]] to i32
208; IR-NEXT:    [[TMP24:%.*]] = add i32 [[TMP8]], [[TMP23]]
209; IR-NEXT:    [[TMP25:%.*]] = sub i32 [[TMP8]], [[TMP23]]
210; IR-NEXT:    [[TMP26:%.*]] = select i1 [[TMP16]], i32 [[TMP24]], i32 [[TMP25]]
211; IR-NEXT:    [[TMP27:%.*]] = zext i32 [[TMP26]] to i64
212; IR-NEXT:    [[TMP28:%.*]] = mul i64 [[TMP27]], 1000000
213; IR-NEXT:    [[TMP29:%.*]] = trunc i64 [[TMP28]] to i32
214; IR-NEXT:    [[TMP30:%.*]] = lshr i64 [[TMP28]], 32
215; IR-NEXT:    [[TMP31:%.*]] = trunc i64 [[TMP30]] to i32
216; IR-NEXT:    [[TMP32:%.*]] = mul i32 [[TMP31]], [[TMP4]]
217; IR-NEXT:    [[TMP33:%.*]] = sub i32 1000000, [[TMP32]]
218; IR-NEXT:    [[TMP34:%.*]] = icmp uge i32 [[TMP33]], [[TMP4]]
219; IR-NEXT:    [[TMP35:%.*]] = icmp uge i32 1000000, [[TMP32]]
220; IR-NEXT:    [[TMP36:%.*]] = and i1 [[TMP34]], [[TMP35]]
221; IR-NEXT:    [[TMP37:%.*]] = add i32 [[TMP31]], 1
222; IR-NEXT:    [[TMP38:%.*]] = sub i32 [[TMP31]], 1
223; IR-NEXT:    [[TMP39:%.*]] = select i1 [[TMP36]], i32 [[TMP37]], i32 [[TMP31]]
224; IR-NEXT:    [[TMP40:%.*]] = select i1 [[TMP35]], i32 [[TMP39]], i32 [[TMP38]]
225; IR-NEXT:    [[TMP41:%.*]] = xor i32 [[TMP40]], [[TMP2]]
226; IR-NEXT:    [[TMP42:%.*]] = sub i32 [[TMP41]], [[TMP2]]
227; IR-NEXT:    ret i32 [[TMP42]]
228;
229; GCN-LABEL: select_sdiv_lhs_opaque_const1_i32:
230; GCN:       ; %bb.0:
231; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
232; GCN-NEXT:    s_getpc_b64 s[4:5]
233; GCN-NEXT:    s_add_u32 s4, s4, gv@gotpcrel32@lo+4
234; GCN-NEXT:    s_addc_u32 s5, s5, gv@gotpcrel32@hi+4
235; GCN-NEXT:    s_load_dword s4, s[4:5], 0x0
236; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
237; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
238; GCN-NEXT:    s_mov_b32 s6, 0xf4240
239; GCN-NEXT:    s_waitcnt lgkmcnt(0)
240; GCN-NEXT:    v_mov_b32_e32 v1, s4
241; GCN-NEXT:    v_cndmask_b32_e64 v0, v1, 5, vcc
242; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
243; GCN-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
244; GCN-NEXT:    v_xor_b32_e32 v0, v0, v1
245; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
246; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v2
247; GCN-NEXT:    v_mul_f32_e32 v2, 0x4f800000, v2
248; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
249; GCN-NEXT:    v_mul_lo_u32 v3, v2, v0
250; GCN-NEXT:    v_mul_hi_u32 v4, v2, v0
251; GCN-NEXT:    v_sub_u32_e32 v5, vcc, 0, v3
252; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v4
253; GCN-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
254; GCN-NEXT:    v_mul_hi_u32 v3, v3, v2
255; GCN-NEXT:    v_add_u32_e64 v4, s[4:5], v2, v3
256; GCN-NEXT:    v_sub_u32_e64 v2, s[4:5], v2, v3
257; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
258; GCN-NEXT:    v_mul_hi_u32 v2, v2, s6
259; GCN-NEXT:    s_mov_b32 s4, 0xf4241
260; GCN-NEXT:    v_mul_lo_u32 v3, v2, v0
261; GCN-NEXT:    v_add_u32_e32 v4, vcc, 1, v2
262; GCN-NEXT:    v_add_u32_e32 v5, vcc, -1, v2
263; GCN-NEXT:    v_sub_u32_e32 v6, vcc, s6, v3
264; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, s4, v3
265; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v0
266; GCN-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
267; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v4, s[4:5]
268; GCN-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
269; GCN-NEXT:    v_xor_b32_e32 v0, v0, v1
270; GCN-NEXT:    v_sub_u32_e32 v0, vcc, v0, v1
271; GCN-NEXT:    s_setpc_b64 s[30:31]
272  %select = select i1 %cond, i32 5, i32 ptrtoint (i32 addrspace(1)* @gv to i32)
273  %op = sdiv i32 1000000, %select
274  ret i32 %op
275}
276
277define i32 @select_sdiv_rhs_opaque_const0_i32(i1 %cond) {
278; IR-LABEL: @select_sdiv_rhs_opaque_const0_i32(
279; IR-NEXT:    [[SELECT:%.*]] = select i1 [[COND:%.*]], i32 ptrtoint (i32 addrspace(1)* @gv to i32), i32 234234
280; IR-NEXT:    [[OP:%.*]] = sdiv i32 [[SELECT]], 42
281; IR-NEXT:    ret i32 [[OP]]
282;
283; GCN-LABEL: select_sdiv_rhs_opaque_const0_i32:
284; GCN:       ; %bb.0:
285; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
286; GCN-NEXT:    s_getpc_b64 s[4:5]
287; GCN-NEXT:    s_add_u32 s4, s4, gv@gotpcrel32@lo+4
288; GCN-NEXT:    s_addc_u32 s5, s5, gv@gotpcrel32@hi+4
289; GCN-NEXT:    s_load_dword s4, s[4:5], 0x0
290; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
291; GCN-NEXT:    v_mov_b32_e32 v1, 0x392fa
292; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
293; GCN-NEXT:    s_mov_b32 s5, 0x30c30c31
294; GCN-NEXT:    s_waitcnt lgkmcnt(0)
295; GCN-NEXT:    v_mov_b32_e32 v2, s4
296; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
297; GCN-NEXT:    v_mul_hi_i32 v0, v0, s5
298; GCN-NEXT:    v_lshrrev_b32_e32 v1, 31, v0
299; GCN-NEXT:    v_ashrrev_i32_e32 v0, 3, v0
300; GCN-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
301; GCN-NEXT:    s_setpc_b64 s[30:31]
302  %select = select i1 %cond, i32 ptrtoint (i32 addrspace(1)* @gv to i32), i32 234234
303  %op = sdiv i32 %select, 42
304  ret i32 %op
305}
306
307define i32 @select_sdiv_rhs_opaque_const1_i32(i1 %cond) {
308; IR-LABEL: @select_sdiv_rhs_opaque_const1_i32(
309; IR-NEXT:    [[SELECT:%.*]] = select i1 [[COND:%.*]], i32 42000, i32 ptrtoint (i32 addrspace(1)* @gv to i32)
310; IR-NEXT:    [[OP:%.*]] = sdiv i32 [[SELECT]], 42
311; IR-NEXT:    ret i32 [[OP]]
312;
313; GCN-LABEL: select_sdiv_rhs_opaque_const1_i32:
314; GCN:       ; %bb.0:
315; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
316; GCN-NEXT:    s_getpc_b64 s[4:5]
317; GCN-NEXT:    s_add_u32 s4, s4, gv@gotpcrel32@lo+4
318; GCN-NEXT:    s_addc_u32 s5, s5, gv@gotpcrel32@hi+4
319; GCN-NEXT:    s_load_dword s4, s[4:5], 0x0
320; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
321; GCN-NEXT:    v_mov_b32_e32 v1, 0xa410
322; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
323; GCN-NEXT:    s_mov_b32 s5, 0x30c30c31
324; GCN-NEXT:    s_waitcnt lgkmcnt(0)
325; GCN-NEXT:    v_mov_b32_e32 v2, s4
326; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
327; GCN-NEXT:    v_mul_hi_i32 v0, v0, s5
328; GCN-NEXT:    v_lshrrev_b32_e32 v1, 31, v0
329; GCN-NEXT:    v_ashrrev_i32_e32 v0, 3, v0
330; GCN-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
331; GCN-NEXT:    s_setpc_b64 s[30:31]
332  %select = select i1 %cond, i32 42000, i32 ptrtoint (i32 addrspace(1)* @gv to i32)
333  %op = sdiv i32 %select, 42
334  ret i32 %op
335}
336
337define i32 @select_add_lhs_const_i32(i1 %cond) {
338; IR-LABEL: @select_add_lhs_const_i32(
339; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], i32 1000005, i32 1000008
340; IR-NEXT:    ret i32 [[OP]]
341;
342; GCN-LABEL: select_add_lhs_const_i32:
343; GCN:       ; %bb.0:
344; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
345; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
346; GCN-NEXT:    v_mov_b32_e32 v1, 0xf4248
347; GCN-NEXT:    v_mov_b32_e32 v2, 0xf4245
348; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
349; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
350; GCN-NEXT:    s_setpc_b64 s[30:31]
351  %select = select i1 %cond, i32 5, i32 8
352  %op = add i32 1000000, %select
353  ret i32 %op
354}
355
356define float @select_fadd_lhs_const_i32_fmf(i1 %cond) {
357; IR-LABEL: @select_fadd_lhs_const_i32_fmf(
358; IR-NEXT:    [[OP:%.*]] = select nnan nsz i1 [[COND:%.*]], float 3.000000e+00, float 5.000000e+00
359; IR-NEXT:    ret float [[OP]]
360; GCN-LABEL: select_fadd_lhs_const_i32_fmf:
361; GCN:       ; %bb.0:
362; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
363; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
364; GCN-NEXT:    v_mov_b32_e32 v1, 0x40a00000
365; GCN-NEXT:    v_mov_b32_e32 v2, 0x40400000
366; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
367; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
368; GCN-NEXT:    s_setpc_b64 s[30:31]
369  %select = select i1 %cond, float 2.0, float 4.0
370  %op = fadd nnan nsz float 1.0, %select
371  ret float %op
372}
373
374; Make sure we don't try to use mul24 instead
375define i32 @select_mul_lhs_const_i32(i1 %cond) {
376; GCN-LABEL: select_mul_lhs_const_i32:
377; GCN:       ; %bb.0:
378; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
379; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
380; GCN-NEXT:    v_mov_b32_e32 v1, 0x1f40
381; GCN-NEXT:    v_mov_b32_e32 v2, 0x1388
382; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
383; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
384; GCN-NEXT:    s_setpc_b64 s[30:31]
385; IR-LABEL: @select_mul_lhs_const_i32(
386; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], i32 5000, i32 8000
387; IR-NEXT:    ret i32 [[OP]]
388  %select = select i1 %cond, i32 5, i32 8
389  %op = mul i32 1000, %select
390  ret i32 %op
391}
392
393; Make sure we don't try to use mul24 instead
394define i32 @select_mul_rhs_const_i32(i1 %cond) {
395; GCN-LABEL: select_mul_rhs_const_i32:
396; GCN:       ; %bb.0:
397; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
398; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
399; GCN-NEXT:    v_mov_b32_e32 v1, 0x1f40
400; GCN-NEXT:    v_mov_b32_e32 v2, 0x1388
401; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
402; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
403; GCN-NEXT:    s_setpc_b64 s[30:31]
404; IR-LABEL: @select_mul_rhs_const_i32(
405; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], i32 5000, i32 8000
406; IR-NEXT:    ret i32 [[OP]]
407;
408  %select = select i1 %cond, i32 5, i32 8
409  %op = mul i32 %select, 1000
410  ret i32 %op
411}
412
413define amdgpu_kernel void @select_add_lhs_const_i16(i1 %cond) {
414; IR-LABEL: @select_add_lhs_const_i16(
415; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], i16 128, i16 131
416; IR-NEXT:    store i16 [[OP]], i16 addrspace(1)* undef
417; IR-NEXT:    ret void
418
419; GCN-LABEL: select_add_lhs_const_i16:
420; GCN:       ; %bb.0:
421; GCN-NEXT:    s_load_dword s0, s[4:5], 0x0
422; GCN-NEXT:    v_mov_b32_e32 v0, 0x83
423; GCN-NEXT:    v_mov_b32_e32 v1, 0x80
424; GCN-NEXT:    s_waitcnt lgkmcnt(0)
425; GCN-NEXT:    s_and_b32 s0, 1, s0
426; GCN-NEXT:    v_cmp_eq_u32_e64 vcc, s0, 1
427; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
428; GCN-NEXT:    flat_store_short v[0:1], v0
429; GCN-NEXT:    s_endpgm
430;
431  %select = select i1 %cond, i16 5, i16 8
432  %op = add i16 %select, 123
433  store i16 %op, i16 addrspace(1)* undef
434  ret void
435}
436
437define i16 @select_add_trunc_select(i1 %cond) {
438; GCN-LABEL: select_add_trunc_select:
439; GCN:       ; %bb.0:
440; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
441; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
442; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
443; GCN-NEXT:    v_cndmask_b32_e64 v0, 50, 47, vcc
444; GCN-NEXT:    s_setpc_b64 s[30:31]
445; IR-LABEL: @select_add_trunc_select(
446; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], i16 47, i16 50
447; IR-NEXT:    ret i16 [[OP]]
448;
449  %select = select i1 %cond, i32 5, i32 8
450  %trunc = trunc i32 %select to i16
451  %op = add i16 %trunc, 42
452  ret i16 %op
453}
454
455define i32 @select_add_sext_select(i1 %cond) {
456; IR-LABEL: @select_add_sext_select(
457; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], i32 29, i32 50
458; IR-NEXT:    ret i32 [[OP]]
459; GCN-LABEL: select_add_sext_select:
460; GCN:       ; %bb.0:
461; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
462; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
463; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
464; GCN-NEXT:    v_cndmask_b32_e64 v0, 50, 29, vcc
465; GCN-NEXT:    s_setpc_b64 s[30:31]
466  %select = select i1 %cond, i16 -13, i16 8
467  %trunc = sext i16 %select to i32
468  %op = add i32 %trunc, 42
469  ret i32 %op
470}
471
472define i32 @select_add_zext_select(i1 %cond) {
473; IR-LABEL: @select_add_zext_select(
474; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], i32 47, i32 50
475; IR-NEXT:    ret i32 [[OP]]
476
477; GCN-LABEL: select_add_zext_select:
478; GCN:       ; %bb.0:
479; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
480; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
481; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
482; GCN-NEXT:    v_cndmask_b32_e64 v0, 50, 47, vcc
483; GCN-NEXT:    s_setpc_b64 s[30:31]
484  %select = select i1 %cond, i16 5, i16 8
485  %trunc = zext i16 %select to i32
486  %op = add i32 %trunc, 42
487  ret i32 %op
488}
489
490define i32 @select_add_bitcast_select(i1 %cond) {
491; IR-LABEL: @select_add_bitcast_select(
492; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], i32 1065353258, i32 1073741866
493; IR-NEXT:    ret i32 [[OP]]
494;
495; GCN-LABEL: select_add_bitcast_select:
496; GCN:       ; %bb.0:
497; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
498; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
499; GCN-NEXT:    v_mov_b32_e32 v1, 0x4000002a
500; GCN-NEXT:    v_mov_b32_e32 v2, 0x3f80002a
501; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
502; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
503; GCN-NEXT:    s_setpc_b64 s[30:31]
504  %select = select i1 %cond, float 1.0, float 2.0
505  %trunc = bitcast float %select to i32
506  %op = add i32 %trunc, 42
507  ret i32 %op
508}
509
510; If we fold through a cast, we need to ensure it doesn't have
511; multiple uses.
512define <2 x half> @multi_use_cast_regression(i1 %cond) {
513; IR-LABEL: @multi_use_cast_regression(
514; IR-NEXT:    [[SELECT:%.*]] = select i1 [[COND:%.*]], half 0xH3C00, half 0xH0000
515; IR-NEXT:    [[FPEXT:%.*]] = fpext half [[SELECT]] to float
516; IR-NEXT:    [[FSUB:%.*]] = fsub nsz float 1.000000e+00, [[FPEXT]]
517; IR-NEXT:    [[CALL:%.*]] = call nsz <2 x half> @llvm.amdgcn.cvt.pkrtz(float [[FPEXT]], float [[FSUB]])
518; IR-NEXT:    ret <2 x half> [[CALL]]
519;
520; GCN-LABEL: multi_use_cast_regression:
521; GCN:       ; %bb.0:
522; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
523; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
524; GCN-NEXT:    v_mov_b32_e32 v1, 0x3c00
525; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
526; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
527; GCN-NEXT:    v_cvt_f32_f16_e32 v0, v0
528; GCN-NEXT:    v_sub_f32_e32 v1, 1.0, v0
529; GCN-NEXT:    v_cvt_pkrtz_f16_f32 v0, v0, v1
530; GCN-NEXT:    s_setpc_b64 s[30:31]
531  %select = select i1 %cond, half 1.000000e+00, half 0.000000e+00
532  %fpext = fpext half %select to float
533  %fsub = fsub nsz float 1.0, %fpext
534  %call = call nsz <2 x half> @llvm.amdgcn.cvt.pkrtz(float %fpext, float %fsub) #3
535  ret <2 x half> %call
536}
537
538declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #0
539
540attributes #0 = { nounwind readnone speculatable }
541