1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -amdgpu-codegenprepare %s | FileCheck -check-prefix=IR %s
3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s
4
5define i32 @select_sdiv_lhs_const_i32(i1 %cond) {
6; IR-LABEL: @select_sdiv_lhs_const_i32(
7; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], i32 200000, i32 125000
8; IR-NEXT:    ret i32 [[OP]]
9;
10; GCN-LABEL: select_sdiv_lhs_const_i32:
11; GCN:       ; %bb.0:
12; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
13; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
14; GCN-NEXT:    v_mov_b32_e32 v1, 0x1e848
15; GCN-NEXT:    v_mov_b32_e32 v2, 0x30d40
16; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
17; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
18; GCN-NEXT:    s_setpc_b64 s[30:31]
19  %select = select i1 %cond, i32 5, i32 8
20  %op = sdiv i32 1000000, %select
21  ret i32 %op
22}
23
24define i32 @select_sdiv_rhs_const_i32(i1 %cond) {
25; IR-LABEL: @select_sdiv_rhs_const_i32(
26; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], i32 1000, i32 10000
27; IR-NEXT:    ret i32 [[OP]]
28;
29; GCN-LABEL: select_sdiv_rhs_const_i32:
30; GCN:       ; %bb.0:
31; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
32; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
33; GCN-NEXT:    v_mov_b32_e32 v1, 0x2710
34; GCN-NEXT:    v_mov_b32_e32 v2, 0x3e8
35; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
36; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
37; GCN-NEXT:    s_setpc_b64 s[30:31]
38  %select = select i1 %cond, i32 42000, i32 420000
39  %op = sdiv i32 %select, 42
40  ret i32 %op
41}
42
43define <2 x i32> @select_sdiv_lhs_const_v2i32(i1 %cond) {
44; IR-LABEL: @select_sdiv_lhs_const_v2i32(
45; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], <2 x i32> <i32 666, i32 undef>, <2 x i32> <i32 555, i32 1428>
46; IR-NEXT:    ret <2 x i32> [[OP]]
47;
48; GCN-LABEL: select_sdiv_lhs_const_v2i32:
49; GCN:       ; %bb.0:
50; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
51; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
52; GCN-NEXT:    v_mov_b32_e32 v1, 0x22b
53; GCN-NEXT:    v_mov_b32_e32 v2, 0x29a
54; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
55; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
56; GCN-NEXT:    v_mov_b32_e32 v1, 0x594
57; GCN-NEXT:    s_setpc_b64 s[30:31]
58  %select = select i1 %cond, <2 x i32> <i32 5, i32 undef>, <2 x i32> <i32 6, i32 7>
59  %op = sdiv <2 x i32> <i32 3333, i32 9999>, %select
60  ret <2 x i32> %op
61}
62
63define <2 x i32> @select_sdiv_rhs_const_v2i32(i1 %cond) {
64; IR-LABEL: @select_sdiv_rhs_const_v2i32(
65; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], <2 x i32> <i32 198621, i32 20855308>, <2 x i32> <i32 222748, i32 2338858>
66; IR-NEXT:    ret <2 x i32> [[OP]]
67;
68; GCN-LABEL: select_sdiv_rhs_const_v2i32:
69; GCN:       ; %bb.0:
70; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
71; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
72; GCN-NEXT:    v_mov_b32_e32 v1, 0x3661c
73; GCN-NEXT:    v_mov_b32_e32 v2, 0x307dd
74; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
75; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
76; GCN-NEXT:    v_mov_b32_e32 v1, 0x23b02a
77; GCN-NEXT:    v_mov_b32_e32 v2, 0x13e3a0c
78; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
79; GCN-NEXT:    s_setpc_b64 s[30:31]
80  %select = select i1 %cond, <2 x i32> <i32 8342123, i32 834212353>, <2 x i32> <i32 9355456, i32 93554321>
81  %op = sdiv <2 x i32> %select, <i32 42, i32 40>
82  ret <2 x i32> %op
83}
84
85@gv = external addrspace(1) global i32
86
87define i32 @select_sdiv_lhs_opaque_const0_i32(i1 %cond) {
88; IR-LABEL: @select_sdiv_lhs_opaque_const0_i32(
89; IR-NEXT:    [[SELECT:%.*]] = select i1 [[COND:%.*]], i32 ptrtoint (i32 addrspace(1)* @gv to i32), i32 5
90; IR-NEXT:    [[TMP1:%.*]] = ashr i32 [[SELECT]], 31
91; IR-NEXT:    [[TMP2:%.*]] = xor i32 0, [[TMP1]]
92; IR-NEXT:    [[TMP3:%.*]] = add i32 [[SELECT]], [[TMP1]]
93; IR-NEXT:    [[TMP4:%.*]] = xor i32 [[TMP3]], [[TMP1]]
94; IR-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP4]] to float
95; IR-NEXT:    [[TMP6:%.*]] = fdiv fast float 1.000000e+00, [[TMP5]]
96; IR-NEXT:    [[TMP7:%.*]] = fmul fast float [[TMP6]], 0x41F0000000000000
97; IR-NEXT:    [[TMP8:%.*]] = fptoui float [[TMP7]] to i32
98; IR-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
99; IR-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP4]] to i64
100; IR-NEXT:    [[TMP11:%.*]] = mul i64 [[TMP9]], [[TMP10]]
101; IR-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
102; IR-NEXT:    [[TMP13:%.*]] = lshr i64 [[TMP11]], 32
103; IR-NEXT:    [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32
104; IR-NEXT:    [[TMP15:%.*]] = sub i32 0, [[TMP12]]
105; IR-NEXT:    [[TMP16:%.*]] = icmp eq i32 [[TMP14]], 0
106; IR-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP15]], i32 [[TMP12]]
107; IR-NEXT:    [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
108; IR-NEXT:    [[TMP19:%.*]] = zext i32 [[TMP8]] to i64
109; IR-NEXT:    [[TMP20:%.*]] = mul i64 [[TMP18]], [[TMP19]]
110; IR-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
111; IR-NEXT:    [[TMP22:%.*]] = lshr i64 [[TMP20]], 32
112; IR-NEXT:    [[TMP23:%.*]] = trunc i64 [[TMP22]] to i32
113; IR-NEXT:    [[TMP24:%.*]] = add i32 [[TMP8]], [[TMP23]]
114; IR-NEXT:    [[TMP25:%.*]] = sub i32 [[TMP8]], [[TMP23]]
115; IR-NEXT:    [[TMP26:%.*]] = select i1 [[TMP16]], i32 [[TMP24]], i32 [[TMP25]]
116; IR-NEXT:    [[TMP27:%.*]] = zext i32 [[TMP26]] to i64
117; IR-NEXT:    [[TMP28:%.*]] = mul i64 [[TMP27]], 1000000
118; IR-NEXT:    [[TMP29:%.*]] = trunc i64 [[TMP28]] to i32
119; IR-NEXT:    [[TMP30:%.*]] = lshr i64 [[TMP28]], 32
120; IR-NEXT:    [[TMP31:%.*]] = trunc i64 [[TMP30]] to i32
121; IR-NEXT:    [[TMP32:%.*]] = mul i32 [[TMP31]], [[TMP4]]
122; IR-NEXT:    [[TMP33:%.*]] = sub i32 1000000, [[TMP32]]
123; IR-NEXT:    [[TMP34:%.*]] = icmp uge i32 [[TMP33]], [[TMP4]]
124; IR-NEXT:    [[TMP35:%.*]] = select i1 [[TMP34]], i32 -1, i32 0
125; IR-NEXT:    [[TMP36:%.*]] = icmp uge i32 1000000, [[TMP32]]
126; IR-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i32 -1, i32 0
127; IR-NEXT:    [[TMP38:%.*]] = and i32 [[TMP35]], [[TMP37]]
128; IR-NEXT:    [[TMP39:%.*]] = icmp eq i32 [[TMP38]], 0
129; IR-NEXT:    [[TMP40:%.*]] = add i32 [[TMP31]], 1
130; IR-NEXT:    [[TMP41:%.*]] = sub i32 [[TMP31]], 1
131; IR-NEXT:    [[TMP42:%.*]] = select i1 [[TMP39]], i32 [[TMP31]], i32 [[TMP40]]
132; IR-NEXT:    [[TMP43:%.*]] = select i1 [[TMP36]], i32 [[TMP42]], i32 [[TMP41]]
133; IR-NEXT:    [[TMP44:%.*]] = xor i32 [[TMP43]], [[TMP2]]
134; IR-NEXT:    [[TMP45:%.*]] = sub i32 [[TMP44]], [[TMP2]]
135; IR-NEXT:    ret i32 [[TMP45]]
136;
137; GCN-LABEL: select_sdiv_lhs_opaque_const0_i32:
138; GCN:       ; %bb.0:
139; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
140; GCN-NEXT:    s_getpc_b64 s[4:5]
141; GCN-NEXT:    s_add_u32 s4, s4, gv@gotpcrel32@lo+4
142; GCN-NEXT:    s_addc_u32 s5, s5, gv@gotpcrel32@hi+4
143; GCN-NEXT:    s_load_dword s4, s[4:5], 0x0
144; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
145; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
146; GCN-NEXT:    s_mov_b32 s6, 0xf4240
147; GCN-NEXT:    s_waitcnt lgkmcnt(0)
148; GCN-NEXT:    v_mov_b32_e32 v1, s4
149; GCN-NEXT:    v_cndmask_b32_e32 v0, 5, v1, vcc
150; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
151; GCN-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
152; GCN-NEXT:    v_xor_b32_e32 v0, v0, v1
153; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
154; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v2
155; GCN-NEXT:    v_mul_f32_e32 v2, 0x4f800000, v2
156; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
157; GCN-NEXT:    v_mul_lo_u32 v3, v2, v0
158; GCN-NEXT:    v_mul_hi_u32 v4, v2, v0
159; GCN-NEXT:    v_sub_u32_e32 v5, vcc, 0, v3
160; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v4
161; GCN-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
162; GCN-NEXT:    v_mul_hi_u32 v3, v3, v2
163; GCN-NEXT:    v_add_u32_e64 v4, s[4:5], v2, v3
164; GCN-NEXT:    v_sub_u32_e64 v2, s[4:5], v2, v3
165; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
166; GCN-NEXT:    v_mul_hi_u32 v2, v2, s6
167; GCN-NEXT:    s_mov_b32 s4, 0xf4241
168; GCN-NEXT:    v_mul_lo_u32 v3, v2, v0
169; GCN-NEXT:    v_add_u32_e32 v4, vcc, 1, v2
170; GCN-NEXT:    v_add_u32_e32 v5, vcc, -1, v2
171; GCN-NEXT:    v_sub_u32_e32 v6, vcc, s6, v3
172; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, s4, v3
173; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v0
174; GCN-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
175; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v4, s[4:5]
176; GCN-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
177; GCN-NEXT:    v_xor_b32_e32 v0, v0, v1
178; GCN-NEXT:    v_sub_u32_e32 v0, vcc, v0, v1
179; GCN-NEXT:    s_setpc_b64 s[30:31]
180  %select = select i1 %cond, i32 ptrtoint (i32 addrspace(1)* @gv to i32), i32 5
181  %op = sdiv i32 1000000, %select
182  ret i32 %op
183}
184
185define i32 @select_sdiv_lhs_opaque_const1_i32(i1 %cond) {
186; IR-LABEL: @select_sdiv_lhs_opaque_const1_i32(
187; IR-NEXT:    [[SELECT:%.*]] = select i1 [[COND:%.*]], i32 5, i32 ptrtoint (i32 addrspace(1)* @gv to i32)
188; IR-NEXT:    [[TMP1:%.*]] = ashr i32 [[SELECT]], 31
189; IR-NEXT:    [[TMP2:%.*]] = xor i32 0, [[TMP1]]
190; IR-NEXT:    [[TMP3:%.*]] = add i32 [[SELECT]], [[TMP1]]
191; IR-NEXT:    [[TMP4:%.*]] = xor i32 [[TMP3]], [[TMP1]]
192; IR-NEXT:    [[TMP5:%.*]] = uitofp i32 [[TMP4]] to float
193; IR-NEXT:    [[TMP6:%.*]] = fdiv fast float 1.000000e+00, [[TMP5]]
194; IR-NEXT:    [[TMP7:%.*]] = fmul fast float [[TMP6]], 0x41F0000000000000
195; IR-NEXT:    [[TMP8:%.*]] = fptoui float [[TMP7]] to i32
196; IR-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
197; IR-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP4]] to i64
198; IR-NEXT:    [[TMP11:%.*]] = mul i64 [[TMP9]], [[TMP10]]
199; IR-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
200; IR-NEXT:    [[TMP13:%.*]] = lshr i64 [[TMP11]], 32
201; IR-NEXT:    [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32
202; IR-NEXT:    [[TMP15:%.*]] = sub i32 0, [[TMP12]]
203; IR-NEXT:    [[TMP16:%.*]] = icmp eq i32 [[TMP14]], 0
204; IR-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP15]], i32 [[TMP12]]
205; IR-NEXT:    [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
206; IR-NEXT:    [[TMP19:%.*]] = zext i32 [[TMP8]] to i64
207; IR-NEXT:    [[TMP20:%.*]] = mul i64 [[TMP18]], [[TMP19]]
208; IR-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
209; IR-NEXT:    [[TMP22:%.*]] = lshr i64 [[TMP20]], 32
210; IR-NEXT:    [[TMP23:%.*]] = trunc i64 [[TMP22]] to i32
211; IR-NEXT:    [[TMP24:%.*]] = add i32 [[TMP8]], [[TMP23]]
212; IR-NEXT:    [[TMP25:%.*]] = sub i32 [[TMP8]], [[TMP23]]
213; IR-NEXT:    [[TMP26:%.*]] = select i1 [[TMP16]], i32 [[TMP24]], i32 [[TMP25]]
214; IR-NEXT:    [[TMP27:%.*]] = zext i32 [[TMP26]] to i64
215; IR-NEXT:    [[TMP28:%.*]] = mul i64 [[TMP27]], 1000000
216; IR-NEXT:    [[TMP29:%.*]] = trunc i64 [[TMP28]] to i32
217; IR-NEXT:    [[TMP30:%.*]] = lshr i64 [[TMP28]], 32
218; IR-NEXT:    [[TMP31:%.*]] = trunc i64 [[TMP30]] to i32
219; IR-NEXT:    [[TMP32:%.*]] = mul i32 [[TMP31]], [[TMP4]]
220; IR-NEXT:    [[TMP33:%.*]] = sub i32 1000000, [[TMP32]]
221; IR-NEXT:    [[TMP34:%.*]] = icmp uge i32 [[TMP33]], [[TMP4]]
222; IR-NEXT:    [[TMP35:%.*]] = select i1 [[TMP34]], i32 -1, i32 0
223; IR-NEXT:    [[TMP36:%.*]] = icmp uge i32 1000000, [[TMP32]]
224; IR-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i32 -1, i32 0
225; IR-NEXT:    [[TMP38:%.*]] = and i32 [[TMP35]], [[TMP37]]
226; IR-NEXT:    [[TMP39:%.*]] = icmp eq i32 [[TMP38]], 0
227; IR-NEXT:    [[TMP40:%.*]] = add i32 [[TMP31]], 1
228; IR-NEXT:    [[TMP41:%.*]] = sub i32 [[TMP31]], 1
229; IR-NEXT:    [[TMP42:%.*]] = select i1 [[TMP39]], i32 [[TMP31]], i32 [[TMP40]]
230; IR-NEXT:    [[TMP43:%.*]] = select i1 [[TMP36]], i32 [[TMP42]], i32 [[TMP41]]
231; IR-NEXT:    [[TMP44:%.*]] = xor i32 [[TMP43]], [[TMP2]]
232; IR-NEXT:    [[TMP45:%.*]] = sub i32 [[TMP44]], [[TMP2]]
233; IR-NEXT:    ret i32 [[TMP45]]
234;
235; GCN-LABEL: select_sdiv_lhs_opaque_const1_i32:
236; GCN:       ; %bb.0:
237; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
238; GCN-NEXT:    s_getpc_b64 s[4:5]
239; GCN-NEXT:    s_add_u32 s4, s4, gv@gotpcrel32@lo+4
240; GCN-NEXT:    s_addc_u32 s5, s5, gv@gotpcrel32@hi+4
241; GCN-NEXT:    s_load_dword s4, s[4:5], 0x0
242; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
243; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
244; GCN-NEXT:    s_mov_b32 s6, 0xf4240
245; GCN-NEXT:    s_waitcnt lgkmcnt(0)
246; GCN-NEXT:    v_mov_b32_e32 v1, s4
247; GCN-NEXT:    v_cndmask_b32_e64 v0, v1, 5, vcc
248; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
249; GCN-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
250; GCN-NEXT:    v_xor_b32_e32 v0, v0, v1
251; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
252; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v2
253; GCN-NEXT:    v_mul_f32_e32 v2, 0x4f800000, v2
254; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
255; GCN-NEXT:    v_mul_lo_u32 v3, v2, v0
256; GCN-NEXT:    v_mul_hi_u32 v4, v2, v0
257; GCN-NEXT:    v_sub_u32_e32 v5, vcc, 0, v3
258; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v4
259; GCN-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
260; GCN-NEXT:    v_mul_hi_u32 v3, v3, v2
261; GCN-NEXT:    v_add_u32_e64 v4, s[4:5], v2, v3
262; GCN-NEXT:    v_sub_u32_e64 v2, s[4:5], v2, v3
263; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
264; GCN-NEXT:    v_mul_hi_u32 v2, v2, s6
265; GCN-NEXT:    s_mov_b32 s4, 0xf4241
266; GCN-NEXT:    v_mul_lo_u32 v3, v2, v0
267; GCN-NEXT:    v_add_u32_e32 v4, vcc, 1, v2
268; GCN-NEXT:    v_add_u32_e32 v5, vcc, -1, v2
269; GCN-NEXT:    v_sub_u32_e32 v6, vcc, s6, v3
270; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, s4, v3
271; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v0
272; GCN-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
273; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v4, s[4:5]
274; GCN-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
275; GCN-NEXT:    v_xor_b32_e32 v0, v0, v1
276; GCN-NEXT:    v_sub_u32_e32 v0, vcc, v0, v1
277; GCN-NEXT:    s_setpc_b64 s[30:31]
278  %select = select i1 %cond, i32 5, i32 ptrtoint (i32 addrspace(1)* @gv to i32)
279  %op = sdiv i32 1000000, %select
280  ret i32 %op
281}
282
283define i32 @select_sdiv_rhs_opaque_const0_i32(i1 %cond) {
284; IR-LABEL: @select_sdiv_rhs_opaque_const0_i32(
285; IR-NEXT:    [[SELECT:%.*]] = select i1 [[COND:%.*]], i32 ptrtoint (i32 addrspace(1)* @gv to i32), i32 234234
286; IR-NEXT:    [[OP:%.*]] = sdiv i32 [[SELECT]], 42
287; IR-NEXT:    ret i32 [[OP]]
288;
289; GCN-LABEL: select_sdiv_rhs_opaque_const0_i32:
290; GCN:       ; %bb.0:
291; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
292; GCN-NEXT:    s_getpc_b64 s[4:5]
293; GCN-NEXT:    s_add_u32 s4, s4, gv@gotpcrel32@lo+4
294; GCN-NEXT:    s_addc_u32 s5, s5, gv@gotpcrel32@hi+4
295; GCN-NEXT:    s_load_dword s4, s[4:5], 0x0
296; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
297; GCN-NEXT:    v_mov_b32_e32 v1, 0x392fa
298; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
299; GCN-NEXT:    s_mov_b32 s5, 0x30c30c31
300; GCN-NEXT:    s_waitcnt lgkmcnt(0)
301; GCN-NEXT:    v_mov_b32_e32 v2, s4
302; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
303; GCN-NEXT:    v_mul_hi_i32 v0, v0, s5
304; GCN-NEXT:    v_lshrrev_b32_e32 v1, 31, v0
305; GCN-NEXT:    v_ashrrev_i32_e32 v0, 3, v0
306; GCN-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
307; GCN-NEXT:    s_setpc_b64 s[30:31]
308  %select = select i1 %cond, i32 ptrtoint (i32 addrspace(1)* @gv to i32), i32 234234
309  %op = sdiv i32 %select, 42
310  ret i32 %op
311}
312
313define i32 @select_sdiv_rhs_opaque_const1_i32(i1 %cond) {
314; IR-LABEL: @select_sdiv_rhs_opaque_const1_i32(
315; IR-NEXT:    [[SELECT:%.*]] = select i1 [[COND:%.*]], i32 42000, i32 ptrtoint (i32 addrspace(1)* @gv to i32)
316; IR-NEXT:    [[OP:%.*]] = sdiv i32 [[SELECT]], 42
317; IR-NEXT:    ret i32 [[OP]]
318;
319; GCN-LABEL: select_sdiv_rhs_opaque_const1_i32:
320; GCN:       ; %bb.0:
321; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
322; GCN-NEXT:    s_getpc_b64 s[4:5]
323; GCN-NEXT:    s_add_u32 s4, s4, gv@gotpcrel32@lo+4
324; GCN-NEXT:    s_addc_u32 s5, s5, gv@gotpcrel32@hi+4
325; GCN-NEXT:    s_load_dword s4, s[4:5], 0x0
326; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
327; GCN-NEXT:    v_mov_b32_e32 v1, 0xa410
328; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
329; GCN-NEXT:    s_mov_b32 s5, 0x30c30c31
330; GCN-NEXT:    s_waitcnt lgkmcnt(0)
331; GCN-NEXT:    v_mov_b32_e32 v2, s4
332; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
333; GCN-NEXT:    v_mul_hi_i32 v0, v0, s5
334; GCN-NEXT:    v_lshrrev_b32_e32 v1, 31, v0
335; GCN-NEXT:    v_ashrrev_i32_e32 v0, 3, v0
336; GCN-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
337; GCN-NEXT:    s_setpc_b64 s[30:31]
338  %select = select i1 %cond, i32 42000, i32 ptrtoint (i32 addrspace(1)* @gv to i32)
339  %op = sdiv i32 %select, 42
340  ret i32 %op
341}
342
343define i32 @select_add_lhs_const_i32(i1 %cond) {
344; IR-LABEL: @select_add_lhs_const_i32(
345; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], i32 1000005, i32 1000008
346; IR-NEXT:    ret i32 [[OP]]
347;
348; GCN-LABEL: select_add_lhs_const_i32:
349; GCN:       ; %bb.0:
350; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
351; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
352; GCN-NEXT:    v_mov_b32_e32 v1, 0xf4248
353; GCN-NEXT:    v_mov_b32_e32 v2, 0xf4245
354; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
355; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
356; GCN-NEXT:    s_setpc_b64 s[30:31]
357  %select = select i1 %cond, i32 5, i32 8
358  %op = add i32 1000000, %select
359  ret i32 %op
360}
361
362define float @select_fadd_lhs_const_i32_fmf(i1 %cond) {
363; IR-LABEL: @select_fadd_lhs_const_i32_fmf(
364; IR-NEXT:    [[OP:%.*]] = select nnan nsz i1 [[COND:%.*]], float 3.000000e+00, float 5.000000e+00
365; IR-NEXT:    ret float [[OP]]
366; GCN-LABEL: select_fadd_lhs_const_i32_fmf:
367; GCN:       ; %bb.0:
368; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
369; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
370; GCN-NEXT:    v_mov_b32_e32 v1, 0x40a00000
371; GCN-NEXT:    v_mov_b32_e32 v2, 0x40400000
372; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
373; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
374; GCN-NEXT:    s_setpc_b64 s[30:31]
375  %select = select i1 %cond, float 2.0, float 4.0
376  %op = fadd nnan nsz float 1.0, %select
377  ret float %op
378}
379
380; Make sure we don't try to use mul24 instead
381define i32 @select_mul_lhs_const_i32(i1 %cond) {
382; GCN-LABEL: select_mul_lhs_const_i32:
383; GCN:       ; %bb.0:
384; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
385; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
386; GCN-NEXT:    v_mov_b32_e32 v1, 0x1f40
387; GCN-NEXT:    v_mov_b32_e32 v2, 0x1388
388; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
389; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
390; GCN-NEXT:    s_setpc_b64 s[30:31]
391; IR-LABEL: @select_mul_lhs_const_i32(
392; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], i32 5000, i32 8000
393; IR-NEXT:    ret i32 [[OP]]
394  %select = select i1 %cond, i32 5, i32 8
395  %op = mul i32 1000, %select
396  ret i32 %op
397}
398
399; Make sure we don't try to use mul24 instead
400define i32 @select_mul_rhs_const_i32(i1 %cond) {
401; GCN-LABEL: select_mul_rhs_const_i32:
402; GCN:       ; %bb.0:
403; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
404; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
405; GCN-NEXT:    v_mov_b32_e32 v1, 0x1f40
406; GCN-NEXT:    v_mov_b32_e32 v2, 0x1388
407; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
408; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
409; GCN-NEXT:    s_setpc_b64 s[30:31]
410; IR-LABEL: @select_mul_rhs_const_i32(
411; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], i32 5000, i32 8000
412; IR-NEXT:    ret i32 [[OP]]
413;
414  %select = select i1 %cond, i32 5, i32 8
415  %op = mul i32 %select, 1000
416  ret i32 %op
417}
418
419define amdgpu_kernel void @select_add_lhs_const_i16(i1 %cond) {
420; IR-LABEL: @select_add_lhs_const_i16(
421; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], i16 128, i16 131
422; IR-NEXT:    store i16 [[OP]], i16 addrspace(1)* undef
423; IR-NEXT:    ret void
424
425; GCN-LABEL: select_add_lhs_const_i16:
426; GCN:       ; %bb.0:
427; GCN-NEXT:    s_load_dword s0, s[4:5], 0x0
428; GCN-NEXT:    v_mov_b32_e32 v0, 0x83
429; GCN-NEXT:    v_mov_b32_e32 v1, 0x80
430; GCN-NEXT:    s_waitcnt lgkmcnt(0)
431; GCN-NEXT:    s_and_b32 s0, 1, s0
432; GCN-NEXT:    v_cmp_eq_u32_e64 vcc, s0, 1
433; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
434; GCN-NEXT:    flat_store_short v[0:1], v0
435; GCN-NEXT:    s_endpgm
436;
437  %select = select i1 %cond, i16 5, i16 8
438  %op = add i16 %select, 123
439  store i16 %op, i16 addrspace(1)* undef
440  ret void
441}
442
443define i16 @select_add_trunc_select(i1 %cond) {
444; GCN-LABEL: select_add_trunc_select:
445; GCN:       ; %bb.0:
446; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
447; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
448; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
449; GCN-NEXT:    v_cndmask_b32_e64 v0, 50, 47, vcc
450; GCN-NEXT:    s_setpc_b64 s[30:31]
451; IR-LABEL: @select_add_trunc_select(
452; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], i16 47, i16 50
453; IR-NEXT:    ret i16 [[OP]]
454;
455  %select = select i1 %cond, i32 5, i32 8
456  %trunc = trunc i32 %select to i16
457  %op = add i16 %trunc, 42
458  ret i16 %op
459}
460
461define i32 @select_add_sext_select(i1 %cond) {
462; IR-LABEL: @select_add_sext_select(
463; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], i32 29, i32 50
464; IR-NEXT:    ret i32 [[OP]]
465; GCN-LABEL: select_add_sext_select:
466; GCN:       ; %bb.0:
467; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
468; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
469; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
470; GCN-NEXT:    v_cndmask_b32_e64 v0, 50, 29, vcc
471; GCN-NEXT:    s_setpc_b64 s[30:31]
472  %select = select i1 %cond, i16 -13, i16 8
473  %trunc = sext i16 %select to i32
474  %op = add i32 %trunc, 42
475  ret i32 %op
476}
477
478define i32 @select_add_zext_select(i1 %cond) {
479; IR-LABEL: @select_add_zext_select(
480; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], i32 47, i32 50
481; IR-NEXT:    ret i32 [[OP]]
482
483; GCN-LABEL: select_add_zext_select:
484; GCN:       ; %bb.0:
485; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
486; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
487; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
488; GCN-NEXT:    v_cndmask_b32_e64 v0, 50, 47, vcc
489; GCN-NEXT:    s_setpc_b64 s[30:31]
490  %select = select i1 %cond, i16 5, i16 8
491  %trunc = zext i16 %select to i32
492  %op = add i32 %trunc, 42
493  ret i32 %op
494}
495
496define i32 @select_add_bitcast_select(i1 %cond) {
497; IR-LABEL: @select_add_bitcast_select(
498; IR-NEXT:    [[OP:%.*]] = select i1 [[COND:%.*]], i32 1065353258, i32 1073741866
499; IR-NEXT:    ret i32 [[OP]]
500;
501; GCN-LABEL: select_add_bitcast_select:
502; GCN:       ; %bb.0:
503; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
504; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
505; GCN-NEXT:    v_mov_b32_e32 v1, 0x4000002a
506; GCN-NEXT:    v_mov_b32_e32 v2, 0x3f80002a
507; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
508; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
509; GCN-NEXT:    s_setpc_b64 s[30:31]
510  %select = select i1 %cond, float 1.0, float 2.0
511  %trunc = bitcast float %select to i32
512  %op = add i32 %trunc, 42
513  ret i32 %op
514}
515
516; If we fold through a cast, we need to ensure it doesn't have
517; multiple uses.
518define <2 x half> @multi_use_cast_regression(i1 %cond) {
519; IR-LABEL: @multi_use_cast_regression(
520; IR-NEXT:    [[SELECT:%.*]] = select i1 [[COND:%.*]], half 0xH3C00, half 0xH0000
521; IR-NEXT:    [[FPEXT:%.*]] = fpext half [[SELECT]] to float
522; IR-NEXT:    [[FSUB:%.*]] = fsub nsz float 1.000000e+00, [[FPEXT]]
523; IR-NEXT:    [[CALL:%.*]] = call nsz <2 x half> @llvm.amdgcn.cvt.pkrtz(float [[FPEXT]], float [[FSUB]])
524; IR-NEXT:    ret <2 x half> [[CALL]]
525;
526; GCN-LABEL: multi_use_cast_regression:
527; GCN:       ; %bb.0:
528; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
529; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
530; GCN-NEXT:    v_mov_b32_e32 v1, 0x3c00
531; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
532; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
533; GCN-NEXT:    v_cvt_f32_f16_e32 v0, v0
534; GCN-NEXT:    v_sub_f32_e32 v1, 1.0, v0
535; GCN-NEXT:    v_cvt_pkrtz_f16_f32 v0, v0, v1
536; GCN-NEXT:    s_setpc_b64 s[30:31]
537  %select = select i1 %cond, half 1.000000e+00, half 0.000000e+00
538  %fpext = fpext half %select to float
539  %fsub = fsub nsz float 1.0, %fpext
540  %call = call nsz <2 x half> @llvm.amdgcn.cvt.pkrtz(float %fpext, float %fsub) #3
541  ret <2 x half> %call
542}
543
544declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #0
545
546attributes #0 = { nounwind readnone speculatable }
547