1; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=CI %s 2; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=GFX9 %s 3 4; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast: 5; HSA: enable_sgpr_private_segment_buffer = 1 6; HSA: enable_sgpr_dispatch_ptr = 0 7; CI: enable_sgpr_queue_ptr = 1 8; GFX9: enable_sgpr_queue_ptr = 0 9 10; CI-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}} 11; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10{{$}} 12; CI-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]] 13; CI-DAG: v_cmp_ne_u32_e64 vcc, [[PTR]], -1 14; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc 15; CI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] 16; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] 17 18; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 19; GFX9-DAG: s_load_dword [[PTR:s[0-9]+]], s[4:5], 0x0{{$}} 20; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16) 21; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16 22; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_SHARED_BASE]] 23 24; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_shared_base 25; GFX9: v_cmp_ne_u32_e64 vcc, [[PTR]], -1 26; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc 27; GFX9-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] 28; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] 29 30; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]] 31 32; At most 2 digits. Make sure src_shared_base is not counted as a high 33; number SGPR. 34 35; CI: NumSgprs: {{[0-9][0-9]+}} 36; GFX9: NumSgprs: {{[0-9]+}} 37define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #0 { 38 %stof = addrspacecast i32 addrspace(3)* %ptr to i32* 39 store volatile i32 7, i32* %stof 40 ret void 41} 42 43; Test handling inside a non-kernel 44; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast_func: 45; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10{{$}} 46; CI-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]] 47; CI-DAG: v_cmp_ne_u32_e32 vcc, -1, v0 48; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc 49; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, v0 50 51; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 52; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16) 53; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16 54; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_SHARED_BASE]] 55 56; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_shared_base 57; GFX9-DAG: v_cmp_ne_u32_e32 vcc, -1, v0 58; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, v0, vcc 59; GFX9-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc 60 61; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]] 62define void @use_group_to_flat_addrspacecast_func(i32 addrspace(3)* %ptr) #0 { 63 %stof = addrspacecast i32 addrspace(3)* %ptr to i32* 64 store volatile i32 7, i32* %stof 65 ret void 66} 67 68; HSA-LABEL: {{^}}use_private_to_flat_addrspacecast: 69; HSA: enable_sgpr_private_segment_buffer = 1 70; HSA: enable_sgpr_dispatch_ptr = 0 71; CI: enable_sgpr_queue_ptr = 1 72; GFX9: enable_sgpr_queue_ptr = 0 73 74; CI-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}} 75; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11{{$}} 76; CI-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]] 77 78; CI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 79; CI-DAG: v_cmp_ne_u32_e64 vcc, [[PTR]], -1 80; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc 81; CI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] 82; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] 83 84; GFX9-DAG: s_load_dword [[PTR:s[0-9]+]], s[4:5], 0x0{{$}} 85; GFX9-DAG: s_getreg_b32 [[SSRC_PRIVATE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16) 86; GFX9-DAG: s_lshl_b32 [[SSRC_PRIVATE_BASE:s[0-9]+]], [[SSRC_PRIVATE]], 16 87; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_PRIVATE_BASE]] 88 89; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_private_base 90 91; GFX9-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 92; GFX9: v_cmp_ne_u32_e64 vcc, [[PTR]], -1 93; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc 94; GFX9: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] 95; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] 96 97; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]] 98 99; CI: NumSgprs: {{[0-9][0-9]+}} 100; GFX9: NumSgprs: {{[0-9]+}} 101define amdgpu_kernel void @use_private_to_flat_addrspacecast(i32 addrspace(5)* %ptr) #0 { 102 %stof = addrspacecast i32 addrspace(5)* %ptr to i32* 103 store volatile i32 7, i32* %stof 104 ret void 105} 106 107; no-op 108; HSA-LABEL: {{^}}use_global_to_flat_addrspacecast: 109; HSA: enable_sgpr_queue_ptr = 0 110 111; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}} 112; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] 113; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] 114; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 115; HSA: flat_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]] 116define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #0 { 117 %stof = addrspacecast i32 addrspace(1)* %ptr to i32* 118 store volatile i32 7, i32* %stof 119 ret void 120} 121 122; no-op 123; HSA-LABEl: {{^}}use_constant_to_flat_addrspacecast: 124; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}} 125; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] 126; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] 127; HSA: flat_load_dword v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}} 128define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(4)* %ptr) #0 { 129 %stof = addrspacecast i32 addrspace(4)* %ptr to i32* 130 %ld = load volatile i32, i32* %stof 131 ret void 132} 133 134; HSA-LABEl: {{^}}use_constant_to_global_addrspacecast: 135; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}} 136; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] 137; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] 138; HSA: {{flat|global}}_load_dword v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}} 139define amdgpu_kernel void @use_constant_to_global_addrspacecast(i32 addrspace(4)* %ptr) #0 { 140 %stof = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(1)* 141 %ld = load volatile i32, i32 addrspace(1)* %stof 142 ret void 143} 144 145; HSA-LABEL: {{^}}use_flat_to_group_addrspacecast: 146; HSA: enable_sgpr_private_segment_buffer = 1 147; HSA: enable_sgpr_dispatch_ptr = 0 148; HSA: enable_sgpr_queue_ptr = 0 149 150; HSA: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}} 151; CI-DAG: v_cmp_ne_u64_e64 vcc, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0{{$}} 152; CI-DAG: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s[[PTR_LO]] 153; CI-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]] 154; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}} 155; GFX9-DAG: s_cmp_lg_u64 s{{\[}}[[CMP_LO:[0-9]+]]:[[CMP_HI:[0-9]+]]{{\]}}, 0 156; GFX9-DAG: s_cselect_b32 s[[PTR_LO]], s[[PTR_LO]], -1 157; GFX9-DAG: v_mov_b32_e32 [[CASTPTR:v[0-9]+]], s[[PTR_LO]] 158; HSA: ds_write_b32 [[CASTPTR]], v[[K]] 159define amdgpu_kernel void @use_flat_to_group_addrspacecast(i32* %ptr) #0 { 160 %ftos = addrspacecast i32* %ptr to i32 addrspace(3)* 161 store volatile i32 0, i32 addrspace(3)* %ftos 162 ret void 163} 164 165; HSA-LABEL: {{^}}use_flat_to_private_addrspacecast: 166; HSA: enable_sgpr_private_segment_buffer = 1 167; HSA: enable_sgpr_dispatch_ptr = 0 168; HSA: enable_sgpr_queue_ptr = 0 169 170; HSA: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}} 171; CI-DAG: v_cmp_ne_u64_e64 vcc, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0{{$}} 172; CI-DAG: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s[[PTR_LO]] 173; CI-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]] 174; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}} 175; GFX9-DAG: s_cmp_lg_u64 s{{\[}}[[CMP_LO:[0-9]+]]:[[CMP_HI:[0-9]+]]{{\]}}, 0 176; GFX9-DAG: s_cselect_b32 s[[PTR_LO]], s[[PTR_LO]], -1 177; GFX9-DAG: v_mov_b32_e32 [[CASTPTR:v[0-9]+]], s[[PTR_LO]] 178; HSA: buffer_store_dword v[[K]], [[CASTPTR]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}} 179define amdgpu_kernel void @use_flat_to_private_addrspacecast(i32* %ptr) #0 { 180 %ftos = addrspacecast i32* %ptr to i32 addrspace(5)* 181 store volatile i32 0, i32 addrspace(5)* %ftos 182 ret void 183} 184 185; HSA-LABEL: {{^}}use_flat_to_global_addrspacecast: 186; HSA: enable_sgpr_queue_ptr = 0 187 188; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0 189; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] 190; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] 191; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0 192; HSA: {{flat|global}}_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]] 193define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32* %ptr) #0 { 194 %ftos = addrspacecast i32* %ptr to i32 addrspace(1)* 195 store volatile i32 0, i32 addrspace(1)* %ftos 196 ret void 197} 198 199; HSA-LABEL: {{^}}use_flat_to_constant_addrspacecast: 200; HSA: enable_sgpr_queue_ptr = 0 201 202; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0 203; HSA: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTRLO]]:[[PTRHI]]{{\]}}, 0x0 204define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #0 { 205 %ftos = addrspacecast i32* %ptr to i32 addrspace(4)* 206 load volatile i32, i32 addrspace(4)* %ftos 207 ret void 208} 209 210; HSA-LABEL: {{^}}cast_0_group_to_flat_addrspacecast: 211; CI: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10 212; CI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE]] 213; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16) 214; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16 215; GFX9-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SSRC_SHARED_BASE]] 216 217; GFX9-XXX: v_mov_b32_e32 v[[HI:[0-9]+]], src_shared_base 218 219; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} 220; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} 221; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] 222define amdgpu_kernel void @cast_0_group_to_flat_addrspacecast() #0 { 223 %cast = addrspacecast i32 addrspace(3)* null to i32* 224 store volatile i32 7, i32* %cast 225 ret void 226} 227 228; HSA-LABEL: {{^}}cast_0_flat_to_group_addrspacecast: 229; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}} 230; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} 231; HSA: ds_write_b32 [[PTR]], [[K]] 232define amdgpu_kernel void @cast_0_flat_to_group_addrspacecast() #0 { 233 %cast = addrspacecast i32* null to i32 addrspace(3)* 234 store volatile i32 7, i32 addrspace(3)* %cast 235 ret void 236} 237 238; HSA-LABEL: {{^}}cast_neg1_group_to_flat_addrspacecast: 239; HSA: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} 240; HSA: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} 241; HSA: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} 242; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] 243define amdgpu_kernel void @cast_neg1_group_to_flat_addrspacecast() #0 { 244 %cast = addrspacecast i32 addrspace(3)* inttoptr (i32 -1 to i32 addrspace(3)*) to i32* 245 store volatile i32 7, i32* %cast 246 ret void 247} 248 249; HSA-LABEL: {{^}}cast_neg1_flat_to_group_addrspacecast: 250; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}} 251; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} 252; HSA: ds_write_b32 [[PTR]], [[K]] 253define amdgpu_kernel void @cast_neg1_flat_to_group_addrspacecast() #0 { 254 %cast = addrspacecast i32* inttoptr (i64 -1 to i32*) to i32 addrspace(3)* 255 store volatile i32 7, i32 addrspace(3)* %cast 256 ret void 257} 258 259; FIXME: Shouldn't need to enable queue ptr 260; HSA-LABEL: {{^}}cast_0_private_to_flat_addrspacecast: 261; CI: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11 262; CI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE]] 263; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16) 264; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16 265; GFX9-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SSRC_SHARED_BASE]] 266 267; GFX9-XXX: v_mov_b32_e32 v[[HI:[0-9]+]], src_shared_base 268 269; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} 270; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} 271; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] 272define amdgpu_kernel void @cast_0_private_to_flat_addrspacecast() #0 { 273 %cast = addrspacecast i32 addrspace(5)* null to i32* 274 store volatile i32 7, i32* %cast 275 ret void 276} 277 278; HSA-LABEL: {{^}}cast_0_flat_to_private_addrspacecast: 279; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}} 280; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} 281; HSA: buffer_store_dword [[K]], [[PTR]], s{{\[[0-9]+:[0-9]+\]}}, 0 282define amdgpu_kernel void @cast_0_flat_to_private_addrspacecast() #0 { 283 %cast = addrspacecast i32* null to i32 addrspace(5)* 284 store volatile i32 7, i32 addrspace(5)* %cast 285 ret void 286} 287 288 289; HSA-LABEL: {{^}}cast_neg1_private_to_flat_addrspacecast: 290; CI: enable_sgpr_queue_ptr = 1 291; GFX9: enable_sgpr_queue_ptr = 0 292 293; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} 294; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} 295; HSA: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} 296; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] 297define amdgpu_kernel void @cast_neg1_private_to_flat_addrspacecast() #0 { 298 %cast = addrspacecast i32 addrspace(5)* inttoptr (i32 -1 to i32 addrspace(5)*) to i32* 299 store volatile i32 7, i32* %cast 300 ret void 301} 302 303; HSA-LABEL: {{^}}cast_neg1_flat_to_private_addrspacecast: 304; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}} 305; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} 306; HSA: buffer_store_dword [[K]], [[PTR]], s{{\[[0-9]+:[0-9]+\]}}, 0 307define amdgpu_kernel void @cast_neg1_flat_to_private_addrspacecast() #0 { 308 %cast = addrspacecast i32* inttoptr (i64 -1 to i32*) to i32 addrspace(5)* 309 store volatile i32 7, i32 addrspace(5)* %cast 310 ret void 311} 312 313 314; Disable optimizations in case there are optimizations added that 315; specialize away generic pointer accesses. 316 317; HSA-LABEL: {{^}}branch_use_flat_i32: 318; HSA: {{flat|global}}_store_dword {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} 319; HSA: s_endpgm 320define amdgpu_kernel void @branch_use_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* %gptr, i32 addrspace(3)* %lptr, i32 %x, i32 %c) #0 { 321entry: 322 %cmp = icmp ne i32 %c, 0 323 br i1 %cmp, label %local, label %global 324 325local: 326 %flat_local = addrspacecast i32 addrspace(3)* %lptr to i32* 327 br label %end 328 329global: 330 %flat_global = addrspacecast i32 addrspace(1)* %gptr to i32* 331 br label %end 332 333end: 334 %fptr = phi i32* [ %flat_local, %local ], [ %flat_global, %global ] 335 store volatile i32 %x, i32* %fptr, align 4 336; %val = load i32, i32* %fptr, align 4 337; store i32 %val, i32 addrspace(1)* %out, align 4 338 ret void 339} 340 341; Check for prologue initializing special SGPRs pointing to scratch. 342; HSA-LABEL: {{^}}store_flat_scratch: 343; CI-DAG: s_mov_b32 flat_scratch_lo, s9 344; CI-DAG: s_add_u32 [[ADD:s[0-9]+]], s8, s11 345; CI: s_lshr_b32 flat_scratch_hi, [[ADD]], 8 346 347; GFX9: s_add_u32 flat_scratch_lo, s6, s9 348; GFX9: s_addc_u32 flat_scratch_hi, s7, 0 349 350; HSA: {{flat|global}}_store_dword 351; HSA: s_barrier 352; HSA: {{flat|global}}_load_dword 353define amdgpu_kernel void @store_flat_scratch(i32 addrspace(1)* noalias %out, i32) #0 { 354 %alloca = alloca i32, i32 9, align 4, addrspace(5) 355 %x = call i32 @llvm.amdgcn.workitem.id.x() #2 356 %pptr = getelementptr i32, i32 addrspace(5)* %alloca, i32 %x 357 %fptr = addrspacecast i32 addrspace(5)* %pptr to i32* 358 store volatile i32 %x, i32* %fptr 359 ; Dummy call 360 call void @llvm.amdgcn.s.barrier() #1 361 %reload = load volatile i32, i32* %fptr, align 4 362 store volatile i32 %reload, i32 addrspace(1)* %out, align 4 363 ret void 364} 365 366; HSA-LABEL: {{^}}use_constant_to_constant32_addrspacecast 367; GFX9: s_load_dwordx2 [[PTRPTR:s\[[0-9]+:[0-9]+\]]], s[4:5], 0x0{{$}} 368; GFX9: s_load_dword [[OFFSET:s[0-9]+]], s[4:5], 0x8{{$}} 369; GFX9: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}}, [[PTRPTR]], 0x0{{$}} 370; GFX9: s_mov_b32 s[[PTR_HI]], 0{{$}} 371; GFX9: s_add_i32 s[[PTR_LO]], s[[PTR_LO]], [[OFFSET]] 372; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x0{{$}} 373define amdgpu_kernel void @use_constant_to_constant32_addrspacecast(i8 addrspace(4)* addrspace(4)* %ptr.ptr, i32 %offset) #0 { 374 %ptr = load volatile i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %ptr.ptr 375 %addrspacecast = addrspacecast i8 addrspace(4)* %ptr to i8 addrspace(6)* 376 %gep = getelementptr i8, i8 addrspace(6)* %addrspacecast, i32 %offset 377 %ptr.cast = bitcast i8 addrspace(6)* %gep to i32 addrspace(6)* 378 %load = load volatile i32, i32 addrspace(6)* %ptr.cast, align 4 379 ret void 380} 381 382; HSA-LABEL: {{^}}use_global_to_constant32_addrspacecast 383; GFX9: s_load_dwordx2 [[PTRPTR:s\[[0-9]+:[0-9]+\]]], s[4:5], 0x0{{$}} 384; GFX9: s_load_dword [[OFFSET:s[0-9]+]], s[4:5], 0x8{{$}} 385; GFX9: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}}, [[PTRPTR]], 0x0{{$}} 386; GFX9: s_mov_b32 s[[PTR_HI]], 0{{$}} 387; GFX9: s_add_i32 s[[PTR_LO]], s[[PTR_LO]], [[OFFSET]] 388; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x0{{$}} 389define amdgpu_kernel void @use_global_to_constant32_addrspacecast(i8 addrspace(1)* addrspace(4)* %ptr.ptr, i32 %offset) #0 { 390 %ptr = load volatile i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* %ptr.ptr 391 %addrspacecast = addrspacecast i8 addrspace(1)* %ptr to i8 addrspace(6)* 392 %gep = getelementptr i8, i8 addrspace(6)* %addrspacecast, i32 %offset 393 %ptr.cast = bitcast i8 addrspace(6)* %gep to i32 addrspace(6)* 394 %load = load volatile i32, i32 addrspace(6)* %ptr.cast, align 4 395 ret void 396} 397 398declare void @llvm.amdgcn.s.barrier() #1 399declare i32 @llvm.amdgcn.workitem.id.x() #2 400 401attributes #0 = { nounwind } 402attributes #1 = { nounwind convergent } 403attributes #2 = { nounwind readnone } 404