1; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-code-object-v3,-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=CI %s 2; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-code-object-v3,-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=GFX9 %s 3 4; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast: 5; HSA: enable_sgpr_private_segment_buffer = 1 6; HSA: enable_sgpr_dispatch_ptr = 0 7; CI: enable_sgpr_queue_ptr = 1 8; GFX9: enable_sgpr_queue_ptr = 0 9 10; CI-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}} 11; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10{{$}} 12; CI-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]] 13; CI-DAG: v_cmp_ne_u32_e64 vcc, [[PTR]], -1 14; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc 15; CI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] 16; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] 17 18; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 19; GFX9-DAG: s_load_dword [[PTR:s[0-9]+]], s[4:5], 0x0{{$}} 20; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16) 21; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16 22; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_SHARED_BASE]] 23 24; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_shared_base 25; GFX9: v_cmp_ne_u32_e64 vcc, [[PTR]], -1 26; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc 27; GFX9-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] 28; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] 29 30; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]] 31 32; At most 2 digits. Make sure src_shared_base is not counted as a high 33; number SGPR. 34 35; CI: NumSgprs: {{[0-9][0-9]+}} 36; GFX9: NumSgprs: {{[0-9]+}} 37define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #0 { 38 %stof = addrspacecast i32 addrspace(3)* %ptr to i32* 39 store volatile i32 7, i32* %stof 40 ret void 41} 42 43; Test handling inside a non-kernel 44; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast_func: 45; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10{{$}} 46; CI-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]] 47; CI-DAG: v_cmp_ne_u32_e32 vcc, -1, v0 48; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc 49; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, v0 50 51; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 52; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16) 53; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16 54; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_SHARED_BASE]] 55 56; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_shared_base 57; GFX9-DAG: v_cmp_ne_u32_e32 vcc, -1, v0 58; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, v0, vcc 59; GFX9-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc 60 61; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]] 62define void @use_group_to_flat_addrspacecast_func(i32 addrspace(3)* %ptr) #0 { 63 %stof = addrspacecast i32 addrspace(3)* %ptr to i32* 64 store volatile i32 7, i32* %stof 65 ret void 66} 67 68; HSA-LABEL: {{^}}use_private_to_flat_addrspacecast: 69; HSA: enable_sgpr_private_segment_buffer = 1 70; HSA: enable_sgpr_dispatch_ptr = 0 71; CI: enable_sgpr_queue_ptr = 1 72; GFX9: enable_sgpr_queue_ptr = 0 73 74; CI-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}} 75; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11{{$}} 76; CI-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]] 77 78; CI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 79; CI-DAG: v_cmp_ne_u32_e64 vcc, [[PTR]], -1 80; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc 81; CI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] 82; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] 83 84; GFX9-DAG: s_load_dword [[PTR:s[0-9]+]], s[4:5], 0x0{{$}} 85; GFX9-DAG: s_getreg_b32 [[SSRC_PRIVATE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16) 86; GFX9-DAG: s_lshl_b32 [[SSRC_PRIVATE_BASE:s[0-9]+]], [[SSRC_PRIVATE]], 16 87; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_PRIVATE_BASE]] 88 89; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_private_base 90 91; GFX9-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 92; GFX9: v_cmp_ne_u32_e64 vcc, [[PTR]], -1 93; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc 94; GFX9: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] 95; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] 96 97; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]] 98 99; CI: NumSgprs: {{[0-9][0-9]+}} 100; GFX9: NumSgprs: {{[0-9]+}} 101define amdgpu_kernel void @use_private_to_flat_addrspacecast(i32 addrspace(5)* %ptr) #0 { 102 %stof = addrspacecast i32 addrspace(5)* %ptr to i32* 103 store volatile i32 7, i32* %stof 104 ret void 105} 106 107; no-op 108; HSA-LABEL: {{^}}use_global_to_flat_addrspacecast: 109; HSA: enable_sgpr_queue_ptr = 0 110 111; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}} 112; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] 113; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] 114; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 115; HSA: flat_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]] 116define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #0 { 117 %stof = addrspacecast i32 addrspace(1)* %ptr to i32* 118 store volatile i32 7, i32* %stof 119 ret void 120} 121 122; no-op 123; HSA-LABEl: {{^}}use_constant_to_flat_addrspacecast: 124; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}} 125; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] 126; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] 127; HSA: flat_load_dword v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}} 128define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(4)* %ptr) #0 { 129 %stof = addrspacecast i32 addrspace(4)* %ptr to i32* 130 %ld = load volatile i32, i32* %stof 131 ret void 132} 133 134; HSA-LABEl: {{^}}use_constant_to_global_addrspacecast: 135; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}} 136; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] 137; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] 138; HSA: {{flat|global}}_load_dword v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}} 139define amdgpu_kernel void @use_constant_to_global_addrspacecast(i32 addrspace(4)* %ptr) #0 { 140 %stof = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(1)* 141 %ld = load volatile i32, i32 addrspace(1)* %stof 142 ret void 143} 144 145; HSA-LABEL: {{^}}use_flat_to_group_addrspacecast: 146; HSA: enable_sgpr_private_segment_buffer = 1 147; HSA: enable_sgpr_dispatch_ptr = 0 148; HSA: enable_sgpr_queue_ptr = 0 149 150; HSA: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}} 151; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}} 152; CI-DAG: v_cmp_ne_u64_e64 s{{\[}}[[CMP_LO:[0-9]+]]:[[CMP_HI:[0-9]+]]{{\]}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0{{$}} 153; CI-DAG: s_cmp_lg_u32 s[[CMP_LO]], 0 154; GFX9-DAG: s_cmp_lg_u64 s{{\[}}[[CMP_LO:[0-9]+]]:[[CMP_HI:[0-9]+]]{{\]}}, 0 155; HSA-DAG: s_cselect_b32 s[[PTR_LO]], s[[PTR_LO]], -1 156; HSA-DAG: v_mov_b32_e32 [[CASTPTR:v[0-9]+]], s[[PTR_LO]] 157; HSA: ds_write_b32 [[CASTPTR]], v[[K]] 158define amdgpu_kernel void @use_flat_to_group_addrspacecast(i32* %ptr) #0 { 159 %ftos = addrspacecast i32* %ptr to i32 addrspace(3)* 160 store volatile i32 0, i32 addrspace(3)* %ftos 161 ret void 162} 163 164; HSA-LABEL: {{^}}use_flat_to_private_addrspacecast: 165; HSA: enable_sgpr_private_segment_buffer = 1 166; HSA: enable_sgpr_dispatch_ptr = 0 167; HSA: enable_sgpr_queue_ptr = 0 168 169; HSA: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}} 170; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}} 171; CI-DAG: v_cmp_ne_u64_e64 s{{\[}}[[CMP_LO:[0-9]+]]:[[CMP_HI:[0-9]+]]{{\]}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0{{$}} 172; CI-DAG: s_cmp_lg_u32 s[[CMP_LO]], 0 173; GFX9-DAG: s_cmp_lg_u64 s{{\[}}[[CMP_LO:[0-9]+]]:[[CMP_HI:[0-9]+]]{{\]}}, 0 174; HSA-DAG: s_cselect_b32 s[[PTR_LO]], s[[PTR_LO]], -1 175; HSA-DAG: v_mov_b32_e32 [[CASTPTR:v[0-9]+]], s[[PTR_LO]] 176; HSA: buffer_store_dword v[[K]], [[CASTPTR]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}} 177define amdgpu_kernel void @use_flat_to_private_addrspacecast(i32* %ptr) #0 { 178 %ftos = addrspacecast i32* %ptr to i32 addrspace(5)* 179 store volatile i32 0, i32 addrspace(5)* %ftos 180 ret void 181} 182 183; HSA-LABEL: {{^}}use_flat_to_global_addrspacecast: 184; HSA: enable_sgpr_queue_ptr = 0 185 186; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0 187; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] 188; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] 189; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0 190; HSA: {{flat|global}}_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]] 191define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32* %ptr) #0 { 192 %ftos = addrspacecast i32* %ptr to i32 addrspace(1)* 193 store volatile i32 0, i32 addrspace(1)* %ftos 194 ret void 195} 196 197; HSA-LABEL: {{^}}use_flat_to_constant_addrspacecast: 198; HSA: enable_sgpr_queue_ptr = 0 199 200; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0 201; HSA: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTRLO]]:[[PTRHI]]{{\]}}, 0x0 202define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #0 { 203 %ftos = addrspacecast i32* %ptr to i32 addrspace(4)* 204 load volatile i32, i32 addrspace(4)* %ftos 205 ret void 206} 207 208; HSA-LABEL: {{^}}cast_0_group_to_flat_addrspacecast: 209; CI: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10 210; CI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE]] 211; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16) 212; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16 213; GFX9-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SSRC_SHARED_BASE]] 214 215; GFX9-XXX: v_mov_b32_e32 v[[HI:[0-9]+]], src_shared_base 216 217; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} 218; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} 219; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] 220define amdgpu_kernel void @cast_0_group_to_flat_addrspacecast() #0 { 221 %cast = addrspacecast i32 addrspace(3)* null to i32* 222 store volatile i32 7, i32* %cast 223 ret void 224} 225 226; HSA-LABEL: {{^}}cast_0_flat_to_group_addrspacecast: 227; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}} 228; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} 229; HSA: ds_write_b32 [[PTR]], [[K]] 230define amdgpu_kernel void @cast_0_flat_to_group_addrspacecast() #0 { 231 %cast = addrspacecast i32* null to i32 addrspace(3)* 232 store volatile i32 7, i32 addrspace(3)* %cast 233 ret void 234} 235 236; HSA-LABEL: {{^}}cast_neg1_group_to_flat_addrspacecast: 237; HSA: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} 238; HSA: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} 239; HSA: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} 240; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] 241define amdgpu_kernel void @cast_neg1_group_to_flat_addrspacecast() #0 { 242 %cast = addrspacecast i32 addrspace(3)* inttoptr (i32 -1 to i32 addrspace(3)*) to i32* 243 store volatile i32 7, i32* %cast 244 ret void 245} 246 247; HSA-LABEL: {{^}}cast_neg1_flat_to_group_addrspacecast: 248; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}} 249; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} 250; HSA: ds_write_b32 [[PTR]], [[K]] 251define amdgpu_kernel void @cast_neg1_flat_to_group_addrspacecast() #0 { 252 %cast = addrspacecast i32* inttoptr (i64 -1 to i32*) to i32 addrspace(3)* 253 store volatile i32 7, i32 addrspace(3)* %cast 254 ret void 255} 256 257; FIXME: Shouldn't need to enable queue ptr 258; HSA-LABEL: {{^}}cast_0_private_to_flat_addrspacecast: 259; CI: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11 260; CI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE]] 261; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16) 262; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16 263; GFX9-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SSRC_SHARED_BASE]] 264 265; GFX9-XXX: v_mov_b32_e32 v[[HI:[0-9]+]], src_shared_base 266 267; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} 268; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} 269; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] 270define amdgpu_kernel void @cast_0_private_to_flat_addrspacecast() #0 { 271 %cast = addrspacecast i32 addrspace(5)* null to i32* 272 store volatile i32 7, i32* %cast 273 ret void 274} 275 276; HSA-LABEL: {{^}}cast_0_flat_to_private_addrspacecast: 277; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}} 278; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} 279; HSA: buffer_store_dword [[K]], [[PTR]], s{{\[[0-9]+:[0-9]+\]}}, 0 280define amdgpu_kernel void @cast_0_flat_to_private_addrspacecast() #0 { 281 %cast = addrspacecast i32* null to i32 addrspace(5)* 282 store volatile i32 7, i32 addrspace(5)* %cast 283 ret void 284} 285 286 287; HSA-LABEL: {{^}}cast_neg1_private_to_flat_addrspacecast: 288; CI: enable_sgpr_queue_ptr = 1 289; GFX9: enable_sgpr_queue_ptr = 0 290 291; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} 292; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} 293; HSA: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} 294; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] 295define amdgpu_kernel void @cast_neg1_private_to_flat_addrspacecast() #0 { 296 %cast = addrspacecast i32 addrspace(5)* inttoptr (i32 -1 to i32 addrspace(5)*) to i32* 297 store volatile i32 7, i32* %cast 298 ret void 299} 300 301; HSA-LABEL: {{^}}cast_neg1_flat_to_private_addrspacecast: 302; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}} 303; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} 304; HSA: buffer_store_dword [[K]], [[PTR]], s{{\[[0-9]+:[0-9]+\]}}, 0 305define amdgpu_kernel void @cast_neg1_flat_to_private_addrspacecast() #0 { 306 %cast = addrspacecast i32* inttoptr (i64 -1 to i32*) to i32 addrspace(5)* 307 store volatile i32 7, i32 addrspace(5)* %cast 308 ret void 309} 310 311 312; Disable optimizations in case there are optimizations added that 313; specialize away generic pointer accesses. 314 315; HSA-LABEL: {{^}}branch_use_flat_i32: 316; HSA: {{flat|global}}_store_dword {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} 317; HSA: s_endpgm 318define amdgpu_kernel void @branch_use_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* %gptr, i32 addrspace(3)* %lptr, i32 %x, i32 %c) #0 { 319entry: 320 %cmp = icmp ne i32 %c, 0 321 br i1 %cmp, label %local, label %global 322 323local: 324 %flat_local = addrspacecast i32 addrspace(3)* %lptr to i32* 325 br label %end 326 327global: 328 %flat_global = addrspacecast i32 addrspace(1)* %gptr to i32* 329 br label %end 330 331end: 332 %fptr = phi i32* [ %flat_local, %local ], [ %flat_global, %global ] 333 store volatile i32 %x, i32* %fptr, align 4 334; %val = load i32, i32* %fptr, align 4 335; store i32 %val, i32 addrspace(1)* %out, align 4 336 ret void 337} 338 339; Check for prologue initializing special SGPRs pointing to scratch. 340; HSA-LABEL: {{^}}store_flat_scratch: 341; CI-DAG: s_mov_b32 flat_scratch_lo, s9 342; CI-DAG: s_add_u32 [[ADD:s[0-9]+]], s8, s11 343; CI: s_lshr_b32 flat_scratch_hi, [[ADD]], 8 344 345; GFX9: s_add_u32 flat_scratch_lo, s6, s9 346; GFX9: s_addc_u32 flat_scratch_hi, s7, 0 347 348; HSA: {{flat|global}}_store_dword 349; HSA: s_barrier 350; HSA: {{flat|global}}_load_dword 351define amdgpu_kernel void @store_flat_scratch(i32 addrspace(1)* noalias %out, i32) #0 { 352 %alloca = alloca i32, i32 9, align 4, addrspace(5) 353 %x = call i32 @llvm.amdgcn.workitem.id.x() #2 354 %pptr = getelementptr i32, i32 addrspace(5)* %alloca, i32 %x 355 %fptr = addrspacecast i32 addrspace(5)* %pptr to i32* 356 store volatile i32 %x, i32* %fptr 357 ; Dummy call 358 call void @llvm.amdgcn.s.barrier() #1 359 %reload = load volatile i32, i32* %fptr, align 4 360 store volatile i32 %reload, i32 addrspace(1)* %out, align 4 361 ret void 362} 363 364; HSA-LABEL: {{^}}use_constant_to_constant32_addrspacecast 365; GFX9: s_load_dwordx2 [[PTRPTR:s\[[0-9]+:[0-9]+\]]], s[4:5], 0x0{{$}} 366; GFX9: s_load_dword [[OFFSET:s[0-9]+]], s[4:5], 0x8{{$}} 367; GFX9: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}}, [[PTRPTR]], 0x0{{$}} 368; GFX9: s_mov_b32 s[[PTR_HI]], 0{{$}} 369; GFX9: s_add_i32 s[[PTR_LO]], s[[PTR_LO]], [[OFFSET]] 370; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x0{{$}} 371define amdgpu_kernel void @use_constant_to_constant32_addrspacecast(i8 addrspace(4)* addrspace(4)* %ptr.ptr, i32 %offset) #0 { 372 %ptr = load volatile i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %ptr.ptr 373 %addrspacecast = addrspacecast i8 addrspace(4)* %ptr to i8 addrspace(6)* 374 %gep = getelementptr i8, i8 addrspace(6)* %addrspacecast, i32 %offset 375 %ptr.cast = bitcast i8 addrspace(6)* %gep to i32 addrspace(6)* 376 %load = load volatile i32, i32 addrspace(6)* %ptr.cast, align 4 377 ret void 378} 379 380; HSA-LABEL: {{^}}use_global_to_constant32_addrspacecast 381; GFX9: s_load_dwordx2 [[PTRPTR:s\[[0-9]+:[0-9]+\]]], s[4:5], 0x0{{$}} 382; GFX9: s_load_dword [[OFFSET:s[0-9]+]], s[4:5], 0x8{{$}} 383; GFX9: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}}, [[PTRPTR]], 0x0{{$}} 384; GFX9: s_mov_b32 s[[PTR_HI]], 0{{$}} 385; GFX9: s_add_i32 s[[PTR_LO]], s[[PTR_LO]], [[OFFSET]] 386; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x0{{$}} 387define amdgpu_kernel void @use_global_to_constant32_addrspacecast(i8 addrspace(1)* addrspace(4)* %ptr.ptr, i32 %offset) #0 { 388 %ptr = load volatile i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* %ptr.ptr 389 %addrspacecast = addrspacecast i8 addrspace(1)* %ptr to i8 addrspace(6)* 390 %gep = getelementptr i8, i8 addrspace(6)* %addrspacecast, i32 %offset 391 %ptr.cast = bitcast i8 addrspace(6)* %gep to i32 addrspace(6)* 392 %load = load volatile i32, i32 addrspace(6)* %ptr.cast, align 4 393 ret void 394} 395 396declare void @llvm.amdgcn.s.barrier() #1 397declare i32 @llvm.amdgcn.workitem.id.x() #2 398 399attributes #0 = { nounwind } 400attributes #1 = { nounwind convergent } 401attributes #2 = { nounwind readnone } 402