1; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-code-object-v3,-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=CI %s 2; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-code-object-v3,-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=GFX9 %s 3 4; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast: 5; HSA: enable_sgpr_private_segment_buffer = 1 6; HSA: enable_sgpr_dispatch_ptr = 0 7; CI: enable_sgpr_queue_ptr = 1 8; GFX9: enable_sgpr_queue_ptr = 0 9 10; CI-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}} 11; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10{{$}} 12; CI-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]] 13; CI-DAG: v_cmp_ne_u32_e64 vcc, [[PTR]], -1 14; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc 15; CI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] 16; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] 17 18; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 19; GFX9-DAG: s_load_dword [[PTR:s[0-9]+]], s[4:5], 0x0{{$}} 20; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16) 21; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16 22; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_SHARED_BASE]] 23 24; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_shared_base 25; GFX9: v_cmp_ne_u32_e64 vcc, [[PTR]], -1 26; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc 27; GFX9-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] 28; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] 29 30; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]] 31 32; At most 2 digits. Make sure src_shared_base is not counted as a high 33; number SGPR. 34 35; CI: NumSgprs: {{[0-9][0-9]+}} 36; GFX9: NumSgprs: {{[0-9]+}} 37define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #0 { 38 %stof = addrspacecast i32 addrspace(3)* %ptr to i32* 39 store volatile i32 7, i32* %stof 40 ret void 41} 42 43; HSA-LABEL: {{^}}use_private_to_flat_addrspacecast: 44; HSA: enable_sgpr_private_segment_buffer = 1 45; HSA: enable_sgpr_dispatch_ptr = 0 46; CI: enable_sgpr_queue_ptr = 1 47; GFX9: enable_sgpr_queue_ptr = 0 48 49; CI-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}} 50; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11{{$}} 51; CI-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]] 52 53; CI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 54; CI-DAG: v_cmp_ne_u32_e64 vcc, [[PTR]], 0 55; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc 56; CI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] 57; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] 58 59; GFX9-DAG: s_load_dword [[PTR:s[0-9]+]], s[4:5], 0x0{{$}} 60; GFX9-DAG: s_getreg_b32 [[SSRC_PRIVATE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16) 61; GFX9-DAG: s_lshl_b32 [[SSRC_PRIVATE_BASE:s[0-9]+]], [[SSRC_PRIVATE]], 16 62; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_PRIVATE_BASE]] 63 64; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_private_base 65 66; GFX9-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 67; GFX9: v_cmp_ne_u32_e64 vcc, [[PTR]], 0 68; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc 69; GFX9: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] 70; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] 71 72; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]] 73 74; CI: NumSgprs: {{[0-9][0-9]+}} 75; GFX9: NumSgprs: {{[0-9]+}} 76define amdgpu_kernel void @use_private_to_flat_addrspacecast(i32 addrspace(5)* %ptr) #0 { 77 %stof = addrspacecast i32 addrspace(5)* %ptr to i32* 78 store volatile i32 7, i32* %stof 79 ret void 80} 81 82; no-op 83; HSA-LABEL: {{^}}use_global_to_flat_addrspacecast: 84; HSA: enable_sgpr_queue_ptr = 0 85 86; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}} 87; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] 88; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] 89; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 90; HSA: flat_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]] 91define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #0 { 92 %stof = addrspacecast i32 addrspace(1)* %ptr to i32* 93 store volatile i32 7, i32* %stof 94 ret void 95} 96 97; no-op 98; HSA-LABEl: {{^}}use_constant_to_flat_addrspacecast: 99; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}} 100; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] 101; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] 102; HSA: flat_load_dword v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}} 103define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(4)* %ptr) #0 { 104 %stof = addrspacecast i32 addrspace(4)* %ptr to i32* 105 %ld = load volatile i32, i32* %stof 106 ret void 107} 108 109; HSA-LABEl: {{^}}use_constant_to_global_addrspacecast: 110; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}} 111; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] 112; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] 113; HSA: {{flat|global}}_load_dword v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}} 114define amdgpu_kernel void @use_constant_to_global_addrspacecast(i32 addrspace(4)* %ptr) #0 { 115 %stof = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(1)* 116 %ld = load volatile i32, i32 addrspace(1)* %stof 117 ret void 118} 119 120; HSA-LABEL: {{^}}use_flat_to_group_addrspacecast: 121; HSA: enable_sgpr_private_segment_buffer = 1 122; HSA: enable_sgpr_dispatch_ptr = 0 123; HSA: enable_sgpr_queue_ptr = 0 124 125; HSA: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}} 126; HSA-DAG: v_cmp_ne_u64_e64 vcc, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0{{$}} 127; HSA-DAG: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s[[PTR_LO]] 128; HSA-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]] 129; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}} 130; HSA: ds_write_b32 [[CASTPTR]], v[[K]] 131define amdgpu_kernel void @use_flat_to_group_addrspacecast(i32* %ptr) #0 { 132 %ftos = addrspacecast i32* %ptr to i32 addrspace(3)* 133 store volatile i32 0, i32 addrspace(3)* %ftos 134 ret void 135} 136 137; HSA-LABEL: {{^}}use_flat_to_private_addrspacecast: 138; HSA: enable_sgpr_private_segment_buffer = 1 139; HSA: enable_sgpr_dispatch_ptr = 0 140; HSA: enable_sgpr_queue_ptr = 0 141 142; HSA: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}} 143; HSA-DAG: v_cmp_ne_u64_e64 vcc, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0{{$}} 144; HSA-DAG: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s[[PTR_LO]] 145; HSA-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], 0, v[[VPTR_LO]] 146; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}} 147; HSA: buffer_store_dword v[[K]], [[CASTPTR]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}} 148define amdgpu_kernel void @use_flat_to_private_addrspacecast(i32* %ptr) #0 { 149 %ftos = addrspacecast i32* %ptr to i32 addrspace(5)* 150 store volatile i32 0, i32 addrspace(5)* %ftos 151 ret void 152} 153 154; HSA-LABEL: {{^}}use_flat_to_global_addrspacecast: 155; HSA: enable_sgpr_queue_ptr = 0 156 157; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0 158; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] 159; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] 160; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0 161; HSA: {{flat|global}}_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]] 162define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32* %ptr) #0 { 163 %ftos = addrspacecast i32* %ptr to i32 addrspace(1)* 164 store volatile i32 0, i32 addrspace(1)* %ftos 165 ret void 166} 167 168; HSA-LABEL: {{^}}use_flat_to_constant_addrspacecast: 169; HSA: enable_sgpr_queue_ptr = 0 170 171; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0 172; HSA: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTRLO]]:[[PTRHI]]{{\]}}, 0x0 173define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #0 { 174 %ftos = addrspacecast i32* %ptr to i32 addrspace(4)* 175 load volatile i32, i32 addrspace(4)* %ftos 176 ret void 177} 178 179; HSA-LABEL: {{^}}cast_0_group_to_flat_addrspacecast: 180; CI: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10 181; CI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE]] 182; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16) 183; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16 184; GFX9-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SSRC_SHARED_BASE]] 185 186; GFX9-XXX: v_mov_b32_e32 v[[HI:[0-9]+]], src_shared_base 187 188; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} 189; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} 190; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] 191define amdgpu_kernel void @cast_0_group_to_flat_addrspacecast() #0 { 192 %cast = addrspacecast i32 addrspace(3)* null to i32* 193 store volatile i32 7, i32* %cast 194 ret void 195} 196 197; HSA-LABEL: {{^}}cast_0_flat_to_group_addrspacecast: 198; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}} 199; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} 200; HSA: ds_write_b32 [[PTR]], [[K]] 201define amdgpu_kernel void @cast_0_flat_to_group_addrspacecast() #0 { 202 %cast = addrspacecast i32* null to i32 addrspace(3)* 203 store volatile i32 7, i32 addrspace(3)* %cast 204 ret void 205} 206 207; HSA-LABEL: {{^}}cast_neg1_group_to_flat_addrspacecast: 208; HSA: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} 209; HSA: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} 210; HSA: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} 211; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] 212define amdgpu_kernel void @cast_neg1_group_to_flat_addrspacecast() #0 { 213 %cast = addrspacecast i32 addrspace(3)* inttoptr (i32 -1 to i32 addrspace(3)*) to i32* 214 store volatile i32 7, i32* %cast 215 ret void 216} 217 218; HSA-LABEL: {{^}}cast_neg1_flat_to_group_addrspacecast: 219; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}} 220; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} 221; HSA: ds_write_b32 [[PTR]], [[K]] 222define amdgpu_kernel void @cast_neg1_flat_to_group_addrspacecast() #0 { 223 %cast = addrspacecast i32* inttoptr (i64 -1 to i32*) to i32 addrspace(3)* 224 store volatile i32 7, i32 addrspace(3)* %cast 225 ret void 226} 227 228; FIXME: Shouldn't need to enable queue ptr 229; HSA-LABEL: {{^}}cast_0_private_to_flat_addrspacecast: 230; CI: enable_sgpr_queue_ptr = 1 231; GFX9: enable_sgpr_queue_ptr = 0 232 233; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} 234; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} 235; HSA: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} 236; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] 237define amdgpu_kernel void @cast_0_private_to_flat_addrspacecast() #0 { 238 %cast = addrspacecast i32 addrspace(5)* null to i32* 239 store volatile i32 7, i32* %cast 240 ret void 241} 242 243; HSA-LABEL: {{^}}cast_0_flat_to_private_addrspacecast: 244; HSA: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} 245; HSA: buffer_store_dword [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 246define amdgpu_kernel void @cast_0_flat_to_private_addrspacecast() #0 { 247 %cast = addrspacecast i32* null to i32 addrspace(5)* 248 store volatile i32 7, i32 addrspace(5)* %cast 249 ret void 250} 251 252; Disable optimizations in case there are optimizations added that 253; specialize away generic pointer accesses. 254 255; HSA-LABEL: {{^}}branch_use_flat_i32: 256; HSA: {{flat|global}}_store_dword {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} 257; HSA: s_endpgm 258define amdgpu_kernel void @branch_use_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* %gptr, i32 addrspace(3)* %lptr, i32 %x, i32 %c) #0 { 259entry: 260 %cmp = icmp ne i32 %c, 0 261 br i1 %cmp, label %local, label %global 262 263local: 264 %flat_local = addrspacecast i32 addrspace(3)* %lptr to i32* 265 br label %end 266 267global: 268 %flat_global = addrspacecast i32 addrspace(1)* %gptr to i32* 269 br label %end 270 271end: 272 %fptr = phi i32* [ %flat_local, %local ], [ %flat_global, %global ] 273 store volatile i32 %x, i32* %fptr, align 4 274; %val = load i32, i32* %fptr, align 4 275; store i32 %val, i32 addrspace(1)* %out, align 4 276 ret void 277} 278 279; Check for prologue initializing special SGPRs pointing to scratch. 280; HSA-LABEL: {{^}}store_flat_scratch: 281; CI-DAG: s_mov_b32 flat_scratch_lo, s9 282; CI-DAG: s_add_u32 [[ADD:s[0-9]+]], s8, s11 283; CI: s_lshr_b32 flat_scratch_hi, [[ADD]], 8 284 285; GFX9: s_add_u32 flat_scratch_lo, s6, s9 286; GFX9: s_addc_u32 flat_scratch_hi, s7, 0 287 288; HSA: {{flat|global}}_store_dword 289; HSA: s_barrier 290; HSA: {{flat|global}}_load_dword 291define amdgpu_kernel void @store_flat_scratch(i32 addrspace(1)* noalias %out, i32) #0 { 292 %alloca = alloca i32, i32 9, align 4, addrspace(5) 293 %x = call i32 @llvm.amdgcn.workitem.id.x() #2 294 %pptr = getelementptr i32, i32 addrspace(5)* %alloca, i32 %x 295 %fptr = addrspacecast i32 addrspace(5)* %pptr to i32* 296 store volatile i32 %x, i32* %fptr 297 ; Dummy call 298 call void @llvm.amdgcn.s.barrier() #1 299 %reload = load volatile i32, i32* %fptr, align 4 300 store volatile i32 %reload, i32 addrspace(1)* %out, align 4 301 ret void 302} 303 304; HSA-LABEL: {{^}}use_constant_to_constant32_addrspacecast 305; GFX9: s_load_dwordx2 [[PTRPTR:s\[[0-9]+:[0-9]+\]]], s[4:5], 0x0{{$}} 306; GFX9: s_load_dword [[OFFSET:s[0-9]+]], s[4:5], 0x8{{$}} 307; GFX9: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}}, [[PTRPTR]], 0x0{{$}} 308; GFX9: s_mov_b32 s[[PTR_HI]], 0{{$}} 309; GFX9: s_add_i32 s[[PTR_LO]], s[[PTR_LO]], [[OFFSET]] 310; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x0{{$}} 311define amdgpu_kernel void @use_constant_to_constant32_addrspacecast(i8 addrspace(4)* addrspace(4)* %ptr.ptr, i32 %offset) #0 { 312 %ptr = load volatile i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %ptr.ptr 313 %addrspacecast = addrspacecast i8 addrspace(4)* %ptr to i8 addrspace(6)* 314 %gep = getelementptr i8, i8 addrspace(6)* %addrspacecast, i32 %offset 315 %ptr.cast = bitcast i8 addrspace(6)* %gep to i32 addrspace(6)* 316 %load = load volatile i32, i32 addrspace(6)* %ptr.cast, align 4 317 ret void 318} 319 320; HSA-LABEL: {{^}}use_global_to_constant32_addrspacecast 321; GFX9: s_load_dwordx2 [[PTRPTR:s\[[0-9]+:[0-9]+\]]], s[4:5], 0x0{{$}} 322; GFX9: s_load_dword [[OFFSET:s[0-9]+]], s[4:5], 0x8{{$}} 323; GFX9: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}}, [[PTRPTR]], 0x0{{$}} 324; GFX9: s_mov_b32 s[[PTR_HI]], 0{{$}} 325; GFX9: s_add_i32 s[[PTR_LO]], s[[PTR_LO]], [[OFFSET]] 326; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x0{{$}} 327define amdgpu_kernel void @use_global_to_constant32_addrspacecast(i8 addrspace(1)* addrspace(4)* %ptr.ptr, i32 %offset) #0 { 328 %ptr = load volatile i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* %ptr.ptr 329 %addrspacecast = addrspacecast i8 addrspace(1)* %ptr to i8 addrspace(6)* 330 %gep = getelementptr i8, i8 addrspace(6)* %addrspacecast, i32 %offset 331 %ptr.cast = bitcast i8 addrspace(6)* %gep to i32 addrspace(6)* 332 %load = load volatile i32, i32 addrspace(6)* %ptr.cast, align 4 333 ret void 334} 335 336declare void @llvm.amdgcn.s.barrier() #1 337declare i32 @llvm.amdgcn.workitem.id.x() #2 338 339attributes #0 = { nounwind } 340attributes #1 = { nounwind convergent } 341attributes #2 = { nounwind readnone } 342