1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
3; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
4
5; ===================================================================================
6; V_ADD_LSHL_U32
7; ===================================================================================
8
9define amdgpu_ps float @add_shl(i32 %a, i32 %b, i32 %c) {
10; VI-LABEL: add_shl:
11; VI:       ; %bb.0:
12; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
13; VI-NEXT:    v_lshlrev_b32_e32 v0, v2, v0
14; VI-NEXT:    ; return to shader part epilog
15;
16; GFX9-LABEL: add_shl:
17; GFX9:       ; %bb.0:
18; GFX9-NEXT:    v_add_lshl_u32 v0, v0, v1, v2
19; GFX9-NEXT:    ; return to shader part epilog
20  %x = add i32 %a, %b
21  %result = shl i32 %x, %c
22  %bc = bitcast i32 %result to float
23  ret float %bc
24}
25
26define amdgpu_ps float @add_shl_vgpr_c(i32 inreg %a, i32 inreg %b, i32 %c) {
27; VI-LABEL: add_shl_vgpr_c:
28; VI:       ; %bb.0:
29; VI-NEXT:    s_add_i32 s2, s2, s3
30; VI-NEXT:    v_lshlrev_b32_e64 v0, v0, s2
31; VI-NEXT:    ; return to shader part epilog
32;
33; GFX9-LABEL: add_shl_vgpr_c:
34; GFX9:       ; %bb.0:
35; GFX9-NEXT:    s_add_i32 s2, s2, s3
36; GFX9-NEXT:    v_lshlrev_b32_e64 v0, v0, s2
37; GFX9-NEXT:    ; return to shader part epilog
38  %x = add i32 %a, %b
39  %result = shl i32 %x, %c
40  %bc = bitcast i32 %result to float
41  ret float %bc
42}
43
44define amdgpu_ps float @add_shl_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) {
45; VI-LABEL: add_shl_vgpr_ac:
46; VI:       ; %bb.0:
47; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v0
48; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
49; VI-NEXT:    ; return to shader part epilog
50;
51; GFX9-LABEL: add_shl_vgpr_ac:
52; GFX9:       ; %bb.0:
53; GFX9-NEXT:    v_add_lshl_u32 v0, v0, s2, v1
54; GFX9-NEXT:    ; return to shader part epilog
55  %x = add i32 %a, %b
56  %result = shl i32 %x, %c
57  %bc = bitcast i32 %result to float
58  ret float %bc
59}
60
61define amdgpu_ps float @add_shl_vgpr_const(i32 %a, i32 %b) {
62; VI-LABEL: add_shl_vgpr_const:
63; VI:       ; %bb.0:
64; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
65; VI-NEXT:    v_lshlrev_b32_e32 v0, 9, v0
66; VI-NEXT:    ; return to shader part epilog
67;
68; GFX9-LABEL: add_shl_vgpr_const:
69; GFX9:       ; %bb.0:
70; GFX9-NEXT:    v_add_lshl_u32 v0, v0, v1, 9
71; GFX9-NEXT:    ; return to shader part epilog
72  %x = add i32 %a, %b
73  %result = shl i32 %x, 9
74  %bc = bitcast i32 %result to float
75  ret float %bc
76}
77
78define amdgpu_ps float @add_shl_vgpr_const_inline_const(i32 %a) {
79; VI-LABEL: add_shl_vgpr_const_inline_const:
80; VI:       ; %bb.0:
81; VI-NEXT:    v_lshlrev_b32_e32 v0, 9, v0
82; VI-NEXT:    v_add_u32_e32 v0, vcc, 0x7e800, v0
83; VI-NEXT:    ; return to shader part epilog
84;
85; GFX9-LABEL: add_shl_vgpr_const_inline_const:
86; GFX9:       ; %bb.0:
87; GFX9-NEXT:    v_mov_b32_e32 v1, 0x7e800
88; GFX9-NEXT:    v_lshl_add_u32 v0, v0, 9, v1
89; GFX9-NEXT:    ; return to shader part epilog
90  %x = add i32 %a, 1012
91  %result = shl i32 %x, 9
92  %bc = bitcast i32 %result to float
93  ret float %bc
94}
95
96; TODO: Non-optimal code generation because SelectionDAG combines
97;       (shl (add x, CONST), y) ---> (add (shl x, y), CONST').
98;
99define amdgpu_ps float @add_shl_vgpr_inline_const_x2(i32 %a) {
100; VI-LABEL: add_shl_vgpr_inline_const_x2:
101; VI:       ; %bb.0:
102; VI-NEXT:    v_lshlrev_b32_e32 v0, 9, v0
103; VI-NEXT:    v_add_u32_e32 v0, vcc, 0x600, v0
104; VI-NEXT:    ; return to shader part epilog
105;
106; GFX9-LABEL: add_shl_vgpr_inline_const_x2:
107; GFX9:       ; %bb.0:
108; GFX9-NEXT:    v_mov_b32_e32 v1, 0x600
109; GFX9-NEXT:    v_lshl_add_u32 v0, v0, 9, v1
110; GFX9-NEXT:    ; return to shader part epilog
111  %x = add i32 %a, 3
112  %result = shl i32 %x, 9
113  %bc = bitcast i32 %result to float
114  ret float %bc
115}
116