1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
3; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
4; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
5
6; ===================================================================================
7; V_ADD3_U32
8; ===================================================================================
9
10define amdgpu_ps float @add3(i32 %a, i32 %b, i32 %c) {
11; VI-LABEL: add3:
12; VI:       ; %bb.0:
13; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
14; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
15; VI-NEXT:    ; return to shader part epilog
16;
17; GFX9-LABEL: add3:
18; GFX9:       ; %bb.0:
19; GFX9-NEXT:    v_add3_u32 v0, v0, v1, v2
20; GFX9-NEXT:    ; return to shader part epilog
21;
22; GFX10-LABEL: add3:
23; GFX10:       ; %bb.0:
24; GFX10-NEXT:    v_add3_u32 v0, v0, v1, v2
25; GFX10-NEXT:    ; return to shader part epilog
26  %x = add i32 %a, %b
27  %result = add i32 %x, %c
28  %bc = bitcast i32 %result to float
29  ret float %bc
30}
31
32; V_MAD_U32_U24 is given higher priority.
33define amdgpu_ps float @mad_no_add3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
34; VI-LABEL: mad_no_add3:
35; VI:       ; %bb.0:
36; VI-NEXT:    v_mad_u32_u24 v0, v0, v1, v4
37; VI-NEXT:    v_mad_u32_u24 v0, v2, v3, v0
38; VI-NEXT:    ; return to shader part epilog
39;
40; GFX9-LABEL: mad_no_add3:
41; GFX9:       ; %bb.0:
42; GFX9-NEXT:    v_mad_u32_u24 v0, v0, v1, v4
43; GFX9-NEXT:    v_mad_u32_u24 v0, v2, v3, v0
44; GFX9-NEXT:    ; return to shader part epilog
45;
46; GFX10-LABEL: mad_no_add3:
47; GFX10:       ; %bb.0:
48; GFX10-NEXT:    v_mad_u32_u24 v0, v0, v1, v4
49; GFX10-NEXT:    v_mad_u32_u24 v0, v2, v3, v0
50; GFX10-NEXT:    ; return to shader part epilog
51  %a0 = shl i32 %a, 8
52  %a1 = lshr i32 %a0, 8
53  %b0 = shl i32 %b, 8
54  %b1 = lshr i32 %b0, 8
55  %mul1 = mul i32 %a1, %b1
56
57  %c0 = shl i32 %c, 8
58  %c1 = lshr i32 %c0, 8
59  %d0 = shl i32 %d, 8
60  %d1 = lshr i32 %d0, 8
61  %mul2 = mul i32 %c1, %d1
62
63  %add0 = add i32 %e, %mul1
64  %add1 = add i32 %mul2, %add0
65
66  %bc = bitcast i32 %add1 to float
67  ret float %bc
68}
69
70; ThreeOp instruction variant not used due to Constant Bus Limitations
71; TODO: with reassociation it is possible to replace a v_add_u32_e32 with a s_add_i32
72define amdgpu_ps float @add3_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {
73; VI-LABEL: add3_vgpr_b:
74; VI:       ; %bb.0:
75; VI-NEXT:    s_add_i32 s3, s3, s2
76; VI-NEXT:    v_add_u32_e32 v0, vcc, s3, v0
77; VI-NEXT:    ; return to shader part epilog
78;
79; GFX9-LABEL: add3_vgpr_b:
80; GFX9:       ; %bb.0:
81; GFX9-NEXT:    s_add_i32 s3, s3, s2
82; GFX9-NEXT:    v_add_u32_e32 v0, s3, v0
83; GFX9-NEXT:    ; return to shader part epilog
84;
85; GFX10-LABEL: add3_vgpr_b:
86; GFX10:       ; %bb.0:
87; GFX10-NEXT:    v_add3_u32 v0, s3, s2, v0
88; GFX10-NEXT:    ; return to shader part epilog
89  %x = add i32 %a, %b
90  %result = add i32 %x, %c
91  %bc = bitcast i32 %result to float
92  ret float %bc
93}
94
95define amdgpu_ps float @add3_vgpr_all2(i32 %a, i32 %b, i32 %c) {
96; VI-LABEL: add3_vgpr_all2:
97; VI:       ; %bb.0:
98; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v2
99; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
100; VI-NEXT:    ; return to shader part epilog
101;
102; GFX9-LABEL: add3_vgpr_all2:
103; GFX9:       ; %bb.0:
104; GFX9-NEXT:    v_add3_u32 v0, v1, v2, v0
105; GFX9-NEXT:    ; return to shader part epilog
106;
107; GFX10-LABEL: add3_vgpr_all2:
108; GFX10:       ; %bb.0:
109; GFX10-NEXT:    v_add3_u32 v0, v1, v2, v0
110; GFX10-NEXT:    ; return to shader part epilog
111  %x = add i32 %b, %c
112  %result = add i32 %a, %x
113  %bc = bitcast i32 %result to float
114  ret float %bc
115}
116
117define amdgpu_ps float @add3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) {
118; VI-LABEL: add3_vgpr_bc:
119; VI:       ; %bb.0:
120; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v0
121; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
122; VI-NEXT:    ; return to shader part epilog
123;
124; GFX9-LABEL: add3_vgpr_bc:
125; GFX9:       ; %bb.0:
126; GFX9-NEXT:    v_add3_u32 v0, s2, v0, v1
127; GFX9-NEXT:    ; return to shader part epilog
128;
129; GFX10-LABEL: add3_vgpr_bc:
130; GFX10:       ; %bb.0:
131; GFX10-NEXT:    v_add3_u32 v0, s2, v0, v1
132; GFX10-NEXT:    ; return to shader part epilog
133  %x = add i32 %a, %b
134  %result = add i32 %x, %c
135  %bc = bitcast i32 %result to float
136  ret float %bc
137}
138
139define amdgpu_ps float @add3_vgpr_const(i32 %a, i32 %b) {
140; VI-LABEL: add3_vgpr_const:
141; VI:       ; %bb.0:
142; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
143; VI-NEXT:    v_add_u32_e32 v0, vcc, 16, v0
144; VI-NEXT:    ; return to shader part epilog
145;
146; GFX9-LABEL: add3_vgpr_const:
147; GFX9:       ; %bb.0:
148; GFX9-NEXT:    v_add3_u32 v0, v0, v1, 16
149; GFX9-NEXT:    ; return to shader part epilog
150;
151; GFX10-LABEL: add3_vgpr_const:
152; GFX10:       ; %bb.0:
153; GFX10-NEXT:    v_add3_u32 v0, v0, v1, 16
154; GFX10-NEXT:    ; return to shader part epilog
155  %x = add i32 %a, %b
156  %result = add i32 %x, 16
157  %bc = bitcast i32 %result to float
158  ret float %bc
159}
160
161define amdgpu_ps <2 x float> @add3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x) {
162; VI-LABEL: add3_multiuse_outer:
163; VI:       ; %bb.0:
164; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
165; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
166; VI-NEXT:    v_mul_lo_u32 v1, v0, v3
167; VI-NEXT:    ; return to shader part epilog
168;
169; GFX9-LABEL: add3_multiuse_outer:
170; GFX9:       ; %bb.0:
171; GFX9-NEXT:    v_add3_u32 v0, v0, v1, v2
172; GFX9-NEXT:    v_mul_lo_u32 v1, v0, v3
173; GFX9-NEXT:    ; return to shader part epilog
174;
175; GFX10-LABEL: add3_multiuse_outer:
176; GFX10:       ; %bb.0:
177; GFX10-NEXT:    v_add3_u32 v0, v0, v1, v2
178; GFX10-NEXT:    v_mul_lo_u32 v1, v0, v3
179; GFX10-NEXT:    ; return to shader part epilog
180  %inner = add i32 %a, %b
181  %outer = add i32 %inner, %c
182  %x1 = mul i32 %outer, %x
183  %r1 = insertelement <2 x i32> undef, i32 %outer, i32 0
184  %r0 = insertelement <2 x i32> %r1, i32 %x1, i32 1
185  %bc = bitcast <2 x i32> %r0 to <2 x float>
186  ret <2 x float> %bc
187}
188
189define amdgpu_ps <2 x float> @add3_multiuse_inner(i32 %a, i32 %b, i32 %c) {
190; VI-LABEL: add3_multiuse_inner:
191; VI:       ; %bb.0:
192; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
193; VI-NEXT:    v_add_u32_e32 v1, vcc, v0, v2
194; VI-NEXT:    ; return to shader part epilog
195;
196; GFX9-LABEL: add3_multiuse_inner:
197; GFX9:       ; %bb.0:
198; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
199; GFX9-NEXT:    v_add_u32_e32 v1, v0, v2
200; GFX9-NEXT:    ; return to shader part epilog
201;
202; GFX10-LABEL: add3_multiuse_inner:
203; GFX10:       ; %bb.0:
204; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1
205; GFX10-NEXT:    v_add_nc_u32_e32 v1, v0, v2
206; GFX10-NEXT:    ; return to shader part epilog
207  %inner = add i32 %a, %b
208  %outer = add i32 %inner, %c
209  %r1 = insertelement <2 x i32> undef, i32 %inner, i32 0
210  %r0 = insertelement <2 x i32> %r1, i32 %outer, i32 1
211  %bc = bitcast <2 x i32> %r0 to <2 x float>
212  ret <2 x float> %bc
213}
214
215; A case where uniform values end up in VGPRs -- we could use v_add3_u32 here,
216; but we don't.
217define amdgpu_ps float @add3_uniform_vgpr(float inreg %a, float inreg %b, float inreg %c) {
218; VI-LABEL: add3_uniform_vgpr:
219; VI:       ; %bb.0:
220; VI-NEXT:    v_add_f32_e64 v0, s2, 1.0
221; VI-NEXT:    v_add_f32_e64 v1, s3, 2.0
222; VI-NEXT:    v_mov_b32_e32 v2, 0x40400000
223; VI-NEXT:    v_add_f32_e32 v2, s4, v2
224; VI-NEXT:    v_add_u32_e32 v0, vcc, v1, v0
225; VI-NEXT:    v_add_u32_e32 v0, vcc, v2, v0
226; VI-NEXT:    ; return to shader part epilog
227;
228; GFX9-LABEL: add3_uniform_vgpr:
229; GFX9:       ; %bb.0:
230; GFX9-NEXT:    v_add_f32_e64 v0, s2, 1.0
231; GFX9-NEXT:    v_add_f32_e64 v1, s3, 2.0
232; GFX9-NEXT:    v_mov_b32_e32 v2, 0x40400000
233; GFX9-NEXT:    v_add_f32_e32 v2, s4, v2
234; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
235; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
236; GFX9-NEXT:    ; return to shader part epilog
237;
238; GFX10-LABEL: add3_uniform_vgpr:
239; GFX10:       ; %bb.0:
240; GFX10-NEXT:    v_add_f32_e64 v0, s2, 1.0
241; GFX10-NEXT:    v_add_f32_e64 v1, s3, 2.0
242; GFX10-NEXT:    v_add_f32_e64 v2, 0x40400000, s4
243; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1
244; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v2
245; GFX10-NEXT:    ; return to shader part epilog
246  %a1 = fadd float %a, 1.0
247  %b2 = fadd float %b, 2.0
248  %c3 = fadd float %c, 3.0
249  %bc.a = bitcast float %a1 to i32
250  %bc.b = bitcast float %b2 to i32
251  %bc.c = bitcast float %c3 to i32
252  %x = add i32 %bc.a, %bc.b
253  %result = add i32 %x, %bc.c
254  %bc = bitcast i32 %result to float
255  ret float %bc
256}
257