1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
3; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
4; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
5
6; ===================================================================================
7; V_ADD3_U32
8; ===================================================================================
9
10define amdgpu_ps float @add3(i32 %a, i32 %b, i32 %c) {
11; VI-LABEL: add3:
12; VI:       ; %bb.0:
13; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
14; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
15; VI-NEXT:    ; return to shader part epilog
16;
17; GFX9-LABEL: add3:
18; GFX9:       ; %bb.0:
19; GFX9-NEXT:    v_add3_u32 v0, v0, v1, v2
20; GFX9-NEXT:    ; return to shader part epilog
21;
22; GFX10-LABEL: add3:
23; GFX10:       ; %bb.0:
24; GFX10-NEXT:    v_add3_u32 v0, v0, v1, v2
25; GFX10-NEXT:    ; implicit-def: $vcc_hi
26; GFX10-NEXT:    ; return to shader part epilog
27  %x = add i32 %a, %b
28  %result = add i32 %x, %c
29  %bc = bitcast i32 %result to float
30  ret float %bc
31}
32
33; V_MAD_U32_U24 is given higher priority.
34define amdgpu_ps float @mad_no_add3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
35; VI-LABEL: mad_no_add3:
36; VI:       ; %bb.0:
37; VI-NEXT:    v_mad_u32_u24 v0, v0, v1, v4
38; VI-NEXT:    v_mad_u32_u24 v0, v2, v3, v0
39; VI-NEXT:    ; return to shader part epilog
40;
41; GFX9-LABEL: mad_no_add3:
42; GFX9:       ; %bb.0:
43; GFX9-NEXT:    v_mad_u32_u24 v0, v0, v1, v4
44; GFX9-NEXT:    v_mad_u32_u24 v0, v2, v3, v0
45; GFX9-NEXT:    ; return to shader part epilog
46;
47; GFX10-LABEL: mad_no_add3:
48; GFX10:       ; %bb.0:
49; GFX10-NEXT:    v_mad_u32_u24 v0, v0, v1, v4
50; GFX10-NEXT:    ; implicit-def: $vcc_hi
51; GFX10-NEXT:    v_mad_u32_u24 v0, v2, v3, v0
52; GFX10-NEXT:    ; return to shader part epilog
53  %a0 = shl i32 %a, 8
54  %a1 = lshr i32 %a0, 8
55  %b0 = shl i32 %b, 8
56  %b1 = lshr i32 %b0, 8
57  %mul1 = mul i32 %a1, %b1
58
59  %c0 = shl i32 %c, 8
60  %c1 = lshr i32 %c0, 8
61  %d0 = shl i32 %d, 8
62  %d1 = lshr i32 %d0, 8
63  %mul2 = mul i32 %c1, %d1
64
65  %add0 = add i32 %e, %mul1
66  %add1 = add i32 %mul2, %add0
67
68  %bc = bitcast i32 %add1 to float
69  ret float %bc
70}
71
72; ThreeOp instruction variant not used due to Constant Bus Limitations
73; TODO: with reassociation it is possible to replace a v_add_u32_e32 with a s_add_i32
74define amdgpu_ps float @add3_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {
75; VI-LABEL: add3_vgpr_b:
76; VI:       ; %bb.0:
77; VI-NEXT:    s_add_i32 s3, s3, s2
78; VI-NEXT:    v_add_u32_e32 v0, vcc, s3, v0
79; VI-NEXT:    ; return to shader part epilog
80;
81; GFX9-LABEL: add3_vgpr_b:
82; GFX9:       ; %bb.0:
83; GFX9-NEXT:    s_add_i32 s3, s3, s2
84; GFX9-NEXT:    v_add_u32_e32 v0, s3, v0
85; GFX9-NEXT:    ; return to shader part epilog
86;
87; GFX10-LABEL: add3_vgpr_b:
88; GFX10:       ; %bb.0:
89; GFX10-NEXT:    v_add3_u32 v0, s3, s2, v0
90; GFX10-NEXT:    ; implicit-def: $vcc_hi
91; GFX10-NEXT:    ; return to shader part epilog
92  %x = add i32 %a, %b
93  %result = add i32 %x, %c
94  %bc = bitcast i32 %result to float
95  ret float %bc
96}
97
98define amdgpu_ps float @add3_vgpr_all2(i32 %a, i32 %b, i32 %c) {
99; VI-LABEL: add3_vgpr_all2:
100; VI:       ; %bb.0:
101; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v2
102; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
103; VI-NEXT:    ; return to shader part epilog
104;
105; GFX9-LABEL: add3_vgpr_all2:
106; GFX9:       ; %bb.0:
107; GFX9-NEXT:    v_add3_u32 v0, v1, v2, v0
108; GFX9-NEXT:    ; return to shader part epilog
109;
110; GFX10-LABEL: add3_vgpr_all2:
111; GFX10:       ; %bb.0:
112; GFX10-NEXT:    v_add3_u32 v0, v1, v2, v0
113; GFX10-NEXT:    ; implicit-def: $vcc_hi
114; GFX10-NEXT:    ; return to shader part epilog
115  %x = add i32 %b, %c
116  %result = add i32 %a, %x
117  %bc = bitcast i32 %result to float
118  ret float %bc
119}
120
121define amdgpu_ps float @add3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) {
122; VI-LABEL: add3_vgpr_bc:
123; VI:       ; %bb.0:
124; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v0
125; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
126; VI-NEXT:    ; return to shader part epilog
127;
128; GFX9-LABEL: add3_vgpr_bc:
129; GFX9:       ; %bb.0:
130; GFX9-NEXT:    v_add3_u32 v0, s2, v0, v1
131; GFX9-NEXT:    ; return to shader part epilog
132;
133; GFX10-LABEL: add3_vgpr_bc:
134; GFX10:       ; %bb.0:
135; GFX10-NEXT:    v_add3_u32 v0, s2, v0, v1
136; GFX10-NEXT:    ; implicit-def: $vcc_hi
137; GFX10-NEXT:    ; return to shader part epilog
138  %x = add i32 %a, %b
139  %result = add i32 %x, %c
140  %bc = bitcast i32 %result to float
141  ret float %bc
142}
143
144define amdgpu_ps float @add3_vgpr_const(i32 %a, i32 %b) {
145; VI-LABEL: add3_vgpr_const:
146; VI:       ; %bb.0:
147; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
148; VI-NEXT:    v_add_u32_e32 v0, vcc, 16, v0
149; VI-NEXT:    ; return to shader part epilog
150;
151; GFX9-LABEL: add3_vgpr_const:
152; GFX9:       ; %bb.0:
153; GFX9-NEXT:    v_add3_u32 v0, v0, v1, 16
154; GFX9-NEXT:    ; return to shader part epilog
155;
156; GFX10-LABEL: add3_vgpr_const:
157; GFX10:       ; %bb.0:
158; GFX10-NEXT:    v_add3_u32 v0, v0, v1, 16
159; GFX10-NEXT:    ; implicit-def: $vcc_hi
160; GFX10-NEXT:    ; return to shader part epilog
161  %x = add i32 %a, %b
162  %result = add i32 %x, 16
163  %bc = bitcast i32 %result to float
164  ret float %bc
165}
166
167define amdgpu_ps <2 x float> @add3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x) {
168; VI-LABEL: add3_multiuse_outer:
169; VI:       ; %bb.0:
170; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
171; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
172; VI-NEXT:    v_mul_lo_u32 v1, v0, v3
173; VI-NEXT:    ; return to shader part epilog
174;
175; GFX9-LABEL: add3_multiuse_outer:
176; GFX9:       ; %bb.0:
177; GFX9-NEXT:    v_add3_u32 v0, v0, v1, v2
178; GFX9-NEXT:    v_mul_lo_u32 v1, v0, v3
179; GFX9-NEXT:    ; return to shader part epilog
180;
181; GFX10-LABEL: add3_multiuse_outer:
182; GFX10:       ; %bb.0:
183; GFX10-NEXT:    v_add3_u32 v0, v0, v1, v2
184; GFX10-NEXT:    ; implicit-def: $vcc_hi
185; GFX10-NEXT:    v_mul_lo_u32 v1, v0, v3
186; GFX10-NEXT:    ; return to shader part epilog
187  %inner = add i32 %a, %b
188  %outer = add i32 %inner, %c
189  %x1 = mul i32 %outer, %x
190  %r1 = insertelement <2 x i32> undef, i32 %outer, i32 0
191  %r0 = insertelement <2 x i32> %r1, i32 %x1, i32 1
192  %bc = bitcast <2 x i32> %r0 to <2 x float>
193  ret <2 x float> %bc
194}
195
196define amdgpu_ps <2 x float> @add3_multiuse_inner(i32 %a, i32 %b, i32 %c) {
197; VI-LABEL: add3_multiuse_inner:
198; VI:       ; %bb.0:
199; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
200; VI-NEXT:    v_add_u32_e32 v1, vcc, v0, v2
201; VI-NEXT:    ; return to shader part epilog
202;
203; GFX9-LABEL: add3_multiuse_inner:
204; GFX9:       ; %bb.0:
205; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
206; GFX9-NEXT:    v_add_u32_e32 v1, v0, v2
207; GFX9-NEXT:    ; return to shader part epilog
208;
209; GFX10-LABEL: add3_multiuse_inner:
210; GFX10:       ; %bb.0:
211; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1
212; GFX10-NEXT:    ; implicit-def: $vcc_hi
213; GFX10-NEXT:    v_add_nc_u32_e32 v1, v0, v2
214; GFX10-NEXT:    ; return to shader part epilog
215  %inner = add i32 %a, %b
216  %outer = add i32 %inner, %c
217  %r1 = insertelement <2 x i32> undef, i32 %inner, i32 0
218  %r0 = insertelement <2 x i32> %r1, i32 %outer, i32 1
219  %bc = bitcast <2 x i32> %r0 to <2 x float>
220  ret <2 x float> %bc
221}
222
223; A case where uniform values end up in VGPRs -- we could use v_add3_u32 here,
224; but we don't.
225define amdgpu_ps float @add3_uniform_vgpr(float inreg %a, float inreg %b, float inreg %c) {
226; VI-LABEL: add3_uniform_vgpr:
227; VI:       ; %bb.0:
228; VI-NEXT:    v_mov_b32_e32 v2, 0x40400000
229; VI-NEXT:    v_add_f32_e64 v0, s2, 1.0
230; VI-NEXT:    v_add_f32_e64 v1, s3, 2.0
231; VI-NEXT:    v_add_f32_e32 v2, s4, v2
232; VI-NEXT:    v_add_u32_e32 v0, vcc, v1, v0
233; VI-NEXT:    v_add_u32_e32 v0, vcc, v2, v0
234; VI-NEXT:    ; return to shader part epilog
235;
236; GFX9-LABEL: add3_uniform_vgpr:
237; GFX9:       ; %bb.0:
238; GFX9-NEXT:    v_mov_b32_e32 v2, 0x40400000
239; GFX9-NEXT:    v_add_f32_e64 v0, s2, 1.0
240; GFX9-NEXT:    v_add_f32_e64 v1, s3, 2.0
241; GFX9-NEXT:    v_add_f32_e32 v2, s4, v2
242; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
243; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
244; GFX9-NEXT:    ; return to shader part epilog
245;
246; GFX10-LABEL: add3_uniform_vgpr:
247; GFX10:       ; %bb.0:
248; GFX10-NEXT:    v_add_f32_e64 v0, s2, 1.0
249; GFX10-NEXT:    v_add_f32_e64 v1, s3, 2.0
250; GFX10-NEXT:    v_add_f32_e64 v2, 0x40400000, s4
251; GFX10-NEXT:    ; implicit-def: $vcc_hi
252; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1
253; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v2
254; GFX10-NEXT:    ; return to shader part epilog
255  %a1 = fadd float %a, 1.0
256  %b2 = fadd float %b, 2.0
257  %c3 = fadd float %c, 3.0
258  %bc.a = bitcast float %a1 to i32
259  %bc.b = bitcast float %b2 to i32
260  %bc.c = bitcast float %c3 to i32
261  %x = add i32 %bc.a, %bc.b
262  %result = add i32 %x, %bc.c
263  %bc = bitcast i32 %result to float
264  ret float %bc
265}
266