1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s
3; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
4
5define i32 @test_min_max_ValK0_K1_u32(i32 %a) {
6; GFX9-LABEL: test_min_max_ValK0_K1_u32:
7; GFX9:       ; %bb.0:
8; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
9; GFX9-NEXT:    v_med3_u32 v0, v0, 12, 17
10; GFX9-NEXT:    s_setpc_b64 s[30:31]
11;
12; GFX10-LABEL: test_min_max_ValK0_K1_u32:
13; GFX10:       ; %bb.0:
14; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
15; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
16; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
17; GFX10-NEXT:    s_setpc_b64 s[30:31]
18  %umax = call i32 @llvm.umax.i32(i32 %a, i32 12)
19  %umed = call i32 @llvm.umin.i32(i32 %umax, i32 17)
20  ret i32 %umed
21}
22
23define i32 @min_max_ValK0_K1_i32(i32 %a) {
24; GFX9-LABEL: min_max_ValK0_K1_i32:
25; GFX9:       ; %bb.0:
26; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
27; GFX9-NEXT:    v_med3_u32 v0, v0, 12, 17
28; GFX9-NEXT:    s_setpc_b64 s[30:31]
29;
30; GFX10-LABEL: min_max_ValK0_K1_i32:
31; GFX10:       ; %bb.0:
32; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
33; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
34; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
35; GFX10-NEXT:    s_setpc_b64 s[30:31]
36  %umax = call i32 @llvm.umax.i32(i32 12, i32 %a)
37  %umed = call i32 @llvm.umin.i32(i32 %umax, i32 17)
38  ret i32 %umed
39}
40
41define i32 @test_min_K1max_ValK0__u32(i32 %a) {
42; GFX9-LABEL: test_min_K1max_ValK0__u32:
43; GFX9:       ; %bb.0:
44; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
45; GFX9-NEXT:    v_med3_u32 v0, v0, 12, 17
46; GFX9-NEXT:    s_setpc_b64 s[30:31]
47;
48; GFX10-LABEL: test_min_K1max_ValK0__u32:
49; GFX10:       ; %bb.0:
50; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
51; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
52; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
53; GFX10-NEXT:    s_setpc_b64 s[30:31]
54  %umax = call i32 @llvm.umax.i32(i32 %a, i32 12)
55  %umed = call i32 @llvm.umin.i32(i32 17, i32 %umax)
56  ret i32 %umed
57}
58
59define i32 @test_min_K1max_K0Val__u32(i32 %a) {
60; GFX9-LABEL: test_min_K1max_K0Val__u32:
61; GFX9:       ; %bb.0:
62; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
63; GFX9-NEXT:    v_med3_u32 v0, v0, 12, 17
64; GFX9-NEXT:    s_setpc_b64 s[30:31]
65;
66; GFX10-LABEL: test_min_K1max_K0Val__u32:
67; GFX10:       ; %bb.0:
68; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
69; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
70; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
71; GFX10-NEXT:    s_setpc_b64 s[30:31]
72  %umax = call i32 @llvm.umax.i32(i32 12, i32 %a)
73  %umed = call i32 @llvm.umin.i32(i32 17, i32 %umax)
74  ret i32 %umed
75}
76
77define i32 @test_max_min_ValK1_K0_u32(i32 %a) {
78; GFX9-LABEL: test_max_min_ValK1_K0_u32:
79; GFX9:       ; %bb.0:
80; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
81; GFX9-NEXT:    v_med3_u32 v0, v0, 12, 17
82; GFX9-NEXT:    s_setpc_b64 s[30:31]
83;
84; GFX10-LABEL: test_max_min_ValK1_K0_u32:
85; GFX10:       ; %bb.0:
86; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
87; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
88; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
89; GFX10-NEXT:    s_setpc_b64 s[30:31]
90  %umin = call i32 @llvm.umin.i32(i32 %a, i32 17)
91  %umed = call i32 @llvm.umax.i32(i32 %umin, i32 12)
92  ret i32 %umed
93}
94
95define i32 @test_max_min_K1Val_K0_u32(i32 %a) {
96; GFX9-LABEL: test_max_min_K1Val_K0_u32:
97; GFX9:       ; %bb.0:
98; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
99; GFX9-NEXT:    v_med3_u32 v0, v0, 12, 17
100; GFX9-NEXT:    s_setpc_b64 s[30:31]
101;
102; GFX10-LABEL: test_max_min_K1Val_K0_u32:
103; GFX10:       ; %bb.0:
104; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
105; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
106; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
107; GFX10-NEXT:    s_setpc_b64 s[30:31]
108  %umin = call i32 @llvm.umin.i32(i32 17, i32 %a)
109  %umed = call i32 @llvm.umax.i32(i32 %umin, i32 12)
110  ret i32 %umed
111}
112
113define i32 @test_max_K0min_ValK1__u32(i32 %a) {
114; GFX9-LABEL: test_max_K0min_ValK1__u32:
115; GFX9:       ; %bb.0:
116; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
117; GFX9-NEXT:    v_med3_u32 v0, v0, 12, 17
118; GFX9-NEXT:    s_setpc_b64 s[30:31]
119;
120; GFX10-LABEL: test_max_K0min_ValK1__u32:
121; GFX10:       ; %bb.0:
122; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
123; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
124; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
125; GFX10-NEXT:    s_setpc_b64 s[30:31]
126  %umin = call i32 @llvm.umin.i32(i32 %a, i32 17)
127  %umed = call i32 @llvm.umax.i32(i32 12, i32 %umin)
128  ret i32 %umed
129}
130
131define i32 @test_max_K0min_K1Val__u32(i32 %a) {
132; GFX9-LABEL: test_max_K0min_K1Val__u32:
133; GFX9:       ; %bb.0:
134; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
135; GFX9-NEXT:    v_med3_u32 v0, v0, 12, 17
136; GFX9-NEXT:    s_setpc_b64 s[30:31]
137;
138; GFX10-LABEL: test_max_K0min_K1Val__u32:
139; GFX10:       ; %bb.0:
140; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
141; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
142; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
143; GFX10-NEXT:    s_setpc_b64 s[30:31]
144  %umin = call i32 @llvm.umin.i32(i32 17, i32 %a)
145  %umed = call i32 @llvm.umax.i32(i32 12, i32 %umin)
146  ret i32 %umed
147}
148
149define <2 x i16> @test_max_K0min_K1Val__v2u16(<2 x i16> %a) {
150; GFX9-LABEL: test_max_K0min_K1Val__v2u16:
151; GFX9:       ; %bb.0:
152; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
153; GFX9-NEXT:    v_pk_min_u16 v0, 17, v0 op_sel_hi:[0,1]
154; GFX9-NEXT:    v_pk_max_u16 v0, 12, v0 op_sel_hi:[0,1]
155; GFX9-NEXT:    s_setpc_b64 s[30:31]
156;
157; GFX10-LABEL: test_max_K0min_K1Val__v2u16:
158; GFX10:       ; %bb.0:
159; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
160; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
161; GFX10-NEXT:    v_pk_min_u16 v0, 17, v0 op_sel_hi:[0,1]
162; GFX10-NEXT:    v_pk_max_u16 v0, 12, v0 op_sel_hi:[0,1]
163; GFX10-NEXT:    s_setpc_b64 s[30:31]
164  %umin = call <2 x i16> @llvm.umin.v2i16(<2 x i16> <i16 17, i16 17>, <2 x i16> %a)
165  %umed = call <2 x i16> @llvm.umax.v2i16(<2 x i16> <i16 12, i16 12>, <2 x i16> %umin)
166  ret <2 x i16> %umed
167}
168
169define amdgpu_ps i32 @test_uniform_min_max(i32 inreg %a) {
170; GFX9-LABEL: test_uniform_min_max:
171; GFX9:       ; %bb.0:
172; GFX9-NEXT:    s_max_u32 s0, s2, 12
173; GFX9-NEXT:    s_min_u32 s0, s0, 17
174; GFX9-NEXT:    ; return to shader part epilog
175;
176; GFX10-LABEL: test_uniform_min_max:
177; GFX10:       ; %bb.0:
178; GFX10-NEXT:    s_max_u32 s0, s2, 12
179; GFX10-NEXT:    s_min_u32 s0, s0, 17
180; GFX10-NEXT:    ; return to shader part epilog
181  %umax = call i32 @llvm.umax.i32(i32 %a, i32 12)
182  %umed = call i32 @llvm.umin.i32(i32 %umax, i32 17)
183  ret i32 %umed
184}
185
186define i32 @test_non_inline_constant_u32(i32 %a) {
187; GFX9-LABEL: test_non_inline_constant_u32:
188; GFX9:       ; %bb.0:
189; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
190; GFX9-NEXT:    v_mov_b32_e32 v1, 0x41
191; GFX9-NEXT:    v_med3_u32 v0, v0, 12, v1
192; GFX9-NEXT:    s_setpc_b64 s[30:31]
193;
194; GFX10-LABEL: test_non_inline_constant_u32:
195; GFX10:       ; %bb.0:
196; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
197; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
198; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 0x41
199; GFX10-NEXT:    s_setpc_b64 s[30:31]
200  %umax = call i32 @llvm.umax.i32(i32 %a, i32 12)
201  %umed = call i32 @llvm.umin.i32(i32 %umax, i32 65)
202  ret i32 %umed
203}
204
205declare i32 @llvm.umin.i32(i32, i32)
206declare i32 @llvm.umax.i32(i32, i32)
207declare <2 x i16> @llvm.umin.v2i16(<2 x i16>, <2 x i16>)
208declare <2 x i16> @llvm.umax.v2i16(<2 x i16>, <2 x i16>)
209