1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s 3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s 4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s 5; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s 6 7define i8 @v_shl_i8(i8 %value, i8 %amount) { 8; GFX6-LABEL: v_shl_i8: 9; GFX6: ; %bb.0: 10; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 11; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1 12; GFX6-NEXT: v_lshlrev_b32_e32 v0, v1, v0 13; GFX6-NEXT: s_setpc_b64 s[30:31] 14; 15; GFX8-LABEL: v_shl_i8: 16; GFX8: ; %bb.0: 17; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 18; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD 19; GFX8-NEXT: s_setpc_b64 s[30:31] 20; 21; GFX9-LABEL: v_shl_i8: 22; GFX9: ; %bb.0: 23; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 24; GFX9-NEXT: v_lshlrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD 25; GFX9-NEXT: s_setpc_b64 s[30:31] 26; 27; GFX10-LABEL: v_shl_i8: 28; GFX10: ; %bb.0: 29; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 30; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 31; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1 32; GFX10-NEXT: v_lshlrev_b16 v0, v1, v0 33; GFX10-NEXT: s_setpc_b64 s[30:31] 34 %result = shl i8 %value, %amount 35 ret i8 %result 36} 37 38define i8 @v_shl_i8_7(i8 %value) { 39; GFX6-LABEL: v_shl_i8_7: 40; GFX6: ; %bb.0: 41; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 42; GFX6-NEXT: v_lshlrev_b32_e32 v0, 7, v0 43; GFX6-NEXT: s_setpc_b64 s[30:31] 44; 45; GFX8-LABEL: v_shl_i8_7: 46; GFX8: ; %bb.0: 47; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 48; GFX8-NEXT: v_lshlrev_b16_e32 v0, 7, v0 49; GFX8-NEXT: s_setpc_b64 s[30:31] 50; 51; GFX9-LABEL: v_shl_i8_7: 52; GFX9: ; %bb.0: 53; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 54; GFX9-NEXT: v_lshlrev_b16_e32 v0, 7, v0 55; GFX9-NEXT: s_setpc_b64 s[30:31] 56; 57; GFX10-LABEL: v_shl_i8_7: 58; GFX10: ; %bb.0: 59; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 60; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 61; GFX10-NEXT: v_lshlrev_b16 v0, 7, v0 62; GFX10-NEXT: s_setpc_b64 s[30:31] 63 %result = shl i8 %value, 7 64 ret i8 %result 65} 66 67define amdgpu_ps i8 @s_shl_i8(i8 inreg %value, i8 inreg %amount) { 68; GFX6-LABEL: s_shl_i8: 69; GFX6: ; %bb.0: 70; GFX6-NEXT: s_and_b32 s1, s1, 0xff 71; GFX6-NEXT: s_lshl_b32 s0, s0, s1 72; GFX6-NEXT: ; return to shader part epilog 73; 74; GFX8-LABEL: s_shl_i8: 75; GFX8: ; %bb.0: 76; GFX8-NEXT: s_movk_i32 s2, 0xff 77; GFX8-NEXT: s_and_b32 s0, s0, s2 78; GFX8-NEXT: s_and_b32 s1, s1, s2 79; GFX8-NEXT: s_lshl_b32 s0, s0, s1 80; GFX8-NEXT: ; return to shader part epilog 81; 82; GFX9-LABEL: s_shl_i8: 83; GFX9: ; %bb.0: 84; GFX9-NEXT: s_movk_i32 s2, 0xff 85; GFX9-NEXT: s_and_b32 s0, s0, s2 86; GFX9-NEXT: s_and_b32 s1, s1, s2 87; GFX9-NEXT: s_lshl_b32 s0, s0, s1 88; GFX9-NEXT: ; return to shader part epilog 89; 90; GFX10-LABEL: s_shl_i8: 91; GFX10: ; %bb.0: 92; GFX10-NEXT: s_movk_i32 s2, 0xff 93; GFX10-NEXT: s_and_b32 s0, s0, s2 94; GFX10-NEXT: s_and_b32 s1, s1, s2 95; GFX10-NEXT: s_lshl_b32 s0, s0, s1 96; GFX10-NEXT: ; return to shader part epilog 97 %result = shl i8 %value, %amount 98 ret i8 %result 99} 100 101define amdgpu_ps i8 @s_shl_i8_7(i8 inreg %value) { 102; GFX6-LABEL: s_shl_i8_7: 103; GFX6: ; %bb.0: 104; GFX6-NEXT: s_lshl_b32 s0, s0, 7 105; GFX6-NEXT: ; return to shader part epilog 106; 107; GFX8-LABEL: s_shl_i8_7: 108; GFX8: ; %bb.0: 109; GFX8-NEXT: s_bfe_u32 s1, 7, 0x100000 110; GFX8-NEXT: s_lshl_b32 s0, s0, s1 111; GFX8-NEXT: ; return to shader part epilog 112; 113; GFX9-LABEL: s_shl_i8_7: 114; GFX9: ; %bb.0: 115; GFX9-NEXT: s_bfe_u32 s1, 7, 0x100000 116; GFX9-NEXT: s_lshl_b32 s0, s0, s1 117; GFX9-NEXT: ; return to shader part epilog 118; 119; GFX10-LABEL: s_shl_i8_7: 120; GFX10: ; %bb.0: 121; GFX10-NEXT: s_bfe_u32 s1, 7, 0x100000 122; GFX10-NEXT: s_lshl_b32 s0, s0, s1 123; GFX10-NEXT: ; return to shader part epilog 124 %result = shl i8 %value, 7 125 ret i8 %result 126} 127 128 129define i24 @v_shl_i24(i24 %value, i24 %amount) { 130; GCN-LABEL: v_shl_i24: 131; GCN: ; %bb.0: 132; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 133; GCN-NEXT: v_and_b32_e32 v1, 0xffffff, v1 134; GCN-NEXT: v_lshlrev_b32_e32 v0, v1, v0 135; GCN-NEXT: s_setpc_b64 s[30:31] 136; 137; GFX10-LABEL: v_shl_i24: 138; GFX10: ; %bb.0: 139; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 140; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 141; GFX10-NEXT: v_and_b32_e32 v1, 0xffffff, v1 142; GFX10-NEXT: v_lshlrev_b32_e32 v0, v1, v0 143; GFX10-NEXT: s_setpc_b64 s[30:31] 144 %result = shl i24 %value, %amount 145 ret i24 %result 146} 147 148define i24 @v_shl_i24_7(i24 %value) { 149; GCN-LABEL: v_shl_i24_7: 150; GCN: ; %bb.0: 151; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 152; GCN-NEXT: v_lshlrev_b32_e32 v0, 7, v0 153; GCN-NEXT: s_setpc_b64 s[30:31] 154; 155; GFX10-LABEL: v_shl_i24_7: 156; GFX10: ; %bb.0: 157; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 158; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 159; GFX10-NEXT: v_lshlrev_b32_e32 v0, 7, v0 160; GFX10-NEXT: s_setpc_b64 s[30:31] 161 %result = shl i24 %value, 7 162 ret i24 %result 163} 164 165define amdgpu_ps i24 @s_shl_i24(i24 inreg %value, i24 inreg %amount) { 166; GCN-LABEL: s_shl_i24: 167; GCN: ; %bb.0: 168; GCN-NEXT: s_and_b32 s1, s1, 0xffffff 169; GCN-NEXT: s_lshl_b32 s0, s0, s1 170; GCN-NEXT: ; return to shader part epilog 171; 172; GFX10-LABEL: s_shl_i24: 173; GFX10: ; %bb.0: 174; GFX10-NEXT: s_and_b32 s1, s1, 0xffffff 175; GFX10-NEXT: s_lshl_b32 s0, s0, s1 176; GFX10-NEXT: ; return to shader part epilog 177 %result = shl i24 %value, %amount 178 ret i24 %result 179} 180 181define amdgpu_ps i24 @s_shl_i24_7(i24 inreg %value) { 182; GCN-LABEL: s_shl_i24_7: 183; GCN: ; %bb.0: 184; GCN-NEXT: s_lshl_b32 s0, s0, 7 185; GCN-NEXT: ; return to shader part epilog 186; 187; GFX10-LABEL: s_shl_i24_7: 188; GFX10: ; %bb.0: 189; GFX10-NEXT: s_lshl_b32 s0, s0, 7 190; GFX10-NEXT: ; return to shader part epilog 191 %result = shl i24 %value, 7 192 ret i24 %result 193} 194 195define i32 @v_shl_i32(i32 %value, i32 %amount) { 196; GCN-LABEL: v_shl_i32: 197; GCN: ; %bb.0: 198; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 199; GCN-NEXT: v_lshlrev_b32_e32 v0, v1, v0 200; GCN-NEXT: s_setpc_b64 s[30:31] 201; 202; GFX10-LABEL: v_shl_i32: 203; GFX10: ; %bb.0: 204; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 205; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 206; GFX10-NEXT: v_lshlrev_b32_e32 v0, v1, v0 207; GFX10-NEXT: s_setpc_b64 s[30:31] 208 %result = shl i32 %value, %amount 209 ret i32 %result 210} 211 212define i32 @v_shl_i32_31(i32 %value) { 213; GCN-LABEL: v_shl_i32_31: 214; GCN: ; %bb.0: 215; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 216; GCN-NEXT: v_lshlrev_b32_e32 v0, 31, v0 217; GCN-NEXT: s_setpc_b64 s[30:31] 218; 219; GFX10-LABEL: v_shl_i32_31: 220; GFX10: ; %bb.0: 221; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 222; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 223; GFX10-NEXT: v_lshlrev_b32_e32 v0, 31, v0 224; GFX10-NEXT: s_setpc_b64 s[30:31] 225 %result = shl i32 %value, 31 226 ret i32 %result 227} 228 229define amdgpu_ps i32 @s_shl_i32(i32 inreg %value, i32 inreg %amount) { 230; GCN-LABEL: s_shl_i32: 231; GCN: ; %bb.0: 232; GCN-NEXT: s_lshl_b32 s0, s0, s1 233; GCN-NEXT: ; return to shader part epilog 234; 235; GFX10-LABEL: s_shl_i32: 236; GFX10: ; %bb.0: 237; GFX10-NEXT: s_lshl_b32 s0, s0, s1 238; GFX10-NEXT: ; return to shader part epilog 239 %result = shl i32 %value, %amount 240 ret i32 %result 241} 242 243define amdgpu_ps i32 @s_shl_i32_31(i32 inreg %value) { 244; GCN-LABEL: s_shl_i32_31: 245; GCN: ; %bb.0: 246; GCN-NEXT: s_lshl_b32 s0, s0, 31 247; GCN-NEXT: ; return to shader part epilog 248; 249; GFX10-LABEL: s_shl_i32_31: 250; GFX10: ; %bb.0: 251; GFX10-NEXT: s_lshl_b32 s0, s0, 31 252; GFX10-NEXT: ; return to shader part epilog 253 %result = shl i32 %value, 31 254 ret i32 %result 255} 256 257define amdgpu_ps float @shl_i32_sv(i32 inreg %value, i32 %amount) { 258; GFX6-LABEL: shl_i32_sv: 259; GFX6: ; %bb.0: 260; GFX6-NEXT: v_lshl_b32_e32 v0, s0, v0 261; GFX6-NEXT: ; return to shader part epilog 262; 263; GFX8-LABEL: shl_i32_sv: 264; GFX8: ; %bb.0: 265; GFX8-NEXT: v_lshlrev_b32_e64 v0, v0, s0 266; GFX8-NEXT: ; return to shader part epilog 267; 268; GFX9-LABEL: shl_i32_sv: 269; GFX9: ; %bb.0: 270; GFX9-NEXT: v_lshlrev_b32_e64 v0, v0, s0 271; GFX9-NEXT: ; return to shader part epilog 272; 273; GFX10-LABEL: shl_i32_sv: 274; GFX10: ; %bb.0: 275; GFX10-NEXT: v_lshlrev_b32_e64 v0, v0, s0 276; GFX10-NEXT: ; return to shader part epilog 277 %result = shl i32 %value, %amount 278 %cast = bitcast i32 %result to float 279 ret float %cast 280} 281 282define amdgpu_ps float @shl_i32_vs(i32 %value, i32 inreg %amount) { 283; GCN-LABEL: shl_i32_vs: 284; GCN: ; %bb.0: 285; GCN-NEXT: v_lshlrev_b32_e32 v0, s0, v0 286; GCN-NEXT: ; return to shader part epilog 287; 288; GFX10-LABEL: shl_i32_vs: 289; GFX10: ; %bb.0: 290; GFX10-NEXT: v_lshlrev_b32_e32 v0, s0, v0 291; GFX10-NEXT: ; return to shader part epilog 292 %result = shl i32 %value, %amount 293 %cast = bitcast i32 %result to float 294 ret float %cast 295} 296 297define <2 x i32> @v_shl_v2i32(<2 x i32> %value, <2 x i32> %amount) { 298; GCN-LABEL: v_shl_v2i32: 299; GCN: ; %bb.0: 300; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 301; GCN-NEXT: v_lshlrev_b32_e32 v0, v2, v0 302; GCN-NEXT: v_lshlrev_b32_e32 v1, v3, v1 303; GCN-NEXT: s_setpc_b64 s[30:31] 304; 305; GFX10-LABEL: v_shl_v2i32: 306; GFX10: ; %bb.0: 307; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 308; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 309; GFX10-NEXT: v_lshlrev_b32_e32 v0, v2, v0 310; GFX10-NEXT: v_lshlrev_b32_e32 v1, v3, v1 311; GFX10-NEXT: s_setpc_b64 s[30:31] 312 %result = shl <2 x i32> %value, %amount 313 ret <2 x i32> %result 314} 315 316define <2 x i32> @v_shl_v2i32_31(<2 x i32> %value) { 317; GCN-LABEL: v_shl_v2i32_31: 318; GCN: ; %bb.0: 319; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 320; GCN-NEXT: v_lshlrev_b32_e32 v0, 31, v0 321; GCN-NEXT: v_lshlrev_b32_e32 v1, 31, v1 322; GCN-NEXT: s_setpc_b64 s[30:31] 323; 324; GFX10-LABEL: v_shl_v2i32_31: 325; GFX10: ; %bb.0: 326; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 327; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 328; GFX10-NEXT: v_lshlrev_b32_e32 v0, 31, v0 329; GFX10-NEXT: v_lshlrev_b32_e32 v1, 31, v1 330; GFX10-NEXT: s_setpc_b64 s[30:31] 331 %result = shl <2 x i32> %value, <i32 31, i32 31> 332 ret <2 x i32> %result 333} 334 335define amdgpu_ps <2 x i32> @s_shl_v2i32(<2 x i32> inreg %value, <2 x i32> inreg %amount) { 336; GCN-LABEL: s_shl_v2i32: 337; GCN: ; %bb.0: 338; GCN-NEXT: s_lshl_b32 s0, s0, s2 339; GCN-NEXT: s_lshl_b32 s1, s1, s3 340; GCN-NEXT: ; return to shader part epilog 341; 342; GFX10-LABEL: s_shl_v2i32: 343; GFX10: ; %bb.0: 344; GFX10-NEXT: s_lshl_b32 s0, s0, s2 345; GFX10-NEXT: s_lshl_b32 s1, s1, s3 346; GFX10-NEXT: ; return to shader part epilog 347 %result = shl <2 x i32> %value, %amount 348 ret <2 x i32> %result 349} 350 351define <3 x i32> @v_shl_v3i32(<3 x i32> %value, <3 x i32> %amount) { 352; GCN-LABEL: v_shl_v3i32: 353; GCN: ; %bb.0: 354; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 355; GCN-NEXT: v_lshlrev_b32_e32 v0, v3, v0 356; GCN-NEXT: v_lshlrev_b32_e32 v1, v4, v1 357; GCN-NEXT: v_lshlrev_b32_e32 v2, v5, v2 358; GCN-NEXT: s_setpc_b64 s[30:31] 359; 360; GFX10-LABEL: v_shl_v3i32: 361; GFX10: ; %bb.0: 362; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 363; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 364; GFX10-NEXT: v_lshlrev_b32_e32 v0, v3, v0 365; GFX10-NEXT: v_lshlrev_b32_e32 v1, v4, v1 366; GFX10-NEXT: v_lshlrev_b32_e32 v2, v5, v2 367; GFX10-NEXT: s_setpc_b64 s[30:31] 368 %result = shl <3 x i32> %value, %amount 369 ret <3 x i32> %result 370} 371 372define amdgpu_ps <3 x i32> @s_shl_v3i32(<3 x i32> inreg %value, <3 x i32> inreg %amount) { 373; GCN-LABEL: s_shl_v3i32: 374; GCN: ; %bb.0: 375; GCN-NEXT: s_lshl_b32 s0, s0, s3 376; GCN-NEXT: s_lshl_b32 s1, s1, s4 377; GCN-NEXT: s_lshl_b32 s2, s2, s5 378; GCN-NEXT: ; return to shader part epilog 379; 380; GFX10-LABEL: s_shl_v3i32: 381; GFX10: ; %bb.0: 382; GFX10-NEXT: s_lshl_b32 s0, s0, s3 383; GFX10-NEXT: s_lshl_b32 s1, s1, s4 384; GFX10-NEXT: s_lshl_b32 s2, s2, s5 385; GFX10-NEXT: ; return to shader part epilog 386 %result = shl <3 x i32> %value, %amount 387 ret <3 x i32> %result 388} 389 390define <4 x i32> @v_shl_v4i32(<4 x i32> %value, <4 x i32> %amount) { 391; GCN-LABEL: v_shl_v4i32: 392; GCN: ; %bb.0: 393; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 394; GCN-NEXT: v_lshlrev_b32_e32 v0, v4, v0 395; GCN-NEXT: v_lshlrev_b32_e32 v1, v5, v1 396; GCN-NEXT: v_lshlrev_b32_e32 v2, v6, v2 397; GCN-NEXT: v_lshlrev_b32_e32 v3, v7, v3 398; GCN-NEXT: s_setpc_b64 s[30:31] 399; 400; GFX10-LABEL: v_shl_v4i32: 401; GFX10: ; %bb.0: 402; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 403; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 404; GFX10-NEXT: v_lshlrev_b32_e32 v0, v4, v0 405; GFX10-NEXT: v_lshlrev_b32_e32 v1, v5, v1 406; GFX10-NEXT: v_lshlrev_b32_e32 v2, v6, v2 407; GFX10-NEXT: v_lshlrev_b32_e32 v3, v7, v3 408; GFX10-NEXT: s_setpc_b64 s[30:31] 409 %result = shl <4 x i32> %value, %amount 410 ret <4 x i32> %result 411} 412 413define amdgpu_ps <4 x i32> @s_shl_v4i32(<4 x i32> inreg %value, <4 x i32> inreg %amount) { 414; GCN-LABEL: s_shl_v4i32: 415; GCN: ; %bb.0: 416; GCN-NEXT: s_lshl_b32 s0, s0, s4 417; GCN-NEXT: s_lshl_b32 s1, s1, s5 418; GCN-NEXT: s_lshl_b32 s2, s2, s6 419; GCN-NEXT: s_lshl_b32 s3, s3, s7 420; GCN-NEXT: ; return to shader part epilog 421; 422; GFX10-LABEL: s_shl_v4i32: 423; GFX10: ; %bb.0: 424; GFX10-NEXT: s_lshl_b32 s0, s0, s4 425; GFX10-NEXT: s_lshl_b32 s1, s1, s5 426; GFX10-NEXT: s_lshl_b32 s2, s2, s6 427; GFX10-NEXT: s_lshl_b32 s3, s3, s7 428; GFX10-NEXT: ; return to shader part epilog 429 %result = shl <4 x i32> %value, %amount 430 ret <4 x i32> %result 431} 432 433define <5 x i32> @v_shl_v5i32(<5 x i32> %value, <5 x i32> %amount) { 434; GCN-LABEL: v_shl_v5i32: 435; GCN: ; %bb.0: 436; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 437; GCN-NEXT: v_lshlrev_b32_e32 v0, v5, v0 438; GCN-NEXT: v_lshlrev_b32_e32 v1, v6, v1 439; GCN-NEXT: v_lshlrev_b32_e32 v2, v7, v2 440; GCN-NEXT: v_lshlrev_b32_e32 v3, v8, v3 441; GCN-NEXT: v_lshlrev_b32_e32 v4, v9, v4 442; GCN-NEXT: s_setpc_b64 s[30:31] 443; 444; GFX10-LABEL: v_shl_v5i32: 445; GFX10: ; %bb.0: 446; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 447; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 448; GFX10-NEXT: v_lshlrev_b32_e32 v0, v5, v0 449; GFX10-NEXT: v_lshlrev_b32_e32 v1, v6, v1 450; GFX10-NEXT: v_lshlrev_b32_e32 v2, v7, v2 451; GFX10-NEXT: v_lshlrev_b32_e32 v3, v8, v3 452; GFX10-NEXT: v_lshlrev_b32_e32 v4, v9, v4 453; GFX10-NEXT: s_setpc_b64 s[30:31] 454 %result = shl <5 x i32> %value, %amount 455 ret <5 x i32> %result 456} 457 458define amdgpu_ps <5 x i32> @s_shl_v5i32(<5 x i32> inreg %value, <5 x i32> inreg %amount) { 459; GCN-LABEL: s_shl_v5i32: 460; GCN: ; %bb.0: 461; GCN-NEXT: s_lshl_b32 s0, s0, s5 462; GCN-NEXT: s_lshl_b32 s1, s1, s6 463; GCN-NEXT: s_lshl_b32 s2, s2, s7 464; GCN-NEXT: s_lshl_b32 s3, s3, s8 465; GCN-NEXT: s_lshl_b32 s4, s4, s9 466; GCN-NEXT: ; return to shader part epilog 467; 468; GFX10-LABEL: s_shl_v5i32: 469; GFX10: ; %bb.0: 470; GFX10-NEXT: s_lshl_b32 s0, s0, s5 471; GFX10-NEXT: s_lshl_b32 s1, s1, s6 472; GFX10-NEXT: s_lshl_b32 s2, s2, s7 473; GFX10-NEXT: s_lshl_b32 s3, s3, s8 474; GFX10-NEXT: s_lshl_b32 s4, s4, s9 475; GFX10-NEXT: ; return to shader part epilog 476 %result = shl <5 x i32> %value, %amount 477 ret <5 x i32> %result 478} 479 480define <16 x i32> @v_shl_v16i32(<16 x i32> %value, <16 x i32> %amount) { 481; GCN-LABEL: v_shl_v16i32: 482; GCN: ; %bb.0: 483; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 484; GCN-NEXT: v_lshlrev_b32_e32 v0, v16, v0 485; GCN-NEXT: v_lshlrev_b32_e32 v1, v17, v1 486; GCN-NEXT: v_lshlrev_b32_e32 v2, v18, v2 487; GCN-NEXT: v_lshlrev_b32_e32 v3, v19, v3 488; GCN-NEXT: v_lshlrev_b32_e32 v4, v20, v4 489; GCN-NEXT: v_lshlrev_b32_e32 v5, v21, v5 490; GCN-NEXT: v_lshlrev_b32_e32 v6, v22, v6 491; GCN-NEXT: v_lshlrev_b32_e32 v7, v23, v7 492; GCN-NEXT: v_lshlrev_b32_e32 v8, v24, v8 493; GCN-NEXT: v_lshlrev_b32_e32 v9, v25, v9 494; GCN-NEXT: v_lshlrev_b32_e32 v10, v26, v10 495; GCN-NEXT: v_lshlrev_b32_e32 v11, v27, v11 496; GCN-NEXT: v_lshlrev_b32_e32 v12, v28, v12 497; GCN-NEXT: v_lshlrev_b32_e32 v13, v29, v13 498; GCN-NEXT: v_lshlrev_b32_e32 v14, v30, v14 499; GCN-NEXT: v_lshlrev_b32_e32 v15, v31, v15 500; GCN-NEXT: s_setpc_b64 s[30:31] 501; 502; GFX10-LABEL: v_shl_v16i32: 503; GFX10: ; %bb.0: 504; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 505; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 506; GFX10-NEXT: v_lshlrev_b32_e32 v0, v16, v0 507; GFX10-NEXT: v_lshlrev_b32_e32 v1, v17, v1 508; GFX10-NEXT: v_lshlrev_b32_e32 v2, v18, v2 509; GFX10-NEXT: v_lshlrev_b32_e32 v3, v19, v3 510; GFX10-NEXT: v_lshlrev_b32_e32 v4, v20, v4 511; GFX10-NEXT: v_lshlrev_b32_e32 v5, v21, v5 512; GFX10-NEXT: v_lshlrev_b32_e32 v6, v22, v6 513; GFX10-NEXT: v_lshlrev_b32_e32 v7, v23, v7 514; GFX10-NEXT: v_lshlrev_b32_e32 v8, v24, v8 515; GFX10-NEXT: v_lshlrev_b32_e32 v9, v25, v9 516; GFX10-NEXT: v_lshlrev_b32_e32 v10, v26, v10 517; GFX10-NEXT: v_lshlrev_b32_e32 v11, v27, v11 518; GFX10-NEXT: v_lshlrev_b32_e32 v12, v28, v12 519; GFX10-NEXT: v_lshlrev_b32_e32 v13, v29, v13 520; GFX10-NEXT: v_lshlrev_b32_e32 v14, v30, v14 521; GFX10-NEXT: v_lshlrev_b32_e32 v15, v31, v15 522; GFX10-NEXT: s_setpc_b64 s[30:31] 523 %result = shl <16 x i32> %value, %amount 524 ret <16 x i32> %result 525} 526 527define amdgpu_ps <16 x i32> @s_shl_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) { 528; GCN-LABEL: s_shl_v16i32: 529; GCN: ; %bb.0: 530; GCN-NEXT: s_lshl_b32 s0, s0, s16 531; GCN-NEXT: s_lshl_b32 s1, s1, s17 532; GCN-NEXT: s_lshl_b32 s2, s2, s18 533; GCN-NEXT: s_lshl_b32 s3, s3, s19 534; GCN-NEXT: s_lshl_b32 s4, s4, s20 535; GCN-NEXT: s_lshl_b32 s5, s5, s21 536; GCN-NEXT: s_lshl_b32 s6, s6, s22 537; GCN-NEXT: s_lshl_b32 s7, s7, s23 538; GCN-NEXT: s_lshl_b32 s8, s8, s24 539; GCN-NEXT: s_lshl_b32 s9, s9, s25 540; GCN-NEXT: s_lshl_b32 s10, s10, s26 541; GCN-NEXT: s_lshl_b32 s11, s11, s27 542; GCN-NEXT: s_lshl_b32 s12, s12, s28 543; GCN-NEXT: s_lshl_b32 s13, s13, s29 544; GCN-NEXT: s_lshl_b32 s14, s14, s30 545; GCN-NEXT: s_lshl_b32 s15, s15, s31 546; GCN-NEXT: ; return to shader part epilog 547; 548; GFX10-LABEL: s_shl_v16i32: 549; GFX10: ; %bb.0: 550; GFX10-NEXT: s_lshl_b32 s0, s0, s16 551; GFX10-NEXT: s_lshl_b32 s1, s1, s17 552; GFX10-NEXT: s_lshl_b32 s2, s2, s18 553; GFX10-NEXT: s_lshl_b32 s3, s3, s19 554; GFX10-NEXT: s_lshl_b32 s4, s4, s20 555; GFX10-NEXT: s_lshl_b32 s5, s5, s21 556; GFX10-NEXT: s_lshl_b32 s6, s6, s22 557; GFX10-NEXT: s_lshl_b32 s7, s7, s23 558; GFX10-NEXT: s_lshl_b32 s8, s8, s24 559; GFX10-NEXT: s_lshl_b32 s9, s9, s25 560; GFX10-NEXT: s_lshl_b32 s10, s10, s26 561; GFX10-NEXT: s_lshl_b32 s11, s11, s27 562; GFX10-NEXT: s_lshl_b32 s12, s12, s28 563; GFX10-NEXT: s_lshl_b32 s13, s13, s29 564; GFX10-NEXT: s_lshl_b32 s14, s14, s30 565; GFX10-NEXT: s_lshl_b32 s15, s15, s31 566; GFX10-NEXT: ; return to shader part epilog 567 %result = shl <16 x i32> %value, %amount 568 ret <16 x i32> %result 569} 570 571define i16 @v_shl_i16(i16 %value, i16 %amount) { 572; GFX6-LABEL: v_shl_i16: 573; GFX6: ; %bb.0: 574; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 575; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 576; GFX6-NEXT: v_lshlrev_b32_e32 v0, v1, v0 577; GFX6-NEXT: s_setpc_b64 s[30:31] 578; 579; GFX8-LABEL: v_shl_i16: 580; GFX8: ; %bb.0: 581; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 582; GFX8-NEXT: v_lshlrev_b16_e32 v0, v1, v0 583; GFX8-NEXT: s_setpc_b64 s[30:31] 584; 585; GFX9-LABEL: v_shl_i16: 586; GFX9: ; %bb.0: 587; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 588; GFX9-NEXT: v_lshlrev_b16_e32 v0, v1, v0 589; GFX9-NEXT: s_setpc_b64 s[30:31] 590; 591; GFX10-LABEL: v_shl_i16: 592; GFX10: ; %bb.0: 593; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 594; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 595; GFX10-NEXT: v_lshlrev_b16 v0, v1, v0 596; GFX10-NEXT: s_setpc_b64 s[30:31] 597 %result = shl i16 %value, %amount 598 ret i16 %result 599} 600 601define i16 @v_shl_i16_31(i16 %value) { 602; GCN-LABEL: v_shl_i16_31: 603; GCN: ; %bb.0: 604; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 605; GCN-NEXT: s_setpc_b64 s[30:31] 606; 607; GFX10-LABEL: v_shl_i16_31: 608; GFX10: ; %bb.0: 609; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 610; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 611; GFX10-NEXT: s_setpc_b64 s[30:31] 612 %result = shl i16 %value, 31 613 ret i16 %result 614} 615 616define amdgpu_ps i16 @s_shl_i16(i16 inreg %value, i16 inreg %amount) { 617; GFX6-LABEL: s_shl_i16: 618; GFX6: ; %bb.0: 619; GFX6-NEXT: s_and_b32 s1, s1, 0xffff 620; GFX6-NEXT: s_lshl_b32 s0, s0, s1 621; GFX6-NEXT: ; return to shader part epilog 622; 623; GFX8-LABEL: s_shl_i16: 624; GFX8: ; %bb.0: 625; GFX8-NEXT: s_mov_b32 s2, 0xffff 626; GFX8-NEXT: s_and_b32 s0, s0, s2 627; GFX8-NEXT: s_and_b32 s1, s1, s2 628; GFX8-NEXT: s_lshl_b32 s0, s0, s1 629; GFX8-NEXT: ; return to shader part epilog 630; 631; GFX9-LABEL: s_shl_i16: 632; GFX9: ; %bb.0: 633; GFX9-NEXT: s_mov_b32 s2, 0xffff 634; GFX9-NEXT: s_and_b32 s0, s0, s2 635; GFX9-NEXT: s_and_b32 s1, s1, s2 636; GFX9-NEXT: s_lshl_b32 s0, s0, s1 637; GFX9-NEXT: ; return to shader part epilog 638; 639; GFX10-LABEL: s_shl_i16: 640; GFX10: ; %bb.0: 641; GFX10-NEXT: s_mov_b32 s2, 0xffff 642; GFX10-NEXT: s_and_b32 s0, s0, s2 643; GFX10-NEXT: s_and_b32 s1, s1, s2 644; GFX10-NEXT: s_lshl_b32 s0, s0, s1 645; GFX10-NEXT: ; return to shader part epilog 646 %result = shl i16 %value, %amount 647 ret i16 %result 648} 649 650define amdgpu_ps i16 @s_shl_i16_15(i16 inreg %value) { 651; GFX6-LABEL: s_shl_i16_15: 652; GFX6: ; %bb.0: 653; GFX6-NEXT: s_lshl_b32 s0, s0, 15 654; GFX6-NEXT: ; return to shader part epilog 655; 656; GFX8-LABEL: s_shl_i16_15: 657; GFX8: ; %bb.0: 658; GFX8-NEXT: s_bfe_u32 s1, 15, 0x100000 659; GFX8-NEXT: s_lshl_b32 s0, s0, s1 660; GFX8-NEXT: ; return to shader part epilog 661; 662; GFX9-LABEL: s_shl_i16_15: 663; GFX9: ; %bb.0: 664; GFX9-NEXT: s_bfe_u32 s1, 15, 0x100000 665; GFX9-NEXT: s_lshl_b32 s0, s0, s1 666; GFX9-NEXT: ; return to shader part epilog 667; 668; GFX10-LABEL: s_shl_i16_15: 669; GFX10: ; %bb.0: 670; GFX10-NEXT: s_bfe_u32 s1, 15, 0x100000 671; GFX10-NEXT: s_lshl_b32 s0, s0, s1 672; GFX10-NEXT: ; return to shader part epilog 673 %result = shl i16 %value, 15 674 ret i16 %result 675} 676 677define amdgpu_ps half @shl_i16_sv(i16 inreg %value, i16 %amount) { 678; GFX6-LABEL: shl_i16_sv: 679; GFX6: ; %bb.0: 680; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 681; GFX6-NEXT: v_lshl_b32_e32 v0, s0, v0 682; GFX6-NEXT: ; return to shader part epilog 683; 684; GFX8-LABEL: shl_i16_sv: 685; GFX8: ; %bb.0: 686; GFX8-NEXT: v_lshlrev_b16_e64 v0, v0, s0 687; GFX8-NEXT: ; return to shader part epilog 688; 689; GFX9-LABEL: shl_i16_sv: 690; GFX9: ; %bb.0: 691; GFX9-NEXT: v_lshlrev_b16_e64 v0, v0, s0 692; GFX9-NEXT: ; return to shader part epilog 693; 694; GFX10-LABEL: shl_i16_sv: 695; GFX10: ; %bb.0: 696; GFX10-NEXT: v_lshlrev_b16 v0, v0, s0 697; GFX10-NEXT: ; return to shader part epilog 698 %result = shl i16 %value, %amount 699 %cast = bitcast i16 %result to half 700 ret half %cast 701} 702 703define amdgpu_ps half @shl_i16_vs(i16 %value, i16 inreg %amount) { 704; GFX6-LABEL: shl_i16_vs: 705; GFX6: ; %bb.0: 706; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 707; GFX6-NEXT: v_lshlrev_b32_e32 v0, s0, v0 708; GFX6-NEXT: ; return to shader part epilog 709; 710; GFX8-LABEL: shl_i16_vs: 711; GFX8: ; %bb.0: 712; GFX8-NEXT: v_lshlrev_b16_e32 v0, s0, v0 713; GFX8-NEXT: ; return to shader part epilog 714; 715; GFX9-LABEL: shl_i16_vs: 716; GFX9: ; %bb.0: 717; GFX9-NEXT: v_lshlrev_b16_e32 v0, s0, v0 718; GFX9-NEXT: ; return to shader part epilog 719; 720; GFX10-LABEL: shl_i16_vs: 721; GFX10: ; %bb.0: 722; GFX10-NEXT: v_lshlrev_b16 v0, s0, v0 723; GFX10-NEXT: ; return to shader part epilog 724 %result = shl i16 %value, %amount 725 %cast = bitcast i16 %result to half 726 ret half %cast 727} 728 729define <2 x i16> @v_shl_v2i16(<2 x i16> %value, <2 x i16> %amount) { 730; GFX6-LABEL: v_shl_v2i16: 731; GFX6: ; %bb.0: 732; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 733; GFX6-NEXT: s_mov_b32 s4, 0xffff 734; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1 735; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0 736; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 737; GFX6-NEXT: v_lshlrev_b32_e32 v0, v1, v0 738; GFX6-NEXT: v_lshlrev_b32_e32 v1, v3, v2 739; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 740; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 741; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 742; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 743; GFX6-NEXT: s_setpc_b64 s[30:31] 744; 745; GFX8-LABEL: v_shl_v2i16: 746; GFX8: ; %bb.0: 747; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 748; GFX8-NEXT: v_lshlrev_b16_e32 v2, v1, v0 749; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 750; GFX8-NEXT: v_or_b32_e32 v0, v2, v0 751; GFX8-NEXT: s_setpc_b64 s[30:31] 752; 753; GFX9-LABEL: v_shl_v2i16: 754; GFX9: ; %bb.0: 755; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 756; GFX9-NEXT: v_pk_lshlrev_b16 v0, v1, v0 757; GFX9-NEXT: s_setpc_b64 s[30:31] 758; 759; GFX10-LABEL: v_shl_v2i16: 760; GFX10: ; %bb.0: 761; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 762; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 763; GFX10-NEXT: v_pk_lshlrev_b16 v0, v1, v0 764; GFX10-NEXT: s_setpc_b64 s[30:31] 765 %result = shl <2 x i16> %value, %amount 766 ret <2 x i16> %result 767} 768 769define <2 x i16> @v_shl_v2i16_15(<2 x i16> %value) { 770; GFX6-LABEL: v_shl_v2i16_15: 771; GFX6: ; %bb.0: 772; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 773; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0 774; GFX6-NEXT: v_lshlrev_b32_e32 v0, 15, v0 775; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 776; GFX6-NEXT: v_lshlrev_b32_e32 v1, 31, v1 777; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 778; GFX6-NEXT: s_setpc_b64 s[30:31] 779; 780; GFX8-LABEL: v_shl_v2i16_15: 781; GFX8: ; %bb.0: 782; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 783; GFX8-NEXT: v_mov_b32_e32 v2, 15 784; GFX8-NEXT: v_lshlrev_b16_e32 v1, 15, v0 785; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 786; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 787; GFX8-NEXT: s_setpc_b64 s[30:31] 788; 789; GFX9-LABEL: v_shl_v2i16_15: 790; GFX9: ; %bb.0: 791; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 792; GFX9-NEXT: v_pk_lshlrev_b16 v0, 15, v0 op_sel_hi:[0,1] 793; GFX9-NEXT: s_setpc_b64 s[30:31] 794; 795; GFX10-LABEL: v_shl_v2i16_15: 796; GFX10: ; %bb.0: 797; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 798; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 799; GFX10-NEXT: v_pk_lshlrev_b16 v0, 15, v0 op_sel_hi:[0,1] 800; GFX10-NEXT: s_setpc_b64 s[30:31] 801 %result = shl <2 x i16> %value, <i16 15, i16 15> 802 ret <2 x i16> %result 803} 804 805define amdgpu_ps i32 @s_shl_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) { 806; GFX6-LABEL: s_shl_v2i16: 807; GFX6: ; %bb.0: 808; GFX6-NEXT: s_mov_b32 s4, 0xffff 809; GFX6-NEXT: s_lshr_b32 s3, s1, 16 810; GFX6-NEXT: s_lshr_b32 s2, s0, 16 811; GFX6-NEXT: s_and_b32 s1, s1, s4 812; GFX6-NEXT: s_lshl_b32 s0, s0, s1 813; GFX6-NEXT: s_lshl_b32 s1, s2, s3 814; GFX6-NEXT: s_and_b32 s1, s1, s4 815; GFX6-NEXT: s_and_b32 s0, s0, s4 816; GFX6-NEXT: s_lshl_b32 s1, s1, 16 817; GFX6-NEXT: s_or_b32 s0, s0, s1 818; GFX6-NEXT: ; return to shader part epilog 819; 820; GFX8-LABEL: s_shl_v2i16: 821; GFX8: ; %bb.0: 822; GFX8-NEXT: s_mov_b32 s3, 0xffff 823; GFX8-NEXT: s_lshr_b32 s2, s0, 16 824; GFX8-NEXT: s_lshr_b32 s4, s1, 16 825; GFX8-NEXT: s_and_b32 s0, s0, s3 826; GFX8-NEXT: s_and_b32 s1, s1, s3 827; GFX8-NEXT: s_lshl_b32 s0, s0, s1 828; GFX8-NEXT: s_lshl_b32 s1, s2, s4 829; GFX8-NEXT: s_lshl_b32 s1, s1, 16 830; GFX8-NEXT: s_and_b32 s0, s0, s3 831; GFX8-NEXT: s_or_b32 s0, s1, s0 832; GFX8-NEXT: ; return to shader part epilog 833; 834; GFX9-LABEL: s_shl_v2i16: 835; GFX9: ; %bb.0: 836; GFX9-NEXT: s_lshr_b32 s2, s0, 16 837; GFX9-NEXT: s_lshr_b32 s3, s1, 16 838; GFX9-NEXT: s_lshl_b32 s0, s0, s1 839; GFX9-NEXT: s_lshl_b32 s1, s2, s3 840; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1 841; GFX9-NEXT: ; return to shader part epilog 842; 843; GFX10-LABEL: s_shl_v2i16: 844; GFX10: ; %bb.0: 845; GFX10-NEXT: s_lshr_b32 s2, s0, 16 846; GFX10-NEXT: s_lshr_b32 s3, s1, 16 847; GFX10-NEXT: s_lshl_b32 s0, s0, s1 848; GFX10-NEXT: s_lshl_b32 s1, s2, s3 849; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1 850; GFX10-NEXT: ; return to shader part epilog 851 %result = shl <2 x i16> %value, %amount 852 %cast = bitcast <2 x i16> %result to i32 853 ret i32 %cast 854} 855 856define amdgpu_ps float @shl_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) { 857; GFX6-LABEL: shl_v2i16_sv: 858; GFX6: ; %bb.0: 859; GFX6-NEXT: s_lshr_b32 s1, s0, 16 860; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0 861; GFX6-NEXT: s_mov_b32 s2, 0xffff 862; GFX6-NEXT: v_and_b32_e32 v0, s2, v0 863; GFX6-NEXT: v_lshl_b32_e32 v1, s1, v1 864; GFX6-NEXT: v_lshl_b32_e32 v0, s0, v0 865; GFX6-NEXT: v_and_b32_e32 v1, s2, v1 866; GFX6-NEXT: v_and_b32_e32 v0, s2, v0 867; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 868; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 869; GFX6-NEXT: ; return to shader part epilog 870; 871; GFX8-LABEL: shl_v2i16_sv: 872; GFX8: ; %bb.0: 873; GFX8-NEXT: s_lshr_b32 s1, s0, 16 874; GFX8-NEXT: v_mov_b32_e32 v2, s1 875; GFX8-NEXT: v_lshlrev_b16_e64 v1, v0, s0 876; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 877; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 878; GFX8-NEXT: ; return to shader part epilog 879; 880; GFX9-LABEL: shl_v2i16_sv: 881; GFX9: ; %bb.0: 882; GFX9-NEXT: v_pk_lshlrev_b16 v0, v0, s0 883; GFX9-NEXT: ; return to shader part epilog 884; 885; GFX10-LABEL: shl_v2i16_sv: 886; GFX10: ; %bb.0: 887; GFX10-NEXT: v_pk_lshlrev_b16 v0, v0, s0 888; GFX10-NEXT: ; return to shader part epilog 889 %result = shl <2 x i16> %value, %amount 890 %cast = bitcast <2 x i16> %result to float 891 ret float %cast 892} 893 894define amdgpu_ps float @shl_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) { 895; GFX6-LABEL: shl_v2i16_vs: 896; GFX6: ; %bb.0: 897; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0 898; GFX6-NEXT: s_lshr_b32 s1, s0, 16 899; GFX6-NEXT: s_mov_b32 s2, 0xffff 900; GFX6-NEXT: v_lshlrev_b32_e32 v1, s1, v1 901; GFX6-NEXT: s_and_b32 s0, s0, s2 902; GFX6-NEXT: v_lshlrev_b32_e32 v0, s0, v0 903; GFX6-NEXT: v_and_b32_e32 v1, s2, v1 904; GFX6-NEXT: v_and_b32_e32 v0, s2, v0 905; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 906; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 907; GFX6-NEXT: ; return to shader part epilog 908; 909; GFX8-LABEL: shl_v2i16_vs: 910; GFX8: ; %bb.0: 911; GFX8-NEXT: s_lshr_b32 s1, s0, 16 912; GFX8-NEXT: v_mov_b32_e32 v2, s1 913; GFX8-NEXT: v_lshlrev_b16_e32 v1, s0, v0 914; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 915; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 916; GFX8-NEXT: ; return to shader part epilog 917; 918; GFX9-LABEL: shl_v2i16_vs: 919; GFX9: ; %bb.0: 920; GFX9-NEXT: v_pk_lshlrev_b16 v0, s0, v0 921; GFX9-NEXT: ; return to shader part epilog 922; 923; GFX10-LABEL: shl_v2i16_vs: 924; GFX10: ; %bb.0: 925; GFX10-NEXT: v_pk_lshlrev_b16 v0, s0, v0 926; GFX10-NEXT: ; return to shader part epilog 927 %result = shl <2 x i16> %value, %amount 928 %cast = bitcast <2 x i16> %result to float 929 ret float %cast 930} 931 932; FIXME 933; define <3 x i16> @v_shl_v3i16(<3 x i16> %value, <3 x i16> %amount) { 934; %result = shl <3 x i16> %value, %amount 935; ret <3 x i16> %result 936; } 937 938; define amdgpu_ps <3 x i16> @s_shl_v3i16(<3 x i16> inreg %value, <3 x i16> inreg %amount) { 939; %result = shl <3 x i16> %value, %amount 940; ret <3 x i16> %result 941; } 942 943define <2 x float> @v_shl_v4i16(<4 x i16> %value, <4 x i16> %amount) { 944; GFX6-LABEL: v_shl_v4i16: 945; GFX6: ; %bb.0: 946; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 947; GFX6-NEXT: s_mov_b32 s4, 0xffff 948; GFX6-NEXT: v_and_b32_e32 v4, s4, v4 949; GFX6-NEXT: v_lshlrev_b32_e32 v0, v4, v0 950; GFX6-NEXT: v_and_b32_e32 v4, s4, v5 951; GFX6-NEXT: v_lshlrev_b32_e32 v1, v4, v1 952; GFX6-NEXT: v_and_b32_e32 v4, s4, v6 953; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 954; GFX6-NEXT: v_lshlrev_b32_e32 v2, v4, v2 955; GFX6-NEXT: v_and_b32_e32 v4, s4, v7 956; GFX6-NEXT: v_lshlrev_b32_e32 v3, v4, v3 957; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 958; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 959; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 960; GFX6-NEXT: v_and_b32_e32 v1, s4, v2 961; GFX6-NEXT: v_and_b32_e32 v2, s4, v3 962; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2 963; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 964; GFX6-NEXT: s_setpc_b64 s[30:31] 965; 966; GFX8-LABEL: v_shl_v4i16: 967; GFX8: ; %bb.0: 968; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 969; GFX8-NEXT: v_lshlrev_b16_e32 v4, v2, v0 970; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 971; GFX8-NEXT: v_lshlrev_b16_e32 v2, v3, v1 972; GFX8-NEXT: v_lshlrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 973; GFX8-NEXT: v_or_b32_e32 v0, v4, v0 974; GFX8-NEXT: v_or_b32_e32 v1, v2, v1 975; GFX8-NEXT: s_setpc_b64 s[30:31] 976; 977; GFX9-LABEL: v_shl_v4i16: 978; GFX9: ; %bb.0: 979; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 980; GFX9-NEXT: v_pk_lshlrev_b16 v0, v2, v0 981; GFX9-NEXT: v_pk_lshlrev_b16 v1, v3, v1 982; GFX9-NEXT: s_setpc_b64 s[30:31] 983; 984; GFX10-LABEL: v_shl_v4i16: 985; GFX10: ; %bb.0: 986; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 987; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 988; GFX10-NEXT: v_pk_lshlrev_b16 v0, v2, v0 989; GFX10-NEXT: v_pk_lshlrev_b16 v1, v3, v1 990; GFX10-NEXT: s_setpc_b64 s[30:31] 991 %result = shl <4 x i16> %value, %amount 992 %cast = bitcast <4 x i16> %result to <2 x float> 993 ret <2 x float> %cast 994} 995 996define amdgpu_ps <2 x i32> @s_shl_v4i16(<4 x i16> inreg %value, <4 x i16> inreg %amount) { 997; GFX6-LABEL: s_shl_v4i16: 998; GFX6: ; %bb.0: 999; GFX6-NEXT: s_mov_b32 s8, 0xffff 1000; GFX6-NEXT: s_and_b32 s4, s4, s8 1001; GFX6-NEXT: s_lshl_b32 s0, s0, s4 1002; GFX6-NEXT: s_and_b32 s4, s5, s8 1003; GFX6-NEXT: s_lshl_b32 s1, s1, s4 1004; GFX6-NEXT: s_and_b32 s4, s6, s8 1005; GFX6-NEXT: s_and_b32 s1, s1, s8 1006; GFX6-NEXT: s_lshl_b32 s2, s2, s4 1007; GFX6-NEXT: s_and_b32 s4, s7, s8 1008; GFX6-NEXT: s_lshl_b32 s3, s3, s4 1009; GFX6-NEXT: s_and_b32 s0, s0, s8 1010; GFX6-NEXT: s_lshl_b32 s1, s1, 16 1011; GFX6-NEXT: s_or_b32 s0, s0, s1 1012; GFX6-NEXT: s_and_b32 s1, s2, s8 1013; GFX6-NEXT: s_and_b32 s2, s3, s8 1014; GFX6-NEXT: s_lshl_b32 s2, s2, 16 1015; GFX6-NEXT: s_or_b32 s1, s1, s2 1016; GFX6-NEXT: ; return to shader part epilog 1017; 1018; GFX8-LABEL: s_shl_v4i16: 1019; GFX8: ; %bb.0: 1020; GFX8-NEXT: s_mov_b32 s6, 0xffff 1021; GFX8-NEXT: s_lshr_b32 s4, s0, 16 1022; GFX8-NEXT: s_lshr_b32 s7, s2, 16 1023; GFX8-NEXT: s_and_b32 s0, s0, s6 1024; GFX8-NEXT: s_and_b32 s2, s2, s6 1025; GFX8-NEXT: s_lshl_b32 s0, s0, s2 1026; GFX8-NEXT: s_lshl_b32 s2, s4, s7 1027; GFX8-NEXT: s_lshr_b32 s5, s1, 16 1028; GFX8-NEXT: s_lshr_b32 s8, s3, 16 1029; GFX8-NEXT: s_and_b32 s1, s1, s6 1030; GFX8-NEXT: s_and_b32 s3, s3, s6 1031; GFX8-NEXT: s_lshl_b32 s1, s1, s3 1032; GFX8-NEXT: s_lshl_b32 s3, s5, s8 1033; GFX8-NEXT: s_lshl_b32 s2, s2, 16 1034; GFX8-NEXT: s_and_b32 s0, s0, s6 1035; GFX8-NEXT: s_or_b32 s0, s2, s0 1036; GFX8-NEXT: s_lshl_b32 s2, s3, 16 1037; GFX8-NEXT: s_and_b32 s1, s1, s6 1038; GFX8-NEXT: s_or_b32 s1, s2, s1 1039; GFX8-NEXT: ; return to shader part epilog 1040; 1041; GFX9-LABEL: s_shl_v4i16: 1042; GFX9: ; %bb.0: 1043; GFX9-NEXT: s_lshr_b32 s4, s0, 16 1044; GFX9-NEXT: s_lshr_b32 s5, s2, 16 1045; GFX9-NEXT: s_lshl_b32 s0, s0, s2 1046; GFX9-NEXT: s_lshl_b32 s2, s4, s5 1047; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2 1048; GFX9-NEXT: s_lshr_b32 s2, s1, 16 1049; GFX9-NEXT: s_lshr_b32 s4, s3, 16 1050; GFX9-NEXT: s_lshl_b32 s1, s1, s3 1051; GFX9-NEXT: s_lshl_b32 s2, s2, s4 1052; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2 1053; GFX9-NEXT: ; return to shader part epilog 1054; 1055; GFX10-LABEL: s_shl_v4i16: 1056; GFX10: ; %bb.0: 1057; GFX10-NEXT: s_lshr_b32 s4, s0, 16 1058; GFX10-NEXT: s_lshr_b32 s5, s2, 16 1059; GFX10-NEXT: s_lshl_b32 s0, s0, s2 1060; GFX10-NEXT: s_lshl_b32 s2, s4, s5 1061; GFX10-NEXT: s_lshr_b32 s4, s1, 16 1062; GFX10-NEXT: s_lshr_b32 s5, s3, 16 1063; GFX10-NEXT: s_lshl_b32 s1, s1, s3 1064; GFX10-NEXT: s_lshl_b32 s3, s4, s5 1065; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2 1066; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3 1067; GFX10-NEXT: ; return to shader part epilog 1068 %result = shl <4 x i16> %value, %amount 1069 %cast = bitcast <4 x i16> %result to <2 x i32> 1070 ret <2 x i32> %cast 1071} 1072 1073; FIXME 1074; define <5 x i16> @v_shl_v5i16(<5 x i16> %value, <5 x i16> %amount) { 1075; %result = shl <5 x i16> %value, %amount 1076; ret <5 x i16> %result 1077; } 1078 1079; define amdgpu_ps <5 x i16> @s_shl_v5i16(<5 x i16> inreg %value, <5 x i16> inreg %amount) { 1080; %result = shl <5 x i16> %value, %amount 1081; ret <5 x i16> %result 1082; } 1083 1084; define <3 x float> @v_shl_v6i16(<6 x i16> %value, <6 x i16> %amount) { 1085; %result = shl <6 x i16> %value, %amount 1086; %cast = bitcast <6 x i16> %result to <3 x float> 1087; ret <3 x float> %cast 1088; } 1089 1090; define amdgpu_ps <3 x i32> @s_shl_v6i16(<6 x i16> inreg %value, <6 x i16> inreg %amount) { 1091; %result = shl <6 x i16> %value, %amount 1092; %cast = bitcast <6 x i16> %result to <3 x i32> 1093; ret <3 x i32> %cast 1094; } 1095 1096define <4 x float> @v_shl_v8i16(<8 x i16> %value, <8 x i16> %amount) { 1097; GFX6-LABEL: v_shl_v8i16: 1098; GFX6: ; %bb.0: 1099; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1100; GFX6-NEXT: s_mov_b32 s4, 0xffff 1101; GFX6-NEXT: v_and_b32_e32 v8, s4, v8 1102; GFX6-NEXT: v_lshlrev_b32_e32 v0, v8, v0 1103; GFX6-NEXT: v_and_b32_e32 v8, s4, v9 1104; GFX6-NEXT: v_lshlrev_b32_e32 v1, v8, v1 1105; GFX6-NEXT: v_and_b32_e32 v8, s4, v10 1106; GFX6-NEXT: v_lshlrev_b32_e32 v2, v8, v2 1107; GFX6-NEXT: v_and_b32_e32 v8, s4, v11 1108; GFX6-NEXT: v_lshlrev_b32_e32 v3, v8, v3 1109; GFX6-NEXT: v_and_b32_e32 v8, s4, v12 1110; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 1111; GFX6-NEXT: v_lshlrev_b32_e32 v4, v8, v4 1112; GFX6-NEXT: v_and_b32_e32 v8, s4, v13 1113; GFX6-NEXT: v_lshlrev_b32_e32 v5, v8, v5 1114; GFX6-NEXT: v_and_b32_e32 v8, s4, v14 1115; GFX6-NEXT: v_mov_b32_e32 v16, 0xffff 1116; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 1117; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1118; GFX6-NEXT: v_lshlrev_b32_e32 v6, v8, v6 1119; GFX6-NEXT: v_and_b32_e32 v8, s4, v15 1120; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 1121; GFX6-NEXT: v_and_b32_e32 v1, v2, v16 1122; GFX6-NEXT: v_and_b32_e32 v2, v3, v16 1123; GFX6-NEXT: v_and_b32_e32 v3, v5, v16 1124; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2 1125; GFX6-NEXT: v_lshlrev_b32_e32 v7, v8, v7 1126; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 1127; GFX6-NEXT: v_and_b32_e32 v2, v4, v16 1128; GFX6-NEXT: v_and_b32_e32 v4, v7, v16 1129; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3 1130; GFX6-NEXT: v_or_b32_e32 v2, v2, v3 1131; GFX6-NEXT: v_and_b32_e32 v3, v6, v16 1132; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4 1133; GFX6-NEXT: v_or_b32_e32 v3, v3, v4 1134; GFX6-NEXT: s_setpc_b64 s[30:31] 1135; 1136; GFX8-LABEL: v_shl_v8i16: 1137; GFX8: ; %bb.0: 1138; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1139; GFX8-NEXT: v_lshlrev_b16_e32 v8, v4, v0 1140; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1141; GFX8-NEXT: v_lshlrev_b16_e32 v4, v5, v1 1142; GFX8-NEXT: v_lshlrev_b16_sdwa v1, v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1143; GFX8-NEXT: v_or_b32_e32 v1, v4, v1 1144; GFX8-NEXT: v_lshlrev_b16_e32 v4, v6, v2 1145; GFX8-NEXT: v_lshlrev_b16_sdwa v2, v6, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1146; GFX8-NEXT: v_or_b32_e32 v2, v4, v2 1147; GFX8-NEXT: v_lshlrev_b16_e32 v4, v7, v3 1148; GFX8-NEXT: v_lshlrev_b16_sdwa v3, v7, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1149; GFX8-NEXT: v_or_b32_e32 v0, v8, v0 1150; GFX8-NEXT: v_or_b32_e32 v3, v4, v3 1151; GFX8-NEXT: s_setpc_b64 s[30:31] 1152; 1153; GFX9-LABEL: v_shl_v8i16: 1154; GFX9: ; %bb.0: 1155; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1156; GFX9-NEXT: v_pk_lshlrev_b16 v0, v4, v0 1157; GFX9-NEXT: v_pk_lshlrev_b16 v1, v5, v1 1158; GFX9-NEXT: v_pk_lshlrev_b16 v2, v6, v2 1159; GFX9-NEXT: v_pk_lshlrev_b16 v3, v7, v3 1160; GFX9-NEXT: s_setpc_b64 s[30:31] 1161; 1162; GFX10-LABEL: v_shl_v8i16: 1163; GFX10: ; %bb.0: 1164; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1165; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1166; GFX10-NEXT: v_pk_lshlrev_b16 v0, v4, v0 1167; GFX10-NEXT: v_pk_lshlrev_b16 v1, v5, v1 1168; GFX10-NEXT: v_pk_lshlrev_b16 v2, v6, v2 1169; GFX10-NEXT: v_pk_lshlrev_b16 v3, v7, v3 1170; GFX10-NEXT: s_setpc_b64 s[30:31] 1171 %result = shl <8 x i16> %value, %amount 1172 %cast = bitcast <8 x i16> %result to <4 x float> 1173 ret <4 x float> %cast 1174} 1175 1176define amdgpu_ps <4 x i32> @s_shl_v8i16(<8 x i16> inreg %value, <8 x i16> inreg %amount) { 1177; GFX6-LABEL: s_shl_v8i16: 1178; GFX6: ; %bb.0: 1179; GFX6-NEXT: s_mov_b32 s16, 0xffff 1180; GFX6-NEXT: s_and_b32 s8, s8, s16 1181; GFX6-NEXT: s_lshl_b32 s0, s0, s8 1182; GFX6-NEXT: s_and_b32 s8, s9, s16 1183; GFX6-NEXT: s_lshl_b32 s1, s1, s8 1184; GFX6-NEXT: s_and_b32 s8, s10, s16 1185; GFX6-NEXT: s_lshl_b32 s2, s2, s8 1186; GFX6-NEXT: s_and_b32 s8, s11, s16 1187; GFX6-NEXT: s_lshl_b32 s3, s3, s8 1188; GFX6-NEXT: s_and_b32 s8, s12, s16 1189; GFX6-NEXT: s_and_b32 s1, s1, s16 1190; GFX6-NEXT: s_lshl_b32 s4, s4, s8 1191; GFX6-NEXT: s_and_b32 s8, s13, s16 1192; GFX6-NEXT: s_lshl_b32 s5, s5, s8 1193; GFX6-NEXT: s_and_b32 s8, s14, s16 1194; GFX6-NEXT: s_and_b32 s0, s0, s16 1195; GFX6-NEXT: s_lshl_b32 s1, s1, 16 1196; GFX6-NEXT: s_lshl_b32 s6, s6, s8 1197; GFX6-NEXT: s_and_b32 s8, s15, s16 1198; GFX6-NEXT: s_or_b32 s0, s0, s1 1199; GFX6-NEXT: s_and_b32 s1, s2, s16 1200; GFX6-NEXT: s_and_b32 s2, s3, s16 1201; GFX6-NEXT: s_and_b32 s3, s5, s16 1202; GFX6-NEXT: s_lshl_b32 s2, s2, 16 1203; GFX6-NEXT: s_lshl_b32 s7, s7, s8 1204; GFX6-NEXT: s_or_b32 s1, s1, s2 1205; GFX6-NEXT: s_and_b32 s2, s4, s16 1206; GFX6-NEXT: s_and_b32 s4, s7, s16 1207; GFX6-NEXT: s_lshl_b32 s3, s3, 16 1208; GFX6-NEXT: s_or_b32 s2, s2, s3 1209; GFX6-NEXT: s_and_b32 s3, s6, s16 1210; GFX6-NEXT: s_lshl_b32 s4, s4, 16 1211; GFX6-NEXT: s_or_b32 s3, s3, s4 1212; GFX6-NEXT: ; return to shader part epilog 1213; 1214; GFX8-LABEL: s_shl_v8i16: 1215; GFX8: ; %bb.0: 1216; GFX8-NEXT: s_mov_b32 s12, 0xffff 1217; GFX8-NEXT: s_lshr_b32 s8, s0, 16 1218; GFX8-NEXT: s_lshr_b32 s13, s4, 16 1219; GFX8-NEXT: s_and_b32 s0, s0, s12 1220; GFX8-NEXT: s_and_b32 s4, s4, s12 1221; GFX8-NEXT: s_lshl_b32 s0, s0, s4 1222; GFX8-NEXT: s_lshl_b32 s4, s8, s13 1223; GFX8-NEXT: s_lshr_b32 s9, s1, 16 1224; GFX8-NEXT: s_lshr_b32 s14, s5, 16 1225; GFX8-NEXT: s_and_b32 s1, s1, s12 1226; GFX8-NEXT: s_and_b32 s5, s5, s12 1227; GFX8-NEXT: s_lshl_b32 s1, s1, s5 1228; GFX8-NEXT: s_lshr_b32 s10, s2, 16 1229; GFX8-NEXT: s_lshr_b32 s15, s6, 16 1230; GFX8-NEXT: s_and_b32 s2, s2, s12 1231; GFX8-NEXT: s_and_b32 s6, s6, s12 1232; GFX8-NEXT: s_lshl_b32 s5, s9, s14 1233; GFX8-NEXT: s_lshl_b32 s4, s4, 16 1234; GFX8-NEXT: s_and_b32 s0, s0, s12 1235; GFX8-NEXT: s_lshl_b32 s2, s2, s6 1236; GFX8-NEXT: s_lshr_b32 s11, s3, 16 1237; GFX8-NEXT: s_lshr_b32 s16, s7, 16 1238; GFX8-NEXT: s_or_b32 s0, s4, s0 1239; GFX8-NEXT: s_and_b32 s3, s3, s12 1240; GFX8-NEXT: s_and_b32 s7, s7, s12 1241; GFX8-NEXT: s_lshl_b32 s6, s10, s15 1242; GFX8-NEXT: s_lshl_b32 s4, s5, 16 1243; GFX8-NEXT: s_and_b32 s1, s1, s12 1244; GFX8-NEXT: s_lshl_b32 s3, s3, s7 1245; GFX8-NEXT: s_or_b32 s1, s4, s1 1246; GFX8-NEXT: s_lshl_b32 s7, s11, s16 1247; GFX8-NEXT: s_lshl_b32 s4, s6, 16 1248; GFX8-NEXT: s_and_b32 s2, s2, s12 1249; GFX8-NEXT: s_or_b32 s2, s4, s2 1250; GFX8-NEXT: s_lshl_b32 s4, s7, 16 1251; GFX8-NEXT: s_and_b32 s3, s3, s12 1252; GFX8-NEXT: s_or_b32 s3, s4, s3 1253; GFX8-NEXT: ; return to shader part epilog 1254; 1255; GFX9-LABEL: s_shl_v8i16: 1256; GFX9: ; %bb.0: 1257; GFX9-NEXT: s_lshr_b32 s8, s0, 16 1258; GFX9-NEXT: s_lshr_b32 s9, s4, 16 1259; GFX9-NEXT: s_lshl_b32 s0, s0, s4 1260; GFX9-NEXT: s_lshl_b32 s4, s8, s9 1261; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s4 1262; GFX9-NEXT: s_lshr_b32 s4, s1, 16 1263; GFX9-NEXT: s_lshr_b32 s8, s5, 16 1264; GFX9-NEXT: s_lshl_b32 s1, s1, s5 1265; GFX9-NEXT: s_lshl_b32 s4, s4, s8 1266; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4 1267; GFX9-NEXT: s_lshr_b32 s4, s2, 16 1268; GFX9-NEXT: s_lshr_b32 s5, s6, 16 1269; GFX9-NEXT: s_lshl_b32 s4, s4, s5 1270; GFX9-NEXT: s_lshl_b32 s2, s2, s6 1271; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4 1272; GFX9-NEXT: s_lshr_b32 s4, s3, 16 1273; GFX9-NEXT: s_lshr_b32 s5, s7, 16 1274; GFX9-NEXT: s_lshl_b32 s3, s3, s7 1275; GFX9-NEXT: s_lshl_b32 s4, s4, s5 1276; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4 1277; GFX9-NEXT: ; return to shader part epilog 1278; 1279; GFX10-LABEL: s_shl_v8i16: 1280; GFX10: ; %bb.0: 1281; GFX10-NEXT: s_lshr_b32 s8, s0, 16 1282; GFX10-NEXT: s_lshr_b32 s9, s4, 16 1283; GFX10-NEXT: s_lshl_b32 s0, s0, s4 1284; GFX10-NEXT: s_lshl_b32 s4, s8, s9 1285; GFX10-NEXT: s_lshr_b32 s8, s1, 16 1286; GFX10-NEXT: s_lshr_b32 s9, s5, 16 1287; GFX10-NEXT: s_lshl_b32 s1, s1, s5 1288; GFX10-NEXT: s_lshl_b32 s5, s8, s9 1289; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s4 1290; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s5 1291; GFX10-NEXT: s_lshr_b32 s4, s2, 16 1292; GFX10-NEXT: s_lshr_b32 s5, s6, 16 1293; GFX10-NEXT: s_lshl_b32 s2, s2, s6 1294; GFX10-NEXT: s_lshl_b32 s4, s4, s5 1295; GFX10-NEXT: s_lshr_b32 s5, s3, 16 1296; GFX10-NEXT: s_lshr_b32 s6, s7, 16 1297; GFX10-NEXT: s_lshl_b32 s3, s3, s7 1298; GFX10-NEXT: s_lshl_b32 s5, s5, s6 1299; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s4 1300; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s5 1301; GFX10-NEXT: ; return to shader part epilog 1302 %result = shl <8 x i16> %value, %amount 1303 %cast = bitcast <8 x i16> %result to <4 x i32> 1304 ret <4 x i32> %cast 1305} 1306 1307define i64 @v_shl_i64(i64 %value, i64 %amount) { 1308; GFX6-LABEL: v_shl_i64: 1309; GFX6: ; %bb.0: 1310; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1311; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v2 1312; GFX6-NEXT: s_setpc_b64 s[30:31] 1313; 1314; GFX8-LABEL: v_shl_i64: 1315; GFX8: ; %bb.0: 1316; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1317; GFX8-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1] 1318; GFX8-NEXT: s_setpc_b64 s[30:31] 1319; 1320; GFX9-LABEL: v_shl_i64: 1321; GFX9: ; %bb.0: 1322; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1323; GFX9-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1] 1324; GFX9-NEXT: s_setpc_b64 s[30:31] 1325; 1326; GFX10-LABEL: v_shl_i64: 1327; GFX10: ; %bb.0: 1328; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1329; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1330; GFX10-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1] 1331; GFX10-NEXT: s_setpc_b64 s[30:31] 1332 %result = shl i64 %value, %amount 1333 ret i64 %result 1334} 1335 1336define i64 @v_shl_i64_63(i64 %value) { 1337; GCN-LABEL: v_shl_i64_63: 1338; GCN: ; %bb.0: 1339; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1340; GCN-NEXT: v_lshlrev_b32_e32 v1, 31, v0 1341; GCN-NEXT: v_mov_b32_e32 v0, 0 1342; GCN-NEXT: s_setpc_b64 s[30:31] 1343; 1344; GFX10-LABEL: v_shl_i64_63: 1345; GFX10: ; %bb.0: 1346; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1347; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1348; GFX10-NEXT: v_lshlrev_b32_e32 v1, 31, v0 1349; GFX10-NEXT: v_mov_b32_e32 v0, 0 1350; GFX10-NEXT: s_setpc_b64 s[30:31] 1351 %result = shl i64 %value, 63 1352 ret i64 %result 1353} 1354 1355define i64 @v_shl_i64_33(i64 %value) { 1356; GCN-LABEL: v_shl_i64_33: 1357; GCN: ; %bb.0: 1358; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1359; GCN-NEXT: v_lshlrev_b32_e32 v1, 1, v0 1360; GCN-NEXT: v_mov_b32_e32 v0, 0 1361; GCN-NEXT: s_setpc_b64 s[30:31] 1362; 1363; GFX10-LABEL: v_shl_i64_33: 1364; GFX10: ; %bb.0: 1365; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1366; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1367; GFX10-NEXT: v_lshlrev_b32_e32 v1, 1, v0 1368; GFX10-NEXT: v_mov_b32_e32 v0, 0 1369; GFX10-NEXT: s_setpc_b64 s[30:31] 1370 %result = shl i64 %value, 33 1371 ret i64 %result 1372} 1373 1374define i64 @v_shl_i64_32(i64 %value) { 1375; GCN-LABEL: v_shl_i64_32: 1376; GCN: ; %bb.0: 1377; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1378; GCN-NEXT: v_mov_b32_e32 v1, v0 1379; GCN-NEXT: v_mov_b32_e32 v0, 0 1380; GCN-NEXT: s_setpc_b64 s[30:31] 1381; 1382; GFX10-LABEL: v_shl_i64_32: 1383; GFX10: ; %bb.0: 1384; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1385; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1386; GFX10-NEXT: v_mov_b32_e32 v1, v0 1387; GFX10-NEXT: v_mov_b32_e32 v0, 0 1388; GFX10-NEXT: s_setpc_b64 s[30:31] 1389 %result = shl i64 %value, 32 1390 ret i64 %result 1391} 1392 1393define i64 @v_shl_i64_31(i64 %value) { 1394; GFX6-LABEL: v_shl_i64_31: 1395; GFX6: ; %bb.0: 1396; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1397; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 31 1398; GFX6-NEXT: s_setpc_b64 s[30:31] 1399; 1400; GFX8-LABEL: v_shl_i64_31: 1401; GFX8: ; %bb.0: 1402; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1403; GFX8-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1] 1404; GFX8-NEXT: s_setpc_b64 s[30:31] 1405; 1406; GFX9-LABEL: v_shl_i64_31: 1407; GFX9: ; %bb.0: 1408; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1409; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1] 1410; GFX9-NEXT: s_setpc_b64 s[30:31] 1411; 1412; GFX10-LABEL: v_shl_i64_31: 1413; GFX10: ; %bb.0: 1414; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1415; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1416; GFX10-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1] 1417; GFX10-NEXT: s_setpc_b64 s[30:31] 1418 %result = shl i64 %value, 31 1419 ret i64 %result 1420} 1421 1422define amdgpu_ps i64 @s_shl_i64(i64 inreg %value, i64 inreg %amount) { 1423; GCN-LABEL: s_shl_i64: 1424; GCN: ; %bb.0: 1425; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 1426; GCN-NEXT: ; return to shader part epilog 1427; 1428; GFX10-LABEL: s_shl_i64: 1429; GFX10: ; %bb.0: 1430; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 1431; GFX10-NEXT: ; return to shader part epilog 1432 %result = shl i64 %value, %amount 1433 ret i64 %result 1434} 1435 1436define amdgpu_ps i64 @s_shl_i64_63(i64 inreg %value) { 1437; GCN-LABEL: s_shl_i64_63: 1438; GCN: ; %bb.0: 1439; GCN-NEXT: s_lshl_b32 s1, s0, 31 1440; GCN-NEXT: s_mov_b32 s0, 0 1441; GCN-NEXT: ; return to shader part epilog 1442; 1443; GFX10-LABEL: s_shl_i64_63: 1444; GFX10: ; %bb.0: 1445; GFX10-NEXT: s_lshl_b32 s1, s0, 31 1446; GFX10-NEXT: s_mov_b32 s0, 0 1447; GFX10-NEXT: ; return to shader part epilog 1448 %result = shl i64 %value, 63 1449 ret i64 %result 1450} 1451 1452define amdgpu_ps i64 @s_shl_i64_33(i64 inreg %value) { 1453; GCN-LABEL: s_shl_i64_33: 1454; GCN: ; %bb.0: 1455; GCN-NEXT: s_lshl_b32 s1, s0, 1 1456; GCN-NEXT: s_mov_b32 s0, 0 1457; GCN-NEXT: ; return to shader part epilog 1458; 1459; GFX10-LABEL: s_shl_i64_33: 1460; GFX10: ; %bb.0: 1461; GFX10-NEXT: s_lshl_b32 s1, s0, 1 1462; GFX10-NEXT: s_mov_b32 s0, 0 1463; GFX10-NEXT: ; return to shader part epilog 1464 %result = shl i64 %value, 33 1465 ret i64 %result 1466} 1467 1468define amdgpu_ps i64 @s_shl_i64_32(i64 inreg %value) { 1469; GCN-LABEL: s_shl_i64_32: 1470; GCN: ; %bb.0: 1471; GCN-NEXT: s_mov_b32 s1, s0 1472; GCN-NEXT: s_mov_b32 s0, 0 1473; GCN-NEXT: ; return to shader part epilog 1474; 1475; GFX10-LABEL: s_shl_i64_32: 1476; GFX10: ; %bb.0: 1477; GFX10-NEXT: s_mov_b32 s1, s0 1478; GFX10-NEXT: s_mov_b32 s0, 0 1479; GFX10-NEXT: ; return to shader part epilog 1480 %result = shl i64 %value, 32 1481 ret i64 %result 1482} 1483 1484define amdgpu_ps i64 @s_shl_i64_31(i64 inreg %value) { 1485; GCN-LABEL: s_shl_i64_31: 1486; GCN: ; %bb.0: 1487; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], 31 1488; GCN-NEXT: ; return to shader part epilog 1489; 1490; GFX10-LABEL: s_shl_i64_31: 1491; GFX10: ; %bb.0: 1492; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 31 1493; GFX10-NEXT: ; return to shader part epilog 1494 %result = shl i64 %value, 31 1495 ret i64 %result 1496} 1497 1498define amdgpu_ps <2 x float> @shl_i64_sv(i64 inreg %value, i64 %amount) { 1499; GFX6-LABEL: shl_i64_sv: 1500; GFX6: ; %bb.0: 1501; GFX6-NEXT: v_lshl_b64 v[0:1], s[0:1], v0 1502; GFX6-NEXT: ; return to shader part epilog 1503; 1504; GFX8-LABEL: shl_i64_sv: 1505; GFX8: ; %bb.0: 1506; GFX8-NEXT: v_lshlrev_b64 v[0:1], v0, s[0:1] 1507; GFX8-NEXT: ; return to shader part epilog 1508; 1509; GFX9-LABEL: shl_i64_sv: 1510; GFX9: ; %bb.0: 1511; GFX9-NEXT: v_lshlrev_b64 v[0:1], v0, s[0:1] 1512; GFX9-NEXT: ; return to shader part epilog 1513; 1514; GFX10-LABEL: shl_i64_sv: 1515; GFX10: ; %bb.0: 1516; GFX10-NEXT: v_lshlrev_b64 v[0:1], v0, s[0:1] 1517; GFX10-NEXT: ; return to shader part epilog 1518 %result = shl i64 %value, %amount 1519 %cast = bitcast i64 %result to <2 x float> 1520 ret <2 x float> %cast 1521} 1522 1523define amdgpu_ps <2 x float> @shl_i64_vs(i64 %value, i64 inreg %amount) { 1524; GFX6-LABEL: shl_i64_vs: 1525; GFX6: ; %bb.0: 1526; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s0 1527; GFX6-NEXT: ; return to shader part epilog 1528; 1529; GFX8-LABEL: shl_i64_vs: 1530; GFX8: ; %bb.0: 1531; GFX8-NEXT: v_lshlrev_b64 v[0:1], s0, v[0:1] 1532; GFX8-NEXT: ; return to shader part epilog 1533; 1534; GFX9-LABEL: shl_i64_vs: 1535; GFX9: ; %bb.0: 1536; GFX9-NEXT: v_lshlrev_b64 v[0:1], s0, v[0:1] 1537; GFX9-NEXT: ; return to shader part epilog 1538; 1539; GFX10-LABEL: shl_i64_vs: 1540; GFX10: ; %bb.0: 1541; GFX10-NEXT: v_lshlrev_b64 v[0:1], s0, v[0:1] 1542; GFX10-NEXT: ; return to shader part epilog 1543 %result = shl i64 %value, %amount 1544 %cast = bitcast i64 %result to <2 x float> 1545 ret <2 x float> %cast 1546} 1547 1548define <2 x i64> @v_shl_v2i64(<2 x i64> %value, <2 x i64> %amount) { 1549; GFX6-LABEL: v_shl_v2i64: 1550; GFX6: ; %bb.0: 1551; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1552; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v4 1553; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], v6 1554; GFX6-NEXT: s_setpc_b64 s[30:31] 1555; 1556; GFX8-LABEL: v_shl_v2i64: 1557; GFX8: ; %bb.0: 1558; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1559; GFX8-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1] 1560; GFX8-NEXT: v_lshlrev_b64 v[2:3], v6, v[2:3] 1561; GFX8-NEXT: s_setpc_b64 s[30:31] 1562; 1563; GFX9-LABEL: v_shl_v2i64: 1564; GFX9: ; %bb.0: 1565; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1566; GFX9-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1] 1567; GFX9-NEXT: v_lshlrev_b64 v[2:3], v6, v[2:3] 1568; GFX9-NEXT: s_setpc_b64 s[30:31] 1569; 1570; GFX10-LABEL: v_shl_v2i64: 1571; GFX10: ; %bb.0: 1572; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1573; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1574; GFX10-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1] 1575; GFX10-NEXT: v_lshlrev_b64 v[2:3], v6, v[2:3] 1576; GFX10-NEXT: s_setpc_b64 s[30:31] 1577 %result = shl <2 x i64> %value, %amount 1578 ret <2 x i64> %result 1579} 1580 1581define <2 x i64> @v_shl_v2i64_31(<2 x i64> %value) { 1582; GFX6-LABEL: v_shl_v2i64_31: 1583; GFX6: ; %bb.0: 1584; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1585; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 31 1586; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], 31 1587; GFX6-NEXT: s_setpc_b64 s[30:31] 1588; 1589; GFX8-LABEL: v_shl_v2i64_31: 1590; GFX8: ; %bb.0: 1591; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1592; GFX8-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1] 1593; GFX8-NEXT: v_lshlrev_b64 v[2:3], 31, v[2:3] 1594; GFX8-NEXT: s_setpc_b64 s[30:31] 1595; 1596; GFX9-LABEL: v_shl_v2i64_31: 1597; GFX9: ; %bb.0: 1598; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1599; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1] 1600; GFX9-NEXT: v_lshlrev_b64 v[2:3], 31, v[2:3] 1601; GFX9-NEXT: s_setpc_b64 s[30:31] 1602; 1603; GFX10-LABEL: v_shl_v2i64_31: 1604; GFX10: ; %bb.0: 1605; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1606; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1607; GFX10-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1] 1608; GFX10-NEXT: v_lshlrev_b64 v[2:3], 31, v[2:3] 1609; GFX10-NEXT: s_setpc_b64 s[30:31] 1610 %result = shl <2 x i64> %value, <i64 31, i64 31> 1611 ret <2 x i64> %result 1612} 1613 1614define amdgpu_ps <2 x i64> @s_shl_v2i64(<2 x i64> inreg %value, <2 x i64> inreg %amount) { 1615; GCN-LABEL: s_shl_v2i64: 1616; GCN: ; %bb.0: 1617; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], s4 1618; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s6 1619; GCN-NEXT: ; return to shader part epilog 1620; 1621; GFX10-LABEL: s_shl_v2i64: 1622; GFX10: ; %bb.0: 1623; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s4 1624; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], s6 1625; GFX10-NEXT: ; return to shader part epilog 1626 %result = shl <2 x i64> %value, %amount 1627 ret <2 x i64> %result 1628} 1629