1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -amdgpu-bypass-slow-div=0 -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=GFX8 %s
3; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -amdgpu-bypass-slow-div=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s
4; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -amdgpu-bypass-slow-div=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
5
6define amdgpu_kernel void @sdivrem_i32(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 %x, i32 %y) {
7; GFX8-LABEL: sdivrem_i32:
8; GFX8:       ; %bb.0:
9; GFX8-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x10
10; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
11; GFX8-NEXT:    s_ashr_i32 s8, s7, 31
12; GFX8-NEXT:    s_add_i32 s0, s7, s8
13; GFX8-NEXT:    s_xor_b32 s7, s0, s8
14; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s7
15; GFX8-NEXT:    s_sub_i32 s0, 0, s7
16; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
17; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
18; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0
19; GFX8-NEXT:    v_mul_lo_u32 v1, s0, v0
20; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
21; GFX8-NEXT:    s_ashr_i32 s4, s6, 31
22; GFX8-NEXT:    s_add_i32 s5, s6, s4
23; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v1
24; GFX8-NEXT:    s_xor_b32 s5, s5, s4
25; GFX8-NEXT:    s_xor_b32 s6, s4, s8
26; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
27; GFX8-NEXT:    v_mul_hi_u32 v2, s5, v0
28; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
29; GFX8-NEXT:    v_mov_b32_e32 v0, s0
30; GFX8-NEXT:    v_mov_b32_e32 v1, s1
31; GFX8-NEXT:    v_mul_lo_u32 v3, v2, s7
32; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v2
33; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s5, v3
34; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s7, v3
35; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
36; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s7, v3
37; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
38; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v2
39; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s7, v3
40; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
41; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s7, v3
42; GFX8-NEXT:    v_xor_b32_e32 v2, s6, v2
43; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
44; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s6, v2
45; GFX8-NEXT:    v_xor_b32_e32 v3, s4, v3
46; GFX8-NEXT:    flat_store_dword v[0:1], v2
47; GFX8-NEXT:    v_mov_b32_e32 v0, s2
48; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, s4, v3
49; GFX8-NEXT:    v_mov_b32_e32 v1, s3
50; GFX8-NEXT:    flat_store_dword v[0:1], v3
51; GFX8-NEXT:    s_endpgm
52;
53; GFX9-LABEL: sdivrem_i32:
54; GFX9:       ; %bb.0:
55; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x10
56; GFX9-NEXT:    v_mov_b32_e32 v2, 0
57; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
58; GFX9-NEXT:    s_ashr_i32 s6, s1, 31
59; GFX9-NEXT:    s_add_i32 s1, s1, s6
60; GFX9-NEXT:    s_xor_b32 s7, s1, s6
61; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s7
62; GFX9-NEXT:    s_sub_i32 s1, 0, s7
63; GFX9-NEXT:    s_ashr_i32 s8, s0, 31
64; GFX9-NEXT:    s_add_i32 s0, s0, s8
65; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
66; GFX9-NEXT:    s_xor_b32 s9, s0, s8
67; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
68; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
69; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v0
70; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
71; GFX9-NEXT:    s_xor_b32 s4, s8, s6
72; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
73; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
74; GFX9-NEXT:    v_mul_hi_u32 v0, s9, v0
75; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s7
76; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
77; GFX9-NEXT:    v_sub_u32_e32 v1, s9, v1
78; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
79; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
80; GFX9-NEXT:    v_subrev_u32_e32 v3, s7, v1
81; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
82; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
83; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
84; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
85; GFX9-NEXT:    v_subrev_u32_e32 v3, s7, v1
86; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
87; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v0
88; GFX9-NEXT:    v_subrev_u32_e32 v0, s4, v0
89; GFX9-NEXT:    v_xor_b32_e32 v1, s8, v1
90; GFX9-NEXT:    v_subrev_u32_e32 v1, s8, v1
91; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
92; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]
93; GFX9-NEXT:    global_store_dword v2, v1, s[2:3]
94; GFX9-NEXT:    s_endpgm
95;
96; GFX10-LABEL: sdivrem_i32:
97; GFX10:       ; %bb.0:
98; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x10
99; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
100; GFX10-NEXT:    s_ashr_i32 s6, s1, 31
101; GFX10-NEXT:    s_ashr_i32 s8, s0, 31
102; GFX10-NEXT:    s_add_i32 s1, s1, s6
103; GFX10-NEXT:    s_add_i32 s0, s0, s8
104; GFX10-NEXT:    s_xor_b32 s7, s1, s6
105; GFX10-NEXT:    s_xor_b32 s0, s0, s8
106; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s7
107; GFX10-NEXT:    s_sub_i32 s1, 0, s7
108; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
109; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
110; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
111; GFX10-NEXT:    v_mul_lo_u32 v1, s1, v0
112; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v1
113; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1
114; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v0
115; GFX10-NEXT:    v_mul_lo_u32 v1, v0, s7
116; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v0
117; GFX10-NEXT:    v_sub_nc_u32_e32 v1, s0, v1
118; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
119; GFX10-NEXT:    s_xor_b32 s4, s8, s6
120; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s7, v1
121; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s7, v1
122; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
123; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo
124; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v0
125; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s7, v1
126; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s7, v1
127; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
128; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo
129; GFX10-NEXT:    v_mov_b32_e32 v2, 0
130; GFX10-NEXT:    v_xor_b32_e32 v0, s4, v0
131; GFX10-NEXT:    v_xor_b32_e32 v1, s8, v1
132; GFX10-NEXT:    v_subrev_nc_u32_e32 v0, s4, v0
133; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, s8, v1
134; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
135; GFX10-NEXT:    global_store_dword v2, v0, s[0:1]
136; GFX10-NEXT:    global_store_dword v2, v1, s[2:3]
137; GFX10-NEXT:    s_endpgm
138  %div = sdiv i32 %x, %y
139  store i32 %div, i32 addrspace(1)* %out0
140  %rem = srem i32 %x, %y
141  store i32 %rem, i32 addrspace(1)* %out1
142  ret void
143}
144
145define amdgpu_kernel void @sdivrem_i64(i64 addrspace(1)* %out0, i64 addrspace(1)* %out1, i64 %x, i64 %y) {
146; GFX8-LABEL: sdivrem_i64:
147; GFX8:       ; %bb.0:
148; GFX8-NEXT:    s_load_dwordx8 s[4:11], s[4:5], 0x0
149; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
150; GFX8-NEXT:    s_ashr_i32 s2, s9, 31
151; GFX8-NEXT:    s_ashr_i32 s12, s11, 31
152; GFX8-NEXT:    s_add_u32 s0, s8, s2
153; GFX8-NEXT:    s_addc_u32 s1, s9, s2
154; GFX8-NEXT:    s_add_u32 s8, s10, s12
155; GFX8-NEXT:    s_mov_b32 s13, s12
156; GFX8-NEXT:    s_addc_u32 s9, s11, s12
157; GFX8-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
158; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s9
159; GFX8-NEXT:    v_cvt_f32_u32_e32 v1, s8
160; GFX8-NEXT:    s_mov_b32 s3, s2
161; GFX8-NEXT:    s_xor_b64 s[10:11], s[0:1], s[2:3]
162; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0
163; GFX8-NEXT:    v_add_f32_e32 v0, v0, v1
164; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
165; GFX8-NEXT:    s_sub_u32 s14, 0, s8
166; GFX8-NEXT:    s_subb_u32 s15, 0, s9
167; GFX8-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
168; GFX8-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
169; GFX8-NEXT:    v_trunc_f32_e32 v2, v1
170; GFX8-NEXT:    v_mul_f32_e32 v1, 0xcf800000, v2
171; GFX8-NEXT:    v_add_f32_e32 v0, v1, v0
172; GFX8-NEXT:    v_cvt_u32_f32_e32 v3, v0
173; GFX8-NEXT:    v_cvt_u32_f32_e32 v4, v2
174; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s14, v3, 0
175; GFX8-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s14, v4, v[1:2]
176; GFX8-NEXT:    v_mul_hi_u32 v5, v3, v0
177; GFX8-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s15, v3, v[1:2]
178; GFX8-NEXT:    v_mul_lo_u32 v2, v4, v0
179; GFX8-NEXT:    v_mul_hi_u32 v0, v4, v0
180; GFX8-NEXT:    v_mul_lo_u32 v6, v3, v1
181; GFX8-NEXT:    v_mul_lo_u32 v7, v4, v1
182; GFX8-NEXT:    v_mul_hi_u32 v8, v3, v1
183; GFX8-NEXT:    v_mul_hi_u32 v1, v4, v1
184; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v6
185; GFX8-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
186; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v7, v0
187; GFX8-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
188; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v5
189; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
190; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v6, v2
191; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v8
192; GFX8-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
193; GFX8-NEXT:    v_add_u32_e32 v5, vcc, v7, v5
194; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
195; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
196; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v5, v2
197; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v2
198; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v3, v0
199; GFX8-NEXT:    v_addc_u32_e32 v4, vcc, v4, v1, vcc
200; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s14, v3, 0
201; GFX8-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s14, v4, v[1:2]
202; GFX8-NEXT:    v_mul_hi_u32 v6, v3, v0
203; GFX8-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s15, v3, v[1:2]
204; GFX8-NEXT:    v_mul_lo_u32 v2, v4, v0
205; GFX8-NEXT:    v_mul_hi_u32 v0, v4, v0
206; GFX8-NEXT:    v_mul_lo_u32 v5, v3, v1
207; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v5
208; GFX8-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
209; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v6
210; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
211; GFX8-NEXT:    v_mul_lo_u32 v6, v4, v1
212; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v5, v2
213; GFX8-NEXT:    v_mul_hi_u32 v5, v3, v1
214; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v6, v0
215; GFX8-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
216; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v5
217; GFX8-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
218; GFX8-NEXT:    v_add_u32_e32 v5, vcc, v6, v5
219; GFX8-NEXT:    v_mul_hi_u32 v1, v4, v1
220; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
221; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
222; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v5, v2
223; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v2
224; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v3, v0
225; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v4, v1, vcc
226; GFX8-NEXT:    v_mul_lo_u32 v2, s11, v0
227; GFX8-NEXT:    v_mul_lo_u32 v3, s10, v1
228; GFX8-NEXT:    v_mul_hi_u32 v4, s10, v0
229; GFX8-NEXT:    v_mul_hi_u32 v0, s11, v0
230; GFX8-NEXT:    v_mul_hi_u32 v5, s11, v1
231; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v3
232; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
233; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v4
234; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
235; GFX8-NEXT:    v_mul_lo_u32 v4, s11, v1
236; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v2
237; GFX8-NEXT:    v_mul_hi_u32 v3, s10, v1
238; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v4, v0
239; GFX8-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
240; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v3
241; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
242; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v4, v3
243; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v0, v2
244; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s8, v4, 0
245; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
246; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v2
247; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v5, v2
248; GFX8-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s8, v3, v[1:2]
249; GFX8-NEXT:    v_mov_b32_e32 v6, s11
250; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s10, v0
251; GFX8-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s9, v4, v[1:2]
252; GFX8-NEXT:    v_mov_b32_e32 v5, s9
253; GFX8-NEXT:    v_subb_u32_e64 v2, s[0:1], v6, v1, vcc
254; GFX8-NEXT:    v_sub_u32_e64 v1, s[0:1], s11, v1
255; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v2
256; GFX8-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
257; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v0
258; GFX8-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
259; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v2
260; GFX8-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
261; GFX8-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[0:1]
262; GFX8-NEXT:    v_subrev_u32_e32 v7, vcc, s8, v0
263; GFX8-NEXT:    v_subbrev_u32_e64 v8, s[0:1], 0, v1, vcc
264; GFX8-NEXT:    v_add_u32_e64 v9, s[0:1], 1, v4
265; GFX8-NEXT:    v_addc_u32_e64 v10, s[0:1], 0, v3, s[0:1]
266; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v8
267; GFX8-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[0:1]
268; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v7
269; GFX8-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
270; GFX8-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[0:1]
271; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v8
272; GFX8-NEXT:    v_subrev_u32_e32 v5, vcc, s8, v7
273; GFX8-NEXT:    v_cndmask_b32_e64 v11, v11, v12, s[0:1]
274; GFX8-NEXT:    v_add_u32_e64 v12, s[0:1], 1, v9
275; GFX8-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
276; GFX8-NEXT:    v_addc_u32_e64 v13, s[0:1], 0, v10, s[0:1]
277; GFX8-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
278; GFX8-NEXT:    v_cndmask_b32_e32 v9, v9, v12, vcc
279; GFX8-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc
280; GFX8-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
281; GFX8-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v11
282; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v9, vcc
283; GFX8-NEXT:    v_cndmask_b32_e64 v5, v7, v5, s[0:1]
284; GFX8-NEXT:    v_cndmask_b32_e64 v1, v8, v1, s[0:1]
285; GFX8-NEXT:    s_xor_b64 s[0:1], s[2:3], s[12:13]
286; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v10, vcc
287; GFX8-NEXT:    v_cndmask_b32_e32 v5, v0, v5, vcc
288; GFX8-NEXT:    v_xor_b32_e32 v0, s0, v4
289; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v1, vcc
290; GFX8-NEXT:    v_xor_b32_e32 v1, s1, v3
291; GFX8-NEXT:    v_mov_b32_e32 v3, s1
292; GFX8-NEXT:    v_subrev_u32_e32 v0, vcc, s0, v0
293; GFX8-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
294; GFX8-NEXT:    v_xor_b32_e32 v3, s2, v5
295; GFX8-NEXT:    v_xor_b32_e32 v4, s2, v2
296; GFX8-NEXT:    v_mov_b32_e32 v5, s2
297; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s2, v3
298; GFX8-NEXT:    v_subb_u32_e32 v3, vcc, v4, v5, vcc
299; GFX8-NEXT:    v_mov_b32_e32 v4, s4
300; GFX8-NEXT:    v_mov_b32_e32 v5, s5
301; GFX8-NEXT:    flat_store_dwordx2 v[4:5], v[0:1]
302; GFX8-NEXT:    v_mov_b32_e32 v0, s6
303; GFX8-NEXT:    v_mov_b32_e32 v1, s7
304; GFX8-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
305; GFX8-NEXT:    s_endpgm
306;
307; GFX9-LABEL: sdivrem_i64:
308; GFX9:       ; %bb.0:
309; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[4:5], 0x0
310; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
311; GFX9-NEXT:    s_ashr_i32 s2, s9, 31
312; GFX9-NEXT:    s_ashr_i32 s12, s11, 31
313; GFX9-NEXT:    s_add_u32 s0, s8, s2
314; GFX9-NEXT:    s_addc_u32 s1, s9, s2
315; GFX9-NEXT:    s_add_u32 s8, s10, s12
316; GFX9-NEXT:    s_mov_b32 s13, s12
317; GFX9-NEXT:    s_addc_u32 s9, s11, s12
318; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
319; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s9
320; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s8
321; GFX9-NEXT:    s_mov_b32 s3, s2
322; GFX9-NEXT:    s_xor_b64 s[10:11], s[0:1], s[2:3]
323; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0
324; GFX9-NEXT:    v_add_f32_e32 v0, v0, v1
325; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
326; GFX9-NEXT:    s_sub_u32 s14, 0, s8
327; GFX9-NEXT:    s_subb_u32 s15, 0, s9
328; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
329; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
330; GFX9-NEXT:    v_trunc_f32_e32 v2, v1
331; GFX9-NEXT:    v_mul_f32_e32 v1, 0xcf800000, v2
332; GFX9-NEXT:    v_add_f32_e32 v0, v1, v0
333; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v0
334; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v2
335; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s14, v3, 0
336; GFX9-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s14, v4, v[1:2]
337; GFX9-NEXT:    v_mul_hi_u32 v5, v3, v0
338; GFX9-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s15, v3, v[1:2]
339; GFX9-NEXT:    v_mul_lo_u32 v2, v4, v0
340; GFX9-NEXT:    v_mul_hi_u32 v0, v4, v0
341; GFX9-NEXT:    v_mul_lo_u32 v6, v3, v1
342; GFX9-NEXT:    v_mul_lo_u32 v7, v4, v1
343; GFX9-NEXT:    v_mul_hi_u32 v8, v3, v1
344; GFX9-NEXT:    v_mul_hi_u32 v1, v4, v1
345; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v6
346; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
347; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v7, v0
348; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
349; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v5
350; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
351; GFX9-NEXT:    v_add_u32_e32 v2, v6, v2
352; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v8
353; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
354; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
355; GFX9-NEXT:    v_add_u32_e32 v5, v7, v5
356; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
357; GFX9-NEXT:    v_add3_u32 v1, v5, v2, v1
358; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v0
359; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v1, vcc
360; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s14, v3, 0
361; GFX9-NEXT:    v_mov_b32_e32 v7, s9
362; GFX9-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s14, v4, v[1:2]
363; GFX9-NEXT:    v_mul_hi_u32 v6, v3, v0
364; GFX9-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s15, v3, v[1:2]
365; GFX9-NEXT:    v_mul_lo_u32 v2, v4, v0
366; GFX9-NEXT:    v_mul_hi_u32 v0, v4, v0
367; GFX9-NEXT:    v_mul_lo_u32 v5, v3, v1
368; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v5
369; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
370; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v6
371; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
372; GFX9-NEXT:    v_mul_lo_u32 v6, v4, v1
373; GFX9-NEXT:    v_add_u32_e32 v2, v5, v2
374; GFX9-NEXT:    v_mul_hi_u32 v5, v3, v1
375; GFX9-NEXT:    v_mul_hi_u32 v1, v4, v1
376; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v6, v0
377; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
378; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v5
379; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
380; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
381; GFX9-NEXT:    v_add_u32_e32 v5, v6, v5
382; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
383; GFX9-NEXT:    v_add3_u32 v1, v5, v2, v1
384; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v3, v0
385; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v4, v1, vcc
386; GFX9-NEXT:    v_mul_lo_u32 v2, s11, v0
387; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v1
388; GFX9-NEXT:    v_mul_hi_u32 v4, s10, v0
389; GFX9-NEXT:    v_mul_hi_u32 v0, s11, v0
390; GFX9-NEXT:    v_mul_hi_u32 v6, s11, v1
391; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
392; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
393; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
394; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
395; GFX9-NEXT:    v_mul_lo_u32 v4, s11, v1
396; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
397; GFX9-NEXT:    v_mul_hi_u32 v3, s10, v1
398; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v4, v0
399; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
400; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
401; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
402; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v0, v2
403; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s8, v5, 0
404; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
405; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
406; GFX9-NEXT:    v_add3_u32 v3, v3, v2, v6
407; GFX9-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s8, v3, v[1:2]
408; GFX9-NEXT:    v_mov_b32_e32 v6, s11
409; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, s10, v0
410; GFX9-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s9, v5, v[1:2]
411; GFX9-NEXT:    v_mov_b32_e32 v4, 0
412; GFX9-NEXT:    v_subb_co_u32_e64 v2, s[0:1], v6, v1, vcc
413; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v2
414; GFX9-NEXT:    v_sub_u32_e32 v1, s11, v1
415; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
416; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v0
417; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[0:1]
418; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v2
419; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v7, vcc
420; GFX9-NEXT:    v_cndmask_b32_e64 v6, v6, v8, s[0:1]
421; GFX9-NEXT:    v_subrev_co_u32_e32 v8, vcc, s8, v0
422; GFX9-NEXT:    v_subbrev_co_u32_e64 v9, s[0:1], 0, v1, vcc
423; GFX9-NEXT:    v_add_co_u32_e64 v10, s[0:1], 1, v5
424; GFX9-NEXT:    v_addc_co_u32_e64 v11, s[0:1], 0, v3, s[0:1]
425; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v9
426; GFX9-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[0:1]
427; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v8
428; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v7, vcc
429; GFX9-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[0:1]
430; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v9
431; GFX9-NEXT:    v_subrev_co_u32_e32 v7, vcc, s8, v8
432; GFX9-NEXT:    v_cndmask_b32_e64 v12, v12, v13, s[0:1]
433; GFX9-NEXT:    v_add_co_u32_e64 v13, s[0:1], 1, v10
434; GFX9-NEXT:    v_subbrev_co_u32_e32 v1, vcc, 0, v1, vcc
435; GFX9-NEXT:    v_addc_co_u32_e64 v14, s[0:1], 0, v11, s[0:1]
436; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
437; GFX9-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc
438; GFX9-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc
439; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
440; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v12
441; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v10, vcc
442; GFX9-NEXT:    v_cndmask_b32_e64 v6, v8, v7, s[0:1]
443; GFX9-NEXT:    v_cndmask_b32_e64 v1, v9, v1, s[0:1]
444; GFX9-NEXT:    s_xor_b64 s[0:1], s[2:3], s[12:13]
445; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc
446; GFX9-NEXT:    v_cndmask_b32_e32 v6, v0, v6, vcc
447; GFX9-NEXT:    v_xor_b32_e32 v0, s0, v5
448; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v1, vcc
449; GFX9-NEXT:    v_xor_b32_e32 v1, s1, v3
450; GFX9-NEXT:    v_mov_b32_e32 v3, s1
451; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s0, v0
452; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
453; GFX9-NEXT:    v_xor_b32_e32 v3, s2, v6
454; GFX9-NEXT:    v_xor_b32_e32 v5, s2, v2
455; GFX9-NEXT:    v_mov_b32_e32 v6, s2
456; GFX9-NEXT:    v_subrev_co_u32_e32 v2, vcc, s2, v3
457; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v5, v6, vcc
458; GFX9-NEXT:    global_store_dwordx2 v4, v[0:1], s[4:5]
459; GFX9-NEXT:    global_store_dwordx2 v4, v[2:3], s[6:7]
460; GFX9-NEXT:    s_endpgm
461;
462; GFX10-LABEL: sdivrem_i64:
463; GFX10:       ; %bb.0:
464; GFX10-NEXT:    s_load_dwordx8 s[4:11], s[4:5], 0x0
465; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
466; GFX10-NEXT:    s_ashr_i32 s2, s9, 31
467; GFX10-NEXT:    s_ashr_i32 s12, s11, 31
468; GFX10-NEXT:    s_add_u32 s0, s8, s2
469; GFX10-NEXT:    s_addc_u32 s1, s9, s2
470; GFX10-NEXT:    s_add_u32 s8, s10, s12
471; GFX10-NEXT:    s_mov_b32 s13, s12
472; GFX10-NEXT:    s_addc_u32 s9, s11, s12
473; GFX10-NEXT:    s_mov_b32 s3, s2
474; GFX10-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
475; GFX10-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
476; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s9
477; GFX10-NEXT:    v_cvt_f32_u32_e32 v1, s8
478; GFX10-NEXT:    s_sub_u32 s10, 0, s8
479; GFX10-NEXT:    s_subb_u32 s11, 0, s9
480; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0
481; GFX10-NEXT:    v_add_f32_e32 v0, v0, v1
482; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
483; GFX10-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
484; GFX10-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
485; GFX10-NEXT:    v_trunc_f32_e32 v1, v1
486; GFX10-NEXT:    v_mul_f32_e32 v2, 0xcf800000, v1
487; GFX10-NEXT:    v_add_f32_e32 v0, v2, v0
488; GFX10-NEXT:    v_cvt_u32_f32_e32 v2, v1
489; GFX10-NEXT:    v_cvt_u32_f32_e32 v3, v0
490; GFX10-NEXT:    v_mul_lo_u32 v4, s10, v2
491; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s14, s10, v3, 0
492; GFX10-NEXT:    v_mul_lo_u32 v5, s11, v3
493; GFX10-NEXT:    v_mul_hi_u32 v6, v2, v0
494; GFX10-NEXT:    v_add3_u32 v1, v1, v4, v5
495; GFX10-NEXT:    v_mul_lo_u32 v4, v2, v0
496; GFX10-NEXT:    v_mul_hi_u32 v0, v3, v0
497; GFX10-NEXT:    v_mul_lo_u32 v5, v3, v1
498; GFX10-NEXT:    v_mul_lo_u32 v7, v2, v1
499; GFX10-NEXT:    v_mul_hi_u32 v8, v3, v1
500; GFX10-NEXT:    v_mul_hi_u32 v1, v2, v1
501; GFX10-NEXT:    v_add_co_u32 v4, s14, v4, v5
502; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s14
503; GFX10-NEXT:    v_add_co_u32 v6, s14, v7, v6
504; GFX10-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s14
505; GFX10-NEXT:    v_add_co_u32 v0, s14, v4, v0
506; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s14
507; GFX10-NEXT:    v_add_co_u32 v4, s14, v6, v8
508; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s14
509; GFX10-NEXT:    v_add_nc_u32_e32 v0, v5, v0
510; GFX10-NEXT:    v_add_nc_u32_e32 v5, v7, v6
511; GFX10-NEXT:    v_add_co_u32 v0, s14, v4, v0
512; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s14
513; GFX10-NEXT:    v_add_co_u32 v3, vcc_lo, v3, v0
514; GFX10-NEXT:    v_add3_u32 v1, v5, v4, v1
515; GFX10-NEXT:    v_mul_lo_u32 v4, s11, v3
516; GFX10-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, v2, v1, vcc_lo
517; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s14, s10, v3, 0
518; GFX10-NEXT:    v_mul_lo_u32 v5, s10, v2
519; GFX10-NEXT:    v_mul_hi_u32 v6, v2, v0
520; GFX10-NEXT:    v_add3_u32 v1, v1, v5, v4
521; GFX10-NEXT:    v_mul_lo_u32 v4, v2, v0
522; GFX10-NEXT:    v_mul_hi_u32 v0, v3, v0
523; GFX10-NEXT:    v_mul_lo_u32 v5, v3, v1
524; GFX10-NEXT:    v_mul_lo_u32 v7, v2, v1
525; GFX10-NEXT:    v_mul_hi_u32 v8, v3, v1
526; GFX10-NEXT:    v_mul_hi_u32 v1, v2, v1
527; GFX10-NEXT:    v_add_co_u32 v4, s10, v4, v5
528; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s10
529; GFX10-NEXT:    v_add_co_u32 v6, s10, v7, v6
530; GFX10-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s10
531; GFX10-NEXT:    v_add_co_u32 v0, s10, v4, v0
532; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s10
533; GFX10-NEXT:    v_add_co_u32 v4, s10, v6, v8
534; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s10
535; GFX10-NEXT:    v_add_nc_u32_e32 v0, v5, v0
536; GFX10-NEXT:    v_add_nc_u32_e32 v5, v7, v6
537; GFX10-NEXT:    v_add_co_u32 v0, s10, v4, v0
538; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s10
539; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v3, v0
540; GFX10-NEXT:    v_add3_u32 v1, v5, v4, v1
541; GFX10-NEXT:    v_mul_hi_u32 v4, s1, v0
542; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v2, v1, vcc_lo
543; GFX10-NEXT:    v_mul_lo_u32 v2, s1, v0
544; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v0
545; GFX10-NEXT:    v_mul_lo_u32 v3, s0, v1
546; GFX10-NEXT:    v_mul_lo_u32 v5, s1, v1
547; GFX10-NEXT:    v_mul_hi_u32 v6, s0, v1
548; GFX10-NEXT:    v_mul_hi_u32 v1, s1, v1
549; GFX10-NEXT:    v_add_co_u32 v2, s10, v2, v3
550; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s10
551; GFX10-NEXT:    v_add_co_u32 v4, s10, v5, v4
552; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s10
553; GFX10-NEXT:    v_add_co_u32 v0, s10, v2, v0
554; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s10
555; GFX10-NEXT:    v_add_co_u32 v2, s10, v4, v6
556; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s10
557; GFX10-NEXT:    v_add_nc_u32_e32 v0, v3, v0
558; GFX10-NEXT:    v_add_nc_u32_e32 v3, v5, v4
559; GFX10-NEXT:    v_add_co_u32 v2, s10, v2, v0
560; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s10
561; GFX10-NEXT:    v_mul_lo_u32 v4, s9, v2
562; GFX10-NEXT:    v_add_co_u32 v6, vcc_lo, v2, 1
563; GFX10-NEXT:    v_add3_u32 v3, v3, v0, v1
564; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s10, s8, v2, 0
565; GFX10-NEXT:    v_mul_lo_u32 v5, s8, v3
566; GFX10-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
567; GFX10-NEXT:    v_add3_u32 v1, v1, v5, v4
568; GFX10-NEXT:    v_add_co_u32 v4, vcc_lo, v6, 1
569; GFX10-NEXT:    v_add_co_ci_u32_e32 v5, vcc_lo, 0, v7, vcc_lo
570; GFX10-NEXT:    v_sub_nc_u32_e32 v8, s1, v1
571; GFX10-NEXT:    v_sub_co_u32 v0, vcc_lo, s0, v0
572; GFX10-NEXT:    v_sub_co_ci_u32_e64 v1, s0, s1, v1, vcc_lo
573; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
574; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s8, v0
575; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc_lo
576; GFX10-NEXT:    v_sub_co_u32 v10, vcc_lo, v0, s8
577; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v11, s0, 0, v8, vcc_lo
578; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s9, v1
579; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
580; GFX10-NEXT:    v_cmp_eq_u32_e32 vcc_lo, s9, v11
581; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s0
582; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s8, v10
583; GFX10-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s0
584; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s9, v11
585; GFX10-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s0
586; GFX10-NEXT:    v_cmp_eq_u32_e64 s0, s9, v1
587; GFX10-NEXT:    v_cndmask_b32_e64 v9, v12, v9, s0
588; GFX10-NEXT:    v_cndmask_b32_e32 v12, v14, v13, vcc_lo
589; GFX10-NEXT:    v_sub_co_u32 v13, vcc_lo, v10, s8
590; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
591; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
592; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v12
593; GFX10-NEXT:    v_cmp_ne_u32_e64 s1, 0, v9
594; GFX10-NEXT:    s_xor_b64 s[8:9], s[2:3], s[12:13]
595; GFX10-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc_lo
596; GFX10-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc_lo
597; GFX10-NEXT:    v_cndmask_b32_e64 v6, v10, v13, s0
598; GFX10-NEXT:    v_cndmask_b32_e64 v7, v11, v8, s0
599; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, v4, s1
600; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s1
601; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, v6, s1
602; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v7, s1
603; GFX10-NEXT:    v_mov_b32_e32 v4, 0
604; GFX10-NEXT:    v_xor_b32_e32 v2, s8, v2
605; GFX10-NEXT:    v_xor_b32_e32 v3, s9, v3
606; GFX10-NEXT:    v_xor_b32_e32 v5, s2, v0
607; GFX10-NEXT:    v_xor_b32_e32 v6, s2, v1
608; GFX10-NEXT:    v_sub_co_u32 v0, vcc_lo, v2, s8
609; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v1, vcc_lo, s9, v3, vcc_lo
610; GFX10-NEXT:    v_sub_co_u32 v2, vcc_lo, v5, s2
611; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v3, vcc_lo, s2, v6, vcc_lo
612; GFX10-NEXT:    global_store_dwordx2 v4, v[0:1], s[4:5]
613; GFX10-NEXT:    global_store_dwordx2 v4, v[2:3], s[6:7]
614; GFX10-NEXT:    s_endpgm
615  %div = sdiv i64 %x, %y
616  store i64 %div, i64 addrspace(1)* %out0
617  %rem = srem i64 %x, %y
618  store i64 %rem, i64 addrspace(1)* %out1
619  ret void
620}
621
622define amdgpu_kernel void @sdivrem_v2i32(<2 x i32> addrspace(1)* %out0, <2 x i32> addrspace(1)* %out1, <2 x i32> %x, <2 x i32> %y) {
623; GFX8-LABEL: sdivrem_v2i32:
624; GFX8:       ; %bb.0:
625; GFX8-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x10
626; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
627; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
628; GFX8-NEXT:    s_ashr_i32 s2, s10, 31
629; GFX8-NEXT:    s_add_i32 s0, s10, s2
630; GFX8-NEXT:    s_xor_b32 s3, s0, s2
631; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s3
632; GFX8-NEXT:    s_sub_i32 s1, 0, s3
633; GFX8-NEXT:    s_ashr_i32 s12, s11, 31
634; GFX8-NEXT:    s_add_i32 s0, s11, s12
635; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
636; GFX8-NEXT:    s_xor_b32 s11, s0, s12
637; GFX8-NEXT:    v_cvt_f32_u32_e32 v2, s11
638; GFX8-NEXT:    s_ashr_i32 s10, s8, 31
639; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
640; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0
641; GFX8-NEXT:    s_add_i32 s0, s8, s10
642; GFX8-NEXT:    s_xor_b32 s0, s0, s10
643; GFX8-NEXT:    v_rcp_iflag_f32_e32 v2, v2
644; GFX8-NEXT:    v_mul_lo_u32 v1, s1, v0
645; GFX8-NEXT:    s_sub_i32 s8, 0, s11
646; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v1
647; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
648; GFX8-NEXT:    v_mul_hi_u32 v0, s0, v0
649; GFX8-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v2
650; GFX8-NEXT:    v_cvt_u32_f32_e32 v1, v1
651; GFX8-NEXT:    v_mul_lo_u32 v2, v0, s3
652; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v0
653; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, s0, v2
654; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2
655; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
656; GFX8-NEXT:    v_subrev_u32_e64 v3, s[0:1], s3, v2
657; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
658; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v0
659; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2
660; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
661; GFX8-NEXT:    v_subrev_u32_e64 v3, s[0:1], s3, v2
662; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
663; GFX8-NEXT:    v_mul_lo_u32 v3, s8, v1
664; GFX8-NEXT:    s_xor_b32 s0, s10, s2
665; GFX8-NEXT:    s_ashr_i32 s2, s9, 31
666; GFX8-NEXT:    s_add_i32 s1, s9, s2
667; GFX8-NEXT:    v_mul_hi_u32 v3, v1, v3
668; GFX8-NEXT:    s_xor_b32 s1, s1, s2
669; GFX8-NEXT:    v_xor_b32_e32 v0, s0, v0
670; GFX8-NEXT:    v_xor_b32_e32 v2, s10, v2
671; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v3
672; GFX8-NEXT:    v_mul_hi_u32 v1, s1, v1
673; GFX8-NEXT:    v_subrev_u32_e32 v0, vcc, s0, v0
674; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s10, v2
675; GFX8-NEXT:    v_mul_lo_u32 v3, v1, s11
676; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v1
677; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s1, v3
678; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
679; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
680; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s11, v3
681; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
682; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v1
683; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
684; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
685; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s11, v3
686; GFX8-NEXT:    s_xor_b32 s0, s2, s12
687; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
688; GFX8-NEXT:    v_xor_b32_e32 v1, s0, v1
689; GFX8-NEXT:    v_mov_b32_e32 v4, s4
690; GFX8-NEXT:    v_subrev_u32_e32 v1, vcc, s0, v1
691; GFX8-NEXT:    v_mov_b32_e32 v5, s5
692; GFX8-NEXT:    v_xor_b32_e32 v3, s2, v3
693; GFX8-NEXT:    flat_store_dwordx2 v[4:5], v[0:1]
694; GFX8-NEXT:    v_mov_b32_e32 v0, s6
695; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, s2, v3
696; GFX8-NEXT:    v_mov_b32_e32 v1, s7
697; GFX8-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
698; GFX8-NEXT:    s_endpgm
699;
700; GFX9-LABEL: sdivrem_v2i32:
701; GFX9:       ; %bb.0:
702; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x10
703; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
704; GFX9-NEXT:    s_ashr_i32 s6, s10, 31
705; GFX9-NEXT:    s_add_i32 s0, s10, s6
706; GFX9-NEXT:    s_xor_b32 s7, s0, s6
707; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s7
708; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
709; GFX9-NEXT:    s_ashr_i32 s4, s11, 31
710; GFX9-NEXT:    s_add_i32 s5, s11, s4
711; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
712; GFX9-NEXT:    s_xor_b32 s5, s5, s4
713; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s5
714; GFX9-NEXT:    s_sub_i32 s11, 0, s7
715; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
716; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
717; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
718; GFX9-NEXT:    s_ashr_i32 s10, s8, 31
719; GFX9-NEXT:    s_add_i32 s8, s8, s10
720; GFX9-NEXT:    v_mul_lo_u32 v2, s11, v0
721; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
722; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
723; GFX9-NEXT:    s_xor_b32 s8, s8, s10
724; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
725; GFX9-NEXT:    s_sub_i32 s11, 0, s5
726; GFX9-NEXT:    v_mul_lo_u32 v3, s11, v1
727; GFX9-NEXT:    s_ashr_i32 s11, s9, 31
728; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
729; GFX9-NEXT:    v_mul_hi_u32 v0, s8, v0
730; GFX9-NEXT:    v_mul_hi_u32 v2, v1, v3
731; GFX9-NEXT:    s_add_i32 s9, s9, s11
732; GFX9-NEXT:    s_xor_b32 s9, s9, s11
733; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s7
734; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
735; GFX9-NEXT:    v_add_u32_e32 v2, 1, v0
736; GFX9-NEXT:    v_mul_hi_u32 v1, s9, v1
737; GFX9-NEXT:    v_sub_u32_e32 v3, s8, v3
738; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v3
739; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
740; GFX9-NEXT:    v_subrev_u32_e32 v2, s7, v3
741; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
742; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
743; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v2
744; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
745; GFX9-NEXT:    v_subrev_u32_e32 v3, s7, v2
746; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
747; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s5
748; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
749; GFX9-NEXT:    s_xor_b32 s6, s10, s6
750; GFX9-NEXT:    s_xor_b32 s4, s11, s4
751; GFX9-NEXT:    v_sub_u32_e32 v3, s9, v3
752; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v3
753; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
754; GFX9-NEXT:    v_subrev_u32_e32 v4, s5, v3
755; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
756; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
757; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v3
758; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
759; GFX9-NEXT:    v_subrev_u32_e32 v4, s5, v3
760; GFX9-NEXT:    v_xor_b32_e32 v0, s6, v0
761; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
762; GFX9-NEXT:    v_xor_b32_e32 v1, s4, v1
763; GFX9-NEXT:    v_subrev_u32_e32 v0, s6, v0
764; GFX9-NEXT:    v_xor_b32_e32 v2, s10, v2
765; GFX9-NEXT:    v_subrev_u32_e32 v1, s4, v1
766; GFX9-NEXT:    v_xor_b32_e32 v3, s11, v3
767; GFX9-NEXT:    v_mov_b32_e32 v4, 0
768; GFX9-NEXT:    v_subrev_u32_e32 v2, s10, v2
769; GFX9-NEXT:    v_subrev_u32_e32 v3, s11, v3
770; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
771; GFX9-NEXT:    global_store_dwordx2 v4, v[0:1], s[0:1]
772; GFX9-NEXT:    global_store_dwordx2 v4, v[2:3], s[2:3]
773; GFX9-NEXT:    s_endpgm
774;
775; GFX10-LABEL: sdivrem_v2i32:
776; GFX10:       ; %bb.0:
777; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x10
778; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
779; GFX10-NEXT:    s_ashr_i32 s8, s2, 31
780; GFX10-NEXT:    s_ashr_i32 s9, s3, 31
781; GFX10-NEXT:    s_add_i32 s2, s2, s8
782; GFX10-NEXT:    s_add_i32 s3, s3, s9
783; GFX10-NEXT:    s_xor_b32 s2, s2, s8
784; GFX10-NEXT:    s_xor_b32 s3, s3, s9
785; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s2
786; GFX10-NEXT:    v_cvt_f32_u32_e32 v1, s3
787; GFX10-NEXT:    s_sub_i32 s6, 0, s2
788; GFX10-NEXT:    s_sub_i32 s7, 0, s3
789; GFX10-NEXT:    s_ashr_i32 s10, s0, 31
790; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
791; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v1
792; GFX10-NEXT:    s_ashr_i32 s11, s1, 31
793; GFX10-NEXT:    s_add_i32 s0, s0, s10
794; GFX10-NEXT:    s_add_i32 s1, s1, s11
795; GFX10-NEXT:    s_xor_b32 s0, s0, s10
796; GFX10-NEXT:    s_xor_b32 s1, s1, s11
797; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
798; GFX10-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
799; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
800; GFX10-NEXT:    v_cvt_u32_f32_e32 v1, v1
801; GFX10-NEXT:    v_mul_lo_u32 v2, s6, v0
802; GFX10-NEXT:    v_mul_lo_u32 v3, s7, v1
803; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
804; GFX10-NEXT:    v_mul_hi_u32 v2, v0, v2
805; GFX10-NEXT:    v_mul_hi_u32 v3, v1, v3
806; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v2
807; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v3
808; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v0
809; GFX10-NEXT:    v_mul_hi_u32 v1, s1, v1
810; GFX10-NEXT:    v_mul_lo_u32 v2, v0, s2
811; GFX10-NEXT:    v_mul_lo_u32 v3, v1, s3
812; GFX10-NEXT:    v_add_nc_u32_e32 v4, 1, v0
813; GFX10-NEXT:    v_add_nc_u32_e32 v5, 1, v1
814; GFX10-NEXT:    v_sub_nc_u32_e32 v2, s0, v2
815; GFX10-NEXT:    v_sub_nc_u32_e32 v3, s1, v3
816; GFX10-NEXT:    s_xor_b32 s1, s10, s8
817; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, s2, v2
818; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s3, v3
819; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s2, v2
820; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, s3, v3
821; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc_lo
822; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s0
823; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, v6, s0
824; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc_lo
825; GFX10-NEXT:    v_add_nc_u32_e32 v5, 1, v1
826; GFX10-NEXT:    v_add_nc_u32_e32 v4, 1, v0
827; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s2, v2
828; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s3, v3
829; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, s2, v2
830; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, s3, v3
831; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s0
832; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc_lo
833; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, v6, s0
834; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc_lo
835; GFX10-NEXT:    s_xor_b32 s0, s11, s9
836; GFX10-NEXT:    v_xor_b32_e32 v0, s1, v0
837; GFX10-NEXT:    v_xor_b32_e32 v1, s0, v1
838; GFX10-NEXT:    v_xor_b32_e32 v2, s10, v2
839; GFX10-NEXT:    v_xor_b32_e32 v3, s11, v3
840; GFX10-NEXT:    v_mov_b32_e32 v4, 0
841; GFX10-NEXT:    v_subrev_nc_u32_e32 v0, s1, v0
842; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, s0, v1
843; GFX10-NEXT:    v_subrev_nc_u32_e32 v2, s10, v2
844; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s11, v3
845; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
846; GFX10-NEXT:    global_store_dwordx2 v4, v[0:1], s[4:5]
847; GFX10-NEXT:    global_store_dwordx2 v4, v[2:3], s[6:7]
848; GFX10-NEXT:    s_endpgm
849  %div = sdiv <2 x i32> %x, %y
850  store <2 x i32> %div, <2 x i32> addrspace(1)* %out0
851  %rem = srem <2 x i32> %x, %y
852  store <2 x i32> %rem, <2 x i32> addrspace(1)* %out1
853  ret void
854}
855
856define amdgpu_kernel void @sdivrem_v4i32(<4 x i32> addrspace(1)* %out0, <4 x i32> addrspace(1)* %out1, <4 x i32> %x, <4 x i32> %y) {
857; GFX8-LABEL: sdivrem_v4i32:
858; GFX8:       ; %bb.0:
859; GFX8-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x10
860; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
861; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
862; GFX8-NEXT:    s_ashr_i32 s2, s12, 31
863; GFX8-NEXT:    s_add_i32 s0, s12, s2
864; GFX8-NEXT:    s_xor_b32 s3, s0, s2
865; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s3
866; GFX8-NEXT:    s_sub_i32 s1, 0, s3
867; GFX8-NEXT:    s_ashr_i32 s16, s13, 31
868; GFX8-NEXT:    s_add_i32 s0, s13, s16
869; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
870; GFX8-NEXT:    s_xor_b32 s13, s0, s16
871; GFX8-NEXT:    v_cvt_f32_u32_e32 v2, s13
872; GFX8-NEXT:    s_ashr_i32 s12, s8, 31
873; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
874; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0
875; GFX8-NEXT:    s_add_i32 s0, s8, s12
876; GFX8-NEXT:    s_xor_b32 s0, s0, s12
877; GFX8-NEXT:    v_rcp_iflag_f32_e32 v2, v2
878; GFX8-NEXT:    v_mul_lo_u32 v1, s1, v0
879; GFX8-NEXT:    s_sub_i32 s8, 0, s13
880; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v1
881; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
882; GFX8-NEXT:    v_mul_hi_u32 v0, s0, v0
883; GFX8-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v2
884; GFX8-NEXT:    v_cvt_u32_f32_e32 v1, v1
885; GFX8-NEXT:    v_mul_lo_u32 v2, v0, s3
886; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v0
887; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, s0, v2
888; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2
889; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
890; GFX8-NEXT:    v_subrev_u32_e64 v3, s[0:1], s3, v2
891; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
892; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v0
893; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2
894; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
895; GFX8-NEXT:    v_subrev_u32_e64 v3, s[0:1], s3, v2
896; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
897; GFX8-NEXT:    v_mul_lo_u32 v3, s8, v1
898; GFX8-NEXT:    s_xor_b32 s0, s12, s2
899; GFX8-NEXT:    s_ashr_i32 s2, s9, 31
900; GFX8-NEXT:    s_add_i32 s1, s9, s2
901; GFX8-NEXT:    v_mul_hi_u32 v3, v1, v3
902; GFX8-NEXT:    s_xor_b32 s1, s1, s2
903; GFX8-NEXT:    v_xor_b32_e32 v0, s0, v0
904; GFX8-NEXT:    v_xor_b32_e32 v2, s12, v2
905; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v3
906; GFX8-NEXT:    v_mul_hi_u32 v1, s1, v1
907; GFX8-NEXT:    s_ashr_i32 s3, s14, 31
908; GFX8-NEXT:    v_subrev_u32_e32 v0, vcc, s0, v0
909; GFX8-NEXT:    v_mul_lo_u32 v3, v1, s13
910; GFX8-NEXT:    v_subrev_u32_e32 v4, vcc, s12, v2
911; GFX8-NEXT:    s_add_i32 s0, s14, s3
912; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, s1, v3
913; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v1
914; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s13, v2
915; GFX8-NEXT:    s_xor_b32 s8, s0, s3
916; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
917; GFX8-NEXT:    v_cvt_f32_u32_e32 v3, s8
918; GFX8-NEXT:    v_subrev_u32_e64 v5, s[0:1], s13, v2
919; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
920; GFX8-NEXT:    v_rcp_iflag_f32_e32 v3, v3
921; GFX8-NEXT:    v_add_u32_e32 v5, vcc, 1, v1
922; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s13, v2
923; GFX8-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
924; GFX8-NEXT:    v_cvt_u32_f32_e32 v3, v3
925; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
926; GFX8-NEXT:    v_subrev_u32_e64 v5, s[0:1], s13, v2
927; GFX8-NEXT:    s_sub_i32 s0, 0, s8
928; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
929; GFX8-NEXT:    v_mul_lo_u32 v5, s0, v3
930; GFX8-NEXT:    s_ashr_i32 s9, s10, 31
931; GFX8-NEXT:    s_add_i32 s1, s10, s9
932; GFX8-NEXT:    s_xor_b32 s1, s1, s9
933; GFX8-NEXT:    v_mul_hi_u32 v5, v3, v5
934; GFX8-NEXT:    s_xor_b32 s0, s2, s16
935; GFX8-NEXT:    v_xor_b32_e32 v2, s2, v2
936; GFX8-NEXT:    v_xor_b32_e32 v1, s0, v1
937; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v3, v5
938; GFX8-NEXT:    v_mul_hi_u32 v3, s1, v3
939; GFX8-NEXT:    v_subrev_u32_e32 v5, vcc, s2, v2
940; GFX8-NEXT:    s_ashr_i32 s2, s15, 31
941; GFX8-NEXT:    v_mul_lo_u32 v6, v3, s8
942; GFX8-NEXT:    v_subrev_u32_e32 v1, vcc, s0, v1
943; GFX8-NEXT:    s_add_i32 s0, s15, s2
944; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, s1, v6
945; GFX8-NEXT:    v_add_u32_e32 v6, vcc, 1, v3
946; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
947; GFX8-NEXT:    s_xor_b32 s10, s0, s2
948; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
949; GFX8-NEXT:    v_cvt_f32_u32_e32 v6, s10
950; GFX8-NEXT:    v_subrev_u32_e64 v7, s[0:1], s8, v2
951; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v7, vcc
952; GFX8-NEXT:    v_rcp_iflag_f32_e32 v6, v6
953; GFX8-NEXT:    v_add_u32_e32 v7, vcc, 1, v3
954; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
955; GFX8-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
956; GFX8-NEXT:    v_cvt_u32_f32_e32 v6, v6
957; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc
958; GFX8-NEXT:    v_subrev_u32_e64 v7, s[0:1], s8, v2
959; GFX8-NEXT:    s_sub_i32 s0, 0, s10
960; GFX8-NEXT:    v_cndmask_b32_e32 v7, v2, v7, vcc
961; GFX8-NEXT:    v_mul_lo_u32 v2, s0, v6
962; GFX8-NEXT:    s_xor_b32 s0, s9, s3
963; GFX8-NEXT:    s_ashr_i32 s3, s11, 31
964; GFX8-NEXT:    s_add_i32 s1, s11, s3
965; GFX8-NEXT:    v_mul_hi_u32 v2, v6, v2
966; GFX8-NEXT:    s_xor_b32 s1, s1, s3
967; GFX8-NEXT:    v_xor_b32_e32 v3, s0, v3
968; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v6, v2
969; GFX8-NEXT:    v_mul_hi_u32 v8, s1, v2
970; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s0, v3
971; GFX8-NEXT:    v_xor_b32_e32 v3, s9, v7
972; GFX8-NEXT:    v_mul_lo_u32 v7, v8, s10
973; GFX8-NEXT:    v_subrev_u32_e32 v6, vcc, s9, v3
974; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s1, v7
975; GFX8-NEXT:    v_add_u32_e32 v7, vcc, 1, v8
976; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
977; GFX8-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc
978; GFX8-NEXT:    v_subrev_u32_e64 v8, s[0:1], s10, v3
979; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v8, vcc
980; GFX8-NEXT:    v_add_u32_e32 v8, vcc, 1, v7
981; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
982; GFX8-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
983; GFX8-NEXT:    v_subrev_u32_e64 v8, s[0:1], s10, v3
984; GFX8-NEXT:    v_cndmask_b32_e32 v8, v3, v8, vcc
985; GFX8-NEXT:    s_xor_b32 s0, s3, s2
986; GFX8-NEXT:    v_xor_b32_e32 v3, s0, v7
987; GFX8-NEXT:    v_xor_b32_e32 v7, s3, v8
988; GFX8-NEXT:    v_mov_b32_e32 v9, s5
989; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, s0, v3
990; GFX8-NEXT:    v_mov_b32_e32 v8, s4
991; GFX8-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]
992; GFX8-NEXT:    v_subrev_u32_e32 v7, vcc, s3, v7
993; GFX8-NEXT:    v_mov_b32_e32 v0, s6
994; GFX8-NEXT:    v_mov_b32_e32 v1, s7
995; GFX8-NEXT:    flat_store_dwordx4 v[0:1], v[4:7]
996; GFX8-NEXT:    s_endpgm
997;
998; GFX9-LABEL: sdivrem_v4i32:
999; GFX9:       ; %bb.0:
1000; GFX9-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x10
1001; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1002; GFX9-NEXT:    s_ashr_i32 s6, s12, 31
1003; GFX9-NEXT:    s_add_i32 s0, s12, s6
1004; GFX9-NEXT:    s_xor_b32 s7, s0, s6
1005; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s7
1006; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1007; GFX9-NEXT:    s_ashr_i32 s4, s13, 31
1008; GFX9-NEXT:    s_add_i32 s5, s13, s4
1009; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1010; GFX9-NEXT:    s_xor_b32 s5, s5, s4
1011; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s5
1012; GFX9-NEXT:    s_sub_i32 s13, 0, s7
1013; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1014; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
1015; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1016; GFX9-NEXT:    s_ashr_i32 s12, s8, 31
1017; GFX9-NEXT:    s_add_i32 s8, s8, s12
1018; GFX9-NEXT:    v_mul_lo_u32 v2, s13, v0
1019; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
1020; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
1021; GFX9-NEXT:    s_xor_b32 s8, s8, s12
1022; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
1023; GFX9-NEXT:    s_sub_i32 s13, 0, s5
1024; GFX9-NEXT:    v_mul_lo_u32 v3, s13, v1
1025; GFX9-NEXT:    s_ashr_i32 s13, s9, 31
1026; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
1027; GFX9-NEXT:    v_mul_hi_u32 v0, s8, v0
1028; GFX9-NEXT:    v_mul_hi_u32 v2, v1, v3
1029; GFX9-NEXT:    s_add_i32 s9, s9, s13
1030; GFX9-NEXT:    s_xor_b32 s9, s9, s13
1031; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s7
1032; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
1033; GFX9-NEXT:    v_add_u32_e32 v2, 1, v0
1034; GFX9-NEXT:    v_mul_hi_u32 v1, s9, v1
1035; GFX9-NEXT:    v_sub_u32_e32 v3, s8, v3
1036; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v3
1037; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1038; GFX9-NEXT:    v_subrev_u32_e32 v2, s7, v3
1039; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
1040; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
1041; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v2
1042; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1043; GFX9-NEXT:    v_subrev_u32_e32 v3, s7, v2
1044; GFX9-NEXT:    s_xor_b32 s6, s12, s6
1045; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
1046; GFX9-NEXT:    v_xor_b32_e32 v0, s6, v0
1047; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s5
1048; GFX9-NEXT:    v_subrev_u32_e32 v0, s6, v0
1049; GFX9-NEXT:    s_ashr_i32 s6, s14, 31
1050; GFX9-NEXT:    s_add_i32 s7, s14, s6
1051; GFX9-NEXT:    v_xor_b32_e32 v2, s12, v2
1052; GFX9-NEXT:    s_xor_b32 s7, s7, s6
1053; GFX9-NEXT:    v_subrev_u32_e32 v4, s12, v2
1054; GFX9-NEXT:    v_sub_u32_e32 v2, s9, v3
1055; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, s7
1056; GFX9-NEXT:    v_add_u32_e32 v5, 1, v1
1057; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v2
1058; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
1059; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1060; GFX9-NEXT:    v_subrev_u32_e32 v5, s5, v2
1061; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
1062; GFX9-NEXT:    v_add_u32_e32 v5, 1, v1
1063; GFX9-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
1064; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
1065; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v2
1066; GFX9-NEXT:    s_sub_i32 s8, 0, s7
1067; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
1068; GFX9-NEXT:    v_mul_lo_u32 v5, s8, v3
1069; GFX9-NEXT:    s_xor_b32 s4, s13, s4
1070; GFX9-NEXT:    v_xor_b32_e32 v1, s4, v1
1071; GFX9-NEXT:    v_subrev_u32_e32 v1, s4, v1
1072; GFX9-NEXT:    s_ashr_i32 s4, s15, 31
1073; GFX9-NEXT:    s_add_i32 s9, s15, s4
1074; GFX9-NEXT:    v_mul_hi_u32 v5, v3, v5
1075; GFX9-NEXT:    s_xor_b32 s9, s9, s4
1076; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s9
1077; GFX9-NEXT:    v_subrev_u32_e32 v6, s5, v2
1078; GFX9-NEXT:    s_ashr_i32 s5, s10, 31
1079; GFX9-NEXT:    s_add_i32 s8, s10, s5
1080; GFX9-NEXT:    s_xor_b32 s8, s8, s5
1081; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
1082; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v3
1083; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v7
1084; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
1085; GFX9-NEXT:    v_xor_b32_e32 v2, s13, v2
1086; GFX9-NEXT:    v_mul_lo_u32 v6, v3, s7
1087; GFX9-NEXT:    v_mul_f32_e32 v7, 0x4f7ffffe, v7
1088; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v7
1089; GFX9-NEXT:    v_subrev_u32_e32 v5, s13, v2
1090; GFX9-NEXT:    v_sub_u32_e32 v2, s8, v6
1091; GFX9-NEXT:    s_sub_i32 s8, 0, s9
1092; GFX9-NEXT:    v_mul_lo_u32 v8, s8, v7
1093; GFX9-NEXT:    v_add_u32_e32 v6, 1, v3
1094; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v2
1095; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
1096; GFX9-NEXT:    v_subrev_u32_e32 v6, s7, v2
1097; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
1098; GFX9-NEXT:    v_mul_hi_u32 v8, v7, v8
1099; GFX9-NEXT:    v_add_u32_e32 v6, 1, v3
1100; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v2
1101; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
1102; GFX9-NEXT:    v_subrev_u32_e32 v6, s7, v2
1103; GFX9-NEXT:    s_ashr_i32 s7, s11, 31
1104; GFX9-NEXT:    s_add_i32 s8, s11, s7
1105; GFX9-NEXT:    s_xor_b32 s8, s8, s7
1106; GFX9-NEXT:    v_add_u32_e32 v7, v7, v8
1107; GFX9-NEXT:    v_mul_hi_u32 v7, s8, v7
1108; GFX9-NEXT:    s_xor_b32 s6, s5, s6
1109; GFX9-NEXT:    v_cndmask_b32_e32 v6, v2, v6, vcc
1110; GFX9-NEXT:    v_xor_b32_e32 v2, s6, v3
1111; GFX9-NEXT:    v_mul_lo_u32 v3, v7, s9
1112; GFX9-NEXT:    v_add_u32_e32 v8, 1, v7
1113; GFX9-NEXT:    s_xor_b32 s4, s7, s4
1114; GFX9-NEXT:    v_subrev_u32_e32 v2, s6, v2
1115; GFX9-NEXT:    v_sub_u32_e32 v3, s8, v3
1116; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
1117; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
1118; GFX9-NEXT:    v_subrev_u32_e32 v8, s9, v3
1119; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v8, vcc
1120; GFX9-NEXT:    v_add_u32_e32 v8, 1, v7
1121; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
1122; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
1123; GFX9-NEXT:    v_subrev_u32_e32 v8, s9, v3
1124; GFX9-NEXT:    v_cndmask_b32_e32 v8, v3, v8, vcc
1125; GFX9-NEXT:    v_xor_b32_e32 v3, s4, v7
1126; GFX9-NEXT:    v_xor_b32_e32 v6, s5, v6
1127; GFX9-NEXT:    v_subrev_u32_e32 v3, s4, v3
1128; GFX9-NEXT:    v_xor_b32_e32 v7, s7, v8
1129; GFX9-NEXT:    v_mov_b32_e32 v8, 0
1130; GFX9-NEXT:    v_subrev_u32_e32 v6, s5, v6
1131; GFX9-NEXT:    v_subrev_u32_e32 v7, s7, v7
1132; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1133; GFX9-NEXT:    global_store_dwordx4 v8, v[0:3], s[0:1]
1134; GFX9-NEXT:    global_store_dwordx4 v8, v[4:7], s[2:3]
1135; GFX9-NEXT:    s_endpgm
1136;
1137; GFX10-LABEL: sdivrem_v4i32:
1138; GFX10:       ; %bb.0:
1139; GFX10-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x10
1140; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
1141; GFX10-NEXT:    s_ashr_i32 s0, s12, 31
1142; GFX10-NEXT:    s_ashr_i32 s1, s13, 31
1143; GFX10-NEXT:    s_ashr_i32 s2, s14, 31
1144; GFX10-NEXT:    s_ashr_i32 s3, s15, 31
1145; GFX10-NEXT:    s_add_i32 s6, s12, s0
1146; GFX10-NEXT:    s_add_i32 s7, s13, s1
1147; GFX10-NEXT:    s_add_i32 s12, s14, s2
1148; GFX10-NEXT:    s_add_i32 s13, s15, s3
1149; GFX10-NEXT:    s_xor_b32 s14, s6, s0
1150; GFX10-NEXT:    s_xor_b32 s15, s7, s1
1151; GFX10-NEXT:    s_xor_b32 s12, s12, s2
1152; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s14
1153; GFX10-NEXT:    s_xor_b32 s13, s13, s3
1154; GFX10-NEXT:    v_cvt_f32_u32_e32 v1, s15
1155; GFX10-NEXT:    v_cvt_f32_u32_e32 v2, s12
1156; GFX10-NEXT:    v_cvt_f32_u32_e32 v3, s13
1157; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1158; GFX10-NEXT:    s_sub_i32 s6, 0, s14
1159; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1160; GFX10-NEXT:    v_rcp_iflag_f32_e32 v2, v2
1161; GFX10-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1162; GFX10-NEXT:    s_sub_i32 s7, 0, s15
1163; GFX10-NEXT:    s_sub_i32 s19, 0, s12
1164; GFX10-NEXT:    s_ashr_i32 s16, s8, 31
1165; GFX10-NEXT:    s_ashr_i32 s17, s9, 31
1166; GFX10-NEXT:    s_ashr_i32 s18, s10, 31
1167; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1168; GFX10-NEXT:    s_xor_b32 s20, s16, s0
1169; GFX10-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
1170; GFX10-NEXT:    v_mul_f32_e32 v2, 0x4f7ffffe, v2
1171; GFX10-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
1172; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
1173; GFX10-NEXT:    s_xor_b32 s21, s17, s1
1174; GFX10-NEXT:    v_cvt_u32_f32_e32 v1, v1
1175; GFX10-NEXT:    v_cvt_u32_f32_e32 v2, v2
1176; GFX10-NEXT:    v_cvt_u32_f32_e32 v3, v3
1177; GFX10-NEXT:    v_mul_lo_u32 v4, s6, v0
1178; GFX10-NEXT:    s_sub_i32 s6, 0, s13
1179; GFX10-NEXT:    v_mul_lo_u32 v5, s7, v1
1180; GFX10-NEXT:    v_mul_lo_u32 v6, s19, v2
1181; GFX10-NEXT:    v_mul_lo_u32 v7, s6, v3
1182; GFX10-NEXT:    s_ashr_i32 s19, s11, 31
1183; GFX10-NEXT:    s_add_i32 s6, s8, s16
1184; GFX10-NEXT:    s_add_i32 s7, s9, s17
1185; GFX10-NEXT:    v_mul_hi_u32 v4, v0, v4
1186; GFX10-NEXT:    s_add_i32 s8, s10, s18
1187; GFX10-NEXT:    v_mul_hi_u32 v5, v1, v5
1188; GFX10-NEXT:    v_mul_hi_u32 v6, v2, v6
1189; GFX10-NEXT:    v_mul_hi_u32 v7, v3, v7
1190; GFX10-NEXT:    s_add_i32 s9, s11, s19
1191; GFX10-NEXT:    s_xor_b32 s10, s6, s16
1192; GFX10-NEXT:    s_xor_b32 s11, s7, s17
1193; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v4
1194; GFX10-NEXT:    s_xor_b32 s8, s8, s18
1195; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v5
1196; GFX10-NEXT:    v_add_nc_u32_e32 v2, v2, v6
1197; GFX10-NEXT:    v_add_nc_u32_e32 v3, v3, v7
1198; GFX10-NEXT:    s_xor_b32 s9, s9, s19
1199; GFX10-NEXT:    v_mul_hi_u32 v0, s10, v0
1200; GFX10-NEXT:    v_mul_hi_u32 v1, s11, v1
1201; GFX10-NEXT:    v_mul_hi_u32 v2, s8, v2
1202; GFX10-NEXT:    v_mul_hi_u32 v3, s9, v3
1203; GFX10-NEXT:    s_xor_b32 s22, s18, s2
1204; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
1205; GFX10-NEXT:    v_mul_lo_u32 v4, v0, s14
1206; GFX10-NEXT:    v_mul_lo_u32 v5, v1, s15
1207; GFX10-NEXT:    v_mul_lo_u32 v6, v2, s12
1208; GFX10-NEXT:    v_mul_lo_u32 v7, v3, s13
1209; GFX10-NEXT:    v_add_nc_u32_e32 v8, 1, v0
1210; GFX10-NEXT:    v_add_nc_u32_e32 v9, 1, v1
1211; GFX10-NEXT:    v_add_nc_u32_e32 v10, 1, v2
1212; GFX10-NEXT:    v_add_nc_u32_e32 v11, 1, v3
1213; GFX10-NEXT:    v_sub_nc_u32_e32 v4, s10, v4
1214; GFX10-NEXT:    v_sub_nc_u32_e32 v5, s11, v5
1215; GFX10-NEXT:    v_sub_nc_u32_e32 v6, s8, v6
1216; GFX10-NEXT:    v_sub_nc_u32_e32 v7, s9, v7
1217; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s14, v4
1218; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s15, v5
1219; GFX10-NEXT:    v_cmp_le_u32_e64 s1, s12, v6
1220; GFX10-NEXT:    v_cmp_le_u32_e64 s2, s13, v7
1221; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc_lo
1222; GFX10-NEXT:    v_subrev_nc_u32_e32 v8, s14, v4
1223; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v9, s0
1224; GFX10-NEXT:    v_subrev_nc_u32_e32 v9, s15, v5
1225; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, v10, s1
1226; GFX10-NEXT:    v_subrev_nc_u32_e32 v10, s12, v6
1227; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v11, s2
1228; GFX10-NEXT:    v_subrev_nc_u32_e32 v11, s13, v7
1229; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v8, vcc_lo
1230; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v9, s0
1231; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v10, s1
1232; GFX10-NEXT:    v_add_nc_u32_e32 v8, 1, v0
1233; GFX10-NEXT:    v_cndmask_b32_e64 v7, v7, v11, s2
1234; GFX10-NEXT:    v_add_nc_u32_e32 v9, 1, v1
1235; GFX10-NEXT:    v_add_nc_u32_e32 v10, 1, v2
1236; GFX10-NEXT:    v_add_nc_u32_e32 v11, 1, v3
1237; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s14, v4
1238; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s15, v5
1239; GFX10-NEXT:    v_cmp_le_u32_e64 s1, s12, v6
1240; GFX10-NEXT:    v_cmp_le_u32_e64 s2, s13, v7
1241; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc_lo
1242; GFX10-NEXT:    v_subrev_nc_u32_e32 v8, s14, v4
1243; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v9, s0
1244; GFX10-NEXT:    v_subrev_nc_u32_e32 v9, s15, v5
1245; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, v10, s1
1246; GFX10-NEXT:    v_subrev_nc_u32_e32 v10, s12, v6
1247; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v11, s2
1248; GFX10-NEXT:    v_subrev_nc_u32_e32 v11, s13, v7
1249; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v8, vcc_lo
1250; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v9, s0
1251; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v10, s1
1252; GFX10-NEXT:    s_xor_b32 s0, s19, s3
1253; GFX10-NEXT:    v_cndmask_b32_e64 v7, v7, v11, s2
1254; GFX10-NEXT:    v_xor_b32_e32 v0, s20, v0
1255; GFX10-NEXT:    v_xor_b32_e32 v1, s21, v1
1256; GFX10-NEXT:    v_xor_b32_e32 v2, s22, v2
1257; GFX10-NEXT:    v_xor_b32_e32 v3, s0, v3
1258; GFX10-NEXT:    v_xor_b32_e32 v4, s16, v4
1259; GFX10-NEXT:    v_xor_b32_e32 v5, s17, v5
1260; GFX10-NEXT:    v_xor_b32_e32 v6, s18, v6
1261; GFX10-NEXT:    v_xor_b32_e32 v7, s19, v7
1262; GFX10-NEXT:    v_subrev_nc_u32_e32 v0, s20, v0
1263; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, s21, v1
1264; GFX10-NEXT:    v_subrev_nc_u32_e32 v2, s22, v2
1265; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s0, v3
1266; GFX10-NEXT:    v_mov_b32_e32 v8, 0
1267; GFX10-NEXT:    v_subrev_nc_u32_e32 v4, s16, v4
1268; GFX10-NEXT:    v_subrev_nc_u32_e32 v5, s17, v5
1269; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, s18, v6
1270; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, s19, v7
1271; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
1272; GFX10-NEXT:    global_store_dwordx4 v8, v[0:3], s[4:5]
1273; GFX10-NEXT:    global_store_dwordx4 v8, v[4:7], s[6:7]
1274; GFX10-NEXT:    s_endpgm
1275  %div = sdiv <4 x i32> %x, %y
1276  store <4 x i32> %div, <4 x i32> addrspace(1)* %out0
1277  %rem = srem <4 x i32> %x, %y
1278  store <4 x i32> %rem, <4 x i32> addrspace(1)* %out1
1279  ret void
1280}
1281
1282define amdgpu_kernel void @sdivrem_v2i64(<2 x i64> addrspace(1)* %out0, <2 x i64> addrspace(1)* %out1, <2 x i64> %x, <2 x i64> %y) {
1283; GFX8-LABEL: sdivrem_v2i64:
1284; GFX8:       ; %bb.0:
1285; GFX8-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x10
1286; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
1287; GFX8-NEXT:    s_ashr_i32 s2, s9, 31
1288; GFX8-NEXT:    s_ashr_i32 s16, s13, 31
1289; GFX8-NEXT:    s_add_u32 s0, s8, s2
1290; GFX8-NEXT:    s_addc_u32 s1, s9, s2
1291; GFX8-NEXT:    s_add_u32 s6, s12, s16
1292; GFX8-NEXT:    s_mov_b32 s17, s16
1293; GFX8-NEXT:    s_addc_u32 s7, s13, s16
1294; GFX8-NEXT:    s_xor_b64 s[6:7], s[6:7], s[16:17]
1295; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s7
1296; GFX8-NEXT:    v_cvt_f32_u32_e32 v1, s6
1297; GFX8-NEXT:    s_mov_b32 s3, s2
1298; GFX8-NEXT:    s_xor_b64 s[8:9], s[0:1], s[2:3]
1299; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0
1300; GFX8-NEXT:    v_add_f32_e32 v0, v0, v1
1301; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1302; GFX8-NEXT:    s_sub_u32 s12, 0, s6
1303; GFX8-NEXT:    s_subb_u32 s13, 0, s7
1304; GFX8-NEXT:    s_xor_b64 s[16:17], s[2:3], s[16:17]
1305; GFX8-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1306; GFX8-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
1307; GFX8-NEXT:    v_trunc_f32_e32 v2, v1
1308; GFX8-NEXT:    v_mul_f32_e32 v1, 0xcf800000, v2
1309; GFX8-NEXT:    v_add_f32_e32 v0, v1, v0
1310; GFX8-NEXT:    v_cvt_u32_f32_e32 v3, v0
1311; GFX8-NEXT:    v_cvt_u32_f32_e32 v4, v2
1312; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s12, v3, 0
1313; GFX8-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s12, v4, v[1:2]
1314; GFX8-NEXT:    v_mul_hi_u32 v5, v3, v0
1315; GFX8-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s13, v3, v[1:2]
1316; GFX8-NEXT:    v_mul_lo_u32 v2, v4, v0
1317; GFX8-NEXT:    v_mul_hi_u32 v0, v4, v0
1318; GFX8-NEXT:    v_mul_lo_u32 v6, v3, v1
1319; GFX8-NEXT:    v_mul_lo_u32 v7, v4, v1
1320; GFX8-NEXT:    v_mul_hi_u32 v8, v3, v1
1321; GFX8-NEXT:    v_mul_hi_u32 v1, v4, v1
1322; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v6
1323; GFX8-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
1324; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v7, v0
1325; GFX8-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
1326; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v5
1327; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
1328; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v6, v2
1329; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v8
1330; GFX8-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
1331; GFX8-NEXT:    v_add_u32_e32 v5, vcc, v7, v5
1332; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
1333; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
1334; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v5, v2
1335; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v2
1336; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v3, v0
1337; GFX8-NEXT:    v_addc_u32_e32 v4, vcc, v4, v1, vcc
1338; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s12, v3, 0
1339; GFX8-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s12, v4, v[1:2]
1340; GFX8-NEXT:    v_mul_hi_u32 v6, v3, v0
1341; GFX8-NEXT:    s_ashr_i32 s12, s15, 31
1342; GFX8-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s13, v3, v[1:2]
1343; GFX8-NEXT:    v_mul_lo_u32 v2, v4, v0
1344; GFX8-NEXT:    v_mul_hi_u32 v0, v4, v0
1345; GFX8-NEXT:    v_mul_lo_u32 v5, v3, v1
1346; GFX8-NEXT:    s_mov_b32 s13, s12
1347; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v5
1348; GFX8-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
1349; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v6
1350; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
1351; GFX8-NEXT:    v_mul_lo_u32 v6, v4, v1
1352; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v5, v2
1353; GFX8-NEXT:    v_mul_hi_u32 v5, v3, v1
1354; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v6, v0
1355; GFX8-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
1356; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v5
1357; GFX8-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
1358; GFX8-NEXT:    v_add_u32_e32 v5, vcc, v6, v5
1359; GFX8-NEXT:    v_mul_hi_u32 v1, v4, v1
1360; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
1361; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
1362; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v5, v2
1363; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v2
1364; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v3, v0
1365; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v4, v1, vcc
1366; GFX8-NEXT:    v_mul_lo_u32 v2, s9, v0
1367; GFX8-NEXT:    v_mul_lo_u32 v3, s8, v1
1368; GFX8-NEXT:    v_mul_hi_u32 v4, s8, v0
1369; GFX8-NEXT:    v_mul_hi_u32 v0, s9, v0
1370; GFX8-NEXT:    v_mul_hi_u32 v5, s9, v1
1371; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v3
1372; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
1373; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v4
1374; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
1375; GFX8-NEXT:    v_mul_lo_u32 v4, s9, v1
1376; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v2
1377; GFX8-NEXT:    v_mul_hi_u32 v3, s8, v1
1378; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v4, v0
1379; GFX8-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
1380; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v3
1381; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
1382; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v4, v3
1383; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v0, v2
1384; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s6, v4, 0
1385; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
1386; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v2
1387; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v5, v2
1388; GFX8-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s6, v3, v[1:2]
1389; GFX8-NEXT:    v_mov_b32_e32 v6, s9
1390; GFX8-NEXT:    v_sub_u32_e32 v7, vcc, s8, v0
1391; GFX8-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s7, v4, v[1:2]
1392; GFX8-NEXT:    v_mov_b32_e32 v5, s7
1393; GFX8-NEXT:    s_ashr_i32 s8, s11, 31
1394; GFX8-NEXT:    v_subb_u32_e64 v6, s[0:1], v6, v1, vcc
1395; GFX8-NEXT:    v_sub_u32_e64 v0, s[0:1], s9, v1
1396; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s7, v6
1397; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, -1, s[0:1]
1398; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s6, v7
1399; GFX8-NEXT:    v_subb_u32_e32 v0, vcc, v0, v5, vcc
1400; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, -1, s[0:1]
1401; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], s7, v6
1402; GFX8-NEXT:    v_subrev_u32_e32 v8, vcc, s6, v7
1403; GFX8-NEXT:    v_cndmask_b32_e64 v2, v1, v2, s[0:1]
1404; GFX8-NEXT:    v_subbrev_u32_e64 v9, s[0:1], 0, v0, vcc
1405; GFX8-NEXT:    v_add_u32_e64 v1, s[0:1], 1, v4
1406; GFX8-NEXT:    v_addc_u32_e64 v10, s[0:1], 0, v3, s[0:1]
1407; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s7, v9
1408; GFX8-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[0:1]
1409; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s6, v8
1410; GFX8-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[0:1]
1411; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], s7, v9
1412; GFX8-NEXT:    v_cndmask_b32_e64 v11, v11, v12, s[0:1]
1413; GFX8-NEXT:    v_add_u32_e64 v12, s[0:1], 1, v1
1414; GFX8-NEXT:    v_addc_u32_e64 v13, s[0:1], 0, v10, s[0:1]
1415; GFX8-NEXT:    s_add_u32 s0, s10, s8
1416; GFX8-NEXT:    s_addc_u32 s1, s11, s8
1417; GFX8-NEXT:    s_add_u32 s10, s14, s12
1418; GFX8-NEXT:    s_addc_u32 s11, s15, s12
1419; GFX8-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
1420; GFX8-NEXT:    v_cvt_f32_u32_e32 v14, s11
1421; GFX8-NEXT:    v_subb_u32_e32 v0, vcc, v0, v5, vcc
1422; GFX8-NEXT:    v_cvt_f32_u32_e32 v5, s10
1423; GFX8-NEXT:    v_subrev_u32_e32 v15, vcc, s6, v8
1424; GFX8-NEXT:    v_subbrev_u32_e32 v16, vcc, 0, v0, vcc
1425; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v14
1426; GFX8-NEXT:    v_add_f32_e32 v0, v0, v5
1427; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1428; GFX8-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
1429; GFX8-NEXT:    v_cndmask_b32_e32 v5, v1, v12, vcc
1430; GFX8-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc
1431; GFX8-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1432; GFX8-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
1433; GFX8-NEXT:    v_trunc_f32_e32 v12, v1
1434; GFX8-NEXT:    v_mul_f32_e32 v1, 0xcf800000, v12
1435; GFX8-NEXT:    v_add_f32_e32 v0, v1, v0
1436; GFX8-NEXT:    v_cvt_u32_f32_e32 v13, v0
1437; GFX8-NEXT:    s_mov_b32 s9, s8
1438; GFX8-NEXT:    s_xor_b64 s[6:7], s[0:1], s[8:9]
1439; GFX8-NEXT:    s_sub_u32 s3, 0, s10
1440; GFX8-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
1441; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s3, v13, 0
1442; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
1443; GFX8-NEXT:    v_cvt_u32_f32_e32 v5, v12
1444; GFX8-NEXT:    s_subb_u32 s18, 0, s11
1445; GFX8-NEXT:    v_cndmask_b32_e32 v10, v3, v10, vcc
1446; GFX8-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s3, v5, v[1:2]
1447; GFX8-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v11
1448; GFX8-NEXT:    v_cndmask_b32_e64 v3, v8, v15, s[0:1]
1449; GFX8-NEXT:    v_mad_u64_u32 v[1:2], s[14:15], s18, v13, v[1:2]
1450; GFX8-NEXT:    v_cndmask_b32_e64 v2, v9, v16, s[0:1]
1451; GFX8-NEXT:    v_cndmask_b32_e32 v7, v7, v3, vcc
1452; GFX8-NEXT:    v_mul_lo_u32 v3, v5, v0
1453; GFX8-NEXT:    v_mul_lo_u32 v8, v13, v1
1454; GFX8-NEXT:    v_cndmask_b32_e32 v6, v6, v2, vcc
1455; GFX8-NEXT:    v_mul_hi_u32 v2, v13, v0
1456; GFX8-NEXT:    v_mul_hi_u32 v0, v5, v0
1457; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v3, v8
1458; GFX8-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
1459; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v2
1460; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
1461; GFX8-NEXT:    v_mul_lo_u32 v3, v5, v1
1462; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v8, v2
1463; GFX8-NEXT:    v_mul_hi_u32 v8, v13, v1
1464; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v3, v0
1465; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
1466; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v8
1467; GFX8-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
1468; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v3, v8
1469; GFX8-NEXT:    v_mul_hi_u32 v1, v5, v1
1470; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
1471; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
1472; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v2
1473; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v2
1474; GFX8-NEXT:    v_add_u32_e32 v8, vcc, v13, v0
1475; GFX8-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s3, v8, 0
1476; GFX8-NEXT:    v_addc_u32_e32 v5, vcc, v5, v1, vcc
1477; GFX8-NEXT:    v_xor_b32_e32 v1, s16, v4
1478; GFX8-NEXT:    v_mov_b32_e32 v0, v3
1479; GFX8-NEXT:    v_mad_u64_u32 v[3:4], s[0:1], s3, v5, v[0:1]
1480; GFX8-NEXT:    v_xor_b32_e32 v9, s17, v10
1481; GFX8-NEXT:    v_mov_b32_e32 v10, s17
1482; GFX8-NEXT:    v_mad_u64_u32 v[3:4], s[0:1], s18, v8, v[3:4]
1483; GFX8-NEXT:    v_subrev_u32_e32 v0, vcc, s16, v1
1484; GFX8-NEXT:    v_subb_u32_e32 v1, vcc, v9, v10, vcc
1485; GFX8-NEXT:    v_xor_b32_e32 v4, s2, v7
1486; GFX8-NEXT:    v_mul_lo_u32 v7, v5, v2
1487; GFX8-NEXT:    v_mul_lo_u32 v9, v8, v3
1488; GFX8-NEXT:    v_mul_hi_u32 v11, v8, v2
1489; GFX8-NEXT:    v_mul_hi_u32 v2, v5, v2
1490; GFX8-NEXT:    v_xor_b32_e32 v6, s2, v6
1491; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v7, v9
1492; GFX8-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
1493; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v7, v11
1494; GFX8-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
1495; GFX8-NEXT:    v_mul_lo_u32 v11, v5, v3
1496; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v9, v7
1497; GFX8-NEXT:    v_mul_hi_u32 v9, v8, v3
1498; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v11, v2
1499; GFX8-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
1500; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v9
1501; GFX8-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
1502; GFX8-NEXT:    v_add_u32_e32 v9, vcc, v11, v9
1503; GFX8-NEXT:    v_mul_hi_u32 v3, v5, v3
1504; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v7
1505; GFX8-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
1506; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v9, v7
1507; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v3, v7
1508; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v8, v2
1509; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
1510; GFX8-NEXT:    v_mov_b32_e32 v10, s2
1511; GFX8-NEXT:    v_mul_lo_u32 v7, s7, v2
1512; GFX8-NEXT:    v_mul_lo_u32 v8, s6, v3
1513; GFX8-NEXT:    v_subrev_u32_e32 v4, vcc, s2, v4
1514; GFX8-NEXT:    v_subb_u32_e32 v5, vcc, v6, v10, vcc
1515; GFX8-NEXT:    v_mul_hi_u32 v6, s6, v2
1516; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v7, v8
1517; GFX8-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
1518; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v7, v6
1519; GFX8-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
1520; GFX8-NEXT:    v_mul_lo_u32 v7, s7, v3
1521; GFX8-NEXT:    v_mul_hi_u32 v2, s7, v2
1522; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v8, v6
1523; GFX8-NEXT:    v_mul_hi_u32 v8, s6, v3
1524; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v7, v2
1525; GFX8-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
1526; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v8
1527; GFX8-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
1528; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v7, v8
1529; GFX8-NEXT:    v_add_u32_e32 v8, vcc, v2, v6
1530; GFX8-NEXT:    v_mul_hi_u32 v9, s7, v3
1531; GFX8-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s10, v8, 0
1532; GFX8-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
1533; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v7, v6
1534; GFX8-NEXT:    v_add_u32_e32 v9, vcc, v9, v6
1535; GFX8-NEXT:    v_mad_u64_u32 v[6:7], s[0:1], s10, v9, v[3:4]
1536; GFX8-NEXT:    v_mov_b32_e32 v10, s7
1537; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, s6, v2
1538; GFX8-NEXT:    v_mad_u64_u32 v[6:7], s[0:1], s11, v8, v[6:7]
1539; GFX8-NEXT:    v_mov_b32_e32 v3, s11
1540; GFX8-NEXT:    v_subb_u32_e64 v7, s[0:1], v10, v6, vcc
1541; GFX8-NEXT:    v_sub_u32_e64 v6, s[0:1], s7, v6
1542; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v7
1543; GFX8-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[0:1]
1544; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v2
1545; GFX8-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[0:1]
1546; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v7
1547; GFX8-NEXT:    v_subb_u32_e32 v6, vcc, v6, v3, vcc
1548; GFX8-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[0:1]
1549; GFX8-NEXT:    v_subrev_u32_e32 v11, vcc, s10, v2
1550; GFX8-NEXT:    v_subbrev_u32_e64 v12, s[0:1], 0, v6, vcc
1551; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v12
1552; GFX8-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[0:1]
1553; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v11
1554; GFX8-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[0:1]
1555; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v12
1556; GFX8-NEXT:    v_cndmask_b32_e64 v13, v13, v14, s[0:1]
1557; GFX8-NEXT:    v_add_u32_e64 v14, s[0:1], 1, v8
1558; GFX8-NEXT:    v_subb_u32_e32 v3, vcc, v6, v3, vcc
1559; GFX8-NEXT:    v_addc_u32_e64 v15, s[0:1], 0, v9, s[0:1]
1560; GFX8-NEXT:    v_add_u32_e32 v6, vcc, 1, v14
1561; GFX8-NEXT:    v_addc_u32_e32 v16, vcc, 0, v15, vcc
1562; GFX8-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v13
1563; GFX8-NEXT:    v_subrev_u32_e64 v13, s[0:1], s10, v11
1564; GFX8-NEXT:    v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]
1565; GFX8-NEXT:    v_cndmask_b32_e32 v6, v14, v6, vcc
1566; GFX8-NEXT:    v_cndmask_b32_e32 v14, v15, v16, vcc
1567; GFX8-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v10
1568; GFX8-NEXT:    v_cndmask_b32_e64 v6, v8, v6, s[0:1]
1569; GFX8-NEXT:    v_cndmask_b32_e64 v8, v9, v14, s[0:1]
1570; GFX8-NEXT:    v_cndmask_b32_e32 v9, v11, v13, vcc
1571; GFX8-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc
1572; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
1573; GFX8-NEXT:    v_cndmask_b32_e64 v9, v2, v9, s[0:1]
1574; GFX8-NEXT:    v_cndmask_b32_e64 v7, v7, v3, s[0:1]
1575; GFX8-NEXT:    s_xor_b64 s[0:1], s[8:9], s[12:13]
1576; GFX8-NEXT:    v_xor_b32_e32 v2, s0, v6
1577; GFX8-NEXT:    v_xor_b32_e32 v3, s1, v8
1578; GFX8-NEXT:    v_mov_b32_e32 v6, s1
1579; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s0, v2
1580; GFX8-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
1581; GFX8-NEXT:    v_xor_b32_e32 v6, s8, v9
1582; GFX8-NEXT:    v_xor_b32_e32 v7, s8, v7
1583; GFX8-NEXT:    v_mov_b32_e32 v8, s8
1584; GFX8-NEXT:    v_subrev_u32_e32 v6, vcc, s8, v6
1585; GFX8-NEXT:    v_subb_u32_e32 v7, vcc, v7, v8, vcc
1586; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
1587; GFX8-NEXT:    v_mov_b32_e32 v9, s5
1588; GFX8-NEXT:    v_mov_b32_e32 v8, s4
1589; GFX8-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]
1590; GFX8-NEXT:    s_nop 0
1591; GFX8-NEXT:    v_mov_b32_e32 v0, s6
1592; GFX8-NEXT:    v_mov_b32_e32 v1, s7
1593; GFX8-NEXT:    flat_store_dwordx4 v[0:1], v[4:7]
1594; GFX8-NEXT:    s_endpgm
1595;
1596; GFX9-LABEL: sdivrem_v2i64:
1597; GFX9:       ; %bb.0:
1598; GFX9-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x10
1599; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1600; GFX9-NEXT:    s_ashr_i32 s2, s9, 31
1601; GFX9-NEXT:    s_ashr_i32 s16, s13, 31
1602; GFX9-NEXT:    s_add_u32 s0, s8, s2
1603; GFX9-NEXT:    s_addc_u32 s1, s9, s2
1604; GFX9-NEXT:    s_add_u32 s6, s12, s16
1605; GFX9-NEXT:    s_mov_b32 s17, s16
1606; GFX9-NEXT:    s_addc_u32 s7, s13, s16
1607; GFX9-NEXT:    s_xor_b64 s[6:7], s[6:7], s[16:17]
1608; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s7
1609; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s6
1610; GFX9-NEXT:    s_mov_b32 s3, s2
1611; GFX9-NEXT:    s_xor_b64 s[8:9], s[0:1], s[2:3]
1612; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0
1613; GFX9-NEXT:    v_add_f32_e32 v0, v0, v1
1614; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1615; GFX9-NEXT:    s_sub_u32 s12, 0, s6
1616; GFX9-NEXT:    s_subb_u32 s13, 0, s7
1617; GFX9-NEXT:    s_xor_b64 s[16:17], s[2:3], s[16:17]
1618; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1619; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
1620; GFX9-NEXT:    v_trunc_f32_e32 v2, v1
1621; GFX9-NEXT:    v_mul_f32_e32 v1, 0xcf800000, v2
1622; GFX9-NEXT:    v_add_f32_e32 v0, v1, v0
1623; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v0
1624; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v2
1625; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s12, v3, 0
1626; GFX9-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s12, v4, v[1:2]
1627; GFX9-NEXT:    v_mul_hi_u32 v5, v3, v0
1628; GFX9-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s13, v3, v[1:2]
1629; GFX9-NEXT:    v_mul_lo_u32 v2, v4, v0
1630; GFX9-NEXT:    v_mul_hi_u32 v0, v4, v0
1631; GFX9-NEXT:    v_mul_lo_u32 v6, v3, v1
1632; GFX9-NEXT:    v_mul_lo_u32 v7, v4, v1
1633; GFX9-NEXT:    v_mul_hi_u32 v8, v3, v1
1634; GFX9-NEXT:    v_mul_hi_u32 v1, v4, v1
1635; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v6
1636; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
1637; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v7, v0
1638; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
1639; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v5
1640; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
1641; GFX9-NEXT:    v_add_u32_e32 v2, v6, v2
1642; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v8
1643; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
1644; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
1645; GFX9-NEXT:    v_add_u32_e32 v5, v7, v5
1646; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
1647; GFX9-NEXT:    v_add3_u32 v1, v5, v2, v1
1648; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v0
1649; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v1, vcc
1650; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s12, v3, 0
1651; GFX9-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s12, v4, v[1:2]
1652; GFX9-NEXT:    v_mul_hi_u32 v6, v3, v0
1653; GFX9-NEXT:    s_ashr_i32 s12, s15, 31
1654; GFX9-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s13, v3, v[1:2]
1655; GFX9-NEXT:    v_mul_lo_u32 v2, v4, v0
1656; GFX9-NEXT:    v_mul_hi_u32 v0, v4, v0
1657; GFX9-NEXT:    v_mul_lo_u32 v5, v3, v1
1658; GFX9-NEXT:    s_mov_b32 s13, s12
1659; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v5
1660; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
1661; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v6
1662; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
1663; GFX9-NEXT:    v_mul_lo_u32 v6, v4, v1
1664; GFX9-NEXT:    v_add_u32_e32 v2, v5, v2
1665; GFX9-NEXT:    v_mul_hi_u32 v5, v3, v1
1666; GFX9-NEXT:    v_mul_hi_u32 v1, v4, v1
1667; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v6, v0
1668; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
1669; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v5
1670; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
1671; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
1672; GFX9-NEXT:    v_add_u32_e32 v5, v6, v5
1673; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
1674; GFX9-NEXT:    v_add3_u32 v1, v5, v2, v1
1675; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v3, v0
1676; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v4, v1, vcc
1677; GFX9-NEXT:    v_mul_lo_u32 v2, s9, v0
1678; GFX9-NEXT:    v_mul_lo_u32 v3, s8, v1
1679; GFX9-NEXT:    v_mul_hi_u32 v4, s8, v0
1680; GFX9-NEXT:    v_mul_hi_u32 v0, s9, v0
1681; GFX9-NEXT:    v_mul_hi_u32 v6, s9, v1
1682; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
1683; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
1684; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
1685; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
1686; GFX9-NEXT:    v_mul_lo_u32 v4, s9, v1
1687; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
1688; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v1
1689; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v4, v0
1690; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
1691; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
1692; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
1693; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v0, v2
1694; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s6, v5, 0
1695; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
1696; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
1697; GFX9-NEXT:    v_add3_u32 v3, v3, v2, v6
1698; GFX9-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s6, v3, v[1:2]
1699; GFX9-NEXT:    v_mov_b32_e32 v6, s9
1700; GFX9-NEXT:    v_sub_co_u32_e32 v7, vcc, s8, v0
1701; GFX9-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s7, v5, v[1:2]
1702; GFX9-NEXT:    v_mov_b32_e32 v4, s7
1703; GFX9-NEXT:    s_ashr_i32 s8, s11, 31
1704; GFX9-NEXT:    v_subb_co_u32_e64 v6, s[0:1], v6, v1, vcc
1705; GFX9-NEXT:    v_sub_u32_e32 v0, s9, v1
1706; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s7, v6
1707; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, -1, s[0:1]
1708; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s6, v7
1709; GFX9-NEXT:    v_subb_co_u32_e32 v0, vcc, v0, v4, vcc
1710; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, -1, s[0:1]
1711; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s7, v6
1712; GFX9-NEXT:    v_subrev_co_u32_e32 v8, vcc, s6, v7
1713; GFX9-NEXT:    v_cndmask_b32_e64 v2, v1, v2, s[0:1]
1714; GFX9-NEXT:    v_subbrev_co_u32_e64 v9, s[0:1], 0, v0, vcc
1715; GFX9-NEXT:    v_add_co_u32_e64 v1, s[0:1], 1, v5
1716; GFX9-NEXT:    v_addc_co_u32_e64 v10, s[0:1], 0, v3, s[0:1]
1717; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s7, v9
1718; GFX9-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[0:1]
1719; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s6, v8
1720; GFX9-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[0:1]
1721; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s7, v9
1722; GFX9-NEXT:    v_cndmask_b32_e64 v11, v11, v12, s[0:1]
1723; GFX9-NEXT:    v_add_co_u32_e64 v12, s[0:1], 1, v1
1724; GFX9-NEXT:    v_addc_co_u32_e64 v13, s[0:1], 0, v10, s[0:1]
1725; GFX9-NEXT:    s_add_u32 s0, s10, s8
1726; GFX9-NEXT:    s_addc_u32 s1, s11, s8
1727; GFX9-NEXT:    s_add_u32 s10, s14, s12
1728; GFX9-NEXT:    s_addc_u32 s11, s15, s12
1729; GFX9-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
1730; GFX9-NEXT:    v_cvt_f32_u32_e32 v14, s11
1731; GFX9-NEXT:    v_subb_co_u32_e32 v0, vcc, v0, v4, vcc
1732; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s10
1733; GFX9-NEXT:    v_subrev_co_u32_e32 v15, vcc, s6, v8
1734; GFX9-NEXT:    v_subbrev_co_u32_e32 v16, vcc, 0, v0, vcc
1735; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v14
1736; GFX9-NEXT:    v_add_f32_e32 v0, v0, v4
1737; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1738; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
1739; GFX9-NEXT:    v_cndmask_b32_e32 v4, v1, v12, vcc
1740; GFX9-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc
1741; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1742; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
1743; GFX9-NEXT:    v_trunc_f32_e32 v12, v1
1744; GFX9-NEXT:    v_mul_f32_e32 v1, 0xcf800000, v12
1745; GFX9-NEXT:    v_add_f32_e32 v0, v1, v0
1746; GFX9-NEXT:    v_cvt_u32_f32_e32 v13, v0
1747; GFX9-NEXT:    s_mov_b32 s9, s8
1748; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[8:9]
1749; GFX9-NEXT:    s_sub_u32 s3, 0, s10
1750; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s3, v13, 0
1751; GFX9-NEXT:    v_cvt_u32_f32_e32 v12, v12
1752; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
1753; GFX9-NEXT:    s_subb_u32 s14, 0, s11
1754; GFX9-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc
1755; GFX9-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s3, v12, v[1:2]
1756; GFX9-NEXT:    v_cndmask_b32_e32 v5, v3, v10, vcc
1757; GFX9-NEXT:    v_mul_hi_u32 v10, v13, v0
1758; GFX9-NEXT:    v_mad_u64_u32 v[1:2], s[0:1], s14, v13, v[1:2]
1759; GFX9-NEXT:    v_mul_lo_u32 v2, v12, v0
1760; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v11
1761; GFX9-NEXT:    v_mul_lo_u32 v3, v13, v1
1762; GFX9-NEXT:    v_cndmask_b32_e64 v8, v8, v15, s[0:1]
1763; GFX9-NEXT:    v_cndmask_b32_e64 v9, v9, v16, s[0:1]
1764; GFX9-NEXT:    v_mul_hi_u32 v0, v12, v0
1765; GFX9-NEXT:    v_add_co_u32_e64 v2, s[0:1], v2, v3
1766; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s[0:1]
1767; GFX9-NEXT:    v_add_co_u32_e64 v2, s[0:1], v2, v10
1768; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s[0:1]
1769; GFX9-NEXT:    v_mul_lo_u32 v10, v12, v1
1770; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
1771; GFX9-NEXT:    v_mul_hi_u32 v3, v13, v1
1772; GFX9-NEXT:    v_mul_hi_u32 v1, v12, v1
1773; GFX9-NEXT:    v_add_co_u32_e64 v0, s[0:1], v10, v0
1774; GFX9-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[0:1]
1775; GFX9-NEXT:    v_add_co_u32_e64 v0, s[0:1], v0, v3
1776; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s[0:1]
1777; GFX9-NEXT:    v_add_co_u32_e64 v0, s[0:1], v0, v2
1778; GFX9-NEXT:    v_add_u32_e32 v3, v10, v3
1779; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s[0:1]
1780; GFX9-NEXT:    v_add3_u32 v1, v3, v2, v1
1781; GFX9-NEXT:    v_add_co_u32_e64 v10, s[0:1], v13, v0
1782; GFX9-NEXT:    v_addc_co_u32_e64 v11, s[0:1], v12, v1, s[0:1]
1783; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s3, v10, 0
1784; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
1785; GFX9-NEXT:    v_xor_b32_e32 v8, s16, v4
1786; GFX9-NEXT:    v_mov_b32_e32 v0, v3
1787; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s3, v11, v[0:1]
1788; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v9, vcc
1789; GFX9-NEXT:    v_xor_b32_e32 v5, s17, v5
1790; GFX9-NEXT:    v_mad_u64_u32 v[3:4], s[0:1], s14, v10, v[0:1]
1791; GFX9-NEXT:    v_mov_b32_e32 v9, s17
1792; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s16, v8
1793; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v5, v9, vcc
1794; GFX9-NEXT:    v_xor_b32_e32 v4, s2, v7
1795; GFX9-NEXT:    v_mul_lo_u32 v5, v11, v2
1796; GFX9-NEXT:    v_mul_lo_u32 v7, v10, v3
1797; GFX9-NEXT:    v_mul_hi_u32 v8, v10, v2
1798; GFX9-NEXT:    v_mul_hi_u32 v2, v11, v2
1799; GFX9-NEXT:    v_xor_b32_e32 v6, s2, v6
1800; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v7
1801; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
1802; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v8
1803; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
1804; GFX9-NEXT:    v_mul_lo_u32 v8, v11, v3
1805; GFX9-NEXT:    v_add_u32_e32 v5, v7, v5
1806; GFX9-NEXT:    v_mul_hi_u32 v7, v10, v3
1807; GFX9-NEXT:    v_mul_hi_u32 v3, v11, v3
1808; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v8, v2
1809; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
1810; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v7
1811; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
1812; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v5
1813; GFX9-NEXT:    v_add_u32_e32 v7, v8, v7
1814; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
1815; GFX9-NEXT:    v_add3_u32 v3, v7, v5, v3
1816; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v10, v2
1817; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v11, v3, vcc
1818; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v2
1819; GFX9-NEXT:    v_mul_lo_u32 v7, s6, v3
1820; GFX9-NEXT:    v_mul_hi_u32 v9, s6, v2
1821; GFX9-NEXT:    v_mul_hi_u32 v2, s7, v2
1822; GFX9-NEXT:    v_mul_hi_u32 v12, s7, v3
1823; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v7
1824; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
1825; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v9
1826; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
1827; GFX9-NEXT:    v_mul_lo_u32 v9, s7, v3
1828; GFX9-NEXT:    v_add_u32_e32 v5, v7, v5
1829; GFX9-NEXT:    v_mul_hi_u32 v7, s6, v3
1830; GFX9-NEXT:    v_mov_b32_e32 v8, s2
1831; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v9, v2
1832; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
1833; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v7
1834; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
1835; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v2, v5
1836; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s10, v10, 0
1837; GFX9-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
1838; GFX9-NEXT:    v_subrev_co_u32_e32 v4, vcc, s2, v4
1839; GFX9-NEXT:    v_subb_co_u32_e32 v5, vcc, v6, v8, vcc
1840; GFX9-NEXT:    v_add_u32_e32 v6, v9, v7
1841; GFX9-NEXT:    v_add3_u32 v8, v6, v11, v12
1842; GFX9-NEXT:    v_mad_u64_u32 v[6:7], s[0:1], s10, v8, v[3:4]
1843; GFX9-NEXT:    v_mov_b32_e32 v9, s7
1844; GFX9-NEXT:    v_sub_co_u32_e32 v2, vcc, s6, v2
1845; GFX9-NEXT:    v_mad_u64_u32 v[6:7], s[0:1], s11, v10, v[6:7]
1846; GFX9-NEXT:    v_mov_b32_e32 v3, s11
1847; GFX9-NEXT:    v_subb_co_u32_e64 v7, s[0:1], v9, v6, vcc
1848; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v7
1849; GFX9-NEXT:    v_sub_u32_e32 v6, s7, v6
1850; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[0:1]
1851; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v2
1852; GFX9-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[0:1]
1853; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v7
1854; GFX9-NEXT:    v_subb_co_u32_e32 v6, vcc, v6, v3, vcc
1855; GFX9-NEXT:    v_cndmask_b32_e64 v9, v9, v11, s[0:1]
1856; GFX9-NEXT:    v_subrev_co_u32_e32 v11, vcc, s10, v2
1857; GFX9-NEXT:    v_subbrev_co_u32_e64 v12, s[0:1], 0, v6, vcc
1858; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v12
1859; GFX9-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[0:1]
1860; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v11
1861; GFX9-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[0:1]
1862; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v12
1863; GFX9-NEXT:    v_cndmask_b32_e64 v13, v13, v14, s[0:1]
1864; GFX9-NEXT:    v_add_co_u32_e64 v14, s[0:1], 1, v10
1865; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v6, v3, vcc
1866; GFX9-NEXT:    v_addc_co_u32_e64 v15, s[0:1], 0, v8, s[0:1]
1867; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, 1, v14
1868; GFX9-NEXT:    v_addc_co_u32_e32 v16, vcc, 0, v15, vcc
1869; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v13
1870; GFX9-NEXT:    v_cndmask_b32_e32 v6, v14, v6, vcc
1871; GFX9-NEXT:    v_cndmask_b32_e32 v14, v15, v16, vcc
1872; GFX9-NEXT:    v_subrev_co_u32_e64 v15, s[0:1], s10, v11
1873; GFX9-NEXT:    v_subbrev_co_u32_e64 v3, s[0:1], 0, v3, s[0:1]
1874; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v9
1875; GFX9-NEXT:    v_cndmask_b32_e32 v9, v11, v15, vcc
1876; GFX9-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc
1877; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
1878; GFX9-NEXT:    v_cndmask_b32_e64 v6, v10, v6, s[0:1]
1879; GFX9-NEXT:    v_cndmask_b32_e64 v8, v8, v14, s[0:1]
1880; GFX9-NEXT:    v_cndmask_b32_e64 v9, v2, v9, s[0:1]
1881; GFX9-NEXT:    v_cndmask_b32_e64 v7, v7, v3, s[0:1]
1882; GFX9-NEXT:    s_xor_b64 s[0:1], s[8:9], s[12:13]
1883; GFX9-NEXT:    v_xor_b32_e32 v2, s0, v6
1884; GFX9-NEXT:    v_xor_b32_e32 v3, s1, v8
1885; GFX9-NEXT:    v_mov_b32_e32 v6, s1
1886; GFX9-NEXT:    v_subrev_co_u32_e32 v2, vcc, s0, v2
1887; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v3, v6, vcc
1888; GFX9-NEXT:    v_xor_b32_e32 v6, s8, v9
1889; GFX9-NEXT:    v_mov_b32_e32 v13, 0
1890; GFX9-NEXT:    v_xor_b32_e32 v7, s8, v7
1891; GFX9-NEXT:    v_mov_b32_e32 v8, s8
1892; GFX9-NEXT:    v_subrev_co_u32_e32 v6, vcc, s8, v6
1893; GFX9-NEXT:    v_subb_co_u32_e32 v7, vcc, v7, v8, vcc
1894; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1895; GFX9-NEXT:    global_store_dwordx4 v13, v[0:3], s[4:5]
1896; GFX9-NEXT:    global_store_dwordx4 v13, v[4:7], s[6:7]
1897; GFX9-NEXT:    s_endpgm
1898;
1899; GFX10-LABEL: sdivrem_v2i64:
1900; GFX10:       ; %bb.0:
1901; GFX10-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x10
1902; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
1903; GFX10-NEXT:    s_ashr_i32 s2, s9, 31
1904; GFX10-NEXT:    s_ashr_i32 s6, s13, 31
1905; GFX10-NEXT:    s_add_u32 s0, s8, s2
1906; GFX10-NEXT:    s_addc_u32 s1, s9, s2
1907; GFX10-NEXT:    s_add_u32 s8, s12, s6
1908; GFX10-NEXT:    s_mov_b32 s7, s6
1909; GFX10-NEXT:    s_addc_u32 s9, s13, s6
1910; GFX10-NEXT:    s_mov_b32 s3, s2
1911; GFX10-NEXT:    s_xor_b64 s[8:9], s[8:9], s[6:7]
1912; GFX10-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
1913; GFX10-NEXT:    v_cvt_f32_u32_e32 v1, s9
1914; GFX10-NEXT:    s_sub_u32 s20, 0, s8
1915; GFX10-NEXT:    s_subb_u32 s21, 0, s9
1916; GFX10-NEXT:    s_ashr_i32 s12, s11, 31
1917; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s8
1918; GFX10-NEXT:    s_xor_b64 s[18:19], s[2:3], s[6:7]
1919; GFX10-NEXT:    s_ashr_i32 s16, s15, 31
1920; GFX10-NEXT:    v_mul_f32_e32 v1, 0x4f800000, v1
1921; GFX10-NEXT:    s_add_u32 s6, s10, s12
1922; GFX10-NEXT:    s_addc_u32 s7, s11, s12
1923; GFX10-NEXT:    s_add_u32 s10, s14, s16
1924; GFX10-NEXT:    s_mov_b32 s17, s16
1925; GFX10-NEXT:    s_addc_u32 s11, s15, s16
1926; GFX10-NEXT:    v_add_f32_e32 v0, v1, v0
1927; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[16:17]
1928; GFX10-NEXT:    s_mov_b32 s13, s12
1929; GFX10-NEXT:    v_cvt_f32_u32_e32 v1, s11
1930; GFX10-NEXT:    v_cvt_f32_u32_e32 v2, s10
1931; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1932; GFX10-NEXT:    s_xor_b64 s[14:15], s[6:7], s[12:13]
1933; GFX10-NEXT:    v_mul_f32_e32 v1, 0x4f800000, v1
1934; GFX10-NEXT:    v_add_f32_e32 v1, v1, v2
1935; GFX10-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1936; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1937; GFX10-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
1938; GFX10-NEXT:    v_trunc_f32_e32 v2, v2
1939; GFX10-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v1
1940; GFX10-NEXT:    v_mul_f32_e32 v1, 0xcf800000, v2
1941; GFX10-NEXT:    v_cvt_u32_f32_e32 v5, v2
1942; GFX10-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
1943; GFX10-NEXT:    v_add_f32_e32 v0, v1, v0
1944; GFX10-NEXT:    v_mul_lo_u32 v7, s20, v5
1945; GFX10-NEXT:    v_trunc_f32_e32 v4, v4
1946; GFX10-NEXT:    v_cvt_u32_f32_e32 v6, v0
1947; GFX10-NEXT:    v_mul_f32_e32 v2, 0xcf800000, v4
1948; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s3, s20, v6, 0
1949; GFX10-NEXT:    v_mul_lo_u32 v8, s21, v6
1950; GFX10-NEXT:    v_add_f32_e32 v2, v2, v3
1951; GFX10-NEXT:    v_cvt_u32_f32_e32 v3, v4
1952; GFX10-NEXT:    s_sub_u32 s3, 0, s10
1953; GFX10-NEXT:    s_subb_u32 s6, 0, s11
1954; GFX10-NEXT:    v_cvt_u32_f32_e32 v4, v2
1955; GFX10-NEXT:    v_mul_lo_u32 v9, s3, v3
1956; GFX10-NEXT:    v_add3_u32 v7, v1, v7, v8
1957; GFX10-NEXT:    v_mul_lo_u32 v10, v5, v0
1958; GFX10-NEXT:    v_mul_hi_u32 v11, v6, v0
1959; GFX10-NEXT:    v_mad_u64_u32 v[1:2], s7, s3, v4, 0
1960; GFX10-NEXT:    v_mul_lo_u32 v8, s6, v4
1961; GFX10-NEXT:    v_mul_lo_u32 v12, v6, v7
1962; GFX10-NEXT:    v_mul_hi_u32 v0, v5, v0
1963; GFX10-NEXT:    v_mul_lo_u32 v13, v5, v7
1964; GFX10-NEXT:    v_mul_hi_u32 v14, v6, v7
1965; GFX10-NEXT:    v_mul_hi_u32 v7, v5, v7
1966; GFX10-NEXT:    v_add3_u32 v2, v2, v9, v8
1967; GFX10-NEXT:    v_add_co_u32 v10, s7, v10, v12
1968; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s7
1969; GFX10-NEXT:    v_add_co_u32 v0, s7, v13, v0
1970; GFX10-NEXT:    v_mul_lo_u32 v8, v3, v1
1971; GFX10-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s7
1972; GFX10-NEXT:    v_mul_lo_u32 v15, v4, v2
1973; GFX10-NEXT:    v_add_co_u32 v10, s7, v10, v11
1974; GFX10-NEXT:    v_mul_hi_u32 v9, v4, v1
1975; GFX10-NEXT:    v_mul_hi_u32 v1, v3, v1
1976; GFX10-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s7
1977; GFX10-NEXT:    v_add_co_u32 v0, s7, v0, v14
1978; GFX10-NEXT:    v_mul_lo_u32 v14, v3, v2
1979; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s7
1980; GFX10-NEXT:    v_add_nc_u32_e32 v10, v12, v10
1981; GFX10-NEXT:    v_add_co_u32 v8, s7, v8, v15
1982; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s7
1983; GFX10-NEXT:    v_mul_hi_u32 v16, v4, v2
1984; GFX10-NEXT:    v_add_nc_u32_e32 v11, v13, v11
1985; GFX10-NEXT:    v_add_co_u32 v1, s7, v14, v1
1986; GFX10-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s7
1987; GFX10-NEXT:    v_add_co_u32 v0, s7, v0, v10
1988; GFX10-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s7
1989; GFX10-NEXT:    v_add_co_u32 v8, s7, v8, v9
1990; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s7
1991; GFX10-NEXT:    v_add_co_u32 v9, s7, v1, v16
1992; GFX10-NEXT:    v_add3_u32 v7, v11, v10, v7
1993; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s7
1994; GFX10-NEXT:    v_add_co_u32 v6, vcc_lo, v6, v0
1995; GFX10-NEXT:    v_add_nc_u32_e32 v8, v12, v8
1996; GFX10-NEXT:    v_add_co_ci_u32_e32 v5, vcc_lo, v5, v7, vcc_lo
1997; GFX10-NEXT:    v_mul_hi_u32 v2, v3, v2
1998; GFX10-NEXT:    v_add_nc_u32_e32 v10, v13, v1
1999; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s7, s20, v6, 0
2000; GFX10-NEXT:    v_add_co_u32 v7, s7, v9, v8
2001; GFX10-NEXT:    v_mul_lo_u32 v9, s21, v6
2002; GFX10-NEXT:    v_mul_lo_u32 v11, s20, v5
2003; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s7
2004; GFX10-NEXT:    v_add_co_u32 v4, vcc_lo, v4, v7
2005; GFX10-NEXT:    v_add3_u32 v2, v10, v8, v2
2006; GFX10-NEXT:    v_mul_lo_u32 v8, v5, v0
2007; GFX10-NEXT:    v_add3_u32 v7, v1, v11, v9
2008; GFX10-NEXT:    v_mul_hi_u32 v10, v6, v0
2009; GFX10-NEXT:    v_mul_hi_u32 v0, v5, v0
2010; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, v3, v2, vcc_lo
2011; GFX10-NEXT:    v_mul_lo_u32 v12, v6, v7
2012; GFX10-NEXT:    v_mad_u64_u32 v[1:2], s7, s3, v4, 0
2013; GFX10-NEXT:    v_mul_lo_u32 v9, s6, v4
2014; GFX10-NEXT:    v_mul_lo_u32 v11, s3, v3
2015; GFX10-NEXT:    v_mul_lo_u32 v13, v5, v7
2016; GFX10-NEXT:    v_mul_hi_u32 v14, v6, v7
2017; GFX10-NEXT:    v_mul_hi_u32 v7, v5, v7
2018; GFX10-NEXT:    v_add_co_u32 v8, s3, v8, v12
2019; GFX10-NEXT:    v_mul_lo_u32 v15, v3, v1
2020; GFX10-NEXT:    v_mul_hi_u32 v16, v4, v1
2021; GFX10-NEXT:    v_add3_u32 v2, v2, v11, v9
2022; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s3
2023; GFX10-NEXT:    v_add_co_u32 v0, s3, v13, v0
2024; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s3
2025; GFX10-NEXT:    v_add_co_u32 v8, s3, v8, v10
2026; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s3
2027; GFX10-NEXT:    v_add_co_u32 v0, s3, v0, v14
2028; GFX10-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s3
2029; GFX10-NEXT:    v_mul_lo_u32 v12, v4, v2
2030; GFX10-NEXT:    v_add_nc_u32_e32 v8, v9, v8
2031; GFX10-NEXT:    v_mul_hi_u32 v1, v3, v1
2032; GFX10-NEXT:    v_mul_lo_u32 v13, v3, v2
2033; GFX10-NEXT:    v_add_nc_u32_e32 v10, v11, v10
2034; GFX10-NEXT:    v_mul_hi_u32 v9, v4, v2
2035; GFX10-NEXT:    v_add_co_u32 v0, s3, v0, v8
2036; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s3
2037; GFX10-NEXT:    v_add_co_u32 v11, s3, v15, v12
2038; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v6, v0
2039; GFX10-NEXT:    v_add3_u32 v7, v10, v8, v7
2040; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s3
2041; GFX10-NEXT:    v_add_co_u32 v1, s3, v13, v1
2042; GFX10-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s3
2043; GFX10-NEXT:    v_add_co_ci_u32_e32 v5, vcc_lo, v5, v7, vcc_lo
2044; GFX10-NEXT:    v_add_co_u32 v8, s3, v11, v16
2045; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s3
2046; GFX10-NEXT:    v_add_co_u32 v1, s3, v1, v9
2047; GFX10-NEXT:    v_mul_lo_u32 v7, s1, v0
2048; GFX10-NEXT:    v_mul_lo_u32 v9, s0, v5
2049; GFX10-NEXT:    v_mul_hi_u32 v10, s1, v0
2050; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v0
2051; GFX10-NEXT:    v_mul_lo_u32 v11, s1, v5
2052; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s3
2053; GFX10-NEXT:    v_add_nc_u32_e32 v8, v12, v8
2054; GFX10-NEXT:    v_mul_hi_u32 v12, s0, v5
2055; GFX10-NEXT:    v_mul_hi_u32 v5, s1, v5
2056; GFX10-NEXT:    v_add_co_u32 v7, s3, v7, v9
2057; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s3
2058; GFX10-NEXT:    v_add_co_u32 v10, s3, v11, v10
2059; GFX10-NEXT:    v_add_co_u32 v0, s6, v7, v0
2060; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s6
2061; GFX10-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s3
2062; GFX10-NEXT:    v_add_co_u32 v10, s3, v10, v12
2063; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s3
2064; GFX10-NEXT:    v_add_nc_u32_e32 v0, v9, v0
2065; GFX10-NEXT:    v_add_co_u32 v8, s3, v1, v8
2066; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s3
2067; GFX10-NEXT:    v_add_nc_u32_e32 v7, v7, v11
2068; GFX10-NEXT:    v_add_co_u32 v9, s3, v10, v0
2069; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s3
2070; GFX10-NEXT:    v_mul_hi_u32 v2, v3, v2
2071; GFX10-NEXT:    v_add_nc_u32_e32 v6, v13, v6
2072; GFX10-NEXT:    v_add_co_u32 v4, vcc_lo, v4, v8
2073; GFX10-NEXT:    v_add3_u32 v5, v7, v0, v5
2074; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
2075; GFX10-NEXT:    v_mul_hi_u32 v8, s14, v4
2076; GFX10-NEXT:    v_add3_u32 v2, v6, v1, v2
2077; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s3, s8, v9, 0
2078; GFX10-NEXT:    v_mul_lo_u32 v6, s9, v9
2079; GFX10-NEXT:    v_mul_lo_u32 v7, s8, v5
2080; GFX10-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, v3, v2, vcc_lo
2081; GFX10-NEXT:    v_mul_lo_u32 v3, s15, v4
2082; GFX10-NEXT:    v_mul_hi_u32 v4, s15, v4
2083; GFX10-NEXT:    v_mul_lo_u32 v10, s14, v2
2084; GFX10-NEXT:    v_mul_lo_u32 v11, s15, v2
2085; GFX10-NEXT:    v_add3_u32 v1, v1, v7, v6
2086; GFX10-NEXT:    v_add_co_u32 v6, vcc_lo, v9, 1
2087; GFX10-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo
2088; GFX10-NEXT:    v_sub_nc_u32_e32 v12, s1, v1
2089; GFX10-NEXT:    v_sub_co_u32 v13, vcc_lo, s0, v0
2090; GFX10-NEXT:    v_sub_co_ci_u32_e64 v14, s0, s1, v1, vcc_lo
2091; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v0, vcc_lo, s9, v12, vcc_lo
2092; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s8, v13
2093; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
2094; GFX10-NEXT:    v_sub_co_u32 v12, vcc_lo, v13, s8
2095; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v15, s0, 0, v0, vcc_lo
2096; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s9, v14
2097; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v0, vcc_lo, s9, v0, vcc_lo
2098; GFX10-NEXT:    v_cndmask_b32_e64 v16, 0, -1, s0
2099; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s8, v12
2100; GFX10-NEXT:    v_cndmask_b32_e64 v17, 0, -1, s0
2101; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s9, v15
2102; GFX10-NEXT:    v_cndmask_b32_e64 v18, 0, -1, s0
2103; GFX10-NEXT:    v_add_co_u32 v19, s0, v6, 1
2104; GFX10-NEXT:    v_add_co_ci_u32_e64 v20, s0, 0, v7, s0
2105; GFX10-NEXT:    v_cmp_eq_u32_e64 s0, s9, v14
2106; GFX10-NEXT:    v_cndmask_b32_e64 v16, v16, v1, s0
2107; GFX10-NEXT:    v_cmp_eq_u32_e64 s0, s9, v15
2108; GFX10-NEXT:    v_cndmask_b32_e64 v17, v18, v17, s0
2109; GFX10-NEXT:    v_add_co_u32 v1, s0, v3, v10
2110; GFX10-NEXT:    v_mul_hi_u32 v10, s14, v2
2111; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s0
2112; GFX10-NEXT:    v_add_co_u32 v4, s0, v11, v4
2113; GFX10-NEXT:    v_add_co_u32 v1, s1, v1, v8
2114; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s1
2115; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s0
2116; GFX10-NEXT:    v_add_co_u32 v4, s0, v4, v10
2117; GFX10-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s0
2118; GFX10-NEXT:    v_add_nc_u32_e32 v1, v3, v1
2119; GFX10-NEXT:    v_mul_hi_u32 v2, s15, v2
2120; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
2121; GFX10-NEXT:    v_add_nc_u32_e32 v3, v8, v10
2122; GFX10-NEXT:    v_add_co_u32 v4, s0, v4, v1
2123; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
2124; GFX10-NEXT:    v_sub_co_u32 v8, s0, v12, s8
2125; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v10, s0, 0, v0, s0
2126; GFX10-NEXT:    v_add3_u32 v2, v3, v1, v2
2127; GFX10-NEXT:    v_cndmask_b32_e32 v3, v6, v19, vcc_lo
2128; GFX10-NEXT:    v_cndmask_b32_e32 v6, v7, v20, vcc_lo
2129; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s0, s10, v4, 0
2130; GFX10-NEXT:    v_mul_lo_u32 v7, s10, v2
2131; GFX10-NEXT:    v_mul_lo_u32 v11, s11, v4
2132; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v17
2133; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v16
2134; GFX10-NEXT:    v_mov_b32_e32 v16, 0
2135; GFX10-NEXT:    v_cndmask_b32_e64 v8, v12, v8, s0
2136; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc_lo
2137; GFX10-NEXT:    v_add3_u32 v1, v1, v7, v11
2138; GFX10-NEXT:    v_cndmask_b32_e64 v6, v15, v10, s0
2139; GFX10-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc_lo
2140; GFX10-NEXT:    v_cndmask_b32_e32 v7, v13, v8, vcc_lo
2141; GFX10-NEXT:    v_sub_co_u32 v8, s0, s14, v0
2142; GFX10-NEXT:    v_sub_co_ci_u32_e64 v9, s1, s15, v1, s0
2143; GFX10-NEXT:    v_cndmask_b32_e32 v6, v14, v6, vcc_lo
2144; GFX10-NEXT:    v_sub_nc_u32_e32 v1, s15, v1
2145; GFX10-NEXT:    v_xor_b32_e32 v0, s18, v3
2146; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s11, v9
2147; GFX10-NEXT:    v_xor_b32_e32 v3, s19, v5
2148; GFX10-NEXT:    v_xor_b32_e32 v6, s2, v6
2149; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc_lo
2150; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v10, vcc_lo, s11, v1, s0
2151; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s10, v8
2152; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, -1, vcc_lo
2153; GFX10-NEXT:    v_sub_co_u32 v12, vcc_lo, v8, s10
2154; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v13, s0, 0, v10, vcc_lo
2155; GFX10-NEXT:    v_sub_co_u32 v0, s0, v0, s18
2156; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v1, s0, s19, v3, s0
2157; GFX10-NEXT:    v_cmp_eq_u32_e64 s0, s11, v9
2158; GFX10-NEXT:    v_xor_b32_e32 v3, s2, v7
2159; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
2160; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v11, s0
2161; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s11, v13
2162; GFX10-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s0
2163; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s10, v12
2164; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s0
2165; GFX10-NEXT:    v_add_co_u32 v14, s0, v4, 1
2166; GFX10-NEXT:    v_add_co_ci_u32_e64 v15, s0, 0, v2, s0
2167; GFX10-NEXT:    v_cmp_eq_u32_e64 s0, s11, v13
2168; GFX10-NEXT:    v_cndmask_b32_e64 v7, v7, v11, s0
2169; GFX10-NEXT:    v_add_co_u32 v11, s0, v14, 1
2170; GFX10-NEXT:    v_add_co_ci_u32_e64 v17, s0, 0, v15, s0
2171; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v7
2172; GFX10-NEXT:    v_sub_co_u32 v7, s0, v12, s10
2173; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v10, s0, 0, v10, s0
2174; GFX10-NEXT:    v_cndmask_b32_e32 v11, v14, v11, vcc_lo
2175; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v5
2176; GFX10-NEXT:    v_cndmask_b32_e32 v14, v15, v17, vcc_lo
2177; GFX10-NEXT:    v_cndmask_b32_e32 v5, v12, v7, vcc_lo
2178; GFX10-NEXT:    v_cndmask_b32_e32 v7, v13, v10, vcc_lo
2179; GFX10-NEXT:    v_cndmask_b32_e64 v10, v4, v11, s0
2180; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, v14, s0
2181; GFX10-NEXT:    v_cndmask_b32_e64 v8, v8, v5, s0
2182; GFX10-NEXT:    v_cndmask_b32_e64 v7, v9, v7, s0
2183; GFX10-NEXT:    s_xor_b64 s[0:1], s[12:13], s[16:17]
2184; GFX10-NEXT:    v_sub_co_u32 v4, vcc_lo, v3, s2
2185; GFX10-NEXT:    v_xor_b32_e32 v3, s0, v10
2186; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v5, vcc_lo, s2, v6, vcc_lo
2187; GFX10-NEXT:    v_xor_b32_e32 v6, s1, v2
2188; GFX10-NEXT:    v_xor_b32_e32 v8, s12, v8
2189; GFX10-NEXT:    v_xor_b32_e32 v7, s12, v7
2190; GFX10-NEXT:    v_sub_co_u32 v2, vcc_lo, v3, s0
2191; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v6, vcc_lo
2192; GFX10-NEXT:    v_sub_co_u32 v6, vcc_lo, v8, s12
2193; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v7, vcc_lo, s12, v7, vcc_lo
2194; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
2195; GFX10-NEXT:    global_store_dwordx4 v16, v[0:3], s[4:5]
2196; GFX10-NEXT:    global_store_dwordx4 v16, v[4:7], s[6:7]
2197; GFX10-NEXT:    s_endpgm
2198  %div = sdiv <2 x i64> %x, %y
2199  store <2 x i64> %div, <2 x i64> addrspace(1)* %out0
2200  %rem = srem <2 x i64> %x, %y
2201  store <2 x i64> %rem, <2 x i64> addrspace(1)* %out1
2202  ret void
2203}
2204
2205define amdgpu_kernel void @sdiv_i8(i8 addrspace(1)* %out0, i8 addrspace(1)* %out1, i8 %x, i8 %y) {
2206; GFX8-LABEL: sdiv_i8:
2207; GFX8:       ; %bb.0:
2208; GFX8-NEXT:    s_load_dword s6, s[4:5], 0x10
2209; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
2210; GFX8-NEXT:    s_bfe_i32 s0, s6, 0x80008
2211; GFX8-NEXT:    s_ashr_i32 s7, s0, 31
2212; GFX8-NEXT:    s_add_i32 s0, s0, s7
2213; GFX8-NEXT:    s_xor_b32 s8, s0, s7
2214; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s8
2215; GFX8-NEXT:    s_sub_i32 s0, 0, s8
2216; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
2217; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
2218; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0
2219; GFX8-NEXT:    v_mul_lo_u32 v1, s0, v0
2220; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
2221; GFX8-NEXT:    s_sext_i32_i8 s4, s6
2222; GFX8-NEXT:    s_ashr_i32 s5, s4, 31
2223; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v1
2224; GFX8-NEXT:    s_add_i32 s4, s4, s5
2225; GFX8-NEXT:    s_xor_b32 s4, s4, s5
2226; GFX8-NEXT:    s_xor_b32 s6, s5, s7
2227; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
2228; GFX8-NEXT:    v_mul_hi_u32 v2, s4, v0
2229; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
2230; GFX8-NEXT:    v_mov_b32_e32 v0, s0
2231; GFX8-NEXT:    v_mov_b32_e32 v1, s1
2232; GFX8-NEXT:    v_mul_lo_u32 v3, v2, s8
2233; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v2
2234; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s4, v3
2235; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
2236; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2237; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s8, v3
2238; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
2239; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v2
2240; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
2241; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2242; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s8, v3
2243; GFX8-NEXT:    v_xor_b32_e32 v2, s6, v2
2244; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
2245; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s6, v2
2246; GFX8-NEXT:    v_xor_b32_e32 v3, s5, v3
2247; GFX8-NEXT:    flat_store_byte v[0:1], v2
2248; GFX8-NEXT:    v_mov_b32_e32 v0, s2
2249; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, s5, v3
2250; GFX8-NEXT:    v_mov_b32_e32 v1, s3
2251; GFX8-NEXT:    flat_store_byte v[0:1], v3
2252; GFX8-NEXT:    s_endpgm
2253;
2254; GFX9-LABEL: sdiv_i8:
2255; GFX9:       ; %bb.0:
2256; GFX9-NEXT:    s_load_dword s0, s[4:5], 0x10
2257; GFX9-NEXT:    v_mov_b32_e32 v2, 0
2258; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
2259; GFX9-NEXT:    s_bfe_i32 s1, s0, 0x80008
2260; GFX9-NEXT:    s_ashr_i32 s6, s1, 31
2261; GFX9-NEXT:    s_add_i32 s1, s1, s6
2262; GFX9-NEXT:    s_xor_b32 s7, s1, s6
2263; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s7
2264; GFX9-NEXT:    s_sub_i32 s1, 0, s7
2265; GFX9-NEXT:    s_sext_i32_i8 s0, s0
2266; GFX9-NEXT:    s_ashr_i32 s8, s0, 31
2267; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
2268; GFX9-NEXT:    s_add_i32 s0, s0, s8
2269; GFX9-NEXT:    s_xor_b32 s9, s0, s8
2270; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
2271; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
2272; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v0
2273; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
2274; GFX9-NEXT:    s_xor_b32 s4, s8, s6
2275; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
2276; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
2277; GFX9-NEXT:    v_mul_hi_u32 v0, s9, v0
2278; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s7
2279; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
2280; GFX9-NEXT:    v_sub_u32_e32 v1, s9, v1
2281; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
2282; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
2283; GFX9-NEXT:    v_subrev_u32_e32 v3, s7, v1
2284; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
2285; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
2286; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
2287; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
2288; GFX9-NEXT:    v_subrev_u32_e32 v3, s7, v1
2289; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
2290; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v0
2291; GFX9-NEXT:    v_subrev_u32_e32 v0, s4, v0
2292; GFX9-NEXT:    v_xor_b32_e32 v1, s8, v1
2293; GFX9-NEXT:    v_subrev_u32_e32 v1, s8, v1
2294; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
2295; GFX9-NEXT:    global_store_byte v2, v0, s[0:1]
2296; GFX9-NEXT:    global_store_byte v2, v1, s[2:3]
2297; GFX9-NEXT:    s_endpgm
2298;
2299; GFX10-LABEL: sdiv_i8:
2300; GFX10:       ; %bb.0:
2301; GFX10-NEXT:    s_load_dword s0, s[4:5], 0x10
2302; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
2303; GFX10-NEXT:    s_bfe_i32 s1, s0, 0x80008
2304; GFX10-NEXT:    s_sext_i32_i8 s0, s0
2305; GFX10-NEXT:    s_ashr_i32 s6, s1, 31
2306; GFX10-NEXT:    s_ashr_i32 s8, s0, 31
2307; GFX10-NEXT:    s_add_i32 s1, s1, s6
2308; GFX10-NEXT:    s_add_i32 s0, s0, s8
2309; GFX10-NEXT:    s_xor_b32 s7, s1, s6
2310; GFX10-NEXT:    s_xor_b32 s0, s0, s8
2311; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s7
2312; GFX10-NEXT:    s_sub_i32 s1, 0, s7
2313; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
2314; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
2315; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
2316; GFX10-NEXT:    v_mul_lo_u32 v1, s1, v0
2317; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v1
2318; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1
2319; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v0
2320; GFX10-NEXT:    v_mul_lo_u32 v1, v0, s7
2321; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v0
2322; GFX10-NEXT:    v_sub_nc_u32_e32 v1, s0, v1
2323; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
2324; GFX10-NEXT:    s_xor_b32 s4, s8, s6
2325; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s7, v1
2326; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s7, v1
2327; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
2328; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo
2329; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v0
2330; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s7, v1
2331; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s7, v1
2332; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
2333; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo
2334; GFX10-NEXT:    v_mov_b32_e32 v2, 0
2335; GFX10-NEXT:    v_xor_b32_e32 v0, s4, v0
2336; GFX10-NEXT:    v_xor_b32_e32 v1, s8, v1
2337; GFX10-NEXT:    v_subrev_nc_u32_e32 v0, s4, v0
2338; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, s8, v1
2339; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
2340; GFX10-NEXT:    global_store_byte v2, v0, s[0:1]
2341; GFX10-NEXT:    global_store_byte v2, v1, s[2:3]
2342; GFX10-NEXT:    s_endpgm
2343  %div = sdiv i8 %x, %y
2344  store i8 %div, i8 addrspace(1)* %out0
2345  %rem = srem i8 %x, %y
2346  store i8 %rem, i8 addrspace(1)* %out1
2347  ret void
2348}
2349
2350define amdgpu_kernel void @sdivrem_v2i8(<2 x i8> addrspace(1)* %out0, <2 x i8> addrspace(1)* %out1, <2 x i8> %x, <2 x i8> %y) {
2351; GFX8-LABEL: sdivrem_v2i8:
2352; GFX8:       ; %bb.0:
2353; GFX8-NEXT:    s_load_dword s2, s[4:5], 0x10
2354; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
2355; GFX8-NEXT:    s_bfe_i32 s0, s2, 0x80010
2356; GFX8-NEXT:    s_ashr_i32 s3, s0, 31
2357; GFX8-NEXT:    s_add_i32 s0, s0, s3
2358; GFX8-NEXT:    s_xor_b32 s8, s0, s3
2359; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s8
2360; GFX8-NEXT:    s_sub_i32 s6, 0, s8
2361; GFX8-NEXT:    s_bfe_i32 s1, s2, 0x80018
2362; GFX8-NEXT:    s_ashr_i32 s10, s1, 31
2363; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
2364; GFX8-NEXT:    s_add_i32 s1, s1, s10
2365; GFX8-NEXT:    s_xor_b32 s11, s1, s10
2366; GFX8-NEXT:    s_sext_i32_i8 s0, s2
2367; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
2368; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0
2369; GFX8-NEXT:    v_cvt_f32_u32_e32 v2, s11
2370; GFX8-NEXT:    s_ashr_i32 s9, s0, 31
2371; GFX8-NEXT:    s_add_i32 s0, s0, s9
2372; GFX8-NEXT:    v_mul_lo_u32 v1, s6, v0
2373; GFX8-NEXT:    s_xor_b32 s0, s0, s9
2374; GFX8-NEXT:    v_rcp_iflag_f32_e32 v2, v2
2375; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
2376; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v1
2377; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
2378; GFX8-NEXT:    v_mul_hi_u32 v0, s0, v0
2379; GFX8-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v2
2380; GFX8-NEXT:    v_cvt_u32_f32_e32 v1, v1
2381; GFX8-NEXT:    v_mul_lo_u32 v2, v0, s8
2382; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v0
2383; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, s0, v2
2384; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
2385; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
2386; GFX8-NEXT:    v_subrev_u32_e64 v3, s[0:1], s8, v2
2387; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
2388; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v0
2389; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
2390; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
2391; GFX8-NEXT:    v_subrev_u32_e64 v3, s[0:1], s8, v2
2392; GFX8-NEXT:    s_sub_i32 s1, 0, s11
2393; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
2394; GFX8-NEXT:    v_mul_lo_u32 v3, s1, v1
2395; GFX8-NEXT:    s_bfe_i32 s1, s2, 0x80008
2396; GFX8-NEXT:    s_ashr_i32 s2, s1, 31
2397; GFX8-NEXT:    s_add_i32 s1, s1, s2
2398; GFX8-NEXT:    v_mul_hi_u32 v3, v1, v3
2399; GFX8-NEXT:    s_xor_b32 s1, s1, s2
2400; GFX8-NEXT:    s_xor_b32 s0, s9, s3
2401; GFX8-NEXT:    v_xor_b32_e32 v0, s0, v0
2402; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v3
2403; GFX8-NEXT:    v_mul_hi_u32 v1, s1, v1
2404; GFX8-NEXT:    v_xor_b32_e32 v2, s9, v2
2405; GFX8-NEXT:    v_subrev_u32_e32 v0, vcc, s0, v0
2406; GFX8-NEXT:    v_mul_lo_u32 v3, v1, s11
2407; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s9, v2
2408; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v1
2409; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s1, v3
2410; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
2411; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
2412; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s11, v3
2413; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
2414; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v1
2415; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
2416; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
2417; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s11, v3
2418; GFX8-NEXT:    s_xor_b32 s0, s2, s10
2419; GFX8-NEXT:    v_xor_b32_e32 v1, s0, v1
2420; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
2421; GFX8-NEXT:    v_subrev_u32_e32 v1, vcc, s0, v1
2422; GFX8-NEXT:    v_and_b32_e32 v1, 0xff, v1
2423; GFX8-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
2424; GFX8-NEXT:    v_xor_b32_e32 v3, s2, v3
2425; GFX8-NEXT:    v_or_b32_sdwa v4, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
2426; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
2427; GFX8-NEXT:    v_mov_b32_e32 v0, s4
2428; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, s2, v3
2429; GFX8-NEXT:    v_mov_b32_e32 v1, s5
2430; GFX8-NEXT:    flat_store_short v[0:1], v4
2431; GFX8-NEXT:    v_and_b32_e32 v0, 0xff, v3
2432; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 8, v0
2433; GFX8-NEXT:    v_or_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
2434; GFX8-NEXT:    v_mov_b32_e32 v0, s6
2435; GFX8-NEXT:    v_mov_b32_e32 v1, s7
2436; GFX8-NEXT:    flat_store_short v[0:1], v2
2437; GFX8-NEXT:    s_endpgm
2438;
2439; GFX9-LABEL: sdivrem_v2i8:
2440; GFX9:       ; %bb.0:
2441; GFX9-NEXT:    s_load_dword s6, s[4:5], 0x10
2442; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
2443; GFX9-NEXT:    s_bfe_i32 s0, s6, 0x80010
2444; GFX9-NEXT:    s_ashr_i32 s7, s0, 31
2445; GFX9-NEXT:    s_add_i32 s0, s0, s7
2446; GFX9-NEXT:    s_xor_b32 s8, s0, s7
2447; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
2448; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
2449; GFX9-NEXT:    s_bfe_i32 s5, s6, 0x80018
2450; GFX9-NEXT:    s_ashr_i32 s9, s5, 31
2451; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
2452; GFX9-NEXT:    s_add_i32 s5, s5, s9
2453; GFX9-NEXT:    s_xor_b32 s5, s5, s9
2454; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s5
2455; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
2456; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
2457; GFX9-NEXT:    s_sub_i32 s10, 0, s8
2458; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
2459; GFX9-NEXT:    s_sext_i32_i8 s4, s6
2460; GFX9-NEXT:    v_mul_lo_u32 v2, s10, v0
2461; GFX9-NEXT:    s_ashr_i32 s10, s4, 31
2462; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
2463; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
2464; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
2465; GFX9-NEXT:    s_add_i32 s4, s4, s10
2466; GFX9-NEXT:    s_xor_b32 s4, s4, s10
2467; GFX9-NEXT:    s_sub_i32 s11, 0, s5
2468; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
2469; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
2470; GFX9-NEXT:    v_mul_lo_u32 v2, s11, v1
2471; GFX9-NEXT:    s_bfe_i32 s6, s6, 0x80008
2472; GFX9-NEXT:    s_ashr_i32 s11, s6, 31
2473; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s8
2474; GFX9-NEXT:    v_mul_hi_u32 v2, v1, v2
2475; GFX9-NEXT:    s_add_i32 s6, s6, s11
2476; GFX9-NEXT:    v_add_u32_e32 v4, 1, v0
2477; GFX9-NEXT:    v_sub_u32_e32 v3, s4, v3
2478; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
2479; GFX9-NEXT:    s_xor_b32 s4, s6, s11
2480; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
2481; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
2482; GFX9-NEXT:    v_subrev_u32_e32 v4, s8, v3
2483; GFX9-NEXT:    v_mul_hi_u32 v1, s4, v1
2484; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
2485; GFX9-NEXT:    v_add_u32_e32 v4, 1, v0
2486; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
2487; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
2488; GFX9-NEXT:    v_subrev_u32_e32 v4, s8, v3
2489; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc
2490; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s5
2491; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
2492; GFX9-NEXT:    s_xor_b32 s6, s10, s7
2493; GFX9-NEXT:    v_xor_b32_e32 v0, s6, v0
2494; GFX9-NEXT:    v_sub_u32_e32 v3, s4, v3
2495; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v3
2496; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
2497; GFX9-NEXT:    v_subrev_u32_e32 v4, s5, v3
2498; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
2499; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
2500; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v3
2501; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
2502; GFX9-NEXT:    s_xor_b32 s4, s11, s9
2503; GFX9-NEXT:    v_xor_b32_e32 v1, s4, v1
2504; GFX9-NEXT:    v_subrev_u32_e32 v4, s5, v3
2505; GFX9-NEXT:    v_subrev_u32_e32 v1, s4, v1
2506; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
2507; GFX9-NEXT:    v_and_b32_e32 v1, 0xff, v1
2508; GFX9-NEXT:    v_subrev_u32_e32 v0, s6, v0
2509; GFX9-NEXT:    v_xor_b32_e32 v3, s11, v3
2510; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
2511; GFX9-NEXT:    v_subrev_u32_e32 v3, s11, v3
2512; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
2513; GFX9-NEXT:    v_mov_b32_e32 v1, 0
2514; GFX9-NEXT:    v_xor_b32_e32 v2, s10, v2
2515; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
2516; GFX9-NEXT:    global_store_short v1, v0, s[0:1]
2517; GFX9-NEXT:    v_and_b32_e32 v0, 0xff, v3
2518; GFX9-NEXT:    v_subrev_u32_e32 v2, s10, v2
2519; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 8, v0
2520; GFX9-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
2521; GFX9-NEXT:    global_store_short v1, v0, s[2:3]
2522; GFX9-NEXT:    s_endpgm
2523;
2524; GFX10-LABEL: sdivrem_v2i8:
2525; GFX10:       ; %bb.0:
2526; GFX10-NEXT:    s_load_dword s0, s[4:5], 0x10
2527; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
2528; GFX10-NEXT:    s_bfe_i32 s1, s0, 0x80018
2529; GFX10-NEXT:    s_bfe_i32 s2, s0, 0x80010
2530; GFX10-NEXT:    s_ashr_i32 s3, s1, 31
2531; GFX10-NEXT:    s_ashr_i32 s8, s2, 31
2532; GFX10-NEXT:    s_add_i32 s1, s1, s3
2533; GFX10-NEXT:    s_add_i32 s2, s2, s8
2534; GFX10-NEXT:    s_xor_b32 s1, s1, s3
2535; GFX10-NEXT:    s_xor_b32 s2, s2, s8
2536; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s1
2537; GFX10-NEXT:    v_cvt_f32_u32_e32 v1, s2
2538; GFX10-NEXT:    s_sub_i32 s6, 0, s1
2539; GFX10-NEXT:    s_sub_i32 s7, 0, s2
2540; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
2541; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v1
2542; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
2543; GFX10-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
2544; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
2545; GFX10-NEXT:    v_cvt_u32_f32_e32 v1, v1
2546; GFX10-NEXT:    v_mul_lo_u32 v2, s6, v0
2547; GFX10-NEXT:    v_mul_lo_u32 v3, s7, v1
2548; GFX10-NEXT:    s_sext_i32_i8 s6, s0
2549; GFX10-NEXT:    s_bfe_i32 s0, s0, 0x80008
2550; GFX10-NEXT:    s_ashr_i32 s9, s6, 31
2551; GFX10-NEXT:    s_ashr_i32 s10, s0, 31
2552; GFX10-NEXT:    s_add_i32 s6, s6, s9
2553; GFX10-NEXT:    s_add_i32 s0, s0, s10
2554; GFX10-NEXT:    v_mul_hi_u32 v2, v0, v2
2555; GFX10-NEXT:    v_mul_hi_u32 v3, v1, v3
2556; GFX10-NEXT:    s_xor_b32 s0, s0, s10
2557; GFX10-NEXT:    s_xor_b32 s6, s6, s9
2558; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v2
2559; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v3
2560; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v0
2561; GFX10-NEXT:    v_mul_hi_u32 v1, s6, v1
2562; GFX10-NEXT:    v_mul_lo_u32 v2, v0, s1
2563; GFX10-NEXT:    v_mul_lo_u32 v3, v1, s2
2564; GFX10-NEXT:    v_add_nc_u32_e32 v5, 1, v0
2565; GFX10-NEXT:    v_add_nc_u32_e32 v4, 1, v1
2566; GFX10-NEXT:    v_sub_nc_u32_e32 v2, s0, v2
2567; GFX10-NEXT:    v_sub_nc_u32_e32 v3, s6, v3
2568; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
2569; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s1, v2
2570; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, s1, v2
2571; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, s2, v3
2572; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s2, v3
2573; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc_lo
2574; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc_lo
2575; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s0
2576; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v7, s0
2577; GFX10-NEXT:    v_add_nc_u32_e32 v5, 1, v0
2578; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s1, v2
2579; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, s1, v2
2580; GFX10-NEXT:    v_add_nc_u32_e32 v4, 1, v1
2581; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s2, v3
2582; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, s2, v3
2583; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc_lo
2584; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc_lo
2585; GFX10-NEXT:    s_xor_b32 s1, s10, s3
2586; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s0
2587; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v7, s0
2588; GFX10-NEXT:    v_xor_b32_e32 v0, s1, v0
2589; GFX10-NEXT:    v_xor_b32_e32 v2, s10, v2
2590; GFX10-NEXT:    s_xor_b32 s0, s9, s8
2591; GFX10-NEXT:    v_xor_b32_e32 v1, s0, v1
2592; GFX10-NEXT:    v_subrev_nc_u32_e32 v0, s1, v0
2593; GFX10-NEXT:    v_xor_b32_e32 v3, s9, v3
2594; GFX10-NEXT:    v_subrev_nc_u32_e32 v2, s10, v2
2595; GFX10-NEXT:    s_movk_i32 s1, 0xff
2596; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, s0, v1
2597; GFX10-NEXT:    v_and_b32_sdwa v0, v0, s1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2598; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s9, v3
2599; GFX10-NEXT:    v_and_b32_sdwa v2, v2, s1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2600; GFX10-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
2601; GFX10-NEXT:    v_mov_b32_e32 v1, 0
2602; GFX10-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
2603; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
2604; GFX10-NEXT:    global_store_short v1, v0, s[4:5]
2605; GFX10-NEXT:    global_store_short v1, v2, s[6:7]
2606; GFX10-NEXT:    s_endpgm
2607  %div = sdiv <2 x i8> %x, %y
2608  store <2 x i8> %div, <2 x i8> addrspace(1)* %out0
2609  %rem = srem <2 x i8> %x, %y
2610  store <2 x i8> %rem, <2 x i8> addrspace(1)* %out1
2611  ret void
2612}
2613
2614define amdgpu_kernel void @sdiv_i16(i16 addrspace(1)* %out0, i16 addrspace(1)* %out1, i16 %x, i16 %y) {
2615; GFX8-LABEL: sdiv_i16:
2616; GFX8:       ; %bb.0:
2617; GFX8-NEXT:    s_load_dword s6, s[4:5], 0x10
2618; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
2619; GFX8-NEXT:    s_bfe_i32 s0, s6, 0x100010
2620; GFX8-NEXT:    s_ashr_i32 s7, s0, 31
2621; GFX8-NEXT:    s_add_i32 s0, s0, s7
2622; GFX8-NEXT:    s_xor_b32 s8, s0, s7
2623; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s8
2624; GFX8-NEXT:    s_sub_i32 s0, 0, s8
2625; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
2626; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
2627; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0
2628; GFX8-NEXT:    v_mul_lo_u32 v1, s0, v0
2629; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
2630; GFX8-NEXT:    s_sext_i32_i16 s4, s6
2631; GFX8-NEXT:    s_ashr_i32 s5, s4, 31
2632; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v1
2633; GFX8-NEXT:    s_add_i32 s4, s4, s5
2634; GFX8-NEXT:    s_xor_b32 s4, s4, s5
2635; GFX8-NEXT:    s_xor_b32 s6, s5, s7
2636; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
2637; GFX8-NEXT:    v_mul_hi_u32 v2, s4, v0
2638; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
2639; GFX8-NEXT:    v_mov_b32_e32 v0, s0
2640; GFX8-NEXT:    v_mov_b32_e32 v1, s1
2641; GFX8-NEXT:    v_mul_lo_u32 v3, v2, s8
2642; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v2
2643; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s4, v3
2644; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
2645; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2646; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s8, v3
2647; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
2648; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v2
2649; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
2650; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2651; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s8, v3
2652; GFX8-NEXT:    v_xor_b32_e32 v2, s6, v2
2653; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
2654; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s6, v2
2655; GFX8-NEXT:    v_xor_b32_e32 v3, s5, v3
2656; GFX8-NEXT:    flat_store_short v[0:1], v2
2657; GFX8-NEXT:    v_mov_b32_e32 v0, s2
2658; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, s5, v3
2659; GFX8-NEXT:    v_mov_b32_e32 v1, s3
2660; GFX8-NEXT:    flat_store_short v[0:1], v3
2661; GFX8-NEXT:    s_endpgm
2662;
2663; GFX9-LABEL: sdiv_i16:
2664; GFX9:       ; %bb.0:
2665; GFX9-NEXT:    s_load_dword s0, s[4:5], 0x10
2666; GFX9-NEXT:    v_mov_b32_e32 v2, 0
2667; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
2668; GFX9-NEXT:    s_bfe_i32 s1, s0, 0x100010
2669; GFX9-NEXT:    s_ashr_i32 s6, s1, 31
2670; GFX9-NEXT:    s_add_i32 s1, s1, s6
2671; GFX9-NEXT:    s_xor_b32 s7, s1, s6
2672; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s7
2673; GFX9-NEXT:    s_sub_i32 s1, 0, s7
2674; GFX9-NEXT:    s_sext_i32_i16 s0, s0
2675; GFX9-NEXT:    s_ashr_i32 s8, s0, 31
2676; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
2677; GFX9-NEXT:    s_add_i32 s0, s0, s8
2678; GFX9-NEXT:    s_xor_b32 s9, s0, s8
2679; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
2680; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
2681; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v0
2682; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
2683; GFX9-NEXT:    s_xor_b32 s4, s8, s6
2684; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
2685; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
2686; GFX9-NEXT:    v_mul_hi_u32 v0, s9, v0
2687; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s7
2688; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
2689; GFX9-NEXT:    v_sub_u32_e32 v1, s9, v1
2690; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
2691; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
2692; GFX9-NEXT:    v_subrev_u32_e32 v3, s7, v1
2693; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
2694; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
2695; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
2696; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
2697; GFX9-NEXT:    v_subrev_u32_e32 v3, s7, v1
2698; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
2699; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v0
2700; GFX9-NEXT:    v_subrev_u32_e32 v0, s4, v0
2701; GFX9-NEXT:    v_xor_b32_e32 v1, s8, v1
2702; GFX9-NEXT:    v_subrev_u32_e32 v1, s8, v1
2703; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
2704; GFX9-NEXT:    global_store_short v2, v0, s[0:1]
2705; GFX9-NEXT:    global_store_short v2, v1, s[2:3]
2706; GFX9-NEXT:    s_endpgm
2707;
2708; GFX10-LABEL: sdiv_i16:
2709; GFX10:       ; %bb.0:
2710; GFX10-NEXT:    s_load_dword s0, s[4:5], 0x10
2711; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
2712; GFX10-NEXT:    s_bfe_i32 s1, s0, 0x100010
2713; GFX10-NEXT:    s_sext_i32_i16 s0, s0
2714; GFX10-NEXT:    s_ashr_i32 s6, s1, 31
2715; GFX10-NEXT:    s_ashr_i32 s8, s0, 31
2716; GFX10-NEXT:    s_add_i32 s1, s1, s6
2717; GFX10-NEXT:    s_add_i32 s0, s0, s8
2718; GFX10-NEXT:    s_xor_b32 s7, s1, s6
2719; GFX10-NEXT:    s_xor_b32 s0, s0, s8
2720; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s7
2721; GFX10-NEXT:    s_sub_i32 s1, 0, s7
2722; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
2723; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
2724; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
2725; GFX10-NEXT:    v_mul_lo_u32 v1, s1, v0
2726; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v1
2727; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1
2728; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v0
2729; GFX10-NEXT:    v_mul_lo_u32 v1, v0, s7
2730; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v0
2731; GFX10-NEXT:    v_sub_nc_u32_e32 v1, s0, v1
2732; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
2733; GFX10-NEXT:    s_xor_b32 s4, s8, s6
2734; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s7, v1
2735; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s7, v1
2736; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
2737; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo
2738; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v0
2739; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s7, v1
2740; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s7, v1
2741; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
2742; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo
2743; GFX10-NEXT:    v_mov_b32_e32 v2, 0
2744; GFX10-NEXT:    v_xor_b32_e32 v0, s4, v0
2745; GFX10-NEXT:    v_xor_b32_e32 v1, s8, v1
2746; GFX10-NEXT:    v_subrev_nc_u32_e32 v0, s4, v0
2747; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, s8, v1
2748; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
2749; GFX10-NEXT:    global_store_short v2, v0, s[0:1]
2750; GFX10-NEXT:    global_store_short v2, v1, s[2:3]
2751; GFX10-NEXT:    s_endpgm
2752  %div = sdiv i16 %x, %y
2753  store i16 %div, i16 addrspace(1)* %out0
2754  %rem = srem i16 %x, %y
2755  store i16 %rem, i16 addrspace(1)* %out1
2756  ret void
2757}
2758
2759define amdgpu_kernel void @sdivrem_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> %x, <2 x i16> %y) {
2760; GFX8-LABEL: sdivrem_v2i16:
2761; GFX8:       ; %bb.0:
2762; GFX8-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x10
2763; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
2764; GFX8-NEXT:    s_sext_i32_i16 s0, s3
2765; GFX8-NEXT:    s_ashr_i32 s8, s0, 31
2766; GFX8-NEXT:    s_add_i32 s0, s0, s8
2767; GFX8-NEXT:    s_xor_b32 s9, s0, s8
2768; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s9
2769; GFX8-NEXT:    s_sub_i32 s6, 0, s9
2770; GFX8-NEXT:    s_bfe_i32 s1, s3, 0x100010
2771; GFX8-NEXT:    s_ashr_i32 s10, s1, 31
2772; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
2773; GFX8-NEXT:    s_add_i32 s1, s1, s10
2774; GFX8-NEXT:    s_xor_b32 s11, s1, s10
2775; GFX8-NEXT:    s_sext_i32_i16 s0, s2
2776; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
2777; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0
2778; GFX8-NEXT:    v_cvt_f32_u32_e32 v2, s11
2779; GFX8-NEXT:    s_ashr_i32 s3, s0, 31
2780; GFX8-NEXT:    s_add_i32 s0, s0, s3
2781; GFX8-NEXT:    v_mul_lo_u32 v1, s6, v0
2782; GFX8-NEXT:    s_xor_b32 s0, s0, s3
2783; GFX8-NEXT:    v_rcp_iflag_f32_e32 v2, v2
2784; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
2785; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v1
2786; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
2787; GFX8-NEXT:    v_mul_hi_u32 v0, s0, v0
2788; GFX8-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v2
2789; GFX8-NEXT:    v_cvt_u32_f32_e32 v1, v1
2790; GFX8-NEXT:    v_mul_lo_u32 v2, v0, s9
2791; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v0
2792; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, s0, v2
2793; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
2794; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
2795; GFX8-NEXT:    v_subrev_u32_e64 v3, s[0:1], s9, v2
2796; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
2797; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v0
2798; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
2799; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
2800; GFX8-NEXT:    v_subrev_u32_e64 v3, s[0:1], s9, v2
2801; GFX8-NEXT:    s_sub_i32 s1, 0, s11
2802; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
2803; GFX8-NEXT:    v_mul_lo_u32 v3, s1, v1
2804; GFX8-NEXT:    s_bfe_i32 s1, s2, 0x100010
2805; GFX8-NEXT:    s_ashr_i32 s2, s1, 31
2806; GFX8-NEXT:    s_add_i32 s1, s1, s2
2807; GFX8-NEXT:    v_mul_hi_u32 v3, v1, v3
2808; GFX8-NEXT:    s_xor_b32 s1, s1, s2
2809; GFX8-NEXT:    s_xor_b32 s0, s3, s8
2810; GFX8-NEXT:    v_xor_b32_e32 v0, s0, v0
2811; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v3
2812; GFX8-NEXT:    v_mul_hi_u32 v1, s1, v1
2813; GFX8-NEXT:    v_xor_b32_e32 v2, s3, v2
2814; GFX8-NEXT:    v_subrev_u32_e32 v0, vcc, s0, v0
2815; GFX8-NEXT:    v_mul_lo_u32 v3, v1, s11
2816; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s3, v2
2817; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v1
2818; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s1, v3
2819; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
2820; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
2821; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s11, v3
2822; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
2823; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v1
2824; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
2825; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
2826; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s11, v3
2827; GFX8-NEXT:    s_xor_b32 s0, s2, s10
2828; GFX8-NEXT:    v_xor_b32_e32 v1, s0, v1
2829; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
2830; GFX8-NEXT:    v_subrev_u32_e32 v1, vcc, s0, v1
2831; GFX8-NEXT:    v_xor_b32_e32 v3, s2, v3
2832; GFX8-NEXT:    v_and_b32_e32 v1, 0xffff, v1
2833; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, s2, v3
2834; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
2835; GFX8-NEXT:    v_or_b32_sdwa v4, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
2836; GFX8-NEXT:    v_and_b32_e32 v0, 0xffff, v3
2837; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
2838; GFX8-NEXT:    v_or_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
2839; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
2840; GFX8-NEXT:    v_mov_b32_e32 v0, s4
2841; GFX8-NEXT:    v_mov_b32_e32 v1, s5
2842; GFX8-NEXT:    flat_store_dword v[0:1], v4
2843; GFX8-NEXT:    v_mov_b32_e32 v0, s6
2844; GFX8-NEXT:    v_mov_b32_e32 v1, s7
2845; GFX8-NEXT:    flat_store_dword v[0:1], v2
2846; GFX8-NEXT:    s_endpgm
2847;
2848; GFX9-LABEL: sdivrem_v2i16:
2849; GFX9:       ; %bb.0:
2850; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x10
2851; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
2852; GFX9-NEXT:    s_sext_i32_i16 s0, s7
2853; GFX9-NEXT:    s_ashr_i32 s8, s0, 31
2854; GFX9-NEXT:    s_add_i32 s0, s0, s8
2855; GFX9-NEXT:    s_xor_b32 s9, s0, s8
2856; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s9
2857; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
2858; GFX9-NEXT:    s_bfe_i32 s5, s7, 0x100010
2859; GFX9-NEXT:    s_ashr_i32 s7, s5, 31
2860; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
2861; GFX9-NEXT:    s_add_i32 s5, s5, s7
2862; GFX9-NEXT:    s_xor_b32 s5, s5, s7
2863; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s5
2864; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
2865; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
2866; GFX9-NEXT:    s_sub_i32 s10, 0, s9
2867; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
2868; GFX9-NEXT:    s_sext_i32_i16 s4, s6
2869; GFX9-NEXT:    v_mul_lo_u32 v2, s10, v0
2870; GFX9-NEXT:    s_ashr_i32 s10, s4, 31
2871; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
2872; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
2873; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
2874; GFX9-NEXT:    s_add_i32 s4, s4, s10
2875; GFX9-NEXT:    s_xor_b32 s4, s4, s10
2876; GFX9-NEXT:    s_sub_i32 s11, 0, s5
2877; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
2878; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
2879; GFX9-NEXT:    v_mul_lo_u32 v2, s11, v1
2880; GFX9-NEXT:    s_bfe_i32 s6, s6, 0x100010
2881; GFX9-NEXT:    s_ashr_i32 s11, s6, 31
2882; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s9
2883; GFX9-NEXT:    v_mul_hi_u32 v2, v1, v2
2884; GFX9-NEXT:    s_add_i32 s6, s6, s11
2885; GFX9-NEXT:    v_add_u32_e32 v4, 1, v0
2886; GFX9-NEXT:    v_sub_u32_e32 v3, s4, v3
2887; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
2888; GFX9-NEXT:    s_xor_b32 s4, s6, s11
2889; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
2890; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
2891; GFX9-NEXT:    v_subrev_u32_e32 v4, s9, v3
2892; GFX9-NEXT:    v_mul_hi_u32 v1, s4, v1
2893; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
2894; GFX9-NEXT:    v_add_u32_e32 v4, 1, v0
2895; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
2896; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
2897; GFX9-NEXT:    v_subrev_u32_e32 v4, s9, v3
2898; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc
2899; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s5
2900; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
2901; GFX9-NEXT:    s_xor_b32 s6, s10, s8
2902; GFX9-NEXT:    v_xor_b32_e32 v0, s6, v0
2903; GFX9-NEXT:    v_sub_u32_e32 v3, s4, v3
2904; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v3
2905; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
2906; GFX9-NEXT:    v_subrev_u32_e32 v4, s5, v3
2907; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
2908; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1
2909; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v3
2910; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
2911; GFX9-NEXT:    v_subrev_u32_e32 v4, s5, v3
2912; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
2913; GFX9-NEXT:    s_xor_b32 s4, s11, s7
2914; GFX9-NEXT:    v_xor_b32_e32 v2, s10, v2
2915; GFX9-NEXT:    v_xor_b32_e32 v1, s4, v1
2916; GFX9-NEXT:    v_xor_b32_e32 v3, s11, v3
2917; GFX9-NEXT:    v_subrev_u32_e32 v0, s6, v0
2918; GFX9-NEXT:    v_subrev_u32_e32 v2, s10, v2
2919; GFX9-NEXT:    v_sub_u32_sdwa v1, v1, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2920; GFX9-NEXT:    v_sub_u32_sdwa v3, v3, s11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2921; GFX9-NEXT:    v_mov_b32_e32 v4, 0xffff
2922; GFX9-NEXT:    v_and_or_b32 v0, v0, v4, v1
2923; GFX9-NEXT:    v_and_or_b32 v1, v2, v4, v3
2924; GFX9-NEXT:    v_mov_b32_e32 v2, 0
2925; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
2926; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]
2927; GFX9-NEXT:    global_store_dword v2, v1, s[2:3]
2928; GFX9-NEXT:    s_endpgm
2929;
2930; GFX10-LABEL: sdivrem_v2i16:
2931; GFX10:       ; %bb.0:
2932; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x10
2933; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
2934; GFX10-NEXT:    s_sext_i32_i16 s2, s1
2935; GFX10-NEXT:    s_bfe_i32 s1, s1, 0x100010
2936; GFX10-NEXT:    s_ashr_i32 s3, s2, 31
2937; GFX10-NEXT:    s_ashr_i32 s8, s1, 31
2938; GFX10-NEXT:    s_add_i32 s2, s2, s3
2939; GFX10-NEXT:    s_add_i32 s1, s1, s8
2940; GFX10-NEXT:    s_xor_b32 s2, s2, s3
2941; GFX10-NEXT:    s_xor_b32 s1, s1, s8
2942; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s2
2943; GFX10-NEXT:    v_cvt_f32_u32_e32 v1, s1
2944; GFX10-NEXT:    s_sub_i32 s6, 0, s2
2945; GFX10-NEXT:    s_sub_i32 s7, 0, s1
2946; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
2947; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v1
2948; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
2949; GFX10-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
2950; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
2951; GFX10-NEXT:    v_cvt_u32_f32_e32 v1, v1
2952; GFX10-NEXT:    v_mul_lo_u32 v2, s6, v0
2953; GFX10-NEXT:    v_mul_lo_u32 v3, s7, v1
2954; GFX10-NEXT:    s_sext_i32_i16 s6, s0
2955; GFX10-NEXT:    s_bfe_i32 s0, s0, 0x100010
2956; GFX10-NEXT:    s_ashr_i32 s9, s6, 31
2957; GFX10-NEXT:    s_ashr_i32 s10, s0, 31
2958; GFX10-NEXT:    s_add_i32 s6, s6, s9
2959; GFX10-NEXT:    s_add_i32 s0, s0, s10
2960; GFX10-NEXT:    v_mul_hi_u32 v2, v0, v2
2961; GFX10-NEXT:    v_mul_hi_u32 v3, v1, v3
2962; GFX10-NEXT:    s_xor_b32 s6, s6, s9
2963; GFX10-NEXT:    s_xor_b32 s0, s0, s10
2964; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v2
2965; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v3
2966; GFX10-NEXT:    v_mul_hi_u32 v0, s6, v0
2967; GFX10-NEXT:    v_mul_hi_u32 v1, s0, v1
2968; GFX10-NEXT:    v_mul_lo_u32 v2, v0, s2
2969; GFX10-NEXT:    v_mul_lo_u32 v3, v1, s1
2970; GFX10-NEXT:    v_add_nc_u32_e32 v4, 1, v0
2971; GFX10-NEXT:    v_add_nc_u32_e32 v5, 1, v1
2972; GFX10-NEXT:    v_sub_nc_u32_e32 v2, s6, v2
2973; GFX10-NEXT:    v_sub_nc_u32_e32 v3, s0, v3
2974; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
2975; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, s2, v2
2976; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s1, v3
2977; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s2, v2
2978; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, s1, v3
2979; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc_lo
2980; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s0
2981; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, v6, s0
2982; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc_lo
2983; GFX10-NEXT:    v_add_nc_u32_e32 v5, 1, v1
2984; GFX10-NEXT:    v_add_nc_u32_e32 v4, 1, v0
2985; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s2, v2
2986; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s1, v3
2987; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, s2, v2
2988; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, s1, v3
2989; GFX10-NEXT:    s_xor_b32 s1, s9, s3
2990; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s0
2991; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc_lo
2992; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, v6, s0
2993; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc_lo
2994; GFX10-NEXT:    s_xor_b32 s0, s10, s8
2995; GFX10-NEXT:    v_xor_b32_e32 v0, s1, v0
2996; GFX10-NEXT:    v_xor_b32_e32 v1, s0, v1
2997; GFX10-NEXT:    v_xor_b32_e32 v2, s9, v2
2998; GFX10-NEXT:    v_xor_b32_e32 v3, s10, v3
2999; GFX10-NEXT:    v_subrev_nc_u32_e32 v0, s1, v0
3000; GFX10-NEXT:    v_sub_nc_u32_sdwa v1, v1, s0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
3001; GFX10-NEXT:    v_subrev_nc_u32_e32 v2, s9, v2
3002; GFX10-NEXT:    v_sub_nc_u32_sdwa v3, v3, s10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
3003; GFX10-NEXT:    v_and_or_b32 v0, 0xffff, v0, v1
3004; GFX10-NEXT:    v_mov_b32_e32 v1, 0
3005; GFX10-NEXT:    v_and_or_b32 v2, 0xffff, v2, v3
3006; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
3007; GFX10-NEXT:    global_store_dword v1, v0, s[4:5]
3008; GFX10-NEXT:    global_store_dword v1, v2, s[6:7]
3009; GFX10-NEXT:    s_endpgm
3010  %div = sdiv <2 x i16> %x, %y
3011  store <2 x i16> %div, <2 x i16> addrspace(1)* %out0
3012  %rem = srem <2 x i16> %x, %y
3013  store <2 x i16> %rem, <2 x i16> addrspace(1)* %out1
3014  ret void
3015}
3016
3017define amdgpu_kernel void @sdivrem_i3(i3 addrspace(1)* %out0, i3 addrspace(1)* %out1, i3 %x, i3 %y) {
3018; GFX8-LABEL: sdivrem_i3:
3019; GFX8:       ; %bb.0:
3020; GFX8-NEXT:    s_load_dword s6, s[4:5], 0x10
3021; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
3022; GFX8-NEXT:    s_bfe_i32 s0, s6, 0x30008
3023; GFX8-NEXT:    s_ashr_i32 s7, s0, 31
3024; GFX8-NEXT:    s_add_i32 s0, s0, s7
3025; GFX8-NEXT:    s_xor_b32 s8, s0, s7
3026; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s8
3027; GFX8-NEXT:    s_sub_i32 s0, 0, s8
3028; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
3029; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
3030; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0
3031; GFX8-NEXT:    v_mul_lo_u32 v1, s0, v0
3032; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
3033; GFX8-NEXT:    s_bfe_i32 s4, s6, 0x30000
3034; GFX8-NEXT:    s_ashr_i32 s5, s4, 31
3035; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v1
3036; GFX8-NEXT:    s_add_i32 s4, s4, s5
3037; GFX8-NEXT:    s_xor_b32 s4, s4, s5
3038; GFX8-NEXT:    s_xor_b32 s6, s5, s7
3039; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
3040; GFX8-NEXT:    v_mul_hi_u32 v2, s4, v0
3041; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
3042; GFX8-NEXT:    v_mov_b32_e32 v0, s0
3043; GFX8-NEXT:    v_mov_b32_e32 v1, s1
3044; GFX8-NEXT:    v_mul_lo_u32 v3, v2, s8
3045; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v2
3046; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s4, v3
3047; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
3048; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
3049; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s8, v3
3050; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
3051; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v2
3052; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
3053; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
3054; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s8, v3
3055; GFX8-NEXT:    v_xor_b32_e32 v2, s6, v2
3056; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
3057; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s6, v2
3058; GFX8-NEXT:    v_xor_b32_e32 v3, s5, v3
3059; GFX8-NEXT:    v_and_b32_e32 v2, 7, v2
3060; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, s5, v3
3061; GFX8-NEXT:    flat_store_byte v[0:1], v2
3062; GFX8-NEXT:    v_mov_b32_e32 v0, s2
3063; GFX8-NEXT:    v_and_b32_e32 v2, 7, v3
3064; GFX8-NEXT:    v_mov_b32_e32 v1, s3
3065; GFX8-NEXT:    flat_store_byte v[0:1], v2
3066; GFX8-NEXT:    s_endpgm
3067;
3068; GFX9-LABEL: sdivrem_i3:
3069; GFX9:       ; %bb.0:
3070; GFX9-NEXT:    s_load_dword s0, s[4:5], 0x10
3071; GFX9-NEXT:    v_mov_b32_e32 v2, 0
3072; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3073; GFX9-NEXT:    s_bfe_i32 s1, s0, 0x30008
3074; GFX9-NEXT:    s_ashr_i32 s6, s1, 31
3075; GFX9-NEXT:    s_add_i32 s1, s1, s6
3076; GFX9-NEXT:    s_xor_b32 s7, s1, s6
3077; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s7
3078; GFX9-NEXT:    s_sub_i32 s1, 0, s7
3079; GFX9-NEXT:    s_bfe_i32 s0, s0, 0x30000
3080; GFX9-NEXT:    s_ashr_i32 s8, s0, 31
3081; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
3082; GFX9-NEXT:    s_add_i32 s0, s0, s8
3083; GFX9-NEXT:    s_xor_b32 s9, s0, s8
3084; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
3085; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
3086; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v0
3087; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
3088; GFX9-NEXT:    s_xor_b32 s4, s8, s6
3089; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
3090; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
3091; GFX9-NEXT:    v_mul_hi_u32 v0, s9, v0
3092; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s7
3093; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
3094; GFX9-NEXT:    v_sub_u32_e32 v1, s9, v1
3095; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
3096; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
3097; GFX9-NEXT:    v_subrev_u32_e32 v3, s7, v1
3098; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
3099; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
3100; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
3101; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
3102; GFX9-NEXT:    v_subrev_u32_e32 v3, s7, v1
3103; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
3104; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v0
3105; GFX9-NEXT:    v_subrev_u32_e32 v0, s4, v0
3106; GFX9-NEXT:    v_xor_b32_e32 v1, s8, v1
3107; GFX9-NEXT:    v_subrev_u32_e32 v1, s8, v1
3108; GFX9-NEXT:    v_and_b32_e32 v0, 7, v0
3109; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3110; GFX9-NEXT:    global_store_byte v2, v0, s[0:1]
3111; GFX9-NEXT:    v_and_b32_e32 v0, 7, v1
3112; GFX9-NEXT:    global_store_byte v2, v0, s[2:3]
3113; GFX9-NEXT:    s_endpgm
3114;
3115; GFX10-LABEL: sdivrem_i3:
3116; GFX10:       ; %bb.0:
3117; GFX10-NEXT:    s_load_dword s0, s[4:5], 0x10
3118; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
3119; GFX10-NEXT:    s_bfe_i32 s1, s0, 0x30008
3120; GFX10-NEXT:    s_bfe_i32 s0, s0, 0x30000
3121; GFX10-NEXT:    s_ashr_i32 s6, s1, 31
3122; GFX10-NEXT:    s_ashr_i32 s7, s0, 31
3123; GFX10-NEXT:    s_add_i32 s1, s1, s6
3124; GFX10-NEXT:    s_add_i32 s0, s0, s7
3125; GFX10-NEXT:    s_xor_b32 s1, s1, s6
3126; GFX10-NEXT:    s_xor_b32 s0, s0, s7
3127; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s1
3128; GFX10-NEXT:    s_sub_i32 s2, 0, s1
3129; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
3130; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
3131; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
3132; GFX10-NEXT:    v_mul_lo_u32 v1, s2, v0
3133; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v1
3134; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1
3135; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v0
3136; GFX10-NEXT:    v_mul_lo_u32 v1, v0, s1
3137; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v0
3138; GFX10-NEXT:    v_sub_nc_u32_e32 v1, s0, v1
3139; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s1, v1
3140; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s1, v1
3141; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
3142; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo
3143; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v0
3144; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s1, v1
3145; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s1, v1
3146; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
3147; GFX10-NEXT:    s_xor_b32 s4, s7, s6
3148; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
3149; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo
3150; GFX10-NEXT:    v_mov_b32_e32 v2, 0
3151; GFX10-NEXT:    v_xor_b32_e32 v0, s4, v0
3152; GFX10-NEXT:    v_xor_b32_e32 v1, s7, v1
3153; GFX10-NEXT:    v_subrev_nc_u32_e32 v0, s4, v0
3154; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, s7, v1
3155; GFX10-NEXT:    v_and_b32_e32 v0, 7, v0
3156; GFX10-NEXT:    v_and_b32_e32 v1, 7, v1
3157; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
3158; GFX10-NEXT:    global_store_byte v2, v0, s[0:1]
3159; GFX10-NEXT:    global_store_byte v2, v1, s[2:3]
3160; GFX10-NEXT:    s_endpgm
3161  %div = sdiv i3 %x, %y
3162  store i3 %div, i3 addrspace(1)* %out0
3163  %rem = srem i3 %x, %y
3164  store i3 %rem, i3 addrspace(1)* %out1
3165  ret void
3166}
3167
3168define amdgpu_kernel void @sdivrem_i27(i27 addrspace(1)* %out0, i27 addrspace(1)* %out1, i27 %x, i27 %y) {
3169; GFX8-LABEL: sdivrem_i27:
3170; GFX8:       ; %bb.0:
3171; GFX8-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x10
3172; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
3173; GFX8-NEXT:    s_bfe_i32 s0, s7, 0x1b0000
3174; GFX8-NEXT:    s_ashr_i32 s7, s0, 31
3175; GFX8-NEXT:    s_add_i32 s0, s0, s7
3176; GFX8-NEXT:    s_xor_b32 s8, s0, s7
3177; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s8
3178; GFX8-NEXT:    s_sub_i32 s0, 0, s8
3179; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
3180; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
3181; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0
3182; GFX8-NEXT:    v_mul_lo_u32 v1, s0, v0
3183; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
3184; GFX8-NEXT:    s_bfe_i32 s4, s6, 0x1b0000
3185; GFX8-NEXT:    s_ashr_i32 s5, s4, 31
3186; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v1
3187; GFX8-NEXT:    s_add_i32 s4, s4, s5
3188; GFX8-NEXT:    s_xor_b32 s4, s4, s5
3189; GFX8-NEXT:    s_xor_b32 s6, s5, s7
3190; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
3191; GFX8-NEXT:    v_mul_hi_u32 v2, s4, v0
3192; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
3193; GFX8-NEXT:    v_mov_b32_e32 v0, s0
3194; GFX8-NEXT:    v_mov_b32_e32 v1, s1
3195; GFX8-NEXT:    v_mul_lo_u32 v3, v2, s8
3196; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v2
3197; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s4, v3
3198; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
3199; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
3200; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s8, v3
3201; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
3202; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v2
3203; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
3204; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
3205; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s8, v3
3206; GFX8-NEXT:    v_xor_b32_e32 v2, s6, v2
3207; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
3208; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s6, v2
3209; GFX8-NEXT:    v_xor_b32_e32 v3, s5, v3
3210; GFX8-NEXT:    v_and_b32_e32 v2, 0x7ffffff, v2
3211; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, s5, v3
3212; GFX8-NEXT:    flat_store_dword v[0:1], v2
3213; GFX8-NEXT:    v_mov_b32_e32 v0, s2
3214; GFX8-NEXT:    v_and_b32_e32 v2, 0x7ffffff, v3
3215; GFX8-NEXT:    v_mov_b32_e32 v1, s3
3216; GFX8-NEXT:    flat_store_dword v[0:1], v2
3217; GFX8-NEXT:    s_endpgm
3218;
3219; GFX9-LABEL: sdivrem_i27:
3220; GFX9:       ; %bb.0:
3221; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x10
3222; GFX9-NEXT:    v_mov_b32_e32 v2, 0
3223; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3224; GFX9-NEXT:    s_bfe_i32 s1, s1, 0x1b0000
3225; GFX9-NEXT:    s_ashr_i32 s6, s1, 31
3226; GFX9-NEXT:    s_add_i32 s1, s1, s6
3227; GFX9-NEXT:    s_xor_b32 s7, s1, s6
3228; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s7
3229; GFX9-NEXT:    s_sub_i32 s1, 0, s7
3230; GFX9-NEXT:    s_bfe_i32 s0, s0, 0x1b0000
3231; GFX9-NEXT:    s_ashr_i32 s8, s0, 31
3232; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
3233; GFX9-NEXT:    s_add_i32 s0, s0, s8
3234; GFX9-NEXT:    s_xor_b32 s9, s0, s8
3235; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
3236; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
3237; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v0
3238; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
3239; GFX9-NEXT:    s_xor_b32 s4, s8, s6
3240; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
3241; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
3242; GFX9-NEXT:    v_mul_hi_u32 v0, s9, v0
3243; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s7
3244; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
3245; GFX9-NEXT:    v_sub_u32_e32 v1, s9, v1
3246; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
3247; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
3248; GFX9-NEXT:    v_subrev_u32_e32 v3, s7, v1
3249; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
3250; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0
3251; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
3252; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
3253; GFX9-NEXT:    v_subrev_u32_e32 v3, s7, v1
3254; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
3255; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v0
3256; GFX9-NEXT:    v_subrev_u32_e32 v0, s4, v0
3257; GFX9-NEXT:    v_xor_b32_e32 v1, s8, v1
3258; GFX9-NEXT:    v_subrev_u32_e32 v1, s8, v1
3259; GFX9-NEXT:    v_and_b32_e32 v0, 0x7ffffff, v0
3260; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
3261; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]
3262; GFX9-NEXT:    v_and_b32_e32 v0, 0x7ffffff, v1
3263; GFX9-NEXT:    global_store_dword v2, v0, s[2:3]
3264; GFX9-NEXT:    s_endpgm
3265;
3266; GFX10-LABEL: sdivrem_i27:
3267; GFX10:       ; %bb.0:
3268; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x10
3269; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
3270; GFX10-NEXT:    s_bfe_i32 s1, s1, 0x1b0000
3271; GFX10-NEXT:    s_bfe_i32 s0, s0, 0x1b0000
3272; GFX10-NEXT:    s_ashr_i32 s6, s1, 31
3273; GFX10-NEXT:    s_ashr_i32 s7, s0, 31
3274; GFX10-NEXT:    s_add_i32 s1, s1, s6
3275; GFX10-NEXT:    s_add_i32 s0, s0, s7
3276; GFX10-NEXT:    s_xor_b32 s1, s1, s6
3277; GFX10-NEXT:    s_xor_b32 s0, s0, s7
3278; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s1
3279; GFX10-NEXT:    s_sub_i32 s2, 0, s1
3280; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
3281; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
3282; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
3283; GFX10-NEXT:    v_mul_lo_u32 v1, s2, v0
3284; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v1
3285; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1
3286; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v0
3287; GFX10-NEXT:    v_mul_lo_u32 v1, v0, s1
3288; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v0
3289; GFX10-NEXT:    v_sub_nc_u32_e32 v1, s0, v1
3290; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s1, v1
3291; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s1, v1
3292; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
3293; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo
3294; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v0
3295; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s1, v1
3296; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s1, v1
3297; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
3298; GFX10-NEXT:    s_xor_b32 s4, s7, s6
3299; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
3300; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo
3301; GFX10-NEXT:    v_mov_b32_e32 v2, 0
3302; GFX10-NEXT:    v_xor_b32_e32 v0, s4, v0
3303; GFX10-NEXT:    v_xor_b32_e32 v1, s7, v1
3304; GFX10-NEXT:    v_subrev_nc_u32_e32 v0, s4, v0
3305; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, s7, v1
3306; GFX10-NEXT:    v_and_b32_e32 v0, 0x7ffffff, v0
3307; GFX10-NEXT:    v_and_b32_e32 v1, 0x7ffffff, v1
3308; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
3309; GFX10-NEXT:    global_store_dword v2, v0, s[0:1]
3310; GFX10-NEXT:    global_store_dword v2, v1, s[2:3]
3311; GFX10-NEXT:    s_endpgm
3312  %div = sdiv i27 %x, %y
3313  store i27 %div, i27 addrspace(1)* %out0
3314  %rem = srem i27 %x, %y
3315  store i27 %rem, i27 addrspace(1)* %out1
3316  ret void
3317}
3318