1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX7 %s 3; RUN: llc -global-isel -march=amdgcn -mcpu=gfx801 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8 %s 4; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s 5; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s 6; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s 7 8define amdgpu_ps i16 @s_mul_i16(i16 inreg %num, i16 inreg %den) { 9; GFX7-LABEL: s_mul_i16: 10; GFX7: ; %bb.0: 11; GFX7-NEXT: s_mul_i32 s0, s0, s1 12; GFX7-NEXT: ; return to shader part epilog 13; 14; GFX8-LABEL: s_mul_i16: 15; GFX8: ; %bb.0: 16; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 17; GFX8-NEXT: s_and_b32 s1, s1, 0xffff 18; GFX8-NEXT: s_mul_i32 s0, s0, s1 19; GFX8-NEXT: ; return to shader part epilog 20; 21; GFX9-LABEL: s_mul_i16: 22; GFX9: ; %bb.0: 23; GFX9-NEXT: s_and_b32 s0, s0, 0xffff 24; GFX9-NEXT: s_and_b32 s1, s1, 0xffff 25; GFX9-NEXT: s_mul_i32 s0, s0, s1 26; GFX9-NEXT: ; return to shader part epilog 27; 28; GFX10PLUS-LABEL: s_mul_i16: 29; GFX10PLUS: ; %bb.0: 30; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xffff 31; GFX10PLUS-NEXT: s_and_b32 s1, s1, 0xffff 32; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s1 33; GFX10PLUS-NEXT: ; return to shader part epilog 34 %result = mul i16 %num, %den 35 ret i16 %result 36} 37 38define i16 @v_mul_i16(i16 %num, i16 %den) { 39; GFX7-LABEL: v_mul_i16: 40; GFX7: ; %bb.0: 41; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 42; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0 43; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1 44; GFX7-NEXT: v_mul_u32_u24_e32 v0, v0, v1 45; GFX7-NEXT: s_setpc_b64 s[30:31] 46; 47; GFX8-LABEL: v_mul_i16: 48; GFX8: ; %bb.0: 49; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 50; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v1 51; GFX8-NEXT: s_setpc_b64 s[30:31] 52; 53; GFX9-LABEL: v_mul_i16: 54; GFX9: ; %bb.0: 55; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 56; GFX9-NEXT: v_mul_lo_u16_e32 v0, v0, v1 57; GFX9-NEXT: s_setpc_b64 s[30:31] 58; 59; GFX10PLUS-LABEL: v_mul_i16: 60; GFX10PLUS: ; %bb.0: 61; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 62; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 63; GFX10PLUS-NEXT: v_mul_lo_u16 v0, v0, v1 64; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 65 %result = mul i16 %num, %den 66 ret i16 %result 67} 68 69define amdgpu_ps zeroext i16 @s_mul_i16_zeroext(i16 inreg zeroext %num, i16 inreg zeroext %den) { 70; GFX7-LABEL: s_mul_i16_zeroext: 71; GFX7: ; %bb.0: 72; GFX7-NEXT: s_mul_i32 s0, s0, s1 73; GFX7-NEXT: s_and_b32 s0, s0, 0xffff 74; GFX7-NEXT: ; return to shader part epilog 75; 76; GFX8-LABEL: s_mul_i16_zeroext: 77; GFX8: ; %bb.0: 78; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 79; GFX8-NEXT: s_and_b32 s1, s1, 0xffff 80; GFX8-NEXT: s_mul_i32 s0, s0, s1 81; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 82; GFX8-NEXT: ; return to shader part epilog 83; 84; GFX9-LABEL: s_mul_i16_zeroext: 85; GFX9: ; %bb.0: 86; GFX9-NEXT: s_and_b32 s0, s0, 0xffff 87; GFX9-NEXT: s_and_b32 s1, s1, 0xffff 88; GFX9-NEXT: s_mul_i32 s0, s0, s1 89; GFX9-NEXT: s_and_b32 s0, s0, 0xffff 90; GFX9-NEXT: ; return to shader part epilog 91; 92; GFX10PLUS-LABEL: s_mul_i16_zeroext: 93; GFX10PLUS: ; %bb.0: 94; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xffff 95; GFX10PLUS-NEXT: s_and_b32 s1, s1, 0xffff 96; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s1 97; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xffff 98; GFX10PLUS-NEXT: ; return to shader part epilog 99 %result = mul i16 %num, %den 100 ret i16 %result 101} 102 103define zeroext i16 @v_mul_i16_zeroext(i16 zeroext %num, i16 zeroext %den) { 104; GFX7-LABEL: v_mul_i16_zeroext: 105; GFX7: ; %bb.0: 106; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 107; GFX7-NEXT: v_mul_u32_u24_e32 v0, v0, v1 108; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0 109; GFX7-NEXT: s_setpc_b64 s[30:31] 110; 111; GFX8-LABEL: v_mul_i16_zeroext: 112; GFX8: ; %bb.0: 113; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 114; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v1 115; GFX8-NEXT: s_setpc_b64 s[30:31] 116; 117; GFX9-LABEL: v_mul_i16_zeroext: 118; GFX9: ; %bb.0: 119; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 120; GFX9-NEXT: v_mul_lo_u16_e32 v0, v0, v1 121; GFX9-NEXT: s_setpc_b64 s[30:31] 122; 123; GFX10PLUS-LABEL: v_mul_i16_zeroext: 124; GFX10PLUS: ; %bb.0: 125; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 126; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 127; GFX10PLUS-NEXT: v_mul_lo_u16 v0, v0, v1 128; GFX10PLUS-NEXT: v_bfe_u32 v0, v0, 0, 16 129; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 130 %result = mul i16 %num, %den 131 ret i16 %result 132} 133 134define amdgpu_ps signext i16 @s_mul_i16_signext(i16 inreg signext %num, i16 inreg signext %den) { 135; GFX7-LABEL: s_mul_i16_signext: 136; GFX7: ; %bb.0: 137; GFX7-NEXT: s_mul_i32 s0, s0, s1 138; GFX7-NEXT: s_sext_i32_i16 s0, s0 139; GFX7-NEXT: ; return to shader part epilog 140; 141; GFX8-LABEL: s_mul_i16_signext: 142; GFX8: ; %bb.0: 143; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 144; GFX8-NEXT: s_and_b32 s1, s1, 0xffff 145; GFX8-NEXT: s_mul_i32 s0, s0, s1 146; GFX8-NEXT: s_sext_i32_i16 s0, s0 147; GFX8-NEXT: ; return to shader part epilog 148; 149; GFX9-LABEL: s_mul_i16_signext: 150; GFX9: ; %bb.0: 151; GFX9-NEXT: s_and_b32 s0, s0, 0xffff 152; GFX9-NEXT: s_and_b32 s1, s1, 0xffff 153; GFX9-NEXT: s_mul_i32 s0, s0, s1 154; GFX9-NEXT: s_sext_i32_i16 s0, s0 155; GFX9-NEXT: ; return to shader part epilog 156; 157; GFX10PLUS-LABEL: s_mul_i16_signext: 158; GFX10PLUS: ; %bb.0: 159; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xffff 160; GFX10PLUS-NEXT: s_and_b32 s1, s1, 0xffff 161; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s1 162; GFX10PLUS-NEXT: s_sext_i32_i16 s0, s0 163; GFX10PLUS-NEXT: ; return to shader part epilog 164 %result = mul i16 %num, %den 165 ret i16 %result 166} 167 168define signext i16 @v_mul_i16_signext(i16 signext %num, i16 signext %den) { 169; GFX7-LABEL: v_mul_i16_signext: 170; GFX7: ; %bb.0: 171; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 172; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0 173; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1 174; GFX7-NEXT: v_mul_u32_u24_e32 v0, v0, v1 175; GFX7-NEXT: v_bfe_i32 v0, v0, 0, 16 176; GFX7-NEXT: s_setpc_b64 s[30:31] 177; 178; GFX8-LABEL: v_mul_i16_signext: 179; GFX8: ; %bb.0: 180; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 181; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v1 182; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 16 183; GFX8-NEXT: s_setpc_b64 s[30:31] 184; 185; GFX9-LABEL: v_mul_i16_signext: 186; GFX9: ; %bb.0: 187; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 188; GFX9-NEXT: v_mul_lo_u16_e32 v0, v0, v1 189; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16 190; GFX9-NEXT: s_setpc_b64 s[30:31] 191; 192; GFX10PLUS-LABEL: v_mul_i16_signext: 193; GFX10PLUS: ; %bb.0: 194; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 195; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 196; GFX10PLUS-NEXT: v_mul_lo_u16 v0, v0, v1 197; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 16 198; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 199 %result = mul i16 %num, %den 200 ret i16 %result 201} 202 203define amdgpu_ps i32 @s_mul_i32(i32 inreg %num, i32 inreg %den) { 204; GCN-LABEL: s_mul_i32: 205; GCN: ; %bb.0: 206; GCN-NEXT: s_mul_i32 s0, s0, s1 207; GCN-NEXT: ; return to shader part epilog 208; 209; GFX10PLUS-LABEL: s_mul_i32: 210; GFX10PLUS: ; %bb.0: 211; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s1 212; GFX10PLUS-NEXT: ; return to shader part epilog 213 %result = mul i32 %num, %den 214 ret i32 %result 215} 216 217define i32 @v_mul_i32(i32 %num, i32 %den) { 218; GCN-LABEL: v_mul_i32: 219; GCN: ; %bb.0: 220; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 221; GCN-NEXT: v_mul_lo_u32 v0, v0, v1 222; GCN-NEXT: s_setpc_b64 s[30:31] 223; 224; GFX10PLUS-LABEL: v_mul_i32: 225; GFX10PLUS: ; %bb.0: 226; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 227; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 228; GFX10PLUS-NEXT: v_mul_lo_u32 v0, v0, v1 229; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 230 %result = mul i32 %num, %den 231 ret i32 %result 232} 233 234define amdgpu_ps <2 x i32> @s_mul_v2i32(<2 x i32> inreg %num, <2 x i32> inreg %den) { 235; GCN-LABEL: s_mul_v2i32: 236; GCN: ; %bb.0: 237; GCN-NEXT: s_mul_i32 s0, s0, s2 238; GCN-NEXT: s_mul_i32 s1, s1, s3 239; GCN-NEXT: ; return to shader part epilog 240; 241; GFX10PLUS-LABEL: s_mul_v2i32: 242; GFX10PLUS: ; %bb.0: 243; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s2 244; GFX10PLUS-NEXT: s_mul_i32 s1, s1, s3 245; GFX10PLUS-NEXT: ; return to shader part epilog 246 %result = mul <2 x i32> %num, %den 247 ret <2 x i32> %result 248} 249 250define <2 x i32> @v_mul_v2i32(<2 x i32> %num, <2 x i32> %den) { 251; GCN-LABEL: v_mul_v2i32: 252; GCN: ; %bb.0: 253; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 254; GCN-NEXT: v_mul_lo_u32 v0, v0, v2 255; GCN-NEXT: v_mul_lo_u32 v1, v1, v3 256; GCN-NEXT: s_setpc_b64 s[30:31] 257; 258; GFX10PLUS-LABEL: v_mul_v2i32: 259; GFX10PLUS: ; %bb.0: 260; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 261; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 262; GFX10PLUS-NEXT: v_mul_lo_u32 v0, v0, v2 263; GFX10PLUS-NEXT: v_mul_lo_u32 v1, v1, v3 264; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 265 %result = mul <2 x i32> %num, %den 266 ret <2 x i32> %result 267} 268 269define amdgpu_cs i33 @s_mul_i33(i33 inreg %num, i33 inreg %den) { 270; GFX7-LABEL: s_mul_i33: 271; GFX7: ; %bb.0: 272; GFX7-NEXT: v_mov_b32_e32 v0, s2 273; GFX7-NEXT: v_mul_hi_u32 v0, s0, v0 274; GFX7-NEXT: s_mul_i32 s4, s0, s2 275; GFX7-NEXT: s_mul_i32 s0, s0, s3 276; GFX7-NEXT: s_mul_i32 s1, s1, s2 277; GFX7-NEXT: v_readfirstlane_b32 s5, v0 278; GFX7-NEXT: s_add_u32 s0, s0, s5 279; GFX7-NEXT: s_add_u32 s1, s1, s0 280; GFX7-NEXT: s_mov_b32 s0, s4 281; GFX7-NEXT: ; return to shader part epilog 282; 283; GFX8-LABEL: s_mul_i33: 284; GFX8: ; %bb.0: 285; GFX8-NEXT: v_mov_b32_e32 v0, s2 286; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0 287; GFX8-NEXT: s_mul_i32 s4, s0, s2 288; GFX8-NEXT: s_mul_i32 s0, s0, s3 289; GFX8-NEXT: s_mul_i32 s1, s1, s2 290; GFX8-NEXT: v_readfirstlane_b32 s5, v0 291; GFX8-NEXT: s_add_u32 s0, s0, s5 292; GFX8-NEXT: s_add_u32 s1, s1, s0 293; GFX8-NEXT: s_mov_b32 s0, s4 294; GFX8-NEXT: ; return to shader part epilog 295; 296; GFX9-LABEL: s_mul_i33: 297; GFX9: ; %bb.0: 298; GFX9-NEXT: s_mul_i32 s4, s0, s2 299; GFX9-NEXT: s_mul_hi_u32 s5, s0, s2 300; GFX9-NEXT: s_mul_i32 s0, s0, s3 301; GFX9-NEXT: s_add_u32 s0, s0, s5 302; GFX9-NEXT: s_mul_i32 s1, s1, s2 303; GFX9-NEXT: s_add_u32 s1, s1, s0 304; GFX9-NEXT: s_mov_b32 s0, s4 305; GFX9-NEXT: ; return to shader part epilog 306; 307; GFX10PLUS-LABEL: s_mul_i33: 308; GFX10PLUS: ; %bb.0: 309; GFX10PLUS-NEXT: s_mul_hi_u32 s4, s0, s2 310; GFX10PLUS-NEXT: s_mul_i32 s3, s0, s3 311; GFX10PLUS-NEXT: s_mul_i32 s1, s1, s2 312; GFX10PLUS-NEXT: s_add_i32 s3, s4, s3 313; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s2 314; GFX10PLUS-NEXT: s_add_i32 s1, s3, s1 315; GFX10PLUS-NEXT: ; return to shader part epilog 316 %result = mul i33 %num, %den 317 ret i33 %result 318} 319 320define amdgpu_ps i64 @s_mul_i64(i64 inreg %num, i64 inreg %den) { 321; GFX7-LABEL: s_mul_i64: 322; GFX7: ; %bb.0: 323; GFX7-NEXT: v_mov_b32_e32 v0, s2 324; GFX7-NEXT: v_mul_hi_u32 v0, s0, v0 325; GFX7-NEXT: s_mul_i32 s4, s0, s2 326; GFX7-NEXT: s_mul_i32 s0, s0, s3 327; GFX7-NEXT: s_mul_i32 s1, s1, s2 328; GFX7-NEXT: v_readfirstlane_b32 s5, v0 329; GFX7-NEXT: s_add_u32 s0, s0, s5 330; GFX7-NEXT: s_add_u32 s1, s1, s0 331; GFX7-NEXT: s_mov_b32 s0, s4 332; GFX7-NEXT: ; return to shader part epilog 333; 334; GFX8-LABEL: s_mul_i64: 335; GFX8: ; %bb.0: 336; GFX8-NEXT: v_mov_b32_e32 v0, s2 337; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0 338; GFX8-NEXT: s_mul_i32 s4, s0, s2 339; GFX8-NEXT: s_mul_i32 s0, s0, s3 340; GFX8-NEXT: s_mul_i32 s1, s1, s2 341; GFX8-NEXT: v_readfirstlane_b32 s5, v0 342; GFX8-NEXT: s_add_u32 s0, s0, s5 343; GFX8-NEXT: s_add_u32 s1, s1, s0 344; GFX8-NEXT: s_mov_b32 s0, s4 345; GFX8-NEXT: ; return to shader part epilog 346; 347; GFX9-LABEL: s_mul_i64: 348; GFX9: ; %bb.0: 349; GFX9-NEXT: s_mul_i32 s4, s0, s2 350; GFX9-NEXT: s_mul_hi_u32 s5, s0, s2 351; GFX9-NEXT: s_mul_i32 s0, s0, s3 352; GFX9-NEXT: s_add_u32 s0, s0, s5 353; GFX9-NEXT: s_mul_i32 s1, s1, s2 354; GFX9-NEXT: s_add_u32 s1, s1, s0 355; GFX9-NEXT: s_mov_b32 s0, s4 356; GFX9-NEXT: ; return to shader part epilog 357; 358; GFX10PLUS-LABEL: s_mul_i64: 359; GFX10PLUS: ; %bb.0: 360; GFX10PLUS-NEXT: s_mul_hi_u32 s4, s0, s2 361; GFX10PLUS-NEXT: s_mul_i32 s3, s0, s3 362; GFX10PLUS-NEXT: s_mul_i32 s1, s1, s2 363; GFX10PLUS-NEXT: s_add_i32 s3, s4, s3 364; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s2 365; GFX10PLUS-NEXT: s_add_i32 s1, s3, s1 366; GFX10PLUS-NEXT: ; return to shader part epilog 367 %result = mul i64 %num, %den 368 ret i64 %result 369} 370 371define i64 @v_mul_i64(i64 %num, i64 %den) { 372; GCN-LABEL: v_mul_i64: 373; GCN: ; %bb.0: 374; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 375; GCN-NEXT: v_mov_b32_e32 v4, v0 376; GCN-NEXT: v_mov_b32_e32 v5, v1 377; GCN-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v2, 0 378; GCN-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v4, v3, v[1:2] 379; GCN-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v5, v2, v[3:4] 380; GCN-NEXT: s_setpc_b64 s[30:31] 381; 382; GFX10-LABEL: v_mul_i64: 383; GFX10: ; %bb.0: 384; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 385; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 386; GFX10-NEXT: v_mov_b32_e32 v4, v0 387; GFX10-NEXT: v_mov_b32_e32 v5, v1 388; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v4, v2, 0 389; GFX10-NEXT: v_mul_lo_u32 v3, v4, v3 390; GFX10-NEXT: v_mul_lo_u32 v2, v5, v2 391; GFX10-NEXT: v_add3_u32 v1, v1, v3, v2 392; GFX10-NEXT: s_setpc_b64 s[30:31] 393; 394; GFX11-LABEL: v_mul_i64: 395; GFX11: ; %bb.0: 396; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 397; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 398; GFX11-NEXT: v_dual_mov_b32 v4, v0 :: v_dual_mov_b32 v5, v1 399; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v4, v2, 0 400; GFX11-NEXT: v_mul_lo_u32 v3, v4, v3 401; GFX11-NEXT: v_mul_lo_u32 v2, v5, v2 402; GFX11-NEXT: v_add3_u32 v1, v1, v3, v2 403; GFX11-NEXT: s_setpc_b64 s[30:31] 404 %result = mul i64 %num, %den 405 ret i64 %result 406} 407 408define amdgpu_ps <3 x i32> @s_mul_i96(i96 inreg %num, i96 inreg %den) { 409; GFX7-LABEL: s_mul_i96: 410; GFX7: ; %bb.0: 411; GFX7-NEXT: v_mov_b32_e32 v0, s3 412; GFX7-NEXT: v_mul_hi_u32 v0, s0, v0 413; GFX7-NEXT: v_mov_b32_e32 v1, s4 414; GFX7-NEXT: v_mul_hi_u32 v1, s0, v1 415; GFX7-NEXT: s_mul_i32 s5, s0, s5 416; GFX7-NEXT: v_readfirstlane_b32 s7, v0 417; GFX7-NEXT: s_mul_i32 s8, s1, s4 418; GFX7-NEXT: v_mov_b32_e32 v0, s1 419; GFX7-NEXT: s_add_u32 s5, s8, s5 420; GFX7-NEXT: s_mul_i32 s2, s2, s3 421; GFX7-NEXT: v_mul_hi_u32 v0, v0, s3 422; GFX7-NEXT: s_mul_i32 s6, s0, s3 423; GFX7-NEXT: s_add_u32 s2, s2, s5 424; GFX7-NEXT: s_mul_i32 s0, s0, s4 425; GFX7-NEXT: v_readfirstlane_b32 s4, v1 426; GFX7-NEXT: s_add_u32 s0, s0, s7 427; GFX7-NEXT: s_addc_u32 s2, s4, s2 428; GFX7-NEXT: s_mul_i32 s1, s1, s3 429; GFX7-NEXT: v_readfirstlane_b32 s3, v0 430; GFX7-NEXT: s_add_u32 s1, s1, s0 431; GFX7-NEXT: s_addc_u32 s2, s3, s2 432; GFX7-NEXT: s_mov_b32 s0, s6 433; GFX7-NEXT: ; return to shader part epilog 434; 435; GFX8-LABEL: s_mul_i96: 436; GFX8: ; %bb.0: 437; GFX8-NEXT: v_mov_b32_e32 v0, s3 438; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0 439; GFX8-NEXT: v_mov_b32_e32 v1, s4 440; GFX8-NEXT: v_mul_hi_u32 v1, s0, v1 441; GFX8-NEXT: s_mul_i32 s5, s0, s5 442; GFX8-NEXT: v_readfirstlane_b32 s7, v0 443; GFX8-NEXT: s_mul_i32 s8, s1, s4 444; GFX8-NEXT: v_mov_b32_e32 v0, s1 445; GFX8-NEXT: s_add_u32 s5, s8, s5 446; GFX8-NEXT: s_mul_i32 s2, s2, s3 447; GFX8-NEXT: v_mul_hi_u32 v0, v0, s3 448; GFX8-NEXT: s_mul_i32 s6, s0, s3 449; GFX8-NEXT: s_add_u32 s2, s2, s5 450; GFX8-NEXT: s_mul_i32 s0, s0, s4 451; GFX8-NEXT: v_readfirstlane_b32 s4, v1 452; GFX8-NEXT: s_add_u32 s0, s0, s7 453; GFX8-NEXT: s_addc_u32 s2, s4, s2 454; GFX8-NEXT: s_mul_i32 s1, s1, s3 455; GFX8-NEXT: v_readfirstlane_b32 s3, v0 456; GFX8-NEXT: s_add_u32 s1, s1, s0 457; GFX8-NEXT: s_addc_u32 s2, s3, s2 458; GFX8-NEXT: s_mov_b32 s0, s6 459; GFX8-NEXT: ; return to shader part epilog 460; 461; GFX9-LABEL: s_mul_i96: 462; GFX9: ; %bb.0: 463; GFX9-NEXT: s_mul_i32 s5, s0, s5 464; GFX9-NEXT: s_mul_i32 s8, s1, s4 465; GFX9-NEXT: s_add_u32 s5, s8, s5 466; GFX9-NEXT: s_mul_i32 s2, s2, s3 467; GFX9-NEXT: s_mul_hi_u32 s7, s0, s3 468; GFX9-NEXT: s_add_u32 s2, s2, s5 469; GFX9-NEXT: s_mul_i32 s5, s0, s4 470; GFX9-NEXT: s_mul_i32 s6, s0, s3 471; GFX9-NEXT: s_mul_hi_u32 s0, s0, s4 472; GFX9-NEXT: s_add_u32 s4, s5, s7 473; GFX9-NEXT: s_addc_u32 s0, s0, s2 474; GFX9-NEXT: s_mul_i32 s2, s1, s3 475; GFX9-NEXT: s_mul_hi_u32 s3, s1, s3 476; GFX9-NEXT: s_add_u32 s1, s2, s4 477; GFX9-NEXT: s_addc_u32 s2, s3, s0 478; GFX9-NEXT: s_mov_b32 s0, s6 479; GFX9-NEXT: ; return to shader part epilog 480; 481; GFX10PLUS-LABEL: s_mul_i96: 482; GFX10PLUS: ; %bb.0: 483; GFX10PLUS-NEXT: s_mul_i32 s6, s0, s5 484; GFX10PLUS-NEXT: s_mul_i32 s7, s1, s4 485; GFX10PLUS-NEXT: s_mul_i32 s2, s2, s3 486; GFX10PLUS-NEXT: s_add_i32 s6, s6, s7 487; GFX10PLUS-NEXT: s_mul_hi_u32 s7, s0, s3 488; GFX10PLUS-NEXT: s_add_i32 s6, s6, s2 489; GFX10PLUS-NEXT: s_mul_i32 s2, s0, s4 490; GFX10PLUS-NEXT: s_mul_i32 s5, s0, s3 491; GFX10PLUS-NEXT: s_mul_hi_u32 s0, s0, s4 492; GFX10PLUS-NEXT: s_add_u32 s2, s2, s7 493; GFX10PLUS-NEXT: s_mul_i32 s4, s1, s3 494; GFX10PLUS-NEXT: s_addc_u32 s0, s0, s6 495; GFX10PLUS-NEXT: s_mul_hi_u32 s3, s1, s3 496; GFX10PLUS-NEXT: s_add_u32 s1, s4, s2 497; GFX10PLUS-NEXT: s_addc_u32 s2, s3, s0 498; GFX10PLUS-NEXT: s_mov_b32 s0, s5 499; GFX10PLUS-NEXT: ; return to shader part epilog 500 %result = mul i96 %num, %den 501 %cast = bitcast i96 %result to <3 x i32> 502 ret <3 x i32> %cast 503} 504 505define i96 @v_mul_i96(i96 %num, i96 %den) { 506; GCN-LABEL: v_mul_i96: 507; GCN: ; %bb.0: 508; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 509; GCN-NEXT: v_mov_b32_e32 v6, v0 510; GCN-NEXT: v_mov_b32_e32 v7, v1 511; GCN-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v5, 0 512; GCN-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v7, v4, v[0:1] 513; GCN-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v3, 0 514; GCN-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v2, v3, v[8:9] 515; GCN-NEXT: v_mov_b32_e32 v2, v8 516; GCN-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v6, v4, v[1:2] 517; GCN-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v7, v3, v[1:2] 518; GCN-NEXT: s_setpc_b64 s[30:31] 519; 520; GFX10-LABEL: v_mul_i96: 521; GFX10: ; %bb.0: 522; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 523; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 524; GFX10-NEXT: v_mov_b32_e32 v6, v0 525; GFX10-NEXT: v_mov_b32_e32 v7, v1 526; GFX10-NEXT: v_mul_lo_u32 v2, v2, v3 527; GFX10-NEXT: v_mul_lo_u32 v5, v6, v5 528; GFX10-NEXT: v_mul_lo_u32 v8, v7, v4 529; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v6, v3, 0 530; GFX10-NEXT: v_add3_u32 v2, v5, v8, v2 531; GFX10-NEXT: v_mad_u64_u32 v[1:2], s4, v6, v4, v[1:2] 532; GFX10-NEXT: v_mad_u64_u32 v[1:2], s4, v7, v3, v[1:2] 533; GFX10-NEXT: s_setpc_b64 s[30:31] 534; 535; GFX11-LABEL: v_mul_i96: 536; GFX11: ; %bb.0: 537; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 538; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 539; GFX11-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v7, v1 540; GFX11-NEXT: v_mul_lo_u32 v2, v2, v3 541; GFX11-NEXT: v_mul_lo_u32 v5, v6, v5 542; GFX11-NEXT: v_mul_lo_u32 v8, v7, v4 543; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v6, v3, 0 544; GFX11-NEXT: v_add3_u32 v2, v5, v8, v2 545; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, v6, v4, v[1:2] 546; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, v7, v3, v[1:2] 547; GFX11-NEXT: s_setpc_b64 s[30:31] 548 %result = mul i96 %num, %den 549 ret i96 %result 550} 551 552define amdgpu_ps <4 x i32> @s_mul_i128(i128 inreg %num, i128 inreg %den) { 553; GFX7-LABEL: s_mul_i128: 554; GFX7: ; %bb.0: 555; GFX7-NEXT: v_mov_b32_e32 v0, s4 556; GFX7-NEXT: v_mul_hi_u32 v0, s0, v0 557; GFX7-NEXT: v_mov_b32_e32 v1, s5 558; GFX7-NEXT: v_mul_hi_u32 v2, s1, v1 559; GFX7-NEXT: s_mul_i32 s10, s0, s6 560; GFX7-NEXT: v_readfirstlane_b32 s9, v0 561; GFX7-NEXT: v_mov_b32_e32 v0, s6 562; GFX7-NEXT: v_mul_hi_u32 v0, s0, v0 563; GFX7-NEXT: v_readfirstlane_b32 s13, v2 564; GFX7-NEXT: v_mov_b32_e32 v2, s2 565; GFX7-NEXT: v_mul_hi_u32 v2, v2, s4 566; GFX7-NEXT: s_mul_i32 s12, s1, s5 567; GFX7-NEXT: v_readfirstlane_b32 s11, v0 568; GFX7-NEXT: s_add_u32 s10, s12, s10 569; GFX7-NEXT: v_mul_hi_u32 v1, s0, v1 570; GFX7-NEXT: v_mov_b32_e32 v0, s1 571; GFX7-NEXT: s_addc_u32 s11, s13, s11 572; GFX7-NEXT: s_mul_i32 s12, s2, s4 573; GFX7-NEXT: v_readfirstlane_b32 s13, v2 574; GFX7-NEXT: s_add_u32 s10, s12, s10 575; GFX7-NEXT: v_mul_hi_u32 v0, v0, s4 576; GFX7-NEXT: s_addc_u32 s11, s13, s11 577; GFX7-NEXT: s_mul_i32 s12, s0, s5 578; GFX7-NEXT: v_readfirstlane_b32 s13, v1 579; GFX7-NEXT: s_add_u32 s9, s12, s9 580; GFX7-NEXT: s_addc_u32 s10, s13, s10 581; GFX7-NEXT: s_mul_i32 s13, s1, s4 582; GFX7-NEXT: s_cselect_b32 s12, 1, 0 583; GFX7-NEXT: v_readfirstlane_b32 s14, v0 584; GFX7-NEXT: s_add_u32 s9, s13, s9 585; GFX7-NEXT: s_mul_i32 s8, s0, s4 586; GFX7-NEXT: s_addc_u32 s10, s14, s10 587; GFX7-NEXT: s_mul_i32 s0, s0, s7 588; GFX7-NEXT: s_addc_u32 s0, s11, s0 589; GFX7-NEXT: s_mul_i32 s1, s1, s6 590; GFX7-NEXT: s_cmp_lg_u32 s12, 0 591; GFX7-NEXT: s_addc_u32 s0, s0, s1 592; GFX7-NEXT: s_mul_i32 s2, s2, s5 593; GFX7-NEXT: s_add_u32 s0, s2, s0 594; GFX7-NEXT: s_mul_i32 s3, s3, s4 595; GFX7-NEXT: s_add_u32 s3, s3, s0 596; GFX7-NEXT: s_mov_b32 s0, s8 597; GFX7-NEXT: s_mov_b32 s1, s9 598; GFX7-NEXT: s_mov_b32 s2, s10 599; GFX7-NEXT: ; return to shader part epilog 600; 601; GFX8-LABEL: s_mul_i128: 602; GFX8: ; %bb.0: 603; GFX8-NEXT: v_mov_b32_e32 v0, s4 604; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0 605; GFX8-NEXT: v_mov_b32_e32 v1, s5 606; GFX8-NEXT: v_mul_hi_u32 v2, s1, v1 607; GFX8-NEXT: s_mul_i32 s10, s0, s6 608; GFX8-NEXT: v_readfirstlane_b32 s9, v0 609; GFX8-NEXT: v_mov_b32_e32 v0, s6 610; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0 611; GFX8-NEXT: v_readfirstlane_b32 s13, v2 612; GFX8-NEXT: v_mov_b32_e32 v2, s2 613; GFX8-NEXT: v_mul_hi_u32 v2, v2, s4 614; GFX8-NEXT: s_mul_i32 s12, s1, s5 615; GFX8-NEXT: v_readfirstlane_b32 s11, v0 616; GFX8-NEXT: s_add_u32 s10, s12, s10 617; GFX8-NEXT: v_mul_hi_u32 v1, s0, v1 618; GFX8-NEXT: v_mov_b32_e32 v0, s1 619; GFX8-NEXT: s_addc_u32 s11, s13, s11 620; GFX8-NEXT: s_mul_i32 s12, s2, s4 621; GFX8-NEXT: v_readfirstlane_b32 s13, v2 622; GFX8-NEXT: s_add_u32 s10, s12, s10 623; GFX8-NEXT: v_mul_hi_u32 v0, v0, s4 624; GFX8-NEXT: s_addc_u32 s11, s13, s11 625; GFX8-NEXT: s_mul_i32 s12, s0, s5 626; GFX8-NEXT: v_readfirstlane_b32 s13, v1 627; GFX8-NEXT: s_add_u32 s9, s12, s9 628; GFX8-NEXT: s_addc_u32 s10, s13, s10 629; GFX8-NEXT: s_mul_i32 s13, s1, s4 630; GFX8-NEXT: s_cselect_b32 s12, 1, 0 631; GFX8-NEXT: v_readfirstlane_b32 s14, v0 632; GFX8-NEXT: s_add_u32 s9, s13, s9 633; GFX8-NEXT: s_mul_i32 s8, s0, s4 634; GFX8-NEXT: s_addc_u32 s10, s14, s10 635; GFX8-NEXT: s_mul_i32 s0, s0, s7 636; GFX8-NEXT: s_addc_u32 s0, s11, s0 637; GFX8-NEXT: s_mul_i32 s1, s1, s6 638; GFX8-NEXT: s_cmp_lg_u32 s12, 0 639; GFX8-NEXT: s_addc_u32 s0, s0, s1 640; GFX8-NEXT: s_mul_i32 s2, s2, s5 641; GFX8-NEXT: s_add_u32 s0, s2, s0 642; GFX8-NEXT: s_mul_i32 s3, s3, s4 643; GFX8-NEXT: s_add_u32 s3, s3, s0 644; GFX8-NEXT: s_mov_b32 s0, s8 645; GFX8-NEXT: s_mov_b32 s1, s9 646; GFX8-NEXT: s_mov_b32 s2, s10 647; GFX8-NEXT: ; return to shader part epilog 648; 649; GFX9-LABEL: s_mul_i128: 650; GFX9: ; %bb.0: 651; GFX9-NEXT: s_mul_i32 s10, s0, s6 652; GFX9-NEXT: s_mul_i32 s12, s1, s5 653; GFX9-NEXT: s_mul_hi_u32 s11, s0, s6 654; GFX9-NEXT: s_mul_hi_u32 s13, s1, s5 655; GFX9-NEXT: s_add_u32 s10, s12, s10 656; GFX9-NEXT: s_addc_u32 s11, s13, s11 657; GFX9-NEXT: s_mul_i32 s12, s2, s4 658; GFX9-NEXT: s_mul_hi_u32 s13, s2, s4 659; GFX9-NEXT: s_add_u32 s10, s12, s10 660; GFX9-NEXT: s_mul_hi_u32 s9, s0, s4 661; GFX9-NEXT: s_addc_u32 s11, s13, s11 662; GFX9-NEXT: s_mul_i32 s12, s0, s5 663; GFX9-NEXT: s_mul_hi_u32 s13, s0, s5 664; GFX9-NEXT: s_add_u32 s9, s12, s9 665; GFX9-NEXT: s_addc_u32 s10, s13, s10 666; GFX9-NEXT: s_mul_i32 s13, s1, s4 667; GFX9-NEXT: s_cselect_b32 s12, 1, 0 668; GFX9-NEXT: s_mul_hi_u32 s14, s1, s4 669; GFX9-NEXT: s_add_u32 s9, s13, s9 670; GFX9-NEXT: s_mul_i32 s8, s0, s4 671; GFX9-NEXT: s_addc_u32 s10, s14, s10 672; GFX9-NEXT: s_mul_i32 s0, s0, s7 673; GFX9-NEXT: s_addc_u32 s0, s11, s0 674; GFX9-NEXT: s_mul_i32 s1, s1, s6 675; GFX9-NEXT: s_cmp_lg_u32 s12, 0 676; GFX9-NEXT: s_addc_u32 s0, s0, s1 677; GFX9-NEXT: s_mul_i32 s2, s2, s5 678; GFX9-NEXT: s_add_u32 s0, s2, s0 679; GFX9-NEXT: s_mul_i32 s3, s3, s4 680; GFX9-NEXT: s_add_u32 s3, s3, s0 681; GFX9-NEXT: s_mov_b32 s0, s8 682; GFX9-NEXT: s_mov_b32 s1, s9 683; GFX9-NEXT: s_mov_b32 s2, s10 684; GFX9-NEXT: ; return to shader part epilog 685; 686; GFX10PLUS-LABEL: s_mul_i128: 687; GFX10PLUS: ; %bb.0: 688; GFX10PLUS-NEXT: s_mul_i32 s9, s0, s6 689; GFX10PLUS-NEXT: s_mul_i32 s11, s1, s5 690; GFX10PLUS-NEXT: s_mul_hi_u32 s10, s0, s6 691; GFX10PLUS-NEXT: s_mul_hi_u32 s12, s1, s5 692; GFX10PLUS-NEXT: s_add_u32 s9, s11, s9 693; GFX10PLUS-NEXT: s_mul_i32 s11, s2, s4 694; GFX10PLUS-NEXT: s_addc_u32 s10, s12, s10 695; GFX10PLUS-NEXT: s_mul_hi_u32 s12, s2, s4 696; GFX10PLUS-NEXT: s_mul_hi_u32 s8, s0, s4 697; GFX10PLUS-NEXT: s_add_u32 s9, s11, s9 698; GFX10PLUS-NEXT: s_mul_i32 s11, s0, s5 699; GFX10PLUS-NEXT: s_addc_u32 s10, s12, s10 700; GFX10PLUS-NEXT: s_mul_hi_u32 s12, s0, s5 701; GFX10PLUS-NEXT: s_add_u32 s8, s11, s8 702; GFX10PLUS-NEXT: s_addc_u32 s9, s12, s9 703; GFX10PLUS-NEXT: s_mul_i32 s12, s1, s4 704; GFX10PLUS-NEXT: s_mul_hi_u32 s13, s1, s4 705; GFX10PLUS-NEXT: s_cselect_b32 s11, 1, 0 706; GFX10PLUS-NEXT: s_add_u32 s8, s12, s8 707; GFX10PLUS-NEXT: s_mul_i32 s12, s0, s7 708; GFX10PLUS-NEXT: s_addc_u32 s7, s13, s9 709; GFX10PLUS-NEXT: s_addc_u32 s9, s10, s12 710; GFX10PLUS-NEXT: s_mul_i32 s1, s1, s6 711; GFX10PLUS-NEXT: s_cmp_lg_u32 s11, 0 712; GFX10PLUS-NEXT: s_mul_i32 s2, s2, s5 713; GFX10PLUS-NEXT: s_addc_u32 s1, s9, s1 714; GFX10PLUS-NEXT: s_mul_i32 s3, s3, s4 715; GFX10PLUS-NEXT: s_add_i32 s1, s1, s2 716; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s4 717; GFX10PLUS-NEXT: s_add_i32 s3, s1, s3 718; GFX10PLUS-NEXT: s_mov_b32 s1, s8 719; GFX10PLUS-NEXT: s_mov_b32 s2, s7 720; GFX10PLUS-NEXT: ; return to shader part epilog 721 %result = mul i128 %num, %den 722 %cast = bitcast i128 %result to <4 x i32> 723 ret <4 x i32> %cast 724} 725 726define i128 @v_mul_i128(i128 %num, i128 %den) { 727; GFX7-LABEL: v_mul_i128: 728; GFX7: ; %bb.0: 729; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 730; GFX7-NEXT: v_mov_b32_e32 v8, v0 731; GFX7-NEXT: v_mov_b32_e32 v9, v1 732; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v6, 0 733; GFX7-NEXT: v_mov_b32_e32 v10, v2 734; GFX7-NEXT: v_mul_lo_u32 v7, v8, v7 735; GFX7-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v9, v5, v[0:1] 736; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v4, 0 737; GFX7-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v10, v4, v[11:12] 738; GFX7-NEXT: v_mul_lo_u32 v6, v9, v6 739; GFX7-NEXT: v_mov_b32_e32 v2, v11 740; GFX7-NEXT: v_mad_u64_u32 v[1:2], vcc, v8, v5, v[1:2] 741; GFX7-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v9, v4, v[1:2] 742; GFX7-NEXT: v_addc_u32_e64 v7, s[4:5], v12, v7, s[4:5] 743; GFX7-NEXT: v_addc_u32_e32 v6, vcc, v7, v6, vcc 744; GFX7-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v10, v5, v[6:7] 745; GFX7-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v3, v4, v[5:6] 746; GFX7-NEXT: s_setpc_b64 s[30:31] 747; 748; GFX8-LABEL: v_mul_i128: 749; GFX8: ; %bb.0: 750; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 751; GFX8-NEXT: v_mov_b32_e32 v8, v0 752; GFX8-NEXT: v_mov_b32_e32 v9, v1 753; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v6, 0 754; GFX8-NEXT: v_mov_b32_e32 v10, v2 755; GFX8-NEXT: v_mul_lo_u32 v7, v8, v7 756; GFX8-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v9, v5, v[0:1] 757; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v4, 0 758; GFX8-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v10, v4, v[11:12] 759; GFX8-NEXT: v_mul_lo_u32 v6, v9, v6 760; GFX8-NEXT: v_mov_b32_e32 v2, v11 761; GFX8-NEXT: v_mad_u64_u32 v[1:2], vcc, v8, v5, v[1:2] 762; GFX8-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v9, v4, v[1:2] 763; GFX8-NEXT: v_addc_u32_e64 v7, s[4:5], v12, v7, s[4:5] 764; GFX8-NEXT: v_addc_u32_e32 v6, vcc, v7, v6, vcc 765; GFX8-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v10, v5, v[6:7] 766; GFX8-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v3, v4, v[5:6] 767; GFX8-NEXT: s_setpc_b64 s[30:31] 768; 769; GFX9-LABEL: v_mul_i128: 770; GFX9: ; %bb.0: 771; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 772; GFX9-NEXT: v_mov_b32_e32 v8, v0 773; GFX9-NEXT: v_mov_b32_e32 v9, v1 774; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v6, 0 775; GFX9-NEXT: v_mov_b32_e32 v10, v2 776; GFX9-NEXT: v_mul_lo_u32 v7, v8, v7 777; GFX9-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v9, v5, v[0:1] 778; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v4, 0 779; GFX9-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v10, v4, v[11:12] 780; GFX9-NEXT: v_mul_lo_u32 v6, v9, v6 781; GFX9-NEXT: v_mov_b32_e32 v2, v11 782; GFX9-NEXT: v_mad_u64_u32 v[1:2], vcc, v8, v5, v[1:2] 783; GFX9-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v9, v4, v[1:2] 784; GFX9-NEXT: v_addc_co_u32_e64 v7, s[4:5], v12, v7, s[4:5] 785; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v6, vcc 786; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v10, v5, v[6:7] 787; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v3, v4, v[5:6] 788; GFX9-NEXT: s_setpc_b64 s[30:31] 789; 790; GFX10-LABEL: v_mul_i128: 791; GFX10: ; %bb.0: 792; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 793; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 794; GFX10-NEXT: v_mov_b32_e32 v8, v0 795; GFX10-NEXT: v_mov_b32_e32 v9, v1 796; GFX10-NEXT: v_mov_b32_e32 v10, v2 797; GFX10-NEXT: v_mul_lo_u32 v3, v3, v4 798; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v8, v6, 0 799; GFX10-NEXT: v_mul_lo_u32 v7, v8, v7 800; GFX10-NEXT: v_mul_lo_u32 v6, v9, v6 801; GFX10-NEXT: v_mad_u64_u32 v[11:12], s4, v9, v5, v[0:1] 802; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v8, v4, 0 803; GFX10-NEXT: v_mad_u64_u32 v[11:12], s4, v10, v4, v[11:12] 804; GFX10-NEXT: v_mov_b32_e32 v2, v11 805; GFX10-NEXT: v_mad_u64_u32 v[1:2], vcc_lo, v8, v5, v[1:2] 806; GFX10-NEXT: v_mul_lo_u32 v5, v10, v5 807; GFX10-NEXT: v_mad_u64_u32 v[1:2], s4, v9, v4, v[1:2] 808; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s4, v12, v7, s4 809; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v7, v6, vcc_lo 810; GFX10-NEXT: v_add3_u32 v3, v4, v5, v3 811; GFX10-NEXT: s_setpc_b64 s[30:31] 812; 813; GFX11-LABEL: v_mul_i128: 814; GFX11: ; %bb.0: 815; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 816; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 817; GFX11-NEXT: v_dual_mov_b32 v8, v0 :: v_dual_mov_b32 v9, v1 818; GFX11-NEXT: v_mov_b32_e32 v10, v2 819; GFX11-NEXT: v_mul_lo_u32 v3, v3, v4 820; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v8, v6, 0 821; GFX11-NEXT: v_mul_lo_u32 v7, v8, v7 822; GFX11-NEXT: v_mul_lo_u32 v6, v9, v6 823; GFX11-NEXT: v_mad_u64_u32 v[11:12], null, v9, v5, v[0:1] 824; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v8, v4, 0 825; GFX11-NEXT: v_mad_u64_u32 v[11:12], null, v10, v4, v[11:12] 826; GFX11-NEXT: v_mov_b32_e32 v2, v11 827; GFX11-NEXT: v_mad_u64_u32 v[1:2], vcc_lo, v8, v5, v[1:2] 828; GFX11-NEXT: v_mul_lo_u32 v5, v10, v5 829; GFX11-NEXT: v_mad_u64_u32 v[1:2], s0, v9, v4, v[1:2] 830; GFX11-NEXT: v_add_co_ci_u32_e64 v7, s0, v12, v7, s0 831; GFX11-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v7, v6, vcc_lo 832; GFX11-NEXT: v_add3_u32 v3, v4, v5, v3 833; GFX11-NEXT: s_setpc_b64 s[30:31] 834 %result = mul i128 %num, %den 835 ret i128 %result 836} 837 838define amdgpu_ps <8 x i32> @s_mul_i256(i256 inreg %num, i256 inreg %den) { 839; GFX7-LABEL: s_mul_i256: 840; GFX7: ; %bb.0: 841; GFX7-NEXT: s_mov_b32 s16, s0 842; GFX7-NEXT: v_mov_b32_e32 v0, s8 843; GFX7-NEXT: v_mul_hi_u32 v0, s16, v0 844; GFX7-NEXT: v_mov_b32_e32 v1, s9 845; GFX7-NEXT: v_mul_hi_u32 v2, s1, v1 846; GFX7-NEXT: v_mul_hi_u32 v1, s16, v1 847; GFX7-NEXT: v_readfirstlane_b32 s17, v0 848; GFX7-NEXT: v_mov_b32_e32 v0, s10 849; GFX7-NEXT: v_mul_hi_u32 v0, s16, v0 850; GFX7-NEXT: v_readfirstlane_b32 s21, v2 851; GFX7-NEXT: v_mov_b32_e32 v2, s2 852; GFX7-NEXT: v_readfirstlane_b32 s23, v1 853; GFX7-NEXT: v_readfirstlane_b32 s19, v0 854; GFX7-NEXT: v_mov_b32_e32 v0, s1 855; GFX7-NEXT: v_mul_hi_u32 v1, v0, s8 856; GFX7-NEXT: v_mul_hi_u32 v3, v2, s8 857; GFX7-NEXT: v_mov_b32_e32 v4, s11 858; GFX7-NEXT: s_mul_i32 s18, s16, s10 859; GFX7-NEXT: v_readfirstlane_b32 s24, v1 860; GFX7-NEXT: v_mov_b32_e32 v1, s12 861; GFX7-NEXT: v_readfirstlane_b32 s22, v3 862; GFX7-NEXT: v_mul_hi_u32 v3, s16, v1 863; GFX7-NEXT: s_mul_i32 s20, s1, s9 864; GFX7-NEXT: v_mul_hi_u32 v5, s1, v4 865; GFX7-NEXT: s_add_u32 s18, s20, s18 866; GFX7-NEXT: v_readfirstlane_b32 s25, v3 867; GFX7-NEXT: v_mul_hi_u32 v3, v2, s10 868; GFX7-NEXT: s_addc_u32 s19, s21, s19 869; GFX7-NEXT: s_mul_i32 s21, s2, s8 870; GFX7-NEXT: s_cselect_b32 s20, 1, 0 871; GFX7-NEXT: s_add_u32 s18, s21, s18 872; GFX7-NEXT: v_readfirstlane_b32 s28, v3 873; GFX7-NEXT: v_mov_b32_e32 v3, s3 874; GFX7-NEXT: s_addc_u32 s19, s22, s19 875; GFX7-NEXT: s_mul_i32 s22, s16, s9 876; GFX7-NEXT: v_readfirstlane_b32 s27, v5 877; GFX7-NEXT: v_mul_hi_u32 v5, v3, s9 878; GFX7-NEXT: s_cselect_b32 s21, 1, 0 879; GFX7-NEXT: s_add_u32 s17, s22, s17 880; GFX7-NEXT: s_addc_u32 s18, s23, s18 881; GFX7-NEXT: s_mul_i32 s23, s1, s8 882; GFX7-NEXT: s_cselect_b32 s22, 1, 0 883; GFX7-NEXT: s_add_u32 s17, s23, s17 884; GFX7-NEXT: s_addc_u32 s18, s24, s18 885; GFX7-NEXT: s_mul_i32 s24, s16, s12 886; GFX7-NEXT: s_mul_i32 s26, s1, s11 887; GFX7-NEXT: v_readfirstlane_b32 s29, v5 888; GFX7-NEXT: v_mov_b32_e32 v5, s4 889; GFX7-NEXT: s_cselect_b32 s23, 1, 0 890; GFX7-NEXT: s_add_u32 s24, s26, s24 891; GFX7-NEXT: v_mul_hi_u32 v6, v5, s8 892; GFX7-NEXT: s_addc_u32 s25, s27, s25 893; GFX7-NEXT: s_mul_i32 s27, s2, s10 894; GFX7-NEXT: s_cselect_b32 s26, 1, 0 895; GFX7-NEXT: s_add_u32 s24, s27, s24 896; GFX7-NEXT: v_mul_hi_u32 v0, v0, s10 897; GFX7-NEXT: s_addc_u32 s25, s28, s25 898; GFX7-NEXT: s_mul_i32 s28, s3, s9 899; GFX7-NEXT: s_cselect_b32 s27, 1, 0 900; GFX7-NEXT: s_add_u32 s24, s28, s24 901; GFX7-NEXT: v_readfirstlane_b32 s30, v6 902; GFX7-NEXT: v_mul_hi_u32 v6, s16, v4 903; GFX7-NEXT: s_addc_u32 s25, s29, s25 904; GFX7-NEXT: s_mul_i32 s29, s4, s8 905; GFX7-NEXT: s_cselect_b32 s28, 1, 0 906; GFX7-NEXT: s_add_u32 s24, s29, s24 907; GFX7-NEXT: v_readfirstlane_b32 s33, v0 908; GFX7-NEXT: v_mul_hi_u32 v0, v2, s9 909; GFX7-NEXT: s_addc_u32 s25, s30, s25 910; GFX7-NEXT: s_mul_i32 s30, s16, s11 911; GFX7-NEXT: s_cselect_b32 s29, 1, 0 912; GFX7-NEXT: v_readfirstlane_b32 s31, v6 913; GFX7-NEXT: s_add_u32 s19, s30, s19 914; GFX7-NEXT: s_addc_u32 s24, s31, s24 915; GFX7-NEXT: s_mul_i32 s31, s1, s10 916; GFX7-NEXT: s_cselect_b32 s30, 1, 0 917; GFX7-NEXT: s_add_u32 s19, s31, s19 918; GFX7-NEXT: v_readfirstlane_b32 s34, v0 919; GFX7-NEXT: v_mul_hi_u32 v0, v3, s8 920; GFX7-NEXT: s_addc_u32 s24, s33, s24 921; GFX7-NEXT: s_mul_i32 s33, s2, s9 922; GFX7-NEXT: s_cselect_b32 s31, 1, 0 923; GFX7-NEXT: s_add_u32 s19, s33, s19 924; GFX7-NEXT: s_addc_u32 s24, s34, s24 925; GFX7-NEXT: s_mul_i32 s34, s3, s8 926; GFX7-NEXT: s_cselect_b32 s33, 1, 0 927; GFX7-NEXT: v_readfirstlane_b32 s35, v0 928; GFX7-NEXT: s_add_u32 s19, s34, s19 929; GFX7-NEXT: v_mov_b32_e32 v0, s14 930; GFX7-NEXT: s_addc_u32 s24, s35, s24 931; GFX7-NEXT: v_mul_hi_u32 v0, s16, v0 932; GFX7-NEXT: s_cselect_b32 s34, 1, 0 933; GFX7-NEXT: s_cmp_lg_u32 s23, 0 934; GFX7-NEXT: s_addc_u32 s19, s22, s19 935; GFX7-NEXT: v_mov_b32_e32 v2, s13 936; GFX7-NEXT: s_cselect_b32 s22, 1, 0 937; GFX7-NEXT: s_cmp_lg_u32 s21, 0 938; GFX7-NEXT: v_mul_hi_u32 v6, s1, v2 939; GFX7-NEXT: s_addc_u32 s20, s20, 0 940; GFX7-NEXT: v_readfirstlane_b32 s23, v0 941; GFX7-NEXT: v_mul_hi_u32 v0, s2, v1 942; GFX7-NEXT: s_cmp_lg_u32 s22, 0 943; GFX7-NEXT: s_addc_u32 s20, s20, s24 944; GFX7-NEXT: s_mul_i32 s22, s16, s14 945; GFX7-NEXT: s_mul_i32 s24, s1, s13 946; GFX7-NEXT: s_cselect_b32 s21, 1, 0 947; GFX7-NEXT: v_readfirstlane_b32 s35, v6 948; GFX7-NEXT: s_add_u32 s22, s24, s22 949; GFX7-NEXT: s_addc_u32 s23, s35, s23 950; GFX7-NEXT: v_readfirstlane_b32 s35, v0 951; GFX7-NEXT: v_mul_hi_u32 v0, v3, s11 952; GFX7-NEXT: s_mul_i32 s24, s2, s12 953; GFX7-NEXT: s_add_u32 s22, s24, s22 954; GFX7-NEXT: s_addc_u32 s23, s35, s23 955; GFX7-NEXT: v_readfirstlane_b32 s35, v0 956; GFX7-NEXT: v_mul_hi_u32 v0, v5, s10 957; GFX7-NEXT: s_mul_i32 s24, s3, s11 958; GFX7-NEXT: s_add_u32 s22, s24, s22 959; GFX7-NEXT: s_addc_u32 s23, s35, s23 960; GFX7-NEXT: v_readfirstlane_b32 s35, v0 961; GFX7-NEXT: v_mov_b32_e32 v0, s5 962; GFX7-NEXT: v_mul_hi_u32 v6, v0, s9 963; GFX7-NEXT: s_mul_i32 s24, s4, s10 964; GFX7-NEXT: s_add_u32 s22, s24, s22 965; GFX7-NEXT: v_mul_hi_u32 v1, s1, v1 966; GFX7-NEXT: s_addc_u32 s23, s35, s23 967; GFX7-NEXT: v_readfirstlane_b32 s35, v6 968; GFX7-NEXT: v_mov_b32_e32 v6, s6 969; GFX7-NEXT: v_mul_hi_u32 v6, v6, s8 970; GFX7-NEXT: s_mul_i32 s24, s5, s9 971; GFX7-NEXT: s_add_u32 s22, s24, s22 972; GFX7-NEXT: v_mul_hi_u32 v2, s16, v2 973; GFX7-NEXT: v_readfirstlane_b32 s36, v1 974; GFX7-NEXT: v_mul_hi_u32 v1, s2, v4 975; GFX7-NEXT: s_addc_u32 s23, s35, s23 976; GFX7-NEXT: s_mul_i32 s24, s6, s8 977; GFX7-NEXT: v_readfirstlane_b32 s35, v6 978; GFX7-NEXT: s_add_u32 s22, s24, s22 979; GFX7-NEXT: s_addc_u32 s23, s35, s23 980; GFX7-NEXT: s_mul_i32 s24, s16, s13 981; GFX7-NEXT: v_readfirstlane_b32 s35, v2 982; GFX7-NEXT: s_add_u32 s24, s24, s25 983; GFX7-NEXT: v_readfirstlane_b32 s37, v1 984; GFX7-NEXT: v_mul_hi_u32 v1, v3, s10 985; GFX7-NEXT: s_addc_u32 s22, s35, s22 986; GFX7-NEXT: s_mul_i32 s35, s1, s12 987; GFX7-NEXT: s_cselect_b32 s25, 1, 0 988; GFX7-NEXT: s_add_u32 s24, s35, s24 989; GFX7-NEXT: s_addc_u32 s22, s36, s22 990; GFX7-NEXT: s_mul_i32 s36, s2, s11 991; GFX7-NEXT: s_cselect_b32 s35, 1, 0 992; GFX7-NEXT: s_add_u32 s24, s36, s24 993; GFX7-NEXT: v_readfirstlane_b32 s38, v1 994; GFX7-NEXT: v_mul_hi_u32 v1, v5, s9 995; GFX7-NEXT: s_addc_u32 s22, s37, s22 996; GFX7-NEXT: s_mul_i32 s37, s3, s10 997; GFX7-NEXT: s_cselect_b32 s36, 1, 0 998; GFX7-NEXT: s_add_u32 s24, s37, s24 999; GFX7-NEXT: v_mul_hi_u32 v0, v0, s8 1000; GFX7-NEXT: s_addc_u32 s22, s38, s22 1001; GFX7-NEXT: s_mul_i32 s38, s4, s9 1002; GFX7-NEXT: s_cselect_b32 s37, 1, 0 1003; GFX7-NEXT: v_readfirstlane_b32 s39, v1 1004; GFX7-NEXT: s_add_u32 s24, s38, s24 1005; GFX7-NEXT: s_addc_u32 s22, s39, s22 1006; GFX7-NEXT: s_mul_i32 s39, s5, s8 1007; GFX7-NEXT: s_cselect_b32 s38, 1, 0 1008; GFX7-NEXT: v_readfirstlane_b32 s40, v0 1009; GFX7-NEXT: s_add_u32 s24, s39, s24 1010; GFX7-NEXT: s_addc_u32 s22, s40, s22 1011; GFX7-NEXT: s_cselect_b32 s39, 1, 0 1012; GFX7-NEXT: s_cmp_lg_u32 s31, 0 1013; GFX7-NEXT: s_addc_u32 s30, s30, 0 1014; GFX7-NEXT: s_cmp_lg_u32 s33, 0 1015; GFX7-NEXT: s_addc_u32 s30, s30, 0 1016; GFX7-NEXT: s_cmp_lg_u32 s34, 0 1017; GFX7-NEXT: s_addc_u32 s30, s30, 0 1018; GFX7-NEXT: s_cmp_lg_u32 s21, 0 1019; GFX7-NEXT: s_addc_u32 s21, s30, s24 1020; GFX7-NEXT: s_cselect_b32 s24, 1, 0 1021; GFX7-NEXT: s_cmp_lg_u32 s27, 0 1022; GFX7-NEXT: s_addc_u32 s26, s26, 0 1023; GFX7-NEXT: s_cmp_lg_u32 s28, 0 1024; GFX7-NEXT: s_addc_u32 s26, s26, 0 1025; GFX7-NEXT: s_cmp_lg_u32 s29, 0 1026; GFX7-NEXT: s_addc_u32 s26, s26, 0 1027; GFX7-NEXT: s_cmp_lg_u32 s24, 0 1028; GFX7-NEXT: s_addc_u32 s22, s26, s22 1029; GFX7-NEXT: s_mul_i32 s16, s16, s15 1030; GFX7-NEXT: s_addc_u32 s15, s23, s16 1031; GFX7-NEXT: s_mul_i32 s1, s1, s14 1032; GFX7-NEXT: s_cmp_lg_u32 s39, 0 1033; GFX7-NEXT: s_addc_u32 s1, s15, s1 1034; GFX7-NEXT: s_mul_i32 s2, s2, s13 1035; GFX7-NEXT: s_cmp_lg_u32 s38, 0 1036; GFX7-NEXT: s_addc_u32 s1, s1, s2 1037; GFX7-NEXT: s_mul_i32 s3, s3, s12 1038; GFX7-NEXT: s_cmp_lg_u32 s37, 0 1039; GFX7-NEXT: s_addc_u32 s1, s1, s3 1040; GFX7-NEXT: s_mul_i32 s4, s4, s11 1041; GFX7-NEXT: s_cmp_lg_u32 s36, 0 1042; GFX7-NEXT: s_addc_u32 s1, s1, s4 1043; GFX7-NEXT: s_mul_i32 s5, s5, s10 1044; GFX7-NEXT: s_cmp_lg_u32 s35, 0 1045; GFX7-NEXT: s_addc_u32 s1, s1, s5 1046; GFX7-NEXT: s_mul_i32 s6, s6, s9 1047; GFX7-NEXT: s_cmp_lg_u32 s25, 0 1048; GFX7-NEXT: s_addc_u32 s1, s1, s6 1049; GFX7-NEXT: s_mul_i32 s7, s7, s8 1050; GFX7-NEXT: s_mul_i32 s0, s0, s8 1051; GFX7-NEXT: s_add_u32 s7, s7, s1 1052; GFX7-NEXT: s_mov_b32 s1, s17 1053; GFX7-NEXT: s_mov_b32 s2, s18 1054; GFX7-NEXT: s_mov_b32 s3, s19 1055; GFX7-NEXT: s_mov_b32 s4, s20 1056; GFX7-NEXT: s_mov_b32 s5, s21 1057; GFX7-NEXT: s_mov_b32 s6, s22 1058; GFX7-NEXT: ; return to shader part epilog 1059; 1060; GFX8-LABEL: s_mul_i256: 1061; GFX8: ; %bb.0: 1062; GFX8-NEXT: s_mov_b32 s16, s0 1063; GFX8-NEXT: v_mov_b32_e32 v0, s8 1064; GFX8-NEXT: v_mul_hi_u32 v0, s16, v0 1065; GFX8-NEXT: v_mov_b32_e32 v1, s9 1066; GFX8-NEXT: v_mul_hi_u32 v2, s1, v1 1067; GFX8-NEXT: v_mul_hi_u32 v1, s16, v1 1068; GFX8-NEXT: v_readfirstlane_b32 s17, v0 1069; GFX8-NEXT: v_mov_b32_e32 v0, s10 1070; GFX8-NEXT: v_mul_hi_u32 v0, s16, v0 1071; GFX8-NEXT: v_readfirstlane_b32 s21, v2 1072; GFX8-NEXT: v_mov_b32_e32 v2, s2 1073; GFX8-NEXT: v_readfirstlane_b32 s23, v1 1074; GFX8-NEXT: v_readfirstlane_b32 s19, v0 1075; GFX8-NEXT: v_mov_b32_e32 v0, s1 1076; GFX8-NEXT: v_mul_hi_u32 v1, v0, s8 1077; GFX8-NEXT: v_mul_hi_u32 v3, v2, s8 1078; GFX8-NEXT: v_mov_b32_e32 v4, s11 1079; GFX8-NEXT: s_mul_i32 s18, s16, s10 1080; GFX8-NEXT: v_readfirstlane_b32 s24, v1 1081; GFX8-NEXT: v_mov_b32_e32 v1, s12 1082; GFX8-NEXT: v_readfirstlane_b32 s22, v3 1083; GFX8-NEXT: v_mul_hi_u32 v3, s16, v1 1084; GFX8-NEXT: s_mul_i32 s20, s1, s9 1085; GFX8-NEXT: v_mul_hi_u32 v5, s1, v4 1086; GFX8-NEXT: s_add_u32 s18, s20, s18 1087; GFX8-NEXT: v_readfirstlane_b32 s25, v3 1088; GFX8-NEXT: v_mul_hi_u32 v3, v2, s10 1089; GFX8-NEXT: s_addc_u32 s19, s21, s19 1090; GFX8-NEXT: s_mul_i32 s21, s2, s8 1091; GFX8-NEXT: s_cselect_b32 s20, 1, 0 1092; GFX8-NEXT: s_add_u32 s18, s21, s18 1093; GFX8-NEXT: v_readfirstlane_b32 s28, v3 1094; GFX8-NEXT: v_mov_b32_e32 v3, s3 1095; GFX8-NEXT: s_addc_u32 s19, s22, s19 1096; GFX8-NEXT: s_mul_i32 s22, s16, s9 1097; GFX8-NEXT: v_readfirstlane_b32 s27, v5 1098; GFX8-NEXT: v_mul_hi_u32 v5, v3, s9 1099; GFX8-NEXT: s_cselect_b32 s21, 1, 0 1100; GFX8-NEXT: s_add_u32 s17, s22, s17 1101; GFX8-NEXT: s_addc_u32 s18, s23, s18 1102; GFX8-NEXT: s_mul_i32 s23, s1, s8 1103; GFX8-NEXT: s_cselect_b32 s22, 1, 0 1104; GFX8-NEXT: s_add_u32 s17, s23, s17 1105; GFX8-NEXT: s_addc_u32 s18, s24, s18 1106; GFX8-NEXT: s_mul_i32 s24, s16, s12 1107; GFX8-NEXT: s_mul_i32 s26, s1, s11 1108; GFX8-NEXT: v_readfirstlane_b32 s29, v5 1109; GFX8-NEXT: v_mov_b32_e32 v5, s4 1110; GFX8-NEXT: s_cselect_b32 s23, 1, 0 1111; GFX8-NEXT: s_add_u32 s24, s26, s24 1112; GFX8-NEXT: v_mul_hi_u32 v6, v5, s8 1113; GFX8-NEXT: s_addc_u32 s25, s27, s25 1114; GFX8-NEXT: s_mul_i32 s27, s2, s10 1115; GFX8-NEXT: s_cselect_b32 s26, 1, 0 1116; GFX8-NEXT: s_add_u32 s24, s27, s24 1117; GFX8-NEXT: v_mul_hi_u32 v0, v0, s10 1118; GFX8-NEXT: s_addc_u32 s25, s28, s25 1119; GFX8-NEXT: s_mul_i32 s28, s3, s9 1120; GFX8-NEXT: s_cselect_b32 s27, 1, 0 1121; GFX8-NEXT: s_add_u32 s24, s28, s24 1122; GFX8-NEXT: v_readfirstlane_b32 s30, v6 1123; GFX8-NEXT: v_mul_hi_u32 v6, s16, v4 1124; GFX8-NEXT: s_addc_u32 s25, s29, s25 1125; GFX8-NEXT: s_mul_i32 s29, s4, s8 1126; GFX8-NEXT: s_cselect_b32 s28, 1, 0 1127; GFX8-NEXT: s_add_u32 s24, s29, s24 1128; GFX8-NEXT: v_readfirstlane_b32 s33, v0 1129; GFX8-NEXT: v_mul_hi_u32 v0, v2, s9 1130; GFX8-NEXT: s_addc_u32 s25, s30, s25 1131; GFX8-NEXT: s_mul_i32 s30, s16, s11 1132; GFX8-NEXT: s_cselect_b32 s29, 1, 0 1133; GFX8-NEXT: v_readfirstlane_b32 s31, v6 1134; GFX8-NEXT: s_add_u32 s19, s30, s19 1135; GFX8-NEXT: s_addc_u32 s24, s31, s24 1136; GFX8-NEXT: s_mul_i32 s31, s1, s10 1137; GFX8-NEXT: s_cselect_b32 s30, 1, 0 1138; GFX8-NEXT: s_add_u32 s19, s31, s19 1139; GFX8-NEXT: v_readfirstlane_b32 s34, v0 1140; GFX8-NEXT: v_mul_hi_u32 v0, v3, s8 1141; GFX8-NEXT: s_addc_u32 s24, s33, s24 1142; GFX8-NEXT: s_mul_i32 s33, s2, s9 1143; GFX8-NEXT: s_cselect_b32 s31, 1, 0 1144; GFX8-NEXT: s_add_u32 s19, s33, s19 1145; GFX8-NEXT: s_addc_u32 s24, s34, s24 1146; GFX8-NEXT: s_mul_i32 s34, s3, s8 1147; GFX8-NEXT: s_cselect_b32 s33, 1, 0 1148; GFX8-NEXT: v_readfirstlane_b32 s35, v0 1149; GFX8-NEXT: s_add_u32 s19, s34, s19 1150; GFX8-NEXT: v_mov_b32_e32 v0, s14 1151; GFX8-NEXT: s_addc_u32 s24, s35, s24 1152; GFX8-NEXT: v_mul_hi_u32 v0, s16, v0 1153; GFX8-NEXT: s_cselect_b32 s34, 1, 0 1154; GFX8-NEXT: s_cmp_lg_u32 s23, 0 1155; GFX8-NEXT: s_addc_u32 s19, s22, s19 1156; GFX8-NEXT: v_mov_b32_e32 v2, s13 1157; GFX8-NEXT: s_cselect_b32 s22, 1, 0 1158; GFX8-NEXT: s_cmp_lg_u32 s21, 0 1159; GFX8-NEXT: v_mul_hi_u32 v6, s1, v2 1160; GFX8-NEXT: s_addc_u32 s20, s20, 0 1161; GFX8-NEXT: v_readfirstlane_b32 s23, v0 1162; GFX8-NEXT: v_mul_hi_u32 v0, s2, v1 1163; GFX8-NEXT: s_cmp_lg_u32 s22, 0 1164; GFX8-NEXT: s_addc_u32 s20, s20, s24 1165; GFX8-NEXT: s_mul_i32 s22, s16, s14 1166; GFX8-NEXT: s_mul_i32 s24, s1, s13 1167; GFX8-NEXT: s_cselect_b32 s21, 1, 0 1168; GFX8-NEXT: v_readfirstlane_b32 s35, v6 1169; GFX8-NEXT: s_add_u32 s22, s24, s22 1170; GFX8-NEXT: s_addc_u32 s23, s35, s23 1171; GFX8-NEXT: v_readfirstlane_b32 s35, v0 1172; GFX8-NEXT: v_mul_hi_u32 v0, v3, s11 1173; GFX8-NEXT: s_mul_i32 s24, s2, s12 1174; GFX8-NEXT: s_add_u32 s22, s24, s22 1175; GFX8-NEXT: s_addc_u32 s23, s35, s23 1176; GFX8-NEXT: v_readfirstlane_b32 s35, v0 1177; GFX8-NEXT: v_mul_hi_u32 v0, v5, s10 1178; GFX8-NEXT: s_mul_i32 s24, s3, s11 1179; GFX8-NEXT: s_add_u32 s22, s24, s22 1180; GFX8-NEXT: s_addc_u32 s23, s35, s23 1181; GFX8-NEXT: v_readfirstlane_b32 s35, v0 1182; GFX8-NEXT: v_mov_b32_e32 v0, s5 1183; GFX8-NEXT: v_mul_hi_u32 v6, v0, s9 1184; GFX8-NEXT: s_mul_i32 s24, s4, s10 1185; GFX8-NEXT: s_add_u32 s22, s24, s22 1186; GFX8-NEXT: v_mul_hi_u32 v1, s1, v1 1187; GFX8-NEXT: s_addc_u32 s23, s35, s23 1188; GFX8-NEXT: v_readfirstlane_b32 s35, v6 1189; GFX8-NEXT: v_mov_b32_e32 v6, s6 1190; GFX8-NEXT: v_mul_hi_u32 v6, v6, s8 1191; GFX8-NEXT: s_mul_i32 s24, s5, s9 1192; GFX8-NEXT: s_add_u32 s22, s24, s22 1193; GFX8-NEXT: v_mul_hi_u32 v2, s16, v2 1194; GFX8-NEXT: v_readfirstlane_b32 s36, v1 1195; GFX8-NEXT: v_mul_hi_u32 v1, s2, v4 1196; GFX8-NEXT: s_addc_u32 s23, s35, s23 1197; GFX8-NEXT: s_mul_i32 s24, s6, s8 1198; GFX8-NEXT: v_readfirstlane_b32 s35, v6 1199; GFX8-NEXT: s_add_u32 s22, s24, s22 1200; GFX8-NEXT: s_addc_u32 s23, s35, s23 1201; GFX8-NEXT: s_mul_i32 s24, s16, s13 1202; GFX8-NEXT: v_readfirstlane_b32 s35, v2 1203; GFX8-NEXT: s_add_u32 s24, s24, s25 1204; GFX8-NEXT: v_readfirstlane_b32 s37, v1 1205; GFX8-NEXT: v_mul_hi_u32 v1, v3, s10 1206; GFX8-NEXT: s_addc_u32 s22, s35, s22 1207; GFX8-NEXT: s_mul_i32 s35, s1, s12 1208; GFX8-NEXT: s_cselect_b32 s25, 1, 0 1209; GFX8-NEXT: s_add_u32 s24, s35, s24 1210; GFX8-NEXT: s_addc_u32 s22, s36, s22 1211; GFX8-NEXT: s_mul_i32 s36, s2, s11 1212; GFX8-NEXT: s_cselect_b32 s35, 1, 0 1213; GFX8-NEXT: s_add_u32 s24, s36, s24 1214; GFX8-NEXT: v_readfirstlane_b32 s38, v1 1215; GFX8-NEXT: v_mul_hi_u32 v1, v5, s9 1216; GFX8-NEXT: s_addc_u32 s22, s37, s22 1217; GFX8-NEXT: s_mul_i32 s37, s3, s10 1218; GFX8-NEXT: s_cselect_b32 s36, 1, 0 1219; GFX8-NEXT: s_add_u32 s24, s37, s24 1220; GFX8-NEXT: v_mul_hi_u32 v0, v0, s8 1221; GFX8-NEXT: s_addc_u32 s22, s38, s22 1222; GFX8-NEXT: s_mul_i32 s38, s4, s9 1223; GFX8-NEXT: s_cselect_b32 s37, 1, 0 1224; GFX8-NEXT: v_readfirstlane_b32 s39, v1 1225; GFX8-NEXT: s_add_u32 s24, s38, s24 1226; GFX8-NEXT: s_addc_u32 s22, s39, s22 1227; GFX8-NEXT: s_mul_i32 s39, s5, s8 1228; GFX8-NEXT: s_cselect_b32 s38, 1, 0 1229; GFX8-NEXT: v_readfirstlane_b32 s40, v0 1230; GFX8-NEXT: s_add_u32 s24, s39, s24 1231; GFX8-NEXT: s_addc_u32 s22, s40, s22 1232; GFX8-NEXT: s_cselect_b32 s39, 1, 0 1233; GFX8-NEXT: s_cmp_lg_u32 s31, 0 1234; GFX8-NEXT: s_addc_u32 s30, s30, 0 1235; GFX8-NEXT: s_cmp_lg_u32 s33, 0 1236; GFX8-NEXT: s_addc_u32 s30, s30, 0 1237; GFX8-NEXT: s_cmp_lg_u32 s34, 0 1238; GFX8-NEXT: s_addc_u32 s30, s30, 0 1239; GFX8-NEXT: s_cmp_lg_u32 s21, 0 1240; GFX8-NEXT: s_addc_u32 s21, s30, s24 1241; GFX8-NEXT: s_cselect_b32 s24, 1, 0 1242; GFX8-NEXT: s_cmp_lg_u32 s27, 0 1243; GFX8-NEXT: s_addc_u32 s26, s26, 0 1244; GFX8-NEXT: s_cmp_lg_u32 s28, 0 1245; GFX8-NEXT: s_addc_u32 s26, s26, 0 1246; GFX8-NEXT: s_cmp_lg_u32 s29, 0 1247; GFX8-NEXT: s_addc_u32 s26, s26, 0 1248; GFX8-NEXT: s_cmp_lg_u32 s24, 0 1249; GFX8-NEXT: s_addc_u32 s22, s26, s22 1250; GFX8-NEXT: s_mul_i32 s16, s16, s15 1251; GFX8-NEXT: s_addc_u32 s15, s23, s16 1252; GFX8-NEXT: s_mul_i32 s1, s1, s14 1253; GFX8-NEXT: s_cmp_lg_u32 s39, 0 1254; GFX8-NEXT: s_addc_u32 s1, s15, s1 1255; GFX8-NEXT: s_mul_i32 s2, s2, s13 1256; GFX8-NEXT: s_cmp_lg_u32 s38, 0 1257; GFX8-NEXT: s_addc_u32 s1, s1, s2 1258; GFX8-NEXT: s_mul_i32 s3, s3, s12 1259; GFX8-NEXT: s_cmp_lg_u32 s37, 0 1260; GFX8-NEXT: s_addc_u32 s1, s1, s3 1261; GFX8-NEXT: s_mul_i32 s4, s4, s11 1262; GFX8-NEXT: s_cmp_lg_u32 s36, 0 1263; GFX8-NEXT: s_addc_u32 s1, s1, s4 1264; GFX8-NEXT: s_mul_i32 s5, s5, s10 1265; GFX8-NEXT: s_cmp_lg_u32 s35, 0 1266; GFX8-NEXT: s_addc_u32 s1, s1, s5 1267; GFX8-NEXT: s_mul_i32 s6, s6, s9 1268; GFX8-NEXT: s_cmp_lg_u32 s25, 0 1269; GFX8-NEXT: s_addc_u32 s1, s1, s6 1270; GFX8-NEXT: s_mul_i32 s7, s7, s8 1271; GFX8-NEXT: s_mul_i32 s0, s0, s8 1272; GFX8-NEXT: s_add_u32 s7, s7, s1 1273; GFX8-NEXT: s_mov_b32 s1, s17 1274; GFX8-NEXT: s_mov_b32 s2, s18 1275; GFX8-NEXT: s_mov_b32 s3, s19 1276; GFX8-NEXT: s_mov_b32 s4, s20 1277; GFX8-NEXT: s_mov_b32 s5, s21 1278; GFX8-NEXT: s_mov_b32 s6, s22 1279; GFX8-NEXT: ; return to shader part epilog 1280; 1281; GFX9-LABEL: s_mul_i256: 1282; GFX9: ; %bb.0: 1283; GFX9-NEXT: s_mul_i32 s18, s0, s10 1284; GFX9-NEXT: s_mul_i32 s20, s1, s9 1285; GFX9-NEXT: s_mul_hi_u32 s19, s0, s10 1286; GFX9-NEXT: s_mul_hi_u32 s21, s1, s9 1287; GFX9-NEXT: s_add_u32 s18, s20, s18 1288; GFX9-NEXT: s_addc_u32 s19, s21, s19 1289; GFX9-NEXT: s_mul_i32 s21, s2, s8 1290; GFX9-NEXT: s_cselect_b32 s20, 1, 0 1291; GFX9-NEXT: s_mul_hi_u32 s22, s2, s8 1292; GFX9-NEXT: s_add_u32 s18, s21, s18 1293; GFX9-NEXT: s_mul_hi_u32 s17, s0, s8 1294; GFX9-NEXT: s_addc_u32 s19, s22, s19 1295; GFX9-NEXT: s_mul_i32 s22, s0, s9 1296; GFX9-NEXT: s_cselect_b32 s21, 1, 0 1297; GFX9-NEXT: s_mul_hi_u32 s23, s0, s9 1298; GFX9-NEXT: s_add_u32 s17, s22, s17 1299; GFX9-NEXT: s_addc_u32 s18, s23, s18 1300; GFX9-NEXT: s_mul_i32 s23, s1, s8 1301; GFX9-NEXT: s_cselect_b32 s22, 1, 0 1302; GFX9-NEXT: s_mul_hi_u32 s24, s1, s8 1303; GFX9-NEXT: s_add_u32 s17, s23, s17 1304; GFX9-NEXT: s_addc_u32 s18, s24, s18 1305; GFX9-NEXT: s_mul_i32 s24, s0, s12 1306; GFX9-NEXT: s_mul_i32 s26, s1, s11 1307; GFX9-NEXT: s_cselect_b32 s23, 1, 0 1308; GFX9-NEXT: s_mul_hi_u32 s25, s0, s12 1309; GFX9-NEXT: s_mul_hi_u32 s27, s1, s11 1310; GFX9-NEXT: s_add_u32 s24, s26, s24 1311; GFX9-NEXT: s_addc_u32 s25, s27, s25 1312; GFX9-NEXT: s_mul_i32 s27, s2, s10 1313; GFX9-NEXT: s_cselect_b32 s26, 1, 0 1314; GFX9-NEXT: s_mul_hi_u32 s28, s2, s10 1315; GFX9-NEXT: s_add_u32 s24, s27, s24 1316; GFX9-NEXT: s_addc_u32 s25, s28, s25 1317; GFX9-NEXT: s_mul_i32 s28, s3, s9 1318; GFX9-NEXT: s_cselect_b32 s27, 1, 0 1319; GFX9-NEXT: s_mul_hi_u32 s29, s3, s9 1320; GFX9-NEXT: s_add_u32 s24, s28, s24 1321; GFX9-NEXT: s_addc_u32 s25, s29, s25 1322; GFX9-NEXT: s_mul_i32 s29, s4, s8 1323; GFX9-NEXT: s_cselect_b32 s28, 1, 0 1324; GFX9-NEXT: s_mul_hi_u32 s30, s4, s8 1325; GFX9-NEXT: s_add_u32 s24, s29, s24 1326; GFX9-NEXT: s_addc_u32 s25, s30, s25 1327; GFX9-NEXT: s_mul_i32 s30, s0, s11 1328; GFX9-NEXT: s_cselect_b32 s29, 1, 0 1329; GFX9-NEXT: s_mul_hi_u32 s31, s0, s11 1330; GFX9-NEXT: s_add_u32 s19, s30, s19 1331; GFX9-NEXT: s_addc_u32 s24, s31, s24 1332; GFX9-NEXT: s_mul_i32 s31, s1, s10 1333; GFX9-NEXT: s_cselect_b32 s30, 1, 0 1334; GFX9-NEXT: s_mul_hi_u32 s33, s1, s10 1335; GFX9-NEXT: s_add_u32 s19, s31, s19 1336; GFX9-NEXT: s_addc_u32 s24, s33, s24 1337; GFX9-NEXT: s_mul_i32 s33, s2, s9 1338; GFX9-NEXT: s_cselect_b32 s31, 1, 0 1339; GFX9-NEXT: s_mul_hi_u32 s34, s2, s9 1340; GFX9-NEXT: s_add_u32 s19, s33, s19 1341; GFX9-NEXT: s_addc_u32 s24, s34, s24 1342; GFX9-NEXT: s_mul_i32 s34, s3, s8 1343; GFX9-NEXT: s_cselect_b32 s33, 1, 0 1344; GFX9-NEXT: s_mul_hi_u32 s35, s3, s8 1345; GFX9-NEXT: s_add_u32 s19, s34, s19 1346; GFX9-NEXT: s_addc_u32 s24, s35, s24 1347; GFX9-NEXT: s_cselect_b32 s34, 1, 0 1348; GFX9-NEXT: s_cmp_lg_u32 s23, 0 1349; GFX9-NEXT: s_addc_u32 s19, s22, s19 1350; GFX9-NEXT: s_cselect_b32 s22, 1, 0 1351; GFX9-NEXT: s_cmp_lg_u32 s21, 0 1352; GFX9-NEXT: s_addc_u32 s20, s20, 0 1353; GFX9-NEXT: s_cmp_lg_u32 s22, 0 1354; GFX9-NEXT: s_addc_u32 s20, s20, s24 1355; GFX9-NEXT: s_mul_i32 s22, s0, s14 1356; GFX9-NEXT: s_mul_i32 s24, s1, s13 1357; GFX9-NEXT: s_cselect_b32 s21, 1, 0 1358; GFX9-NEXT: s_mul_hi_u32 s23, s0, s14 1359; GFX9-NEXT: s_mul_hi_u32 s35, s1, s13 1360; GFX9-NEXT: s_add_u32 s22, s24, s22 1361; GFX9-NEXT: s_addc_u32 s23, s35, s23 1362; GFX9-NEXT: s_mul_i32 s24, s2, s12 1363; GFX9-NEXT: s_mul_hi_u32 s35, s2, s12 1364; GFX9-NEXT: s_add_u32 s22, s24, s22 1365; GFX9-NEXT: s_addc_u32 s23, s35, s23 1366; GFX9-NEXT: s_mul_i32 s24, s3, s11 1367; GFX9-NEXT: s_mul_hi_u32 s35, s3, s11 1368; GFX9-NEXT: s_add_u32 s22, s24, s22 1369; GFX9-NEXT: s_addc_u32 s23, s35, s23 1370; GFX9-NEXT: s_mul_i32 s24, s4, s10 1371; GFX9-NEXT: s_mul_hi_u32 s35, s4, s10 1372; GFX9-NEXT: s_add_u32 s22, s24, s22 1373; GFX9-NEXT: s_addc_u32 s23, s35, s23 1374; GFX9-NEXT: s_mul_i32 s24, s5, s9 1375; GFX9-NEXT: s_mul_hi_u32 s35, s5, s9 1376; GFX9-NEXT: s_add_u32 s22, s24, s22 1377; GFX9-NEXT: s_addc_u32 s23, s35, s23 1378; GFX9-NEXT: s_mul_i32 s24, s6, s8 1379; GFX9-NEXT: s_mul_hi_u32 s35, s6, s8 1380; GFX9-NEXT: s_add_u32 s22, s24, s22 1381; GFX9-NEXT: s_addc_u32 s23, s35, s23 1382; GFX9-NEXT: s_mul_i32 s24, s0, s13 1383; GFX9-NEXT: s_mul_hi_u32 s35, s0, s13 1384; GFX9-NEXT: s_add_u32 s24, s24, s25 1385; GFX9-NEXT: s_addc_u32 s22, s35, s22 1386; GFX9-NEXT: s_mul_i32 s35, s1, s12 1387; GFX9-NEXT: s_cselect_b32 s25, 1, 0 1388; GFX9-NEXT: s_mul_hi_u32 s36, s1, s12 1389; GFX9-NEXT: s_add_u32 s24, s35, s24 1390; GFX9-NEXT: s_addc_u32 s22, s36, s22 1391; GFX9-NEXT: s_mul_i32 s36, s2, s11 1392; GFX9-NEXT: s_cselect_b32 s35, 1, 0 1393; GFX9-NEXT: s_mul_hi_u32 s37, s2, s11 1394; GFX9-NEXT: s_add_u32 s24, s36, s24 1395; GFX9-NEXT: s_addc_u32 s22, s37, s22 1396; GFX9-NEXT: s_mul_i32 s37, s3, s10 1397; GFX9-NEXT: s_cselect_b32 s36, 1, 0 1398; GFX9-NEXT: s_mul_hi_u32 s38, s3, s10 1399; GFX9-NEXT: s_add_u32 s24, s37, s24 1400; GFX9-NEXT: s_addc_u32 s22, s38, s22 1401; GFX9-NEXT: s_mul_i32 s38, s4, s9 1402; GFX9-NEXT: s_cselect_b32 s37, 1, 0 1403; GFX9-NEXT: s_mul_hi_u32 s39, s4, s9 1404; GFX9-NEXT: s_add_u32 s24, s38, s24 1405; GFX9-NEXT: s_addc_u32 s22, s39, s22 1406; GFX9-NEXT: s_mul_i32 s39, s5, s8 1407; GFX9-NEXT: s_cselect_b32 s38, 1, 0 1408; GFX9-NEXT: s_mul_hi_u32 s40, s5, s8 1409; GFX9-NEXT: s_add_u32 s24, s39, s24 1410; GFX9-NEXT: s_addc_u32 s22, s40, s22 1411; GFX9-NEXT: s_cselect_b32 s39, 1, 0 1412; GFX9-NEXT: s_cmp_lg_u32 s31, 0 1413; GFX9-NEXT: s_addc_u32 s30, s30, 0 1414; GFX9-NEXT: s_cmp_lg_u32 s33, 0 1415; GFX9-NEXT: s_addc_u32 s30, s30, 0 1416; GFX9-NEXT: s_cmp_lg_u32 s34, 0 1417; GFX9-NEXT: s_addc_u32 s30, s30, 0 1418; GFX9-NEXT: s_cmp_lg_u32 s21, 0 1419; GFX9-NEXT: s_addc_u32 s21, s30, s24 1420; GFX9-NEXT: s_cselect_b32 s24, 1, 0 1421; GFX9-NEXT: s_cmp_lg_u32 s27, 0 1422; GFX9-NEXT: s_addc_u32 s26, s26, 0 1423; GFX9-NEXT: s_cmp_lg_u32 s28, 0 1424; GFX9-NEXT: s_addc_u32 s26, s26, 0 1425; GFX9-NEXT: s_cmp_lg_u32 s29, 0 1426; GFX9-NEXT: s_addc_u32 s26, s26, 0 1427; GFX9-NEXT: s_cmp_lg_u32 s24, 0 1428; GFX9-NEXT: s_mul_i32 s16, s0, s8 1429; GFX9-NEXT: s_addc_u32 s22, s26, s22 1430; GFX9-NEXT: s_mul_i32 s0, s0, s15 1431; GFX9-NEXT: s_addc_u32 s0, s23, s0 1432; GFX9-NEXT: s_mul_i32 s1, s1, s14 1433; GFX9-NEXT: s_cmp_lg_u32 s39, 0 1434; GFX9-NEXT: s_addc_u32 s0, s0, s1 1435; GFX9-NEXT: s_mul_i32 s2, s2, s13 1436; GFX9-NEXT: s_cmp_lg_u32 s38, 0 1437; GFX9-NEXT: s_addc_u32 s0, s0, s2 1438; GFX9-NEXT: s_mul_i32 s3, s3, s12 1439; GFX9-NEXT: s_cmp_lg_u32 s37, 0 1440; GFX9-NEXT: s_addc_u32 s0, s0, s3 1441; GFX9-NEXT: s_mul_i32 s4, s4, s11 1442; GFX9-NEXT: s_cmp_lg_u32 s36, 0 1443; GFX9-NEXT: s_addc_u32 s0, s0, s4 1444; GFX9-NEXT: s_mul_i32 s5, s5, s10 1445; GFX9-NEXT: s_cmp_lg_u32 s35, 0 1446; GFX9-NEXT: s_addc_u32 s0, s0, s5 1447; GFX9-NEXT: s_mul_i32 s6, s6, s9 1448; GFX9-NEXT: s_cmp_lg_u32 s25, 0 1449; GFX9-NEXT: s_addc_u32 s0, s0, s6 1450; GFX9-NEXT: s_mul_i32 s7, s7, s8 1451; GFX9-NEXT: s_add_u32 s7, s7, s0 1452; GFX9-NEXT: s_mov_b32 s0, s16 1453; GFX9-NEXT: s_mov_b32 s1, s17 1454; GFX9-NEXT: s_mov_b32 s2, s18 1455; GFX9-NEXT: s_mov_b32 s3, s19 1456; GFX9-NEXT: s_mov_b32 s4, s20 1457; GFX9-NEXT: s_mov_b32 s5, s21 1458; GFX9-NEXT: s_mov_b32 s6, s22 1459; GFX9-NEXT: ; return to shader part epilog 1460; 1461; GFX10PLUS-LABEL: s_mul_i256: 1462; GFX10PLUS: ; %bb.0: 1463; GFX10PLUS-NEXT: s_mul_i32 s17, s0, s10 1464; GFX10PLUS-NEXT: s_mul_i32 s19, s1, s9 1465; GFX10PLUS-NEXT: s_mul_hi_u32 s18, s0, s10 1466; GFX10PLUS-NEXT: s_mul_hi_u32 s20, s1, s9 1467; GFX10PLUS-NEXT: s_add_u32 s17, s19, s17 1468; GFX10PLUS-NEXT: s_addc_u32 s18, s20, s18 1469; GFX10PLUS-NEXT: s_mul_i32 s20, s2, s8 1470; GFX10PLUS-NEXT: s_mul_hi_u32 s21, s2, s8 1471; GFX10PLUS-NEXT: s_cselect_b32 s19, 1, 0 1472; GFX10PLUS-NEXT: s_add_u32 s17, s20, s17 1473; GFX10PLUS-NEXT: s_mul_hi_u32 s16, s0, s8 1474; GFX10PLUS-NEXT: s_addc_u32 s18, s21, s18 1475; GFX10PLUS-NEXT: s_mul_i32 s21, s0, s9 1476; GFX10PLUS-NEXT: s_mul_hi_u32 s22, s0, s9 1477; GFX10PLUS-NEXT: s_cselect_b32 s20, 1, 0 1478; GFX10PLUS-NEXT: s_add_u32 s16, s21, s16 1479; GFX10PLUS-NEXT: s_addc_u32 s17, s22, s17 1480; GFX10PLUS-NEXT: s_mul_i32 s22, s1, s8 1481; GFX10PLUS-NEXT: s_mul_hi_u32 s23, s1, s8 1482; GFX10PLUS-NEXT: s_cselect_b32 s21, 1, 0 1483; GFX10PLUS-NEXT: s_add_u32 s16, s22, s16 1484; GFX10PLUS-NEXT: s_addc_u32 s17, s23, s17 1485; GFX10PLUS-NEXT: s_mul_i32 s23, s0, s12 1486; GFX10PLUS-NEXT: s_mul_i32 s25, s1, s11 1487; GFX10PLUS-NEXT: s_mul_hi_u32 s24, s0, s12 1488; GFX10PLUS-NEXT: s_mul_hi_u32 s26, s1, s11 1489; GFX10PLUS-NEXT: s_cselect_b32 s22, 1, 0 1490; GFX10PLUS-NEXT: s_add_u32 s23, s25, s23 1491; GFX10PLUS-NEXT: s_addc_u32 s24, s26, s24 1492; GFX10PLUS-NEXT: s_mul_i32 s26, s2, s10 1493; GFX10PLUS-NEXT: s_mul_hi_u32 s27, s2, s10 1494; GFX10PLUS-NEXT: s_cselect_b32 s25, 1, 0 1495; GFX10PLUS-NEXT: s_add_u32 s23, s26, s23 1496; GFX10PLUS-NEXT: s_addc_u32 s24, s27, s24 1497; GFX10PLUS-NEXT: s_mul_i32 s27, s3, s9 1498; GFX10PLUS-NEXT: s_mul_hi_u32 s28, s3, s9 1499; GFX10PLUS-NEXT: s_cselect_b32 s26, 1, 0 1500; GFX10PLUS-NEXT: s_add_u32 s23, s27, s23 1501; GFX10PLUS-NEXT: s_addc_u32 s24, s28, s24 1502; GFX10PLUS-NEXT: s_mul_i32 s28, s4, s8 1503; GFX10PLUS-NEXT: s_mul_hi_u32 s29, s4, s8 1504; GFX10PLUS-NEXT: s_cselect_b32 s27, 1, 0 1505; GFX10PLUS-NEXT: s_add_u32 s23, s28, s23 1506; GFX10PLUS-NEXT: s_addc_u32 s24, s29, s24 1507; GFX10PLUS-NEXT: s_mul_i32 s29, s0, s11 1508; GFX10PLUS-NEXT: s_mul_hi_u32 s30, s0, s11 1509; GFX10PLUS-NEXT: s_cselect_b32 s28, 1, 0 1510; GFX10PLUS-NEXT: s_add_u32 s18, s29, s18 1511; GFX10PLUS-NEXT: s_addc_u32 s23, s30, s23 1512; GFX10PLUS-NEXT: s_mul_i32 s30, s1, s10 1513; GFX10PLUS-NEXT: s_mul_hi_u32 s31, s1, s10 1514; GFX10PLUS-NEXT: s_cselect_b32 s29, 1, 0 1515; GFX10PLUS-NEXT: s_add_u32 s18, s30, s18 1516; GFX10PLUS-NEXT: s_addc_u32 s23, s31, s23 1517; GFX10PLUS-NEXT: s_mul_i32 s31, s2, s9 1518; GFX10PLUS-NEXT: s_mul_hi_u32 s33, s2, s9 1519; GFX10PLUS-NEXT: s_cselect_b32 s30, 1, 0 1520; GFX10PLUS-NEXT: s_add_u32 s18, s31, s18 1521; GFX10PLUS-NEXT: s_addc_u32 s23, s33, s23 1522; GFX10PLUS-NEXT: s_mul_i32 s33, s3, s8 1523; GFX10PLUS-NEXT: s_mul_hi_u32 s34, s3, s8 1524; GFX10PLUS-NEXT: s_cselect_b32 s31, 1, 0 1525; GFX10PLUS-NEXT: s_add_u32 s18, s33, s18 1526; GFX10PLUS-NEXT: s_addc_u32 s23, s34, s23 1527; GFX10PLUS-NEXT: s_cselect_b32 s33, 1, 0 1528; GFX10PLUS-NEXT: s_cmp_lg_u32 s22, 0 1529; GFX10PLUS-NEXT: s_mul_hi_u32 s22, s0, s14 1530; GFX10PLUS-NEXT: s_addc_u32 s18, s21, s18 1531; GFX10PLUS-NEXT: s_cselect_b32 s21, 1, 0 1532; GFX10PLUS-NEXT: s_cmp_lg_u32 s20, 0 1533; GFX10PLUS-NEXT: s_mul_hi_u32 s34, s1, s13 1534; GFX10PLUS-NEXT: s_addc_u32 s19, s19, 0 1535; GFX10PLUS-NEXT: s_cmp_lg_u32 s21, 0 1536; GFX10PLUS-NEXT: s_mul_i32 s21, s0, s14 1537; GFX10PLUS-NEXT: s_addc_u32 s19, s19, s23 1538; GFX10PLUS-NEXT: s_mul_i32 s23, s1, s13 1539; GFX10PLUS-NEXT: s_cselect_b32 s20, 1, 0 1540; GFX10PLUS-NEXT: s_add_u32 s21, s23, s21 1541; GFX10PLUS-NEXT: s_mul_i32 s23, s2, s12 1542; GFX10PLUS-NEXT: s_addc_u32 s22, s34, s22 1543; GFX10PLUS-NEXT: s_mul_hi_u32 s34, s2, s12 1544; GFX10PLUS-NEXT: s_add_u32 s21, s23, s21 1545; GFX10PLUS-NEXT: s_mul_i32 s23, s3, s11 1546; GFX10PLUS-NEXT: s_addc_u32 s22, s34, s22 1547; GFX10PLUS-NEXT: s_mul_hi_u32 s34, s3, s11 1548; GFX10PLUS-NEXT: s_add_u32 s21, s23, s21 1549; GFX10PLUS-NEXT: s_mul_i32 s23, s4, s10 1550; GFX10PLUS-NEXT: s_addc_u32 s22, s34, s22 1551; GFX10PLUS-NEXT: s_mul_hi_u32 s34, s4, s10 1552; GFX10PLUS-NEXT: s_add_u32 s21, s23, s21 1553; GFX10PLUS-NEXT: s_mul_i32 s23, s5, s9 1554; GFX10PLUS-NEXT: s_addc_u32 s22, s34, s22 1555; GFX10PLUS-NEXT: s_mul_hi_u32 s34, s5, s9 1556; GFX10PLUS-NEXT: s_add_u32 s21, s23, s21 1557; GFX10PLUS-NEXT: s_mul_i32 s23, s6, s8 1558; GFX10PLUS-NEXT: s_addc_u32 s22, s34, s22 1559; GFX10PLUS-NEXT: s_mul_hi_u32 s34, s6, s8 1560; GFX10PLUS-NEXT: s_add_u32 s21, s23, s21 1561; GFX10PLUS-NEXT: s_mul_i32 s23, s0, s13 1562; GFX10PLUS-NEXT: s_addc_u32 s22, s34, s22 1563; GFX10PLUS-NEXT: s_mul_hi_u32 s34, s0, s13 1564; GFX10PLUS-NEXT: s_add_u32 s23, s23, s24 1565; GFX10PLUS-NEXT: s_addc_u32 s21, s34, s21 1566; GFX10PLUS-NEXT: s_mul_i32 s34, s1, s12 1567; GFX10PLUS-NEXT: s_mul_hi_u32 s35, s1, s12 1568; GFX10PLUS-NEXT: s_cselect_b32 s24, 1, 0 1569; GFX10PLUS-NEXT: s_add_u32 s23, s34, s23 1570; GFX10PLUS-NEXT: s_addc_u32 s21, s35, s21 1571; GFX10PLUS-NEXT: s_mul_i32 s35, s2, s11 1572; GFX10PLUS-NEXT: s_mul_hi_u32 s36, s2, s11 1573; GFX10PLUS-NEXT: s_cselect_b32 s34, 1, 0 1574; GFX10PLUS-NEXT: s_add_u32 s23, s35, s23 1575; GFX10PLUS-NEXT: s_addc_u32 s21, s36, s21 1576; GFX10PLUS-NEXT: s_mul_i32 s36, s3, s10 1577; GFX10PLUS-NEXT: s_mul_hi_u32 s37, s3, s10 1578; GFX10PLUS-NEXT: s_cselect_b32 s35, 1, 0 1579; GFX10PLUS-NEXT: s_add_u32 s23, s36, s23 1580; GFX10PLUS-NEXT: s_addc_u32 s21, s37, s21 1581; GFX10PLUS-NEXT: s_mul_i32 s37, s4, s9 1582; GFX10PLUS-NEXT: s_mul_hi_u32 s38, s4, s9 1583; GFX10PLUS-NEXT: s_cselect_b32 s36, 1, 0 1584; GFX10PLUS-NEXT: s_add_u32 s23, s37, s23 1585; GFX10PLUS-NEXT: s_addc_u32 s21, s38, s21 1586; GFX10PLUS-NEXT: s_mul_i32 s38, s5, s8 1587; GFX10PLUS-NEXT: s_mul_hi_u32 s39, s5, s8 1588; GFX10PLUS-NEXT: s_cselect_b32 s37, 1, 0 1589; GFX10PLUS-NEXT: s_add_u32 s23, s38, s23 1590; GFX10PLUS-NEXT: s_addc_u32 s21, s39, s21 1591; GFX10PLUS-NEXT: s_cselect_b32 s38, 1, 0 1592; GFX10PLUS-NEXT: s_cmp_lg_u32 s30, 0 1593; GFX10PLUS-NEXT: s_mul_i32 s1, s1, s14 1594; GFX10PLUS-NEXT: s_addc_u32 s29, s29, 0 1595; GFX10PLUS-NEXT: s_cmp_lg_u32 s31, 0 1596; GFX10PLUS-NEXT: s_mul_i32 s2, s2, s13 1597; GFX10PLUS-NEXT: s_addc_u32 s29, s29, 0 1598; GFX10PLUS-NEXT: s_cmp_lg_u32 s33, 0 1599; GFX10PLUS-NEXT: s_mul_i32 s3, s3, s12 1600; GFX10PLUS-NEXT: s_addc_u32 s29, s29, 0 1601; GFX10PLUS-NEXT: s_cmp_lg_u32 s20, 0 1602; GFX10PLUS-NEXT: s_mul_i32 s4, s4, s11 1603; GFX10PLUS-NEXT: s_addc_u32 s20, s29, s23 1604; GFX10PLUS-NEXT: s_cselect_b32 s23, 1, 0 1605; GFX10PLUS-NEXT: s_cmp_lg_u32 s26, 0 1606; GFX10PLUS-NEXT: s_mul_i32 s26, s0, s15 1607; GFX10PLUS-NEXT: s_addc_u32 s25, s25, 0 1608; GFX10PLUS-NEXT: s_cmp_lg_u32 s27, 0 1609; GFX10PLUS-NEXT: s_mul_i32 s5, s5, s10 1610; GFX10PLUS-NEXT: s_addc_u32 s25, s25, 0 1611; GFX10PLUS-NEXT: s_cmp_lg_u32 s28, 0 1612; GFX10PLUS-NEXT: s_mul_i32 s6, s6, s9 1613; GFX10PLUS-NEXT: s_addc_u32 s25, s25, 0 1614; GFX10PLUS-NEXT: s_cmp_lg_u32 s23, 0 1615; GFX10PLUS-NEXT: s_mul_i32 s7, s7, s8 1616; GFX10PLUS-NEXT: s_addc_u32 s15, s25, s21 1617; GFX10PLUS-NEXT: s_addc_u32 s21, s22, s26 1618; GFX10PLUS-NEXT: s_cmp_lg_u32 s38, 0 1619; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s8 1620; GFX10PLUS-NEXT: s_addc_u32 s1, s21, s1 1621; GFX10PLUS-NEXT: s_cmp_lg_u32 s37, 0 1622; GFX10PLUS-NEXT: s_addc_u32 s1, s1, s2 1623; GFX10PLUS-NEXT: s_cmp_lg_u32 s36, 0 1624; GFX10PLUS-NEXT: s_mov_b32 s2, s17 1625; GFX10PLUS-NEXT: s_addc_u32 s1, s1, s3 1626; GFX10PLUS-NEXT: s_cmp_lg_u32 s35, 0 1627; GFX10PLUS-NEXT: s_mov_b32 s3, s18 1628; GFX10PLUS-NEXT: s_addc_u32 s1, s1, s4 1629; GFX10PLUS-NEXT: s_cmp_lg_u32 s34, 0 1630; GFX10PLUS-NEXT: s_mov_b32 s4, s19 1631; GFX10PLUS-NEXT: s_addc_u32 s1, s1, s5 1632; GFX10PLUS-NEXT: s_cmp_lg_u32 s24, 0 1633; GFX10PLUS-NEXT: s_mov_b32 s5, s20 1634; GFX10PLUS-NEXT: s_addc_u32 s1, s1, s6 1635; GFX10PLUS-NEXT: s_mov_b32 s6, s15 1636; GFX10PLUS-NEXT: s_add_i32 s7, s1, s7 1637; GFX10PLUS-NEXT: s_mov_b32 s1, s16 1638; GFX10PLUS-NEXT: ; return to shader part epilog 1639 %result = mul i256 %num, %den 1640 %cast = bitcast i256 %result to <8 x i32> 1641 ret <8 x i32> %cast 1642} 1643 1644define i256 @v_mul_i256(i256 %num, i256 %den) { 1645; GFX7-LABEL: v_mul_i256: 1646; GFX7: ; %bb.0: 1647; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1648; GFX7-NEXT: v_mov_b32_e32 v16, v0 1649; GFX7-NEXT: v_mov_b32_e32 v17, v1 1650; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v16, v14, 0 1651; GFX7-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v16, v12, 0 1652; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v17, v13, v[0:1] 1653; GFX7-NEXT: v_mul_lo_u32 v27, v3, v12 1654; GFX7-NEXT: v_mul_lo_u32 v26, v5, v10 1655; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v12, v[0:1] 1656; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v3, v11, v[0:1] 1657; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v10, v[0:1] 1658; GFX7-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v17, v11, v[18:19] 1659; GFX7-NEXT: v_cndmask_b32_e64 v20, 0, 1, s[4:5] 1660; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v5, v9, v[0:1] 1661; GFX7-NEXT: v_mad_u64_u32 v[18:19], vcc, v2, v10, v[18:19] 1662; GFX7-NEXT: v_addc_u32_e32 v20, vcc, 0, v20, vcc 1663; GFX7-NEXT: v_mad_u64_u32 v[18:19], vcc, v3, v9, v[18:19] 1664; GFX7-NEXT: v_addc_u32_e32 v22, vcc, 0, v20, vcc 1665; GFX7-NEXT: v_mad_u64_u32 v[18:19], vcc, v4, v8, v[18:19] 1666; GFX7-NEXT: v_addc_u32_e32 v24, vcc, 0, v22, vcc 1667; GFX7-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v16, v10, 0 1668; GFX7-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v6, v8, v[0:1] 1669; GFX7-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v17, v9, v[22:23] 1670; GFX7-NEXT: v_mov_b32_e32 v1, v18 1671; GFX7-NEXT: v_mov_b32_e32 v18, v19 1672; GFX7-NEXT: v_mov_b32_e32 v19, v20 1673; GFX7-NEXT: v_mad_u64_u32 v[18:19], vcc, v16, v13, v[18:19] 1674; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] 1675; GFX7-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v2, v8, v[22:23] 1676; GFX7-NEXT: v_addc_u32_e64 v25, s[4:5], 0, v0, s[4:5] 1677; GFX7-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v17, v12, v[18:19] 1678; GFX7-NEXT: v_mov_b32_e32 v0, v23 1679; GFX7-NEXT: v_mul_lo_u32 v23, v4, v11 1680; GFX7-NEXT: v_mad_u64_u32 v[18:19], s[6:7], v2, v11, v[18:19] 1681; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[12:13], v16, v11, v[0:1] 1682; GFX7-NEXT: v_mad_u64_u32 v[11:12], s[8:9], v3, v10, v[18:19] 1683; GFX7-NEXT: v_mul_lo_u32 v13, v2, v13 1684; GFX7-NEXT: v_mul_lo_u32 v20, v6, v9 1685; GFX7-NEXT: v_mad_u64_u32 v[11:12], s[10:11], v4, v9, v[11:12] 1686; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[12:13] 1687; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[12:13], v17, v10, v[0:1] 1688; GFX7-NEXT: v_addc_u32_e64 v4, s[12:13], 0, v4, s[12:13] 1689; GFX7-NEXT: v_mad_u64_u32 v[18:19], s[12:13], v2, v9, v[0:1] 1690; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[14:15], v16, v8, 0 1691; GFX7-NEXT: v_mov_b32_e32 v2, v22 1692; GFX7-NEXT: v_addc_u32_e64 v10, s[12:13], 0, v4, s[12:13] 1693; GFX7-NEXT: v_mad_u64_u32 v[1:2], s[16:17], v16, v9, v[1:2] 1694; GFX7-NEXT: v_mad_u64_u32 v[3:4], s[12:13], v3, v8, v[18:19] 1695; GFX7-NEXT: v_mad_u64_u32 v[5:6], s[14:15], v5, v8, v[11:12] 1696; GFX7-NEXT: v_addc_u32_e64 v10, s[12:13], 0, v10, s[12:13] 1697; GFX7-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[16:17] 1698; GFX7-NEXT: v_mad_u64_u32 v[1:2], s[12:13], v17, v8, v[1:2] 1699; GFX7-NEXT: v_addc_u32_e64 v3, s[12:13], v11, v3, s[12:13] 1700; GFX7-NEXT: v_mul_lo_u32 v11, v16, v15 1701; GFX7-NEXT: v_mul_lo_u32 v9, v17, v14 1702; GFX7-NEXT: v_addc_u32_e64 v4, s[12:13], v25, v4, s[12:13] 1703; GFX7-NEXT: v_addc_u32_e64 v5, s[12:13], v10, v5, s[12:13] 1704; GFX7-NEXT: v_addc_u32_e64 v6, s[12:13], v24, v6, s[12:13] 1705; GFX7-NEXT: v_addc_u32_e64 v10, s[12:13], v21, v11, s[12:13] 1706; GFX7-NEXT: v_addc_u32_e64 v9, s[12:13], v10, v9, s[14:15] 1707; GFX7-NEXT: v_addc_u32_e64 v9, s[10:11], v9, v13, s[10:11] 1708; GFX7-NEXT: v_addc_u32_e64 v9, s[8:9], v9, v27, s[8:9] 1709; GFX7-NEXT: v_addc_u32_e64 v9, s[6:7], v9, v23, s[6:7] 1710; GFX7-NEXT: v_addc_u32_e64 v9, s[4:5], v9, v26, s[4:5] 1711; GFX7-NEXT: v_addc_u32_e32 v9, vcc, v9, v20, vcc 1712; GFX7-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v7, v8, v[9:10] 1713; GFX7-NEXT: s_setpc_b64 s[30:31] 1714; 1715; GFX8-LABEL: v_mul_i256: 1716; GFX8: ; %bb.0: 1717; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1718; GFX8-NEXT: v_mov_b32_e32 v16, v0 1719; GFX8-NEXT: v_mov_b32_e32 v17, v1 1720; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v16, v14, 0 1721; GFX8-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v16, v12, 0 1722; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v17, v13, v[0:1] 1723; GFX8-NEXT: v_mul_lo_u32 v27, v3, v12 1724; GFX8-NEXT: v_mul_lo_u32 v26, v5, v10 1725; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v12, v[0:1] 1726; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v3, v11, v[0:1] 1727; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v10, v[0:1] 1728; GFX8-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v17, v11, v[18:19] 1729; GFX8-NEXT: v_cndmask_b32_e64 v20, 0, 1, s[4:5] 1730; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v5, v9, v[0:1] 1731; GFX8-NEXT: v_mad_u64_u32 v[18:19], vcc, v2, v10, v[18:19] 1732; GFX8-NEXT: v_addc_u32_e32 v20, vcc, 0, v20, vcc 1733; GFX8-NEXT: v_mad_u64_u32 v[18:19], vcc, v3, v9, v[18:19] 1734; GFX8-NEXT: v_addc_u32_e32 v22, vcc, 0, v20, vcc 1735; GFX8-NEXT: v_mad_u64_u32 v[18:19], vcc, v4, v8, v[18:19] 1736; GFX8-NEXT: v_addc_u32_e32 v24, vcc, 0, v22, vcc 1737; GFX8-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v16, v10, 0 1738; GFX8-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v6, v8, v[0:1] 1739; GFX8-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v17, v9, v[22:23] 1740; GFX8-NEXT: v_mov_b32_e32 v1, v18 1741; GFX8-NEXT: v_mov_b32_e32 v18, v19 1742; GFX8-NEXT: v_mov_b32_e32 v19, v20 1743; GFX8-NEXT: v_mad_u64_u32 v[18:19], vcc, v16, v13, v[18:19] 1744; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] 1745; GFX8-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v2, v8, v[22:23] 1746; GFX8-NEXT: v_addc_u32_e64 v25, s[4:5], 0, v0, s[4:5] 1747; GFX8-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v17, v12, v[18:19] 1748; GFX8-NEXT: v_mov_b32_e32 v0, v23 1749; GFX8-NEXT: v_mul_lo_u32 v23, v4, v11 1750; GFX8-NEXT: v_mad_u64_u32 v[18:19], s[6:7], v2, v11, v[18:19] 1751; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[12:13], v16, v11, v[0:1] 1752; GFX8-NEXT: v_mad_u64_u32 v[11:12], s[8:9], v3, v10, v[18:19] 1753; GFX8-NEXT: v_mul_lo_u32 v13, v2, v13 1754; GFX8-NEXT: v_mul_lo_u32 v20, v6, v9 1755; GFX8-NEXT: v_mad_u64_u32 v[11:12], s[10:11], v4, v9, v[11:12] 1756; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[12:13] 1757; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[12:13], v17, v10, v[0:1] 1758; GFX8-NEXT: v_addc_u32_e64 v4, s[12:13], 0, v4, s[12:13] 1759; GFX8-NEXT: v_mad_u64_u32 v[18:19], s[12:13], v2, v9, v[0:1] 1760; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[14:15], v16, v8, 0 1761; GFX8-NEXT: v_mov_b32_e32 v2, v22 1762; GFX8-NEXT: v_addc_u32_e64 v10, s[12:13], 0, v4, s[12:13] 1763; GFX8-NEXT: v_mad_u64_u32 v[1:2], s[16:17], v16, v9, v[1:2] 1764; GFX8-NEXT: v_mad_u64_u32 v[3:4], s[12:13], v3, v8, v[18:19] 1765; GFX8-NEXT: v_mad_u64_u32 v[5:6], s[14:15], v5, v8, v[11:12] 1766; GFX8-NEXT: v_addc_u32_e64 v10, s[12:13], 0, v10, s[12:13] 1767; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[16:17] 1768; GFX8-NEXT: v_mad_u64_u32 v[1:2], s[12:13], v17, v8, v[1:2] 1769; GFX8-NEXT: v_addc_u32_e64 v3, s[12:13], v11, v3, s[12:13] 1770; GFX8-NEXT: v_mul_lo_u32 v11, v16, v15 1771; GFX8-NEXT: v_mul_lo_u32 v9, v17, v14 1772; GFX8-NEXT: v_addc_u32_e64 v4, s[12:13], v25, v4, s[12:13] 1773; GFX8-NEXT: v_addc_u32_e64 v5, s[12:13], v10, v5, s[12:13] 1774; GFX8-NEXT: v_addc_u32_e64 v6, s[12:13], v24, v6, s[12:13] 1775; GFX8-NEXT: v_addc_u32_e64 v10, s[12:13], v21, v11, s[12:13] 1776; GFX8-NEXT: v_addc_u32_e64 v9, s[12:13], v10, v9, s[14:15] 1777; GFX8-NEXT: v_addc_u32_e64 v9, s[10:11], v9, v13, s[10:11] 1778; GFX8-NEXT: v_addc_u32_e64 v9, s[8:9], v9, v27, s[8:9] 1779; GFX8-NEXT: v_addc_u32_e64 v9, s[6:7], v9, v23, s[6:7] 1780; GFX8-NEXT: v_addc_u32_e64 v9, s[4:5], v9, v26, s[4:5] 1781; GFX8-NEXT: v_addc_u32_e32 v9, vcc, v9, v20, vcc 1782; GFX8-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v7, v8, v[9:10] 1783; GFX8-NEXT: s_setpc_b64 s[30:31] 1784; 1785; GFX9-LABEL: v_mul_i256: 1786; GFX9: ; %bb.0: 1787; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1788; GFX9-NEXT: v_mov_b32_e32 v16, v0 1789; GFX9-NEXT: v_mov_b32_e32 v17, v1 1790; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v16, v14, 0 1791; GFX9-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v16, v12, 0 1792; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v17, v13, v[0:1] 1793; GFX9-NEXT: v_mul_lo_u32 v27, v3, v12 1794; GFX9-NEXT: v_mul_lo_u32 v26, v5, v10 1795; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v12, v[0:1] 1796; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v3, v11, v[0:1] 1797; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v10, v[0:1] 1798; GFX9-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v17, v11, v[18:19] 1799; GFX9-NEXT: v_cndmask_b32_e64 v20, 0, 1, s[4:5] 1800; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v5, v9, v[0:1] 1801; GFX9-NEXT: v_mad_u64_u32 v[18:19], vcc, v2, v10, v[18:19] 1802; GFX9-NEXT: v_addc_co_u32_e32 v20, vcc, 0, v20, vcc 1803; GFX9-NEXT: v_mad_u64_u32 v[18:19], vcc, v3, v9, v[18:19] 1804; GFX9-NEXT: v_addc_co_u32_e32 v22, vcc, 0, v20, vcc 1805; GFX9-NEXT: v_mad_u64_u32 v[18:19], vcc, v4, v8, v[18:19] 1806; GFX9-NEXT: v_addc_co_u32_e32 v24, vcc, 0, v22, vcc 1807; GFX9-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v16, v10, 0 1808; GFX9-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v6, v8, v[0:1] 1809; GFX9-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v17, v9, v[22:23] 1810; GFX9-NEXT: v_mov_b32_e32 v1, v18 1811; GFX9-NEXT: v_mov_b32_e32 v18, v19 1812; GFX9-NEXT: v_mov_b32_e32 v19, v20 1813; GFX9-NEXT: v_mad_u64_u32 v[18:19], vcc, v16, v13, v[18:19] 1814; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] 1815; GFX9-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v2, v8, v[22:23] 1816; GFX9-NEXT: v_addc_co_u32_e64 v25, s[4:5], 0, v0, s[4:5] 1817; GFX9-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v17, v12, v[18:19] 1818; GFX9-NEXT: v_mov_b32_e32 v0, v23 1819; GFX9-NEXT: v_mul_lo_u32 v23, v4, v11 1820; GFX9-NEXT: v_mad_u64_u32 v[18:19], s[6:7], v2, v11, v[18:19] 1821; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[12:13], v16, v11, v[0:1] 1822; GFX9-NEXT: v_mad_u64_u32 v[11:12], s[8:9], v3, v10, v[18:19] 1823; GFX9-NEXT: v_mul_lo_u32 v13, v2, v13 1824; GFX9-NEXT: v_mul_lo_u32 v20, v6, v9 1825; GFX9-NEXT: v_mad_u64_u32 v[11:12], s[10:11], v4, v9, v[11:12] 1826; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[12:13] 1827; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[12:13], v17, v10, v[0:1] 1828; GFX9-NEXT: v_addc_co_u32_e64 v4, s[12:13], 0, v4, s[12:13] 1829; GFX9-NEXT: v_mad_u64_u32 v[18:19], s[12:13], v2, v9, v[0:1] 1830; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[14:15], v16, v8, 0 1831; GFX9-NEXT: v_mov_b32_e32 v2, v22 1832; GFX9-NEXT: v_addc_co_u32_e64 v10, s[12:13], 0, v4, s[12:13] 1833; GFX9-NEXT: v_mad_u64_u32 v[1:2], s[16:17], v16, v9, v[1:2] 1834; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[12:13], v3, v8, v[18:19] 1835; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[14:15], v5, v8, v[11:12] 1836; GFX9-NEXT: v_addc_co_u32_e64 v10, s[12:13], 0, v10, s[12:13] 1837; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[16:17] 1838; GFX9-NEXT: v_mad_u64_u32 v[1:2], s[12:13], v17, v8, v[1:2] 1839; GFX9-NEXT: v_addc_co_u32_e64 v3, s[12:13], v11, v3, s[12:13] 1840; GFX9-NEXT: v_mul_lo_u32 v11, v16, v15 1841; GFX9-NEXT: v_mul_lo_u32 v9, v17, v14 1842; GFX9-NEXT: v_addc_co_u32_e64 v4, s[12:13], v25, v4, s[12:13] 1843; GFX9-NEXT: v_addc_co_u32_e64 v5, s[12:13], v10, v5, s[12:13] 1844; GFX9-NEXT: v_addc_co_u32_e64 v6, s[12:13], v24, v6, s[12:13] 1845; GFX9-NEXT: v_addc_co_u32_e64 v10, s[12:13], v21, v11, s[12:13] 1846; GFX9-NEXT: v_addc_co_u32_e64 v9, s[12:13], v10, v9, s[14:15] 1847; GFX9-NEXT: v_addc_co_u32_e64 v9, s[10:11], v9, v13, s[10:11] 1848; GFX9-NEXT: v_addc_co_u32_e64 v9, s[8:9], v9, v27, s[8:9] 1849; GFX9-NEXT: v_addc_co_u32_e64 v9, s[6:7], v9, v23, s[6:7] 1850; GFX9-NEXT: v_addc_co_u32_e64 v9, s[4:5], v9, v26, s[4:5] 1851; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v9, v20, vcc 1852; GFX9-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v7, v8, v[9:10] 1853; GFX9-NEXT: s_setpc_b64 s[30:31] 1854; 1855; GFX10-LABEL: v_mul_i256: 1856; GFX10: ; %bb.0: 1857; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1858; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1859; GFX10-NEXT: v_mov_b32_e32 v16, v0 1860; GFX10-NEXT: v_mov_b32_e32 v17, v1 1861; GFX10-NEXT: v_mul_lo_u32 v27, v6, v9 1862; GFX10-NEXT: v_mul_lo_u32 v28, v5, v10 1863; GFX10-NEXT: v_mul_lo_u32 v7, v7, v8 1864; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v16, v14, 0 1865; GFX10-NEXT: v_mad_u64_u32 v[18:19], s4, v16, v12, 0 1866; GFX10-NEXT: v_mul_lo_u32 v30, v17, v14 1867; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v17, v13, v[0:1] 1868; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v2, v12, v[0:1] 1869; GFX10-NEXT: v_mad_u64_u32 v[18:19], s4, v17, v11, v[18:19] 1870; GFX10-NEXT: v_cndmask_b32_e64 v20, 0, 1, s4 1871; GFX10-NEXT: v_mad_u64_u32 v[0:1], s5, v3, v11, v[0:1] 1872; GFX10-NEXT: v_mad_u64_u32 v[18:19], vcc_lo, v2, v10, v[18:19] 1873; GFX10-NEXT: v_add_co_ci_u32_e32 v22, vcc_lo, 0, v20, vcc_lo 1874; GFX10-NEXT: v_mad_u64_u32 v[20:21], s4, v16, v10, 0 1875; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v4, v10, v[0:1] 1876; GFX10-NEXT: v_mad_u64_u32 v[18:19], vcc_lo, v3, v9, v[18:19] 1877; GFX10-NEXT: v_add_co_ci_u32_e32 v24, vcc_lo, 0, v22, vcc_lo 1878; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v5, v9, v[0:1] 1879; GFX10-NEXT: v_mad_u64_u32 v[18:19], vcc_lo, v4, v8, v[18:19] 1880; GFX10-NEXT: v_add_co_ci_u32_e32 v26, vcc_lo, 0, v24, vcc_lo 1881; GFX10-NEXT: v_mad_u64_u32 v[22:23], s4, v6, v8, v[0:1] 1882; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v17, v9, v[20:21] 1883; GFX10-NEXT: v_cndmask_b32_e64 v25, 0, 1, s4 1884; GFX10-NEXT: v_mov_b32_e32 v20, v22 1885; GFX10-NEXT: v_mad_u64_u32 v[21:22], vcc_lo, v2, v8, v[0:1] 1886; GFX10-NEXT: v_add_co_ci_u32_e32 v29, vcc_lo, 0, v25, vcc_lo 1887; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v16, v13, v[19:20] 1888; GFX10-NEXT: v_mov_b32_e32 v20, v18 1889; GFX10-NEXT: v_mov_b32_e32 v19, v22 1890; GFX10-NEXT: v_mul_lo_u32 v22, v16, v15 1891; GFX10-NEXT: v_mad_u64_u32 v[24:25], vcc_lo, v17, v12, v[0:1] 1892; GFX10-NEXT: v_mad_u64_u32 v[14:15], s6, v16, v11, v[19:20] 1893; GFX10-NEXT: v_mad_u64_u32 v[0:1], s5, v16, v8, 0 1894; GFX10-NEXT: v_mul_lo_u32 v20, v4, v11 1895; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s6 1896; GFX10-NEXT: v_mad_u64_u32 v[18:19], s5, v2, v11, v[24:25] 1897; GFX10-NEXT: v_mul_lo_u32 v25, v3, v12 1898; GFX10-NEXT: v_mad_u64_u32 v[11:12], s6, v17, v10, v[14:15] 1899; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s6, 0, v6, s6 1900; GFX10-NEXT: v_mul_lo_u32 v24, v2, v13 1901; GFX10-NEXT: v_mad_u64_u32 v[18:19], s7, v3, v10, v[18:19] 1902; GFX10-NEXT: v_mov_b32_e32 v13, v1 1903; GFX10-NEXT: v_mad_u64_u32 v[1:2], s6, v2, v9, v[11:12] 1904; GFX10-NEXT: v_mov_b32_e32 v14, v21 1905; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s6, 0, v6, s6 1906; GFX10-NEXT: v_mad_u64_u32 v[10:11], s6, v4, v9, v[18:19] 1907; GFX10-NEXT: v_mad_u64_u32 v[12:13], s8, v16, v9, v[13:14] 1908; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s8 1909; GFX10-NEXT: v_mad_u64_u32 v[3:4], s8, v3, v8, v[1:2] 1910; GFX10-NEXT: v_add_co_ci_u32_e64 v14, s8, 0, v6, s8 1911; GFX10-NEXT: v_mad_u64_u32 v[5:6], s8, v5, v8, v[10:11] 1912; GFX10-NEXT: v_mad_u64_u32 v[1:2], s9, v17, v8, v[12:13] 1913; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s9, v9, v3, s9 1914; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s9, v29, v4, s9 1915; GFX10-NEXT: v_add_co_ci_u32_e64 v5, s9, v14, v5, s9 1916; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s9, v26, v6, s9 1917; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s9, v23, v22, s9 1918; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s8, v9, v30, s8 1919; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s6, v9, v24, s6 1920; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s6, v9, v25, s7 1921; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s5, v9, v20, s5 1922; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v9, v28, vcc_lo 1923; GFX10-NEXT: v_add_co_ci_u32_e64 v8, vcc_lo, v9, v27, s4 1924; GFX10-NEXT: v_add_nc_u32_e32 v7, v8, v7 1925; GFX10-NEXT: s_setpc_b64 s[30:31] 1926; 1927; GFX11-LABEL: v_mul_i256: 1928; GFX11: ; %bb.0: 1929; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1930; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 1931; GFX11-NEXT: v_dual_mov_b32 v16, v0 :: v_dual_mov_b32 v17, v1 1932; GFX11-NEXT: v_mul_lo_u32 v7, v7, v8 1933; GFX11-NEXT: v_mul_lo_u32 v27, v6, v9 1934; GFX11-NEXT: v_mul_lo_u32 v28, v5, v10 1935; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v16, v14, 0 1936; GFX11-NEXT: v_mad_u64_u32 v[18:19], null, v16, v12, 0 1937; GFX11-NEXT: v_mul_lo_u32 v30, v17, v14 1938; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v17, v13, v[0:1] 1939; GFX11-NEXT: v_mad_u64_u32 v[18:19], s0, v17, v11, v[18:19] 1940; GFX11-NEXT: v_cndmask_b32_e64 v20, 0, 1, s0 1941; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v2, v12, v[0:1] 1942; GFX11-NEXT: v_mad_u64_u32 v[18:19], vcc_lo, v2, v10, v[18:19] 1943; GFX11-NEXT: v_add_co_ci_u32_e32 v22, vcc_lo, 0, v20, vcc_lo 1944; GFX11-NEXT: v_mad_u64_u32 v[20:21], null, v16, v10, 0 1945; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v3, v11, v[0:1] 1946; GFX11-NEXT: v_mad_u64_u32 v[18:19], vcc_lo, v3, v9, v[18:19] 1947; GFX11-NEXT: v_add_co_ci_u32_e32 v24, vcc_lo, 0, v22, vcc_lo 1948; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v4, v10, v[0:1] 1949; GFX11-NEXT: v_mad_u64_u32 v[18:19], vcc_lo, v4, v8, v[18:19] 1950; GFX11-NEXT: v_add_co_ci_u32_e32 v26, vcc_lo, 0, v24, vcc_lo 1951; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v5, v9, v[0:1] 1952; GFX11-NEXT: v_mad_u64_u32 v[22:23], null, v6, v8, v[0:1] 1953; GFX11-NEXT: v_mad_u64_u32 v[0:1], s0, v17, v9, v[20:21] 1954; GFX11-NEXT: v_cndmask_b32_e64 v25, 0, 1, s0 1955; GFX11-NEXT: v_mov_b32_e32 v20, v22 1956; GFX11-NEXT: v_mad_u64_u32 v[21:22], vcc_lo, v2, v8, v[0:1] 1957; GFX11-NEXT: v_add_co_ci_u32_e32 v29, vcc_lo, 0, v25, vcc_lo 1958; GFX11-NEXT: v_mad_u64_u32 v[0:1], s0, v16, v13, v[19:20] 1959; GFX11-NEXT: v_mov_b32_e32 v20, v18 1960; GFX11-NEXT: v_mov_b32_e32 v19, v22 1961; GFX11-NEXT: v_mul_lo_u32 v22, v16, v15 1962; GFX11-NEXT: v_mad_u64_u32 v[24:25], vcc_lo, v17, v12, v[0:1] 1963; GFX11-NEXT: v_mad_u64_u32 v[14:15], s2, v16, v11, v[19:20] 1964; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v16, v8, 0 1965; GFX11-NEXT: v_mul_lo_u32 v20, v4, v11 1966; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 1, s2 1967; GFX11-NEXT: v_mad_u64_u32 v[18:19], s1, v2, v11, v[24:25] 1968; GFX11-NEXT: v_mul_lo_u32 v25, v3, v12 1969; GFX11-NEXT: v_mad_u64_u32 v[11:12], s2, v17, v10, v[14:15] 1970; GFX11-NEXT: v_mov_b32_e32 v14, v21 1971; GFX11-NEXT: v_add_co_ci_u32_e64 v6, s2, 0, v6, s2 1972; GFX11-NEXT: v_mad_u64_u32 v[18:19], s3, v3, v10, v[18:19] 1973; GFX11-NEXT: v_mul_lo_u32 v24, v2, v13 1974; GFX11-NEXT: v_mov_b32_e32 v13, v1 1975; GFX11-NEXT: v_mad_u64_u32 v[1:2], s2, v2, v9, v[11:12] 1976; GFX11-NEXT: v_add_co_ci_u32_e64 v6, s2, 0, v6, s2 1977; GFX11-NEXT: v_mad_u64_u32 v[10:11], s2, v4, v9, v[18:19] 1978; GFX11-NEXT: v_mad_u64_u32 v[12:13], s4, v16, v9, v[13:14] 1979; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, 1, s4 1980; GFX11-NEXT: v_mad_u64_u32 v[3:4], s4, v3, v8, v[1:2] 1981; GFX11-NEXT: v_add_co_ci_u32_e64 v14, s4, 0, v6, s4 1982; GFX11-NEXT: v_mad_u64_u32 v[5:6], s4, v5, v8, v[10:11] 1983; GFX11-NEXT: v_mad_u64_u32 v[1:2], s5, v17, v8, v[12:13] 1984; GFX11-NEXT: v_add_co_ci_u32_e64 v3, s5, v9, v3, s5 1985; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s5, v29, v4, s5 1986; GFX11-NEXT: v_add_co_ci_u32_e64 v5, s5, v14, v5, s5 1987; GFX11-NEXT: v_add_co_ci_u32_e64 v6, s5, v26, v6, s5 1988; GFX11-NEXT: v_add_co_ci_u32_e64 v9, s5, v23, v22, s5 1989; GFX11-NEXT: v_add_co_ci_u32_e64 v9, s4, v9, v30, s4 1990; GFX11-NEXT: v_add_co_ci_u32_e64 v9, s2, v9, v24, s2 1991; GFX11-NEXT: v_add_co_ci_u32_e64 v9, s2, v9, v25, s3 1992; GFX11-NEXT: v_add_co_ci_u32_e64 v9, s1, v9, v20, s1 1993; GFX11-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v9, v28, vcc_lo 1994; GFX11-NEXT: v_add_co_ci_u32_e64 v8, vcc_lo, v9, v27, s0 1995; GFX11-NEXT: v_add_nc_u32_e32 v7, v8, v7 1996; GFX11-NEXT: s_setpc_b64 s[30:31] 1997 %result = mul i256 %num, %den 1998 ret i256 %result 1999} 2000