1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX7 %s 3; RUN: llc -global-isel -march=amdgcn -mcpu=gfx801 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8 %s 4; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s 5; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s 6 7define amdgpu_ps i16 @s_mul_i16(i16 inreg %num, i16 inreg %den) { 8; GFX7-LABEL: s_mul_i16: 9; GFX7: ; %bb.0: 10; GFX7-NEXT: s_mul_i32 s0, s0, s1 11; GFX7-NEXT: ; return to shader part epilog 12; 13; GFX8-LABEL: s_mul_i16: 14; GFX8: ; %bb.0: 15; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 16; GFX8-NEXT: s_and_b32 s1, s1, 0xffff 17; GFX8-NEXT: s_mul_i32 s0, s0, s1 18; GFX8-NEXT: ; return to shader part epilog 19; 20; GFX9-LABEL: s_mul_i16: 21; GFX9: ; %bb.0: 22; GFX9-NEXT: s_and_b32 s0, s0, 0xffff 23; GFX9-NEXT: s_and_b32 s1, s1, 0xffff 24; GFX9-NEXT: s_mul_i32 s0, s0, s1 25; GFX9-NEXT: ; return to shader part epilog 26; 27; GFX10-LABEL: s_mul_i16: 28; GFX10: ; %bb.0: 29; GFX10-NEXT: s_and_b32 s0, s0, 0xffff 30; GFX10-NEXT: s_and_b32 s1, s1, 0xffff 31; GFX10-NEXT: s_mul_i32 s0, s0, s1 32; GFX10-NEXT: ; return to shader part epilog 33 %result = mul i16 %num, %den 34 ret i16 %result 35} 36 37define i16 @v_mul_i16(i16 %num, i16 %den) { 38; GFX7-LABEL: v_mul_i16: 39; GFX7: ; %bb.0: 40; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 41; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0 42; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1 43; GFX7-NEXT: v_mul_u32_u24_e32 v0, v0, v1 44; GFX7-NEXT: s_setpc_b64 s[30:31] 45; 46; GFX8-LABEL: v_mul_i16: 47; GFX8: ; %bb.0: 48; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 49; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v1 50; GFX8-NEXT: s_setpc_b64 s[30:31] 51; 52; GFX9-LABEL: v_mul_i16: 53; GFX9: ; %bb.0: 54; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 55; GFX9-NEXT: v_mul_lo_u16_e32 v0, v0, v1 56; GFX9-NEXT: s_setpc_b64 s[30:31] 57; 58; GFX10-LABEL: v_mul_i16: 59; GFX10: ; %bb.0: 60; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 61; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 62; GFX10-NEXT: v_mul_lo_u16 v0, v0, v1 63; GFX10-NEXT: s_setpc_b64 s[30:31] 64 %result = mul i16 %num, %den 65 ret i16 %result 66} 67 68define amdgpu_ps zeroext i16 @s_mul_i16_zeroext(i16 inreg zeroext %num, i16 inreg zeroext %den) { 69; GFX7-LABEL: s_mul_i16_zeroext: 70; GFX7: ; %bb.0: 71; GFX7-NEXT: s_mul_i32 s0, s0, s1 72; GFX7-NEXT: s_and_b32 s0, s0, 0xffff 73; GFX7-NEXT: ; return to shader part epilog 74; 75; GFX8-LABEL: s_mul_i16_zeroext: 76; GFX8: ; %bb.0: 77; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 78; GFX8-NEXT: s_and_b32 s1, s1, 0xffff 79; GFX8-NEXT: s_mul_i32 s0, s0, s1 80; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 81; GFX8-NEXT: ; return to shader part epilog 82; 83; GFX9-LABEL: s_mul_i16_zeroext: 84; GFX9: ; %bb.0: 85; GFX9-NEXT: s_and_b32 s0, s0, 0xffff 86; GFX9-NEXT: s_and_b32 s1, s1, 0xffff 87; GFX9-NEXT: s_mul_i32 s0, s0, s1 88; GFX9-NEXT: s_and_b32 s0, s0, 0xffff 89; GFX9-NEXT: ; return to shader part epilog 90; 91; GFX10-LABEL: s_mul_i16_zeroext: 92; GFX10: ; %bb.0: 93; GFX10-NEXT: s_and_b32 s0, s0, 0xffff 94; GFX10-NEXT: s_and_b32 s1, s1, 0xffff 95; GFX10-NEXT: s_mul_i32 s0, s0, s1 96; GFX10-NEXT: s_and_b32 s0, s0, 0xffff 97; GFX10-NEXT: ; return to shader part epilog 98 %result = mul i16 %num, %den 99 ret i16 %result 100} 101 102define zeroext i16 @v_mul_i16_zeroext(i16 zeroext %num, i16 zeroext %den) { 103; GFX7-LABEL: v_mul_i16_zeroext: 104; GFX7: ; %bb.0: 105; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 106; GFX7-NEXT: v_mul_u32_u24_e32 v0, v0, v1 107; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0 108; GFX7-NEXT: s_setpc_b64 s[30:31] 109; 110; GFX8-LABEL: v_mul_i16_zeroext: 111; GFX8: ; %bb.0: 112; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 113; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v1 114; GFX8-NEXT: s_setpc_b64 s[30:31] 115; 116; GFX9-LABEL: v_mul_i16_zeroext: 117; GFX9: ; %bb.0: 118; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 119; GFX9-NEXT: v_mul_lo_u16_e32 v0, v0, v1 120; GFX9-NEXT: s_setpc_b64 s[30:31] 121; 122; GFX10-LABEL: v_mul_i16_zeroext: 123; GFX10: ; %bb.0: 124; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 125; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 126; GFX10-NEXT: v_mul_lo_u16 v0, v0, v1 127; GFX10-NEXT: v_bfe_u32 v0, v0, 0, 16 128; GFX10-NEXT: s_setpc_b64 s[30:31] 129 %result = mul i16 %num, %den 130 ret i16 %result 131} 132 133define amdgpu_ps signext i16 @s_mul_i16_signext(i16 inreg signext %num, i16 inreg signext %den) { 134; GFX7-LABEL: s_mul_i16_signext: 135; GFX7: ; %bb.0: 136; GFX7-NEXT: s_mul_i32 s0, s0, s1 137; GFX7-NEXT: s_sext_i32_i16 s0, s0 138; GFX7-NEXT: ; return to shader part epilog 139; 140; GFX8-LABEL: s_mul_i16_signext: 141; GFX8: ; %bb.0: 142; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 143; GFX8-NEXT: s_and_b32 s1, s1, 0xffff 144; GFX8-NEXT: s_mul_i32 s0, s0, s1 145; GFX8-NEXT: s_sext_i32_i16 s0, s0 146; GFX8-NEXT: ; return to shader part epilog 147; 148; GFX9-LABEL: s_mul_i16_signext: 149; GFX9: ; %bb.0: 150; GFX9-NEXT: s_and_b32 s0, s0, 0xffff 151; GFX9-NEXT: s_and_b32 s1, s1, 0xffff 152; GFX9-NEXT: s_mul_i32 s0, s0, s1 153; GFX9-NEXT: s_sext_i32_i16 s0, s0 154; GFX9-NEXT: ; return to shader part epilog 155; 156; GFX10-LABEL: s_mul_i16_signext: 157; GFX10: ; %bb.0: 158; GFX10-NEXT: s_and_b32 s0, s0, 0xffff 159; GFX10-NEXT: s_and_b32 s1, s1, 0xffff 160; GFX10-NEXT: s_mul_i32 s0, s0, s1 161; GFX10-NEXT: s_sext_i32_i16 s0, s0 162; GFX10-NEXT: ; return to shader part epilog 163 %result = mul i16 %num, %den 164 ret i16 %result 165} 166 167define signext i16 @v_mul_i16_signext(i16 signext %num, i16 signext %den) { 168; GFX7-LABEL: v_mul_i16_signext: 169; GFX7: ; %bb.0: 170; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 171; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0 172; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1 173; GFX7-NEXT: v_mul_u32_u24_e32 v0, v0, v1 174; GFX7-NEXT: v_bfe_i32 v0, v0, 0, 16 175; GFX7-NEXT: s_setpc_b64 s[30:31] 176; 177; GFX8-LABEL: v_mul_i16_signext: 178; GFX8: ; %bb.0: 179; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 180; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v1 181; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 16 182; GFX8-NEXT: s_setpc_b64 s[30:31] 183; 184; GFX9-LABEL: v_mul_i16_signext: 185; GFX9: ; %bb.0: 186; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 187; GFX9-NEXT: v_mul_lo_u16_e32 v0, v0, v1 188; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16 189; GFX9-NEXT: s_setpc_b64 s[30:31] 190; 191; GFX10-LABEL: v_mul_i16_signext: 192; GFX10: ; %bb.0: 193; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 194; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 195; GFX10-NEXT: v_mul_lo_u16 v0, v0, v1 196; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 16 197; GFX10-NEXT: s_setpc_b64 s[30:31] 198 %result = mul i16 %num, %den 199 ret i16 %result 200} 201 202define amdgpu_ps i32 @s_mul_i32(i32 inreg %num, i32 inreg %den) { 203; GCN-LABEL: s_mul_i32: 204; GCN: ; %bb.0: 205; GCN-NEXT: s_mul_i32 s0, s0, s1 206; GCN-NEXT: ; return to shader part epilog 207; 208; GFX10-LABEL: s_mul_i32: 209; GFX10: ; %bb.0: 210; GFX10-NEXT: s_mul_i32 s0, s0, s1 211; GFX10-NEXT: ; return to shader part epilog 212 %result = mul i32 %num, %den 213 ret i32 %result 214} 215 216define i32 @v_mul_i32(i32 %num, i32 %den) { 217; GCN-LABEL: v_mul_i32: 218; GCN: ; %bb.0: 219; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 220; GCN-NEXT: v_mul_lo_u32 v0, v0, v1 221; GCN-NEXT: s_setpc_b64 s[30:31] 222; 223; GFX10-LABEL: v_mul_i32: 224; GFX10: ; %bb.0: 225; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 226; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 227; GFX10-NEXT: v_mul_lo_u32 v0, v0, v1 228; GFX10-NEXT: s_setpc_b64 s[30:31] 229 %result = mul i32 %num, %den 230 ret i32 %result 231} 232 233define amdgpu_ps <2 x i32> @s_mul_v2i32(<2 x i32> inreg %num, <2 x i32> inreg %den) { 234; GCN-LABEL: s_mul_v2i32: 235; GCN: ; %bb.0: 236; GCN-NEXT: s_mul_i32 s0, s0, s2 237; GCN-NEXT: s_mul_i32 s1, s1, s3 238; GCN-NEXT: ; return to shader part epilog 239; 240; GFX10-LABEL: s_mul_v2i32: 241; GFX10: ; %bb.0: 242; GFX10-NEXT: s_mul_i32 s0, s0, s2 243; GFX10-NEXT: s_mul_i32 s1, s1, s3 244; GFX10-NEXT: ; return to shader part epilog 245 %result = mul <2 x i32> %num, %den 246 ret <2 x i32> %result 247} 248 249define <2 x i32> @v_mul_v2i32(<2 x i32> %num, <2 x i32> %den) { 250; GCN-LABEL: v_mul_v2i32: 251; GCN: ; %bb.0: 252; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 253; GCN-NEXT: v_mul_lo_u32 v0, v0, v2 254; GCN-NEXT: v_mul_lo_u32 v1, v1, v3 255; GCN-NEXT: s_setpc_b64 s[30:31] 256; 257; GFX10-LABEL: v_mul_v2i32: 258; GFX10: ; %bb.0: 259; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 260; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 261; GFX10-NEXT: v_mul_lo_u32 v0, v0, v2 262; GFX10-NEXT: v_mul_lo_u32 v1, v1, v3 263; GFX10-NEXT: s_setpc_b64 s[30:31] 264 %result = mul <2 x i32> %num, %den 265 ret <2 x i32> %result 266} 267 268define amdgpu_cs i33 @s_mul_i33(i33 inreg %num, i33 inreg %den) { 269; GFX7-LABEL: s_mul_i33: 270; GFX7: ; %bb.0: 271; GFX7-NEXT: v_mov_b32_e32 v0, s2 272; GFX7-NEXT: v_mul_hi_u32 v0, s0, v0 273; GFX7-NEXT: s_mul_i32 s4, s0, s2 274; GFX7-NEXT: s_mul_i32 s1, s1, s2 275; GFX7-NEXT: s_mul_i32 s0, s0, s3 276; GFX7-NEXT: s_add_i32 s1, s1, s0 277; GFX7-NEXT: v_add_i32_e32 v0, vcc, s1, v0 278; GFX7-NEXT: v_readfirstlane_b32 s1, v0 279; GFX7-NEXT: s_mov_b32 s0, s4 280; GFX7-NEXT: ; return to shader part epilog 281; 282; GFX8-LABEL: s_mul_i33: 283; GFX8: ; %bb.0: 284; GFX8-NEXT: v_mov_b32_e32 v0, s2 285; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0 286; GFX8-NEXT: s_mul_i32 s4, s0, s2 287; GFX8-NEXT: s_mul_i32 s1, s1, s2 288; GFX8-NEXT: s_mul_i32 s0, s0, s3 289; GFX8-NEXT: s_add_i32 s1, s1, s0 290; GFX8-NEXT: v_add_u32_e32 v0, vcc, s1, v0 291; GFX8-NEXT: v_readfirstlane_b32 s1, v0 292; GFX8-NEXT: s_mov_b32 s0, s4 293; GFX8-NEXT: ; return to shader part epilog 294; 295; GFX9-LABEL: s_mul_i33: 296; GFX9: ; %bb.0: 297; GFX9-NEXT: s_mul_i32 s1, s1, s2 298; GFX9-NEXT: s_mul_i32 s3, s0, s3 299; GFX9-NEXT: s_mul_i32 s4, s0, s2 300; GFX9-NEXT: s_mul_hi_u32 s0, s0, s2 301; GFX9-NEXT: s_add_i32 s1, s1, s3 302; GFX9-NEXT: s_add_i32 s1, s1, s0 303; GFX9-NEXT: s_mov_b32 s0, s4 304; GFX9-NEXT: ; return to shader part epilog 305; 306; GFX10-LABEL: s_mul_i33: 307; GFX10: ; %bb.0: 308; GFX10-NEXT: s_mul_i32 s1, s1, s2 309; GFX10-NEXT: s_mul_i32 s3, s0, s3 310; GFX10-NEXT: s_mul_hi_u32 s4, s0, s2 311; GFX10-NEXT: s_add_i32 s1, s1, s3 312; GFX10-NEXT: s_mul_i32 s0, s0, s2 313; GFX10-NEXT: s_add_i32 s1, s1, s4 314; GFX10-NEXT: ; return to shader part epilog 315 %result = mul i33 %num, %den 316 ret i33 %result 317} 318 319define amdgpu_ps i64 @s_mul_i64(i64 inreg %num, i64 inreg %den) { 320; GFX7-LABEL: s_mul_i64: 321; GFX7: ; %bb.0: 322; GFX7-NEXT: v_mov_b32_e32 v0, s2 323; GFX7-NEXT: v_mul_hi_u32 v0, s0, v0 324; GFX7-NEXT: s_mul_i32 s4, s0, s2 325; GFX7-NEXT: s_mul_i32 s1, s1, s2 326; GFX7-NEXT: s_mul_i32 s0, s0, s3 327; GFX7-NEXT: s_add_i32 s1, s1, s0 328; GFX7-NEXT: v_add_i32_e32 v0, vcc, s1, v0 329; GFX7-NEXT: v_readfirstlane_b32 s1, v0 330; GFX7-NEXT: s_mov_b32 s0, s4 331; GFX7-NEXT: ; return to shader part epilog 332; 333; GFX8-LABEL: s_mul_i64: 334; GFX8: ; %bb.0: 335; GFX8-NEXT: v_mov_b32_e32 v0, s2 336; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0 337; GFX8-NEXT: s_mul_i32 s4, s0, s2 338; GFX8-NEXT: s_mul_i32 s1, s1, s2 339; GFX8-NEXT: s_mul_i32 s0, s0, s3 340; GFX8-NEXT: s_add_i32 s1, s1, s0 341; GFX8-NEXT: v_add_u32_e32 v0, vcc, s1, v0 342; GFX8-NEXT: v_readfirstlane_b32 s1, v0 343; GFX8-NEXT: s_mov_b32 s0, s4 344; GFX8-NEXT: ; return to shader part epilog 345; 346; GFX9-LABEL: s_mul_i64: 347; GFX9: ; %bb.0: 348; GFX9-NEXT: s_mul_i32 s1, s1, s2 349; GFX9-NEXT: s_mul_i32 s3, s0, s3 350; GFX9-NEXT: s_mul_i32 s4, s0, s2 351; GFX9-NEXT: s_mul_hi_u32 s0, s0, s2 352; GFX9-NEXT: s_add_i32 s1, s1, s3 353; GFX9-NEXT: s_add_i32 s1, s1, s0 354; GFX9-NEXT: s_mov_b32 s0, s4 355; GFX9-NEXT: ; return to shader part epilog 356; 357; GFX10-LABEL: s_mul_i64: 358; GFX10: ; %bb.0: 359; GFX10-NEXT: s_mul_i32 s1, s1, s2 360; GFX10-NEXT: s_mul_i32 s3, s0, s3 361; GFX10-NEXT: s_mul_hi_u32 s4, s0, s2 362; GFX10-NEXT: s_add_i32 s1, s1, s3 363; GFX10-NEXT: s_mul_i32 s0, s0, s2 364; GFX10-NEXT: s_add_i32 s1, s1, s4 365; GFX10-NEXT: ; return to shader part epilog 366 %result = mul i64 %num, %den 367 ret i64 %result 368} 369 370define i64 @v_mul_i64(i64 %num, i64 %den) { 371; GFX7-LABEL: v_mul_i64: 372; GFX7: ; %bb.0: 373; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 374; GFX7-NEXT: v_mul_lo_u32 v1, v1, v2 375; GFX7-NEXT: v_mul_lo_u32 v4, v0, v3 376; GFX7-NEXT: v_mul_lo_u32 v3, v0, v2 377; GFX7-NEXT: v_mul_hi_u32 v0, v0, v2 378; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v4 379; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v0 380; GFX7-NEXT: v_mov_b32_e32 v0, v3 381; GFX7-NEXT: s_setpc_b64 s[30:31] 382; 383; GFX8-LABEL: v_mul_i64: 384; GFX8: ; %bb.0: 385; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 386; GFX8-NEXT: v_mul_lo_u32 v1, v1, v2 387; GFX8-NEXT: v_mul_lo_u32 v4, v0, v3 388; GFX8-NEXT: v_mul_lo_u32 v3, v0, v2 389; GFX8-NEXT: v_mul_hi_u32 v0, v0, v2 390; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v4 391; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v0 392; GFX8-NEXT: v_mov_b32_e32 v0, v3 393; GFX8-NEXT: s_setpc_b64 s[30:31] 394; 395; GFX9-LABEL: v_mul_i64: 396; GFX9: ; %bb.0: 397; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 398; GFX9-NEXT: v_mul_lo_u32 v1, v1, v2 399; GFX9-NEXT: v_mul_lo_u32 v3, v0, v3 400; GFX9-NEXT: v_mul_hi_u32 v4, v0, v2 401; GFX9-NEXT: v_mul_lo_u32 v0, v0, v2 402; GFX9-NEXT: v_add3_u32 v1, v1, v3, v4 403; GFX9-NEXT: s_setpc_b64 s[30:31] 404; 405; GFX10-LABEL: v_mul_i64: 406; GFX10: ; %bb.0: 407; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 408; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 409; GFX10-NEXT: v_mul_lo_u32 v1, v1, v2 410; GFX10-NEXT: v_mul_lo_u32 v3, v0, v3 411; GFX10-NEXT: v_mul_hi_u32 v4, v0, v2 412; GFX10-NEXT: v_mul_lo_u32 v0, v0, v2 413; GFX10-NEXT: v_add3_u32 v1, v1, v3, v4 414; GFX10-NEXT: s_setpc_b64 s[30:31] 415 %result = mul i64 %num, %den 416 ret i64 %result 417} 418 419define amdgpu_ps <3 x i32> @s_mul_i96(i96 inreg %num, i96 inreg %den) { 420; GFX7-LABEL: s_mul_i96: 421; GFX7: ; %bb.0: 422; GFX7-NEXT: v_mov_b32_e32 v0, s3 423; GFX7-NEXT: v_mul_hi_u32 v0, s0, v0 424; GFX7-NEXT: s_mul_i32 s7, s1, s3 425; GFX7-NEXT: s_mul_i32 s8, s0, s4 426; GFX7-NEXT: v_mov_b32_e32 v2, s1 427; GFX7-NEXT: s_add_u32 s7, s7, s8 428; GFX7-NEXT: v_mul_hi_u32 v2, v2, s3 429; GFX7-NEXT: v_mov_b32_e32 v3, s4 430; GFX7-NEXT: v_add_i32_e32 v0, vcc, s7, v0 431; GFX7-NEXT: s_mul_i32 s2, s2, s3 432; GFX7-NEXT: s_mul_i32 s7, s1, s4 433; GFX7-NEXT: v_mul_hi_u32 v3, s0, v3 434; GFX7-NEXT: s_mul_i32 s6, s0, s3 435; GFX7-NEXT: s_cselect_b32 s8, 1, 0 436; GFX7-NEXT: s_mul_i32 s5, s0, s5 437; GFX7-NEXT: s_add_i32 s0, s2, s7 438; GFX7-NEXT: s_add_i32 s0, s0, s5 439; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc 440; GFX7-NEXT: v_add_i32_e32 v2, vcc, s0, v2 441; GFX7-NEXT: v_add_i32_e32 v1, vcc, s8, v1 442; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v3 443; GFX7-NEXT: v_add_i32_e32 v1, vcc, v2, v1 444; GFX7-NEXT: v_readfirstlane_b32 s1, v0 445; GFX7-NEXT: v_readfirstlane_b32 s2, v1 446; GFX7-NEXT: s_mov_b32 s0, s6 447; GFX7-NEXT: ; return to shader part epilog 448; 449; GFX8-LABEL: s_mul_i96: 450; GFX8: ; %bb.0: 451; GFX8-NEXT: v_mov_b32_e32 v0, s3 452; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0 453; GFX8-NEXT: s_mul_i32 s7, s1, s3 454; GFX8-NEXT: s_mul_i32 s8, s0, s4 455; GFX8-NEXT: v_mov_b32_e32 v2, s1 456; GFX8-NEXT: s_add_u32 s7, s7, s8 457; GFX8-NEXT: v_mul_hi_u32 v2, v2, s3 458; GFX8-NEXT: v_mov_b32_e32 v3, s4 459; GFX8-NEXT: v_add_u32_e32 v0, vcc, s7, v0 460; GFX8-NEXT: s_mul_i32 s2, s2, s3 461; GFX8-NEXT: s_mul_i32 s7, s1, s4 462; GFX8-NEXT: v_mul_hi_u32 v3, s0, v3 463; GFX8-NEXT: s_mul_i32 s6, s0, s3 464; GFX8-NEXT: s_cselect_b32 s8, 1, 0 465; GFX8-NEXT: s_mul_i32 s5, s0, s5 466; GFX8-NEXT: s_add_i32 s0, s2, s7 467; GFX8-NEXT: s_add_i32 s0, s0, s5 468; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc 469; GFX8-NEXT: v_add_u32_e32 v2, vcc, s0, v2 470; GFX8-NEXT: v_add_u32_e32 v1, vcc, s8, v1 471; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3 472; GFX8-NEXT: v_add_u32_e32 v1, vcc, v2, v1 473; GFX8-NEXT: v_readfirstlane_b32 s1, v0 474; GFX8-NEXT: v_readfirstlane_b32 s2, v1 475; GFX8-NEXT: s_mov_b32 s0, s6 476; GFX8-NEXT: ; return to shader part epilog 477; 478; GFX9-LABEL: s_mul_i96: 479; GFX9: ; %bb.0: 480; GFX9-NEXT: s_mul_i32 s7, s1, s3 481; GFX9-NEXT: s_mul_i32 s8, s0, s4 482; GFX9-NEXT: s_mul_hi_u32 s9, s0, s3 483; GFX9-NEXT: s_add_u32 s7, s7, s8 484; GFX9-NEXT: s_cselect_b32 s8, 1, 0 485; GFX9-NEXT: s_add_u32 s7, s7, s9 486; GFX9-NEXT: s_cselect_b32 s9, 1, 0 487; GFX9-NEXT: s_add_i32 s8, s8, s9 488; GFX9-NEXT: s_mul_i32 s2, s2, s3 489; GFX9-NEXT: s_mul_i32 s9, s1, s4 490; GFX9-NEXT: s_mul_i32 s5, s0, s5 491; GFX9-NEXT: s_add_i32 s2, s2, s9 492; GFX9-NEXT: s_mul_hi_u32 s1, s1, s3 493; GFX9-NEXT: s_add_i32 s2, s2, s5 494; GFX9-NEXT: s_mul_i32 s6, s0, s3 495; GFX9-NEXT: s_mul_hi_u32 s0, s0, s4 496; GFX9-NEXT: s_add_i32 s1, s2, s1 497; GFX9-NEXT: s_add_i32 s0, s1, s0 498; GFX9-NEXT: s_add_i32 s2, s0, s8 499; GFX9-NEXT: s_mov_b32 s0, s6 500; GFX9-NEXT: s_mov_b32 s1, s7 501; GFX9-NEXT: ; return to shader part epilog 502; 503; GFX10-LABEL: s_mul_i96: 504; GFX10: ; %bb.0: 505; GFX10-NEXT: s_mul_i32 s6, s1, s3 506; GFX10-NEXT: s_mul_i32 s7, s0, s4 507; GFX10-NEXT: s_mul_hi_u32 s8, s0, s3 508; GFX10-NEXT: s_add_u32 s6, s6, s7 509; GFX10-NEXT: s_mul_i32 s2, s2, s3 510; GFX10-NEXT: s_mul_i32 s9, s1, s4 511; GFX10-NEXT: s_cselect_b32 s7, 1, 0 512; GFX10-NEXT: s_add_u32 s6, s6, s8 513; GFX10-NEXT: s_cselect_b32 s8, 1, 0 514; GFX10-NEXT: s_mul_i32 s5, s0, s5 515; GFX10-NEXT: s_add_i32 s2, s2, s9 516; GFX10-NEXT: s_mul_hi_u32 s1, s1, s3 517; GFX10-NEXT: s_add_i32 s2, s2, s5 518; GFX10-NEXT: s_mul_hi_u32 s4, s0, s4 519; GFX10-NEXT: s_add_i32 s1, s2, s1 520; GFX10-NEXT: s_add_i32 s7, s7, s8 521; GFX10-NEXT: s_add_i32 s1, s1, s4 522; GFX10-NEXT: s_mul_i32 s0, s0, s3 523; GFX10-NEXT: s_add_i32 s2, s1, s7 524; GFX10-NEXT: s_mov_b32 s1, s6 525; GFX10-NEXT: ; return to shader part epilog 526 %result = mul i96 %num, %den 527 %cast = bitcast i96 %result to <3 x i32> 528 ret <3 x i32> %cast 529} 530 531define i96 @v_mul_i96(i96 %num, i96 %den) { 532; GFX7-LABEL: v_mul_i96: 533; GFX7: ; %bb.0: 534; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 535; GFX7-NEXT: v_mul_lo_u32 v7, v1, v3 536; GFX7-NEXT: v_mul_lo_u32 v8, v0, v4 537; GFX7-NEXT: v_mul_hi_u32 v9, v0, v3 538; GFX7-NEXT: v_mul_lo_u32 v2, v2, v3 539; GFX7-NEXT: v_mul_lo_u32 v5, v0, v5 540; GFX7-NEXT: v_add_i32_e32 v7, vcc, v7, v8 541; GFX7-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc 542; GFX7-NEXT: v_add_i32_e32 v7, vcc, v7, v9 543; GFX7-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc 544; GFX7-NEXT: v_add_i32_e32 v8, vcc, v8, v9 545; GFX7-NEXT: v_mul_lo_u32 v9, v1, v4 546; GFX7-NEXT: v_mul_hi_u32 v1, v1, v3 547; GFX7-NEXT: v_mul_lo_u32 v6, v0, v3 548; GFX7-NEXT: v_mul_hi_u32 v0, v0, v4 549; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v9 550; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v5 551; GFX7-NEXT: v_add_i32_e32 v1, vcc, v2, v1 552; GFX7-NEXT: v_add_i32_e32 v0, vcc, v1, v0 553; GFX7-NEXT: v_add_i32_e32 v2, vcc, v0, v8 554; GFX7-NEXT: v_mov_b32_e32 v0, v6 555; GFX7-NEXT: v_mov_b32_e32 v1, v7 556; GFX7-NEXT: s_setpc_b64 s[30:31] 557; 558; GFX8-LABEL: v_mul_i96: 559; GFX8: ; %bb.0: 560; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 561; GFX8-NEXT: v_mul_lo_u32 v7, v1, v3 562; GFX8-NEXT: v_mul_lo_u32 v8, v0, v4 563; GFX8-NEXT: v_mul_hi_u32 v9, v0, v3 564; GFX8-NEXT: v_mul_lo_u32 v2, v2, v3 565; GFX8-NEXT: v_mul_lo_u32 v5, v0, v5 566; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v8 567; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc 568; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v9 569; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc 570; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v9 571; GFX8-NEXT: v_mul_lo_u32 v9, v1, v4 572; GFX8-NEXT: v_mul_hi_u32 v1, v1, v3 573; GFX8-NEXT: v_mul_lo_u32 v6, v0, v3 574; GFX8-NEXT: v_mul_hi_u32 v0, v0, v4 575; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v9 576; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5 577; GFX8-NEXT: v_add_u32_e32 v1, vcc, v2, v1 578; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0 579; GFX8-NEXT: v_add_u32_e32 v2, vcc, v0, v8 580; GFX8-NEXT: v_mov_b32_e32 v0, v6 581; GFX8-NEXT: v_mov_b32_e32 v1, v7 582; GFX8-NEXT: s_setpc_b64 s[30:31] 583; 584; GFX9-LABEL: v_mul_i96: 585; GFX9: ; %bb.0: 586; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 587; GFX9-NEXT: v_mul_lo_u32 v7, v1, v3 588; GFX9-NEXT: v_mul_lo_u32 v8, v0, v4 589; GFX9-NEXT: v_mul_hi_u32 v9, v0, v3 590; GFX9-NEXT: v_mul_lo_u32 v2, v2, v3 591; GFX9-NEXT: v_mul_lo_u32 v10, v1, v4 592; GFX9-NEXT: v_mul_lo_u32 v5, v0, v5 593; GFX9-NEXT: v_mul_hi_u32 v1, v1, v3 594; GFX9-NEXT: v_mul_lo_u32 v6, v0, v3 595; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v8 596; GFX9-NEXT: v_mul_hi_u32 v0, v0, v4 597; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc 598; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v9 599; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc 600; GFX9-NEXT: v_add_u32_e32 v2, v2, v10 601; GFX9-NEXT: v_add_u32_e32 v3, v8, v9 602; GFX9-NEXT: v_add3_u32 v1, v2, v5, v1 603; GFX9-NEXT: v_add3_u32 v2, v1, v0, v3 604; GFX9-NEXT: v_mov_b32_e32 v0, v6 605; GFX9-NEXT: v_mov_b32_e32 v1, v7 606; GFX9-NEXT: s_setpc_b64 s[30:31] 607; 608; GFX10-LABEL: v_mul_i96: 609; GFX10: ; %bb.0: 610; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 611; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 612; GFX10-NEXT: v_mul_lo_u32 v6, v1, v3 613; GFX10-NEXT: v_mul_lo_u32 v7, v0, v4 614; GFX10-NEXT: v_mul_hi_u32 v8, v0, v3 615; GFX10-NEXT: v_mul_lo_u32 v2, v2, v3 616; GFX10-NEXT: v_mul_lo_u32 v9, v1, v4 617; GFX10-NEXT: v_mul_lo_u32 v5, v0, v5 618; GFX10-NEXT: v_mul_hi_u32 v4, v0, v4 619; GFX10-NEXT: v_mul_lo_u32 v0, v0, v3 620; GFX10-NEXT: v_add_co_u32 v6, s4, v6, v7 621; GFX10-NEXT: v_mul_hi_u32 v7, v1, v3 622; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s4 623; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v9 624; GFX10-NEXT: v_add_co_u32 v1, s4, v6, v8 625; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s4 626; GFX10-NEXT: v_add3_u32 v2, v2, v5, v7 627; GFX10-NEXT: v_add_nc_u32_e32 v3, v10, v6 628; GFX10-NEXT: v_add3_u32 v2, v2, v4, v3 629; GFX10-NEXT: s_setpc_b64 s[30:31] 630 %result = mul i96 %num, %den 631 ret i96 %result 632} 633 634define amdgpu_ps <4 x i32> @s_mul_i128(i128 inreg %num, i128 inreg %den) { 635; GFX7-LABEL: s_mul_i128: 636; GFX7: ; %bb.0: 637; GFX7-NEXT: v_mov_b32_e32 v0, s4 638; GFX7-NEXT: v_mul_hi_u32 v0, s0, v0 639; GFX7-NEXT: s_mul_i32 s9, s1, s4 640; GFX7-NEXT: s_mul_i32 s10, s0, s5 641; GFX7-NEXT: s_add_u32 s9, s9, s10 642; GFX7-NEXT: v_add_i32_e32 v0, vcc, s9, v0 643; GFX7-NEXT: v_mov_b32_e32 v2, s1 644; GFX7-NEXT: s_cselect_b32 s10, 1, 0 645; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc 646; GFX7-NEXT: v_mul_hi_u32 v2, v2, s4 647; GFX7-NEXT: v_add_i32_e32 v1, vcc, s10, v1 648; GFX7-NEXT: s_mul_i32 s9, s2, s4 649; GFX7-NEXT: s_mul_i32 s10, s1, s5 650; GFX7-NEXT: s_mul_i32 s11, s0, s6 651; GFX7-NEXT: v_mov_b32_e32 v3, s5 652; GFX7-NEXT: s_add_u32 s9, s9, s10 653; GFX7-NEXT: v_mul_hi_u32 v4, s0, v3 654; GFX7-NEXT: s_cselect_b32 s10, 1, 0 655; GFX7-NEXT: s_add_u32 s9, s9, s11 656; GFX7-NEXT: s_cselect_b32 s11, 1, 0 657; GFX7-NEXT: v_add_i32_e32 v2, vcc, s9, v2 658; GFX7-NEXT: s_add_i32 s10, s10, s11 659; GFX7-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc 660; GFX7-NEXT: v_add_i32_e32 v5, vcc, s10, v5 661; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v4 662; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc 663; GFX7-NEXT: v_add_i32_e32 v4, vcc, v5, v4 664; GFX7-NEXT: v_add_i32_e32 v1, vcc, v2, v1 665; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc 666; GFX7-NEXT: v_add_i32_e32 v2, vcc, v4, v2 667; GFX7-NEXT: v_mov_b32_e32 v4, s2 668; GFX7-NEXT: s_mul_i32 s3, s3, s4 669; GFX7-NEXT: s_mul_i32 s5, s2, s5 670; GFX7-NEXT: v_mul_hi_u32 v4, v4, s4 671; GFX7-NEXT: v_mov_b32_e32 v5, s6 672; GFX7-NEXT: s_mul_i32 s8, s0, s4 673; GFX7-NEXT: s_mul_i32 s9, s1, s6 674; GFX7-NEXT: s_mul_i32 s7, s0, s7 675; GFX7-NEXT: v_mul_hi_u32 v3, s1, v3 676; GFX7-NEXT: v_mul_hi_u32 v5, s0, v5 677; GFX7-NEXT: s_add_i32 s0, s3, s5 678; GFX7-NEXT: s_add_i32 s0, s0, s9 679; GFX7-NEXT: s_add_i32 s0, s0, s7 680; GFX7-NEXT: v_add_i32_e32 v4, vcc, s0, v4 681; GFX7-NEXT: v_add_i32_e32 v3, vcc, v4, v3 682; GFX7-NEXT: v_add_i32_e32 v3, vcc, v3, v5 683; GFX7-NEXT: v_add_i32_e32 v2, vcc, v3, v2 684; GFX7-NEXT: v_readfirstlane_b32 s1, v0 685; GFX7-NEXT: v_readfirstlane_b32 s2, v1 686; GFX7-NEXT: v_readfirstlane_b32 s3, v2 687; GFX7-NEXT: s_mov_b32 s0, s8 688; GFX7-NEXT: ; return to shader part epilog 689; 690; GFX8-LABEL: s_mul_i128: 691; GFX8: ; %bb.0: 692; GFX8-NEXT: v_mov_b32_e32 v0, s4 693; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0 694; GFX8-NEXT: s_mul_i32 s9, s1, s4 695; GFX8-NEXT: s_mul_i32 s10, s0, s5 696; GFX8-NEXT: s_add_u32 s9, s9, s10 697; GFX8-NEXT: v_add_u32_e32 v0, vcc, s9, v0 698; GFX8-NEXT: v_mov_b32_e32 v2, s1 699; GFX8-NEXT: s_cselect_b32 s10, 1, 0 700; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc 701; GFX8-NEXT: v_mul_hi_u32 v2, v2, s4 702; GFX8-NEXT: v_add_u32_e32 v1, vcc, s10, v1 703; GFX8-NEXT: s_mul_i32 s9, s2, s4 704; GFX8-NEXT: s_mul_i32 s10, s1, s5 705; GFX8-NEXT: s_mul_i32 s11, s0, s6 706; GFX8-NEXT: v_mov_b32_e32 v3, s5 707; GFX8-NEXT: s_add_u32 s9, s9, s10 708; GFX8-NEXT: v_mul_hi_u32 v4, s0, v3 709; GFX8-NEXT: s_cselect_b32 s10, 1, 0 710; GFX8-NEXT: s_add_u32 s9, s9, s11 711; GFX8-NEXT: s_cselect_b32 s11, 1, 0 712; GFX8-NEXT: v_add_u32_e32 v2, vcc, s9, v2 713; GFX8-NEXT: s_add_i32 s10, s10, s11 714; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc 715; GFX8-NEXT: v_add_u32_e32 v5, vcc, s10, v5 716; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4 717; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc 718; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4 719; GFX8-NEXT: v_add_u32_e32 v1, vcc, v2, v1 720; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc 721; GFX8-NEXT: v_add_u32_e32 v2, vcc, v4, v2 722; GFX8-NEXT: v_mov_b32_e32 v4, s2 723; GFX8-NEXT: s_mul_i32 s3, s3, s4 724; GFX8-NEXT: s_mul_i32 s5, s2, s5 725; GFX8-NEXT: v_mul_hi_u32 v4, v4, s4 726; GFX8-NEXT: v_mov_b32_e32 v5, s6 727; GFX8-NEXT: s_mul_i32 s8, s0, s4 728; GFX8-NEXT: s_mul_i32 s9, s1, s6 729; GFX8-NEXT: s_mul_i32 s7, s0, s7 730; GFX8-NEXT: v_mul_hi_u32 v3, s1, v3 731; GFX8-NEXT: v_mul_hi_u32 v5, s0, v5 732; GFX8-NEXT: s_add_i32 s0, s3, s5 733; GFX8-NEXT: s_add_i32 s0, s0, s9 734; GFX8-NEXT: s_add_i32 s0, s0, s7 735; GFX8-NEXT: v_add_u32_e32 v4, vcc, s0, v4 736; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3 737; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5 738; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2 739; GFX8-NEXT: v_readfirstlane_b32 s1, v0 740; GFX8-NEXT: v_readfirstlane_b32 s2, v1 741; GFX8-NEXT: v_readfirstlane_b32 s3, v2 742; GFX8-NEXT: s_mov_b32 s0, s8 743; GFX8-NEXT: ; return to shader part epilog 744; 745; GFX9-LABEL: s_mul_i128: 746; GFX9: ; %bb.0: 747; GFX9-NEXT: s_mul_i32 s9, s1, s4 748; GFX9-NEXT: s_mul_i32 s10, s0, s5 749; GFX9-NEXT: s_mul_hi_u32 s11, s0, s4 750; GFX9-NEXT: s_add_u32 s9, s9, s10 751; GFX9-NEXT: s_cselect_b32 s10, 1, 0 752; GFX9-NEXT: s_add_u32 s9, s9, s11 753; GFX9-NEXT: s_cselect_b32 s11, 1, 0 754; GFX9-NEXT: s_add_i32 s10, s10, s11 755; GFX9-NEXT: s_mul_i32 s11, s2, s4 756; GFX9-NEXT: s_mul_i32 s12, s1, s5 757; GFX9-NEXT: s_mul_i32 s13, s0, s6 758; GFX9-NEXT: s_add_u32 s11, s11, s12 759; GFX9-NEXT: s_cselect_b32 s12, 1, 0 760; GFX9-NEXT: s_add_u32 s11, s11, s13 761; GFX9-NEXT: s_cselect_b32 s13, 1, 0 762; GFX9-NEXT: s_mul_hi_u32 s14, s1, s4 763; GFX9-NEXT: s_add_i32 s12, s12, s13 764; GFX9-NEXT: s_add_u32 s11, s11, s14 765; GFX9-NEXT: s_cselect_b32 s13, 1, 0 766; GFX9-NEXT: s_mul_hi_u32 s15, s0, s5 767; GFX9-NEXT: s_add_i32 s12, s12, s13 768; GFX9-NEXT: s_add_u32 s11, s11, s15 769; GFX9-NEXT: s_cselect_b32 s13, 1, 0 770; GFX9-NEXT: s_add_i32 s12, s12, s13 771; GFX9-NEXT: s_add_u32 s10, s11, s10 772; GFX9-NEXT: s_cselect_b32 s11, 1, 0 773; GFX9-NEXT: s_add_i32 s12, s12, s11 774; GFX9-NEXT: s_mul_i32 s3, s3, s4 775; GFX9-NEXT: s_mul_i32 s11, s2, s5 776; GFX9-NEXT: s_mul_i32 s13, s1, s6 777; GFX9-NEXT: s_add_i32 s3, s3, s11 778; GFX9-NEXT: s_mul_i32 s7, s0, s7 779; GFX9-NEXT: s_add_i32 s3, s3, s13 780; GFX9-NEXT: s_mul_hi_u32 s2, s2, s4 781; GFX9-NEXT: s_add_i32 s3, s3, s7 782; GFX9-NEXT: s_mul_hi_u32 s1, s1, s5 783; GFX9-NEXT: s_add_i32 s2, s3, s2 784; GFX9-NEXT: s_mul_i32 s8, s0, s4 785; GFX9-NEXT: s_mul_hi_u32 s0, s0, s6 786; GFX9-NEXT: s_add_i32 s1, s2, s1 787; GFX9-NEXT: s_add_i32 s0, s1, s0 788; GFX9-NEXT: s_add_i32 s3, s0, s12 789; GFX9-NEXT: s_mov_b32 s0, s8 790; GFX9-NEXT: s_mov_b32 s1, s9 791; GFX9-NEXT: s_mov_b32 s2, s10 792; GFX9-NEXT: ; return to shader part epilog 793; 794; GFX10-LABEL: s_mul_i128: 795; GFX10: ; %bb.0: 796; GFX10-NEXT: s_mul_i32 s8, s1, s4 797; GFX10-NEXT: s_mul_i32 s9, s0, s5 798; GFX10-NEXT: s_mul_hi_u32 s10, s0, s4 799; GFX10-NEXT: s_add_u32 s8, s8, s9 800; GFX10-NEXT: s_cselect_b32 s9, 1, 0 801; GFX10-NEXT: s_add_u32 s8, s8, s10 802; GFX10-NEXT: s_cselect_b32 s10, 1, 0 803; GFX10-NEXT: s_mul_i32 s11, s1, s5 804; GFX10-NEXT: s_add_i32 s9, s9, s10 805; GFX10-NEXT: s_mul_i32 s10, s2, s4 806; GFX10-NEXT: s_mul_i32 s12, s0, s6 807; GFX10-NEXT: s_add_u32 s10, s10, s11 808; GFX10-NEXT: s_cselect_b32 s11, 1, 0 809; GFX10-NEXT: s_add_u32 s10, s10, s12 810; GFX10-NEXT: s_cselect_b32 s12, 1, 0 811; GFX10-NEXT: s_mul_hi_u32 s13, s1, s4 812; GFX10-NEXT: s_add_i32 s11, s11, s12 813; GFX10-NEXT: s_add_u32 s10, s10, s13 814; GFX10-NEXT: s_cselect_b32 s12, 1, 0 815; GFX10-NEXT: s_mul_hi_u32 s14, s0, s5 816; GFX10-NEXT: s_add_i32 s11, s11, s12 817; GFX10-NEXT: s_add_u32 s10, s10, s14 818; GFX10-NEXT: s_cselect_b32 s12, 1, 0 819; GFX10-NEXT: s_mul_i32 s3, s3, s4 820; GFX10-NEXT: s_add_i32 s11, s11, s12 821; GFX10-NEXT: s_mul_i32 s12, s2, s5 822; GFX10-NEXT: s_add_u32 s9, s10, s9 823; GFX10-NEXT: s_cselect_b32 s10, 1, 0 824; GFX10-NEXT: s_mul_i32 s13, s1, s6 825; GFX10-NEXT: s_add_i32 s3, s3, s12 826; GFX10-NEXT: s_mul_i32 s7, s0, s7 827; GFX10-NEXT: s_add_i32 s3, s3, s13 828; GFX10-NEXT: s_mul_hi_u32 s2, s2, s4 829; GFX10-NEXT: s_add_i32 s3, s3, s7 830; GFX10-NEXT: s_mul_hi_u32 s1, s1, s5 831; GFX10-NEXT: s_add_i32 s2, s3, s2 832; GFX10-NEXT: s_mul_hi_u32 s3, s0, s6 833; GFX10-NEXT: s_add_i32 s1, s2, s1 834; GFX10-NEXT: s_add_i32 s11, s11, s10 835; GFX10-NEXT: s_add_i32 s1, s1, s3 836; GFX10-NEXT: s_mul_i32 s0, s0, s4 837; GFX10-NEXT: s_add_i32 s3, s1, s11 838; GFX10-NEXT: s_mov_b32 s1, s8 839; GFX10-NEXT: s_mov_b32 s2, s9 840; GFX10-NEXT: ; return to shader part epilog 841 %result = mul i128 %num, %den 842 %cast = bitcast i128 %result to <4 x i32> 843 ret <4 x i32> %cast 844} 845 846define i128 @v_mul_i128(i128 %num, i128 %den) { 847; GFX7-LABEL: v_mul_i128: 848; GFX7: ; %bb.0: 849; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 850; GFX7-NEXT: v_mul_lo_u32 v9, v1, v4 851; GFX7-NEXT: v_mul_lo_u32 v10, v0, v5 852; GFX7-NEXT: v_mul_hi_u32 v11, v0, v4 853; GFX7-NEXT: v_mul_lo_u32 v12, v1, v5 854; GFX7-NEXT: v_mul_lo_u32 v13, v0, v6 855; GFX7-NEXT: v_add_i32_e32 v9, vcc, v9, v10 856; GFX7-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc 857; GFX7-NEXT: v_add_i32_e32 v9, vcc, v9, v11 858; GFX7-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc 859; GFX7-NEXT: v_add_i32_e32 v10, vcc, v10, v11 860; GFX7-NEXT: v_mul_lo_u32 v11, v2, v4 861; GFX7-NEXT: v_mul_hi_u32 v14, v1, v4 862; GFX7-NEXT: v_mul_hi_u32 v15, v0, v5 863; GFX7-NEXT: v_mul_lo_u32 v3, v3, v4 864; GFX7-NEXT: v_add_i32_e32 v11, vcc, v11, v12 865; GFX7-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc 866; GFX7-NEXT: v_add_i32_e32 v11, vcc, v11, v13 867; GFX7-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc 868; GFX7-NEXT: v_add_i32_e32 v12, vcc, v12, v13 869; GFX7-NEXT: v_add_i32_e32 v11, vcc, v11, v14 870; GFX7-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc 871; GFX7-NEXT: v_add_i32_e32 v12, vcc, v12, v13 872; GFX7-NEXT: v_add_i32_e32 v11, vcc, v11, v15 873; GFX7-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc 874; GFX7-NEXT: v_add_i32_e32 v12, vcc, v12, v13 875; GFX7-NEXT: v_add_i32_e32 v10, vcc, v11, v10 876; GFX7-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc 877; GFX7-NEXT: v_add_i32_e32 v11, vcc, v12, v11 878; GFX7-NEXT: v_mul_lo_u32 v12, v2, v5 879; GFX7-NEXT: v_mul_lo_u32 v13, v1, v6 880; GFX7-NEXT: v_mul_lo_u32 v7, v0, v7 881; GFX7-NEXT: v_mul_hi_u32 v2, v2, v4 882; GFX7-NEXT: v_mul_hi_u32 v1, v1, v5 883; GFX7-NEXT: v_add_i32_e32 v3, vcc, v3, v12 884; GFX7-NEXT: v_mul_lo_u32 v8, v0, v4 885; GFX7-NEXT: v_mul_hi_u32 v0, v0, v6 886; GFX7-NEXT: v_add_i32_e32 v3, vcc, v3, v13 887; GFX7-NEXT: v_add_i32_e32 v3, vcc, v3, v7 888; GFX7-NEXT: v_add_i32_e32 v2, vcc, v3, v2 889; GFX7-NEXT: v_add_i32_e32 v1, vcc, v2, v1 890; GFX7-NEXT: v_add_i32_e32 v0, vcc, v1, v0 891; GFX7-NEXT: v_add_i32_e32 v3, vcc, v0, v11 892; GFX7-NEXT: v_mov_b32_e32 v0, v8 893; GFX7-NEXT: v_mov_b32_e32 v1, v9 894; GFX7-NEXT: v_mov_b32_e32 v2, v10 895; GFX7-NEXT: s_setpc_b64 s[30:31] 896; 897; GFX8-LABEL: v_mul_i128: 898; GFX8: ; %bb.0: 899; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 900; GFX8-NEXT: v_mul_lo_u32 v9, v1, v4 901; GFX8-NEXT: v_mul_lo_u32 v10, v0, v5 902; GFX8-NEXT: v_mul_hi_u32 v11, v0, v4 903; GFX8-NEXT: v_mul_lo_u32 v12, v1, v5 904; GFX8-NEXT: v_mul_lo_u32 v13, v0, v6 905; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v10 906; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc 907; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v11 908; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc 909; GFX8-NEXT: v_add_u32_e32 v10, vcc, v10, v11 910; GFX8-NEXT: v_mul_lo_u32 v11, v2, v4 911; GFX8-NEXT: v_mul_hi_u32 v14, v1, v4 912; GFX8-NEXT: v_mul_hi_u32 v15, v0, v5 913; GFX8-NEXT: v_mul_lo_u32 v3, v3, v4 914; GFX8-NEXT: v_add_u32_e32 v11, vcc, v11, v12 915; GFX8-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc 916; GFX8-NEXT: v_add_u32_e32 v11, vcc, v11, v13 917; GFX8-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc 918; GFX8-NEXT: v_add_u32_e32 v12, vcc, v12, v13 919; GFX8-NEXT: v_add_u32_e32 v11, vcc, v11, v14 920; GFX8-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc 921; GFX8-NEXT: v_add_u32_e32 v12, vcc, v12, v13 922; GFX8-NEXT: v_add_u32_e32 v11, vcc, v11, v15 923; GFX8-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc 924; GFX8-NEXT: v_add_u32_e32 v12, vcc, v12, v13 925; GFX8-NEXT: v_add_u32_e32 v10, vcc, v11, v10 926; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc 927; GFX8-NEXT: v_add_u32_e32 v11, vcc, v12, v11 928; GFX8-NEXT: v_mul_lo_u32 v12, v2, v5 929; GFX8-NEXT: v_mul_lo_u32 v13, v1, v6 930; GFX8-NEXT: v_mul_lo_u32 v7, v0, v7 931; GFX8-NEXT: v_mul_hi_u32 v2, v2, v4 932; GFX8-NEXT: v_mul_hi_u32 v1, v1, v5 933; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v12 934; GFX8-NEXT: v_mul_lo_u32 v8, v0, v4 935; GFX8-NEXT: v_mul_hi_u32 v0, v0, v6 936; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v13 937; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v7 938; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2 939; GFX8-NEXT: v_add_u32_e32 v1, vcc, v2, v1 940; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0 941; GFX8-NEXT: v_add_u32_e32 v3, vcc, v0, v11 942; GFX8-NEXT: v_mov_b32_e32 v0, v8 943; GFX8-NEXT: v_mov_b32_e32 v1, v9 944; GFX8-NEXT: v_mov_b32_e32 v2, v10 945; GFX8-NEXT: s_setpc_b64 s[30:31] 946; 947; GFX9-LABEL: v_mul_i128: 948; GFX9: ; %bb.0: 949; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 950; GFX9-NEXT: v_mul_lo_u32 v9, v1, v4 951; GFX9-NEXT: v_mul_lo_u32 v10, v0, v5 952; GFX9-NEXT: v_mul_hi_u32 v11, v0, v4 953; GFX9-NEXT: v_mul_lo_u32 v12, v1, v5 954; GFX9-NEXT: v_mul_lo_u32 v13, v0, v6 955; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v10 956; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc 957; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v11 958; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc 959; GFX9-NEXT: v_add_u32_e32 v10, v10, v11 960; GFX9-NEXT: v_mul_lo_u32 v11, v2, v4 961; GFX9-NEXT: v_mul_hi_u32 v14, v1, v4 962; GFX9-NEXT: v_mul_hi_u32 v15, v0, v5 963; GFX9-NEXT: v_mul_lo_u32 v3, v3, v4 964; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v11, v12 965; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc 966; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v11, v13 967; GFX9-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc 968; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v11, v14 969; GFX9-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc 970; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v11, v15 971; GFX9-NEXT: v_add3_u32 v12, v12, v13, v14 972; GFX9-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc 973; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10 974; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc 975; GFX9-NEXT: v_add3_u32 v11, v12, v13, v11 976; GFX9-NEXT: v_mul_lo_u32 v12, v2, v5 977; GFX9-NEXT: v_mul_lo_u32 v13, v1, v6 978; GFX9-NEXT: v_mul_lo_u32 v7, v0, v7 979; GFX9-NEXT: v_mul_hi_u32 v2, v2, v4 980; GFX9-NEXT: v_mul_hi_u32 v1, v1, v5 981; GFX9-NEXT: v_mul_lo_u32 v8, v0, v4 982; GFX9-NEXT: v_mul_hi_u32 v0, v0, v6 983; GFX9-NEXT: v_add_u32_e32 v3, v3, v12 984; GFX9-NEXT: v_add3_u32 v3, v3, v13, v7 985; GFX9-NEXT: v_add3_u32 v1, v3, v2, v1 986; GFX9-NEXT: v_add3_u32 v3, v1, v0, v11 987; GFX9-NEXT: v_mov_b32_e32 v0, v8 988; GFX9-NEXT: v_mov_b32_e32 v1, v9 989; GFX9-NEXT: v_mov_b32_e32 v2, v10 990; GFX9-NEXT: s_setpc_b64 s[30:31] 991; 992; GFX10-LABEL: v_mul_i128: 993; GFX10: ; %bb.0: 994; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 995; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 996; GFX10-NEXT: v_mul_lo_u32 v8, v2, v4 997; GFX10-NEXT: v_mul_lo_u32 v9, v1, v5 998; GFX10-NEXT: v_mul_lo_u32 v10, v1, v4 999; GFX10-NEXT: v_mul_lo_u32 v11, v0, v5 1000; GFX10-NEXT: v_mul_hi_u32 v12, v0, v4 1001; GFX10-NEXT: v_mul_lo_u32 v13, v0, v6 1002; GFX10-NEXT: v_mul_hi_u32 v15, v0, v5 1003; GFX10-NEXT: v_mul_lo_u32 v3, v3, v4 1004; GFX10-NEXT: v_mul_lo_u32 v7, v0, v7 1005; GFX10-NEXT: v_add_co_u32 v8, s4, v8, v9 1006; GFX10-NEXT: v_add_co_u32 v9, s5, v10, v11 1007; GFX10-NEXT: v_mul_hi_u32 v11, v1, v4 1008; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s5 1009; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, 1, s4 1010; GFX10-NEXT: v_add_co_u32 v13, s4, v8, v13 1011; GFX10-NEXT: v_add_co_u32 v8, s5, v9, v12 1012; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s5 1013; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s4 1014; GFX10-NEXT: v_add_co_u32 v11, s4, v13, v11 1015; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s4 1016; GFX10-NEXT: v_add_nc_u32_e32 v9, v10, v9 1017; GFX10-NEXT: v_mul_lo_u32 v10, v2, v5 1018; GFX10-NEXT: v_add_co_u32 v11, s4, v11, v15 1019; GFX10-NEXT: v_add3_u32 v12, v14, v12, v13 1020; GFX10-NEXT: v_mul_lo_u32 v13, v1, v6 1021; GFX10-NEXT: v_mul_hi_u32 v15, v2, v4 1022; GFX10-NEXT: v_mul_hi_u32 v1, v1, v5 1023; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, 1, s4 1024; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v10 1025; GFX10-NEXT: v_add_co_u32 v2, s4, v11, v9 1026; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4 1027; GFX10-NEXT: v_mul_hi_u32 v6, v0, v6 1028; GFX10-NEXT: v_add3_u32 v3, v3, v13, v7 1029; GFX10-NEXT: v_mul_lo_u32 v0, v0, v4 1030; GFX10-NEXT: v_add3_u32 v4, v12, v14, v5 1031; GFX10-NEXT: v_add3_u32 v1, v3, v15, v1 1032; GFX10-NEXT: v_add3_u32 v3, v1, v6, v4 1033; GFX10-NEXT: v_mov_b32_e32 v1, v8 1034; GFX10-NEXT: s_setpc_b64 s[30:31] 1035 %result = mul i128 %num, %den 1036 ret i128 %result 1037} 1038 1039define amdgpu_ps <8 x i32> @s_mul_i256(i256 inreg %num, i256 inreg %den) { 1040; GFX7-LABEL: s_mul_i256: 1041; GFX7: ; %bb.0: 1042; GFX7-NEXT: s_mov_b32 s16, s0 1043; GFX7-NEXT: v_mov_b32_e32 v0, s8 1044; GFX7-NEXT: v_mul_hi_u32 v0, s16, v0 1045; GFX7-NEXT: s_mul_i32 s17, s1, s8 1046; GFX7-NEXT: s_mul_i32 s18, s16, s9 1047; GFX7-NEXT: s_add_u32 s17, s17, s18 1048; GFX7-NEXT: v_add_i32_e32 v0, vcc, s17, v0 1049; GFX7-NEXT: v_mov_b32_e32 v2, s1 1050; GFX7-NEXT: s_cselect_b32 s18, 1, 0 1051; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc 1052; GFX7-NEXT: v_mul_hi_u32 v2, v2, s8 1053; GFX7-NEXT: v_add_i32_e32 v1, vcc, s18, v1 1054; GFX7-NEXT: s_mul_i32 s17, s2, s8 1055; GFX7-NEXT: s_mul_i32 s18, s1, s9 1056; GFX7-NEXT: s_mul_i32 s19, s16, s10 1057; GFX7-NEXT: v_mov_b32_e32 v3, s9 1058; GFX7-NEXT: s_add_u32 s17, s17, s18 1059; GFX7-NEXT: v_mul_hi_u32 v4, s16, v3 1060; GFX7-NEXT: s_cselect_b32 s18, 1, 0 1061; GFX7-NEXT: s_add_u32 s17, s17, s19 1062; GFX7-NEXT: s_cselect_b32 s19, 1, 0 1063; GFX7-NEXT: v_add_i32_e32 v2, vcc, s17, v2 1064; GFX7-NEXT: s_add_i32 s18, s18, s19 1065; GFX7-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc 1066; GFX7-NEXT: v_add_i32_e32 v5, vcc, s18, v5 1067; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v4 1068; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc 1069; GFX7-NEXT: v_add_i32_e32 v4, vcc, v5, v4 1070; GFX7-NEXT: v_add_i32_e32 v1, vcc, v2, v1 1071; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc 1072; GFX7-NEXT: s_mul_i32 s17, s3, s8 1073; GFX7-NEXT: s_mul_i32 s18, s2, s9 1074; GFX7-NEXT: v_add_i32_e32 v2, vcc, v4, v2 1075; GFX7-NEXT: s_mul_i32 s19, s1, s10 1076; GFX7-NEXT: v_mov_b32_e32 v4, s2 1077; GFX7-NEXT: s_add_u32 s17, s17, s18 1078; GFX7-NEXT: v_mul_hi_u32 v5, v4, s8 1079; GFX7-NEXT: s_cselect_b32 s18, 1, 0 1080; GFX7-NEXT: s_add_u32 s17, s17, s19 1081; GFX7-NEXT: s_cselect_b32 s19, 1, 0 1082; GFX7-NEXT: s_mul_i32 s20, s16, s11 1083; GFX7-NEXT: s_add_i32 s18, s18, s19 1084; GFX7-NEXT: v_mul_hi_u32 v3, s1, v3 1085; GFX7-NEXT: s_add_u32 s17, s17, s20 1086; GFX7-NEXT: s_cselect_b32 s19, 1, 0 1087; GFX7-NEXT: v_add_i32_e32 v5, vcc, s17, v5 1088; GFX7-NEXT: v_mov_b32_e32 v6, s10 1089; GFX7-NEXT: s_add_i32 s18, s18, s19 1090; GFX7-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc 1091; GFX7-NEXT: v_mul_hi_u32 v7, s16, v6 1092; GFX7-NEXT: v_add_i32_e32 v8, vcc, s18, v8 1093; GFX7-NEXT: v_add_i32_e32 v3, vcc, v5, v3 1094; GFX7-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc 1095; GFX7-NEXT: v_add_i32_e32 v5, vcc, v8, v5 1096; GFX7-NEXT: v_add_i32_e32 v3, vcc, v3, v7 1097; GFX7-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc 1098; GFX7-NEXT: s_mul_i32 s17, s4, s8 1099; GFX7-NEXT: s_mul_i32 s18, s3, s9 1100; GFX7-NEXT: v_add_i32_e32 v5, vcc, v5, v7 1101; GFX7-NEXT: s_mul_i32 s19, s2, s10 1102; GFX7-NEXT: s_add_u32 s17, s17, s18 1103; GFX7-NEXT: v_add_i32_e32 v2, vcc, v3, v2 1104; GFX7-NEXT: s_cselect_b32 s18, 1, 0 1105; GFX7-NEXT: s_add_u32 s17, s17, s19 1106; GFX7-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc 1107; GFX7-NEXT: s_cselect_b32 s19, 1, 0 1108; GFX7-NEXT: v_add_i32_e32 v3, vcc, v5, v3 1109; GFX7-NEXT: s_mul_i32 s20, s1, s11 1110; GFX7-NEXT: v_mov_b32_e32 v5, s3 1111; GFX7-NEXT: s_add_i32 s18, s18, s19 1112; GFX7-NEXT: v_mul_hi_u32 v7, v5, s8 1113; GFX7-NEXT: s_add_u32 s17, s17, s20 1114; GFX7-NEXT: s_cselect_b32 s19, 1, 0 1115; GFX7-NEXT: s_mul_i32 s21, s16, s12 1116; GFX7-NEXT: s_add_i32 s18, s18, s19 1117; GFX7-NEXT: v_mul_hi_u32 v4, v4, s9 1118; GFX7-NEXT: s_add_u32 s17, s17, s21 1119; GFX7-NEXT: s_cselect_b32 s19, 1, 0 1120; GFX7-NEXT: v_add_i32_e32 v7, vcc, s17, v7 1121; GFX7-NEXT: s_add_i32 s18, s18, s19 1122; GFX7-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc 1123; GFX7-NEXT: v_mul_hi_u32 v8, s1, v6 1124; GFX7-NEXT: v_add_i32_e32 v11, vcc, s18, v11 1125; GFX7-NEXT: v_add_i32_e32 v4, vcc, v7, v4 1126; GFX7-NEXT: v_mov_b32_e32 v9, s11 1127; GFX7-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc 1128; GFX7-NEXT: v_mul_hi_u32 v10, s16, v9 1129; GFX7-NEXT: v_add_i32_e32 v7, vcc, v11, v7 1130; GFX7-NEXT: v_add_i32_e32 v4, vcc, v4, v8 1131; GFX7-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc 1132; GFX7-NEXT: s_mul_i32 s17, s5, s8 1133; GFX7-NEXT: s_mul_i32 s18, s4, s9 1134; GFX7-NEXT: v_add_i32_e32 v7, vcc, v7, v8 1135; GFX7-NEXT: s_mul_i32 s19, s3, s10 1136; GFX7-NEXT: s_add_u32 s17, s17, s18 1137; GFX7-NEXT: v_add_i32_e32 v4, vcc, v4, v10 1138; GFX7-NEXT: s_cselect_b32 s18, 1, 0 1139; GFX7-NEXT: s_add_u32 s17, s17, s19 1140; GFX7-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc 1141; GFX7-NEXT: s_cselect_b32 s19, 1, 0 1142; GFX7-NEXT: v_add_i32_e32 v7, vcc, v7, v8 1143; GFX7-NEXT: s_mul_i32 s20, s2, s11 1144; GFX7-NEXT: s_add_i32 s18, s18, s19 1145; GFX7-NEXT: v_add_i32_e32 v3, vcc, v4, v3 1146; GFX7-NEXT: s_add_u32 s17, s17, s20 1147; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc 1148; GFX7-NEXT: s_cselect_b32 s19, 1, 0 1149; GFX7-NEXT: v_add_i32_e32 v4, vcc, v7, v4 1150; GFX7-NEXT: s_mul_i32 s21, s1, s12 1151; GFX7-NEXT: v_mov_b32_e32 v7, s4 1152; GFX7-NEXT: s_add_i32 s18, s18, s19 1153; GFX7-NEXT: v_mul_hi_u32 v8, v7, s8 1154; GFX7-NEXT: s_add_u32 s17, s17, s21 1155; GFX7-NEXT: s_cselect_b32 s19, 1, 0 1156; GFX7-NEXT: s_mul_i32 s22, s16, s13 1157; GFX7-NEXT: s_add_i32 s18, s18, s19 1158; GFX7-NEXT: v_mul_hi_u32 v10, v5, s9 1159; GFX7-NEXT: s_add_u32 s17, s17, s22 1160; GFX7-NEXT: s_cselect_b32 s19, 1, 0 1161; GFX7-NEXT: v_add_i32_e32 v8, vcc, s17, v8 1162; GFX7-NEXT: s_add_i32 s18, s18, s19 1163; GFX7-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc 1164; GFX7-NEXT: v_mul_hi_u32 v6, s2, v6 1165; GFX7-NEXT: v_add_i32_e32 v14, vcc, s18, v14 1166; GFX7-NEXT: v_add_i32_e32 v8, vcc, v8, v10 1167; GFX7-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc 1168; GFX7-NEXT: v_mul_hi_u32 v11, s1, v9 1169; GFX7-NEXT: v_add_i32_e32 v10, vcc, v14, v10 1170; GFX7-NEXT: v_add_i32_e32 v6, vcc, v8, v6 1171; GFX7-NEXT: v_mov_b32_e32 v12, s12 1172; GFX7-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc 1173; GFX7-NEXT: s_mul_i32 s17, s6, s8 1174; GFX7-NEXT: s_mul_i32 s18, s5, s9 1175; GFX7-NEXT: v_mul_hi_u32 v13, s16, v12 1176; GFX7-NEXT: v_add_i32_e32 v8, vcc, v10, v8 1177; GFX7-NEXT: s_mul_i32 s19, s4, s10 1178; GFX7-NEXT: s_add_u32 s17, s17, s18 1179; GFX7-NEXT: v_add_i32_e32 v6, vcc, v6, v11 1180; GFX7-NEXT: s_cselect_b32 s18, 1, 0 1181; GFX7-NEXT: s_add_u32 s17, s17, s19 1182; GFX7-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc 1183; GFX7-NEXT: s_cselect_b32 s19, 1, 0 1184; GFX7-NEXT: v_add_i32_e32 v8, vcc, v8, v10 1185; GFX7-NEXT: s_mul_i32 s20, s3, s11 1186; GFX7-NEXT: s_add_i32 s18, s18, s19 1187; GFX7-NEXT: v_add_i32_e32 v6, vcc, v6, v13 1188; GFX7-NEXT: s_add_u32 s17, s17, s20 1189; GFX7-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc 1190; GFX7-NEXT: s_cselect_b32 s19, 1, 0 1191; GFX7-NEXT: v_add_i32_e32 v8, vcc, v8, v10 1192; GFX7-NEXT: s_mul_i32 s21, s2, s12 1193; GFX7-NEXT: s_add_i32 s18, s18, s19 1194; GFX7-NEXT: v_add_i32_e32 v4, vcc, v6, v4 1195; GFX7-NEXT: s_add_u32 s17, s17, s21 1196; GFX7-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc 1197; GFX7-NEXT: s_cselect_b32 s19, 1, 0 1198; GFX7-NEXT: v_add_i32_e32 v6, vcc, v8, v6 1199; GFX7-NEXT: s_mul_i32 s22, s1, s13 1200; GFX7-NEXT: v_mov_b32_e32 v8, s5 1201; GFX7-NEXT: s_add_i32 s18, s18, s19 1202; GFX7-NEXT: v_mul_hi_u32 v10, v8, s8 1203; GFX7-NEXT: s_add_u32 s17, s17, s22 1204; GFX7-NEXT: s_cselect_b32 s19, 1, 0 1205; GFX7-NEXT: s_mul_i32 s23, s16, s14 1206; GFX7-NEXT: s_add_i32 s18, s18, s19 1207; GFX7-NEXT: v_mul_hi_u32 v11, v7, s9 1208; GFX7-NEXT: s_add_u32 s17, s17, s23 1209; GFX7-NEXT: s_cselect_b32 s19, 1, 0 1210; GFX7-NEXT: v_add_i32_e32 v10, vcc, s17, v10 1211; GFX7-NEXT: s_add_i32 s18, s18, s19 1212; GFX7-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc 1213; GFX7-NEXT: v_mul_hi_u32 v5, v5, s10 1214; GFX7-NEXT: v_add_i32_e32 v17, vcc, s18, v17 1215; GFX7-NEXT: v_add_i32_e32 v10, vcc, v10, v11 1216; GFX7-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc 1217; GFX7-NEXT: v_mul_hi_u32 v13, s2, v9 1218; GFX7-NEXT: v_add_i32_e32 v11, vcc, v17, v11 1219; GFX7-NEXT: v_add_i32_e32 v5, vcc, v10, v5 1220; GFX7-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc 1221; GFX7-NEXT: v_mul_hi_u32 v14, s1, v12 1222; GFX7-NEXT: v_add_i32_e32 v10, vcc, v11, v10 1223; GFX7-NEXT: v_add_i32_e32 v5, vcc, v5, v13 1224; GFX7-NEXT: v_mov_b32_e32 v15, s13 1225; GFX7-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc 1226; GFX7-NEXT: v_mul_hi_u32 v16, s16, v15 1227; GFX7-NEXT: v_add_i32_e32 v10, vcc, v10, v11 1228; GFX7-NEXT: v_add_i32_e32 v5, vcc, v5, v14 1229; GFX7-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc 1230; GFX7-NEXT: v_add_i32_e32 v10, vcc, v10, v11 1231; GFX7-NEXT: v_add_i32_e32 v5, vcc, v5, v16 1232; GFX7-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc 1233; GFX7-NEXT: v_add_i32_e32 v10, vcc, v10, v11 1234; GFX7-NEXT: s_mul_i32 s7, s7, s8 1235; GFX7-NEXT: s_mul_i32 s17, s6, s9 1236; GFX7-NEXT: v_add_i32_e32 v5, vcc, v5, v6 1237; GFX7-NEXT: s_mul_i32 s5, s5, s10 1238; GFX7-NEXT: s_mul_i32 s4, s4, s11 1239; GFX7-NEXT: s_mul_i32 s11, s3, s12 1240; GFX7-NEXT: s_mul_i32 s12, s2, s13 1241; GFX7-NEXT: s_mul_i32 s13, s1, s14 1242; GFX7-NEXT: v_mul_hi_u32 v11, s2, v12 1243; GFX7-NEXT: v_mul_hi_u32 v12, s1, v15 1244; GFX7-NEXT: s_add_i32 s1, s7, s17 1245; GFX7-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc 1246; GFX7-NEXT: s_add_i32 s1, s1, s5 1247; GFX7-NEXT: v_add_i32_e32 v6, vcc, v10, v6 1248; GFX7-NEXT: v_mov_b32_e32 v10, s6 1249; GFX7-NEXT: s_add_i32 s1, s1, s4 1250; GFX7-NEXT: v_mul_hi_u32 v10, v10, s8 1251; GFX7-NEXT: s_add_i32 s1, s1, s11 1252; GFX7-NEXT: v_mul_hi_u32 v8, v8, s9 1253; GFX7-NEXT: s_add_i32 s1, s1, s12 1254; GFX7-NEXT: s_mul_i32 s15, s16, s15 1255; GFX7-NEXT: v_mul_hi_u32 v7, v7, s10 1256; GFX7-NEXT: s_add_i32 s1, s1, s13 1257; GFX7-NEXT: v_mul_hi_u32 v9, s3, v9 1258; GFX7-NEXT: s_add_i32 s1, s1, s15 1259; GFX7-NEXT: v_add_i32_e32 v10, vcc, s1, v10 1260; GFX7-NEXT: v_mov_b32_e32 v13, s14 1261; GFX7-NEXT: v_add_i32_e32 v8, vcc, v10, v8 1262; GFX7-NEXT: v_mul_hi_u32 v13, s16, v13 1263; GFX7-NEXT: v_add_i32_e32 v7, vcc, v8, v7 1264; GFX7-NEXT: v_add_i32_e32 v7, vcc, v7, v9 1265; GFX7-NEXT: v_add_i32_e32 v7, vcc, v7, v11 1266; GFX7-NEXT: v_add_i32_e32 v7, vcc, v7, v12 1267; GFX7-NEXT: v_add_i32_e32 v7, vcc, v7, v13 1268; GFX7-NEXT: v_add_i32_e32 v6, vcc, v7, v6 1269; GFX7-NEXT: s_mul_i32 s0, s0, s8 1270; GFX7-NEXT: v_readfirstlane_b32 s1, v0 1271; GFX7-NEXT: v_readfirstlane_b32 s2, v1 1272; GFX7-NEXT: v_readfirstlane_b32 s3, v2 1273; GFX7-NEXT: v_readfirstlane_b32 s4, v3 1274; GFX7-NEXT: v_readfirstlane_b32 s5, v4 1275; GFX7-NEXT: v_readfirstlane_b32 s6, v5 1276; GFX7-NEXT: v_readfirstlane_b32 s7, v6 1277; GFX7-NEXT: ; return to shader part epilog 1278; 1279; GFX8-LABEL: s_mul_i256: 1280; GFX8: ; %bb.0: 1281; GFX8-NEXT: s_mov_b32 s16, s0 1282; GFX8-NEXT: v_mov_b32_e32 v0, s8 1283; GFX8-NEXT: v_mul_hi_u32 v0, s16, v0 1284; GFX8-NEXT: s_mul_i32 s17, s1, s8 1285; GFX8-NEXT: s_mul_i32 s18, s16, s9 1286; GFX8-NEXT: s_add_u32 s17, s17, s18 1287; GFX8-NEXT: v_add_u32_e32 v0, vcc, s17, v0 1288; GFX8-NEXT: v_mov_b32_e32 v2, s1 1289; GFX8-NEXT: s_cselect_b32 s18, 1, 0 1290; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc 1291; GFX8-NEXT: v_mul_hi_u32 v2, v2, s8 1292; GFX8-NEXT: v_add_u32_e32 v1, vcc, s18, v1 1293; GFX8-NEXT: s_mul_i32 s17, s2, s8 1294; GFX8-NEXT: s_mul_i32 s18, s1, s9 1295; GFX8-NEXT: s_mul_i32 s19, s16, s10 1296; GFX8-NEXT: v_mov_b32_e32 v3, s9 1297; GFX8-NEXT: s_add_u32 s17, s17, s18 1298; GFX8-NEXT: v_mul_hi_u32 v4, s16, v3 1299; GFX8-NEXT: s_cselect_b32 s18, 1, 0 1300; GFX8-NEXT: s_add_u32 s17, s17, s19 1301; GFX8-NEXT: s_cselect_b32 s19, 1, 0 1302; GFX8-NEXT: v_add_u32_e32 v2, vcc, s17, v2 1303; GFX8-NEXT: s_add_i32 s18, s18, s19 1304; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc 1305; GFX8-NEXT: v_add_u32_e32 v5, vcc, s18, v5 1306; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4 1307; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc 1308; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4 1309; GFX8-NEXT: v_add_u32_e32 v1, vcc, v2, v1 1310; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc 1311; GFX8-NEXT: s_mul_i32 s17, s3, s8 1312; GFX8-NEXT: s_mul_i32 s18, s2, s9 1313; GFX8-NEXT: v_add_u32_e32 v2, vcc, v4, v2 1314; GFX8-NEXT: s_mul_i32 s19, s1, s10 1315; GFX8-NEXT: v_mov_b32_e32 v4, s2 1316; GFX8-NEXT: s_add_u32 s17, s17, s18 1317; GFX8-NEXT: v_mul_hi_u32 v5, v4, s8 1318; GFX8-NEXT: s_cselect_b32 s18, 1, 0 1319; GFX8-NEXT: s_add_u32 s17, s17, s19 1320; GFX8-NEXT: s_cselect_b32 s19, 1, 0 1321; GFX8-NEXT: s_mul_i32 s20, s16, s11 1322; GFX8-NEXT: s_add_i32 s18, s18, s19 1323; GFX8-NEXT: v_mul_hi_u32 v3, s1, v3 1324; GFX8-NEXT: s_add_u32 s17, s17, s20 1325; GFX8-NEXT: s_cselect_b32 s19, 1, 0 1326; GFX8-NEXT: v_add_u32_e32 v5, vcc, s17, v5 1327; GFX8-NEXT: v_mov_b32_e32 v6, s10 1328; GFX8-NEXT: s_add_i32 s18, s18, s19 1329; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc 1330; GFX8-NEXT: v_mul_hi_u32 v7, s16, v6 1331; GFX8-NEXT: v_add_u32_e32 v8, vcc, s18, v8 1332; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3 1333; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc 1334; GFX8-NEXT: v_add_u32_e32 v5, vcc, v8, v5 1335; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v7 1336; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc 1337; GFX8-NEXT: s_mul_i32 s17, s4, s8 1338; GFX8-NEXT: s_mul_i32 s18, s3, s9 1339; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v7 1340; GFX8-NEXT: s_mul_i32 s19, s2, s10 1341; GFX8-NEXT: s_add_u32 s17, s17, s18 1342; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2 1343; GFX8-NEXT: s_cselect_b32 s18, 1, 0 1344; GFX8-NEXT: s_add_u32 s17, s17, s19 1345; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc 1346; GFX8-NEXT: s_cselect_b32 s19, 1, 0 1347; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3 1348; GFX8-NEXT: s_mul_i32 s20, s1, s11 1349; GFX8-NEXT: v_mov_b32_e32 v5, s3 1350; GFX8-NEXT: s_add_i32 s18, s18, s19 1351; GFX8-NEXT: v_mul_hi_u32 v7, v5, s8 1352; GFX8-NEXT: s_add_u32 s17, s17, s20 1353; GFX8-NEXT: s_cselect_b32 s19, 1, 0 1354; GFX8-NEXT: s_mul_i32 s21, s16, s12 1355; GFX8-NEXT: s_add_i32 s18, s18, s19 1356; GFX8-NEXT: v_mul_hi_u32 v4, v4, s9 1357; GFX8-NEXT: s_add_u32 s17, s17, s21 1358; GFX8-NEXT: s_cselect_b32 s19, 1, 0 1359; GFX8-NEXT: v_add_u32_e32 v7, vcc, s17, v7 1360; GFX8-NEXT: s_add_i32 s18, s18, s19 1361; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc 1362; GFX8-NEXT: v_mul_hi_u32 v8, s1, v6 1363; GFX8-NEXT: v_add_u32_e32 v11, vcc, s18, v11 1364; GFX8-NEXT: v_add_u32_e32 v4, vcc, v7, v4 1365; GFX8-NEXT: v_mov_b32_e32 v9, s11 1366; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc 1367; GFX8-NEXT: v_mul_hi_u32 v10, s16, v9 1368; GFX8-NEXT: v_add_u32_e32 v7, vcc, v11, v7 1369; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v8 1370; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc 1371; GFX8-NEXT: s_mul_i32 s17, s5, s8 1372; GFX8-NEXT: s_mul_i32 s18, s4, s9 1373; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v8 1374; GFX8-NEXT: s_mul_i32 s19, s3, s10 1375; GFX8-NEXT: s_add_u32 s17, s17, s18 1376; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v10 1377; GFX8-NEXT: s_cselect_b32 s18, 1, 0 1378; GFX8-NEXT: s_add_u32 s17, s17, s19 1379; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc 1380; GFX8-NEXT: s_cselect_b32 s19, 1, 0 1381; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v8 1382; GFX8-NEXT: s_mul_i32 s20, s2, s11 1383; GFX8-NEXT: s_add_i32 s18, s18, s19 1384; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3 1385; GFX8-NEXT: s_add_u32 s17, s17, s20 1386; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc 1387; GFX8-NEXT: s_cselect_b32 s19, 1, 0 1388; GFX8-NEXT: v_add_u32_e32 v4, vcc, v7, v4 1389; GFX8-NEXT: s_mul_i32 s21, s1, s12 1390; GFX8-NEXT: v_mov_b32_e32 v7, s4 1391; GFX8-NEXT: s_add_i32 s18, s18, s19 1392; GFX8-NEXT: v_mul_hi_u32 v8, v7, s8 1393; GFX8-NEXT: s_add_u32 s17, s17, s21 1394; GFX8-NEXT: s_cselect_b32 s19, 1, 0 1395; GFX8-NEXT: s_mul_i32 s22, s16, s13 1396; GFX8-NEXT: s_add_i32 s18, s18, s19 1397; GFX8-NEXT: v_mul_hi_u32 v10, v5, s9 1398; GFX8-NEXT: s_add_u32 s17, s17, s22 1399; GFX8-NEXT: s_cselect_b32 s19, 1, 0 1400; GFX8-NEXT: v_add_u32_e32 v8, vcc, s17, v8 1401; GFX8-NEXT: s_add_i32 s18, s18, s19 1402; GFX8-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc 1403; GFX8-NEXT: v_mul_hi_u32 v6, s2, v6 1404; GFX8-NEXT: v_add_u32_e32 v14, vcc, s18, v14 1405; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v10 1406; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc 1407; GFX8-NEXT: v_mul_hi_u32 v11, s1, v9 1408; GFX8-NEXT: v_add_u32_e32 v10, vcc, v14, v10 1409; GFX8-NEXT: v_add_u32_e32 v6, vcc, v8, v6 1410; GFX8-NEXT: v_mov_b32_e32 v12, s12 1411; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc 1412; GFX8-NEXT: s_mul_i32 s17, s6, s8 1413; GFX8-NEXT: s_mul_i32 s18, s5, s9 1414; GFX8-NEXT: v_mul_hi_u32 v13, s16, v12 1415; GFX8-NEXT: v_add_u32_e32 v8, vcc, v10, v8 1416; GFX8-NEXT: s_mul_i32 s19, s4, s10 1417; GFX8-NEXT: s_add_u32 s17, s17, s18 1418; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v11 1419; GFX8-NEXT: s_cselect_b32 s18, 1, 0 1420; GFX8-NEXT: s_add_u32 s17, s17, s19 1421; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc 1422; GFX8-NEXT: s_cselect_b32 s19, 1, 0 1423; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v10 1424; GFX8-NEXT: s_mul_i32 s20, s3, s11 1425; GFX8-NEXT: s_add_i32 s18, s18, s19 1426; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v13 1427; GFX8-NEXT: s_add_u32 s17, s17, s20 1428; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc 1429; GFX8-NEXT: s_cselect_b32 s19, 1, 0 1430; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v10 1431; GFX8-NEXT: s_mul_i32 s21, s2, s12 1432; GFX8-NEXT: s_add_i32 s18, s18, s19 1433; GFX8-NEXT: v_add_u32_e32 v4, vcc, v6, v4 1434; GFX8-NEXT: s_add_u32 s17, s17, s21 1435; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc 1436; GFX8-NEXT: s_cselect_b32 s19, 1, 0 1437; GFX8-NEXT: v_add_u32_e32 v6, vcc, v8, v6 1438; GFX8-NEXT: s_mul_i32 s22, s1, s13 1439; GFX8-NEXT: v_mov_b32_e32 v8, s5 1440; GFX8-NEXT: s_add_i32 s18, s18, s19 1441; GFX8-NEXT: v_mul_hi_u32 v10, v8, s8 1442; GFX8-NEXT: s_add_u32 s17, s17, s22 1443; GFX8-NEXT: s_cselect_b32 s19, 1, 0 1444; GFX8-NEXT: s_mul_i32 s23, s16, s14 1445; GFX8-NEXT: s_add_i32 s18, s18, s19 1446; GFX8-NEXT: v_mul_hi_u32 v11, v7, s9 1447; GFX8-NEXT: s_add_u32 s17, s17, s23 1448; GFX8-NEXT: s_cselect_b32 s19, 1, 0 1449; GFX8-NEXT: v_add_u32_e32 v10, vcc, s17, v10 1450; GFX8-NEXT: s_add_i32 s18, s18, s19 1451; GFX8-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc 1452; GFX8-NEXT: v_mul_hi_u32 v5, v5, s10 1453; GFX8-NEXT: v_add_u32_e32 v17, vcc, s18, v17 1454; GFX8-NEXT: v_add_u32_e32 v10, vcc, v10, v11 1455; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc 1456; GFX8-NEXT: v_mul_hi_u32 v13, s2, v9 1457; GFX8-NEXT: v_add_u32_e32 v11, vcc, v17, v11 1458; GFX8-NEXT: v_add_u32_e32 v5, vcc, v10, v5 1459; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc 1460; GFX8-NEXT: v_mul_hi_u32 v14, s1, v12 1461; GFX8-NEXT: v_add_u32_e32 v10, vcc, v11, v10 1462; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v13 1463; GFX8-NEXT: v_mov_b32_e32 v15, s13 1464; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc 1465; GFX8-NEXT: v_mul_hi_u32 v16, s16, v15 1466; GFX8-NEXT: v_add_u32_e32 v10, vcc, v10, v11 1467; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v14 1468; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc 1469; GFX8-NEXT: v_add_u32_e32 v10, vcc, v10, v11 1470; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v16 1471; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc 1472; GFX8-NEXT: v_add_u32_e32 v10, vcc, v10, v11 1473; GFX8-NEXT: s_mul_i32 s7, s7, s8 1474; GFX8-NEXT: s_mul_i32 s17, s6, s9 1475; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v6 1476; GFX8-NEXT: s_mul_i32 s5, s5, s10 1477; GFX8-NEXT: s_mul_i32 s4, s4, s11 1478; GFX8-NEXT: s_mul_i32 s11, s3, s12 1479; GFX8-NEXT: s_mul_i32 s12, s2, s13 1480; GFX8-NEXT: s_mul_i32 s13, s1, s14 1481; GFX8-NEXT: v_mul_hi_u32 v11, s2, v12 1482; GFX8-NEXT: v_mul_hi_u32 v12, s1, v15 1483; GFX8-NEXT: s_add_i32 s1, s7, s17 1484; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc 1485; GFX8-NEXT: s_add_i32 s1, s1, s5 1486; GFX8-NEXT: v_add_u32_e32 v6, vcc, v10, v6 1487; GFX8-NEXT: v_mov_b32_e32 v10, s6 1488; GFX8-NEXT: s_add_i32 s1, s1, s4 1489; GFX8-NEXT: v_mul_hi_u32 v10, v10, s8 1490; GFX8-NEXT: s_add_i32 s1, s1, s11 1491; GFX8-NEXT: v_mul_hi_u32 v8, v8, s9 1492; GFX8-NEXT: s_add_i32 s1, s1, s12 1493; GFX8-NEXT: s_mul_i32 s15, s16, s15 1494; GFX8-NEXT: v_mul_hi_u32 v7, v7, s10 1495; GFX8-NEXT: s_add_i32 s1, s1, s13 1496; GFX8-NEXT: v_mul_hi_u32 v9, s3, v9 1497; GFX8-NEXT: s_add_i32 s1, s1, s15 1498; GFX8-NEXT: v_add_u32_e32 v10, vcc, s1, v10 1499; GFX8-NEXT: v_mov_b32_e32 v13, s14 1500; GFX8-NEXT: v_add_u32_e32 v8, vcc, v10, v8 1501; GFX8-NEXT: v_mul_hi_u32 v13, s16, v13 1502; GFX8-NEXT: v_add_u32_e32 v7, vcc, v8, v7 1503; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v9 1504; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v11 1505; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v12 1506; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v13 1507; GFX8-NEXT: v_add_u32_e32 v6, vcc, v7, v6 1508; GFX8-NEXT: s_mul_i32 s0, s0, s8 1509; GFX8-NEXT: v_readfirstlane_b32 s1, v0 1510; GFX8-NEXT: v_readfirstlane_b32 s2, v1 1511; GFX8-NEXT: v_readfirstlane_b32 s3, v2 1512; GFX8-NEXT: v_readfirstlane_b32 s4, v3 1513; GFX8-NEXT: v_readfirstlane_b32 s5, v4 1514; GFX8-NEXT: v_readfirstlane_b32 s6, v5 1515; GFX8-NEXT: v_readfirstlane_b32 s7, v6 1516; GFX8-NEXT: ; return to shader part epilog 1517; 1518; GFX9-LABEL: s_mul_i256: 1519; GFX9: ; %bb.0: 1520; GFX9-NEXT: s_mov_b32 s16, s0 1521; GFX9-NEXT: s_mul_i32 s17, s1, s8 1522; GFX9-NEXT: s_mul_i32 s18, s16, s9 1523; GFX9-NEXT: s_mul_hi_u32 s19, s16, s8 1524; GFX9-NEXT: s_add_u32 s17, s17, s18 1525; GFX9-NEXT: s_cselect_b32 s18, 1, 0 1526; GFX9-NEXT: s_add_u32 s17, s17, s19 1527; GFX9-NEXT: s_cselect_b32 s19, 1, 0 1528; GFX9-NEXT: s_add_i32 s18, s18, s19 1529; GFX9-NEXT: s_mul_i32 s19, s2, s8 1530; GFX9-NEXT: s_mul_i32 s20, s1, s9 1531; GFX9-NEXT: s_mul_i32 s21, s16, s10 1532; GFX9-NEXT: s_add_u32 s19, s19, s20 1533; GFX9-NEXT: s_cselect_b32 s20, 1, 0 1534; GFX9-NEXT: s_add_u32 s19, s19, s21 1535; GFX9-NEXT: s_cselect_b32 s21, 1, 0 1536; GFX9-NEXT: s_mul_hi_u32 s22, s1, s8 1537; GFX9-NEXT: s_add_i32 s20, s20, s21 1538; GFX9-NEXT: s_add_u32 s19, s19, s22 1539; GFX9-NEXT: s_cselect_b32 s21, 1, 0 1540; GFX9-NEXT: s_mul_hi_u32 s23, s16, s9 1541; GFX9-NEXT: s_add_i32 s20, s20, s21 1542; GFX9-NEXT: s_add_u32 s19, s19, s23 1543; GFX9-NEXT: s_cselect_b32 s21, 1, 0 1544; GFX9-NEXT: s_add_i32 s20, s20, s21 1545; GFX9-NEXT: s_add_u32 s18, s19, s18 1546; GFX9-NEXT: s_cselect_b32 s19, 1, 0 1547; GFX9-NEXT: s_add_i32 s20, s20, s19 1548; GFX9-NEXT: s_mul_i32 s19, s3, s8 1549; GFX9-NEXT: s_mul_i32 s21, s2, s9 1550; GFX9-NEXT: s_mul_i32 s22, s1, s10 1551; GFX9-NEXT: s_add_u32 s19, s19, s21 1552; GFX9-NEXT: s_cselect_b32 s21, 1, 0 1553; GFX9-NEXT: s_add_u32 s19, s19, s22 1554; GFX9-NEXT: s_cselect_b32 s22, 1, 0 1555; GFX9-NEXT: s_mul_i32 s23, s16, s11 1556; GFX9-NEXT: s_add_i32 s21, s21, s22 1557; GFX9-NEXT: s_add_u32 s19, s19, s23 1558; GFX9-NEXT: s_cselect_b32 s22, 1, 0 1559; GFX9-NEXT: s_mul_hi_u32 s24, s2, s8 1560; GFX9-NEXT: s_add_i32 s21, s21, s22 1561; GFX9-NEXT: s_add_u32 s19, s19, s24 1562; GFX9-NEXT: s_cselect_b32 s22, 1, 0 1563; GFX9-NEXT: s_mul_hi_u32 s25, s1, s9 1564; GFX9-NEXT: s_add_i32 s21, s21, s22 1565; GFX9-NEXT: s_add_u32 s19, s19, s25 1566; GFX9-NEXT: s_cselect_b32 s22, 1, 0 1567; GFX9-NEXT: s_mul_hi_u32 s26, s16, s10 1568; GFX9-NEXT: s_add_i32 s21, s21, s22 1569; GFX9-NEXT: s_add_u32 s19, s19, s26 1570; GFX9-NEXT: s_cselect_b32 s22, 1, 0 1571; GFX9-NEXT: s_add_i32 s21, s21, s22 1572; GFX9-NEXT: s_add_u32 s19, s19, s20 1573; GFX9-NEXT: s_cselect_b32 s20, 1, 0 1574; GFX9-NEXT: s_add_i32 s21, s21, s20 1575; GFX9-NEXT: s_mul_i32 s20, s4, s8 1576; GFX9-NEXT: s_mul_i32 s22, s3, s9 1577; GFX9-NEXT: s_mul_i32 s23, s2, s10 1578; GFX9-NEXT: s_add_u32 s20, s20, s22 1579; GFX9-NEXT: s_cselect_b32 s22, 1, 0 1580; GFX9-NEXT: s_add_u32 s20, s20, s23 1581; GFX9-NEXT: s_cselect_b32 s23, 1, 0 1582; GFX9-NEXT: s_mul_i32 s24, s1, s11 1583; GFX9-NEXT: s_add_i32 s22, s22, s23 1584; GFX9-NEXT: s_add_u32 s20, s20, s24 1585; GFX9-NEXT: s_cselect_b32 s23, 1, 0 1586; GFX9-NEXT: s_mul_i32 s25, s16, s12 1587; GFX9-NEXT: s_add_i32 s22, s22, s23 1588; GFX9-NEXT: s_add_u32 s20, s20, s25 1589; GFX9-NEXT: s_cselect_b32 s23, 1, 0 1590; GFX9-NEXT: s_mul_hi_u32 s26, s3, s8 1591; GFX9-NEXT: s_add_i32 s22, s22, s23 1592; GFX9-NEXT: s_add_u32 s20, s20, s26 1593; GFX9-NEXT: s_cselect_b32 s23, 1, 0 1594; GFX9-NEXT: s_mul_hi_u32 s27, s2, s9 1595; GFX9-NEXT: s_add_i32 s22, s22, s23 1596; GFX9-NEXT: s_add_u32 s20, s20, s27 1597; GFX9-NEXT: s_cselect_b32 s23, 1, 0 1598; GFX9-NEXT: s_mul_hi_u32 s28, s1, s10 1599; GFX9-NEXT: s_add_i32 s22, s22, s23 1600; GFX9-NEXT: s_add_u32 s20, s20, s28 1601; GFX9-NEXT: s_cselect_b32 s23, 1, 0 1602; GFX9-NEXT: s_mul_hi_u32 s29, s16, s11 1603; GFX9-NEXT: s_add_i32 s22, s22, s23 1604; GFX9-NEXT: s_add_u32 s20, s20, s29 1605; GFX9-NEXT: s_cselect_b32 s23, 1, 0 1606; GFX9-NEXT: s_add_i32 s22, s22, s23 1607; GFX9-NEXT: s_add_u32 s20, s20, s21 1608; GFX9-NEXT: s_cselect_b32 s21, 1, 0 1609; GFX9-NEXT: s_add_i32 s22, s22, s21 1610; GFX9-NEXT: s_mul_i32 s21, s5, s8 1611; GFX9-NEXT: s_mul_i32 s23, s4, s9 1612; GFX9-NEXT: s_mul_i32 s24, s3, s10 1613; GFX9-NEXT: s_add_u32 s21, s21, s23 1614; GFX9-NEXT: s_cselect_b32 s23, 1, 0 1615; GFX9-NEXT: s_add_u32 s21, s21, s24 1616; GFX9-NEXT: s_cselect_b32 s24, 1, 0 1617; GFX9-NEXT: s_mul_i32 s25, s2, s11 1618; GFX9-NEXT: s_add_i32 s23, s23, s24 1619; GFX9-NEXT: s_add_u32 s21, s21, s25 1620; GFX9-NEXT: s_cselect_b32 s24, 1, 0 1621; GFX9-NEXT: s_mul_i32 s26, s1, s12 1622; GFX9-NEXT: s_add_i32 s23, s23, s24 1623; GFX9-NEXT: s_add_u32 s21, s21, s26 1624; GFX9-NEXT: s_cselect_b32 s24, 1, 0 1625; GFX9-NEXT: s_mul_i32 s27, s16, s13 1626; GFX9-NEXT: s_add_i32 s23, s23, s24 1627; GFX9-NEXT: s_add_u32 s21, s21, s27 1628; GFX9-NEXT: s_cselect_b32 s24, 1, 0 1629; GFX9-NEXT: s_mul_hi_u32 s28, s4, s8 1630; GFX9-NEXT: s_add_i32 s23, s23, s24 1631; GFX9-NEXT: s_add_u32 s21, s21, s28 1632; GFX9-NEXT: s_cselect_b32 s24, 1, 0 1633; GFX9-NEXT: s_mul_hi_u32 s29, s3, s9 1634; GFX9-NEXT: s_add_i32 s23, s23, s24 1635; GFX9-NEXT: s_add_u32 s21, s21, s29 1636; GFX9-NEXT: s_cselect_b32 s24, 1, 0 1637; GFX9-NEXT: s_mul_hi_u32 s30, s2, s10 1638; GFX9-NEXT: s_add_i32 s23, s23, s24 1639; GFX9-NEXT: s_add_u32 s21, s21, s30 1640; GFX9-NEXT: s_cselect_b32 s24, 1, 0 1641; GFX9-NEXT: s_mul_hi_u32 s31, s1, s11 1642; GFX9-NEXT: s_add_i32 s23, s23, s24 1643; GFX9-NEXT: s_add_u32 s21, s21, s31 1644; GFX9-NEXT: s_cselect_b32 s24, 1, 0 1645; GFX9-NEXT: s_mul_hi_u32 s33, s16, s12 1646; GFX9-NEXT: s_add_i32 s23, s23, s24 1647; GFX9-NEXT: s_add_u32 s21, s21, s33 1648; GFX9-NEXT: s_cselect_b32 s24, 1, 0 1649; GFX9-NEXT: s_add_i32 s23, s23, s24 1650; GFX9-NEXT: s_add_u32 s21, s21, s22 1651; GFX9-NEXT: s_cselect_b32 s22, 1, 0 1652; GFX9-NEXT: s_add_i32 s23, s23, s22 1653; GFX9-NEXT: s_mul_i32 s22, s6, s8 1654; GFX9-NEXT: s_mul_i32 s24, s5, s9 1655; GFX9-NEXT: s_mul_i32 s25, s4, s10 1656; GFX9-NEXT: s_add_u32 s22, s22, s24 1657; GFX9-NEXT: s_cselect_b32 s24, 1, 0 1658; GFX9-NEXT: s_add_u32 s22, s22, s25 1659; GFX9-NEXT: s_cselect_b32 s25, 1, 0 1660; GFX9-NEXT: s_mul_i32 s26, s3, s11 1661; GFX9-NEXT: s_add_i32 s24, s24, s25 1662; GFX9-NEXT: s_add_u32 s22, s22, s26 1663; GFX9-NEXT: s_cselect_b32 s25, 1, 0 1664; GFX9-NEXT: s_mul_i32 s27, s2, s12 1665; GFX9-NEXT: s_add_i32 s24, s24, s25 1666; GFX9-NEXT: s_add_u32 s22, s22, s27 1667; GFX9-NEXT: s_cselect_b32 s25, 1, 0 1668; GFX9-NEXT: s_mul_i32 s28, s1, s13 1669; GFX9-NEXT: s_add_i32 s24, s24, s25 1670; GFX9-NEXT: s_add_u32 s22, s22, s28 1671; GFX9-NEXT: s_cselect_b32 s25, 1, 0 1672; GFX9-NEXT: s_mul_i32 s29, s16, s14 1673; GFX9-NEXT: s_add_i32 s24, s24, s25 1674; GFX9-NEXT: s_add_u32 s22, s22, s29 1675; GFX9-NEXT: s_cselect_b32 s25, 1, 0 1676; GFX9-NEXT: s_mul_hi_u32 s30, s5, s8 1677; GFX9-NEXT: s_add_i32 s24, s24, s25 1678; GFX9-NEXT: s_add_u32 s22, s22, s30 1679; GFX9-NEXT: s_cselect_b32 s25, 1, 0 1680; GFX9-NEXT: s_mul_hi_u32 s31, s4, s9 1681; GFX9-NEXT: s_add_i32 s24, s24, s25 1682; GFX9-NEXT: s_add_u32 s22, s22, s31 1683; GFX9-NEXT: s_cselect_b32 s25, 1, 0 1684; GFX9-NEXT: s_mul_hi_u32 s33, s3, s10 1685; GFX9-NEXT: s_add_i32 s24, s24, s25 1686; GFX9-NEXT: s_add_u32 s22, s22, s33 1687; GFX9-NEXT: s_cselect_b32 s25, 1, 0 1688; GFX9-NEXT: s_mul_hi_u32 s34, s2, s11 1689; GFX9-NEXT: s_add_i32 s24, s24, s25 1690; GFX9-NEXT: s_add_u32 s22, s22, s34 1691; GFX9-NEXT: s_cselect_b32 s25, 1, 0 1692; GFX9-NEXT: s_mul_hi_u32 s35, s1, s12 1693; GFX9-NEXT: s_add_i32 s24, s24, s25 1694; GFX9-NEXT: s_add_u32 s22, s22, s35 1695; GFX9-NEXT: s_cselect_b32 s25, 1, 0 1696; GFX9-NEXT: s_mul_hi_u32 s36, s16, s13 1697; GFX9-NEXT: s_add_i32 s24, s24, s25 1698; GFX9-NEXT: s_add_u32 s22, s22, s36 1699; GFX9-NEXT: s_cselect_b32 s25, 1, 0 1700; GFX9-NEXT: s_add_i32 s24, s24, s25 1701; GFX9-NEXT: s_add_u32 s22, s22, s23 1702; GFX9-NEXT: s_cselect_b32 s23, 1, 0 1703; GFX9-NEXT: s_add_i32 s24, s24, s23 1704; GFX9-NEXT: s_mul_i32 s7, s7, s8 1705; GFX9-NEXT: s_mul_i32 s23, s6, s9 1706; GFX9-NEXT: s_mul_i32 s25, s5, s10 1707; GFX9-NEXT: s_add_i32 s7, s7, s23 1708; GFX9-NEXT: s_mul_i32 s26, s4, s11 1709; GFX9-NEXT: s_add_i32 s7, s7, s25 1710; GFX9-NEXT: s_mul_i32 s27, s3, s12 1711; GFX9-NEXT: s_add_i32 s7, s7, s26 1712; GFX9-NEXT: s_mul_i32 s28, s2, s13 1713; GFX9-NEXT: s_add_i32 s7, s7, s27 1714; GFX9-NEXT: s_mul_i32 s29, s1, s14 1715; GFX9-NEXT: s_add_i32 s7, s7, s28 1716; GFX9-NEXT: s_mul_i32 s15, s16, s15 1717; GFX9-NEXT: s_add_i32 s7, s7, s29 1718; GFX9-NEXT: s_mul_hi_u32 s6, s6, s8 1719; GFX9-NEXT: s_add_i32 s7, s7, s15 1720; GFX9-NEXT: s_mul_hi_u32 s5, s5, s9 1721; GFX9-NEXT: s_add_i32 s6, s7, s6 1722; GFX9-NEXT: s_mul_hi_u32 s4, s4, s10 1723; GFX9-NEXT: s_add_i32 s5, s6, s5 1724; GFX9-NEXT: s_mul_hi_u32 s3, s3, s11 1725; GFX9-NEXT: s_add_i32 s4, s5, s4 1726; GFX9-NEXT: s_mul_hi_u32 s2, s2, s12 1727; GFX9-NEXT: s_add_i32 s3, s4, s3 1728; GFX9-NEXT: s_mul_hi_u32 s1, s1, s13 1729; GFX9-NEXT: s_add_i32 s2, s3, s2 1730; GFX9-NEXT: s_mul_i32 s0, s0, s8 1731; GFX9-NEXT: s_mul_hi_u32 s8, s16, s14 1732; GFX9-NEXT: s_add_i32 s1, s2, s1 1733; GFX9-NEXT: s_add_i32 s1, s1, s8 1734; GFX9-NEXT: s_add_i32 s7, s1, s24 1735; GFX9-NEXT: s_mov_b32 s1, s17 1736; GFX9-NEXT: s_mov_b32 s2, s18 1737; GFX9-NEXT: s_mov_b32 s3, s19 1738; GFX9-NEXT: s_mov_b32 s4, s20 1739; GFX9-NEXT: s_mov_b32 s5, s21 1740; GFX9-NEXT: s_mov_b32 s6, s22 1741; GFX9-NEXT: ; return to shader part epilog 1742; 1743; GFX10-LABEL: s_mul_i256: 1744; GFX10: ; %bb.0: 1745; GFX10-NEXT: s_mul_i32 s16, s1, s8 1746; GFX10-NEXT: s_mul_i32 s17, s0, s9 1747; GFX10-NEXT: s_mul_hi_u32 s18, s0, s8 1748; GFX10-NEXT: s_add_u32 s16, s16, s17 1749; GFX10-NEXT: s_cselect_b32 s17, 1, 0 1750; GFX10-NEXT: s_add_u32 s16, s16, s18 1751; GFX10-NEXT: s_cselect_b32 s18, 1, 0 1752; GFX10-NEXT: s_mul_i32 s19, s1, s9 1753; GFX10-NEXT: s_add_i32 s17, s17, s18 1754; GFX10-NEXT: s_mul_i32 s18, s2, s8 1755; GFX10-NEXT: s_mul_i32 s20, s0, s10 1756; GFX10-NEXT: s_add_u32 s18, s18, s19 1757; GFX10-NEXT: s_cselect_b32 s19, 1, 0 1758; GFX10-NEXT: s_add_u32 s18, s18, s20 1759; GFX10-NEXT: s_cselect_b32 s20, 1, 0 1760; GFX10-NEXT: s_mul_hi_u32 s21, s1, s8 1761; GFX10-NEXT: s_add_i32 s19, s19, s20 1762; GFX10-NEXT: s_add_u32 s18, s18, s21 1763; GFX10-NEXT: s_cselect_b32 s20, 1, 0 1764; GFX10-NEXT: s_mul_hi_u32 s22, s0, s9 1765; GFX10-NEXT: s_add_i32 s19, s19, s20 1766; GFX10-NEXT: s_add_u32 s18, s18, s22 1767; GFX10-NEXT: s_cselect_b32 s20, 1, 0 1768; GFX10-NEXT: s_mul_i32 s21, s1, s10 1769; GFX10-NEXT: s_add_i32 s19, s19, s20 1770; GFX10-NEXT: s_add_u32 s17, s18, s17 1771; GFX10-NEXT: s_cselect_b32 s18, 1, 0 1772; GFX10-NEXT: s_mul_i32 s20, s2, s9 1773; GFX10-NEXT: s_add_i32 s19, s19, s18 1774; GFX10-NEXT: s_mul_i32 s18, s3, s8 1775; GFX10-NEXT: s_mul_i32 s22, s0, s11 1776; GFX10-NEXT: s_add_u32 s18, s18, s20 1777; GFX10-NEXT: s_cselect_b32 s20, 1, 0 1778; GFX10-NEXT: s_add_u32 s18, s18, s21 1779; GFX10-NEXT: s_cselect_b32 s21, 1, 0 1780; GFX10-NEXT: s_mul_hi_u32 s23, s2, s8 1781; GFX10-NEXT: s_add_i32 s20, s20, s21 1782; GFX10-NEXT: s_add_u32 s18, s18, s22 1783; GFX10-NEXT: s_cselect_b32 s21, 1, 0 1784; GFX10-NEXT: s_mul_hi_u32 s24, s1, s9 1785; GFX10-NEXT: s_add_i32 s20, s20, s21 1786; GFX10-NEXT: s_add_u32 s18, s18, s23 1787; GFX10-NEXT: s_cselect_b32 s21, 1, 0 1788; GFX10-NEXT: s_mul_hi_u32 s25, s0, s10 1789; GFX10-NEXT: s_add_i32 s20, s20, s21 1790; GFX10-NEXT: s_add_u32 s18, s18, s24 1791; GFX10-NEXT: s_cselect_b32 s21, 1, 0 1792; GFX10-NEXT: s_mul_i32 s22, s2, s10 1793; GFX10-NEXT: s_add_i32 s20, s20, s21 1794; GFX10-NEXT: s_add_u32 s18, s18, s25 1795; GFX10-NEXT: s_cselect_b32 s21, 1, 0 1796; GFX10-NEXT: s_mul_i32 s23, s1, s11 1797; GFX10-NEXT: s_add_i32 s20, s20, s21 1798; GFX10-NEXT: s_add_u32 s18, s18, s19 1799; GFX10-NEXT: s_cselect_b32 s19, 1, 0 1800; GFX10-NEXT: s_mul_i32 s21, s3, s9 1801; GFX10-NEXT: s_add_i32 s20, s20, s19 1802; GFX10-NEXT: s_mul_i32 s19, s4, s8 1803; GFX10-NEXT: s_mul_i32 s24, s0, s12 1804; GFX10-NEXT: s_add_u32 s19, s19, s21 1805; GFX10-NEXT: s_cselect_b32 s21, 1, 0 1806; GFX10-NEXT: s_add_u32 s19, s19, s22 1807; GFX10-NEXT: s_cselect_b32 s22, 1, 0 1808; GFX10-NEXT: s_mul_hi_u32 s25, s3, s8 1809; GFX10-NEXT: s_add_i32 s21, s21, s22 1810; GFX10-NEXT: s_add_u32 s19, s19, s23 1811; GFX10-NEXT: s_cselect_b32 s22, 1, 0 1812; GFX10-NEXT: s_mul_hi_u32 s26, s2, s9 1813; GFX10-NEXT: s_add_i32 s21, s21, s22 1814; GFX10-NEXT: s_add_u32 s19, s19, s24 1815; GFX10-NEXT: s_cselect_b32 s22, 1, 0 1816; GFX10-NEXT: s_mul_hi_u32 s27, s1, s10 1817; GFX10-NEXT: s_add_i32 s21, s21, s22 1818; GFX10-NEXT: s_add_u32 s19, s19, s25 1819; GFX10-NEXT: s_cselect_b32 s22, 1, 0 1820; GFX10-NEXT: s_mul_hi_u32 s28, s0, s11 1821; GFX10-NEXT: s_add_i32 s21, s21, s22 1822; GFX10-NEXT: s_add_u32 s19, s19, s26 1823; GFX10-NEXT: s_cselect_b32 s22, 1, 0 1824; GFX10-NEXT: s_mul_i32 s23, s3, s10 1825; GFX10-NEXT: s_add_i32 s21, s21, s22 1826; GFX10-NEXT: s_add_u32 s19, s19, s27 1827; GFX10-NEXT: s_cselect_b32 s22, 1, 0 1828; GFX10-NEXT: s_mul_i32 s24, s2, s11 1829; GFX10-NEXT: s_add_i32 s21, s21, s22 1830; GFX10-NEXT: s_add_u32 s19, s19, s28 1831; GFX10-NEXT: s_cselect_b32 s22, 1, 0 1832; GFX10-NEXT: s_mul_i32 s25, s1, s12 1833; GFX10-NEXT: s_add_i32 s21, s21, s22 1834; GFX10-NEXT: s_add_u32 s19, s19, s20 1835; GFX10-NEXT: s_cselect_b32 s20, 1, 0 1836; GFX10-NEXT: s_mul_i32 s22, s4, s9 1837; GFX10-NEXT: s_add_i32 s21, s21, s20 1838; GFX10-NEXT: s_mul_i32 s20, s5, s8 1839; GFX10-NEXT: s_mul_i32 s26, s0, s13 1840; GFX10-NEXT: s_add_u32 s20, s20, s22 1841; GFX10-NEXT: s_cselect_b32 s22, 1, 0 1842; GFX10-NEXT: s_add_u32 s20, s20, s23 1843; GFX10-NEXT: s_cselect_b32 s23, 1, 0 1844; GFX10-NEXT: s_mul_hi_u32 s27, s4, s8 1845; GFX10-NEXT: s_add_i32 s22, s22, s23 1846; GFX10-NEXT: s_add_u32 s20, s20, s24 1847; GFX10-NEXT: s_cselect_b32 s23, 1, 0 1848; GFX10-NEXT: s_mul_hi_u32 s28, s3, s9 1849; GFX10-NEXT: s_add_i32 s22, s22, s23 1850; GFX10-NEXT: s_add_u32 s20, s20, s25 1851; GFX10-NEXT: s_cselect_b32 s23, 1, 0 1852; GFX10-NEXT: s_mul_hi_u32 s29, s2, s10 1853; GFX10-NEXT: s_add_i32 s22, s22, s23 1854; GFX10-NEXT: s_add_u32 s20, s20, s26 1855; GFX10-NEXT: s_cselect_b32 s23, 1, 0 1856; GFX10-NEXT: s_mul_hi_u32 s30, s1, s11 1857; GFX10-NEXT: s_add_i32 s22, s22, s23 1858; GFX10-NEXT: s_add_u32 s20, s20, s27 1859; GFX10-NEXT: s_cselect_b32 s23, 1, 0 1860; GFX10-NEXT: s_mul_hi_u32 s31, s0, s12 1861; GFX10-NEXT: s_add_i32 s22, s22, s23 1862; GFX10-NEXT: s_add_u32 s20, s20, s28 1863; GFX10-NEXT: s_cselect_b32 s23, 1, 0 1864; GFX10-NEXT: s_mul_i32 s24, s4, s10 1865; GFX10-NEXT: s_add_i32 s22, s22, s23 1866; GFX10-NEXT: s_add_u32 s20, s20, s29 1867; GFX10-NEXT: s_cselect_b32 s23, 1, 0 1868; GFX10-NEXT: s_mul_i32 s25, s3, s11 1869; GFX10-NEXT: s_add_i32 s22, s22, s23 1870; GFX10-NEXT: s_add_u32 s20, s20, s30 1871; GFX10-NEXT: s_cselect_b32 s23, 1, 0 1872; GFX10-NEXT: s_mul_i32 s26, s2, s12 1873; GFX10-NEXT: s_add_i32 s22, s22, s23 1874; GFX10-NEXT: s_add_u32 s20, s20, s31 1875; GFX10-NEXT: s_cselect_b32 s23, 1, 0 1876; GFX10-NEXT: s_mul_i32 s27, s1, s13 1877; GFX10-NEXT: s_add_i32 s22, s22, s23 1878; GFX10-NEXT: s_add_u32 s20, s20, s21 1879; GFX10-NEXT: s_cselect_b32 s21, 1, 0 1880; GFX10-NEXT: s_mul_i32 s23, s5, s9 1881; GFX10-NEXT: s_add_i32 s22, s22, s21 1882; GFX10-NEXT: s_mul_i32 s21, s6, s8 1883; GFX10-NEXT: s_mul_i32 s28, s0, s14 1884; GFX10-NEXT: s_add_u32 s21, s21, s23 1885; GFX10-NEXT: s_cselect_b32 s23, 1, 0 1886; GFX10-NEXT: s_add_u32 s21, s21, s24 1887; GFX10-NEXT: s_cselect_b32 s24, 1, 0 1888; GFX10-NEXT: s_mul_hi_u32 s29, s5, s8 1889; GFX10-NEXT: s_add_i32 s23, s23, s24 1890; GFX10-NEXT: s_add_u32 s21, s21, s25 1891; GFX10-NEXT: s_cselect_b32 s24, 1, 0 1892; GFX10-NEXT: s_mul_hi_u32 s30, s4, s9 1893; GFX10-NEXT: s_add_i32 s23, s23, s24 1894; GFX10-NEXT: s_add_u32 s21, s21, s26 1895; GFX10-NEXT: s_cselect_b32 s24, 1, 0 1896; GFX10-NEXT: s_mul_hi_u32 s31, s3, s10 1897; GFX10-NEXT: s_add_i32 s23, s23, s24 1898; GFX10-NEXT: s_add_u32 s21, s21, s27 1899; GFX10-NEXT: s_cselect_b32 s24, 1, 0 1900; GFX10-NEXT: s_mul_hi_u32 s33, s2, s11 1901; GFX10-NEXT: s_add_i32 s23, s23, s24 1902; GFX10-NEXT: s_add_u32 s21, s21, s28 1903; GFX10-NEXT: s_cselect_b32 s24, 1, 0 1904; GFX10-NEXT: s_mul_hi_u32 s34, s1, s12 1905; GFX10-NEXT: s_add_i32 s23, s23, s24 1906; GFX10-NEXT: s_add_u32 s21, s21, s29 1907; GFX10-NEXT: s_cselect_b32 s24, 1, 0 1908; GFX10-NEXT: s_mul_hi_u32 s35, s0, s13 1909; GFX10-NEXT: s_add_i32 s23, s23, s24 1910; GFX10-NEXT: s_add_u32 s21, s21, s30 1911; GFX10-NEXT: s_cselect_b32 s24, 1, 0 1912; GFX10-NEXT: s_mul_i32 s7, s7, s8 1913; GFX10-NEXT: s_add_i32 s23, s23, s24 1914; GFX10-NEXT: s_add_u32 s21, s21, s31 1915; GFX10-NEXT: s_cselect_b32 s24, 1, 0 1916; GFX10-NEXT: s_mul_i32 s25, s5, s10 1917; GFX10-NEXT: s_add_i32 s23, s23, s24 1918; GFX10-NEXT: s_add_u32 s21, s21, s33 1919; GFX10-NEXT: s_cselect_b32 s24, 1, 0 1920; GFX10-NEXT: s_mul_i32 s15, s0, s15 1921; GFX10-NEXT: s_add_i32 s23, s23, s24 1922; GFX10-NEXT: s_add_u32 s21, s21, s34 1923; GFX10-NEXT: s_cselect_b32 s24, 1, 0 1924; GFX10-NEXT: s_mul_hi_u32 s5, s5, s9 1925; GFX10-NEXT: s_add_i32 s23, s23, s24 1926; GFX10-NEXT: s_add_u32 s21, s21, s35 1927; GFX10-NEXT: s_cselect_b32 s24, 1, 0 1928; GFX10-NEXT: s_add_i32 s23, s23, s24 1929; GFX10-NEXT: s_mul_i32 s24, s6, s9 1930; GFX10-NEXT: s_add_u32 s21, s21, s22 1931; GFX10-NEXT: s_cselect_b32 s22, 1, 0 1932; GFX10-NEXT: s_add_i32 s7, s7, s24 1933; GFX10-NEXT: s_mul_i32 s24, s4, s11 1934; GFX10-NEXT: s_add_i32 s7, s7, s25 1935; GFX10-NEXT: s_mul_i32 s25, s3, s12 1936; GFX10-NEXT: s_add_i32 s7, s7, s24 1937; GFX10-NEXT: s_mul_i32 s24, s2, s13 1938; GFX10-NEXT: s_add_i32 s7, s7, s25 1939; GFX10-NEXT: s_mul_i32 s25, s1, s14 1940; GFX10-NEXT: s_add_i32 s7, s7, s24 1941; GFX10-NEXT: s_mul_hi_u32 s6, s6, s8 1942; GFX10-NEXT: s_add_i32 s7, s7, s25 1943; GFX10-NEXT: s_mul_hi_u32 s4, s4, s10 1944; GFX10-NEXT: s_add_i32 s7, s7, s15 1945; GFX10-NEXT: s_mul_hi_u32 s3, s3, s11 1946; GFX10-NEXT: s_add_i32 s6, s7, s6 1947; GFX10-NEXT: s_mul_hi_u32 s2, s2, s12 1948; GFX10-NEXT: s_add_i32 s5, s6, s5 1949; GFX10-NEXT: s_mul_hi_u32 s1, s1, s13 1950; GFX10-NEXT: s_add_i32 s4, s5, s4 1951; GFX10-NEXT: s_add_i32 s23, s23, s22 1952; GFX10-NEXT: s_add_i32 s3, s4, s3 1953; GFX10-NEXT: s_mov_b32 s4, s19 1954; GFX10-NEXT: s_add_i32 s2, s3, s2 1955; GFX10-NEXT: s_mul_hi_u32 s3, s0, s14 1956; GFX10-NEXT: s_add_i32 s1, s2, s1 1957; GFX10-NEXT: s_mul_i32 s0, s0, s8 1958; GFX10-NEXT: s_add_i32 s1, s1, s3 1959; GFX10-NEXT: s_mov_b32 s2, s17 1960; GFX10-NEXT: s_add_i32 s7, s1, s23 1961; GFX10-NEXT: s_mov_b32 s1, s16 1962; GFX10-NEXT: s_mov_b32 s3, s18 1963; GFX10-NEXT: s_mov_b32 s5, s20 1964; GFX10-NEXT: s_mov_b32 s6, s21 1965; GFX10-NEXT: ; return to shader part epilog 1966 %result = mul i256 %num, %den 1967 %cast = bitcast i256 %result to <8 x i32> 1968 ret <8 x i32> %cast 1969} 1970 1971define i256 @v_mul_i256(i256 %num, i256 %den) { 1972; GFX7-LABEL: v_mul_i256: 1973; GFX7: ; %bb.0: 1974; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1975; GFX7-NEXT: v_mul_lo_u32 v16, v1, v8 1976; GFX7-NEXT: v_mul_lo_u32 v17, v0, v9 1977; GFX7-NEXT: v_mul_hi_u32 v18, v0, v8 1978; GFX7-NEXT: v_mul_lo_u32 v19, v2, v8 1979; GFX7-NEXT: v_mul_lo_u32 v20, v1, v9 1980; GFX7-NEXT: v_add_i32_e32 v16, vcc, v16, v17 1981; GFX7-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc 1982; GFX7-NEXT: v_add_i32_e32 v16, vcc, v16, v18 1983; GFX7-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc 1984; GFX7-NEXT: v_add_i32_e32 v17, vcc, v17, v18 1985; GFX7-NEXT: v_mul_lo_u32 v18, v0, v10 1986; GFX7-NEXT: v_add_i32_e32 v19, vcc, v19, v20 1987; GFX7-NEXT: v_mul_hi_u32 v21, v1, v8 1988; GFX7-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc 1989; GFX7-NEXT: v_add_i32_e32 v18, vcc, v19, v18 1990; GFX7-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc 1991; GFX7-NEXT: v_add_i32_e32 v19, vcc, v20, v19 1992; GFX7-NEXT: v_add_i32_e32 v18, vcc, v18, v21 1993; GFX7-NEXT: v_mul_hi_u32 v21, v0, v9 1994; GFX7-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc 1995; GFX7-NEXT: v_add_i32_e32 v19, vcc, v19, v20 1996; GFX7-NEXT: v_add_i32_e32 v18, vcc, v18, v21 1997; GFX7-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc 1998; GFX7-NEXT: v_add_i32_e32 v19, vcc, v19, v20 1999; GFX7-NEXT: v_add_i32_e32 v17, vcc, v18, v17 2000; GFX7-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc 2001; GFX7-NEXT: v_mul_lo_u32 v20, v3, v8 2002; GFX7-NEXT: v_mul_lo_u32 v21, v2, v9 2003; GFX7-NEXT: v_add_i32_e32 v18, vcc, v19, v18 2004; GFX7-NEXT: v_mul_lo_u32 v19, v1, v10 2005; GFX7-NEXT: v_add_i32_e32 v20, vcc, v20, v21 2006; GFX7-NEXT: v_mul_lo_u32 v22, v0, v11 2007; GFX7-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc 2008; GFX7-NEXT: v_add_i32_e32 v19, vcc, v20, v19 2009; GFX7-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc 2010; GFX7-NEXT: v_add_i32_e32 v20, vcc, v21, v20 2011; GFX7-NEXT: v_add_i32_e32 v19, vcc, v19, v22 2012; GFX7-NEXT: v_mul_hi_u32 v22, v2, v8 2013; GFX7-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc 2014; GFX7-NEXT: v_add_i32_e32 v20, vcc, v20, v21 2015; GFX7-NEXT: v_add_i32_e32 v19, vcc, v19, v22 2016; GFX7-NEXT: v_mul_hi_u32 v22, v1, v9 2017; GFX7-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc 2018; GFX7-NEXT: v_add_i32_e32 v20, vcc, v20, v21 2019; GFX7-NEXT: v_add_i32_e32 v19, vcc, v19, v22 2020; GFX7-NEXT: v_mul_hi_u32 v22, v0, v10 2021; GFX7-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc 2022; GFX7-NEXT: v_add_i32_e32 v20, vcc, v20, v21 2023; GFX7-NEXT: v_add_i32_e32 v19, vcc, v19, v22 2024; GFX7-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc 2025; GFX7-NEXT: v_add_i32_e32 v20, vcc, v20, v21 2026; GFX7-NEXT: v_add_i32_e32 v18, vcc, v19, v18 2027; GFX7-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc 2028; GFX7-NEXT: v_mul_lo_u32 v21, v4, v8 2029; GFX7-NEXT: v_mul_lo_u32 v22, v3, v9 2030; GFX7-NEXT: v_add_i32_e32 v19, vcc, v20, v19 2031; GFX7-NEXT: v_mul_lo_u32 v20, v2, v10 2032; GFX7-NEXT: v_add_i32_e32 v21, vcc, v21, v22 2033; GFX7-NEXT: v_mul_lo_u32 v23, v1, v11 2034; GFX7-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2035; GFX7-NEXT: v_add_i32_e32 v20, vcc, v21, v20 2036; GFX7-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc 2037; GFX7-NEXT: v_add_i32_e32 v21, vcc, v22, v21 2038; GFX7-NEXT: v_add_i32_e32 v20, vcc, v20, v23 2039; GFX7-NEXT: v_mul_lo_u32 v23, v0, v12 2040; GFX7-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2041; GFX7-NEXT: v_add_i32_e32 v21, vcc, v21, v22 2042; GFX7-NEXT: v_add_i32_e32 v20, vcc, v20, v23 2043; GFX7-NEXT: v_mul_hi_u32 v23, v3, v8 2044; GFX7-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2045; GFX7-NEXT: v_add_i32_e32 v21, vcc, v21, v22 2046; GFX7-NEXT: v_add_i32_e32 v20, vcc, v20, v23 2047; GFX7-NEXT: v_mul_hi_u32 v23, v2, v9 2048; GFX7-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2049; GFX7-NEXT: v_add_i32_e32 v21, vcc, v21, v22 2050; GFX7-NEXT: v_add_i32_e32 v20, vcc, v20, v23 2051; GFX7-NEXT: v_mul_hi_u32 v23, v1, v10 2052; GFX7-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2053; GFX7-NEXT: v_add_i32_e32 v21, vcc, v21, v22 2054; GFX7-NEXT: v_add_i32_e32 v20, vcc, v20, v23 2055; GFX7-NEXT: v_mul_hi_u32 v23, v0, v11 2056; GFX7-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2057; GFX7-NEXT: v_add_i32_e32 v21, vcc, v21, v22 2058; GFX7-NEXT: v_add_i32_e32 v20, vcc, v20, v23 2059; GFX7-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2060; GFX7-NEXT: v_add_i32_e32 v21, vcc, v21, v22 2061; GFX7-NEXT: v_add_i32_e32 v19, vcc, v20, v19 2062; GFX7-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc 2063; GFX7-NEXT: v_mul_lo_u32 v22, v5, v8 2064; GFX7-NEXT: v_mul_lo_u32 v23, v4, v9 2065; GFX7-NEXT: v_add_i32_e32 v20, vcc, v21, v20 2066; GFX7-NEXT: v_mul_lo_u32 v21, v3, v10 2067; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v23 2068; GFX7-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2069; GFX7-NEXT: v_add_i32_e32 v21, vcc, v22, v21 2070; GFX7-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2071; GFX7-NEXT: v_add_i32_e32 v22, vcc, v23, v22 2072; GFX7-NEXT: v_mul_lo_u32 v23, v2, v11 2073; GFX7-NEXT: v_mul_lo_u32 v7, v7, v8 2074; GFX7-NEXT: v_mul_lo_u32 v15, v0, v15 2075; GFX7-NEXT: v_add_i32_e32 v21, vcc, v21, v23 2076; GFX7-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2077; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v23 2078; GFX7-NEXT: v_mul_lo_u32 v23, v1, v12 2079; GFX7-NEXT: v_add_i32_e32 v21, vcc, v21, v23 2080; GFX7-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2081; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v23 2082; GFX7-NEXT: v_mul_lo_u32 v23, v0, v13 2083; GFX7-NEXT: v_add_i32_e32 v21, vcc, v21, v23 2084; GFX7-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2085; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v23 2086; GFX7-NEXT: v_mul_hi_u32 v23, v4, v8 2087; GFX7-NEXT: v_add_i32_e32 v21, vcc, v21, v23 2088; GFX7-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2089; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v23 2090; GFX7-NEXT: v_mul_hi_u32 v23, v3, v9 2091; GFX7-NEXT: v_add_i32_e32 v21, vcc, v21, v23 2092; GFX7-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2093; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v23 2094; GFX7-NEXT: v_mul_hi_u32 v23, v2, v10 2095; GFX7-NEXT: v_add_i32_e32 v21, vcc, v21, v23 2096; GFX7-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2097; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v23 2098; GFX7-NEXT: v_mul_hi_u32 v23, v1, v11 2099; GFX7-NEXT: v_add_i32_e32 v21, vcc, v21, v23 2100; GFX7-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2101; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v23 2102; GFX7-NEXT: v_mul_hi_u32 v23, v0, v12 2103; GFX7-NEXT: v_add_i32_e32 v21, vcc, v21, v23 2104; GFX7-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2105; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v23 2106; GFX7-NEXT: v_add_i32_e32 v20, vcc, v21, v20 2107; GFX7-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc 2108; GFX7-NEXT: v_add_i32_e32 v21, vcc, v22, v21 2109; GFX7-NEXT: v_mul_lo_u32 v22, v6, v8 2110; GFX7-NEXT: v_mul_lo_u32 v23, v5, v9 2111; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v23 2112; GFX7-NEXT: v_mul_lo_u32 v23, v4, v10 2113; GFX7-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2114; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v23 2115; GFX7-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2116; GFX7-NEXT: v_add_i32_e32 v23, vcc, v24, v23 2117; GFX7-NEXT: v_mul_lo_u32 v24, v3, v11 2118; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v24 2119; GFX7-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2120; GFX7-NEXT: v_add_i32_e32 v23, vcc, v23, v24 2121; GFX7-NEXT: v_mul_lo_u32 v24, v2, v12 2122; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v24 2123; GFX7-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2124; GFX7-NEXT: v_add_i32_e32 v23, vcc, v23, v24 2125; GFX7-NEXT: v_mul_lo_u32 v24, v1, v13 2126; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v24 2127; GFX7-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2128; GFX7-NEXT: v_add_i32_e32 v23, vcc, v23, v24 2129; GFX7-NEXT: v_mul_lo_u32 v24, v0, v14 2130; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v24 2131; GFX7-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2132; GFX7-NEXT: v_add_i32_e32 v23, vcc, v23, v24 2133; GFX7-NEXT: v_mul_hi_u32 v24, v5, v8 2134; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v24 2135; GFX7-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2136; GFX7-NEXT: v_add_i32_e32 v23, vcc, v23, v24 2137; GFX7-NEXT: v_mul_hi_u32 v24, v4, v9 2138; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v24 2139; GFX7-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2140; GFX7-NEXT: v_add_i32_e32 v23, vcc, v23, v24 2141; GFX7-NEXT: v_mul_hi_u32 v24, v3, v10 2142; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v24 2143; GFX7-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2144; GFX7-NEXT: v_add_i32_e32 v23, vcc, v23, v24 2145; GFX7-NEXT: v_mul_hi_u32 v24, v2, v11 2146; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v24 2147; GFX7-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2148; GFX7-NEXT: v_add_i32_e32 v23, vcc, v23, v24 2149; GFX7-NEXT: v_mul_hi_u32 v24, v1, v12 2150; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v24 2151; GFX7-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2152; GFX7-NEXT: v_add_i32_e32 v23, vcc, v23, v24 2153; GFX7-NEXT: v_mul_hi_u32 v24, v0, v13 2154; GFX7-NEXT: v_add_i32_e32 v22, vcc, v22, v24 2155; GFX7-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2156; GFX7-NEXT: v_add_i32_e32 v23, vcc, v23, v24 2157; GFX7-NEXT: v_add_i32_e32 v21, vcc, v22, v21 2158; GFX7-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2159; GFX7-NEXT: v_add_i32_e32 v23, vcc, v23, v22 2160; GFX7-NEXT: v_mul_lo_u32 v22, v0, v8 2161; GFX7-NEXT: v_mul_hi_u32 v8, v6, v8 2162; GFX7-NEXT: v_mul_lo_u32 v6, v6, v9 2163; GFX7-NEXT: v_mul_hi_u32 v9, v5, v9 2164; GFX7-NEXT: v_mul_lo_u32 v5, v5, v10 2165; GFX7-NEXT: v_mul_hi_u32 v10, v4, v10 2166; GFX7-NEXT: v_mul_lo_u32 v4, v4, v11 2167; GFX7-NEXT: v_mul_hi_u32 v11, v3, v11 2168; GFX7-NEXT: v_mul_lo_u32 v3, v3, v12 2169; GFX7-NEXT: v_mul_hi_u32 v12, v2, v12 2170; GFX7-NEXT: v_mul_lo_u32 v2, v2, v13 2171; GFX7-NEXT: v_add_i32_e32 v6, vcc, v7, v6 2172; GFX7-NEXT: v_mul_hi_u32 v13, v1, v13 2173; GFX7-NEXT: v_mul_lo_u32 v1, v1, v14 2174; GFX7-NEXT: v_add_i32_e32 v5, vcc, v6, v5 2175; GFX7-NEXT: v_add_i32_e32 v4, vcc, v5, v4 2176; GFX7-NEXT: v_add_i32_e32 v3, vcc, v4, v3 2177; GFX7-NEXT: v_add_i32_e32 v2, vcc, v3, v2 2178; GFX7-NEXT: v_add_i32_e32 v1, vcc, v2, v1 2179; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v15 2180; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v8 2181; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v9 2182; GFX7-NEXT: v_mul_hi_u32 v0, v0, v14 2183; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v10 2184; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v11 2185; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v12 2186; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v13 2187; GFX7-NEXT: v_add_i32_e32 v0, vcc, v1, v0 2188; GFX7-NEXT: v_add_i32_e32 v7, vcc, v0, v23 2189; GFX7-NEXT: v_mov_b32_e32 v0, v22 2190; GFX7-NEXT: v_mov_b32_e32 v1, v16 2191; GFX7-NEXT: v_mov_b32_e32 v2, v17 2192; GFX7-NEXT: v_mov_b32_e32 v3, v18 2193; GFX7-NEXT: v_mov_b32_e32 v4, v19 2194; GFX7-NEXT: v_mov_b32_e32 v5, v20 2195; GFX7-NEXT: v_mov_b32_e32 v6, v21 2196; GFX7-NEXT: s_setpc_b64 s[30:31] 2197; 2198; GFX8-LABEL: v_mul_i256: 2199; GFX8: ; %bb.0: 2200; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2201; GFX8-NEXT: v_mul_lo_u32 v16, v1, v8 2202; GFX8-NEXT: v_mul_lo_u32 v17, v0, v9 2203; GFX8-NEXT: v_mul_hi_u32 v18, v0, v8 2204; GFX8-NEXT: v_mul_lo_u32 v19, v2, v8 2205; GFX8-NEXT: v_mul_lo_u32 v20, v1, v9 2206; GFX8-NEXT: v_add_u32_e32 v16, vcc, v16, v17 2207; GFX8-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc 2208; GFX8-NEXT: v_add_u32_e32 v16, vcc, v16, v18 2209; GFX8-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc 2210; GFX8-NEXT: v_add_u32_e32 v17, vcc, v17, v18 2211; GFX8-NEXT: v_mul_lo_u32 v18, v0, v10 2212; GFX8-NEXT: v_add_u32_e32 v19, vcc, v19, v20 2213; GFX8-NEXT: v_mul_hi_u32 v21, v1, v8 2214; GFX8-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc 2215; GFX8-NEXT: v_add_u32_e32 v18, vcc, v19, v18 2216; GFX8-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc 2217; GFX8-NEXT: v_add_u32_e32 v19, vcc, v20, v19 2218; GFX8-NEXT: v_add_u32_e32 v18, vcc, v18, v21 2219; GFX8-NEXT: v_mul_hi_u32 v21, v0, v9 2220; GFX8-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc 2221; GFX8-NEXT: v_add_u32_e32 v19, vcc, v19, v20 2222; GFX8-NEXT: v_add_u32_e32 v18, vcc, v18, v21 2223; GFX8-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc 2224; GFX8-NEXT: v_add_u32_e32 v19, vcc, v19, v20 2225; GFX8-NEXT: v_add_u32_e32 v17, vcc, v18, v17 2226; GFX8-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc 2227; GFX8-NEXT: v_mul_lo_u32 v20, v3, v8 2228; GFX8-NEXT: v_mul_lo_u32 v21, v2, v9 2229; GFX8-NEXT: v_add_u32_e32 v18, vcc, v19, v18 2230; GFX8-NEXT: v_mul_lo_u32 v19, v1, v10 2231; GFX8-NEXT: v_add_u32_e32 v20, vcc, v20, v21 2232; GFX8-NEXT: v_mul_lo_u32 v22, v0, v11 2233; GFX8-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc 2234; GFX8-NEXT: v_add_u32_e32 v19, vcc, v20, v19 2235; GFX8-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc 2236; GFX8-NEXT: v_add_u32_e32 v20, vcc, v21, v20 2237; GFX8-NEXT: v_add_u32_e32 v19, vcc, v19, v22 2238; GFX8-NEXT: v_mul_hi_u32 v22, v2, v8 2239; GFX8-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc 2240; GFX8-NEXT: v_add_u32_e32 v20, vcc, v20, v21 2241; GFX8-NEXT: v_add_u32_e32 v19, vcc, v19, v22 2242; GFX8-NEXT: v_mul_hi_u32 v22, v1, v9 2243; GFX8-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc 2244; GFX8-NEXT: v_add_u32_e32 v20, vcc, v20, v21 2245; GFX8-NEXT: v_add_u32_e32 v19, vcc, v19, v22 2246; GFX8-NEXT: v_mul_hi_u32 v22, v0, v10 2247; GFX8-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc 2248; GFX8-NEXT: v_add_u32_e32 v20, vcc, v20, v21 2249; GFX8-NEXT: v_add_u32_e32 v19, vcc, v19, v22 2250; GFX8-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc 2251; GFX8-NEXT: v_add_u32_e32 v20, vcc, v20, v21 2252; GFX8-NEXT: v_add_u32_e32 v18, vcc, v19, v18 2253; GFX8-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc 2254; GFX8-NEXT: v_mul_lo_u32 v21, v4, v8 2255; GFX8-NEXT: v_mul_lo_u32 v22, v3, v9 2256; GFX8-NEXT: v_add_u32_e32 v19, vcc, v20, v19 2257; GFX8-NEXT: v_mul_lo_u32 v20, v2, v10 2258; GFX8-NEXT: v_add_u32_e32 v21, vcc, v21, v22 2259; GFX8-NEXT: v_mul_lo_u32 v23, v1, v11 2260; GFX8-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2261; GFX8-NEXT: v_add_u32_e32 v20, vcc, v21, v20 2262; GFX8-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc 2263; GFX8-NEXT: v_add_u32_e32 v21, vcc, v22, v21 2264; GFX8-NEXT: v_add_u32_e32 v20, vcc, v20, v23 2265; GFX8-NEXT: v_mul_lo_u32 v23, v0, v12 2266; GFX8-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2267; GFX8-NEXT: v_add_u32_e32 v21, vcc, v21, v22 2268; GFX8-NEXT: v_add_u32_e32 v20, vcc, v20, v23 2269; GFX8-NEXT: v_mul_hi_u32 v23, v3, v8 2270; GFX8-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2271; GFX8-NEXT: v_add_u32_e32 v21, vcc, v21, v22 2272; GFX8-NEXT: v_add_u32_e32 v20, vcc, v20, v23 2273; GFX8-NEXT: v_mul_hi_u32 v23, v2, v9 2274; GFX8-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2275; GFX8-NEXT: v_add_u32_e32 v21, vcc, v21, v22 2276; GFX8-NEXT: v_add_u32_e32 v20, vcc, v20, v23 2277; GFX8-NEXT: v_mul_hi_u32 v23, v1, v10 2278; GFX8-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2279; GFX8-NEXT: v_add_u32_e32 v21, vcc, v21, v22 2280; GFX8-NEXT: v_add_u32_e32 v20, vcc, v20, v23 2281; GFX8-NEXT: v_mul_hi_u32 v23, v0, v11 2282; GFX8-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2283; GFX8-NEXT: v_add_u32_e32 v21, vcc, v21, v22 2284; GFX8-NEXT: v_add_u32_e32 v20, vcc, v20, v23 2285; GFX8-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2286; GFX8-NEXT: v_add_u32_e32 v21, vcc, v21, v22 2287; GFX8-NEXT: v_add_u32_e32 v19, vcc, v20, v19 2288; GFX8-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc 2289; GFX8-NEXT: v_mul_lo_u32 v22, v5, v8 2290; GFX8-NEXT: v_mul_lo_u32 v23, v4, v9 2291; GFX8-NEXT: v_add_u32_e32 v20, vcc, v21, v20 2292; GFX8-NEXT: v_mul_lo_u32 v21, v3, v10 2293; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v23 2294; GFX8-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2295; GFX8-NEXT: v_add_u32_e32 v21, vcc, v22, v21 2296; GFX8-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2297; GFX8-NEXT: v_add_u32_e32 v22, vcc, v23, v22 2298; GFX8-NEXT: v_mul_lo_u32 v23, v2, v11 2299; GFX8-NEXT: v_mul_lo_u32 v7, v7, v8 2300; GFX8-NEXT: v_mul_lo_u32 v15, v0, v15 2301; GFX8-NEXT: v_add_u32_e32 v21, vcc, v21, v23 2302; GFX8-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2303; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v23 2304; GFX8-NEXT: v_mul_lo_u32 v23, v1, v12 2305; GFX8-NEXT: v_add_u32_e32 v21, vcc, v21, v23 2306; GFX8-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2307; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v23 2308; GFX8-NEXT: v_mul_lo_u32 v23, v0, v13 2309; GFX8-NEXT: v_add_u32_e32 v21, vcc, v21, v23 2310; GFX8-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2311; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v23 2312; GFX8-NEXT: v_mul_hi_u32 v23, v4, v8 2313; GFX8-NEXT: v_add_u32_e32 v21, vcc, v21, v23 2314; GFX8-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2315; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v23 2316; GFX8-NEXT: v_mul_hi_u32 v23, v3, v9 2317; GFX8-NEXT: v_add_u32_e32 v21, vcc, v21, v23 2318; GFX8-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2319; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v23 2320; GFX8-NEXT: v_mul_hi_u32 v23, v2, v10 2321; GFX8-NEXT: v_add_u32_e32 v21, vcc, v21, v23 2322; GFX8-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2323; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v23 2324; GFX8-NEXT: v_mul_hi_u32 v23, v1, v11 2325; GFX8-NEXT: v_add_u32_e32 v21, vcc, v21, v23 2326; GFX8-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2327; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v23 2328; GFX8-NEXT: v_mul_hi_u32 v23, v0, v12 2329; GFX8-NEXT: v_add_u32_e32 v21, vcc, v21, v23 2330; GFX8-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2331; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v23 2332; GFX8-NEXT: v_add_u32_e32 v20, vcc, v21, v20 2333; GFX8-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc 2334; GFX8-NEXT: v_add_u32_e32 v21, vcc, v22, v21 2335; GFX8-NEXT: v_mul_lo_u32 v22, v6, v8 2336; GFX8-NEXT: v_mul_lo_u32 v23, v5, v9 2337; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v23 2338; GFX8-NEXT: v_mul_lo_u32 v23, v4, v10 2339; GFX8-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2340; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v23 2341; GFX8-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2342; GFX8-NEXT: v_add_u32_e32 v23, vcc, v24, v23 2343; GFX8-NEXT: v_mul_lo_u32 v24, v3, v11 2344; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v24 2345; GFX8-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2346; GFX8-NEXT: v_add_u32_e32 v23, vcc, v23, v24 2347; GFX8-NEXT: v_mul_lo_u32 v24, v2, v12 2348; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v24 2349; GFX8-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2350; GFX8-NEXT: v_add_u32_e32 v23, vcc, v23, v24 2351; GFX8-NEXT: v_mul_lo_u32 v24, v1, v13 2352; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v24 2353; GFX8-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2354; GFX8-NEXT: v_add_u32_e32 v23, vcc, v23, v24 2355; GFX8-NEXT: v_mul_lo_u32 v24, v0, v14 2356; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v24 2357; GFX8-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2358; GFX8-NEXT: v_add_u32_e32 v23, vcc, v23, v24 2359; GFX8-NEXT: v_mul_hi_u32 v24, v5, v8 2360; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v24 2361; GFX8-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2362; GFX8-NEXT: v_add_u32_e32 v23, vcc, v23, v24 2363; GFX8-NEXT: v_mul_hi_u32 v24, v4, v9 2364; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v24 2365; GFX8-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2366; GFX8-NEXT: v_add_u32_e32 v23, vcc, v23, v24 2367; GFX8-NEXT: v_mul_hi_u32 v24, v3, v10 2368; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v24 2369; GFX8-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2370; GFX8-NEXT: v_add_u32_e32 v23, vcc, v23, v24 2371; GFX8-NEXT: v_mul_hi_u32 v24, v2, v11 2372; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v24 2373; GFX8-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2374; GFX8-NEXT: v_add_u32_e32 v23, vcc, v23, v24 2375; GFX8-NEXT: v_mul_hi_u32 v24, v1, v12 2376; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v24 2377; GFX8-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2378; GFX8-NEXT: v_add_u32_e32 v23, vcc, v23, v24 2379; GFX8-NEXT: v_mul_hi_u32 v24, v0, v13 2380; GFX8-NEXT: v_add_u32_e32 v22, vcc, v22, v24 2381; GFX8-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2382; GFX8-NEXT: v_add_u32_e32 v23, vcc, v23, v24 2383; GFX8-NEXT: v_add_u32_e32 v21, vcc, v22, v21 2384; GFX8-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2385; GFX8-NEXT: v_add_u32_e32 v23, vcc, v23, v22 2386; GFX8-NEXT: v_mul_lo_u32 v22, v0, v8 2387; GFX8-NEXT: v_mul_hi_u32 v8, v6, v8 2388; GFX8-NEXT: v_mul_lo_u32 v6, v6, v9 2389; GFX8-NEXT: v_mul_hi_u32 v9, v5, v9 2390; GFX8-NEXT: v_mul_lo_u32 v5, v5, v10 2391; GFX8-NEXT: v_mul_hi_u32 v10, v4, v10 2392; GFX8-NEXT: v_mul_lo_u32 v4, v4, v11 2393; GFX8-NEXT: v_mul_hi_u32 v11, v3, v11 2394; GFX8-NEXT: v_mul_lo_u32 v3, v3, v12 2395; GFX8-NEXT: v_mul_hi_u32 v12, v2, v12 2396; GFX8-NEXT: v_mul_lo_u32 v2, v2, v13 2397; GFX8-NEXT: v_add_u32_e32 v6, vcc, v7, v6 2398; GFX8-NEXT: v_mul_hi_u32 v13, v1, v13 2399; GFX8-NEXT: v_mul_lo_u32 v1, v1, v14 2400; GFX8-NEXT: v_add_u32_e32 v5, vcc, v6, v5 2401; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4 2402; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3 2403; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2 2404; GFX8-NEXT: v_add_u32_e32 v1, vcc, v2, v1 2405; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v15 2406; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v8 2407; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v9 2408; GFX8-NEXT: v_mul_hi_u32 v0, v0, v14 2409; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v10 2410; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v11 2411; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v12 2412; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v13 2413; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0 2414; GFX8-NEXT: v_add_u32_e32 v7, vcc, v0, v23 2415; GFX8-NEXT: v_mov_b32_e32 v0, v22 2416; GFX8-NEXT: v_mov_b32_e32 v1, v16 2417; GFX8-NEXT: v_mov_b32_e32 v2, v17 2418; GFX8-NEXT: v_mov_b32_e32 v3, v18 2419; GFX8-NEXT: v_mov_b32_e32 v4, v19 2420; GFX8-NEXT: v_mov_b32_e32 v5, v20 2421; GFX8-NEXT: v_mov_b32_e32 v6, v21 2422; GFX8-NEXT: s_setpc_b64 s[30:31] 2423; 2424; GFX9-LABEL: v_mul_i256: 2425; GFX9: ; %bb.0: 2426; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2427; GFX9-NEXT: v_mul_lo_u32 v16, v2, v8 2428; GFX9-NEXT: v_mul_lo_u32 v17, v1, v9 2429; GFX9-NEXT: v_mul_lo_u32 v18, v0, v10 2430; GFX9-NEXT: v_mul_hi_u32 v19, v1, v8 2431; GFX9-NEXT: v_mul_lo_u32 v20, v1, v8 2432; GFX9-NEXT: v_add_co_u32_e32 v16, vcc, v16, v17 2433; GFX9-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc 2434; GFX9-NEXT: v_add_co_u32_e32 v16, vcc, v16, v18 2435; GFX9-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc 2436; GFX9-NEXT: v_add_co_u32_e32 v19, vcc, v16, v19 2437; GFX9-NEXT: v_mul_lo_u32 v21, v0, v9 2438; GFX9-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc 2439; GFX9-NEXT: v_add3_u32 v18, v17, v18, v16 2440; GFX9-NEXT: v_mul_hi_u32 v16, v0, v8 2441; GFX9-NEXT: v_add_co_u32_e32 v17, vcc, v20, v21 2442; GFX9-NEXT: v_mul_hi_u32 v21, v0, v9 2443; GFX9-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc 2444; GFX9-NEXT: v_add_co_u32_e32 v16, vcc, v17, v16 2445; GFX9-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc 2446; GFX9-NEXT: v_add_u32_e32 v17, v20, v17 2447; GFX9-NEXT: v_add_co_u32_e32 v19, vcc, v19, v21 2448; GFX9-NEXT: v_mul_lo_u32 v21, v3, v8 2449; GFX9-NEXT: v_mul_lo_u32 v22, v2, v9 2450; GFX9-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc 2451; GFX9-NEXT: v_add_co_u32_e32 v17, vcc, v19, v17 2452; GFX9-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc 2453; GFX9-NEXT: v_add3_u32 v18, v18, v20, v19 2454; GFX9-NEXT: v_mul_lo_u32 v19, v1, v10 2455; GFX9-NEXT: v_add_co_u32_e32 v20, vcc, v21, v22 2456; GFX9-NEXT: v_mul_lo_u32 v22, v0, v11 2457; GFX9-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc 2458; GFX9-NEXT: v_add_co_u32_e32 v19, vcc, v20, v19 2459; GFX9-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc 2460; GFX9-NEXT: v_add_co_u32_e32 v19, vcc, v19, v22 2461; GFX9-NEXT: v_mul_hi_u32 v23, v2, v8 2462; GFX9-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2463; GFX9-NEXT: v_add3_u32 v20, v21, v20, v22 2464; GFX9-NEXT: v_mul_hi_u32 v21, v1, v9 2465; GFX9-NEXT: v_add_co_u32_e32 v19, vcc, v19, v23 2466; GFX9-NEXT: v_mul_hi_u32 v23, v0, v10 2467; GFX9-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2468; GFX9-NEXT: v_add_co_u32_e32 v19, vcc, v19, v21 2469; GFX9-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc 2470; GFX9-NEXT: v_add3_u32 v20, v20, v22, v21 2471; GFX9-NEXT: v_add_co_u32_e32 v19, vcc, v19, v23 2472; GFX9-NEXT: v_mul_lo_u32 v22, v4, v8 2473; GFX9-NEXT: v_mul_lo_u32 v23, v3, v9 2474; GFX9-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc 2475; GFX9-NEXT: v_add_co_u32_e32 v18, vcc, v19, v18 2476; GFX9-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc 2477; GFX9-NEXT: v_add3_u32 v19, v20, v21, v19 2478; GFX9-NEXT: v_mul_lo_u32 v20, v2, v10 2479; GFX9-NEXT: v_add_co_u32_e32 v21, vcc, v22, v23 2480; GFX9-NEXT: v_mul_lo_u32 v23, v1, v11 2481; GFX9-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2482; GFX9-NEXT: v_add_co_u32_e32 v20, vcc, v21, v20 2483; GFX9-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc 2484; GFX9-NEXT: v_add_co_u32_e32 v20, vcc, v20, v23 2485; GFX9-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2486; GFX9-NEXT: v_add3_u32 v21, v22, v21, v23 2487; GFX9-NEXT: v_mul_lo_u32 v22, v0, v12 2488; GFX9-NEXT: v_mul_hi_u32 v23, v3, v8 2489; GFX9-NEXT: v_mul_lo_u32 v7, v7, v8 2490; GFX9-NEXT: v_add_co_u32_e32 v20, vcc, v20, v22 2491; GFX9-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2492; GFX9-NEXT: v_add_co_u32_e32 v20, vcc, v20, v23 2493; GFX9-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2494; GFX9-NEXT: v_add3_u32 v21, v21, v22, v23 2495; GFX9-NEXT: v_mul_hi_u32 v22, v2, v9 2496; GFX9-NEXT: v_mul_hi_u32 v23, v1, v10 2497; GFX9-NEXT: v_add_co_u32_e32 v20, vcc, v20, v22 2498; GFX9-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2499; GFX9-NEXT: v_add_co_u32_e32 v20, vcc, v20, v23 2500; GFX9-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2501; GFX9-NEXT: v_add3_u32 v21, v21, v22, v23 2502; GFX9-NEXT: v_mul_hi_u32 v22, v0, v11 2503; GFX9-NEXT: v_mul_lo_u32 v23, v3, v10 2504; GFX9-NEXT: v_add_co_u32_e32 v20, vcc, v20, v22 2505; GFX9-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2506; GFX9-NEXT: v_add_co_u32_e32 v19, vcc, v20, v19 2507; GFX9-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc 2508; GFX9-NEXT: v_add3_u32 v20, v21, v22, v20 2509; GFX9-NEXT: v_mul_lo_u32 v21, v5, v8 2510; GFX9-NEXT: v_mul_lo_u32 v22, v4, v9 2511; GFX9-NEXT: v_add_co_u32_e32 v21, vcc, v21, v22 2512; GFX9-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2513; GFX9-NEXT: v_add_co_u32_e32 v21, vcc, v21, v23 2514; GFX9-NEXT: v_mul_lo_u32 v23, v2, v11 2515; GFX9-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2516; GFX9-NEXT: v_add_co_u32_e32 v21, vcc, v21, v23 2517; GFX9-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2518; GFX9-NEXT: v_add3_u32 v22, v22, v24, v23 2519; GFX9-NEXT: v_mul_lo_u32 v23, v1, v12 2520; GFX9-NEXT: v_add_co_u32_e32 v21, vcc, v21, v23 2521; GFX9-NEXT: v_mul_lo_u32 v23, v0, v13 2522; GFX9-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2523; GFX9-NEXT: v_add_co_u32_e32 v21, vcc, v21, v23 2524; GFX9-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2525; GFX9-NEXT: v_add3_u32 v22, v22, v24, v23 2526; GFX9-NEXT: v_mul_hi_u32 v23, v4, v8 2527; GFX9-NEXT: v_add_co_u32_e32 v21, vcc, v21, v23 2528; GFX9-NEXT: v_mul_hi_u32 v23, v3, v9 2529; GFX9-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2530; GFX9-NEXT: v_add_co_u32_e32 v21, vcc, v21, v23 2531; GFX9-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2532; GFX9-NEXT: v_add3_u32 v22, v22, v24, v23 2533; GFX9-NEXT: v_mul_hi_u32 v23, v2, v10 2534; GFX9-NEXT: v_add_co_u32_e32 v21, vcc, v21, v23 2535; GFX9-NEXT: v_mul_hi_u32 v23, v1, v11 2536; GFX9-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2537; GFX9-NEXT: v_add_co_u32_e32 v21, vcc, v21, v23 2538; GFX9-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2539; GFX9-NEXT: v_add3_u32 v22, v22, v24, v23 2540; GFX9-NEXT: v_mul_hi_u32 v23, v0, v12 2541; GFX9-NEXT: v_add_co_u32_e32 v21, vcc, v21, v23 2542; GFX9-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2543; GFX9-NEXT: v_add_co_u32_e32 v20, vcc, v21, v20 2544; GFX9-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc 2545; GFX9-NEXT: v_add3_u32 v21, v22, v23, v21 2546; GFX9-NEXT: v_mul_lo_u32 v22, v6, v8 2547; GFX9-NEXT: v_mul_lo_u32 v23, v5, v9 2548; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, v22, v23 2549; GFX9-NEXT: v_mul_lo_u32 v23, v4, v10 2550; GFX9-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2551; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, v22, v23 2552; GFX9-NEXT: v_mul_lo_u32 v23, v3, v11 2553; GFX9-NEXT: v_cndmask_b32_e64 v25, 0, 1, vcc 2554; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, v22, v23 2555; GFX9-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc 2556; GFX9-NEXT: v_add3_u32 v23, v24, v25, v23 2557; GFX9-NEXT: v_mul_lo_u32 v24, v2, v12 2558; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, v22, v24 2559; GFX9-NEXT: v_mul_lo_u32 v24, v1, v13 2560; GFX9-NEXT: v_cndmask_b32_e64 v25, 0, 1, vcc 2561; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, v22, v24 2562; GFX9-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2563; GFX9-NEXT: v_add3_u32 v23, v23, v25, v24 2564; GFX9-NEXT: v_mul_lo_u32 v24, v0, v14 2565; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, v22, v24 2566; GFX9-NEXT: v_mul_hi_u32 v24, v5, v8 2567; GFX9-NEXT: v_cndmask_b32_e64 v25, 0, 1, vcc 2568; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, v22, v24 2569; GFX9-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2570; GFX9-NEXT: v_add3_u32 v23, v23, v25, v24 2571; GFX9-NEXT: v_mul_hi_u32 v24, v4, v9 2572; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, v22, v24 2573; GFX9-NEXT: v_mul_hi_u32 v24, v3, v10 2574; GFX9-NEXT: v_cndmask_b32_e64 v25, 0, 1, vcc 2575; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, v22, v24 2576; GFX9-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2577; GFX9-NEXT: v_add3_u32 v23, v23, v25, v24 2578; GFX9-NEXT: v_mul_hi_u32 v24, v2, v11 2579; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, v22, v24 2580; GFX9-NEXT: v_mul_hi_u32 v24, v1, v12 2581; GFX9-NEXT: v_cndmask_b32_e64 v25, 0, 1, vcc 2582; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, v22, v24 2583; GFX9-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2584; GFX9-NEXT: v_add3_u32 v23, v23, v25, v24 2585; GFX9-NEXT: v_mul_hi_u32 v24, v0, v13 2586; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, v22, v24 2587; GFX9-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc 2588; GFX9-NEXT: v_add_co_u32_e32 v21, vcc, v22, v21 2589; GFX9-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc 2590; GFX9-NEXT: v_add3_u32 v22, v23, v24, v22 2591; GFX9-NEXT: v_mul_lo_u32 v23, v6, v9 2592; GFX9-NEXT: v_mul_lo_u32 v24, v4, v11 2593; GFX9-NEXT: v_mul_hi_u32 v4, v4, v10 2594; GFX9-NEXT: v_mul_hi_u32 v6, v6, v8 2595; GFX9-NEXT: v_add_u32_e32 v7, v7, v23 2596; GFX9-NEXT: v_mul_lo_u32 v23, v5, v10 2597; GFX9-NEXT: v_mul_hi_u32 v5, v5, v9 2598; GFX9-NEXT: v_mul_hi_u32 v9, v3, v11 2599; GFX9-NEXT: v_mul_lo_u32 v3, v3, v12 2600; GFX9-NEXT: v_mul_hi_u32 v10, v2, v12 2601; GFX9-NEXT: v_mul_lo_u32 v2, v2, v13 2602; GFX9-NEXT: v_mul_hi_u32 v11, v1, v13 2603; GFX9-NEXT: v_mul_lo_u32 v12, v1, v14 2604; GFX9-NEXT: v_mul_lo_u32 v13, v0, v15 2605; GFX9-NEXT: v_add3_u32 v7, v7, v23, v24 2606; GFX9-NEXT: v_add3_u32 v2, v7, v3, v2 2607; GFX9-NEXT: v_mul_lo_u32 v1, v0, v8 2608; GFX9-NEXT: v_mul_hi_u32 v0, v0, v14 2609; GFX9-NEXT: v_add3_u32 v2, v2, v12, v13 2610; GFX9-NEXT: v_add3_u32 v2, v2, v6, v5 2611; GFX9-NEXT: v_add3_u32 v2, v2, v4, v9 2612; GFX9-NEXT: v_add3_u32 v2, v2, v10, v11 2613; GFX9-NEXT: v_add3_u32 v7, v2, v0, v22 2614; GFX9-NEXT: v_mov_b32_e32 v0, v1 2615; GFX9-NEXT: v_mov_b32_e32 v1, v16 2616; GFX9-NEXT: v_mov_b32_e32 v2, v17 2617; GFX9-NEXT: v_mov_b32_e32 v3, v18 2618; GFX9-NEXT: v_mov_b32_e32 v4, v19 2619; GFX9-NEXT: v_mov_b32_e32 v5, v20 2620; GFX9-NEXT: v_mov_b32_e32 v6, v21 2621; GFX9-NEXT: s_setpc_b64 s[30:31] 2622; 2623; GFX10-LABEL: v_mul_i256: 2624; GFX10: ; %bb.0: 2625; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2626; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 2627; GFX10-NEXT: v_mul_lo_u32 v16, v1, v8 2628; GFX10-NEXT: v_mul_lo_u32 v17, v0, v9 2629; GFX10-NEXT: v_mul_hi_u32 v18, v0, v8 2630; GFX10-NEXT: v_mul_lo_u32 v19, v2, v8 2631; GFX10-NEXT: v_mul_lo_u32 v20, v1, v9 2632; GFX10-NEXT: v_mul_hi_u32 v21, v1, v8 2633; GFX10-NEXT: v_mul_lo_u32 v22, v3, v8 2634; GFX10-NEXT: v_mul_lo_u32 v25, v1, v10 2635; GFX10-NEXT: v_mul_hi_u32 v23, v0, v9 2636; GFX10-NEXT: v_add_co_u32 v16, s4, v16, v17 2637; GFX10-NEXT: v_cndmask_b32_e64 v17, 0, 1, s4 2638; GFX10-NEXT: v_mul_hi_u32 v27, v0, v10 2639; GFX10-NEXT: v_mul_hi_u32 v29, v3, v9 2640; GFX10-NEXT: v_add_co_u32 v16, s4, v16, v18 2641; GFX10-NEXT: v_cndmask_b32_e64 v18, 0, 1, s4 2642; GFX10-NEXT: v_add_co_u32 v19, s4, v19, v20 2643; GFX10-NEXT: v_mul_lo_u32 v20, v2, v9 2644; GFX10-NEXT: v_cndmask_b32_e64 v24, 0, 1, s4 2645; GFX10-NEXT: v_add_nc_u32_e32 v17, v17, v18 2646; GFX10-NEXT: v_mul_lo_u32 v18, v0, v10 2647; GFX10-NEXT: v_mul_hi_u32 v31, v4, v9 2648; GFX10-NEXT: v_mul_lo_u32 v7, v7, v8 2649; GFX10-NEXT: v_mul_lo_u32 v15, v0, v15 2650; GFX10-NEXT: v_add_co_u32 v18, s4, v19, v18 2651; GFX10-NEXT: v_cndmask_b32_e64 v19, 0, 1, s4 2652; GFX10-NEXT: v_add_co_u32 v20, s4, v22, v20 2653; GFX10-NEXT: v_add_co_u32 v18, s5, v18, v21 2654; GFX10-NEXT: v_cndmask_b32_e64 v21, 0, 1, s5 2655; GFX10-NEXT: v_mul_lo_u32 v22, v0, v11 2656; GFX10-NEXT: v_cndmask_b32_e64 v26, 0, 1, s4 2657; GFX10-NEXT: v_add_co_u32 v20, s4, v20, v25 2658; GFX10-NEXT: v_add3_u32 v19, v24, v19, v21 2659; GFX10-NEXT: v_mul_hi_u32 v21, v2, v8 2660; GFX10-NEXT: v_cndmask_b32_e64 v24, 0, 1, s4 2661; GFX10-NEXT: v_add_co_u32 v18, s5, v18, v23 2662; GFX10-NEXT: v_add_co_u32 v20, s4, v20, v22 2663; GFX10-NEXT: v_mul_hi_u32 v23, v1, v9 2664; GFX10-NEXT: v_cndmask_b32_e64 v25, 0, 1, s4 2665; GFX10-NEXT: v_cndmask_b32_e64 v22, 0, 1, s5 2666; GFX10-NEXT: v_add_co_u32 v20, s4, v20, v21 2667; GFX10-NEXT: v_add_co_u32 v17, s5, v18, v17 2668; GFX10-NEXT: v_add3_u32 v21, v26, v24, v25 2669; GFX10-NEXT: v_cndmask_b32_e64 v24, 0, 1, s4 2670; GFX10-NEXT: v_add_co_u32 v20, s4, v20, v23 2671; GFX10-NEXT: v_cndmask_b32_e64 v18, 0, 1, s5 2672; GFX10-NEXT: v_cndmask_b32_e64 v23, 0, 1, s4 2673; GFX10-NEXT: v_mul_lo_u32 v25, v4, v8 2674; GFX10-NEXT: v_mul_lo_u32 v26, v3, v9 2675; GFX10-NEXT: v_add_co_u32 v20, s5, v20, v27 2676; GFX10-NEXT: v_add3_u32 v18, v19, v22, v18 2677; GFX10-NEXT: v_add3_u32 v19, v21, v24, v23 2678; GFX10-NEXT: v_mul_lo_u32 v21, v2, v10 2679; GFX10-NEXT: v_mul_lo_u32 v24, v1, v11 2680; GFX10-NEXT: v_cndmask_b32_e64 v23, 0, 1, s5 2681; GFX10-NEXT: v_add_co_u32 v22, s4, v25, v26 2682; GFX10-NEXT: v_cndmask_b32_e64 v25, 0, 1, s4 2683; GFX10-NEXT: v_mul_hi_u32 v26, v3, v8 2684; GFX10-NEXT: v_add_co_u32 v21, s4, v22, v21 2685; GFX10-NEXT: v_mul_lo_u32 v22, v0, v12 2686; GFX10-NEXT: v_cndmask_b32_e64 v27, 0, 1, s4 2687; GFX10-NEXT: v_add_co_u32 v21, s4, v21, v24 2688; GFX10-NEXT: v_cndmask_b32_e64 v24, 0, 1, s4 2689; GFX10-NEXT: v_add_co_u32 v18, s4, v20, v18 2690; GFX10-NEXT: v_cndmask_b32_e64 v20, 0, 1, s4 2691; GFX10-NEXT: v_add_co_u32 v21, s4, v21, v22 2692; GFX10-NEXT: v_mul_hi_u32 v22, v2, v9 2693; GFX10-NEXT: v_add3_u32 v24, v25, v27, v24 2694; GFX10-NEXT: v_cndmask_b32_e64 v25, 0, 1, s4 2695; GFX10-NEXT: v_add_co_u32 v21, s4, v21, v26 2696; GFX10-NEXT: v_cndmask_b32_e64 v26, 0, 1, s4 2697; GFX10-NEXT: v_add3_u32 v19, v19, v23, v20 2698; GFX10-NEXT: v_mul_hi_u32 v20, v1, v10 2699; GFX10-NEXT: v_add_co_u32 v21, s4, v21, v22 2700; GFX10-NEXT: v_add3_u32 v23, v24, v25, v26 2701; GFX10-NEXT: v_mul_lo_u32 v22, v5, v8 2702; GFX10-NEXT: v_mul_lo_u32 v24, v4, v9 2703; GFX10-NEXT: v_cndmask_b32_e64 v25, 0, 1, s4 2704; GFX10-NEXT: v_mul_lo_u32 v26, v3, v10 2705; GFX10-NEXT: v_add_co_u32 v20, s4, v21, v20 2706; GFX10-NEXT: v_cndmask_b32_e64 v21, 0, 1, s4 2707; GFX10-NEXT: v_mul_hi_u32 v27, v0, v11 2708; GFX10-NEXT: v_add_co_u32 v22, s4, v22, v24 2709; GFX10-NEXT: v_add3_u32 v21, v23, v25, v21 2710; GFX10-NEXT: v_mul_lo_u32 v23, v2, v11 2711; GFX10-NEXT: v_cndmask_b32_e64 v24, 0, 1, s4 2712; GFX10-NEXT: v_add_co_u32 v22, s4, v22, v26 2713; GFX10-NEXT: v_mul_lo_u32 v26, v1, v12 2714; GFX10-NEXT: v_add_co_u32 v20, s5, v20, v27 2715; GFX10-NEXT: v_cndmask_b32_e64 v27, 0, 1, s4 2716; GFX10-NEXT: v_add_co_u32 v22, s4, v22, v23 2717; GFX10-NEXT: v_mul_lo_u32 v23, v0, v13 2718; GFX10-NEXT: v_cndmask_b32_e64 v28, 0, 1, s4 2719; GFX10-NEXT: v_cndmask_b32_e64 v25, 0, 1, s5 2720; GFX10-NEXT: v_add_co_u32 v22, s4, v22, v26 2721; GFX10-NEXT: v_mul_hi_u32 v26, v4, v8 2722; GFX10-NEXT: v_add_co_u32 v19, s5, v20, v19 2723; GFX10-NEXT: v_cndmask_b32_e64 v20, 0, 1, s5 2724; GFX10-NEXT: v_cndmask_b32_e64 v30, 0, 1, s4 2725; GFX10-NEXT: v_add_co_u32 v22, s4, v22, v23 2726; GFX10-NEXT: v_add3_u32 v23, v24, v27, v28 2727; GFX10-NEXT: v_cndmask_b32_e64 v24, 0, 1, s4 2728; GFX10-NEXT: v_add3_u32 v20, v21, v25, v20 2729; GFX10-NEXT: v_add_co_u32 v21, s4, v22, v26 2730; GFX10-NEXT: v_mul_hi_u32 v22, v2, v10 2731; GFX10-NEXT: v_add3_u32 v23, v23, v30, v24 2732; GFX10-NEXT: v_cndmask_b32_e64 v24, 0, 1, s4 2733; GFX10-NEXT: v_add_co_u32 v21, s4, v21, v29 2734; GFX10-NEXT: v_cndmask_b32_e64 v25, 0, 1, s4 2735; GFX10-NEXT: v_mul_hi_u32 v26, v1, v11 2736; GFX10-NEXT: v_mul_lo_u32 v27, v6, v8 2737; GFX10-NEXT: v_mul_lo_u32 v28, v5, v9 2738; GFX10-NEXT: v_add_co_u32 v21, s4, v21, v22 2739; GFX10-NEXT: v_add3_u32 v23, v23, v24, v25 2740; GFX10-NEXT: v_mul_lo_u32 v24, v4, v10 2741; GFX10-NEXT: v_cndmask_b32_e64 v22, 0, 1, s4 2742; GFX10-NEXT: v_add_co_u32 v21, s5, v21, v26 2743; GFX10-NEXT: v_add_co_u32 v25, s4, v27, v28 2744; GFX10-NEXT: v_cndmask_b32_e64 v26, 0, 1, s5 2745; GFX10-NEXT: v_mul_lo_u32 v27, v3, v11 2746; GFX10-NEXT: v_cndmask_b32_e64 v28, 0, 1, s4 2747; GFX10-NEXT: v_add_co_u32 v24, s4, v25, v24 2748; GFX10-NEXT: v_mul_hi_u32 v29, v0, v12 2749; GFX10-NEXT: v_add3_u32 v22, v23, v22, v26 2750; GFX10-NEXT: v_mul_lo_u32 v23, v2, v12 2751; GFX10-NEXT: v_cndmask_b32_e64 v25, 0, 1, s4 2752; GFX10-NEXT: v_add_co_u32 v24, s4, v24, v27 2753; GFX10-NEXT: v_mul_lo_u32 v27, v1, v13 2754; GFX10-NEXT: v_add_co_u32 v21, s5, v21, v29 2755; GFX10-NEXT: v_cndmask_b32_e64 v29, 0, 1, s4 2756; GFX10-NEXT: v_add_co_u32 v23, s4, v24, v23 2757; GFX10-NEXT: v_mul_lo_u32 v24, v0, v14 2758; GFX10-NEXT: v_cndmask_b32_e64 v30, 0, 1, s4 2759; GFX10-NEXT: v_cndmask_b32_e64 v26, 0, 1, s5 2760; GFX10-NEXT: v_add_co_u32 v23, s4, v23, v27 2761; GFX10-NEXT: v_mul_hi_u32 v27, v5, v8 2762; GFX10-NEXT: v_cndmask_b32_e64 v32, 0, 1, s4 2763; GFX10-NEXT: v_add_co_u32 v20, s5, v21, v20 2764; GFX10-NEXT: v_add_co_u32 v23, s4, v23, v24 2765; GFX10-NEXT: v_add3_u32 v24, v28, v25, v29 2766; GFX10-NEXT: v_cndmask_b32_e64 v28, 0, 1, s4 2767; GFX10-NEXT: v_mul_hi_u32 v25, v3, v10 2768; GFX10-NEXT: v_add_co_u32 v23, s4, v23, v27 2769; GFX10-NEXT: v_cndmask_b32_e64 v21, 0, 1, s5 2770; GFX10-NEXT: v_add3_u32 v24, v24, v30, v32 2771; GFX10-NEXT: v_cndmask_b32_e64 v27, 0, 1, s4 2772; GFX10-NEXT: v_add_co_u32 v23, s4, v23, v31 2773; GFX10-NEXT: v_add3_u32 v21, v22, v26, v21 2774; GFX10-NEXT: v_mul_hi_u32 v26, v2, v11 2775; GFX10-NEXT: v_add3_u32 v22, v24, v28, v27 2776; GFX10-NEXT: v_cndmask_b32_e64 v24, 0, 1, s4 2777; GFX10-NEXT: v_add_co_u32 v23, s4, v23, v25 2778; GFX10-NEXT: v_cndmask_b32_e64 v25, 0, 1, s4 2779; GFX10-NEXT: v_mul_lo_u32 v28, v6, v9 2780; GFX10-NEXT: v_mul_lo_u32 v29, v3, v12 2781; GFX10-NEXT: v_mul_hi_u32 v27, v1, v12 2782; GFX10-NEXT: v_add_co_u32 v23, s4, v23, v26 2783; GFX10-NEXT: v_add3_u32 v22, v22, v24, v25 2784; GFX10-NEXT: v_mul_lo_u32 v24, v5, v10 2785; GFX10-NEXT: v_mul_lo_u32 v25, v4, v11 2786; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v28 2787; GFX10-NEXT: v_mul_lo_u32 v28, v2, v13 2788; GFX10-NEXT: v_mul_hi_u32 v6, v6, v8 2789; GFX10-NEXT: v_mul_hi_u32 v5, v5, v9 2790; GFX10-NEXT: v_cndmask_b32_e64 v26, 0, 1, s4 2791; GFX10-NEXT: v_add_co_u32 v23, s4, v23, v27 2792; GFX10-NEXT: v_add3_u32 v7, v7, v24, v25 2793; GFX10-NEXT: v_mul_lo_u32 v24, v1, v14 2794; GFX10-NEXT: v_mul_hi_u32 v25, v0, v13 2795; GFX10-NEXT: v_mul_hi_u32 v4, v4, v10 2796; GFX10-NEXT: v_mul_hi_u32 v3, v3, v11 2797; GFX10-NEXT: v_add3_u32 v7, v7, v29, v28 2798; GFX10-NEXT: v_cndmask_b32_e64 v27, 0, 1, s4 2799; GFX10-NEXT: v_mul_hi_u32 v2, v2, v12 2800; GFX10-NEXT: v_mul_hi_u32 v1, v1, v13 2801; GFX10-NEXT: v_add3_u32 v7, v7, v24, v15 2802; GFX10-NEXT: v_add_co_u32 v9, s4, v23, v25 2803; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s4 2804; GFX10-NEXT: v_add3_u32 v22, v22, v26, v27 2805; GFX10-NEXT: v_add3_u32 v5, v7, v6, v5 2806; GFX10-NEXT: v_add_co_u32 v6, s4, v9, v21 2807; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s4 2808; GFX10-NEXT: v_add3_u32 v3, v5, v4, v3 2809; GFX10-NEXT: v_mul_hi_u32 v4, v0, v14 2810; GFX10-NEXT: v_mul_lo_u32 v0, v0, v8 2811; GFX10-NEXT: v_add3_u32 v5, v22, v10, v7 2812; GFX10-NEXT: v_add3_u32 v1, v3, v2, v1 2813; GFX10-NEXT: v_mov_b32_e32 v2, v17 2814; GFX10-NEXT: v_mov_b32_e32 v3, v18 2815; GFX10-NEXT: v_add3_u32 v7, v1, v4, v5 2816; GFX10-NEXT: v_mov_b32_e32 v1, v16 2817; GFX10-NEXT: v_mov_b32_e32 v4, v19 2818; GFX10-NEXT: v_mov_b32_e32 v5, v20 2819; GFX10-NEXT: s_setpc_b64 s[30:31] 2820 %result = mul i256 %num, %den 2821 ret i256 %result 2822} 2823