1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s 3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s 4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s 5; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s 6 7define i8 @v_lshr_i8(i8 %value, i8 %amount) { 8; GFX6-LABEL: v_lshr_i8: 9; GFX6: ; %bb.0: 10; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 11; GFX6-NEXT: s_movk_i32 s4, 0xff 12; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 13; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 14; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0 15; GFX6-NEXT: s_setpc_b64 s[30:31] 16; 17; GFX8-LABEL: v_lshr_i8: 18; GFX8: ; %bb.0: 19; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 20; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 21; GFX8-NEXT: s_setpc_b64 s[30:31] 22; 23; GFX9-LABEL: v_lshr_i8: 24; GFX9: ; %bb.0: 25; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 26; GFX9-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 27; GFX9-NEXT: s_setpc_b64 s[30:31] 28; 29; GFX10-LABEL: v_lshr_i8: 30; GFX10: ; %bb.0: 31; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 32; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 33; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1 34; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0 35; GFX10-NEXT: v_lshrrev_b16 v0, v1, v0 36; GFX10-NEXT: s_setpc_b64 s[30:31] 37 %result = lshr i8 %value, %amount 38 ret i8 %result 39} 40 41define i8 @v_lshr_i8_7(i8 %value) { 42; GFX6-LABEL: v_lshr_i8_7: 43; GFX6: ; %bb.0: 44; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 45; GFX6-NEXT: v_bfe_u32 v0, v0, 7, 1 46; GFX6-NEXT: s_setpc_b64 s[30:31] 47; 48; GFX8-LABEL: v_lshr_i8_7: 49; GFX8: ; %bb.0: 50; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 51; GFX8-NEXT: v_mov_b32_e32 v1, 7 52; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 53; GFX8-NEXT: s_setpc_b64 s[30:31] 54; 55; GFX9-LABEL: v_lshr_i8_7: 56; GFX9: ; %bb.0: 57; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 58; GFX9-NEXT: v_mov_b32_e32 v1, 7 59; GFX9-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 60; GFX9-NEXT: s_setpc_b64 s[30:31] 61; 62; GFX10-LABEL: v_lshr_i8_7: 63; GFX10: ; %bb.0: 64; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 65; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 66; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0 67; GFX10-NEXT: v_lshrrev_b16 v0, 7, v0 68; GFX10-NEXT: s_setpc_b64 s[30:31] 69 %result = lshr i8 %value, 7 70 ret i8 %result 71} 72 73define amdgpu_ps i8 @s_lshr_i8(i8 inreg %value, i8 inreg %amount) { 74; GCN-LABEL: s_lshr_i8: 75; GCN: ; %bb.0: 76; GCN-NEXT: s_and_b32 s0, s0, 0xff 77; GCN-NEXT: s_lshr_b32 s0, s0, s1 78; GCN-NEXT: ; return to shader part epilog 79; 80; GFX10-LABEL: s_lshr_i8: 81; GFX10: ; %bb.0: 82; GFX10-NEXT: s_and_b32 s0, s0, 0xff 83; GFX10-NEXT: s_lshr_b32 s0, s0, s1 84; GFX10-NEXT: ; return to shader part epilog 85 %result = lshr i8 %value, %amount 86 ret i8 %result 87} 88 89define amdgpu_ps i8 @s_lshr_i8_7(i8 inreg %value) { 90; GCN-LABEL: s_lshr_i8_7: 91; GCN: ; %bb.0: 92; GCN-NEXT: s_bfe_u32 s0, s0, 0x10007 93; GCN-NEXT: ; return to shader part epilog 94; 95; GFX10-LABEL: s_lshr_i8_7: 96; GFX10: ; %bb.0: 97; GFX10-NEXT: s_bfe_u32 s0, s0, 0x10007 98; GFX10-NEXT: ; return to shader part epilog 99 %result = lshr i8 %value, 7 100 ret i8 %result 101} 102 103 104define i24 @v_lshr_i24(i24 %value, i24 %amount) { 105; GCN-LABEL: v_lshr_i24: 106; GCN: ; %bb.0: 107; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 108; GCN-NEXT: s_mov_b32 s4, 0xffffff 109; GCN-NEXT: v_and_b32_e32 v1, s4, v1 110; GCN-NEXT: v_and_b32_e32 v0, s4, v0 111; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0 112; GCN-NEXT: s_setpc_b64 s[30:31] 113; 114; GFX10-LABEL: v_lshr_i24: 115; GFX10: ; %bb.0: 116; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 117; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 118; GFX10-NEXT: s_mov_b32 s4, 0xffffff 119; GFX10-NEXT: v_and_b32_e32 v1, s4, v1 120; GFX10-NEXT: v_and_b32_e32 v0, s4, v0 121; GFX10-NEXT: v_lshrrev_b32_e32 v0, v1, v0 122; GFX10-NEXT: s_setpc_b64 s[30:31] 123 %result = lshr i24 %value, %amount 124 ret i24 %result 125} 126 127define i24 @v_lshr_i24_7(i24 %value) { 128; GCN-LABEL: v_lshr_i24_7: 129; GCN: ; %bb.0: 130; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 131; GCN-NEXT: v_bfe_u32 v0, v0, 7, 17 132; GCN-NEXT: s_setpc_b64 s[30:31] 133; 134; GFX10-LABEL: v_lshr_i24_7: 135; GFX10: ; %bb.0: 136; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 137; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 138; GFX10-NEXT: v_bfe_u32 v0, v0, 7, 17 139; GFX10-NEXT: s_setpc_b64 s[30:31] 140 %result = lshr i24 %value, 7 141 ret i24 %result 142} 143 144define amdgpu_ps i24 @s_lshr_i24(i24 inreg %value, i24 inreg %amount) { 145; GCN-LABEL: s_lshr_i24: 146; GCN: ; %bb.0: 147; GCN-NEXT: s_and_b32 s0, s0, 0xffffff 148; GCN-NEXT: s_lshr_b32 s0, s0, s1 149; GCN-NEXT: ; return to shader part epilog 150; 151; GFX10-LABEL: s_lshr_i24: 152; GFX10: ; %bb.0: 153; GFX10-NEXT: s_and_b32 s0, s0, 0xffffff 154; GFX10-NEXT: s_lshr_b32 s0, s0, s1 155; GFX10-NEXT: ; return to shader part epilog 156 %result = lshr i24 %value, %amount 157 ret i24 %result 158} 159 160define amdgpu_ps i24 @s_lshr_i24_7(i24 inreg %value) { 161; GCN-LABEL: s_lshr_i24_7: 162; GCN: ; %bb.0: 163; GCN-NEXT: s_bfe_u32 s0, s0, 0x110007 164; GCN-NEXT: ; return to shader part epilog 165; 166; GFX10-LABEL: s_lshr_i24_7: 167; GFX10: ; %bb.0: 168; GFX10-NEXT: s_bfe_u32 s0, s0, 0x110007 169; GFX10-NEXT: ; return to shader part epilog 170 %result = lshr i24 %value, 7 171 ret i24 %result 172} 173 174define i32 @v_lshr_i32(i32 %value, i32 %amount) { 175; GCN-LABEL: v_lshr_i32: 176; GCN: ; %bb.0: 177; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 178; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0 179; GCN-NEXT: s_setpc_b64 s[30:31] 180; 181; GFX10-LABEL: v_lshr_i32: 182; GFX10: ; %bb.0: 183; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 184; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 185; GFX10-NEXT: v_lshrrev_b32_e32 v0, v1, v0 186; GFX10-NEXT: s_setpc_b64 s[30:31] 187 %result = lshr i32 %value, %amount 188 ret i32 %result 189} 190 191define i32 @v_lshr_i32_31(i32 %value) { 192; GCN-LABEL: v_lshr_i32_31: 193; GCN: ; %bb.0: 194; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 195; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0 196; GCN-NEXT: s_setpc_b64 s[30:31] 197; 198; GFX10-LABEL: v_lshr_i32_31: 199; GFX10: ; %bb.0: 200; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 201; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 202; GFX10-NEXT: v_lshrrev_b32_e32 v0, 31, v0 203; GFX10-NEXT: s_setpc_b64 s[30:31] 204 %result = lshr i32 %value, 31 205 ret i32 %result 206} 207 208define amdgpu_ps i32 @s_lshr_i32(i32 inreg %value, i32 inreg %amount) { 209; GCN-LABEL: s_lshr_i32: 210; GCN: ; %bb.0: 211; GCN-NEXT: s_lshr_b32 s0, s0, s1 212; GCN-NEXT: ; return to shader part epilog 213; 214; GFX10-LABEL: s_lshr_i32: 215; GFX10: ; %bb.0: 216; GFX10-NEXT: s_lshr_b32 s0, s0, s1 217; GFX10-NEXT: ; return to shader part epilog 218 %result = lshr i32 %value, %amount 219 ret i32 %result 220} 221 222define amdgpu_ps i32 @s_lshr_i32_31(i32 inreg %value) { 223; GCN-LABEL: s_lshr_i32_31: 224; GCN: ; %bb.0: 225; GCN-NEXT: s_lshr_b32 s0, s0, 31 226; GCN-NEXT: ; return to shader part epilog 227; 228; GFX10-LABEL: s_lshr_i32_31: 229; GFX10: ; %bb.0: 230; GFX10-NEXT: s_lshr_b32 s0, s0, 31 231; GFX10-NEXT: ; return to shader part epilog 232 %result = lshr i32 %value, 31 233 ret i32 %result 234} 235 236define amdgpu_ps float @lshr_i32_sv(i32 inreg %value, i32 %amount) { 237; GFX6-LABEL: lshr_i32_sv: 238; GFX6: ; %bb.0: 239; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0 240; GFX6-NEXT: ; return to shader part epilog 241; 242; GFX8-LABEL: lshr_i32_sv: 243; GFX8: ; %bb.0: 244; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s0 245; GFX8-NEXT: ; return to shader part epilog 246; 247; GFX9-LABEL: lshr_i32_sv: 248; GFX9: ; %bb.0: 249; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s0 250; GFX9-NEXT: ; return to shader part epilog 251; 252; GFX10-LABEL: lshr_i32_sv: 253; GFX10: ; %bb.0: 254; GFX10-NEXT: v_lshrrev_b32_e64 v0, v0, s0 255; GFX10-NEXT: ; return to shader part epilog 256 %result = lshr i32 %value, %amount 257 %cast = bitcast i32 %result to float 258 ret float %cast 259} 260 261define amdgpu_ps float @lshr_i32_vs(i32 %value, i32 inreg %amount) { 262; GCN-LABEL: lshr_i32_vs: 263; GCN: ; %bb.0: 264; GCN-NEXT: v_lshrrev_b32_e32 v0, s0, v0 265; GCN-NEXT: ; return to shader part epilog 266; 267; GFX10-LABEL: lshr_i32_vs: 268; GFX10: ; %bb.0: 269; GFX10-NEXT: v_lshrrev_b32_e32 v0, s0, v0 270; GFX10-NEXT: ; return to shader part epilog 271 %result = lshr i32 %value, %amount 272 %cast = bitcast i32 %result to float 273 ret float %cast 274} 275 276define <2 x i32> @v_lshr_v2i32(<2 x i32> %value, <2 x i32> %amount) { 277; GCN-LABEL: v_lshr_v2i32: 278; GCN: ; %bb.0: 279; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 280; GCN-NEXT: v_lshrrev_b32_e32 v0, v2, v0 281; GCN-NEXT: v_lshrrev_b32_e32 v1, v3, v1 282; GCN-NEXT: s_setpc_b64 s[30:31] 283; 284; GFX10-LABEL: v_lshr_v2i32: 285; GFX10: ; %bb.0: 286; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 287; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 288; GFX10-NEXT: v_lshrrev_b32_e32 v0, v2, v0 289; GFX10-NEXT: v_lshrrev_b32_e32 v1, v3, v1 290; GFX10-NEXT: s_setpc_b64 s[30:31] 291 %result = lshr <2 x i32> %value, %amount 292 ret <2 x i32> %result 293} 294 295define <2 x i32> @v_lshr_v2i32_31(<2 x i32> %value) { 296; GCN-LABEL: v_lshr_v2i32_31: 297; GCN: ; %bb.0: 298; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 299; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0 300; GCN-NEXT: v_lshrrev_b32_e32 v1, 31, v1 301; GCN-NEXT: s_setpc_b64 s[30:31] 302; 303; GFX10-LABEL: v_lshr_v2i32_31: 304; GFX10: ; %bb.0: 305; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 306; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 307; GFX10-NEXT: v_lshrrev_b32_e32 v0, 31, v0 308; GFX10-NEXT: v_lshrrev_b32_e32 v1, 31, v1 309; GFX10-NEXT: s_setpc_b64 s[30:31] 310 %result = lshr <2 x i32> %value, <i32 31, i32 31> 311 ret <2 x i32> %result 312} 313 314define amdgpu_ps <2 x i32> @s_lshr_v2i32(<2 x i32> inreg %value, <2 x i32> inreg %amount) { 315; GCN-LABEL: s_lshr_v2i32: 316; GCN: ; %bb.0: 317; GCN-NEXT: s_lshr_b32 s0, s0, s2 318; GCN-NEXT: s_lshr_b32 s1, s1, s3 319; GCN-NEXT: ; return to shader part epilog 320; 321; GFX10-LABEL: s_lshr_v2i32: 322; GFX10: ; %bb.0: 323; GFX10-NEXT: s_lshr_b32 s0, s0, s2 324; GFX10-NEXT: s_lshr_b32 s1, s1, s3 325; GFX10-NEXT: ; return to shader part epilog 326 %result = lshr <2 x i32> %value, %amount 327 ret <2 x i32> %result 328} 329 330define <3 x i32> @v_lshr_v3i32(<3 x i32> %value, <3 x i32> %amount) { 331; GCN-LABEL: v_lshr_v3i32: 332; GCN: ; %bb.0: 333; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 334; GCN-NEXT: v_lshrrev_b32_e32 v0, v3, v0 335; GCN-NEXT: v_lshrrev_b32_e32 v1, v4, v1 336; GCN-NEXT: v_lshrrev_b32_e32 v2, v5, v2 337; GCN-NEXT: s_setpc_b64 s[30:31] 338; 339; GFX10-LABEL: v_lshr_v3i32: 340; GFX10: ; %bb.0: 341; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 342; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 343; GFX10-NEXT: v_lshrrev_b32_e32 v0, v3, v0 344; GFX10-NEXT: v_lshrrev_b32_e32 v1, v4, v1 345; GFX10-NEXT: v_lshrrev_b32_e32 v2, v5, v2 346; GFX10-NEXT: s_setpc_b64 s[30:31] 347 %result = lshr <3 x i32> %value, %amount 348 ret <3 x i32> %result 349} 350 351define amdgpu_ps <3 x i32> @s_lshr_v3i32(<3 x i32> inreg %value, <3 x i32> inreg %amount) { 352; GCN-LABEL: s_lshr_v3i32: 353; GCN: ; %bb.0: 354; GCN-NEXT: s_lshr_b32 s0, s0, s3 355; GCN-NEXT: s_lshr_b32 s1, s1, s4 356; GCN-NEXT: s_lshr_b32 s2, s2, s5 357; GCN-NEXT: ; return to shader part epilog 358; 359; GFX10-LABEL: s_lshr_v3i32: 360; GFX10: ; %bb.0: 361; GFX10-NEXT: s_lshr_b32 s0, s0, s3 362; GFX10-NEXT: s_lshr_b32 s1, s1, s4 363; GFX10-NEXT: s_lshr_b32 s2, s2, s5 364; GFX10-NEXT: ; return to shader part epilog 365 %result = lshr <3 x i32> %value, %amount 366 ret <3 x i32> %result 367} 368 369define <4 x i32> @v_lshr_v4i32(<4 x i32> %value, <4 x i32> %amount) { 370; GCN-LABEL: v_lshr_v4i32: 371; GCN: ; %bb.0: 372; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 373; GCN-NEXT: v_lshrrev_b32_e32 v0, v4, v0 374; GCN-NEXT: v_lshrrev_b32_e32 v1, v5, v1 375; GCN-NEXT: v_lshrrev_b32_e32 v2, v6, v2 376; GCN-NEXT: v_lshrrev_b32_e32 v3, v7, v3 377; GCN-NEXT: s_setpc_b64 s[30:31] 378; 379; GFX10-LABEL: v_lshr_v4i32: 380; GFX10: ; %bb.0: 381; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 382; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 383; GFX10-NEXT: v_lshrrev_b32_e32 v0, v4, v0 384; GFX10-NEXT: v_lshrrev_b32_e32 v1, v5, v1 385; GFX10-NEXT: v_lshrrev_b32_e32 v2, v6, v2 386; GFX10-NEXT: v_lshrrev_b32_e32 v3, v7, v3 387; GFX10-NEXT: s_setpc_b64 s[30:31] 388 %result = lshr <4 x i32> %value, %amount 389 ret <4 x i32> %result 390} 391 392define amdgpu_ps <4 x i32> @s_lshr_v4i32(<4 x i32> inreg %value, <4 x i32> inreg %amount) { 393; GCN-LABEL: s_lshr_v4i32: 394; GCN: ; %bb.0: 395; GCN-NEXT: s_lshr_b32 s0, s0, s4 396; GCN-NEXT: s_lshr_b32 s1, s1, s5 397; GCN-NEXT: s_lshr_b32 s2, s2, s6 398; GCN-NEXT: s_lshr_b32 s3, s3, s7 399; GCN-NEXT: ; return to shader part epilog 400; 401; GFX10-LABEL: s_lshr_v4i32: 402; GFX10: ; %bb.0: 403; GFX10-NEXT: s_lshr_b32 s0, s0, s4 404; GFX10-NEXT: s_lshr_b32 s1, s1, s5 405; GFX10-NEXT: s_lshr_b32 s2, s2, s6 406; GFX10-NEXT: s_lshr_b32 s3, s3, s7 407; GFX10-NEXT: ; return to shader part epilog 408 %result = lshr <4 x i32> %value, %amount 409 ret <4 x i32> %result 410} 411 412define <5 x i32> @v_lshr_v5i32(<5 x i32> %value, <5 x i32> %amount) { 413; GCN-LABEL: v_lshr_v5i32: 414; GCN: ; %bb.0: 415; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 416; GCN-NEXT: v_lshrrev_b32_e32 v0, v5, v0 417; GCN-NEXT: v_lshrrev_b32_e32 v1, v6, v1 418; GCN-NEXT: v_lshrrev_b32_e32 v2, v7, v2 419; GCN-NEXT: v_lshrrev_b32_e32 v3, v8, v3 420; GCN-NEXT: v_lshrrev_b32_e32 v4, v9, v4 421; GCN-NEXT: s_setpc_b64 s[30:31] 422; 423; GFX10-LABEL: v_lshr_v5i32: 424; GFX10: ; %bb.0: 425; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 426; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 427; GFX10-NEXT: v_lshrrev_b32_e32 v0, v5, v0 428; GFX10-NEXT: v_lshrrev_b32_e32 v1, v6, v1 429; GFX10-NEXT: v_lshrrev_b32_e32 v2, v7, v2 430; GFX10-NEXT: v_lshrrev_b32_e32 v3, v8, v3 431; GFX10-NEXT: v_lshrrev_b32_e32 v4, v9, v4 432; GFX10-NEXT: s_setpc_b64 s[30:31] 433 %result = lshr <5 x i32> %value, %amount 434 ret <5 x i32> %result 435} 436 437define amdgpu_ps <5 x i32> @s_lshr_v5i32(<5 x i32> inreg %value, <5 x i32> inreg %amount) { 438; GCN-LABEL: s_lshr_v5i32: 439; GCN: ; %bb.0: 440; GCN-NEXT: s_lshr_b32 s0, s0, s5 441; GCN-NEXT: s_lshr_b32 s1, s1, s6 442; GCN-NEXT: s_lshr_b32 s2, s2, s7 443; GCN-NEXT: s_lshr_b32 s3, s3, s8 444; GCN-NEXT: s_lshr_b32 s4, s4, s9 445; GCN-NEXT: ; return to shader part epilog 446; 447; GFX10-LABEL: s_lshr_v5i32: 448; GFX10: ; %bb.0: 449; GFX10-NEXT: s_lshr_b32 s0, s0, s5 450; GFX10-NEXT: s_lshr_b32 s1, s1, s6 451; GFX10-NEXT: s_lshr_b32 s2, s2, s7 452; GFX10-NEXT: s_lshr_b32 s3, s3, s8 453; GFX10-NEXT: s_lshr_b32 s4, s4, s9 454; GFX10-NEXT: ; return to shader part epilog 455 %result = lshr <5 x i32> %value, %amount 456 ret <5 x i32> %result 457} 458 459define <16 x i32> @v_lshr_v16i32(<16 x i32> %value, <16 x i32> %amount) { 460; GCN-LABEL: v_lshr_v16i32: 461; GCN: ; %bb.0: 462; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 463; GCN-NEXT: v_lshrrev_b32_e32 v0, v16, v0 464; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 465; GCN-NEXT: v_lshrrev_b32_e32 v1, v17, v1 466; GCN-NEXT: v_lshrrev_b32_e32 v2, v18, v2 467; GCN-NEXT: v_lshrrev_b32_e32 v3, v19, v3 468; GCN-NEXT: v_lshrrev_b32_e32 v4, v20, v4 469; GCN-NEXT: v_lshrrev_b32_e32 v5, v21, v5 470; GCN-NEXT: v_lshrrev_b32_e32 v6, v22, v6 471; GCN-NEXT: v_lshrrev_b32_e32 v7, v23, v7 472; GCN-NEXT: v_lshrrev_b32_e32 v8, v24, v8 473; GCN-NEXT: v_lshrrev_b32_e32 v9, v25, v9 474; GCN-NEXT: v_lshrrev_b32_e32 v10, v26, v10 475; GCN-NEXT: v_lshrrev_b32_e32 v11, v27, v11 476; GCN-NEXT: v_lshrrev_b32_e32 v12, v28, v12 477; GCN-NEXT: v_lshrrev_b32_e32 v13, v29, v13 478; GCN-NEXT: v_lshrrev_b32_e32 v14, v30, v14 479; GCN-NEXT: s_waitcnt vmcnt(0) 480; GCN-NEXT: v_lshrrev_b32_e32 v15, v16, v15 481; GCN-NEXT: s_setpc_b64 s[30:31] 482; 483; GFX10-LABEL: v_lshr_v16i32: 484; GFX10: ; %bb.0: 485; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 486; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 487; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32 488; GFX10-NEXT: v_lshrrev_b32_e32 v0, v16, v0 489; GFX10-NEXT: v_lshrrev_b32_e32 v1, v17, v1 490; GFX10-NEXT: v_lshrrev_b32_e32 v2, v18, v2 491; GFX10-NEXT: v_lshrrev_b32_e32 v3, v19, v3 492; GFX10-NEXT: v_lshrrev_b32_e32 v4, v20, v4 493; GFX10-NEXT: v_lshrrev_b32_e32 v5, v21, v5 494; GFX10-NEXT: v_lshrrev_b32_e32 v6, v22, v6 495; GFX10-NEXT: v_lshrrev_b32_e32 v7, v23, v7 496; GFX10-NEXT: v_lshrrev_b32_e32 v8, v24, v8 497; GFX10-NEXT: v_lshrrev_b32_e32 v9, v25, v9 498; GFX10-NEXT: v_lshrrev_b32_e32 v10, v26, v10 499; GFX10-NEXT: v_lshrrev_b32_e32 v11, v27, v11 500; GFX10-NEXT: v_lshrrev_b32_e32 v12, v28, v12 501; GFX10-NEXT: v_lshrrev_b32_e32 v13, v29, v13 502; GFX10-NEXT: v_lshrrev_b32_e32 v14, v30, v14 503; GFX10-NEXT: s_waitcnt vmcnt(0) 504; GFX10-NEXT: v_lshrrev_b32_e32 v15, v31, v15 505; GFX10-NEXT: s_setpc_b64 s[30:31] 506 %result = lshr <16 x i32> %value, %amount 507 ret <16 x i32> %result 508} 509 510define amdgpu_ps <16 x i32> @s_lshr_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) { 511; GCN-LABEL: s_lshr_v16i32: 512; GCN: ; %bb.0: 513; GCN-NEXT: s_lshr_b32 s0, s0, s16 514; GCN-NEXT: s_lshr_b32 s1, s1, s17 515; GCN-NEXT: s_lshr_b32 s2, s2, s18 516; GCN-NEXT: s_lshr_b32 s3, s3, s19 517; GCN-NEXT: s_lshr_b32 s4, s4, s20 518; GCN-NEXT: s_lshr_b32 s5, s5, s21 519; GCN-NEXT: s_lshr_b32 s6, s6, s22 520; GCN-NEXT: s_lshr_b32 s7, s7, s23 521; GCN-NEXT: s_lshr_b32 s8, s8, s24 522; GCN-NEXT: s_lshr_b32 s9, s9, s25 523; GCN-NEXT: s_lshr_b32 s10, s10, s26 524; GCN-NEXT: s_lshr_b32 s11, s11, s27 525; GCN-NEXT: s_lshr_b32 s12, s12, s28 526; GCN-NEXT: s_lshr_b32 s13, s13, s29 527; GCN-NEXT: s_lshr_b32 s14, s14, s30 528; GCN-NEXT: s_lshr_b32 s15, s15, s31 529; GCN-NEXT: ; return to shader part epilog 530; 531; GFX10-LABEL: s_lshr_v16i32: 532; GFX10: ; %bb.0: 533; GFX10-NEXT: s_lshr_b32 s0, s0, s16 534; GFX10-NEXT: s_lshr_b32 s1, s1, s17 535; GFX10-NEXT: s_lshr_b32 s2, s2, s18 536; GFX10-NEXT: s_lshr_b32 s3, s3, s19 537; GFX10-NEXT: s_lshr_b32 s4, s4, s20 538; GFX10-NEXT: s_lshr_b32 s5, s5, s21 539; GFX10-NEXT: s_lshr_b32 s6, s6, s22 540; GFX10-NEXT: s_lshr_b32 s7, s7, s23 541; GFX10-NEXT: s_lshr_b32 s8, s8, s24 542; GFX10-NEXT: s_lshr_b32 s9, s9, s25 543; GFX10-NEXT: s_lshr_b32 s10, s10, s26 544; GFX10-NEXT: s_lshr_b32 s11, s11, s27 545; GFX10-NEXT: s_lshr_b32 s12, s12, s28 546; GFX10-NEXT: s_lshr_b32 s13, s13, s29 547; GFX10-NEXT: s_lshr_b32 s14, s14, s30 548; GFX10-NEXT: s_lshr_b32 s15, s15, s31 549; GFX10-NEXT: ; return to shader part epilog 550 %result = lshr <16 x i32> %value, %amount 551 ret <16 x i32> %result 552} 553 554define i16 @v_lshr_i16(i16 %value, i16 %amount) { 555; GFX6-LABEL: v_lshr_i16: 556; GFX6: ; %bb.0: 557; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 558; GFX6-NEXT: s_mov_b32 s4, 0xffff 559; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 560; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 561; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0 562; GFX6-NEXT: s_setpc_b64 s[30:31] 563; 564; GFX8-LABEL: v_lshr_i16: 565; GFX8: ; %bb.0: 566; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 567; GFX8-NEXT: v_lshrrev_b16_e32 v0, v1, v0 568; GFX8-NEXT: s_setpc_b64 s[30:31] 569; 570; GFX9-LABEL: v_lshr_i16: 571; GFX9: ; %bb.0: 572; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 573; GFX9-NEXT: v_lshrrev_b16_e32 v0, v1, v0 574; GFX9-NEXT: s_setpc_b64 s[30:31] 575; 576; GFX10-LABEL: v_lshr_i16: 577; GFX10: ; %bb.0: 578; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 579; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 580; GFX10-NEXT: v_lshrrev_b16 v0, v1, v0 581; GFX10-NEXT: s_setpc_b64 s[30:31] 582 %result = lshr i16 %value, %amount 583 ret i16 %result 584} 585 586define i16 @v_lshr_i16_31(i16 %value) { 587; GCN-LABEL: v_lshr_i16_31: 588; GCN: ; %bb.0: 589; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 590; GCN-NEXT: s_setpc_b64 s[30:31] 591; 592; GFX10-LABEL: v_lshr_i16_31: 593; GFX10: ; %bb.0: 594; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 595; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 596; GFX10-NEXT: s_setpc_b64 s[30:31] 597 %result = lshr i16 %value, 31 598 ret i16 %result 599} 600 601define amdgpu_ps i16 @s_lshr_i16(i16 inreg %value, i16 inreg %amount) { 602; GCN-LABEL: s_lshr_i16: 603; GCN: ; %bb.0: 604; GCN-NEXT: s_and_b32 s0, s0, 0xffff 605; GCN-NEXT: s_lshr_b32 s0, s0, s1 606; GCN-NEXT: ; return to shader part epilog 607; 608; GFX10-LABEL: s_lshr_i16: 609; GFX10: ; %bb.0: 610; GFX10-NEXT: s_and_b32 s0, s0, 0xffff 611; GFX10-NEXT: s_lshr_b32 s0, s0, s1 612; GFX10-NEXT: ; return to shader part epilog 613 %result = lshr i16 %value, %amount 614 ret i16 %result 615} 616 617define amdgpu_ps i16 @s_lshr_i16_15(i16 inreg %value) { 618; GCN-LABEL: s_lshr_i16_15: 619; GCN: ; %bb.0: 620; GCN-NEXT: s_bfe_u32 s0, s0, 0x1000f 621; GCN-NEXT: ; return to shader part epilog 622; 623; GFX10-LABEL: s_lshr_i16_15: 624; GFX10: ; %bb.0: 625; GFX10-NEXT: s_bfe_u32 s0, s0, 0x1000f 626; GFX10-NEXT: ; return to shader part epilog 627 %result = lshr i16 %value, 15 628 ret i16 %result 629} 630 631define amdgpu_ps half @lshr_i16_sv(i16 inreg %value, i16 %amount) { 632; GFX6-LABEL: lshr_i16_sv: 633; GFX6: ; %bb.0: 634; GFX6-NEXT: s_mov_b32 s1, 0xffff 635; GFX6-NEXT: v_and_b32_e32 v0, s1, v0 636; GFX6-NEXT: s_and_b32 s0, s0, s1 637; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0 638; GFX6-NEXT: ; return to shader part epilog 639; 640; GFX8-LABEL: lshr_i16_sv: 641; GFX8: ; %bb.0: 642; GFX8-NEXT: v_lshrrev_b16_e64 v0, v0, s0 643; GFX8-NEXT: ; return to shader part epilog 644; 645; GFX9-LABEL: lshr_i16_sv: 646; GFX9: ; %bb.0: 647; GFX9-NEXT: v_lshrrev_b16_e64 v0, v0, s0 648; GFX9-NEXT: ; return to shader part epilog 649; 650; GFX10-LABEL: lshr_i16_sv: 651; GFX10: ; %bb.0: 652; GFX10-NEXT: v_lshrrev_b16 v0, v0, s0 653; GFX10-NEXT: ; return to shader part epilog 654 %result = lshr i16 %value, %amount 655 %cast = bitcast i16 %result to half 656 ret half %cast 657} 658 659define amdgpu_ps half @lshr_i16_vs(i16 %value, i16 inreg %amount) { 660; GFX6-LABEL: lshr_i16_vs: 661; GFX6: ; %bb.0: 662; GFX6-NEXT: s_mov_b32 s1, 0xffff 663; GFX6-NEXT: s_and_b32 s0, s0, s1 664; GFX6-NEXT: v_and_b32_e32 v0, s1, v0 665; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0 666; GFX6-NEXT: ; return to shader part epilog 667; 668; GFX8-LABEL: lshr_i16_vs: 669; GFX8: ; %bb.0: 670; GFX8-NEXT: v_lshrrev_b16_e32 v0, s0, v0 671; GFX8-NEXT: ; return to shader part epilog 672; 673; GFX9-LABEL: lshr_i16_vs: 674; GFX9: ; %bb.0: 675; GFX9-NEXT: v_lshrrev_b16_e32 v0, s0, v0 676; GFX9-NEXT: ; return to shader part epilog 677; 678; GFX10-LABEL: lshr_i16_vs: 679; GFX10: ; %bb.0: 680; GFX10-NEXT: v_lshrrev_b16 v0, s0, v0 681; GFX10-NEXT: ; return to shader part epilog 682 %result = lshr i16 %value, %amount 683 %cast = bitcast i16 %result to half 684 ret half %cast 685} 686 687define <2 x i16> @v_lshr_v2i16(<2 x i16> %value, <2 x i16> %amount) { 688; GFX6-LABEL: v_lshr_v2i16: 689; GFX6: ; %bb.0: 690; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 691; GFX6-NEXT: s_mov_b32 s4, 0xffff 692; GFX6-NEXT: v_and_b32_e32 v2, s4, v2 693; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 694; GFX6-NEXT: v_lshrrev_b32_e32 v0, v2, v0 695; GFX6-NEXT: v_and_b32_e32 v2, s4, v3 696; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 697; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1 698; GFX6-NEXT: s_setpc_b64 s[30:31] 699; 700; GFX8-LABEL: v_lshr_v2i16: 701; GFX8: ; %bb.0: 702; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 703; GFX8-NEXT: v_lshrrev_b16_e32 v2, v1, v0 704; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 705; GFX8-NEXT: v_or_b32_e32 v0, v2, v0 706; GFX8-NEXT: s_setpc_b64 s[30:31] 707; 708; GFX9-LABEL: v_lshr_v2i16: 709; GFX9: ; %bb.0: 710; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 711; GFX9-NEXT: v_pk_lshrrev_b16 v0, v1, v0 712; GFX9-NEXT: s_setpc_b64 s[30:31] 713; 714; GFX10-LABEL: v_lshr_v2i16: 715; GFX10: ; %bb.0: 716; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 717; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 718; GFX10-NEXT: v_pk_lshrrev_b16 v0, v1, v0 719; GFX10-NEXT: s_setpc_b64 s[30:31] 720 %result = lshr <2 x i16> %value, %amount 721 ret <2 x i16> %result 722} 723 724define <2 x i16> @v_lshr_v2i16_15(<2 x i16> %value) { 725; GFX6-LABEL: v_lshr_v2i16_15: 726; GFX6: ; %bb.0: 727; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 728; GFX6-NEXT: v_bfe_u32 v0, v0, 15, 1 729; GFX6-NEXT: v_bfe_u32 v1, v1, 15, 1 730; GFX6-NEXT: s_setpc_b64 s[30:31] 731; 732; GFX8-LABEL: v_lshr_v2i16_15: 733; GFX8: ; %bb.0: 734; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 735; GFX8-NEXT: v_mov_b32_e32 v2, 15 736; GFX8-NEXT: v_lshrrev_b16_e32 v1, 15, v0 737; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 738; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 739; GFX8-NEXT: s_setpc_b64 s[30:31] 740; 741; GFX9-LABEL: v_lshr_v2i16_15: 742; GFX9: ; %bb.0: 743; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 744; GFX9-NEXT: v_pk_lshrrev_b16 v0, 15, v0 op_sel_hi:[0,1] 745; GFX9-NEXT: s_setpc_b64 s[30:31] 746; 747; GFX10-LABEL: v_lshr_v2i16_15: 748; GFX10: ; %bb.0: 749; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 750; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 751; GFX10-NEXT: v_pk_lshrrev_b16 v0, 15, v0 op_sel_hi:[0,1] 752; GFX10-NEXT: s_setpc_b64 s[30:31] 753 %result = lshr <2 x i16> %value, <i16 15, i16 15> 754 ret <2 x i16> %result 755} 756 757define amdgpu_ps i32 @s_lshr_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) { 758; GFX6-LABEL: s_lshr_v2i16: 759; GFX6: ; %bb.0: 760; GFX6-NEXT: s_mov_b32 s4, 0xffff 761; GFX6-NEXT: s_and_b32 s1, s1, s4 762; GFX6-NEXT: s_and_b32 s0, s0, s4 763; GFX6-NEXT: s_lshr_b32 s1, s1, s3 764; GFX6-NEXT: s_lshr_b32 s0, s0, s2 765; GFX6-NEXT: s_lshl_b32 s1, s1, 16 766; GFX6-NEXT: s_or_b32 s0, s0, s1 767; GFX6-NEXT: ; return to shader part epilog 768; 769; GFX8-LABEL: s_lshr_v2i16: 770; GFX8: ; %bb.0: 771; GFX8-NEXT: s_mov_b32 s3, 0xffff 772; GFX8-NEXT: s_lshr_b32 s2, s0, 16 773; GFX8-NEXT: s_and_b32 s0, s0, s3 774; GFX8-NEXT: s_lshr_b32 s4, s1, 16 775; GFX8-NEXT: s_lshr_b32 s0, s0, s1 776; GFX8-NEXT: s_lshr_b32 s1, s2, s4 777; GFX8-NEXT: s_lshl_b32 s1, s1, 16 778; GFX8-NEXT: s_and_b32 s0, s0, s3 779; GFX8-NEXT: s_or_b32 s0, s1, s0 780; GFX8-NEXT: ; return to shader part epilog 781; 782; GFX9-LABEL: s_lshr_v2i16: 783; GFX9: ; %bb.0: 784; GFX9-NEXT: s_lshr_b32 s2, s0, 16 785; GFX9-NEXT: s_and_b32 s0, s0, 0xffff 786; GFX9-NEXT: s_lshr_b32 s3, s1, 16 787; GFX9-NEXT: s_lshr_b32 s0, s0, s1 788; GFX9-NEXT: s_lshr_b32 s1, s2, s3 789; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1 790; GFX9-NEXT: ; return to shader part epilog 791; 792; GFX10-LABEL: s_lshr_v2i16: 793; GFX10: ; %bb.0: 794; GFX10-NEXT: s_lshr_b32 s2, s0, 16 795; GFX10-NEXT: s_and_b32 s0, s0, 0xffff 796; GFX10-NEXT: s_lshr_b32 s3, s1, 16 797; GFX10-NEXT: s_lshr_b32 s0, s0, s1 798; GFX10-NEXT: s_lshr_b32 s1, s2, s3 799; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1 800; GFX10-NEXT: ; return to shader part epilog 801 %result = lshr <2 x i16> %value, %amount 802 %cast = bitcast <2 x i16> %result to i32 803 ret i32 %cast 804} 805 806define amdgpu_ps float @lshr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) { 807; GFX6-LABEL: lshr_v2i16_sv: 808; GFX6: ; %bb.0: 809; GFX6-NEXT: s_mov_b32 s2, 0xffff 810; GFX6-NEXT: v_and_b32_e32 v0, s2, v0 811; GFX6-NEXT: s_and_b32 s0, s0, s2 812; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0 813; GFX6-NEXT: v_and_b32_e32 v1, s2, v1 814; GFX6-NEXT: s_and_b32 s0, s1, s2 815; GFX6-NEXT: v_lshr_b32_e32 v1, s0, v1 816; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 817; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 818; GFX6-NEXT: ; return to shader part epilog 819; 820; GFX8-LABEL: lshr_v2i16_sv: 821; GFX8: ; %bb.0: 822; GFX8-NEXT: s_lshr_b32 s1, s0, 16 823; GFX8-NEXT: v_mov_b32_e32 v2, s1 824; GFX8-NEXT: v_lshrrev_b16_e64 v1, v0, s0 825; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 826; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 827; GFX8-NEXT: ; return to shader part epilog 828; 829; GFX9-LABEL: lshr_v2i16_sv: 830; GFX9: ; %bb.0: 831; GFX9-NEXT: v_pk_lshrrev_b16 v0, v0, s0 832; GFX9-NEXT: ; return to shader part epilog 833; 834; GFX10-LABEL: lshr_v2i16_sv: 835; GFX10: ; %bb.0: 836; GFX10-NEXT: v_pk_lshrrev_b16 v0, v0, s0 837; GFX10-NEXT: ; return to shader part epilog 838 %result = lshr <2 x i16> %value, %amount 839 %cast = bitcast <2 x i16> %result to float 840 ret float %cast 841} 842 843define amdgpu_ps float @lshr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) { 844; GFX6-LABEL: lshr_v2i16_vs: 845; GFX6: ; %bb.0: 846; GFX6-NEXT: s_mov_b32 s2, 0xffff 847; GFX6-NEXT: s_and_b32 s0, s0, s2 848; GFX6-NEXT: v_and_b32_e32 v0, s2, v0 849; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0 850; GFX6-NEXT: s_and_b32 s0, s1, s2 851; GFX6-NEXT: v_and_b32_e32 v1, s2, v1 852; GFX6-NEXT: v_lshrrev_b32_e32 v1, s0, v1 853; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 854; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 855; GFX6-NEXT: ; return to shader part epilog 856; 857; GFX8-LABEL: lshr_v2i16_vs: 858; GFX8: ; %bb.0: 859; GFX8-NEXT: s_lshr_b32 s1, s0, 16 860; GFX8-NEXT: v_mov_b32_e32 v2, s1 861; GFX8-NEXT: v_lshrrev_b16_e32 v1, s0, v0 862; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 863; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 864; GFX8-NEXT: ; return to shader part epilog 865; 866; GFX9-LABEL: lshr_v2i16_vs: 867; GFX9: ; %bb.0: 868; GFX9-NEXT: v_pk_lshrrev_b16 v0, s0, v0 869; GFX9-NEXT: ; return to shader part epilog 870; 871; GFX10-LABEL: lshr_v2i16_vs: 872; GFX10: ; %bb.0: 873; GFX10-NEXT: v_pk_lshrrev_b16 v0, s0, v0 874; GFX10-NEXT: ; return to shader part epilog 875 %result = lshr <2 x i16> %value, %amount 876 %cast = bitcast <2 x i16> %result to float 877 ret float %cast 878} 879 880; FIXME 881; define <3 x i16> @v_lshr_v3i16(<3 x i16> %value, <3 x i16> %amount) { 882; %result = lshr <3 x i16> %value, %amount 883; ret <3 x i16> %result 884; } 885 886; define amdgpu_ps <3 x i16> @s_lshr_v3i16(<3 x i16> inreg %value, <3 x i16> inreg %amount) { 887; %result = lshr <3 x i16> %value, %amount 888; ret <3 x i16> %result 889; } 890 891define <2 x float> @v_lshr_v4i16(<4 x i16> %value, <4 x i16> %amount) { 892; GFX6-LABEL: v_lshr_v4i16: 893; GFX6: ; %bb.0: 894; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 895; GFX6-NEXT: s_mov_b32 s4, 0xffff 896; GFX6-NEXT: v_and_b32_e32 v4, s4, v4 897; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 898; GFX6-NEXT: v_lshrrev_b32_e32 v0, v4, v0 899; GFX6-NEXT: v_and_b32_e32 v4, s4, v5 900; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 901; GFX6-NEXT: v_lshrrev_b32_e32 v1, v4, v1 902; GFX6-NEXT: v_and_b32_e32 v4, s4, v6 903; GFX6-NEXT: v_and_b32_e32 v2, s4, v2 904; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2 905; GFX6-NEXT: v_and_b32_e32 v4, s4, v7 906; GFX6-NEXT: v_and_b32_e32 v3, s4, v3 907; GFX6-NEXT: v_lshrrev_b32_e32 v3, v4, v3 908; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 909; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 910; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3 911; GFX6-NEXT: v_or_b32_e32 v1, v2, v1 912; GFX6-NEXT: s_setpc_b64 s[30:31] 913; 914; GFX8-LABEL: v_lshr_v4i16: 915; GFX8: ; %bb.0: 916; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 917; GFX8-NEXT: v_lshrrev_b16_e32 v4, v2, v0 918; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 919; GFX8-NEXT: v_lshrrev_b16_e32 v2, v3, v1 920; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 921; GFX8-NEXT: v_or_b32_e32 v0, v4, v0 922; GFX8-NEXT: v_or_b32_e32 v1, v2, v1 923; GFX8-NEXT: s_setpc_b64 s[30:31] 924; 925; GFX9-LABEL: v_lshr_v4i16: 926; GFX9: ; %bb.0: 927; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 928; GFX9-NEXT: v_pk_lshrrev_b16 v0, v2, v0 929; GFX9-NEXT: v_pk_lshrrev_b16 v1, v3, v1 930; GFX9-NEXT: s_setpc_b64 s[30:31] 931; 932; GFX10-LABEL: v_lshr_v4i16: 933; GFX10: ; %bb.0: 934; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 935; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 936; GFX10-NEXT: v_pk_lshrrev_b16 v0, v2, v0 937; GFX10-NEXT: v_pk_lshrrev_b16 v1, v3, v1 938; GFX10-NEXT: s_setpc_b64 s[30:31] 939 %result = lshr <4 x i16> %value, %amount 940 %cast = bitcast <4 x i16> %result to <2 x float> 941 ret <2 x float> %cast 942} 943 944define amdgpu_ps <2 x i32> @s_lshr_v4i16(<4 x i16> inreg %value, <4 x i16> inreg %amount) { 945; GFX6-LABEL: s_lshr_v4i16: 946; GFX6: ; %bb.0: 947; GFX6-NEXT: s_mov_b32 s8, 0xffff 948; GFX6-NEXT: s_and_b32 s1, s1, s8 949; GFX6-NEXT: s_and_b32 s0, s0, s8 950; GFX6-NEXT: s_lshr_b32 s1, s1, s5 951; GFX6-NEXT: s_and_b32 s3, s3, s8 952; GFX6-NEXT: s_lshr_b32 s0, s0, s4 953; GFX6-NEXT: s_and_b32 s2, s2, s8 954; GFX6-NEXT: s_lshr_b32 s3, s3, s7 955; GFX6-NEXT: s_lshl_b32 s1, s1, 16 956; GFX6-NEXT: s_lshr_b32 s2, s2, s6 957; GFX6-NEXT: s_or_b32 s0, s0, s1 958; GFX6-NEXT: s_lshl_b32 s1, s3, 16 959; GFX6-NEXT: s_or_b32 s1, s2, s1 960; GFX6-NEXT: ; return to shader part epilog 961; 962; GFX8-LABEL: s_lshr_v4i16: 963; GFX8: ; %bb.0: 964; GFX8-NEXT: s_mov_b32 s6, 0xffff 965; GFX8-NEXT: s_lshr_b32 s4, s0, 16 966; GFX8-NEXT: s_and_b32 s0, s0, s6 967; GFX8-NEXT: s_lshr_b32 s7, s2, 16 968; GFX8-NEXT: s_lshr_b32 s5, s1, 16 969; GFX8-NEXT: s_and_b32 s1, s1, s6 970; GFX8-NEXT: s_lshr_b32 s8, s3, 16 971; GFX8-NEXT: s_lshr_b32 s0, s0, s2 972; GFX8-NEXT: s_lshr_b32 s2, s4, s7 973; GFX8-NEXT: s_lshr_b32 s1, s1, s3 974; GFX8-NEXT: s_lshr_b32 s3, s5, s8 975; GFX8-NEXT: s_lshl_b32 s2, s2, 16 976; GFX8-NEXT: s_and_b32 s0, s0, s6 977; GFX8-NEXT: s_or_b32 s0, s2, s0 978; GFX8-NEXT: s_lshl_b32 s2, s3, 16 979; GFX8-NEXT: s_and_b32 s1, s1, s6 980; GFX8-NEXT: s_or_b32 s1, s2, s1 981; GFX8-NEXT: ; return to shader part epilog 982; 983; GFX9-LABEL: s_lshr_v4i16: 984; GFX9: ; %bb.0: 985; GFX9-NEXT: s_mov_b32 s5, 0xffff 986; GFX9-NEXT: s_lshr_b32 s4, s0, 16 987; GFX9-NEXT: s_and_b32 s0, s0, s5 988; GFX9-NEXT: s_lshr_b32 s6, s2, 16 989; GFX9-NEXT: s_lshr_b32 s0, s0, s2 990; GFX9-NEXT: s_lshr_b32 s2, s4, s6 991; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2 992; GFX9-NEXT: s_lshr_b32 s2, s1, 16 993; GFX9-NEXT: s_and_b32 s1, s1, s5 994; GFX9-NEXT: s_lshr_b32 s4, s3, 16 995; GFX9-NEXT: s_lshr_b32 s1, s1, s3 996; GFX9-NEXT: s_lshr_b32 s2, s2, s4 997; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2 998; GFX9-NEXT: ; return to shader part epilog 999; 1000; GFX10-LABEL: s_lshr_v4i16: 1001; GFX10: ; %bb.0: 1002; GFX10-NEXT: s_mov_b32 s4, 0xffff 1003; GFX10-NEXT: s_lshr_b32 s5, s0, 16 1004; GFX10-NEXT: s_and_b32 s0, s0, s4 1005; GFX10-NEXT: s_lshr_b32 s6, s2, 16 1006; GFX10-NEXT: s_lshr_b32 s0, s0, s2 1007; GFX10-NEXT: s_lshr_b32 s2, s5, s6 1008; GFX10-NEXT: s_lshr_b32 s5, s1, 16 1009; GFX10-NEXT: s_and_b32 s1, s1, s4 1010; GFX10-NEXT: s_lshr_b32 s4, s3, 16 1011; GFX10-NEXT: s_lshr_b32 s1, s1, s3 1012; GFX10-NEXT: s_lshr_b32 s3, s5, s4 1013; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2 1014; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3 1015; GFX10-NEXT: ; return to shader part epilog 1016 %result = lshr <4 x i16> %value, %amount 1017 %cast = bitcast <4 x i16> %result to <2 x i32> 1018 ret <2 x i32> %cast 1019} 1020 1021; FIXME 1022; define <5 x i16> @v_lshr_v5i16(<5 x i16> %value, <5 x i16> %amount) { 1023; %result = lshr <5 x i16> %value, %amount 1024; ret <5 x i16> %result 1025; } 1026 1027; define amdgpu_ps <5 x i16> @s_lshr_v5i16(<5 x i16> inreg %value, <5 x i16> inreg %amount) { 1028; %result = lshr <5 x i16> %value, %amount 1029; ret <5 x i16> %result 1030; } 1031 1032; define <3 x float> @v_lshr_v6i16(<6 x i16> %value, <6 x i16> %amount) { 1033; %result = lshr <6 x i16> %value, %amount 1034; %cast = bitcast <6 x i16> %result to <3 x float> 1035; ret <3 x float> %cast 1036; } 1037 1038; define amdgpu_ps <3 x i32> @s_lshr_v6i16(<6 x i16> inreg %value, <6 x i16> inreg %amount) { 1039; %result = lshr <6 x i16> %value, %amount 1040; %cast = bitcast <6 x i16> %result to <3 x i32> 1041; ret <3 x i32> %cast 1042; } 1043 1044define <4 x float> @v_lshr_v8i16(<8 x i16> %value, <8 x i16> %amount) { 1045; GFX6-LABEL: v_lshr_v8i16: 1046; GFX6: ; %bb.0: 1047; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1048; GFX6-NEXT: s_mov_b32 s4, 0xffff 1049; GFX6-NEXT: v_and_b32_e32 v8, s4, v8 1050; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 1051; GFX6-NEXT: v_lshrrev_b32_e32 v0, v8, v0 1052; GFX6-NEXT: v_and_b32_e32 v8, s4, v9 1053; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 1054; GFX6-NEXT: v_lshrrev_b32_e32 v1, v8, v1 1055; GFX6-NEXT: v_and_b32_e32 v8, s4, v10 1056; GFX6-NEXT: v_and_b32_e32 v2, s4, v2 1057; GFX6-NEXT: v_lshrrev_b32_e32 v2, v8, v2 1058; GFX6-NEXT: v_and_b32_e32 v8, s4, v11 1059; GFX6-NEXT: v_and_b32_e32 v3, s4, v3 1060; GFX6-NEXT: v_lshrrev_b32_e32 v3, v8, v3 1061; GFX6-NEXT: v_and_b32_e32 v8, s4, v12 1062; GFX6-NEXT: v_and_b32_e32 v4, s4, v4 1063; GFX6-NEXT: v_lshrrev_b32_e32 v4, v8, v4 1064; GFX6-NEXT: v_and_b32_e32 v8, s4, v13 1065; GFX6-NEXT: v_and_b32_e32 v5, s4, v5 1066; GFX6-NEXT: v_mov_b32_e32 v16, 0xffff 1067; GFX6-NEXT: v_lshrrev_b32_e32 v5, v8, v5 1068; GFX6-NEXT: v_and_b32_e32 v8, s4, v14 1069; GFX6-NEXT: v_and_b32_e32 v6, s4, v6 1070; GFX6-NEXT: v_lshrrev_b32_e32 v6, v8, v6 1071; GFX6-NEXT: v_and_b32_e32 v8, v15, v16 1072; GFX6-NEXT: v_and_b32_e32 v7, v7, v16 1073; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1074; GFX6-NEXT: v_lshrrev_b32_e32 v7, v8, v7 1075; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 1076; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3 1077; GFX6-NEXT: v_or_b32_e32 v1, v2, v1 1078; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v5 1079; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v7 1080; GFX6-NEXT: v_or_b32_e32 v2, v4, v2 1081; GFX6-NEXT: v_or_b32_e32 v3, v6, v3 1082; GFX6-NEXT: s_setpc_b64 s[30:31] 1083; 1084; GFX8-LABEL: v_lshr_v8i16: 1085; GFX8: ; %bb.0: 1086; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1087; GFX8-NEXT: v_lshrrev_b16_e32 v8, v4, v0 1088; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1089; GFX8-NEXT: v_lshrrev_b16_e32 v4, v5, v1 1090; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1091; GFX8-NEXT: v_or_b32_e32 v1, v4, v1 1092; GFX8-NEXT: v_lshrrev_b16_e32 v4, v6, v2 1093; GFX8-NEXT: v_lshrrev_b16_sdwa v2, v6, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1094; GFX8-NEXT: v_or_b32_e32 v2, v4, v2 1095; GFX8-NEXT: v_lshrrev_b16_e32 v4, v7, v3 1096; GFX8-NEXT: v_lshrrev_b16_sdwa v3, v7, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1097; GFX8-NEXT: v_or_b32_e32 v0, v8, v0 1098; GFX8-NEXT: v_or_b32_e32 v3, v4, v3 1099; GFX8-NEXT: s_setpc_b64 s[30:31] 1100; 1101; GFX9-LABEL: v_lshr_v8i16: 1102; GFX9: ; %bb.0: 1103; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1104; GFX9-NEXT: v_pk_lshrrev_b16 v0, v4, v0 1105; GFX9-NEXT: v_pk_lshrrev_b16 v1, v5, v1 1106; GFX9-NEXT: v_pk_lshrrev_b16 v2, v6, v2 1107; GFX9-NEXT: v_pk_lshrrev_b16 v3, v7, v3 1108; GFX9-NEXT: s_setpc_b64 s[30:31] 1109; 1110; GFX10-LABEL: v_lshr_v8i16: 1111; GFX10: ; %bb.0: 1112; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1113; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1114; GFX10-NEXT: v_pk_lshrrev_b16 v0, v4, v0 1115; GFX10-NEXT: v_pk_lshrrev_b16 v1, v5, v1 1116; GFX10-NEXT: v_pk_lshrrev_b16 v2, v6, v2 1117; GFX10-NEXT: v_pk_lshrrev_b16 v3, v7, v3 1118; GFX10-NEXT: s_setpc_b64 s[30:31] 1119 %result = lshr <8 x i16> %value, %amount 1120 %cast = bitcast <8 x i16> %result to <4 x float> 1121 ret <4 x float> %cast 1122} 1123 1124define amdgpu_ps <4 x i32> @s_lshr_v8i16(<8 x i16> inreg %value, <8 x i16> inreg %amount) { 1125; GFX6-LABEL: s_lshr_v8i16: 1126; GFX6: ; %bb.0: 1127; GFX6-NEXT: s_mov_b32 s16, 0xffff 1128; GFX6-NEXT: s_and_b32 s1, s1, s16 1129; GFX6-NEXT: s_and_b32 s0, s0, s16 1130; GFX6-NEXT: s_lshr_b32 s1, s1, s9 1131; GFX6-NEXT: s_and_b32 s3, s3, s16 1132; GFX6-NEXT: s_lshr_b32 s0, s0, s8 1133; GFX6-NEXT: s_and_b32 s2, s2, s16 1134; GFX6-NEXT: s_lshr_b32 s3, s3, s11 1135; GFX6-NEXT: s_and_b32 s5, s5, s16 1136; GFX6-NEXT: s_and_b32 s7, s7, s16 1137; GFX6-NEXT: s_lshl_b32 s1, s1, 16 1138; GFX6-NEXT: s_lshr_b32 s2, s2, s10 1139; GFX6-NEXT: s_and_b32 s4, s4, s16 1140; GFX6-NEXT: s_lshr_b32 s5, s5, s13 1141; GFX6-NEXT: s_and_b32 s6, s6, s16 1142; GFX6-NEXT: s_lshr_b32 s7, s7, s15 1143; GFX6-NEXT: s_or_b32 s0, s0, s1 1144; GFX6-NEXT: s_lshl_b32 s1, s3, 16 1145; GFX6-NEXT: s_lshr_b32 s4, s4, s12 1146; GFX6-NEXT: s_lshr_b32 s6, s6, s14 1147; GFX6-NEXT: s_or_b32 s1, s2, s1 1148; GFX6-NEXT: s_lshl_b32 s2, s5, 16 1149; GFX6-NEXT: s_lshl_b32 s3, s7, 16 1150; GFX6-NEXT: s_or_b32 s2, s4, s2 1151; GFX6-NEXT: s_or_b32 s3, s6, s3 1152; GFX6-NEXT: ; return to shader part epilog 1153; 1154; GFX8-LABEL: s_lshr_v8i16: 1155; GFX8: ; %bb.0: 1156; GFX8-NEXT: s_mov_b32 s12, 0xffff 1157; GFX8-NEXT: s_lshr_b32 s8, s0, 16 1158; GFX8-NEXT: s_and_b32 s0, s0, s12 1159; GFX8-NEXT: s_lshr_b32 s13, s4, 16 1160; GFX8-NEXT: s_lshr_b32 s9, s1, 16 1161; GFX8-NEXT: s_and_b32 s1, s1, s12 1162; GFX8-NEXT: s_lshr_b32 s14, s5, 16 1163; GFX8-NEXT: s_lshr_b32 s0, s0, s4 1164; GFX8-NEXT: s_lshr_b32 s4, s8, s13 1165; GFX8-NEXT: s_lshr_b32 s10, s2, 16 1166; GFX8-NEXT: s_and_b32 s2, s2, s12 1167; GFX8-NEXT: s_lshr_b32 s15, s6, 16 1168; GFX8-NEXT: s_lshr_b32 s1, s1, s5 1169; GFX8-NEXT: s_lshr_b32 s5, s9, s14 1170; GFX8-NEXT: s_lshl_b32 s4, s4, 16 1171; GFX8-NEXT: s_and_b32 s0, s0, s12 1172; GFX8-NEXT: s_lshr_b32 s11, s3, 16 1173; GFX8-NEXT: s_and_b32 s3, s3, s12 1174; GFX8-NEXT: s_lshr_b32 s16, s7, 16 1175; GFX8-NEXT: s_lshr_b32 s2, s2, s6 1176; GFX8-NEXT: s_lshr_b32 s6, s10, s15 1177; GFX8-NEXT: s_or_b32 s0, s4, s0 1178; GFX8-NEXT: s_lshl_b32 s4, s5, 16 1179; GFX8-NEXT: s_and_b32 s1, s1, s12 1180; GFX8-NEXT: s_lshr_b32 s3, s3, s7 1181; GFX8-NEXT: s_lshr_b32 s7, s11, s16 1182; GFX8-NEXT: s_or_b32 s1, s4, s1 1183; GFX8-NEXT: s_lshl_b32 s4, s6, 16 1184; GFX8-NEXT: s_and_b32 s2, s2, s12 1185; GFX8-NEXT: s_or_b32 s2, s4, s2 1186; GFX8-NEXT: s_lshl_b32 s4, s7, 16 1187; GFX8-NEXT: s_and_b32 s3, s3, s12 1188; GFX8-NEXT: s_or_b32 s3, s4, s3 1189; GFX8-NEXT: ; return to shader part epilog 1190; 1191; GFX9-LABEL: s_lshr_v8i16: 1192; GFX9: ; %bb.0: 1193; GFX9-NEXT: s_mov_b32 s9, 0xffff 1194; GFX9-NEXT: s_lshr_b32 s8, s0, 16 1195; GFX9-NEXT: s_and_b32 s0, s0, s9 1196; GFX9-NEXT: s_lshr_b32 s10, s4, 16 1197; GFX9-NEXT: s_lshr_b32 s0, s0, s4 1198; GFX9-NEXT: s_lshr_b32 s4, s8, s10 1199; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s4 1200; GFX9-NEXT: s_lshr_b32 s4, s1, 16 1201; GFX9-NEXT: s_and_b32 s1, s1, s9 1202; GFX9-NEXT: s_lshr_b32 s8, s5, 16 1203; GFX9-NEXT: s_lshr_b32 s1, s1, s5 1204; GFX9-NEXT: s_lshr_b32 s4, s4, s8 1205; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4 1206; GFX9-NEXT: s_lshr_b32 s4, s2, 16 1207; GFX9-NEXT: s_and_b32 s2, s2, s9 1208; GFX9-NEXT: s_lshr_b32 s5, s6, 16 1209; GFX9-NEXT: s_lshr_b32 s2, s2, s6 1210; GFX9-NEXT: s_lshr_b32 s4, s4, s5 1211; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4 1212; GFX9-NEXT: s_lshr_b32 s4, s3, 16 1213; GFX9-NEXT: s_and_b32 s3, s3, s9 1214; GFX9-NEXT: s_lshr_b32 s5, s7, 16 1215; GFX9-NEXT: s_lshr_b32 s3, s3, s7 1216; GFX9-NEXT: s_lshr_b32 s4, s4, s5 1217; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4 1218; GFX9-NEXT: ; return to shader part epilog 1219; 1220; GFX10-LABEL: s_lshr_v8i16: 1221; GFX10: ; %bb.0: 1222; GFX10-NEXT: s_mov_b32 s8, 0xffff 1223; GFX10-NEXT: s_lshr_b32 s9, s0, 16 1224; GFX10-NEXT: s_and_b32 s0, s0, s8 1225; GFX10-NEXT: s_lshr_b32 s10, s4, 16 1226; GFX10-NEXT: s_lshr_b32 s0, s0, s4 1227; GFX10-NEXT: s_lshr_b32 s4, s9, s10 1228; GFX10-NEXT: s_lshr_b32 s9, s1, 16 1229; GFX10-NEXT: s_and_b32 s1, s1, s8 1230; GFX10-NEXT: s_lshr_b32 s10, s5, 16 1231; GFX10-NEXT: s_lshr_b32 s1, s1, s5 1232; GFX10-NEXT: s_lshr_b32 s5, s9, s10 1233; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s4 1234; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s5 1235; GFX10-NEXT: s_lshr_b32 s4, s2, 16 1236; GFX10-NEXT: s_and_b32 s2, s2, s8 1237; GFX10-NEXT: s_lshr_b32 s5, s6, 16 1238; GFX10-NEXT: s_lshr_b32 s2, s2, s6 1239; GFX10-NEXT: s_lshr_b32 s4, s4, s5 1240; GFX10-NEXT: s_lshr_b32 s5, s3, 16 1241; GFX10-NEXT: s_and_b32 s3, s3, s8 1242; GFX10-NEXT: s_lshr_b32 s6, s7, 16 1243; GFX10-NEXT: s_lshr_b32 s3, s3, s7 1244; GFX10-NEXT: s_lshr_b32 s5, s5, s6 1245; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s4 1246; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s5 1247; GFX10-NEXT: ; return to shader part epilog 1248 %result = lshr <8 x i16> %value, %amount 1249 %cast = bitcast <8 x i16> %result to <4 x i32> 1250 ret <4 x i32> %cast 1251} 1252 1253define i64 @v_lshr_i64(i64 %value, i64 %amount) { 1254; GFX6-LABEL: v_lshr_i64: 1255; GFX6: ; %bb.0: 1256; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1257; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], v2 1258; GFX6-NEXT: s_setpc_b64 s[30:31] 1259; 1260; GFX8-LABEL: v_lshr_i64: 1261; GFX8: ; %bb.0: 1262; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1263; GFX8-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 1264; GFX8-NEXT: s_setpc_b64 s[30:31] 1265; 1266; GFX9-LABEL: v_lshr_i64: 1267; GFX9: ; %bb.0: 1268; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1269; GFX9-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 1270; GFX9-NEXT: s_setpc_b64 s[30:31] 1271; 1272; GFX10-LABEL: v_lshr_i64: 1273; GFX10: ; %bb.0: 1274; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1275; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1276; GFX10-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 1277; GFX10-NEXT: s_setpc_b64 s[30:31] 1278 %result = lshr i64 %value, %amount 1279 ret i64 %result 1280} 1281 1282define i64 @v_lshr_i64_63(i64 %value) { 1283; GCN-LABEL: v_lshr_i64_63: 1284; GCN: ; %bb.0: 1285; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1286; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v1 1287; GCN-NEXT: v_mov_b32_e32 v1, 0 1288; GCN-NEXT: s_setpc_b64 s[30:31] 1289; 1290; GFX10-LABEL: v_lshr_i64_63: 1291; GFX10: ; %bb.0: 1292; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1293; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1294; GFX10-NEXT: v_lshrrev_b32_e32 v0, 31, v1 1295; GFX10-NEXT: v_mov_b32_e32 v1, 0 1296; GFX10-NEXT: s_setpc_b64 s[30:31] 1297 %result = lshr i64 %value, 63 1298 ret i64 %result 1299} 1300 1301define i64 @v_lshr_i64_33(i64 %value) { 1302; GCN-LABEL: v_lshr_i64_33: 1303; GCN: ; %bb.0: 1304; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1305; GCN-NEXT: v_lshrrev_b32_e32 v0, 1, v1 1306; GCN-NEXT: v_mov_b32_e32 v1, 0 1307; GCN-NEXT: s_setpc_b64 s[30:31] 1308; 1309; GFX10-LABEL: v_lshr_i64_33: 1310; GFX10: ; %bb.0: 1311; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1312; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1313; GFX10-NEXT: v_lshrrev_b32_e32 v0, 1, v1 1314; GFX10-NEXT: v_mov_b32_e32 v1, 0 1315; GFX10-NEXT: s_setpc_b64 s[30:31] 1316 %result = lshr i64 %value, 33 1317 ret i64 %result 1318} 1319 1320define i64 @v_lshr_i64_32(i64 %value) { 1321; GCN-LABEL: v_lshr_i64_32: 1322; GCN: ; %bb.0: 1323; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1324; GCN-NEXT: v_mov_b32_e32 v0, v1 1325; GCN-NEXT: v_mov_b32_e32 v1, 0 1326; GCN-NEXT: s_setpc_b64 s[30:31] 1327; 1328; GFX10-LABEL: v_lshr_i64_32: 1329; GFX10: ; %bb.0: 1330; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1331; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1332; GFX10-NEXT: v_mov_b32_e32 v0, v1 1333; GFX10-NEXT: v_mov_b32_e32 v1, 0 1334; GFX10-NEXT: s_setpc_b64 s[30:31] 1335 %result = lshr i64 %value, 32 1336 ret i64 %result 1337} 1338 1339define i64 @v_lshr_i64_31(i64 %value) { 1340; GFX6-LABEL: v_lshr_i64_31: 1341; GFX6: ; %bb.0: 1342; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1343; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 31 1344; GFX6-NEXT: s_setpc_b64 s[30:31] 1345; 1346; GFX8-LABEL: v_lshr_i64_31: 1347; GFX8: ; %bb.0: 1348; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1349; GFX8-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1350; GFX8-NEXT: s_setpc_b64 s[30:31] 1351; 1352; GFX9-LABEL: v_lshr_i64_31: 1353; GFX9: ; %bb.0: 1354; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1355; GFX9-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1356; GFX9-NEXT: s_setpc_b64 s[30:31] 1357; 1358; GFX10-LABEL: v_lshr_i64_31: 1359; GFX10: ; %bb.0: 1360; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1361; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1362; GFX10-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1363; GFX10-NEXT: s_setpc_b64 s[30:31] 1364 %result = lshr i64 %value, 31 1365 ret i64 %result 1366} 1367 1368define amdgpu_ps i64 @s_lshr_i64(i64 inreg %value, i64 inreg %amount) { 1369; GCN-LABEL: s_lshr_i64: 1370; GCN: ; %bb.0: 1371; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], s2 1372; GCN-NEXT: ; return to shader part epilog 1373; 1374; GFX10-LABEL: s_lshr_i64: 1375; GFX10: ; %bb.0: 1376; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], s2 1377; GFX10-NEXT: ; return to shader part epilog 1378 %result = lshr i64 %value, %amount 1379 ret i64 %result 1380} 1381 1382define amdgpu_ps i64 @s_lshr_i64_63(i64 inreg %value) { 1383; GCN-LABEL: s_lshr_i64_63: 1384; GCN: ; %bb.0: 1385; GCN-NEXT: s_lshr_b32 s0, s1, 31 1386; GCN-NEXT: s_mov_b32 s1, 0 1387; GCN-NEXT: ; return to shader part epilog 1388; 1389; GFX10-LABEL: s_lshr_i64_63: 1390; GFX10: ; %bb.0: 1391; GFX10-NEXT: s_lshr_b32 s0, s1, 31 1392; GFX10-NEXT: s_mov_b32 s1, 0 1393; GFX10-NEXT: ; return to shader part epilog 1394 %result = lshr i64 %value, 63 1395 ret i64 %result 1396} 1397 1398define amdgpu_ps i64 @s_lshr_i64_33(i64 inreg %value) { 1399; GCN-LABEL: s_lshr_i64_33: 1400; GCN: ; %bb.0: 1401; GCN-NEXT: s_lshr_b32 s0, s1, 1 1402; GCN-NEXT: s_mov_b32 s1, 0 1403; GCN-NEXT: ; return to shader part epilog 1404; 1405; GFX10-LABEL: s_lshr_i64_33: 1406; GFX10: ; %bb.0: 1407; GFX10-NEXT: s_lshr_b32 s0, s1, 1 1408; GFX10-NEXT: s_mov_b32 s1, 0 1409; GFX10-NEXT: ; return to shader part epilog 1410 %result = lshr i64 %value, 33 1411 ret i64 %result 1412} 1413 1414define amdgpu_ps i64 @s_lshr_i64_32(i64 inreg %value) { 1415; GCN-LABEL: s_lshr_i64_32: 1416; GCN: ; %bb.0: 1417; GCN-NEXT: s_mov_b32 s0, s1 1418; GCN-NEXT: s_mov_b32 s1, 0 1419; GCN-NEXT: ; return to shader part epilog 1420; 1421; GFX10-LABEL: s_lshr_i64_32: 1422; GFX10: ; %bb.0: 1423; GFX10-NEXT: s_mov_b32 s0, s1 1424; GFX10-NEXT: s_mov_b32 s1, 0 1425; GFX10-NEXT: ; return to shader part epilog 1426 %result = lshr i64 %value, 32 1427 ret i64 %result 1428} 1429 1430define amdgpu_ps i64 @s_lshr_i64_31(i64 inreg %value) { 1431; GCN-LABEL: s_lshr_i64_31: 1432; GCN: ; %bb.0: 1433; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], 31 1434; GCN-NEXT: ; return to shader part epilog 1435; 1436; GFX10-LABEL: s_lshr_i64_31: 1437; GFX10: ; %bb.0: 1438; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], 31 1439; GFX10-NEXT: ; return to shader part epilog 1440 %result = lshr i64 %value, 31 1441 ret i64 %result 1442} 1443 1444define amdgpu_ps <2 x float> @lshr_i64_sv(i64 inreg %value, i64 %amount) { 1445; GFX6-LABEL: lshr_i64_sv: 1446; GFX6: ; %bb.0: 1447; GFX6-NEXT: v_lshr_b64 v[0:1], s[0:1], v0 1448; GFX6-NEXT: ; return to shader part epilog 1449; 1450; GFX8-LABEL: lshr_i64_sv: 1451; GFX8: ; %bb.0: 1452; GFX8-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1] 1453; GFX8-NEXT: ; return to shader part epilog 1454; 1455; GFX9-LABEL: lshr_i64_sv: 1456; GFX9: ; %bb.0: 1457; GFX9-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1] 1458; GFX9-NEXT: ; return to shader part epilog 1459; 1460; GFX10-LABEL: lshr_i64_sv: 1461; GFX10: ; %bb.0: 1462; GFX10-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1] 1463; GFX10-NEXT: ; return to shader part epilog 1464 %result = lshr i64 %value, %amount 1465 %cast = bitcast i64 %result to <2 x float> 1466 ret <2 x float> %cast 1467} 1468 1469define amdgpu_ps <2 x float> @lshr_i64_vs(i64 %value, i64 inreg %amount) { 1470; GFX6-LABEL: lshr_i64_vs: 1471; GFX6: ; %bb.0: 1472; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], s0 1473; GFX6-NEXT: ; return to shader part epilog 1474; 1475; GFX8-LABEL: lshr_i64_vs: 1476; GFX8: ; %bb.0: 1477; GFX8-NEXT: v_lshrrev_b64 v[0:1], s0, v[0:1] 1478; GFX8-NEXT: ; return to shader part epilog 1479; 1480; GFX9-LABEL: lshr_i64_vs: 1481; GFX9: ; %bb.0: 1482; GFX9-NEXT: v_lshrrev_b64 v[0:1], s0, v[0:1] 1483; GFX9-NEXT: ; return to shader part epilog 1484; 1485; GFX10-LABEL: lshr_i64_vs: 1486; GFX10: ; %bb.0: 1487; GFX10-NEXT: v_lshrrev_b64 v[0:1], s0, v[0:1] 1488; GFX10-NEXT: ; return to shader part epilog 1489 %result = lshr i64 %value, %amount 1490 %cast = bitcast i64 %result to <2 x float> 1491 ret <2 x float> %cast 1492} 1493 1494define <2 x i64> @v_lshr_v2i64(<2 x i64> %value, <2 x i64> %amount) { 1495; GFX6-LABEL: v_lshr_v2i64: 1496; GFX6: ; %bb.0: 1497; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1498; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], v4 1499; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], v6 1500; GFX6-NEXT: s_setpc_b64 s[30:31] 1501; 1502; GFX8-LABEL: v_lshr_v2i64: 1503; GFX8: ; %bb.0: 1504; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1505; GFX8-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1] 1506; GFX8-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3] 1507; GFX8-NEXT: s_setpc_b64 s[30:31] 1508; 1509; GFX9-LABEL: v_lshr_v2i64: 1510; GFX9: ; %bb.0: 1511; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1512; GFX9-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1] 1513; GFX9-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3] 1514; GFX9-NEXT: s_setpc_b64 s[30:31] 1515; 1516; GFX10-LABEL: v_lshr_v2i64: 1517; GFX10: ; %bb.0: 1518; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1519; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1520; GFX10-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1] 1521; GFX10-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3] 1522; GFX10-NEXT: s_setpc_b64 s[30:31] 1523 %result = lshr <2 x i64> %value, %amount 1524 ret <2 x i64> %result 1525} 1526 1527define <2 x i64> @v_lshr_v2i64_31(<2 x i64> %value) { 1528; GFX6-LABEL: v_lshr_v2i64_31: 1529; GFX6: ; %bb.0: 1530; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1531; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 31 1532; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], 31 1533; GFX6-NEXT: s_setpc_b64 s[30:31] 1534; 1535; GFX8-LABEL: v_lshr_v2i64_31: 1536; GFX8: ; %bb.0: 1537; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1538; GFX8-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1539; GFX8-NEXT: v_lshrrev_b64 v[2:3], 31, v[2:3] 1540; GFX8-NEXT: s_setpc_b64 s[30:31] 1541; 1542; GFX9-LABEL: v_lshr_v2i64_31: 1543; GFX9: ; %bb.0: 1544; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1545; GFX9-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1546; GFX9-NEXT: v_lshrrev_b64 v[2:3], 31, v[2:3] 1547; GFX9-NEXT: s_setpc_b64 s[30:31] 1548; 1549; GFX10-LABEL: v_lshr_v2i64_31: 1550; GFX10: ; %bb.0: 1551; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1552; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1553; GFX10-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1554; GFX10-NEXT: v_lshrrev_b64 v[2:3], 31, v[2:3] 1555; GFX10-NEXT: s_setpc_b64 s[30:31] 1556 %result = lshr <2 x i64> %value, <i64 31, i64 31> 1557 ret <2 x i64> %result 1558} 1559 1560define amdgpu_ps <2 x i64> @s_lshr_v2i64(<2 x i64> inreg %value, <2 x i64> inreg %amount) { 1561; GCN-LABEL: s_lshr_v2i64: 1562; GCN: ; %bb.0: 1563; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], s4 1564; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], s6 1565; GCN-NEXT: ; return to shader part epilog 1566; 1567; GFX10-LABEL: s_lshr_v2i64: 1568; GFX10: ; %bb.0: 1569; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], s4 1570; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s6 1571; GFX10-NEXT: ; return to shader part epilog 1572 %result = lshr <2 x i64> %value, %amount 1573 ret <2 x i64> %result 1574} 1575 1576define i65 @v_lshr_i65(i65 %value, i65 %amount) { 1577; GFX6-LABEL: v_lshr_i65: 1578; GFX6: ; %bb.0: 1579; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1580; GFX6-NEXT: v_and_b32_e32 v4, 1, v2 1581; GFX6-NEXT: v_mov_b32_e32 v5, 0 1582; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 64, v3 1583; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 64, v3 1584; GFX6-NEXT: v_lshr_b64 v[6:7], v[0:1], v3 1585; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], v8 1586; GFX6-NEXT: v_lshr_b64 v[10:11], v[4:5], v3 1587; GFX6-NEXT: v_lshr_b64 v[4:5], v[4:5], v2 1588; GFX6-NEXT: v_or_b32_e32 v6, v6, v8 1589; GFX6-NEXT: v_or_b32_e32 v7, v7, v9 1590; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3 1591; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc 1592; GFX6-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc 1593; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3 1594; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5] 1595; GFX6-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5] 1596; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc 1597; GFX6-NEXT: s_setpc_b64 s[30:31] 1598; 1599; GFX8-LABEL: v_lshr_i65: 1600; GFX8: ; %bb.0: 1601; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1602; GFX8-NEXT: v_and_b32_e32 v4, 1, v2 1603; GFX8-NEXT: v_mov_b32_e32 v5, 0 1604; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 64, v3 1605; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 64, v3 1606; GFX8-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1] 1607; GFX8-NEXT: v_lshlrev_b64 v[8:9], v8, v[4:5] 1608; GFX8-NEXT: v_lshrrev_b64 v[10:11], v3, v[4:5] 1609; GFX8-NEXT: v_lshrrev_b64 v[4:5], v2, v[4:5] 1610; GFX8-NEXT: v_or_b32_e32 v6, v6, v8 1611; GFX8-NEXT: v_or_b32_e32 v7, v7, v9 1612; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3 1613; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc 1614; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc 1615; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3 1616; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5] 1617; GFX8-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5] 1618; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc 1619; GFX8-NEXT: s_setpc_b64 s[30:31] 1620; 1621; GFX9-LABEL: v_lshr_i65: 1622; GFX9: ; %bb.0: 1623; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1624; GFX9-NEXT: v_and_b32_e32 v4, 1, v2 1625; GFX9-NEXT: v_mov_b32_e32 v5, 0 1626; GFX9-NEXT: v_sub_u32_e32 v8, 64, v3 1627; GFX9-NEXT: v_subrev_u32_e32 v2, 64, v3 1628; GFX9-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1] 1629; GFX9-NEXT: v_lshlrev_b64 v[8:9], v8, v[4:5] 1630; GFX9-NEXT: v_lshrrev_b64 v[10:11], v3, v[4:5] 1631; GFX9-NEXT: v_lshrrev_b64 v[4:5], v2, v[4:5] 1632; GFX9-NEXT: v_or_b32_e32 v6, v6, v8 1633; GFX9-NEXT: v_or_b32_e32 v7, v7, v9 1634; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3 1635; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc 1636; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc 1637; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3 1638; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5] 1639; GFX9-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5] 1640; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc 1641; GFX9-NEXT: s_setpc_b64 s[30:31] 1642; 1643; GFX10-LABEL: v_lshr_i65: 1644; GFX10: ; %bb.0: 1645; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1646; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1647; GFX10-NEXT: v_and_b32_e32 v4, 1, v2 1648; GFX10-NEXT: v_mov_b32_e32 v5, 0 1649; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v3 1650; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 64, v3 1651; GFX10-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1] 1652; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v3 1653; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v3 1654; GFX10-NEXT: v_lshlrev_b64 v[8:9], v2, v[4:5] 1655; GFX10-NEXT: v_lshrrev_b64 v[10:11], v10, v[4:5] 1656; GFX10-NEXT: v_lshrrev_b64 v[4:5], v3, v[4:5] 1657; GFX10-NEXT: v_or_b32_e32 v2, v6, v8 1658; GFX10-NEXT: v_or_b32_e32 v6, v7, v9 1659; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo 1660; GFX10-NEXT: v_cndmask_b32_e32 v5, v11, v6, vcc_lo 1661; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v0, s4 1662; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s4 1663; GFX10-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc_lo 1664; GFX10-NEXT: s_setpc_b64 s[30:31] 1665 %result = lshr i65 %value, %amount 1666 ret i65 %result 1667} 1668 1669define i65 @v_lshr_i65_33(i65 %value) { 1670; GFX6-LABEL: v_lshr_i65_33: 1671; GFX6: ; %bb.0: 1672; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1673; GFX6-NEXT: v_mov_b32_e32 v3, v1 1674; GFX6-NEXT: v_and_b32_e32 v0, 1, v2 1675; GFX6-NEXT: v_mov_b32_e32 v1, 0 1676; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 31 1677; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v3 1678; GFX6-NEXT: v_or_b32_e32 v0, v2, v0 1679; GFX6-NEXT: v_mov_b32_e32 v2, 0 1680; GFX6-NEXT: s_setpc_b64 s[30:31] 1681; 1682; GFX8-LABEL: v_lshr_i65_33: 1683; GFX8: ; %bb.0: 1684; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1685; GFX8-NEXT: v_mov_b32_e32 v3, v1 1686; GFX8-NEXT: v_and_b32_e32 v0, 1, v2 1687; GFX8-NEXT: v_mov_b32_e32 v1, 0 1688; GFX8-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1] 1689; GFX8-NEXT: v_lshrrev_b32_e32 v2, 1, v3 1690; GFX8-NEXT: v_or_b32_e32 v0, v2, v0 1691; GFX8-NEXT: v_mov_b32_e32 v2, 0 1692; GFX8-NEXT: s_setpc_b64 s[30:31] 1693; 1694; GFX9-LABEL: v_lshr_i65_33: 1695; GFX9: ; %bb.0: 1696; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1697; GFX9-NEXT: v_mov_b32_e32 v3, v1 1698; GFX9-NEXT: v_and_b32_e32 v0, 1, v2 1699; GFX9-NEXT: v_mov_b32_e32 v1, 0 1700; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1] 1701; GFX9-NEXT: v_lshrrev_b32_e32 v2, 1, v3 1702; GFX9-NEXT: v_or_b32_e32 v0, v2, v0 1703; GFX9-NEXT: v_mov_b32_e32 v2, 0 1704; GFX9-NEXT: s_setpc_b64 s[30:31] 1705; 1706; GFX10-LABEL: v_lshr_i65_33: 1707; GFX10: ; %bb.0: 1708; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1709; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1710; GFX10-NEXT: v_mov_b32_e32 v3, v1 1711; GFX10-NEXT: v_mov_b32_e32 v1, 0 1712; GFX10-NEXT: v_and_b32_e32 v0, 1, v2 1713; GFX10-NEXT: v_lshrrev_b32_e32 v2, 1, v3 1714; GFX10-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1] 1715; GFX10-NEXT: v_or_b32_e32 v0, v2, v0 1716; GFX10-NEXT: v_mov_b32_e32 v2, 0 1717; GFX10-NEXT: s_setpc_b64 s[30:31] 1718 %result = lshr i65 %value, 33 1719 ret i65 %result 1720} 1721 1722define amdgpu_ps i65 @s_lshr_i65(i65 inreg %value, i65 inreg %amount) { 1723; GCN-LABEL: s_lshr_i65: 1724; GCN: ; %bb.0: 1725; GCN-NEXT: s_and_b64 s[4:5], s[2:3], 1 1726; GCN-NEXT: s_sub_i32 s10, s3, 64 1727; GCN-NEXT: s_sub_i32 s8, 64, s3 1728; GCN-NEXT: s_cmp_lt_u32 s3, 64 1729; GCN-NEXT: s_cselect_b32 s11, 1, 0 1730; GCN-NEXT: s_cmp_eq_u32 s3, 0 1731; GCN-NEXT: s_cselect_b32 s12, 1, 0 1732; GCN-NEXT: s_lshr_b64 s[6:7], s[4:5], s3 1733; GCN-NEXT: s_lshr_b64 s[2:3], s[0:1], s3 1734; GCN-NEXT: s_lshl_b64 s[8:9], s[4:5], s8 1735; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] 1736; GCN-NEXT: s_lshr_b64 s[4:5], s[4:5], s10 1737; GCN-NEXT: s_cmp_lg_u32 s11, 0 1738; GCN-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5] 1739; GCN-NEXT: s_cmp_lg_u32 s12, 0 1740; GCN-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] 1741; GCN-NEXT: s_cmp_lg_u32 s11, 0 1742; GCN-NEXT: s_cselect_b64 s[2:3], s[6:7], 0 1743; GCN-NEXT: ; return to shader part epilog 1744; 1745; GFX10-LABEL: s_lshr_i65: 1746; GFX10: ; %bb.0: 1747; GFX10-NEXT: s_and_b64 s[4:5], s[2:3], 1 1748; GFX10-NEXT: s_sub_i32 s10, s3, 64 1749; GFX10-NEXT: s_sub_i32 s2, 64, s3 1750; GFX10-NEXT: s_cmp_lt_u32 s3, 64 1751; GFX10-NEXT: s_cselect_b32 s11, 1, 0 1752; GFX10-NEXT: s_cmp_eq_u32 s3, 0 1753; GFX10-NEXT: s_cselect_b32 s12, 1, 0 1754; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s3 1755; GFX10-NEXT: s_lshl_b64 s[8:9], s[4:5], s2 1756; GFX10-NEXT: s_lshr_b64 s[2:3], s[4:5], s3 1757; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] 1758; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], s10 1759; GFX10-NEXT: s_cmp_lg_u32 s11, 0 1760; GFX10-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5] 1761; GFX10-NEXT: s_cmp_lg_u32 s12, 0 1762; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] 1763; GFX10-NEXT: s_cmp_lg_u32 s11, 0 1764; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], 0 1765; GFX10-NEXT: ; return to shader part epilog 1766 %result = lshr i65 %value, %amount 1767 ret i65 %result 1768} 1769 1770define amdgpu_ps i65 @s_lshr_i65_33(i65 inreg %value) { 1771; GCN-LABEL: s_lshr_i65_33: 1772; GCN: ; %bb.0: 1773; GCN-NEXT: s_and_b64 s[2:3], s[2:3], 1 1774; GCN-NEXT: s_lshr_b32 s0, s1, 1 1775; GCN-NEXT: s_mov_b32 s1, 0 1776; GCN-NEXT: s_lshl_b64 s[4:5], s[2:3], 31 1777; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] 1778; GCN-NEXT: s_lshr_b32 s2, s3, 1 1779; GCN-NEXT: ; return to shader part epilog 1780; 1781; GFX10-LABEL: s_lshr_i65_33: 1782; GFX10: ; %bb.0: 1783; GFX10-NEXT: s_and_b64 s[2:3], s[2:3], 1 1784; GFX10-NEXT: s_lshr_b32 s0, s1, 1 1785; GFX10-NEXT: s_mov_b32 s1, 0 1786; GFX10-NEXT: s_lshl_b64 s[4:5], s[2:3], 31 1787; GFX10-NEXT: s_lshr_b32 s2, s3, 1 1788; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] 1789; GFX10-NEXT: ; return to shader part epilog 1790 %result = lshr i65 %value, 33 1791 ret i65 %result 1792} 1793 1794; FIXME: Argument lowering asserts 1795; define <2 x i65> @v_lshr_v2i65(<2 x i65> %value, <2 x i65> %amount) { 1796; %result = lshr <2 x i65> %value, %amount 1797; ret <2 x i65> %result 1798; } 1799 1800; define amdgpu_ps <2 x i65> @s_lshr_v2i65(<2 x i65> inreg %value, <2 x i65> inreg %amount) { 1801; %result = lshr <2 x i65> %value, %amount 1802; ret <2 x i65> %result 1803; } 1804