1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s 3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s 4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s 5; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s 6; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s 7 8define i8 @v_lshr_i8(i8 %value, i8 %amount) { 9; GFX6-LABEL: v_lshr_i8: 10; GFX6: ; %bb.0: 11; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 12; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1 13; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0 14; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0 15; GFX6-NEXT: s_setpc_b64 s[30:31] 16; 17; GFX8-LABEL: v_lshr_i8: 18; GFX8: ; %bb.0: 19; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 20; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 21; GFX8-NEXT: s_setpc_b64 s[30:31] 22; 23; GFX9-LABEL: v_lshr_i8: 24; GFX9: ; %bb.0: 25; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 26; GFX9-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 27; GFX9-NEXT: s_setpc_b64 s[30:31] 28; 29; GFX10PLUS-LABEL: v_lshr_i8: 30; GFX10PLUS: ; %bb.0: 31; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 32; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 33; GFX10PLUS-NEXT: v_and_b32_e32 v1, 0xff, v1 34; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0xff, v0 35; GFX10PLUS-NEXT: v_lshrrev_b16 v0, v1, v0 36; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 37 %result = lshr i8 %value, %amount 38 ret i8 %result 39} 40 41define i8 @v_lshr_i8_7(i8 %value) { 42; GFX6-LABEL: v_lshr_i8_7: 43; GFX6: ; %bb.0: 44; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 45; GFX6-NEXT: v_bfe_u32 v0, v0, 7, 1 46; GFX6-NEXT: s_setpc_b64 s[30:31] 47; 48; GFX8-LABEL: v_lshr_i8_7: 49; GFX8: ; %bb.0: 50; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 51; GFX8-NEXT: v_mov_b32_e32 v1, 7 52; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 53; GFX8-NEXT: s_setpc_b64 s[30:31] 54; 55; GFX9-LABEL: v_lshr_i8_7: 56; GFX9: ; %bb.0: 57; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 58; GFX9-NEXT: v_mov_b32_e32 v1, 7 59; GFX9-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 60; GFX9-NEXT: s_setpc_b64 s[30:31] 61; 62; GFX10PLUS-LABEL: v_lshr_i8_7: 63; GFX10PLUS: ; %bb.0: 64; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 65; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 66; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0xff, v0 67; GFX10PLUS-NEXT: v_lshrrev_b16 v0, 7, v0 68; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 69 %result = lshr i8 %value, 7 70 ret i8 %result 71} 72 73define amdgpu_ps i8 @s_lshr_i8(i8 inreg %value, i8 inreg %amount) { 74; GCN-LABEL: s_lshr_i8: 75; GCN: ; %bb.0: 76; GCN-NEXT: s_and_b32 s0, s0, 0xff 77; GCN-NEXT: s_lshr_b32 s0, s0, s1 78; GCN-NEXT: ; return to shader part epilog 79; 80; GFX10PLUS-LABEL: s_lshr_i8: 81; GFX10PLUS: ; %bb.0: 82; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xff 83; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s1 84; GFX10PLUS-NEXT: ; return to shader part epilog 85 %result = lshr i8 %value, %amount 86 ret i8 %result 87} 88 89define amdgpu_ps i8 @s_lshr_i8_7(i8 inreg %value) { 90; GCN-LABEL: s_lshr_i8_7: 91; GCN: ; %bb.0: 92; GCN-NEXT: s_bfe_u32 s0, s0, 0x10007 93; GCN-NEXT: ; return to shader part epilog 94; 95; GFX10PLUS-LABEL: s_lshr_i8_7: 96; GFX10PLUS: ; %bb.0: 97; GFX10PLUS-NEXT: s_bfe_u32 s0, s0, 0x10007 98; GFX10PLUS-NEXT: ; return to shader part epilog 99 %result = lshr i8 %value, 7 100 ret i8 %result 101} 102 103 104define i24 @v_lshr_i24(i24 %value, i24 %amount) { 105; GCN-LABEL: v_lshr_i24: 106; GCN: ; %bb.0: 107; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 108; GCN-NEXT: v_and_b32_e32 v1, 0xffffff, v1 109; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 110; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0 111; GCN-NEXT: s_setpc_b64 s[30:31] 112; 113; GFX10PLUS-LABEL: v_lshr_i24: 114; GFX10PLUS: ; %bb.0: 115; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 116; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 117; GFX10PLUS-NEXT: v_and_b32_e32 v1, 0xffffff, v1 118; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0xffffff, v0 119; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, v1, v0 120; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 121 %result = lshr i24 %value, %amount 122 ret i24 %result 123} 124 125define i24 @v_lshr_i24_7(i24 %value) { 126; GCN-LABEL: v_lshr_i24_7: 127; GCN: ; %bb.0: 128; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 129; GCN-NEXT: v_bfe_u32 v0, v0, 7, 17 130; GCN-NEXT: s_setpc_b64 s[30:31] 131; 132; GFX10PLUS-LABEL: v_lshr_i24_7: 133; GFX10PLUS: ; %bb.0: 134; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 135; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 136; GFX10PLUS-NEXT: v_bfe_u32 v0, v0, 7, 17 137; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 138 %result = lshr i24 %value, 7 139 ret i24 %result 140} 141 142define amdgpu_ps i24 @s_lshr_i24(i24 inreg %value, i24 inreg %amount) { 143; GCN-LABEL: s_lshr_i24: 144; GCN: ; %bb.0: 145; GCN-NEXT: s_and_b32 s0, s0, 0xffffff 146; GCN-NEXT: s_lshr_b32 s0, s0, s1 147; GCN-NEXT: ; return to shader part epilog 148; 149; GFX10PLUS-LABEL: s_lshr_i24: 150; GFX10PLUS: ; %bb.0: 151; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xffffff 152; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s1 153; GFX10PLUS-NEXT: ; return to shader part epilog 154 %result = lshr i24 %value, %amount 155 ret i24 %result 156} 157 158define amdgpu_ps i24 @s_lshr_i24_7(i24 inreg %value) { 159; GCN-LABEL: s_lshr_i24_7: 160; GCN: ; %bb.0: 161; GCN-NEXT: s_bfe_u32 s0, s0, 0x110007 162; GCN-NEXT: ; return to shader part epilog 163; 164; GFX10PLUS-LABEL: s_lshr_i24_7: 165; GFX10PLUS: ; %bb.0: 166; GFX10PLUS-NEXT: s_bfe_u32 s0, s0, 0x110007 167; GFX10PLUS-NEXT: ; return to shader part epilog 168 %result = lshr i24 %value, 7 169 ret i24 %result 170} 171 172define i32 @v_lshr_i32(i32 %value, i32 %amount) { 173; GCN-LABEL: v_lshr_i32: 174; GCN: ; %bb.0: 175; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 176; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0 177; GCN-NEXT: s_setpc_b64 s[30:31] 178; 179; GFX10PLUS-LABEL: v_lshr_i32: 180; GFX10PLUS: ; %bb.0: 181; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 182; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 183; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, v1, v0 184; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 185 %result = lshr i32 %value, %amount 186 ret i32 %result 187} 188 189define i32 @v_lshr_i32_31(i32 %value) { 190; GCN-LABEL: v_lshr_i32_31: 191; GCN: ; %bb.0: 192; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 193; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0 194; GCN-NEXT: s_setpc_b64 s[30:31] 195; 196; GFX10PLUS-LABEL: v_lshr_i32_31: 197; GFX10PLUS: ; %bb.0: 198; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 199; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 200; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, 31, v0 201; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 202 %result = lshr i32 %value, 31 203 ret i32 %result 204} 205 206define amdgpu_ps i32 @s_lshr_i32(i32 inreg %value, i32 inreg %amount) { 207; GCN-LABEL: s_lshr_i32: 208; GCN: ; %bb.0: 209; GCN-NEXT: s_lshr_b32 s0, s0, s1 210; GCN-NEXT: ; return to shader part epilog 211; 212; GFX10PLUS-LABEL: s_lshr_i32: 213; GFX10PLUS: ; %bb.0: 214; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s1 215; GFX10PLUS-NEXT: ; return to shader part epilog 216 %result = lshr i32 %value, %amount 217 ret i32 %result 218} 219 220define amdgpu_ps i32 @s_lshr_i32_31(i32 inreg %value) { 221; GCN-LABEL: s_lshr_i32_31: 222; GCN: ; %bb.0: 223; GCN-NEXT: s_lshr_b32 s0, s0, 31 224; GCN-NEXT: ; return to shader part epilog 225; 226; GFX10PLUS-LABEL: s_lshr_i32_31: 227; GFX10PLUS: ; %bb.0: 228; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, 31 229; GFX10PLUS-NEXT: ; return to shader part epilog 230 %result = lshr i32 %value, 31 231 ret i32 %result 232} 233 234define amdgpu_ps float @lshr_i32_sv(i32 inreg %value, i32 %amount) { 235; GFX6-LABEL: lshr_i32_sv: 236; GFX6: ; %bb.0: 237; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0 238; GFX6-NEXT: ; return to shader part epilog 239; 240; GFX8-LABEL: lshr_i32_sv: 241; GFX8: ; %bb.0: 242; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s0 243; GFX8-NEXT: ; return to shader part epilog 244; 245; GFX9-LABEL: lshr_i32_sv: 246; GFX9: ; %bb.0: 247; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s0 248; GFX9-NEXT: ; return to shader part epilog 249; 250; GFX10PLUS-LABEL: lshr_i32_sv: 251; GFX10PLUS: ; %bb.0: 252; GFX10PLUS-NEXT: v_lshrrev_b32_e64 v0, v0, s0 253; GFX10PLUS-NEXT: ; return to shader part epilog 254 %result = lshr i32 %value, %amount 255 %cast = bitcast i32 %result to float 256 ret float %cast 257} 258 259define amdgpu_ps float @lshr_i32_vs(i32 %value, i32 inreg %amount) { 260; GCN-LABEL: lshr_i32_vs: 261; GCN: ; %bb.0: 262; GCN-NEXT: v_lshrrev_b32_e32 v0, s0, v0 263; GCN-NEXT: ; return to shader part epilog 264; 265; GFX10PLUS-LABEL: lshr_i32_vs: 266; GFX10PLUS: ; %bb.0: 267; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, s0, v0 268; GFX10PLUS-NEXT: ; return to shader part epilog 269 %result = lshr i32 %value, %amount 270 %cast = bitcast i32 %result to float 271 ret float %cast 272} 273 274define <2 x i32> @v_lshr_v2i32(<2 x i32> %value, <2 x i32> %amount) { 275; GCN-LABEL: v_lshr_v2i32: 276; GCN: ; %bb.0: 277; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 278; GCN-NEXT: v_lshrrev_b32_e32 v0, v2, v0 279; GCN-NEXT: v_lshrrev_b32_e32 v1, v3, v1 280; GCN-NEXT: s_setpc_b64 s[30:31] 281; 282; GFX10PLUS-LABEL: v_lshr_v2i32: 283; GFX10PLUS: ; %bb.0: 284; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 285; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 286; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, v2, v0 287; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v1, v3, v1 288; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 289 %result = lshr <2 x i32> %value, %amount 290 ret <2 x i32> %result 291} 292 293define <2 x i32> @v_lshr_v2i32_31(<2 x i32> %value) { 294; GCN-LABEL: v_lshr_v2i32_31: 295; GCN: ; %bb.0: 296; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 297; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0 298; GCN-NEXT: v_lshrrev_b32_e32 v1, 31, v1 299; GCN-NEXT: s_setpc_b64 s[30:31] 300; 301; GFX10PLUS-LABEL: v_lshr_v2i32_31: 302; GFX10PLUS: ; %bb.0: 303; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 304; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 305; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, 31, v0 306; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v1, 31, v1 307; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 308 %result = lshr <2 x i32> %value, <i32 31, i32 31> 309 ret <2 x i32> %result 310} 311 312define amdgpu_ps <2 x i32> @s_lshr_v2i32(<2 x i32> inreg %value, <2 x i32> inreg %amount) { 313; GCN-LABEL: s_lshr_v2i32: 314; GCN: ; %bb.0: 315; GCN-NEXT: s_lshr_b32 s0, s0, s2 316; GCN-NEXT: s_lshr_b32 s1, s1, s3 317; GCN-NEXT: ; return to shader part epilog 318; 319; GFX10PLUS-LABEL: s_lshr_v2i32: 320; GFX10PLUS: ; %bb.0: 321; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s2 322; GFX10PLUS-NEXT: s_lshr_b32 s1, s1, s3 323; GFX10PLUS-NEXT: ; return to shader part epilog 324 %result = lshr <2 x i32> %value, %amount 325 ret <2 x i32> %result 326} 327 328define <3 x i32> @v_lshr_v3i32(<3 x i32> %value, <3 x i32> %amount) { 329; GCN-LABEL: v_lshr_v3i32: 330; GCN: ; %bb.0: 331; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 332; GCN-NEXT: v_lshrrev_b32_e32 v0, v3, v0 333; GCN-NEXT: v_lshrrev_b32_e32 v1, v4, v1 334; GCN-NEXT: v_lshrrev_b32_e32 v2, v5, v2 335; GCN-NEXT: s_setpc_b64 s[30:31] 336; 337; GFX10PLUS-LABEL: v_lshr_v3i32: 338; GFX10PLUS: ; %bb.0: 339; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 340; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 341; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, v3, v0 342; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v1, v4, v1 343; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v2, v5, v2 344; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 345 %result = lshr <3 x i32> %value, %amount 346 ret <3 x i32> %result 347} 348 349define amdgpu_ps <3 x i32> @s_lshr_v3i32(<3 x i32> inreg %value, <3 x i32> inreg %amount) { 350; GCN-LABEL: s_lshr_v3i32: 351; GCN: ; %bb.0: 352; GCN-NEXT: s_lshr_b32 s0, s0, s3 353; GCN-NEXT: s_lshr_b32 s1, s1, s4 354; GCN-NEXT: s_lshr_b32 s2, s2, s5 355; GCN-NEXT: ; return to shader part epilog 356; 357; GFX10PLUS-LABEL: s_lshr_v3i32: 358; GFX10PLUS: ; %bb.0: 359; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s3 360; GFX10PLUS-NEXT: s_lshr_b32 s1, s1, s4 361; GFX10PLUS-NEXT: s_lshr_b32 s2, s2, s5 362; GFX10PLUS-NEXT: ; return to shader part epilog 363 %result = lshr <3 x i32> %value, %amount 364 ret <3 x i32> %result 365} 366 367define <4 x i32> @v_lshr_v4i32(<4 x i32> %value, <4 x i32> %amount) { 368; GCN-LABEL: v_lshr_v4i32: 369; GCN: ; %bb.0: 370; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 371; GCN-NEXT: v_lshrrev_b32_e32 v0, v4, v0 372; GCN-NEXT: v_lshrrev_b32_e32 v1, v5, v1 373; GCN-NEXT: v_lshrrev_b32_e32 v2, v6, v2 374; GCN-NEXT: v_lshrrev_b32_e32 v3, v7, v3 375; GCN-NEXT: s_setpc_b64 s[30:31] 376; 377; GFX10PLUS-LABEL: v_lshr_v4i32: 378; GFX10PLUS: ; %bb.0: 379; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 380; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 381; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, v4, v0 382; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v1, v5, v1 383; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v2, v6, v2 384; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v3, v7, v3 385; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 386 %result = lshr <4 x i32> %value, %amount 387 ret <4 x i32> %result 388} 389 390define amdgpu_ps <4 x i32> @s_lshr_v4i32(<4 x i32> inreg %value, <4 x i32> inreg %amount) { 391; GCN-LABEL: s_lshr_v4i32: 392; GCN: ; %bb.0: 393; GCN-NEXT: s_lshr_b32 s0, s0, s4 394; GCN-NEXT: s_lshr_b32 s1, s1, s5 395; GCN-NEXT: s_lshr_b32 s2, s2, s6 396; GCN-NEXT: s_lshr_b32 s3, s3, s7 397; GCN-NEXT: ; return to shader part epilog 398; 399; GFX10PLUS-LABEL: s_lshr_v4i32: 400; GFX10PLUS: ; %bb.0: 401; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s4 402; GFX10PLUS-NEXT: s_lshr_b32 s1, s1, s5 403; GFX10PLUS-NEXT: s_lshr_b32 s2, s2, s6 404; GFX10PLUS-NEXT: s_lshr_b32 s3, s3, s7 405; GFX10PLUS-NEXT: ; return to shader part epilog 406 %result = lshr <4 x i32> %value, %amount 407 ret <4 x i32> %result 408} 409 410define <5 x i32> @v_lshr_v5i32(<5 x i32> %value, <5 x i32> %amount) { 411; GCN-LABEL: v_lshr_v5i32: 412; GCN: ; %bb.0: 413; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 414; GCN-NEXT: v_lshrrev_b32_e32 v0, v5, v0 415; GCN-NEXT: v_lshrrev_b32_e32 v1, v6, v1 416; GCN-NEXT: v_lshrrev_b32_e32 v2, v7, v2 417; GCN-NEXT: v_lshrrev_b32_e32 v3, v8, v3 418; GCN-NEXT: v_lshrrev_b32_e32 v4, v9, v4 419; GCN-NEXT: s_setpc_b64 s[30:31] 420; 421; GFX10PLUS-LABEL: v_lshr_v5i32: 422; GFX10PLUS: ; %bb.0: 423; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 424; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 425; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, v5, v0 426; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v1, v6, v1 427; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v2, v7, v2 428; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v3, v8, v3 429; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v4, v9, v4 430; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 431 %result = lshr <5 x i32> %value, %amount 432 ret <5 x i32> %result 433} 434 435define amdgpu_ps <5 x i32> @s_lshr_v5i32(<5 x i32> inreg %value, <5 x i32> inreg %amount) { 436; GCN-LABEL: s_lshr_v5i32: 437; GCN: ; %bb.0: 438; GCN-NEXT: s_lshr_b32 s0, s0, s5 439; GCN-NEXT: s_lshr_b32 s1, s1, s6 440; GCN-NEXT: s_lshr_b32 s2, s2, s7 441; GCN-NEXT: s_lshr_b32 s3, s3, s8 442; GCN-NEXT: s_lshr_b32 s4, s4, s9 443; GCN-NEXT: ; return to shader part epilog 444; 445; GFX10PLUS-LABEL: s_lshr_v5i32: 446; GFX10PLUS: ; %bb.0: 447; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s5 448; GFX10PLUS-NEXT: s_lshr_b32 s1, s1, s6 449; GFX10PLUS-NEXT: s_lshr_b32 s2, s2, s7 450; GFX10PLUS-NEXT: s_lshr_b32 s3, s3, s8 451; GFX10PLUS-NEXT: s_lshr_b32 s4, s4, s9 452; GFX10PLUS-NEXT: ; return to shader part epilog 453 %result = lshr <5 x i32> %value, %amount 454 ret <5 x i32> %result 455} 456 457define <16 x i32> @v_lshr_v16i32(<16 x i32> %value, <16 x i32> %amount) { 458; GCN-LABEL: v_lshr_v16i32: 459; GCN: ; %bb.0: 460; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 461; GCN-NEXT: v_lshrrev_b32_e32 v0, v16, v0 462; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 463; GCN-NEXT: v_lshrrev_b32_e32 v1, v17, v1 464; GCN-NEXT: v_lshrrev_b32_e32 v2, v18, v2 465; GCN-NEXT: v_lshrrev_b32_e32 v3, v19, v3 466; GCN-NEXT: v_lshrrev_b32_e32 v4, v20, v4 467; GCN-NEXT: v_lshrrev_b32_e32 v5, v21, v5 468; GCN-NEXT: v_lshrrev_b32_e32 v6, v22, v6 469; GCN-NEXT: v_lshrrev_b32_e32 v7, v23, v7 470; GCN-NEXT: v_lshrrev_b32_e32 v8, v24, v8 471; GCN-NEXT: v_lshrrev_b32_e32 v9, v25, v9 472; GCN-NEXT: v_lshrrev_b32_e32 v10, v26, v10 473; GCN-NEXT: v_lshrrev_b32_e32 v11, v27, v11 474; GCN-NEXT: v_lshrrev_b32_e32 v12, v28, v12 475; GCN-NEXT: v_lshrrev_b32_e32 v13, v29, v13 476; GCN-NEXT: v_lshrrev_b32_e32 v14, v30, v14 477; GCN-NEXT: s_waitcnt vmcnt(0) 478; GCN-NEXT: v_lshrrev_b32_e32 v15, v16, v15 479; GCN-NEXT: s_setpc_b64 s[30:31] 480; 481; GFX10-LABEL: v_lshr_v16i32: 482; GFX10: ; %bb.0: 483; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 484; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 485; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32 486; GFX10-NEXT: v_lshrrev_b32_e32 v0, v16, v0 487; GFX10-NEXT: v_lshrrev_b32_e32 v1, v17, v1 488; GFX10-NEXT: v_lshrrev_b32_e32 v2, v18, v2 489; GFX10-NEXT: v_lshrrev_b32_e32 v3, v19, v3 490; GFX10-NEXT: v_lshrrev_b32_e32 v4, v20, v4 491; GFX10-NEXT: v_lshrrev_b32_e32 v5, v21, v5 492; GFX10-NEXT: v_lshrrev_b32_e32 v6, v22, v6 493; GFX10-NEXT: v_lshrrev_b32_e32 v7, v23, v7 494; GFX10-NEXT: v_lshrrev_b32_e32 v8, v24, v8 495; GFX10-NEXT: v_lshrrev_b32_e32 v9, v25, v9 496; GFX10-NEXT: v_lshrrev_b32_e32 v10, v26, v10 497; GFX10-NEXT: v_lshrrev_b32_e32 v11, v27, v11 498; GFX10-NEXT: v_lshrrev_b32_e32 v12, v28, v12 499; GFX10-NEXT: v_lshrrev_b32_e32 v13, v29, v13 500; GFX10-NEXT: v_lshrrev_b32_e32 v14, v30, v14 501; GFX10-NEXT: s_waitcnt vmcnt(0) 502; GFX10-NEXT: v_lshrrev_b32_e32 v15, v31, v15 503; GFX10-NEXT: s_setpc_b64 s[30:31] 504; 505; GFX11-LABEL: v_lshr_v16i32: 506; GFX11: ; %bb.0: 507; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 508; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 509; GFX11-NEXT: scratch_load_b32 v31, off, s32 510; GFX11-NEXT: v_lshrrev_b32_e32 v0, v16, v0 511; GFX11-NEXT: v_lshrrev_b32_e32 v1, v17, v1 512; GFX11-NEXT: v_lshrrev_b32_e32 v2, v18, v2 513; GFX11-NEXT: v_lshrrev_b32_e32 v3, v19, v3 514; GFX11-NEXT: v_lshrrev_b32_e32 v4, v20, v4 515; GFX11-NEXT: v_lshrrev_b32_e32 v5, v21, v5 516; GFX11-NEXT: v_lshrrev_b32_e32 v6, v22, v6 517; GFX11-NEXT: v_lshrrev_b32_e32 v7, v23, v7 518; GFX11-NEXT: v_lshrrev_b32_e32 v8, v24, v8 519; GFX11-NEXT: v_lshrrev_b32_e32 v9, v25, v9 520; GFX11-NEXT: v_lshrrev_b32_e32 v10, v26, v10 521; GFX11-NEXT: v_lshrrev_b32_e32 v11, v27, v11 522; GFX11-NEXT: v_lshrrev_b32_e32 v12, v28, v12 523; GFX11-NEXT: v_lshrrev_b32_e32 v13, v29, v13 524; GFX11-NEXT: v_lshrrev_b32_e32 v14, v30, v14 525; GFX11-NEXT: s_waitcnt vmcnt(0) 526; GFX11-NEXT: v_lshrrev_b32_e32 v15, v31, v15 527; GFX11-NEXT: s_setpc_b64 s[30:31] 528 %result = lshr <16 x i32> %value, %amount 529 ret <16 x i32> %result 530} 531 532define amdgpu_ps <16 x i32> @s_lshr_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) { 533; GCN-LABEL: s_lshr_v16i32: 534; GCN: ; %bb.0: 535; GCN-NEXT: s_lshr_b32 s0, s0, s16 536; GCN-NEXT: s_lshr_b32 s1, s1, s17 537; GCN-NEXT: s_lshr_b32 s2, s2, s18 538; GCN-NEXT: s_lshr_b32 s3, s3, s19 539; GCN-NEXT: s_lshr_b32 s4, s4, s20 540; GCN-NEXT: s_lshr_b32 s5, s5, s21 541; GCN-NEXT: s_lshr_b32 s6, s6, s22 542; GCN-NEXT: s_lshr_b32 s7, s7, s23 543; GCN-NEXT: s_lshr_b32 s8, s8, s24 544; GCN-NEXT: s_lshr_b32 s9, s9, s25 545; GCN-NEXT: s_lshr_b32 s10, s10, s26 546; GCN-NEXT: s_lshr_b32 s11, s11, s27 547; GCN-NEXT: s_lshr_b32 s12, s12, s28 548; GCN-NEXT: s_lshr_b32 s13, s13, s29 549; GCN-NEXT: s_lshr_b32 s14, s14, s30 550; GCN-NEXT: s_lshr_b32 s15, s15, s31 551; GCN-NEXT: ; return to shader part epilog 552; 553; GFX10PLUS-LABEL: s_lshr_v16i32: 554; GFX10PLUS: ; %bb.0: 555; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s16 556; GFX10PLUS-NEXT: s_lshr_b32 s1, s1, s17 557; GFX10PLUS-NEXT: s_lshr_b32 s2, s2, s18 558; GFX10PLUS-NEXT: s_lshr_b32 s3, s3, s19 559; GFX10PLUS-NEXT: s_lshr_b32 s4, s4, s20 560; GFX10PLUS-NEXT: s_lshr_b32 s5, s5, s21 561; GFX10PLUS-NEXT: s_lshr_b32 s6, s6, s22 562; GFX10PLUS-NEXT: s_lshr_b32 s7, s7, s23 563; GFX10PLUS-NEXT: s_lshr_b32 s8, s8, s24 564; GFX10PLUS-NEXT: s_lshr_b32 s9, s9, s25 565; GFX10PLUS-NEXT: s_lshr_b32 s10, s10, s26 566; GFX10PLUS-NEXT: s_lshr_b32 s11, s11, s27 567; GFX10PLUS-NEXT: s_lshr_b32 s12, s12, s28 568; GFX10PLUS-NEXT: s_lshr_b32 s13, s13, s29 569; GFX10PLUS-NEXT: s_lshr_b32 s14, s14, s30 570; GFX10PLUS-NEXT: s_lshr_b32 s15, s15, s31 571; GFX10PLUS-NEXT: ; return to shader part epilog 572 %result = lshr <16 x i32> %value, %amount 573 ret <16 x i32> %result 574} 575 576define i16 @v_lshr_i16(i16 %value, i16 %amount) { 577; GFX6-LABEL: v_lshr_i16: 578; GFX6: ; %bb.0: 579; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 580; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 581; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 582; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0 583; GFX6-NEXT: s_setpc_b64 s[30:31] 584; 585; GFX8-LABEL: v_lshr_i16: 586; GFX8: ; %bb.0: 587; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 588; GFX8-NEXT: v_lshrrev_b16_e32 v0, v1, v0 589; GFX8-NEXT: s_setpc_b64 s[30:31] 590; 591; GFX9-LABEL: v_lshr_i16: 592; GFX9: ; %bb.0: 593; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 594; GFX9-NEXT: v_lshrrev_b16_e32 v0, v1, v0 595; GFX9-NEXT: s_setpc_b64 s[30:31] 596; 597; GFX10PLUS-LABEL: v_lshr_i16: 598; GFX10PLUS: ; %bb.0: 599; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 600; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 601; GFX10PLUS-NEXT: v_lshrrev_b16 v0, v1, v0 602; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 603 %result = lshr i16 %value, %amount 604 ret i16 %result 605} 606 607define i16 @v_lshr_i16_31(i16 %value) { 608; GCN-LABEL: v_lshr_i16_31: 609; GCN: ; %bb.0: 610; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 611; GCN-NEXT: s_setpc_b64 s[30:31] 612; 613; GFX10PLUS-LABEL: v_lshr_i16_31: 614; GFX10PLUS: ; %bb.0: 615; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 616; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 617; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 618 %result = lshr i16 %value, 31 619 ret i16 %result 620} 621 622define amdgpu_ps i16 @s_lshr_i16(i16 inreg %value, i16 inreg %amount) { 623; GCN-LABEL: s_lshr_i16: 624; GCN: ; %bb.0: 625; GCN-NEXT: s_and_b32 s0, s0, 0xffff 626; GCN-NEXT: s_lshr_b32 s0, s0, s1 627; GCN-NEXT: ; return to shader part epilog 628; 629; GFX10PLUS-LABEL: s_lshr_i16: 630; GFX10PLUS: ; %bb.0: 631; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xffff 632; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s1 633; GFX10PLUS-NEXT: ; return to shader part epilog 634 %result = lshr i16 %value, %amount 635 ret i16 %result 636} 637 638define amdgpu_ps i16 @s_lshr_i16_15(i16 inreg %value) { 639; GCN-LABEL: s_lshr_i16_15: 640; GCN: ; %bb.0: 641; GCN-NEXT: s_bfe_u32 s0, s0, 0x1000f 642; GCN-NEXT: ; return to shader part epilog 643; 644; GFX10PLUS-LABEL: s_lshr_i16_15: 645; GFX10PLUS: ; %bb.0: 646; GFX10PLUS-NEXT: s_bfe_u32 s0, s0, 0x1000f 647; GFX10PLUS-NEXT: ; return to shader part epilog 648 %result = lshr i16 %value, 15 649 ret i16 %result 650} 651 652define amdgpu_ps half @lshr_i16_sv(i16 inreg %value, i16 %amount) { 653; GFX6-LABEL: lshr_i16_sv: 654; GFX6: ; %bb.0: 655; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 656; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 657; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0 658; GFX6-NEXT: ; return to shader part epilog 659; 660; GFX8-LABEL: lshr_i16_sv: 661; GFX8: ; %bb.0: 662; GFX8-NEXT: v_lshrrev_b16_e64 v0, v0, s0 663; GFX8-NEXT: ; return to shader part epilog 664; 665; GFX9-LABEL: lshr_i16_sv: 666; GFX9: ; %bb.0: 667; GFX9-NEXT: v_lshrrev_b16_e64 v0, v0, s0 668; GFX9-NEXT: ; return to shader part epilog 669; 670; GFX10PLUS-LABEL: lshr_i16_sv: 671; GFX10PLUS: ; %bb.0: 672; GFX10PLUS-NEXT: v_lshrrev_b16 v0, v0, s0 673; GFX10PLUS-NEXT: ; return to shader part epilog 674 %result = lshr i16 %value, %amount 675 %cast = bitcast i16 %result to half 676 ret half %cast 677} 678 679define amdgpu_ps half @lshr_i16_vs(i16 %value, i16 inreg %amount) { 680; GFX6-LABEL: lshr_i16_vs: 681; GFX6: ; %bb.0: 682; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 683; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 684; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0 685; GFX6-NEXT: ; return to shader part epilog 686; 687; GFX8-LABEL: lshr_i16_vs: 688; GFX8: ; %bb.0: 689; GFX8-NEXT: v_lshrrev_b16_e32 v0, s0, v0 690; GFX8-NEXT: ; return to shader part epilog 691; 692; GFX9-LABEL: lshr_i16_vs: 693; GFX9: ; %bb.0: 694; GFX9-NEXT: v_lshrrev_b16_e32 v0, s0, v0 695; GFX9-NEXT: ; return to shader part epilog 696; 697; GFX10PLUS-LABEL: lshr_i16_vs: 698; GFX10PLUS: ; %bb.0: 699; GFX10PLUS-NEXT: v_lshrrev_b16 v0, s0, v0 700; GFX10PLUS-NEXT: ; return to shader part epilog 701 %result = lshr i16 %value, %amount 702 %cast = bitcast i16 %result to half 703 ret half %cast 704} 705 706define <2 x i16> @v_lshr_v2i16(<2 x i16> %value, <2 x i16> %amount) { 707; GFX6-LABEL: v_lshr_v2i16: 708; GFX6: ; %bb.0: 709; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 710; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2 711; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 712; GFX6-NEXT: v_lshrrev_b32_e32 v0, v2, v0 713; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3 714; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 715; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1 716; GFX6-NEXT: s_setpc_b64 s[30:31] 717; 718; GFX8-LABEL: v_lshr_v2i16: 719; GFX8: ; %bb.0: 720; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 721; GFX8-NEXT: v_lshrrev_b16_e32 v2, v1, v0 722; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 723; GFX8-NEXT: v_or_b32_e32 v0, v2, v0 724; GFX8-NEXT: s_setpc_b64 s[30:31] 725; 726; GFX9-LABEL: v_lshr_v2i16: 727; GFX9: ; %bb.0: 728; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 729; GFX9-NEXT: v_pk_lshrrev_b16 v0, v1, v0 730; GFX9-NEXT: s_setpc_b64 s[30:31] 731; 732; GFX10PLUS-LABEL: v_lshr_v2i16: 733; GFX10PLUS: ; %bb.0: 734; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 735; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 736; GFX10PLUS-NEXT: v_pk_lshrrev_b16 v0, v1, v0 737; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 738 %result = lshr <2 x i16> %value, %amount 739 ret <2 x i16> %result 740} 741 742define <2 x i16> @v_lshr_v2i16_15(<2 x i16> %value) { 743; GFX6-LABEL: v_lshr_v2i16_15: 744; GFX6: ; %bb.0: 745; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 746; GFX6-NEXT: v_bfe_u32 v0, v0, 15, 1 747; GFX6-NEXT: v_bfe_u32 v1, v1, 15, 1 748; GFX6-NEXT: s_setpc_b64 s[30:31] 749; 750; GFX8-LABEL: v_lshr_v2i16_15: 751; GFX8: ; %bb.0: 752; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 753; GFX8-NEXT: v_mov_b32_e32 v2, 15 754; GFX8-NEXT: v_lshrrev_b16_e32 v1, 15, v0 755; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 756; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 757; GFX8-NEXT: s_setpc_b64 s[30:31] 758; 759; GFX9-LABEL: v_lshr_v2i16_15: 760; GFX9: ; %bb.0: 761; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 762; GFX9-NEXT: v_pk_lshrrev_b16 v0, 15, v0 op_sel_hi:[0,1] 763; GFX9-NEXT: s_setpc_b64 s[30:31] 764; 765; GFX10PLUS-LABEL: v_lshr_v2i16_15: 766; GFX10PLUS: ; %bb.0: 767; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 768; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 769; GFX10PLUS-NEXT: v_pk_lshrrev_b16 v0, 15, v0 op_sel_hi:[0,1] 770; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 771 %result = lshr <2 x i16> %value, <i16 15, i16 15> 772 ret <2 x i16> %result 773} 774 775define amdgpu_ps i32 @s_lshr_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) { 776; GFX6-LABEL: s_lshr_v2i16: 777; GFX6: ; %bb.0: 778; GFX6-NEXT: s_and_b32 s1, s1, 0xffff 779; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 780; GFX6-NEXT: s_lshr_b32 s1, s1, s3 781; GFX6-NEXT: s_lshr_b32 s0, s0, s2 782; GFX6-NEXT: s_lshl_b32 s1, s1, 16 783; GFX6-NEXT: s_or_b32 s0, s0, s1 784; GFX6-NEXT: ; return to shader part epilog 785; 786; GFX8-LABEL: s_lshr_v2i16: 787; GFX8: ; %bb.0: 788; GFX8-NEXT: s_lshr_b32 s2, s0, 16 789; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 790; GFX8-NEXT: s_lshr_b32 s3, s1, 16 791; GFX8-NEXT: s_lshr_b32 s0, s0, s1 792; GFX8-NEXT: s_lshr_b32 s1, s2, s3 793; GFX8-NEXT: s_lshl_b32 s1, s1, 16 794; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 795; GFX8-NEXT: s_or_b32 s0, s1, s0 796; GFX8-NEXT: ; return to shader part epilog 797; 798; GFX9-LABEL: s_lshr_v2i16: 799; GFX9: ; %bb.0: 800; GFX9-NEXT: s_lshr_b32 s2, s0, 16 801; GFX9-NEXT: s_and_b32 s0, s0, 0xffff 802; GFX9-NEXT: s_lshr_b32 s3, s1, 16 803; GFX9-NEXT: s_lshr_b32 s0, s0, s1 804; GFX9-NEXT: s_lshr_b32 s1, s2, s3 805; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1 806; GFX9-NEXT: ; return to shader part epilog 807; 808; GFX10PLUS-LABEL: s_lshr_v2i16: 809; GFX10PLUS: ; %bb.0: 810; GFX10PLUS-NEXT: s_lshr_b32 s2, s0, 16 811; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xffff 812; GFX10PLUS-NEXT: s_lshr_b32 s3, s1, 16 813; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s1 814; GFX10PLUS-NEXT: s_lshr_b32 s1, s2, s3 815; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s0, s1 816; GFX10PLUS-NEXT: ; return to shader part epilog 817 %result = lshr <2 x i16> %value, %amount 818 %cast = bitcast <2 x i16> %result to i32 819 ret i32 %cast 820} 821 822define amdgpu_ps float @lshr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) { 823; GFX6-LABEL: lshr_v2i16_sv: 824; GFX6: ; %bb.0: 825; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 826; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 827; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0 828; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 829; GFX6-NEXT: s_and_b32 s0, s1, 0xffff 830; GFX6-NEXT: v_lshr_b32_e32 v1, s0, v1 831; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 832; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 833; GFX6-NEXT: ; return to shader part epilog 834; 835; GFX8-LABEL: lshr_v2i16_sv: 836; GFX8: ; %bb.0: 837; GFX8-NEXT: s_lshr_b32 s1, s0, 16 838; GFX8-NEXT: v_mov_b32_e32 v2, s1 839; GFX8-NEXT: v_lshrrev_b16_e64 v1, v0, s0 840; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 841; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 842; GFX8-NEXT: ; return to shader part epilog 843; 844; GFX9-LABEL: lshr_v2i16_sv: 845; GFX9: ; %bb.0: 846; GFX9-NEXT: v_pk_lshrrev_b16 v0, v0, s0 847; GFX9-NEXT: ; return to shader part epilog 848; 849; GFX10PLUS-LABEL: lshr_v2i16_sv: 850; GFX10PLUS: ; %bb.0: 851; GFX10PLUS-NEXT: v_pk_lshrrev_b16 v0, v0, s0 852; GFX10PLUS-NEXT: ; return to shader part epilog 853 %result = lshr <2 x i16> %value, %amount 854 %cast = bitcast <2 x i16> %result to float 855 ret float %cast 856} 857 858define amdgpu_ps float @lshr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) { 859; GFX6-LABEL: lshr_v2i16_vs: 860; GFX6: ; %bb.0: 861; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 862; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 863; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0 864; GFX6-NEXT: s_and_b32 s0, s1, 0xffff 865; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 866; GFX6-NEXT: v_lshrrev_b32_e32 v1, s0, v1 867; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 868; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 869; GFX6-NEXT: ; return to shader part epilog 870; 871; GFX8-LABEL: lshr_v2i16_vs: 872; GFX8: ; %bb.0: 873; GFX8-NEXT: s_lshr_b32 s1, s0, 16 874; GFX8-NEXT: v_mov_b32_e32 v2, s1 875; GFX8-NEXT: v_lshrrev_b16_e32 v1, s0, v0 876; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 877; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 878; GFX8-NEXT: ; return to shader part epilog 879; 880; GFX9-LABEL: lshr_v2i16_vs: 881; GFX9: ; %bb.0: 882; GFX9-NEXT: v_pk_lshrrev_b16 v0, s0, v0 883; GFX9-NEXT: ; return to shader part epilog 884; 885; GFX10PLUS-LABEL: lshr_v2i16_vs: 886; GFX10PLUS: ; %bb.0: 887; GFX10PLUS-NEXT: v_pk_lshrrev_b16 v0, s0, v0 888; GFX10PLUS-NEXT: ; return to shader part epilog 889 %result = lshr <2 x i16> %value, %amount 890 %cast = bitcast <2 x i16> %result to float 891 ret float %cast 892} 893 894; FIXME 895; define <3 x i16> @v_lshr_v3i16(<3 x i16> %value, <3 x i16> %amount) { 896; %result = lshr <3 x i16> %value, %amount 897; ret <3 x i16> %result 898; } 899 900; define amdgpu_ps <3 x i16> @s_lshr_v3i16(<3 x i16> inreg %value, <3 x i16> inreg %amount) { 901; %result = lshr <3 x i16> %value, %amount 902; ret <3 x i16> %result 903; } 904 905define <2 x float> @v_lshr_v4i16(<4 x i16> %value, <4 x i16> %amount) { 906; GFX6-LABEL: v_lshr_v4i16: 907; GFX6: ; %bb.0: 908; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 909; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4 910; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 911; GFX6-NEXT: v_lshrrev_b32_e32 v0, v4, v0 912; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v5 913; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 914; GFX6-NEXT: v_lshrrev_b32_e32 v1, v4, v1 915; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v6 916; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2 917; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2 918; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v7 919; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3 920; GFX6-NEXT: v_lshrrev_b32_e32 v3, v4, v3 921; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 922; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 923; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3 924; GFX6-NEXT: v_or_b32_e32 v1, v2, v1 925; GFX6-NEXT: s_setpc_b64 s[30:31] 926; 927; GFX8-LABEL: v_lshr_v4i16: 928; GFX8: ; %bb.0: 929; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 930; GFX8-NEXT: v_lshrrev_b16_e32 v4, v2, v0 931; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 932; GFX8-NEXT: v_lshrrev_b16_e32 v2, v3, v1 933; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 934; GFX8-NEXT: v_or_b32_e32 v0, v4, v0 935; GFX8-NEXT: v_or_b32_e32 v1, v2, v1 936; GFX8-NEXT: s_setpc_b64 s[30:31] 937; 938; GFX9-LABEL: v_lshr_v4i16: 939; GFX9: ; %bb.0: 940; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 941; GFX9-NEXT: v_pk_lshrrev_b16 v0, v2, v0 942; GFX9-NEXT: v_pk_lshrrev_b16 v1, v3, v1 943; GFX9-NEXT: s_setpc_b64 s[30:31] 944; 945; GFX10PLUS-LABEL: v_lshr_v4i16: 946; GFX10PLUS: ; %bb.0: 947; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 948; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 949; GFX10PLUS-NEXT: v_pk_lshrrev_b16 v0, v2, v0 950; GFX10PLUS-NEXT: v_pk_lshrrev_b16 v1, v3, v1 951; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 952 %result = lshr <4 x i16> %value, %amount 953 %cast = bitcast <4 x i16> %result to <2 x float> 954 ret <2 x float> %cast 955} 956 957define amdgpu_ps <2 x i32> @s_lshr_v4i16(<4 x i16> inreg %value, <4 x i16> inreg %amount) { 958; GFX6-LABEL: s_lshr_v4i16: 959; GFX6: ; %bb.0: 960; GFX6-NEXT: s_and_b32 s1, s1, 0xffff 961; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 962; GFX6-NEXT: s_lshr_b32 s1, s1, s5 963; GFX6-NEXT: s_and_b32 s3, s3, 0xffff 964; GFX6-NEXT: s_lshr_b32 s0, s0, s4 965; GFX6-NEXT: s_and_b32 s2, s2, 0xffff 966; GFX6-NEXT: s_lshr_b32 s3, s3, s7 967; GFX6-NEXT: s_lshl_b32 s1, s1, 16 968; GFX6-NEXT: s_lshr_b32 s2, s2, s6 969; GFX6-NEXT: s_or_b32 s0, s0, s1 970; GFX6-NEXT: s_lshl_b32 s1, s3, 16 971; GFX6-NEXT: s_or_b32 s1, s2, s1 972; GFX6-NEXT: ; return to shader part epilog 973; 974; GFX8-LABEL: s_lshr_v4i16: 975; GFX8: ; %bb.0: 976; GFX8-NEXT: s_lshr_b32 s4, s0, 16 977; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 978; GFX8-NEXT: s_lshr_b32 s6, s2, 16 979; GFX8-NEXT: s_lshr_b32 s5, s1, 16 980; GFX8-NEXT: s_and_b32 s1, s1, 0xffff 981; GFX8-NEXT: s_lshr_b32 s7, s3, 16 982; GFX8-NEXT: s_lshr_b32 s0, s0, s2 983; GFX8-NEXT: s_lshr_b32 s2, s4, s6 984; GFX8-NEXT: s_lshr_b32 s1, s1, s3 985; GFX8-NEXT: s_lshr_b32 s3, s5, s7 986; GFX8-NEXT: s_lshl_b32 s2, s2, 16 987; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 988; GFX8-NEXT: s_or_b32 s0, s2, s0 989; GFX8-NEXT: s_lshl_b32 s2, s3, 16 990; GFX8-NEXT: s_and_b32 s1, s1, 0xffff 991; GFX8-NEXT: s_or_b32 s1, s2, s1 992; GFX8-NEXT: ; return to shader part epilog 993; 994; GFX9-LABEL: s_lshr_v4i16: 995; GFX9: ; %bb.0: 996; GFX9-NEXT: s_lshr_b32 s4, s0, 16 997; GFX9-NEXT: s_and_b32 s0, s0, 0xffff 998; GFX9-NEXT: s_lshr_b32 s5, s2, 16 999; GFX9-NEXT: s_lshr_b32 s0, s0, s2 1000; GFX9-NEXT: s_lshr_b32 s2, s4, s5 1001; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2 1002; GFX9-NEXT: s_lshr_b32 s2, s1, 16 1003; GFX9-NEXT: s_and_b32 s1, s1, 0xffff 1004; GFX9-NEXT: s_lshr_b32 s4, s3, 16 1005; GFX9-NEXT: s_lshr_b32 s1, s1, s3 1006; GFX9-NEXT: s_lshr_b32 s2, s2, s4 1007; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2 1008; GFX9-NEXT: ; return to shader part epilog 1009; 1010; GFX10PLUS-LABEL: s_lshr_v4i16: 1011; GFX10PLUS: ; %bb.0: 1012; GFX10PLUS-NEXT: s_lshr_b32 s4, s0, 16 1013; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xffff 1014; GFX10PLUS-NEXT: s_lshr_b32 s5, s2, 16 1015; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s2 1016; GFX10PLUS-NEXT: s_lshr_b32 s2, s4, s5 1017; GFX10PLUS-NEXT: s_lshr_b32 s4, s1, 16 1018; GFX10PLUS-NEXT: s_and_b32 s1, s1, 0xffff 1019; GFX10PLUS-NEXT: s_lshr_b32 s5, s3, 16 1020; GFX10PLUS-NEXT: s_lshr_b32 s1, s1, s3 1021; GFX10PLUS-NEXT: s_lshr_b32 s3, s4, s5 1022; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s0, s2 1023; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s1, s1, s3 1024; GFX10PLUS-NEXT: ; return to shader part epilog 1025 %result = lshr <4 x i16> %value, %amount 1026 %cast = bitcast <4 x i16> %result to <2 x i32> 1027 ret <2 x i32> %cast 1028} 1029 1030; FIXME 1031; define <5 x i16> @v_lshr_v5i16(<5 x i16> %value, <5 x i16> %amount) { 1032; %result = lshr <5 x i16> %value, %amount 1033; ret <5 x i16> %result 1034; } 1035 1036; define amdgpu_ps <5 x i16> @s_lshr_v5i16(<5 x i16> inreg %value, <5 x i16> inreg %amount) { 1037; %result = lshr <5 x i16> %value, %amount 1038; ret <5 x i16> %result 1039; } 1040 1041; define <3 x float> @v_lshr_v6i16(<6 x i16> %value, <6 x i16> %amount) { 1042; %result = lshr <6 x i16> %value, %amount 1043; %cast = bitcast <6 x i16> %result to <3 x float> 1044; ret <3 x float> %cast 1045; } 1046 1047; define amdgpu_ps <3 x i32> @s_lshr_v6i16(<6 x i16> inreg %value, <6 x i16> inreg %amount) { 1048; %result = lshr <6 x i16> %value, %amount 1049; %cast = bitcast <6 x i16> %result to <3 x i32> 1050; ret <3 x i32> %cast 1051; } 1052 1053define <4 x float> @v_lshr_v8i16(<8 x i16> %value, <8 x i16> %amount) { 1054; GFX6-LABEL: v_lshr_v8i16: 1055; GFX6: ; %bb.0: 1056; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1057; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v8 1058; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 1059; GFX6-NEXT: v_lshrrev_b32_e32 v0, v8, v0 1060; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v9 1061; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 1062; GFX6-NEXT: v_lshrrev_b32_e32 v1, v8, v1 1063; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v10 1064; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2 1065; GFX6-NEXT: v_lshrrev_b32_e32 v2, v8, v2 1066; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v11 1067; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3 1068; GFX6-NEXT: v_lshrrev_b32_e32 v3, v8, v3 1069; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v12 1070; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4 1071; GFX6-NEXT: v_lshrrev_b32_e32 v4, v8, v4 1072; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v13 1073; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v5 1074; GFX6-NEXT: v_lshrrev_b32_e32 v5, v8, v5 1075; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v14 1076; GFX6-NEXT: v_and_b32_e32 v6, 0xffff, v6 1077; GFX6-NEXT: v_lshrrev_b32_e32 v6, v8, v6 1078; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v15 1079; GFX6-NEXT: v_and_b32_e32 v7, 0xffff, v7 1080; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1081; GFX6-NEXT: v_lshrrev_b32_e32 v7, v8, v7 1082; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 1083; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3 1084; GFX6-NEXT: v_or_b32_e32 v1, v2, v1 1085; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v5 1086; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v7 1087; GFX6-NEXT: v_or_b32_e32 v2, v4, v2 1088; GFX6-NEXT: v_or_b32_e32 v3, v6, v3 1089; GFX6-NEXT: s_setpc_b64 s[30:31] 1090; 1091; GFX8-LABEL: v_lshr_v8i16: 1092; GFX8: ; %bb.0: 1093; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1094; GFX8-NEXT: v_lshrrev_b16_e32 v8, v4, v0 1095; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1096; GFX8-NEXT: v_lshrrev_b16_e32 v4, v5, v1 1097; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1098; GFX8-NEXT: v_or_b32_e32 v1, v4, v1 1099; GFX8-NEXT: v_lshrrev_b16_e32 v4, v6, v2 1100; GFX8-NEXT: v_lshrrev_b16_sdwa v2, v6, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1101; GFX8-NEXT: v_or_b32_e32 v2, v4, v2 1102; GFX8-NEXT: v_lshrrev_b16_e32 v4, v7, v3 1103; GFX8-NEXT: v_lshrrev_b16_sdwa v3, v7, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1104; GFX8-NEXT: v_or_b32_e32 v0, v8, v0 1105; GFX8-NEXT: v_or_b32_e32 v3, v4, v3 1106; GFX8-NEXT: s_setpc_b64 s[30:31] 1107; 1108; GFX9-LABEL: v_lshr_v8i16: 1109; GFX9: ; %bb.0: 1110; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1111; GFX9-NEXT: v_pk_lshrrev_b16 v0, v4, v0 1112; GFX9-NEXT: v_pk_lshrrev_b16 v1, v5, v1 1113; GFX9-NEXT: v_pk_lshrrev_b16 v2, v6, v2 1114; GFX9-NEXT: v_pk_lshrrev_b16 v3, v7, v3 1115; GFX9-NEXT: s_setpc_b64 s[30:31] 1116; 1117; GFX10PLUS-LABEL: v_lshr_v8i16: 1118; GFX10PLUS: ; %bb.0: 1119; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1120; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 1121; GFX10PLUS-NEXT: v_pk_lshrrev_b16 v0, v4, v0 1122; GFX10PLUS-NEXT: v_pk_lshrrev_b16 v1, v5, v1 1123; GFX10PLUS-NEXT: v_pk_lshrrev_b16 v2, v6, v2 1124; GFX10PLUS-NEXT: v_pk_lshrrev_b16 v3, v7, v3 1125; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 1126 %result = lshr <8 x i16> %value, %amount 1127 %cast = bitcast <8 x i16> %result to <4 x float> 1128 ret <4 x float> %cast 1129} 1130 1131define amdgpu_ps <4 x i32> @s_lshr_v8i16(<8 x i16> inreg %value, <8 x i16> inreg %amount) { 1132; GFX6-LABEL: s_lshr_v8i16: 1133; GFX6: ; %bb.0: 1134; GFX6-NEXT: s_and_b32 s1, s1, 0xffff 1135; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 1136; GFX6-NEXT: s_lshr_b32 s1, s1, s9 1137; GFX6-NEXT: s_and_b32 s3, s3, 0xffff 1138; GFX6-NEXT: s_lshr_b32 s0, s0, s8 1139; GFX6-NEXT: s_and_b32 s2, s2, 0xffff 1140; GFX6-NEXT: s_lshr_b32 s3, s3, s11 1141; GFX6-NEXT: s_and_b32 s5, s5, 0xffff 1142; GFX6-NEXT: s_and_b32 s7, s7, 0xffff 1143; GFX6-NEXT: s_lshl_b32 s1, s1, 16 1144; GFX6-NEXT: s_lshr_b32 s2, s2, s10 1145; GFX6-NEXT: s_and_b32 s4, s4, 0xffff 1146; GFX6-NEXT: s_lshr_b32 s5, s5, s13 1147; GFX6-NEXT: s_and_b32 s6, s6, 0xffff 1148; GFX6-NEXT: s_lshr_b32 s7, s7, s15 1149; GFX6-NEXT: s_or_b32 s0, s0, s1 1150; GFX6-NEXT: s_lshl_b32 s1, s3, 16 1151; GFX6-NEXT: s_lshr_b32 s4, s4, s12 1152; GFX6-NEXT: s_lshr_b32 s6, s6, s14 1153; GFX6-NEXT: s_or_b32 s1, s2, s1 1154; GFX6-NEXT: s_lshl_b32 s2, s5, 16 1155; GFX6-NEXT: s_lshl_b32 s3, s7, 16 1156; GFX6-NEXT: s_or_b32 s2, s4, s2 1157; GFX6-NEXT: s_or_b32 s3, s6, s3 1158; GFX6-NEXT: ; return to shader part epilog 1159; 1160; GFX8-LABEL: s_lshr_v8i16: 1161; GFX8: ; %bb.0: 1162; GFX8-NEXT: s_lshr_b32 s8, s0, 16 1163; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 1164; GFX8-NEXT: s_lshr_b32 s12, s4, 16 1165; GFX8-NEXT: s_lshr_b32 s9, s1, 16 1166; GFX8-NEXT: s_and_b32 s1, s1, 0xffff 1167; GFX8-NEXT: s_lshr_b32 s13, s5, 16 1168; GFX8-NEXT: s_lshr_b32 s0, s0, s4 1169; GFX8-NEXT: s_lshr_b32 s4, s8, s12 1170; GFX8-NEXT: s_lshr_b32 s10, s2, 16 1171; GFX8-NEXT: s_and_b32 s2, s2, 0xffff 1172; GFX8-NEXT: s_lshr_b32 s14, s6, 16 1173; GFX8-NEXT: s_lshr_b32 s1, s1, s5 1174; GFX8-NEXT: s_lshr_b32 s5, s9, s13 1175; GFX8-NEXT: s_lshl_b32 s4, s4, 16 1176; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 1177; GFX8-NEXT: s_lshr_b32 s11, s3, 16 1178; GFX8-NEXT: s_and_b32 s3, s3, 0xffff 1179; GFX8-NEXT: s_lshr_b32 s15, s7, 16 1180; GFX8-NEXT: s_lshr_b32 s2, s2, s6 1181; GFX8-NEXT: s_lshr_b32 s6, s10, s14 1182; GFX8-NEXT: s_or_b32 s0, s4, s0 1183; GFX8-NEXT: s_lshl_b32 s4, s5, 16 1184; GFX8-NEXT: s_and_b32 s1, s1, 0xffff 1185; GFX8-NEXT: s_lshr_b32 s3, s3, s7 1186; GFX8-NEXT: s_lshr_b32 s7, s11, s15 1187; GFX8-NEXT: s_or_b32 s1, s4, s1 1188; GFX8-NEXT: s_lshl_b32 s4, s6, 16 1189; GFX8-NEXT: s_and_b32 s2, s2, 0xffff 1190; GFX8-NEXT: s_or_b32 s2, s4, s2 1191; GFX8-NEXT: s_lshl_b32 s4, s7, 16 1192; GFX8-NEXT: s_and_b32 s3, s3, 0xffff 1193; GFX8-NEXT: s_or_b32 s3, s4, s3 1194; GFX8-NEXT: ; return to shader part epilog 1195; 1196; GFX9-LABEL: s_lshr_v8i16: 1197; GFX9: ; %bb.0: 1198; GFX9-NEXT: s_lshr_b32 s8, s0, 16 1199; GFX9-NEXT: s_and_b32 s0, s0, 0xffff 1200; GFX9-NEXT: s_lshr_b32 s9, s4, 16 1201; GFX9-NEXT: s_lshr_b32 s0, s0, s4 1202; GFX9-NEXT: s_lshr_b32 s4, s8, s9 1203; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s4 1204; GFX9-NEXT: s_lshr_b32 s4, s1, 16 1205; GFX9-NEXT: s_and_b32 s1, s1, 0xffff 1206; GFX9-NEXT: s_lshr_b32 s8, s5, 16 1207; GFX9-NEXT: s_lshr_b32 s1, s1, s5 1208; GFX9-NEXT: s_lshr_b32 s4, s4, s8 1209; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4 1210; GFX9-NEXT: s_lshr_b32 s4, s2, 16 1211; GFX9-NEXT: s_and_b32 s2, s2, 0xffff 1212; GFX9-NEXT: s_lshr_b32 s5, s6, 16 1213; GFX9-NEXT: s_lshr_b32 s2, s2, s6 1214; GFX9-NEXT: s_lshr_b32 s4, s4, s5 1215; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4 1216; GFX9-NEXT: s_lshr_b32 s4, s3, 16 1217; GFX9-NEXT: s_and_b32 s3, s3, 0xffff 1218; GFX9-NEXT: s_lshr_b32 s5, s7, 16 1219; GFX9-NEXT: s_lshr_b32 s3, s3, s7 1220; GFX9-NEXT: s_lshr_b32 s4, s4, s5 1221; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4 1222; GFX9-NEXT: ; return to shader part epilog 1223; 1224; GFX10PLUS-LABEL: s_lshr_v8i16: 1225; GFX10PLUS: ; %bb.0: 1226; GFX10PLUS-NEXT: s_lshr_b32 s8, s0, 16 1227; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xffff 1228; GFX10PLUS-NEXT: s_lshr_b32 s9, s4, 16 1229; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s4 1230; GFX10PLUS-NEXT: s_lshr_b32 s4, s8, s9 1231; GFX10PLUS-NEXT: s_lshr_b32 s8, s1, 16 1232; GFX10PLUS-NEXT: s_and_b32 s1, s1, 0xffff 1233; GFX10PLUS-NEXT: s_lshr_b32 s9, s5, 16 1234; GFX10PLUS-NEXT: s_lshr_b32 s1, s1, s5 1235; GFX10PLUS-NEXT: s_lshr_b32 s5, s8, s9 1236; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s0, s4 1237; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s1, s1, s5 1238; GFX10PLUS-NEXT: s_lshr_b32 s4, s2, 16 1239; GFX10PLUS-NEXT: s_and_b32 s2, s2, 0xffff 1240; GFX10PLUS-NEXT: s_lshr_b32 s5, s6, 16 1241; GFX10PLUS-NEXT: s_lshr_b32 s2, s2, s6 1242; GFX10PLUS-NEXT: s_lshr_b32 s4, s4, s5 1243; GFX10PLUS-NEXT: s_lshr_b32 s5, s3, 16 1244; GFX10PLUS-NEXT: s_and_b32 s3, s3, 0xffff 1245; GFX10PLUS-NEXT: s_lshr_b32 s6, s7, 16 1246; GFX10PLUS-NEXT: s_lshr_b32 s3, s3, s7 1247; GFX10PLUS-NEXT: s_lshr_b32 s5, s5, s6 1248; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s2, s2, s4 1249; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s3, s3, s5 1250; GFX10PLUS-NEXT: ; return to shader part epilog 1251 %result = lshr <8 x i16> %value, %amount 1252 %cast = bitcast <8 x i16> %result to <4 x i32> 1253 ret <4 x i32> %cast 1254} 1255 1256define i64 @v_lshr_i64(i64 %value, i64 %amount) { 1257; GFX6-LABEL: v_lshr_i64: 1258; GFX6: ; %bb.0: 1259; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1260; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], v2 1261; GFX6-NEXT: s_setpc_b64 s[30:31] 1262; 1263; GFX8-LABEL: v_lshr_i64: 1264; GFX8: ; %bb.0: 1265; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1266; GFX8-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 1267; GFX8-NEXT: s_setpc_b64 s[30:31] 1268; 1269; GFX9-LABEL: v_lshr_i64: 1270; GFX9: ; %bb.0: 1271; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1272; GFX9-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 1273; GFX9-NEXT: s_setpc_b64 s[30:31] 1274; 1275; GFX10PLUS-LABEL: v_lshr_i64: 1276; GFX10PLUS: ; %bb.0: 1277; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1278; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 1279; GFX10PLUS-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 1280; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 1281 %result = lshr i64 %value, %amount 1282 ret i64 %result 1283} 1284 1285define i64 @v_lshr_i64_63(i64 %value) { 1286; GCN-LABEL: v_lshr_i64_63: 1287; GCN: ; %bb.0: 1288; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1289; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v1 1290; GCN-NEXT: v_mov_b32_e32 v1, 0 1291; GCN-NEXT: s_setpc_b64 s[30:31] 1292; 1293; GFX10PLUS-LABEL: v_lshr_i64_63: 1294; GFX10PLUS: ; %bb.0: 1295; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1296; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 1297; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, 31, v1 1298; GFX10PLUS-NEXT: v_mov_b32_e32 v1, 0 1299; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 1300 %result = lshr i64 %value, 63 1301 ret i64 %result 1302} 1303 1304define i64 @v_lshr_i64_33(i64 %value) { 1305; GCN-LABEL: v_lshr_i64_33: 1306; GCN: ; %bb.0: 1307; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1308; GCN-NEXT: v_lshrrev_b32_e32 v0, 1, v1 1309; GCN-NEXT: v_mov_b32_e32 v1, 0 1310; GCN-NEXT: s_setpc_b64 s[30:31] 1311; 1312; GFX10PLUS-LABEL: v_lshr_i64_33: 1313; GFX10PLUS: ; %bb.0: 1314; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1315; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 1316; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, 1, v1 1317; GFX10PLUS-NEXT: v_mov_b32_e32 v1, 0 1318; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 1319 %result = lshr i64 %value, 33 1320 ret i64 %result 1321} 1322 1323define i64 @v_lshr_i64_32(i64 %value) { 1324; GCN-LABEL: v_lshr_i64_32: 1325; GCN: ; %bb.0: 1326; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1327; GCN-NEXT: v_mov_b32_e32 v0, v1 1328; GCN-NEXT: v_mov_b32_e32 v1, 0 1329; GCN-NEXT: s_setpc_b64 s[30:31] 1330; 1331; GFX10-LABEL: v_lshr_i64_32: 1332; GFX10: ; %bb.0: 1333; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1334; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1335; GFX10-NEXT: v_mov_b32_e32 v0, v1 1336; GFX10-NEXT: v_mov_b32_e32 v1, 0 1337; GFX10-NEXT: s_setpc_b64 s[30:31] 1338; 1339; GFX11-LABEL: v_lshr_i64_32: 1340; GFX11: ; %bb.0: 1341; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1342; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 1343; GFX11-NEXT: v_dual_mov_b32 v0, v1 :: v_dual_mov_b32 v1, 0 1344; GFX11-NEXT: s_setpc_b64 s[30:31] 1345 %result = lshr i64 %value, 32 1346 ret i64 %result 1347} 1348 1349define i64 @v_lshr_i64_31(i64 %value) { 1350; GFX6-LABEL: v_lshr_i64_31: 1351; GFX6: ; %bb.0: 1352; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1353; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 31 1354; GFX6-NEXT: s_setpc_b64 s[30:31] 1355; 1356; GFX8-LABEL: v_lshr_i64_31: 1357; GFX8: ; %bb.0: 1358; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1359; GFX8-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1360; GFX8-NEXT: s_setpc_b64 s[30:31] 1361; 1362; GFX9-LABEL: v_lshr_i64_31: 1363; GFX9: ; %bb.0: 1364; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1365; GFX9-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1366; GFX9-NEXT: s_setpc_b64 s[30:31] 1367; 1368; GFX10PLUS-LABEL: v_lshr_i64_31: 1369; GFX10PLUS: ; %bb.0: 1370; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1371; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 1372; GFX10PLUS-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1373; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 1374 %result = lshr i64 %value, 31 1375 ret i64 %result 1376} 1377 1378define amdgpu_ps i64 @s_lshr_i64(i64 inreg %value, i64 inreg %amount) { 1379; GCN-LABEL: s_lshr_i64: 1380; GCN: ; %bb.0: 1381; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], s2 1382; GCN-NEXT: ; return to shader part epilog 1383; 1384; GFX10PLUS-LABEL: s_lshr_i64: 1385; GFX10PLUS: ; %bb.0: 1386; GFX10PLUS-NEXT: s_lshr_b64 s[0:1], s[0:1], s2 1387; GFX10PLUS-NEXT: ; return to shader part epilog 1388 %result = lshr i64 %value, %amount 1389 ret i64 %result 1390} 1391 1392define amdgpu_ps i64 @s_lshr_i64_63(i64 inreg %value) { 1393; GCN-LABEL: s_lshr_i64_63: 1394; GCN: ; %bb.0: 1395; GCN-NEXT: s_lshr_b32 s0, s1, 31 1396; GCN-NEXT: s_mov_b32 s1, 0 1397; GCN-NEXT: ; return to shader part epilog 1398; 1399; GFX10PLUS-LABEL: s_lshr_i64_63: 1400; GFX10PLUS: ; %bb.0: 1401; GFX10PLUS-NEXT: s_lshr_b32 s0, s1, 31 1402; GFX10PLUS-NEXT: s_mov_b32 s1, 0 1403; GFX10PLUS-NEXT: ; return to shader part epilog 1404 %result = lshr i64 %value, 63 1405 ret i64 %result 1406} 1407 1408define amdgpu_ps i64 @s_lshr_i64_33(i64 inreg %value) { 1409; GCN-LABEL: s_lshr_i64_33: 1410; GCN: ; %bb.0: 1411; GCN-NEXT: s_lshr_b32 s0, s1, 1 1412; GCN-NEXT: s_mov_b32 s1, 0 1413; GCN-NEXT: ; return to shader part epilog 1414; 1415; GFX10PLUS-LABEL: s_lshr_i64_33: 1416; GFX10PLUS: ; %bb.0: 1417; GFX10PLUS-NEXT: s_lshr_b32 s0, s1, 1 1418; GFX10PLUS-NEXT: s_mov_b32 s1, 0 1419; GFX10PLUS-NEXT: ; return to shader part epilog 1420 %result = lshr i64 %value, 33 1421 ret i64 %result 1422} 1423 1424define amdgpu_ps i64 @s_lshr_i64_32(i64 inreg %value) { 1425; GCN-LABEL: s_lshr_i64_32: 1426; GCN: ; %bb.0: 1427; GCN-NEXT: s_mov_b32 s0, s1 1428; GCN-NEXT: s_mov_b32 s1, 0 1429; GCN-NEXT: ; return to shader part epilog 1430; 1431; GFX10PLUS-LABEL: s_lshr_i64_32: 1432; GFX10PLUS: ; %bb.0: 1433; GFX10PLUS-NEXT: s_mov_b32 s0, s1 1434; GFX10PLUS-NEXT: s_mov_b32 s1, 0 1435; GFX10PLUS-NEXT: ; return to shader part epilog 1436 %result = lshr i64 %value, 32 1437 ret i64 %result 1438} 1439 1440define amdgpu_ps i64 @s_lshr_i64_31(i64 inreg %value) { 1441; GCN-LABEL: s_lshr_i64_31: 1442; GCN: ; %bb.0: 1443; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], 31 1444; GCN-NEXT: ; return to shader part epilog 1445; 1446; GFX10PLUS-LABEL: s_lshr_i64_31: 1447; GFX10PLUS: ; %bb.0: 1448; GFX10PLUS-NEXT: s_lshr_b64 s[0:1], s[0:1], 31 1449; GFX10PLUS-NEXT: ; return to shader part epilog 1450 %result = lshr i64 %value, 31 1451 ret i64 %result 1452} 1453 1454define amdgpu_ps <2 x float> @lshr_i64_sv(i64 inreg %value, i64 %amount) { 1455; GFX6-LABEL: lshr_i64_sv: 1456; GFX6: ; %bb.0: 1457; GFX6-NEXT: v_lshr_b64 v[0:1], s[0:1], v0 1458; GFX6-NEXT: ; return to shader part epilog 1459; 1460; GFX8-LABEL: lshr_i64_sv: 1461; GFX8: ; %bb.0: 1462; GFX8-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1] 1463; GFX8-NEXT: ; return to shader part epilog 1464; 1465; GFX9-LABEL: lshr_i64_sv: 1466; GFX9: ; %bb.0: 1467; GFX9-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1] 1468; GFX9-NEXT: ; return to shader part epilog 1469; 1470; GFX10PLUS-LABEL: lshr_i64_sv: 1471; GFX10PLUS: ; %bb.0: 1472; GFX10PLUS-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1] 1473; GFX10PLUS-NEXT: ; return to shader part epilog 1474 %result = lshr i64 %value, %amount 1475 %cast = bitcast i64 %result to <2 x float> 1476 ret <2 x float> %cast 1477} 1478 1479define amdgpu_ps <2 x float> @lshr_i64_vs(i64 %value, i64 inreg %amount) { 1480; GFX6-LABEL: lshr_i64_vs: 1481; GFX6: ; %bb.0: 1482; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], s0 1483; GFX6-NEXT: ; return to shader part epilog 1484; 1485; GFX8-LABEL: lshr_i64_vs: 1486; GFX8: ; %bb.0: 1487; GFX8-NEXT: v_lshrrev_b64 v[0:1], s0, v[0:1] 1488; GFX8-NEXT: ; return to shader part epilog 1489; 1490; GFX9-LABEL: lshr_i64_vs: 1491; GFX9: ; %bb.0: 1492; GFX9-NEXT: v_lshrrev_b64 v[0:1], s0, v[0:1] 1493; GFX9-NEXT: ; return to shader part epilog 1494; 1495; GFX10PLUS-LABEL: lshr_i64_vs: 1496; GFX10PLUS: ; %bb.0: 1497; GFX10PLUS-NEXT: v_lshrrev_b64 v[0:1], s0, v[0:1] 1498; GFX10PLUS-NEXT: ; return to shader part epilog 1499 %result = lshr i64 %value, %amount 1500 %cast = bitcast i64 %result to <2 x float> 1501 ret <2 x float> %cast 1502} 1503 1504define <2 x i64> @v_lshr_v2i64(<2 x i64> %value, <2 x i64> %amount) { 1505; GFX6-LABEL: v_lshr_v2i64: 1506; GFX6: ; %bb.0: 1507; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1508; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], v4 1509; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], v6 1510; GFX6-NEXT: s_setpc_b64 s[30:31] 1511; 1512; GFX8-LABEL: v_lshr_v2i64: 1513; GFX8: ; %bb.0: 1514; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1515; GFX8-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1] 1516; GFX8-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3] 1517; GFX8-NEXT: s_setpc_b64 s[30:31] 1518; 1519; GFX9-LABEL: v_lshr_v2i64: 1520; GFX9: ; %bb.0: 1521; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1522; GFX9-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1] 1523; GFX9-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3] 1524; GFX9-NEXT: s_setpc_b64 s[30:31] 1525; 1526; GFX10PLUS-LABEL: v_lshr_v2i64: 1527; GFX10PLUS: ; %bb.0: 1528; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1529; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 1530; GFX10PLUS-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1] 1531; GFX10PLUS-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3] 1532; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 1533 %result = lshr <2 x i64> %value, %amount 1534 ret <2 x i64> %result 1535} 1536 1537define <2 x i64> @v_lshr_v2i64_31(<2 x i64> %value) { 1538; GFX6-LABEL: v_lshr_v2i64_31: 1539; GFX6: ; %bb.0: 1540; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1541; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 31 1542; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], 31 1543; GFX6-NEXT: s_setpc_b64 s[30:31] 1544; 1545; GFX8-LABEL: v_lshr_v2i64_31: 1546; GFX8: ; %bb.0: 1547; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1548; GFX8-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1549; GFX8-NEXT: v_lshrrev_b64 v[2:3], 31, v[2:3] 1550; GFX8-NEXT: s_setpc_b64 s[30:31] 1551; 1552; GFX9-LABEL: v_lshr_v2i64_31: 1553; GFX9: ; %bb.0: 1554; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1555; GFX9-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1556; GFX9-NEXT: v_lshrrev_b64 v[2:3], 31, v[2:3] 1557; GFX9-NEXT: s_setpc_b64 s[30:31] 1558; 1559; GFX10PLUS-LABEL: v_lshr_v2i64_31: 1560; GFX10PLUS: ; %bb.0: 1561; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1562; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 1563; GFX10PLUS-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1564; GFX10PLUS-NEXT: v_lshrrev_b64 v[2:3], 31, v[2:3] 1565; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 1566 %result = lshr <2 x i64> %value, <i64 31, i64 31> 1567 ret <2 x i64> %result 1568} 1569 1570define amdgpu_ps <2 x i64> @s_lshr_v2i64(<2 x i64> inreg %value, <2 x i64> inreg %amount) { 1571; GCN-LABEL: s_lshr_v2i64: 1572; GCN: ; %bb.0: 1573; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], s4 1574; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], s6 1575; GCN-NEXT: ; return to shader part epilog 1576; 1577; GFX10PLUS-LABEL: s_lshr_v2i64: 1578; GFX10PLUS: ; %bb.0: 1579; GFX10PLUS-NEXT: s_lshr_b64 s[0:1], s[0:1], s4 1580; GFX10PLUS-NEXT: s_lshr_b64 s[2:3], s[2:3], s6 1581; GFX10PLUS-NEXT: ; return to shader part epilog 1582 %result = lshr <2 x i64> %value, %amount 1583 ret <2 x i64> %result 1584} 1585 1586define i65 @v_lshr_i65(i65 %value, i65 %amount) { 1587; GFX6-LABEL: v_lshr_i65: 1588; GFX6: ; %bb.0: 1589; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1590; GFX6-NEXT: v_and_b32_e32 v4, 1, v2 1591; GFX6-NEXT: v_mov_b32_e32 v5, 0 1592; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 64, v3 1593; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 64, v3 1594; GFX6-NEXT: v_lshr_b64 v[6:7], v[0:1], v3 1595; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], v8 1596; GFX6-NEXT: v_lshr_b64 v[10:11], v[4:5], v3 1597; GFX6-NEXT: v_lshr_b64 v[4:5], v[4:5], v2 1598; GFX6-NEXT: v_or_b32_e32 v6, v6, v8 1599; GFX6-NEXT: v_or_b32_e32 v7, v7, v9 1600; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3 1601; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc 1602; GFX6-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc 1603; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3 1604; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5] 1605; GFX6-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5] 1606; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc 1607; GFX6-NEXT: s_setpc_b64 s[30:31] 1608; 1609; GFX8-LABEL: v_lshr_i65: 1610; GFX8: ; %bb.0: 1611; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1612; GFX8-NEXT: v_and_b32_e32 v4, 1, v2 1613; GFX8-NEXT: v_mov_b32_e32 v5, 0 1614; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 64, v3 1615; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 64, v3 1616; GFX8-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1] 1617; GFX8-NEXT: v_lshlrev_b64 v[8:9], v8, v[4:5] 1618; GFX8-NEXT: v_lshrrev_b64 v[10:11], v3, v[4:5] 1619; GFX8-NEXT: v_lshrrev_b64 v[4:5], v2, v[4:5] 1620; GFX8-NEXT: v_or_b32_e32 v6, v6, v8 1621; GFX8-NEXT: v_or_b32_e32 v7, v7, v9 1622; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3 1623; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc 1624; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc 1625; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3 1626; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5] 1627; GFX8-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5] 1628; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc 1629; GFX8-NEXT: s_setpc_b64 s[30:31] 1630; 1631; GFX9-LABEL: v_lshr_i65: 1632; GFX9: ; %bb.0: 1633; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1634; GFX9-NEXT: v_and_b32_e32 v4, 1, v2 1635; GFX9-NEXT: v_mov_b32_e32 v5, 0 1636; GFX9-NEXT: v_sub_u32_e32 v8, 64, v3 1637; GFX9-NEXT: v_subrev_u32_e32 v2, 64, v3 1638; GFX9-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1] 1639; GFX9-NEXT: v_lshlrev_b64 v[8:9], v8, v[4:5] 1640; GFX9-NEXT: v_lshrrev_b64 v[10:11], v3, v[4:5] 1641; GFX9-NEXT: v_lshrrev_b64 v[4:5], v2, v[4:5] 1642; GFX9-NEXT: v_or_b32_e32 v6, v6, v8 1643; GFX9-NEXT: v_or_b32_e32 v7, v7, v9 1644; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3 1645; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc 1646; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc 1647; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3 1648; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5] 1649; GFX9-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5] 1650; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc 1651; GFX9-NEXT: s_setpc_b64 s[30:31] 1652; 1653; GFX10-LABEL: v_lshr_i65: 1654; GFX10: ; %bb.0: 1655; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1656; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1657; GFX10-NEXT: v_mov_b32_e32 v5, 0 1658; GFX10-NEXT: v_and_b32_e32 v4, 1, v2 1659; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v3 1660; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 64, v3 1661; GFX10-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1] 1662; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v3 1663; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v3 1664; GFX10-NEXT: v_lshlrev_b64 v[8:9], v2, v[4:5] 1665; GFX10-NEXT: v_lshrrev_b64 v[10:11], v10, v[4:5] 1666; GFX10-NEXT: v_lshrrev_b64 v[4:5], v3, v[4:5] 1667; GFX10-NEXT: v_or_b32_e32 v2, v6, v8 1668; GFX10-NEXT: v_or_b32_e32 v6, v7, v9 1669; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo 1670; GFX10-NEXT: v_cndmask_b32_e32 v5, v11, v6, vcc_lo 1671; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v0, s4 1672; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s4 1673; GFX10-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc_lo 1674; GFX10-NEXT: s_setpc_b64 s[30:31] 1675; 1676; GFX11-LABEL: v_lshr_i65: 1677; GFX11: ; %bb.0: 1678; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1679; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 1680; GFX11-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v4, 1, v2 1681; GFX11-NEXT: v_sub_nc_u32_e32 v2, 64, v3 1682; GFX11-NEXT: v_subrev_nc_u32_e32 v10, 64, v3 1683; GFX11-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1] 1684; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v3 1685; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v3 1686; GFX11-NEXT: v_lshlrev_b64 v[8:9], v2, v[4:5] 1687; GFX11-NEXT: v_lshrrev_b64 v[10:11], v10, v[4:5] 1688; GFX11-NEXT: v_lshrrev_b64 v[4:5], v3, v[4:5] 1689; GFX11-NEXT: v_or_b32_e32 v2, v6, v8 1690; GFX11-NEXT: v_or_b32_e32 v6, v7, v9 1691; GFX11-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo 1692; GFX11-NEXT: v_cndmask_b32_e32 v5, v11, v6, vcc_lo 1693; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, v0, s0 1694; GFX11-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc_lo 1695; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0 1696; GFX11-NEXT: s_setpc_b64 s[30:31] 1697 %result = lshr i65 %value, %amount 1698 ret i65 %result 1699} 1700 1701define i65 @v_lshr_i65_33(i65 %value) { 1702; GFX6-LABEL: v_lshr_i65_33: 1703; GFX6: ; %bb.0: 1704; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1705; GFX6-NEXT: v_mov_b32_e32 v3, v1 1706; GFX6-NEXT: v_and_b32_e32 v0, 1, v2 1707; GFX6-NEXT: v_mov_b32_e32 v1, 0 1708; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 31 1709; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v3 1710; GFX6-NEXT: v_or_b32_e32 v0, v2, v0 1711; GFX6-NEXT: v_mov_b32_e32 v2, 0 1712; GFX6-NEXT: s_setpc_b64 s[30:31] 1713; 1714; GFX8-LABEL: v_lshr_i65_33: 1715; GFX8: ; %bb.0: 1716; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1717; GFX8-NEXT: v_mov_b32_e32 v3, v1 1718; GFX8-NEXT: v_and_b32_e32 v0, 1, v2 1719; GFX8-NEXT: v_mov_b32_e32 v1, 0 1720; GFX8-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1] 1721; GFX8-NEXT: v_lshrrev_b32_e32 v2, 1, v3 1722; GFX8-NEXT: v_or_b32_e32 v0, v2, v0 1723; GFX8-NEXT: v_mov_b32_e32 v2, 0 1724; GFX8-NEXT: s_setpc_b64 s[30:31] 1725; 1726; GFX9-LABEL: v_lshr_i65_33: 1727; GFX9: ; %bb.0: 1728; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1729; GFX9-NEXT: v_mov_b32_e32 v3, v1 1730; GFX9-NEXT: v_and_b32_e32 v0, 1, v2 1731; GFX9-NEXT: v_mov_b32_e32 v1, 0 1732; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1] 1733; GFX9-NEXT: v_lshrrev_b32_e32 v2, 1, v3 1734; GFX9-NEXT: v_or_b32_e32 v0, v2, v0 1735; GFX9-NEXT: v_mov_b32_e32 v2, 0 1736; GFX9-NEXT: s_setpc_b64 s[30:31] 1737; 1738; GFX10-LABEL: v_lshr_i65_33: 1739; GFX10: ; %bb.0: 1740; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1741; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1742; GFX10-NEXT: v_mov_b32_e32 v3, v1 1743; GFX10-NEXT: v_mov_b32_e32 v1, 0 1744; GFX10-NEXT: v_and_b32_e32 v0, 1, v2 1745; GFX10-NEXT: v_lshrrev_b32_e32 v2, 1, v3 1746; GFX10-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1] 1747; GFX10-NEXT: v_or_b32_e32 v0, v2, v0 1748; GFX10-NEXT: v_mov_b32_e32 v2, 0 1749; GFX10-NEXT: s_setpc_b64 s[30:31] 1750; 1751; GFX11-LABEL: v_lshr_i65_33: 1752; GFX11: ; %bb.0: 1753; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1754; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 1755; GFX11-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_and_b32 v0, 1, v2 1756; GFX11-NEXT: v_mov_b32_e32 v1, 0 1757; GFX11-NEXT: v_lshrrev_b32_e32 v2, 1, v3 1758; GFX11-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1] 1759; GFX11-NEXT: v_or_b32_e32 v0, v2, v0 1760; GFX11-NEXT: v_mov_b32_e32 v2, 0 1761; GFX11-NEXT: s_setpc_b64 s[30:31] 1762 %result = lshr i65 %value, 33 1763 ret i65 %result 1764} 1765 1766define amdgpu_ps i65 @s_lshr_i65(i65 inreg %value, i65 inreg %amount) { 1767; GCN-LABEL: s_lshr_i65: 1768; GCN: ; %bb.0: 1769; GCN-NEXT: s_and_b64 s[4:5], s[2:3], 1 1770; GCN-NEXT: s_sub_i32 s10, s3, 64 1771; GCN-NEXT: s_sub_i32 s8, 64, s3 1772; GCN-NEXT: s_cmp_lt_u32 s3, 64 1773; GCN-NEXT: s_cselect_b32 s11, 1, 0 1774; GCN-NEXT: s_cmp_eq_u32 s3, 0 1775; GCN-NEXT: s_cselect_b32 s12, 1, 0 1776; GCN-NEXT: s_lshr_b64 s[6:7], s[4:5], s3 1777; GCN-NEXT: s_lshr_b64 s[2:3], s[0:1], s3 1778; GCN-NEXT: s_lshl_b64 s[8:9], s[4:5], s8 1779; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] 1780; GCN-NEXT: s_lshr_b64 s[4:5], s[4:5], s10 1781; GCN-NEXT: s_cmp_lg_u32 s11, 0 1782; GCN-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5] 1783; GCN-NEXT: s_cmp_lg_u32 s12, 0 1784; GCN-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] 1785; GCN-NEXT: s_cmp_lg_u32 s11, 0 1786; GCN-NEXT: s_cselect_b64 s[2:3], s[6:7], 0 1787; GCN-NEXT: ; return to shader part epilog 1788; 1789; GFX10PLUS-LABEL: s_lshr_i65: 1790; GFX10PLUS: ; %bb.0: 1791; GFX10PLUS-NEXT: s_and_b64 s[4:5], s[2:3], 1 1792; GFX10PLUS-NEXT: s_sub_i32 s10, s3, 64 1793; GFX10PLUS-NEXT: s_sub_i32 s2, 64, s3 1794; GFX10PLUS-NEXT: s_cmp_lt_u32 s3, 64 1795; GFX10PLUS-NEXT: s_cselect_b32 s11, 1, 0 1796; GFX10PLUS-NEXT: s_cmp_eq_u32 s3, 0 1797; GFX10PLUS-NEXT: s_cselect_b32 s12, 1, 0 1798; GFX10PLUS-NEXT: s_lshr_b64 s[6:7], s[0:1], s3 1799; GFX10PLUS-NEXT: s_lshl_b64 s[8:9], s[4:5], s2 1800; GFX10PLUS-NEXT: s_lshr_b64 s[2:3], s[4:5], s3 1801; GFX10PLUS-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] 1802; GFX10PLUS-NEXT: s_lshr_b64 s[4:5], s[4:5], s10 1803; GFX10PLUS-NEXT: s_cmp_lg_u32 s11, 0 1804; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5] 1805; GFX10PLUS-NEXT: s_cmp_lg_u32 s12, 0 1806; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] 1807; GFX10PLUS-NEXT: s_cmp_lg_u32 s11, 0 1808; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[2:3], 0 1809; GFX10PLUS-NEXT: ; return to shader part epilog 1810 %result = lshr i65 %value, %amount 1811 ret i65 %result 1812} 1813 1814define amdgpu_ps i65 @s_lshr_i65_33(i65 inreg %value) { 1815; GCN-LABEL: s_lshr_i65_33: 1816; GCN: ; %bb.0: 1817; GCN-NEXT: s_and_b64 s[2:3], s[2:3], 1 1818; GCN-NEXT: s_lshr_b32 s0, s1, 1 1819; GCN-NEXT: s_mov_b32 s1, 0 1820; GCN-NEXT: s_lshl_b64 s[4:5], s[2:3], 31 1821; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] 1822; GCN-NEXT: s_lshr_b32 s2, s3, 1 1823; GCN-NEXT: ; return to shader part epilog 1824; 1825; GFX10PLUS-LABEL: s_lshr_i65_33: 1826; GFX10PLUS: ; %bb.0: 1827; GFX10PLUS-NEXT: s_and_b64 s[2:3], s[2:3], 1 1828; GFX10PLUS-NEXT: s_lshr_b32 s0, s1, 1 1829; GFX10PLUS-NEXT: s_mov_b32 s1, 0 1830; GFX10PLUS-NEXT: s_lshl_b64 s[4:5], s[2:3], 31 1831; GFX10PLUS-NEXT: s_lshr_b32 s2, s3, 1 1832; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] 1833; GFX10PLUS-NEXT: ; return to shader part epilog 1834 %result = lshr i65 %value, 33 1835 ret i65 %result 1836} 1837 1838; FIXME: Argument lowering asserts 1839; define <2 x i65> @v_lshr_v2i65(<2 x i65> %value, <2 x i65> %amount) { 1840; %result = lshr <2 x i65> %value, %amount 1841; ret <2 x i65> %result 1842; } 1843 1844; define amdgpu_ps <2 x i65> @s_lshr_v2i65(<2 x i65> inreg %value, <2 x i65> inreg %amount) { 1845; %result = lshr <2 x i65> %value, %amount 1846; ret <2 x i65> %result 1847; } 1848