1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s 3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s 4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s 5 6define i8 @v_lshr_i8(i8 %value, i8 %amount) { 7; GFX6-LABEL: v_lshr_i8: 8; GFX6: ; %bb.0: 9; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 10; GFX6-NEXT: s_movk_i32 s4, 0xff 11; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 12; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 13; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0 14; GFX6-NEXT: s_setpc_b64 s[30:31] 15; 16; GFX8-LABEL: v_lshr_i8: 17; GFX8: ; %bb.0: 18; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 19; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 20; GFX8-NEXT: s_setpc_b64 s[30:31] 21; 22; GFX9-LABEL: v_lshr_i8: 23; GFX9: ; %bb.0: 24; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 25; GFX9-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 26; GFX9-NEXT: s_setpc_b64 s[30:31] 27 %result = lshr i8 %value, %amount 28 ret i8 %result 29} 30 31define i8 @v_lshr_i8_7(i8 %value) { 32; GFX6-LABEL: v_lshr_i8_7: 33; GFX6: ; %bb.0: 34; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 35; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0 36; GFX6-NEXT: v_lshrrev_b32_e32 v0, 7, v0 37; GFX6-NEXT: s_setpc_b64 s[30:31] 38; 39; GFX8-LABEL: v_lshr_i8_7: 40; GFX8: ; %bb.0: 41; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 42; GFX8-NEXT: v_mov_b32_e32 v1, 7 43; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 44; GFX8-NEXT: s_setpc_b64 s[30:31] 45; 46; GFX9-LABEL: v_lshr_i8_7: 47; GFX9: ; %bb.0: 48; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 49; GFX9-NEXT: s_mov_b32 s4, 7 50; GFX9-NEXT: v_lshrrev_b16_sdwa v0, s4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 51; GFX9-NEXT: s_setpc_b64 s[30:31] 52 %result = lshr i8 %value, 7 53 ret i8 %result 54} 55 56define amdgpu_ps i8 @s_lshr_i8(i8 inreg %value, i8 inreg %amount) { 57; GFX6-LABEL: s_lshr_i8: 58; GFX6: ; %bb.0: 59; GFX6-NEXT: s_movk_i32 s2, 0xff 60; GFX6-NEXT: s_and_b32 s1, s1, s2 61; GFX6-NEXT: s_and_b32 s0, s0, s2 62; GFX6-NEXT: s_lshr_b32 s0, s0, s1 63; GFX6-NEXT: ; return to shader part epilog 64; 65; GFX8-LABEL: s_lshr_i8: 66; GFX8: ; %bb.0: 67; GFX8-NEXT: s_movk_i32 s2, 0xff 68; GFX8-NEXT: s_and_b32 s0, s0, s2 69; GFX8-NEXT: s_and_b32 s1, s1, s2 70; GFX8-NEXT: s_lshr_b32 s0, s0, s1 71; GFX8-NEXT: ; return to shader part epilog 72; 73; GFX9-LABEL: s_lshr_i8: 74; GFX9: ; %bb.0: 75; GFX9-NEXT: s_movk_i32 s2, 0xff 76; GFX9-NEXT: s_and_b32 s0, s0, s2 77; GFX9-NEXT: s_and_b32 s1, s1, s2 78; GFX9-NEXT: s_lshr_b32 s0, s0, s1 79; GFX9-NEXT: ; return to shader part epilog 80 %result = lshr i8 %value, %amount 81 ret i8 %result 82} 83 84define amdgpu_ps i8 @s_lshr_i8_7(i8 inreg %value) { 85; GCN-LABEL: s_lshr_i8_7: 86; GCN: ; %bb.0: 87; GCN-NEXT: s_and_b32 s0, s0, 0xff 88; GCN-NEXT: s_lshr_b32 s0, s0, 7 89; GCN-NEXT: ; return to shader part epilog 90 %result = lshr i8 %value, 7 91 ret i8 %result 92} 93 94 95define i24 @v_lshr_i24(i24 %value, i24 %amount) { 96; GCN-LABEL: v_lshr_i24: 97; GCN: ; %bb.0: 98; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 99; GCN-NEXT: s_mov_b32 s4, 0xffffff 100; GCN-NEXT: v_and_b32_e32 v1, s4, v1 101; GCN-NEXT: v_and_b32_e32 v0, s4, v0 102; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0 103; GCN-NEXT: s_setpc_b64 s[30:31] 104 %result = lshr i24 %value, %amount 105 ret i24 %result 106} 107 108define i24 @v_lshr_i24_7(i24 %value) { 109; GCN-LABEL: v_lshr_i24_7: 110; GCN: ; %bb.0: 111; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 112; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 113; GCN-NEXT: v_lshrrev_b32_e32 v0, 7, v0 114; GCN-NEXT: s_setpc_b64 s[30:31] 115 %result = lshr i24 %value, 7 116 ret i24 %result 117} 118 119define amdgpu_ps i24 @s_lshr_i24(i24 inreg %value, i24 inreg %amount) { 120; GCN-LABEL: s_lshr_i24: 121; GCN: ; %bb.0: 122; GCN-NEXT: s_mov_b32 s2, 0xffffff 123; GCN-NEXT: s_and_b32 s1, s1, s2 124; GCN-NEXT: s_and_b32 s0, s0, s2 125; GCN-NEXT: s_lshr_b32 s0, s0, s1 126; GCN-NEXT: ; return to shader part epilog 127 %result = lshr i24 %value, %amount 128 ret i24 %result 129} 130 131define amdgpu_ps i24 @s_lshr_i24_7(i24 inreg %value) { 132; GCN-LABEL: s_lshr_i24_7: 133; GCN: ; %bb.0: 134; GCN-NEXT: s_and_b32 s0, s0, 0xffffff 135; GCN-NEXT: s_lshr_b32 s0, s0, 7 136; GCN-NEXT: ; return to shader part epilog 137 %result = lshr i24 %value, 7 138 ret i24 %result 139} 140 141define i32 @v_lshr_i32(i32 %value, i32 %amount) { 142; GCN-LABEL: v_lshr_i32: 143; GCN: ; %bb.0: 144; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 145; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0 146; GCN-NEXT: s_setpc_b64 s[30:31] 147 %result = lshr i32 %value, %amount 148 ret i32 %result 149} 150 151define i32 @v_lshr_i32_31(i32 %value) { 152; GCN-LABEL: v_lshr_i32_31: 153; GCN: ; %bb.0: 154; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 155; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0 156; GCN-NEXT: s_setpc_b64 s[30:31] 157 %result = lshr i32 %value, 31 158 ret i32 %result 159} 160 161define amdgpu_ps i32 @s_lshr_i32(i32 inreg %value, i32 inreg %amount) { 162; GCN-LABEL: s_lshr_i32: 163; GCN: ; %bb.0: 164; GCN-NEXT: s_lshr_b32 s0, s0, s1 165; GCN-NEXT: ; return to shader part epilog 166 %result = lshr i32 %value, %amount 167 ret i32 %result 168} 169 170define amdgpu_ps i32 @s_lshr_i32_31(i32 inreg %value) { 171; GCN-LABEL: s_lshr_i32_31: 172; GCN: ; %bb.0: 173; GCN-NEXT: s_lshr_b32 s0, s0, 31 174; GCN-NEXT: ; return to shader part epilog 175 %result = lshr i32 %value, 31 176 ret i32 %result 177} 178 179define amdgpu_ps float @lshr_i32_sv(i32 inreg %value, i32 %amount) { 180; GFX6-LABEL: lshr_i32_sv: 181; GFX6: ; %bb.0: 182; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0 183; GFX6-NEXT: ; return to shader part epilog 184; 185; GFX8-LABEL: lshr_i32_sv: 186; GFX8: ; %bb.0: 187; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s0 188; GFX8-NEXT: ; return to shader part epilog 189; 190; GFX9-LABEL: lshr_i32_sv: 191; GFX9: ; %bb.0: 192; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s0 193; GFX9-NEXT: ; return to shader part epilog 194 %result = lshr i32 %value, %amount 195 %cast = bitcast i32 %result to float 196 ret float %cast 197} 198 199define amdgpu_ps float @lshr_i32_vs(i32 %value, i32 inreg %amount) { 200; GCN-LABEL: lshr_i32_vs: 201; GCN: ; %bb.0: 202; GCN-NEXT: v_lshrrev_b32_e32 v0, s0, v0 203; GCN-NEXT: ; return to shader part epilog 204 %result = lshr i32 %value, %amount 205 %cast = bitcast i32 %result to float 206 ret float %cast 207} 208 209define <2 x i32> @v_lshr_v2i32(<2 x i32> %value, <2 x i32> %amount) { 210; GCN-LABEL: v_lshr_v2i32: 211; GCN: ; %bb.0: 212; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 213; GCN-NEXT: v_lshrrev_b32_e32 v0, v2, v0 214; GCN-NEXT: v_lshrrev_b32_e32 v1, v3, v1 215; GCN-NEXT: s_setpc_b64 s[30:31] 216 %result = lshr <2 x i32> %value, %amount 217 ret <2 x i32> %result 218} 219 220define <2 x i32> @v_lshr_v2i32_31(<2 x i32> %value) { 221; GCN-LABEL: v_lshr_v2i32_31: 222; GCN: ; %bb.0: 223; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 224; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0 225; GCN-NEXT: v_lshrrev_b32_e32 v1, 31, v1 226; GCN-NEXT: s_setpc_b64 s[30:31] 227 %result = lshr <2 x i32> %value, <i32 31, i32 31> 228 ret <2 x i32> %result 229} 230 231define amdgpu_ps <2 x i32> @s_lshr_v2i32(<2 x i32> inreg %value, <2 x i32> inreg %amount) { 232; GCN-LABEL: s_lshr_v2i32: 233; GCN: ; %bb.0: 234; GCN-NEXT: s_lshr_b32 s0, s0, s2 235; GCN-NEXT: s_lshr_b32 s1, s1, s3 236; GCN-NEXT: ; return to shader part epilog 237 %result = lshr <2 x i32> %value, %amount 238 ret <2 x i32> %result 239} 240 241define <3 x i32> @v_lshr_v3i32(<3 x i32> %value, <3 x i32> %amount) { 242; GCN-LABEL: v_lshr_v3i32: 243; GCN: ; %bb.0: 244; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 245; GCN-NEXT: v_lshrrev_b32_e32 v0, v3, v0 246; GCN-NEXT: v_lshrrev_b32_e32 v1, v4, v1 247; GCN-NEXT: v_lshrrev_b32_e32 v2, v5, v2 248; GCN-NEXT: s_setpc_b64 s[30:31] 249 %result = lshr <3 x i32> %value, %amount 250 ret <3 x i32> %result 251} 252 253define amdgpu_ps <3 x i32> @s_lshr_v3i32(<3 x i32> inreg %value, <3 x i32> inreg %amount) { 254; GCN-LABEL: s_lshr_v3i32: 255; GCN: ; %bb.0: 256; GCN-NEXT: s_lshr_b32 s0, s0, s3 257; GCN-NEXT: s_lshr_b32 s1, s1, s4 258; GCN-NEXT: s_lshr_b32 s2, s2, s5 259; GCN-NEXT: ; return to shader part epilog 260 %result = lshr <3 x i32> %value, %amount 261 ret <3 x i32> %result 262} 263 264define <4 x i32> @v_lshr_v4i32(<4 x i32> %value, <4 x i32> %amount) { 265; GCN-LABEL: v_lshr_v4i32: 266; GCN: ; %bb.0: 267; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 268; GCN-NEXT: v_lshrrev_b32_e32 v0, v4, v0 269; GCN-NEXT: v_lshrrev_b32_e32 v1, v5, v1 270; GCN-NEXT: v_lshrrev_b32_e32 v2, v6, v2 271; GCN-NEXT: v_lshrrev_b32_e32 v3, v7, v3 272; GCN-NEXT: s_setpc_b64 s[30:31] 273 %result = lshr <4 x i32> %value, %amount 274 ret <4 x i32> %result 275} 276 277define amdgpu_ps <4 x i32> @s_lshr_v4i32(<4 x i32> inreg %value, <4 x i32> inreg %amount) { 278; GCN-LABEL: s_lshr_v4i32: 279; GCN: ; %bb.0: 280; GCN-NEXT: s_lshr_b32 s0, s0, s4 281; GCN-NEXT: s_lshr_b32 s1, s1, s5 282; GCN-NEXT: s_lshr_b32 s2, s2, s6 283; GCN-NEXT: s_lshr_b32 s3, s3, s7 284; GCN-NEXT: ; return to shader part epilog 285 %result = lshr <4 x i32> %value, %amount 286 ret <4 x i32> %result 287} 288 289define <5 x i32> @v_lshr_v5i32(<5 x i32> %value, <5 x i32> %amount) { 290; GCN-LABEL: v_lshr_v5i32: 291; GCN: ; %bb.0: 292; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 293; GCN-NEXT: v_lshrrev_b32_e32 v0, v5, v0 294; GCN-NEXT: v_lshrrev_b32_e32 v1, v6, v1 295; GCN-NEXT: v_lshrrev_b32_e32 v2, v7, v2 296; GCN-NEXT: v_lshrrev_b32_e32 v3, v8, v3 297; GCN-NEXT: v_lshrrev_b32_e32 v4, v9, v4 298; GCN-NEXT: s_setpc_b64 s[30:31] 299 %result = lshr <5 x i32> %value, %amount 300 ret <5 x i32> %result 301} 302 303define amdgpu_ps <5 x i32> @s_lshr_v5i32(<5 x i32> inreg %value, <5 x i32> inreg %amount) { 304; GCN-LABEL: s_lshr_v5i32: 305; GCN: ; %bb.0: 306; GCN-NEXT: s_lshr_b32 s0, s0, s5 307; GCN-NEXT: s_lshr_b32 s1, s1, s6 308; GCN-NEXT: s_lshr_b32 s2, s2, s7 309; GCN-NEXT: s_lshr_b32 s3, s3, s8 310; GCN-NEXT: s_lshr_b32 s4, s4, s9 311; GCN-NEXT: ; return to shader part epilog 312 %result = lshr <5 x i32> %value, %amount 313 ret <5 x i32> %result 314} 315 316define <16 x i32> @v_lshr_v16i32(<16 x i32> %value, <16 x i32> %amount) { 317; GCN-LABEL: v_lshr_v16i32: 318; GCN: ; %bb.0: 319; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 320; GCN-NEXT: v_lshrrev_b32_e32 v0, v16, v0 321; GCN-NEXT: v_lshrrev_b32_e32 v1, v17, v1 322; GCN-NEXT: v_lshrrev_b32_e32 v2, v18, v2 323; GCN-NEXT: v_lshrrev_b32_e32 v3, v19, v3 324; GCN-NEXT: v_lshrrev_b32_e32 v4, v20, v4 325; GCN-NEXT: v_lshrrev_b32_e32 v5, v21, v5 326; GCN-NEXT: v_lshrrev_b32_e32 v6, v22, v6 327; GCN-NEXT: v_lshrrev_b32_e32 v7, v23, v7 328; GCN-NEXT: v_lshrrev_b32_e32 v8, v24, v8 329; GCN-NEXT: v_lshrrev_b32_e32 v9, v25, v9 330; GCN-NEXT: v_lshrrev_b32_e32 v10, v26, v10 331; GCN-NEXT: v_lshrrev_b32_e32 v11, v27, v11 332; GCN-NEXT: v_lshrrev_b32_e32 v12, v28, v12 333; GCN-NEXT: v_lshrrev_b32_e32 v13, v29, v13 334; GCN-NEXT: v_lshrrev_b32_e32 v14, v30, v14 335; GCN-NEXT: v_lshrrev_b32_e32 v15, v31, v15 336; GCN-NEXT: s_setpc_b64 s[30:31] 337 %result = lshr <16 x i32> %value, %amount 338 ret <16 x i32> %result 339} 340 341define amdgpu_ps <16 x i32> @s_lshr_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) { 342; GCN-LABEL: s_lshr_v16i32: 343; GCN: ; %bb.0: 344; GCN-NEXT: s_lshr_b32 s0, s0, s16 345; GCN-NEXT: s_lshr_b32 s1, s1, s17 346; GCN-NEXT: s_lshr_b32 s2, s2, s18 347; GCN-NEXT: s_lshr_b32 s3, s3, s19 348; GCN-NEXT: s_lshr_b32 s4, s4, s20 349; GCN-NEXT: s_lshr_b32 s5, s5, s21 350; GCN-NEXT: s_lshr_b32 s6, s6, s22 351; GCN-NEXT: s_lshr_b32 s7, s7, s23 352; GCN-NEXT: s_lshr_b32 s8, s8, s24 353; GCN-NEXT: s_lshr_b32 s9, s9, s25 354; GCN-NEXT: s_lshr_b32 s10, s10, s26 355; GCN-NEXT: s_lshr_b32 s11, s11, s27 356; GCN-NEXT: s_lshr_b32 s12, s12, s28 357; GCN-NEXT: s_lshr_b32 s13, s13, s29 358; GCN-NEXT: s_lshr_b32 s14, s14, s30 359; GCN-NEXT: s_lshr_b32 s15, s15, s31 360; GCN-NEXT: ; return to shader part epilog 361 %result = lshr <16 x i32> %value, %amount 362 ret <16 x i32> %result 363} 364 365define i16 @v_lshr_i16(i16 %value, i16 %amount) { 366; GFX6-LABEL: v_lshr_i16: 367; GFX6: ; %bb.0: 368; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 369; GFX6-NEXT: s_mov_b32 s4, 0xffff 370; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 371; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 372; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0 373; GFX6-NEXT: s_setpc_b64 s[30:31] 374; 375; GFX8-LABEL: v_lshr_i16: 376; GFX8: ; %bb.0: 377; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 378; GFX8-NEXT: v_lshrrev_b16_e32 v0, v1, v0 379; GFX8-NEXT: s_setpc_b64 s[30:31] 380; 381; GFX9-LABEL: v_lshr_i16: 382; GFX9: ; %bb.0: 383; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 384; GFX9-NEXT: v_lshrrev_b16_e32 v0, v1, v0 385; GFX9-NEXT: s_setpc_b64 s[30:31] 386 %result = lshr i16 %value, %amount 387 ret i16 %result 388} 389 390define i16 @v_lshr_i16_31(i16 %value) { 391; GCN-LABEL: v_lshr_i16_31: 392; GCN: ; %bb.0: 393; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 394; GCN-NEXT: s_setpc_b64 s[30:31] 395 %result = lshr i16 %value, 31 396 ret i16 %result 397} 398 399define amdgpu_ps i16 @s_lshr_i16(i16 inreg %value, i16 inreg %amount) { 400; GFX6-LABEL: s_lshr_i16: 401; GFX6: ; %bb.0: 402; GFX6-NEXT: s_mov_b32 s2, 0xffff 403; GFX6-NEXT: s_and_b32 s1, s1, s2 404; GFX6-NEXT: s_and_b32 s0, s0, s2 405; GFX6-NEXT: s_lshr_b32 s0, s0, s1 406; GFX6-NEXT: ; return to shader part epilog 407; 408; GFX8-LABEL: s_lshr_i16: 409; GFX8: ; %bb.0: 410; GFX8-NEXT: s_mov_b32 s2, 0xffff 411; GFX8-NEXT: s_and_b32 s0, s0, s2 412; GFX8-NEXT: s_and_b32 s1, s1, s2 413; GFX8-NEXT: s_lshr_b32 s0, s0, s1 414; GFX8-NEXT: ; return to shader part epilog 415; 416; GFX9-LABEL: s_lshr_i16: 417; GFX9: ; %bb.0: 418; GFX9-NEXT: s_mov_b32 s2, 0xffff 419; GFX9-NEXT: s_and_b32 s0, s0, s2 420; GFX9-NEXT: s_and_b32 s1, s1, s2 421; GFX9-NEXT: s_lshr_b32 s0, s0, s1 422; GFX9-NEXT: ; return to shader part epilog 423 %result = lshr i16 %value, %amount 424 ret i16 %result 425} 426 427define amdgpu_ps i16 @s_lshr_i16_15(i16 inreg %value) { 428; GCN-LABEL: s_lshr_i16_15: 429; GCN: ; %bb.0: 430; GCN-NEXT: s_and_b32 s0, s0, 0xffff 431; GCN-NEXT: s_lshr_b32 s0, s0, 15 432; GCN-NEXT: ; return to shader part epilog 433 %result = lshr i16 %value, 15 434 ret i16 %result 435} 436 437define amdgpu_ps half @lshr_i16_sv(i16 inreg %value, i16 %amount) { 438; GFX6-LABEL: lshr_i16_sv: 439; GFX6: ; %bb.0: 440; GFX6-NEXT: s_mov_b32 s1, 0xffff 441; GFX6-NEXT: v_and_b32_e32 v0, s1, v0 442; GFX6-NEXT: s_and_b32 s0, s0, s1 443; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0 444; GFX6-NEXT: ; return to shader part epilog 445; 446; GFX8-LABEL: lshr_i16_sv: 447; GFX8: ; %bb.0: 448; GFX8-NEXT: v_lshrrev_b16_e64 v0, v0, s0 449; GFX8-NEXT: ; return to shader part epilog 450; 451; GFX9-LABEL: lshr_i16_sv: 452; GFX9: ; %bb.0: 453; GFX9-NEXT: v_lshrrev_b16_e64 v0, v0, s0 454; GFX9-NEXT: ; return to shader part epilog 455 %result = lshr i16 %value, %amount 456 %cast = bitcast i16 %result to half 457 ret half %cast 458} 459 460define amdgpu_ps half @lshr_i16_vs(i16 %value, i16 inreg %amount) { 461; GFX6-LABEL: lshr_i16_vs: 462; GFX6: ; %bb.0: 463; GFX6-NEXT: s_mov_b32 s1, 0xffff 464; GFX6-NEXT: s_and_b32 s0, s0, s1 465; GFX6-NEXT: v_and_b32_e32 v0, s1, v0 466; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0 467; GFX6-NEXT: ; return to shader part epilog 468; 469; GFX8-LABEL: lshr_i16_vs: 470; GFX8: ; %bb.0: 471; GFX8-NEXT: v_lshrrev_b16_e32 v0, s0, v0 472; GFX8-NEXT: ; return to shader part epilog 473; 474; GFX9-LABEL: lshr_i16_vs: 475; GFX9: ; %bb.0: 476; GFX9-NEXT: v_lshrrev_b16_e32 v0, s0, v0 477; GFX9-NEXT: ; return to shader part epilog 478 %result = lshr i16 %value, %amount 479 %cast = bitcast i16 %result to half 480 ret half %cast 481} 482 483define <2 x i16> @v_lshr_v2i16(<2 x i16> %value, <2 x i16> %amount) { 484; GFX6-LABEL: v_lshr_v2i16: 485; GFX6: ; %bb.0: 486; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 487; GFX6-NEXT: s_mov_b32 s4, 0xffff 488; GFX6-NEXT: v_and_b32_e32 v2, s4, v2 489; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 490; GFX6-NEXT: v_lshrrev_b32_e32 v0, v2, v0 491; GFX6-NEXT: v_and_b32_e32 v2, s4, v3 492; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 493; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1 494; GFX6-NEXT: s_setpc_b64 s[30:31] 495; 496; GFX8-LABEL: v_lshr_v2i16: 497; GFX8: ; %bb.0: 498; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 499; GFX8-NEXT: v_lshrrev_b16_e32 v2, v1, v0 500; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 501; GFX8-NEXT: v_or_b32_e32 v0, v2, v0 502; GFX8-NEXT: s_setpc_b64 s[30:31] 503; 504; GFX9-LABEL: v_lshr_v2i16: 505; GFX9: ; %bb.0: 506; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 507; GFX9-NEXT: v_pk_lshrrev_b16 v0, v1, v0 508; GFX9-NEXT: s_setpc_b64 s[30:31] 509 %result = lshr <2 x i16> %value, %amount 510 ret <2 x i16> %result 511} 512 513define <2 x i16> @v_lshr_v2i16_15(<2 x i16> %value) { 514; GFX6-LABEL: v_lshr_v2i16_15: 515; GFX6: ; %bb.0: 516; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 517; GFX6-NEXT: s_mov_b32 s4, 0xffff 518; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 519; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 520; GFX6-NEXT: v_lshrrev_b32_e32 v0, 15, v0 521; GFX6-NEXT: v_lshrrev_b32_e32 v1, 15, v1 522; GFX6-NEXT: s_setpc_b64 s[30:31] 523; 524; GFX8-LABEL: v_lshr_v2i16_15: 525; GFX8: ; %bb.0: 526; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 527; GFX8-NEXT: v_mov_b32_e32 v2, 15 528; GFX8-NEXT: v_lshrrev_b16_e32 v1, 15, v0 529; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 530; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 531; GFX8-NEXT: s_setpc_b64 s[30:31] 532; 533; GFX9-LABEL: v_lshr_v2i16_15: 534; GFX9: ; %bb.0: 535; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 536; GFX9-NEXT: s_pack_ll_b32_b16 s4, 15, 15 537; GFX9-NEXT: v_pk_lshrrev_b16 v0, s4, v0 538; GFX9-NEXT: s_setpc_b64 s[30:31] 539 %result = lshr <2 x i16> %value, <i16 15, i16 15> 540 ret <2 x i16> %result 541} 542 543define amdgpu_ps i32 @s_lshr_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) { 544; GFX6-LABEL: s_lshr_v2i16: 545; GFX6: ; %bb.0: 546; GFX6-NEXT: s_mov_b32 s4, 0xffff 547; GFX6-NEXT: s_and_b32 s2, s2, s4 548; GFX6-NEXT: s_and_b32 s0, s0, s4 549; GFX6-NEXT: s_lshr_b32 s0, s0, s2 550; GFX6-NEXT: s_and_b32 s2, s3, s4 551; GFX6-NEXT: s_and_b32 s1, s1, s4 552; GFX6-NEXT: s_lshr_b32 s1, s1, s2 553; GFX6-NEXT: s_and_b32 s1, s1, s4 554; GFX6-NEXT: s_and_b32 s0, s0, s4 555; GFX6-NEXT: s_lshl_b32 s1, s1, 16 556; GFX6-NEXT: s_or_b32 s0, s0, s1 557; GFX6-NEXT: ; return to shader part epilog 558; 559; GFX8-LABEL: s_lshr_v2i16: 560; GFX8: ; %bb.0: 561; GFX8-NEXT: s_lshr_b32 s2, s0, 16 562; GFX8-NEXT: s_mov_b32 s3, 0xffff 563; GFX8-NEXT: s_lshr_b32 s4, s1, 16 564; GFX8-NEXT: s_and_b32 s0, s0, s3 565; GFX8-NEXT: s_and_b32 s1, s1, s3 566; GFX8-NEXT: s_and_b32 s2, s2, s3 567; GFX8-NEXT: s_and_b32 s4, s4, s3 568; GFX8-NEXT: s_lshr_b32 s0, s0, s1 569; GFX8-NEXT: s_lshr_b32 s1, s2, s4 570; GFX8-NEXT: s_lshl_b32 s1, s1, 16 571; GFX8-NEXT: s_and_b32 s0, s0, s3 572; GFX8-NEXT: s_or_b32 s0, s1, s0 573; GFX8-NEXT: ; return to shader part epilog 574; 575; GFX9-LABEL: s_lshr_v2i16: 576; GFX9: ; %bb.0: 577; GFX9-NEXT: s_lshr_b32 s2, s0, 16 578; GFX9-NEXT: s_lshr_b32 s3, s1, 16 579; GFX9-NEXT: s_lshr_b32 s0, s0, s1 580; GFX9-NEXT: s_lshr_b32 s1, s2, s3 581; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1 582; GFX9-NEXT: ; return to shader part epilog 583 %result = lshr <2 x i16> %value, %amount 584 %cast = bitcast <2 x i16> %result to i32 585 ret i32 %cast 586} 587 588define amdgpu_ps float @lshr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) { 589; GFX6-LABEL: lshr_v2i16_sv: 590; GFX6: ; %bb.0: 591; GFX6-NEXT: s_mov_b32 s2, 0xffff 592; GFX6-NEXT: v_and_b32_e32 v0, s2, v0 593; GFX6-NEXT: s_and_b32 s0, s0, s2 594; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0 595; GFX6-NEXT: v_and_b32_e32 v1, s2, v1 596; GFX6-NEXT: s_and_b32 s0, s1, s2 597; GFX6-NEXT: v_lshr_b32_e32 v1, s0, v1 598; GFX6-NEXT: v_and_b32_e32 v1, s2, v1 599; GFX6-NEXT: v_and_b32_e32 v0, s2, v0 600; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 601; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 602; GFX6-NEXT: ; return to shader part epilog 603; 604; GFX8-LABEL: lshr_v2i16_sv: 605; GFX8: ; %bb.0: 606; GFX8-NEXT: s_lshr_b32 s1, s0, 16 607; GFX8-NEXT: v_mov_b32_e32 v2, s1 608; GFX8-NEXT: v_lshrrev_b16_e64 v1, v0, s0 609; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 610; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 611; GFX8-NEXT: ; return to shader part epilog 612; 613; GFX9-LABEL: lshr_v2i16_sv: 614; GFX9: ; %bb.0: 615; GFX9-NEXT: v_pk_lshrrev_b16 v0, v0, s0 616; GFX9-NEXT: ; return to shader part epilog 617 %result = lshr <2 x i16> %value, %amount 618 %cast = bitcast <2 x i16> %result to float 619 ret float %cast 620} 621 622define amdgpu_ps float @lshr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) { 623; GFX6-LABEL: lshr_v2i16_vs: 624; GFX6: ; %bb.0: 625; GFX6-NEXT: s_mov_b32 s2, 0xffff 626; GFX6-NEXT: s_and_b32 s0, s0, s2 627; GFX6-NEXT: v_and_b32_e32 v0, s2, v0 628; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0 629; GFX6-NEXT: s_and_b32 s0, s1, s2 630; GFX6-NEXT: v_and_b32_e32 v1, s2, v1 631; GFX6-NEXT: v_lshrrev_b32_e32 v1, s0, v1 632; GFX6-NEXT: v_and_b32_e32 v1, s2, v1 633; GFX6-NEXT: v_and_b32_e32 v0, s2, v0 634; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 635; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 636; GFX6-NEXT: ; return to shader part epilog 637; 638; GFX8-LABEL: lshr_v2i16_vs: 639; GFX8: ; %bb.0: 640; GFX8-NEXT: s_lshr_b32 s1, s0, 16 641; GFX8-NEXT: v_mov_b32_e32 v2, s1 642; GFX8-NEXT: v_lshrrev_b16_e32 v1, s0, v0 643; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 644; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 645; GFX8-NEXT: ; return to shader part epilog 646; 647; GFX9-LABEL: lshr_v2i16_vs: 648; GFX9: ; %bb.0: 649; GFX9-NEXT: v_pk_lshrrev_b16 v0, s0, v0 650; GFX9-NEXT: ; return to shader part epilog 651 %result = lshr <2 x i16> %value, %amount 652 %cast = bitcast <2 x i16> %result to float 653 ret float %cast 654} 655 656; FIXME 657; define <3 x i16> @v_lshr_v3i16(<3 x i16> %value, <3 x i16> %amount) { 658; %result = lshr <3 x i16> %value, %amount 659; ret <3 x i16> %result 660; } 661 662; define amdgpu_ps <3 x i16> @s_lshr_v3i16(<3 x i16> inreg %value, <3 x i16> inreg %amount) { 663; %result = lshr <3 x i16> %value, %amount 664; ret <3 x i16> %result 665; } 666 667define <2 x float> @v_lshr_v4i16(<4 x i16> %value, <4 x i16> %amount) { 668; GFX6-LABEL: v_lshr_v4i16: 669; GFX6: ; %bb.0: 670; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 671; GFX6-NEXT: s_mov_b32 s4, 0xffff 672; GFX6-NEXT: v_and_b32_e32 v4, s4, v4 673; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 674; GFX6-NEXT: v_lshrrev_b32_e32 v0, v4, v0 675; GFX6-NEXT: v_and_b32_e32 v4, s4, v5 676; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 677; GFX6-NEXT: v_lshrrev_b32_e32 v1, v4, v1 678; GFX6-NEXT: v_and_b32_e32 v4, s4, v6 679; GFX6-NEXT: v_and_b32_e32 v2, s4, v2 680; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 681; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2 682; GFX6-NEXT: v_and_b32_e32 v4, s4, v7 683; GFX6-NEXT: v_and_b32_e32 v3, s4, v3 684; GFX6-NEXT: v_lshrrev_b32_e32 v3, v4, v3 685; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 686; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 687; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 688; GFX6-NEXT: v_and_b32_e32 v1, s4, v2 689; GFX6-NEXT: v_and_b32_e32 v2, s4, v3 690; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2 691; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 692; GFX6-NEXT: s_setpc_b64 s[30:31] 693; 694; GFX8-LABEL: v_lshr_v4i16: 695; GFX8: ; %bb.0: 696; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 697; GFX8-NEXT: v_lshrrev_b16_e32 v4, v2, v0 698; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 699; GFX8-NEXT: v_lshrrev_b16_e32 v2, v3, v1 700; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 701; GFX8-NEXT: v_or_b32_e32 v0, v4, v0 702; GFX8-NEXT: v_or_b32_e32 v1, v2, v1 703; GFX8-NEXT: s_setpc_b64 s[30:31] 704; 705; GFX9-LABEL: v_lshr_v4i16: 706; GFX9: ; %bb.0: 707; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 708; GFX9-NEXT: v_pk_lshrrev_b16 v0, v2, v0 709; GFX9-NEXT: v_pk_lshrrev_b16 v1, v3, v1 710; GFX9-NEXT: s_setpc_b64 s[30:31] 711 %result = lshr <4 x i16> %value, %amount 712 %cast = bitcast <4 x i16> %result to <2 x float> 713 ret <2 x float> %cast 714} 715 716define amdgpu_ps <2 x i32> @s_lshr_v4i16(<4 x i16> inreg %value, <4 x i16> inreg %amount) { 717; GFX6-LABEL: s_lshr_v4i16: 718; GFX6: ; %bb.0: 719; GFX6-NEXT: s_mov_b32 s8, 0xffff 720; GFX6-NEXT: s_and_b32 s4, s4, s8 721; GFX6-NEXT: s_and_b32 s0, s0, s8 722; GFX6-NEXT: s_lshr_b32 s0, s0, s4 723; GFX6-NEXT: s_and_b32 s4, s5, s8 724; GFX6-NEXT: s_and_b32 s1, s1, s8 725; GFX6-NEXT: s_lshr_b32 s1, s1, s4 726; GFX6-NEXT: s_and_b32 s4, s6, s8 727; GFX6-NEXT: s_and_b32 s2, s2, s8 728; GFX6-NEXT: s_and_b32 s1, s1, s8 729; GFX6-NEXT: s_lshr_b32 s2, s2, s4 730; GFX6-NEXT: s_and_b32 s4, s7, s8 731; GFX6-NEXT: s_and_b32 s3, s3, s8 732; GFX6-NEXT: s_lshr_b32 s3, s3, s4 733; GFX6-NEXT: s_and_b32 s0, s0, s8 734; GFX6-NEXT: s_lshl_b32 s1, s1, 16 735; GFX6-NEXT: s_or_b32 s0, s0, s1 736; GFX6-NEXT: s_and_b32 s1, s2, s8 737; GFX6-NEXT: s_and_b32 s2, s3, s8 738; GFX6-NEXT: s_lshl_b32 s2, s2, 16 739; GFX6-NEXT: s_or_b32 s1, s1, s2 740; GFX6-NEXT: ; return to shader part epilog 741; 742; GFX8-LABEL: s_lshr_v4i16: 743; GFX8: ; %bb.0: 744; GFX8-NEXT: s_lshr_b32 s4, s0, 16 745; GFX8-NEXT: s_mov_b32 s6, 0xffff 746; GFX8-NEXT: s_lshr_b32 s7, s2, 16 747; GFX8-NEXT: s_lshr_b32 s5, s1, 16 748; GFX8-NEXT: s_lshr_b32 s8, s3, 16 749; GFX8-NEXT: s_and_b32 s0, s0, s6 750; GFX8-NEXT: s_and_b32 s2, s2, s6 751; GFX8-NEXT: s_and_b32 s4, s4, s6 752; GFX8-NEXT: s_and_b32 s7, s7, s6 753; GFX8-NEXT: s_lshr_b32 s0, s0, s2 754; GFX8-NEXT: s_lshr_b32 s2, s4, s7 755; GFX8-NEXT: s_and_b32 s1, s1, s6 756; GFX8-NEXT: s_and_b32 s3, s3, s6 757; GFX8-NEXT: s_and_b32 s5, s5, s6 758; GFX8-NEXT: s_and_b32 s8, s8, s6 759; GFX8-NEXT: s_lshr_b32 s1, s1, s3 760; GFX8-NEXT: s_lshr_b32 s3, s5, s8 761; GFX8-NEXT: s_lshl_b32 s2, s2, 16 762; GFX8-NEXT: s_and_b32 s0, s0, s6 763; GFX8-NEXT: s_or_b32 s0, s2, s0 764; GFX8-NEXT: s_lshl_b32 s2, s3, 16 765; GFX8-NEXT: s_and_b32 s1, s1, s6 766; GFX8-NEXT: s_or_b32 s1, s2, s1 767; GFX8-NEXT: ; return to shader part epilog 768; 769; GFX9-LABEL: s_lshr_v4i16: 770; GFX9: ; %bb.0: 771; GFX9-NEXT: s_lshr_b32 s4, s0, 16 772; GFX9-NEXT: s_lshr_b32 s5, s2, 16 773; GFX9-NEXT: s_lshr_b32 s0, s0, s2 774; GFX9-NEXT: s_lshr_b32 s2, s4, s5 775; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2 776; GFX9-NEXT: s_lshr_b32 s2, s1, 16 777; GFX9-NEXT: s_lshr_b32 s4, s3, 16 778; GFX9-NEXT: s_lshr_b32 s1, s1, s3 779; GFX9-NEXT: s_lshr_b32 s2, s2, s4 780; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2 781; GFX9-NEXT: ; return to shader part epilog 782 %result = lshr <4 x i16> %value, %amount 783 %cast = bitcast <4 x i16> %result to <2 x i32> 784 ret <2 x i32> %cast 785} 786 787; FIXME 788; define <5 x i16> @v_lshr_v5i16(<5 x i16> %value, <5 x i16> %amount) { 789; %result = lshr <5 x i16> %value, %amount 790; ret <5 x i16> %result 791; } 792 793; define amdgpu_ps <5 x i16> @s_lshr_v5i16(<5 x i16> inreg %value, <5 x i16> inreg %amount) { 794; %result = lshr <5 x i16> %value, %amount 795; ret <5 x i16> %result 796; } 797 798; define <3 x float> @v_lshr_v6i16(<6 x i16> %value, <6 x i16> %amount) { 799; %result = lshr <6 x i16> %value, %amount 800; %cast = bitcast <6 x i16> %result to <3 x float> 801; ret <3 x float> %cast 802; } 803 804; define amdgpu_ps <3 x i32> @s_lshr_v6i16(<6 x i16> inreg %value, <6 x i16> inreg %amount) { 805; %result = lshr <6 x i16> %value, %amount 806; %cast = bitcast <6 x i16> %result to <3 x i32> 807; ret <3 x i32> %cast 808; } 809 810define <4 x float> @v_lshr_v8i16(<8 x i16> %value, <8 x i16> %amount) { 811; GFX6-LABEL: v_lshr_v8i16: 812; GFX6: ; %bb.0: 813; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 814; GFX6-NEXT: s_mov_b32 s4, 0xffff 815; GFX6-NEXT: v_and_b32_e32 v8, s4, v8 816; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 817; GFX6-NEXT: v_lshrrev_b32_e32 v0, v8, v0 818; GFX6-NEXT: v_and_b32_e32 v8, s4, v9 819; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 820; GFX6-NEXT: v_lshrrev_b32_e32 v1, v8, v1 821; GFX6-NEXT: v_and_b32_e32 v8, s4, v10 822; GFX6-NEXT: v_and_b32_e32 v2, s4, v2 823; GFX6-NEXT: v_lshrrev_b32_e32 v2, v8, v2 824; GFX6-NEXT: v_and_b32_e32 v8, s4, v11 825; GFX6-NEXT: v_and_b32_e32 v3, s4, v3 826; GFX6-NEXT: v_mov_b32_e32 v16, 0xffff 827; GFX6-NEXT: v_lshrrev_b32_e32 v3, v8, v3 828; GFX6-NEXT: v_and_b32_e32 v8, s4, v12 829; GFX6-NEXT: v_and_b32_e32 v4, s4, v4 830; GFX6-NEXT: v_and_b32_e32 v1, v1, v16 831; GFX6-NEXT: v_lshrrev_b32_e32 v4, v8, v4 832; GFX6-NEXT: v_and_b32_e32 v8, s4, v13 833; GFX6-NEXT: v_and_b32_e32 v5, s4, v5 834; GFX6-NEXT: v_lshrrev_b32_e32 v5, v8, v5 835; GFX6-NEXT: v_and_b32_e32 v8, s4, v14 836; GFX6-NEXT: v_and_b32_e32 v6, s4, v6 837; GFX6-NEXT: v_and_b32_e32 v0, v0, v16 838; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 839; GFX6-NEXT: v_lshrrev_b32_e32 v6, v8, v6 840; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 841; GFX6-NEXT: v_and_b32_e32 v1, v2, v16 842; GFX6-NEXT: v_and_b32_e32 v2, v3, v16 843; GFX6-NEXT: v_and_b32_e32 v8, v15, v16 844; GFX6-NEXT: v_and_b32_e32 v7, v7, v16 845; GFX6-NEXT: v_and_b32_e32 v3, v5, v16 846; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2 847; GFX6-NEXT: v_lshrrev_b32_e32 v7, v8, v7 848; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 849; GFX6-NEXT: v_and_b32_e32 v2, v4, v16 850; GFX6-NEXT: v_and_b32_e32 v4, v7, v16 851; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3 852; GFX6-NEXT: v_or_b32_e32 v2, v2, v3 853; GFX6-NEXT: v_and_b32_e32 v3, v6, v16 854; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4 855; GFX6-NEXT: v_or_b32_e32 v3, v3, v4 856; GFX6-NEXT: s_setpc_b64 s[30:31] 857; 858; GFX8-LABEL: v_lshr_v8i16: 859; GFX8: ; %bb.0: 860; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 861; GFX8-NEXT: v_lshrrev_b16_e32 v8, v4, v0 862; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 863; GFX8-NEXT: v_lshrrev_b16_e32 v4, v5, v1 864; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 865; GFX8-NEXT: v_or_b32_e32 v1, v4, v1 866; GFX8-NEXT: v_lshrrev_b16_e32 v4, v6, v2 867; GFX8-NEXT: v_lshrrev_b16_sdwa v2, v6, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 868; GFX8-NEXT: v_or_b32_e32 v2, v4, v2 869; GFX8-NEXT: v_lshrrev_b16_e32 v4, v7, v3 870; GFX8-NEXT: v_lshrrev_b16_sdwa v3, v7, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 871; GFX8-NEXT: v_or_b32_e32 v0, v8, v0 872; GFX8-NEXT: v_or_b32_e32 v3, v4, v3 873; GFX8-NEXT: s_setpc_b64 s[30:31] 874; 875; GFX9-LABEL: v_lshr_v8i16: 876; GFX9: ; %bb.0: 877; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 878; GFX9-NEXT: v_pk_lshrrev_b16 v0, v4, v0 879; GFX9-NEXT: v_pk_lshrrev_b16 v1, v5, v1 880; GFX9-NEXT: v_pk_lshrrev_b16 v2, v6, v2 881; GFX9-NEXT: v_pk_lshrrev_b16 v3, v7, v3 882; GFX9-NEXT: s_setpc_b64 s[30:31] 883 %result = lshr <8 x i16> %value, %amount 884 %cast = bitcast <8 x i16> %result to <4 x float> 885 ret <4 x float> %cast 886} 887 888define amdgpu_ps <4 x i32> @s_lshr_v8i16(<8 x i16> inreg %value, <8 x i16> inreg %amount) { 889; GFX6-LABEL: s_lshr_v8i16: 890; GFX6: ; %bb.0: 891; GFX6-NEXT: s_mov_b32 s16, 0xffff 892; GFX6-NEXT: s_and_b32 s8, s8, s16 893; GFX6-NEXT: s_and_b32 s0, s0, s16 894; GFX6-NEXT: s_lshr_b32 s0, s0, s8 895; GFX6-NEXT: s_and_b32 s8, s9, s16 896; GFX6-NEXT: s_and_b32 s1, s1, s16 897; GFX6-NEXT: s_lshr_b32 s1, s1, s8 898; GFX6-NEXT: s_and_b32 s8, s10, s16 899; GFX6-NEXT: s_and_b32 s2, s2, s16 900; GFX6-NEXT: s_lshr_b32 s2, s2, s8 901; GFX6-NEXT: s_and_b32 s8, s11, s16 902; GFX6-NEXT: s_and_b32 s3, s3, s16 903; GFX6-NEXT: s_lshr_b32 s3, s3, s8 904; GFX6-NEXT: s_and_b32 s8, s12, s16 905; GFX6-NEXT: s_and_b32 s4, s4, s16 906; GFX6-NEXT: s_and_b32 s1, s1, s16 907; GFX6-NEXT: s_lshr_b32 s4, s4, s8 908; GFX6-NEXT: s_and_b32 s8, s13, s16 909; GFX6-NEXT: s_and_b32 s5, s5, s16 910; GFX6-NEXT: s_lshr_b32 s5, s5, s8 911; GFX6-NEXT: s_and_b32 s8, s14, s16 912; GFX6-NEXT: s_and_b32 s6, s6, s16 913; GFX6-NEXT: s_and_b32 s0, s0, s16 914; GFX6-NEXT: s_lshl_b32 s1, s1, 16 915; GFX6-NEXT: s_lshr_b32 s6, s6, s8 916; GFX6-NEXT: s_or_b32 s0, s0, s1 917; GFX6-NEXT: s_and_b32 s1, s2, s16 918; GFX6-NEXT: s_and_b32 s2, s3, s16 919; GFX6-NEXT: s_and_b32 s8, s15, s16 920; GFX6-NEXT: s_and_b32 s7, s7, s16 921; GFX6-NEXT: s_and_b32 s3, s5, s16 922; GFX6-NEXT: s_lshl_b32 s2, s2, 16 923; GFX6-NEXT: s_lshr_b32 s7, s7, s8 924; GFX6-NEXT: s_or_b32 s1, s1, s2 925; GFX6-NEXT: s_and_b32 s2, s4, s16 926; GFX6-NEXT: s_and_b32 s4, s7, s16 927; GFX6-NEXT: s_lshl_b32 s3, s3, 16 928; GFX6-NEXT: s_or_b32 s2, s2, s3 929; GFX6-NEXT: s_and_b32 s3, s6, s16 930; GFX6-NEXT: s_lshl_b32 s4, s4, 16 931; GFX6-NEXT: s_or_b32 s3, s3, s4 932; GFX6-NEXT: ; return to shader part epilog 933; 934; GFX8-LABEL: s_lshr_v8i16: 935; GFX8: ; %bb.0: 936; GFX8-NEXT: s_lshr_b32 s8, s0, 16 937; GFX8-NEXT: s_mov_b32 s12, 0xffff 938; GFX8-NEXT: s_lshr_b32 s13, s4, 16 939; GFX8-NEXT: s_lshr_b32 s9, s1, 16 940; GFX8-NEXT: s_lshr_b32 s14, s5, 16 941; GFX8-NEXT: s_and_b32 s0, s0, s12 942; GFX8-NEXT: s_and_b32 s4, s4, s12 943; GFX8-NEXT: s_and_b32 s8, s8, s12 944; GFX8-NEXT: s_and_b32 s13, s13, s12 945; GFX8-NEXT: s_lshr_b32 s10, s2, 16 946; GFX8-NEXT: s_lshr_b32 s15, s6, 16 947; GFX8-NEXT: s_lshr_b32 s0, s0, s4 948; GFX8-NEXT: s_lshr_b32 s4, s8, s13 949; GFX8-NEXT: s_and_b32 s1, s1, s12 950; GFX8-NEXT: s_and_b32 s5, s5, s12 951; GFX8-NEXT: s_and_b32 s9, s9, s12 952; GFX8-NEXT: s_and_b32 s14, s14, s12 953; GFX8-NEXT: s_lshr_b32 s11, s3, 16 954; GFX8-NEXT: s_lshr_b32 s16, s7, 16 955; GFX8-NEXT: s_lshr_b32 s1, s1, s5 956; GFX8-NEXT: s_and_b32 s2, s2, s12 957; GFX8-NEXT: s_and_b32 s6, s6, s12 958; GFX8-NEXT: s_and_b32 s10, s10, s12 959; GFX8-NEXT: s_and_b32 s15, s15, s12 960; GFX8-NEXT: s_lshr_b32 s5, s9, s14 961; GFX8-NEXT: s_lshl_b32 s4, s4, 16 962; GFX8-NEXT: s_and_b32 s0, s0, s12 963; GFX8-NEXT: s_lshr_b32 s2, s2, s6 964; GFX8-NEXT: s_or_b32 s0, s4, s0 965; GFX8-NEXT: s_and_b32 s3, s3, s12 966; GFX8-NEXT: s_and_b32 s7, s7, s12 967; GFX8-NEXT: s_and_b32 s11, s11, s12 968; GFX8-NEXT: s_and_b32 s16, s16, s12 969; GFX8-NEXT: s_lshr_b32 s6, s10, s15 970; GFX8-NEXT: s_lshl_b32 s4, s5, 16 971; GFX8-NEXT: s_and_b32 s1, s1, s12 972; GFX8-NEXT: s_lshr_b32 s3, s3, s7 973; GFX8-NEXT: s_or_b32 s1, s4, s1 974; GFX8-NEXT: s_lshr_b32 s7, s11, s16 975; GFX8-NEXT: s_lshl_b32 s4, s6, 16 976; GFX8-NEXT: s_and_b32 s2, s2, s12 977; GFX8-NEXT: s_or_b32 s2, s4, s2 978; GFX8-NEXT: s_lshl_b32 s4, s7, 16 979; GFX8-NEXT: s_and_b32 s3, s3, s12 980; GFX8-NEXT: s_or_b32 s3, s4, s3 981; GFX8-NEXT: ; return to shader part epilog 982; 983; GFX9-LABEL: s_lshr_v8i16: 984; GFX9: ; %bb.0: 985; GFX9-NEXT: s_lshr_b32 s8, s0, 16 986; GFX9-NEXT: s_lshr_b32 s9, s4, 16 987; GFX9-NEXT: s_lshr_b32 s0, s0, s4 988; GFX9-NEXT: s_lshr_b32 s4, s8, s9 989; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s4 990; GFX9-NEXT: s_lshr_b32 s4, s1, 16 991; GFX9-NEXT: s_lshr_b32 s8, s5, 16 992; GFX9-NEXT: s_lshr_b32 s1, s1, s5 993; GFX9-NEXT: s_lshr_b32 s4, s4, s8 994; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4 995; GFX9-NEXT: s_lshr_b32 s4, s2, 16 996; GFX9-NEXT: s_lshr_b32 s5, s6, 16 997; GFX9-NEXT: s_lshr_b32 s4, s4, s5 998; GFX9-NEXT: s_lshr_b32 s2, s2, s6 999; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4 1000; GFX9-NEXT: s_lshr_b32 s4, s3, 16 1001; GFX9-NEXT: s_lshr_b32 s5, s7, 16 1002; GFX9-NEXT: s_lshr_b32 s3, s3, s7 1003; GFX9-NEXT: s_lshr_b32 s4, s4, s5 1004; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4 1005; GFX9-NEXT: ; return to shader part epilog 1006 %result = lshr <8 x i16> %value, %amount 1007 %cast = bitcast <8 x i16> %result to <4 x i32> 1008 ret <4 x i32> %cast 1009} 1010 1011define i64 @v_lshr_i64(i64 %value, i64 %amount) { 1012; GFX6-LABEL: v_lshr_i64: 1013; GFX6: ; %bb.0: 1014; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1015; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], v2 1016; GFX6-NEXT: s_setpc_b64 s[30:31] 1017; 1018; GFX8-LABEL: v_lshr_i64: 1019; GFX8: ; %bb.0: 1020; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1021; GFX8-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 1022; GFX8-NEXT: s_setpc_b64 s[30:31] 1023; 1024; GFX9-LABEL: v_lshr_i64: 1025; GFX9: ; %bb.0: 1026; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1027; GFX9-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 1028; GFX9-NEXT: s_setpc_b64 s[30:31] 1029 %result = lshr i64 %value, %amount 1030 ret i64 %result 1031} 1032 1033define i64 @v_lshr_i64_63(i64 %value) { 1034; GCN-LABEL: v_lshr_i64_63: 1035; GCN: ; %bb.0: 1036; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1037; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v1 1038; GCN-NEXT: v_mov_b32_e32 v1, 0 1039; GCN-NEXT: s_setpc_b64 s[30:31] 1040 %result = lshr i64 %value, 63 1041 ret i64 %result 1042} 1043 1044define i64 @v_lshr_i64_33(i64 %value) { 1045; GCN-LABEL: v_lshr_i64_33: 1046; GCN: ; %bb.0: 1047; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1048; GCN-NEXT: v_lshrrev_b32_e32 v0, 1, v1 1049; GCN-NEXT: v_mov_b32_e32 v1, 0 1050; GCN-NEXT: s_setpc_b64 s[30:31] 1051 %result = lshr i64 %value, 33 1052 ret i64 %result 1053} 1054 1055define i64 @v_lshr_i64_32(i64 %value) { 1056; GCN-LABEL: v_lshr_i64_32: 1057; GCN: ; %bb.0: 1058; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1059; GCN-NEXT: v_mov_b32_e32 v0, v1 1060; GCN-NEXT: v_mov_b32_e32 v1, 0 1061; GCN-NEXT: s_setpc_b64 s[30:31] 1062 %result = lshr i64 %value, 32 1063 ret i64 %result 1064} 1065 1066define i64 @v_lshr_i64_31(i64 %value) { 1067; GFX6-LABEL: v_lshr_i64_31: 1068; GFX6: ; %bb.0: 1069; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1070; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 31 1071; GFX6-NEXT: s_setpc_b64 s[30:31] 1072; 1073; GFX8-LABEL: v_lshr_i64_31: 1074; GFX8: ; %bb.0: 1075; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1076; GFX8-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1077; GFX8-NEXT: s_setpc_b64 s[30:31] 1078; 1079; GFX9-LABEL: v_lshr_i64_31: 1080; GFX9: ; %bb.0: 1081; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1082; GFX9-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1083; GFX9-NEXT: s_setpc_b64 s[30:31] 1084 %result = lshr i64 %value, 31 1085 ret i64 %result 1086} 1087 1088define amdgpu_ps i64 @s_lshr_i64(i64 inreg %value, i64 inreg %amount) { 1089; GCN-LABEL: s_lshr_i64: 1090; GCN: ; %bb.0: 1091; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], s2 1092; GCN-NEXT: ; return to shader part epilog 1093 %result = lshr i64 %value, %amount 1094 ret i64 %result 1095} 1096 1097define amdgpu_ps i64 @s_lshr_i64_63(i64 inreg %value) { 1098; GCN-LABEL: s_lshr_i64_63: 1099; GCN: ; %bb.0: 1100; GCN-NEXT: s_lshr_b32 s0, s1, 31 1101; GCN-NEXT: s_mov_b32 s1, 0 1102; GCN-NEXT: ; return to shader part epilog 1103 %result = lshr i64 %value, 63 1104 ret i64 %result 1105} 1106 1107define amdgpu_ps i64 @s_lshr_i64_33(i64 inreg %value) { 1108; GCN-LABEL: s_lshr_i64_33: 1109; GCN: ; %bb.0: 1110; GCN-NEXT: s_lshr_b32 s0, s1, 1 1111; GCN-NEXT: s_mov_b32 s1, 0 1112; GCN-NEXT: ; return to shader part epilog 1113 %result = lshr i64 %value, 33 1114 ret i64 %result 1115} 1116 1117define amdgpu_ps i64 @s_lshr_i64_32(i64 inreg %value) { 1118; GCN-LABEL: s_lshr_i64_32: 1119; GCN: ; %bb.0: 1120; GCN-NEXT: s_mov_b32 s0, s1 1121; GCN-NEXT: s_mov_b32 s1, 0 1122; GCN-NEXT: ; return to shader part epilog 1123 %result = lshr i64 %value, 32 1124 ret i64 %result 1125} 1126 1127define amdgpu_ps i64 @s_lshr_i64_31(i64 inreg %value) { 1128; GCN-LABEL: s_lshr_i64_31: 1129; GCN: ; %bb.0: 1130; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], 31 1131; GCN-NEXT: ; return to shader part epilog 1132 %result = lshr i64 %value, 31 1133 ret i64 %result 1134} 1135 1136define amdgpu_ps <2 x float> @lshr_i64_sv(i64 inreg %value, i64 %amount) { 1137; GFX6-LABEL: lshr_i64_sv: 1138; GFX6: ; %bb.0: 1139; GFX6-NEXT: v_lshr_b64 v[0:1], s[0:1], v0 1140; GFX6-NEXT: ; return to shader part epilog 1141; 1142; GFX8-LABEL: lshr_i64_sv: 1143; GFX8: ; %bb.0: 1144; GFX8-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1] 1145; GFX8-NEXT: ; return to shader part epilog 1146; 1147; GFX9-LABEL: lshr_i64_sv: 1148; GFX9: ; %bb.0: 1149; GFX9-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1] 1150; GFX9-NEXT: ; return to shader part epilog 1151 %result = lshr i64 %value, %amount 1152 %cast = bitcast i64 %result to <2 x float> 1153 ret <2 x float> %cast 1154} 1155 1156define amdgpu_ps <2 x float> @lshr_i64_vs(i64 %value, i64 inreg %amount) { 1157; GFX6-LABEL: lshr_i64_vs: 1158; GFX6: ; %bb.0: 1159; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], s0 1160; GFX6-NEXT: ; return to shader part epilog 1161; 1162; GFX8-LABEL: lshr_i64_vs: 1163; GFX8: ; %bb.0: 1164; GFX8-NEXT: v_lshrrev_b64 v[0:1], s0, v[0:1] 1165; GFX8-NEXT: ; return to shader part epilog 1166; 1167; GFX9-LABEL: lshr_i64_vs: 1168; GFX9: ; %bb.0: 1169; GFX9-NEXT: v_lshrrev_b64 v[0:1], s0, v[0:1] 1170; GFX9-NEXT: ; return to shader part epilog 1171 %result = lshr i64 %value, %amount 1172 %cast = bitcast i64 %result to <2 x float> 1173 ret <2 x float> %cast 1174} 1175 1176define <2 x i64> @v_lshr_v2i64(<2 x i64> %value, <2 x i64> %amount) { 1177; GFX6-LABEL: v_lshr_v2i64: 1178; GFX6: ; %bb.0: 1179; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1180; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], v4 1181; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], v6 1182; GFX6-NEXT: s_setpc_b64 s[30:31] 1183; 1184; GFX8-LABEL: v_lshr_v2i64: 1185; GFX8: ; %bb.0: 1186; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1187; GFX8-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1] 1188; GFX8-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3] 1189; GFX8-NEXT: s_setpc_b64 s[30:31] 1190; 1191; GFX9-LABEL: v_lshr_v2i64: 1192; GFX9: ; %bb.0: 1193; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1194; GFX9-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1] 1195; GFX9-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3] 1196; GFX9-NEXT: s_setpc_b64 s[30:31] 1197 %result = lshr <2 x i64> %value, %amount 1198 ret <2 x i64> %result 1199} 1200 1201define <2 x i64> @v_lshr_v2i64_31(<2 x i64> %value) { 1202; GFX6-LABEL: v_lshr_v2i64_31: 1203; GFX6: ; %bb.0: 1204; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1205; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 31 1206; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], 31 1207; GFX6-NEXT: s_setpc_b64 s[30:31] 1208; 1209; GFX8-LABEL: v_lshr_v2i64_31: 1210; GFX8: ; %bb.0: 1211; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1212; GFX8-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1213; GFX8-NEXT: v_lshrrev_b64 v[2:3], 31, v[2:3] 1214; GFX8-NEXT: s_setpc_b64 s[30:31] 1215; 1216; GFX9-LABEL: v_lshr_v2i64_31: 1217; GFX9: ; %bb.0: 1218; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1219; GFX9-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1220; GFX9-NEXT: v_lshrrev_b64 v[2:3], 31, v[2:3] 1221; GFX9-NEXT: s_setpc_b64 s[30:31] 1222 %result = lshr <2 x i64> %value, <i64 31, i64 31> 1223 ret <2 x i64> %result 1224} 1225 1226define amdgpu_ps <2 x i64> @s_lshr_v2i64(<2 x i64> inreg %value, <2 x i64> inreg %amount) { 1227; GCN-LABEL: s_lshr_v2i64: 1228; GCN: ; %bb.0: 1229; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], s4 1230; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], s6 1231; GCN-NEXT: ; return to shader part epilog 1232 %result = lshr <2 x i64> %value, %amount 1233 ret <2 x i64> %result 1234} 1235