1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s 3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s 4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s 5; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s 6 7define i8 @v_lshr_i8(i8 %value, i8 %amount) { 8; GFX6-LABEL: v_lshr_i8: 9; GFX6: ; %bb.0: 10; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 11; GFX6-NEXT: s_movk_i32 s4, 0xff 12; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 13; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 14; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0 15; GFX6-NEXT: s_setpc_b64 s[30:31] 16; 17; GFX8-LABEL: v_lshr_i8: 18; GFX8: ; %bb.0: 19; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 20; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 21; GFX8-NEXT: s_setpc_b64 s[30:31] 22; 23; GFX9-LABEL: v_lshr_i8: 24; GFX9: ; %bb.0: 25; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 26; GFX9-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 27; GFX9-NEXT: s_setpc_b64 s[30:31] 28; 29; GFX10-LABEL: v_lshr_i8: 30; GFX10: ; %bb.0: 31; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 32; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 33; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1 34; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0 35; GFX10-NEXT: v_lshrrev_b16 v0, v1, v0 36; GFX10-NEXT: s_setpc_b64 s[30:31] 37 %result = lshr i8 %value, %amount 38 ret i8 %result 39} 40 41define i8 @v_lshr_i8_7(i8 %value) { 42; GFX6-LABEL: v_lshr_i8_7: 43; GFX6: ; %bb.0: 44; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 45; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0 46; GFX6-NEXT: v_lshrrev_b32_e32 v0, 7, v0 47; GFX6-NEXT: s_setpc_b64 s[30:31] 48; 49; GFX8-LABEL: v_lshr_i8_7: 50; GFX8: ; %bb.0: 51; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 52; GFX8-NEXT: v_mov_b32_e32 v1, 7 53; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 54; GFX8-NEXT: s_setpc_b64 s[30:31] 55; 56; GFX9-LABEL: v_lshr_i8_7: 57; GFX9: ; %bb.0: 58; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 59; GFX9-NEXT: v_mov_b32_e32 v1, 7 60; GFX9-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 61; GFX9-NEXT: s_setpc_b64 s[30:31] 62; 63; GFX10-LABEL: v_lshr_i8_7: 64; GFX10: ; %bb.0: 65; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 66; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 67; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0 68; GFX10-NEXT: v_lshrrev_b16 v0, 7, v0 69; GFX10-NEXT: s_setpc_b64 s[30:31] 70 %result = lshr i8 %value, 7 71 ret i8 %result 72} 73 74define amdgpu_ps i8 @s_lshr_i8(i8 inreg %value, i8 inreg %amount) { 75; GFX6-LABEL: s_lshr_i8: 76; GFX6: ; %bb.0: 77; GFX6-NEXT: s_movk_i32 s2, 0xff 78; GFX6-NEXT: s_and_b32 s1, s1, s2 79; GFX6-NEXT: s_and_b32 s0, s0, s2 80; GFX6-NEXT: s_lshr_b32 s0, s0, s1 81; GFX6-NEXT: ; return to shader part epilog 82; 83; GFX8-LABEL: s_lshr_i8: 84; GFX8: ; %bb.0: 85; GFX8-NEXT: s_movk_i32 s2, 0xff 86; GFX8-NEXT: s_and_b32 s0, s0, s2 87; GFX8-NEXT: s_and_b32 s1, s1, s2 88; GFX8-NEXT: s_lshr_b32 s0, s0, s1 89; GFX8-NEXT: ; return to shader part epilog 90; 91; GFX9-LABEL: s_lshr_i8: 92; GFX9: ; %bb.0: 93; GFX9-NEXT: s_movk_i32 s2, 0xff 94; GFX9-NEXT: s_and_b32 s0, s0, s2 95; GFX9-NEXT: s_and_b32 s1, s1, s2 96; GFX9-NEXT: s_lshr_b32 s0, s0, s1 97; GFX9-NEXT: ; return to shader part epilog 98; 99; GFX10-LABEL: s_lshr_i8: 100; GFX10: ; %bb.0: 101; GFX10-NEXT: s_movk_i32 s2, 0xff 102; GFX10-NEXT: s_and_b32 s0, s0, s2 103; GFX10-NEXT: s_and_b32 s1, s1, s2 104; GFX10-NEXT: s_lshr_b32 s0, s0, s1 105; GFX10-NEXT: ; return to shader part epilog 106 %result = lshr i8 %value, %amount 107 ret i8 %result 108} 109 110define amdgpu_ps i8 @s_lshr_i8_7(i8 inreg %value) { 111; GCN-LABEL: s_lshr_i8_7: 112; GCN: ; %bb.0: 113; GCN-NEXT: s_and_b32 s0, s0, 0xff 114; GCN-NEXT: s_lshr_b32 s0, s0, 7 115; GCN-NEXT: ; return to shader part epilog 116; 117; GFX10-LABEL: s_lshr_i8_7: 118; GFX10: ; %bb.0: 119; GFX10-NEXT: s_and_b32 s0, s0, 0xff 120; GFX10-NEXT: s_lshr_b32 s0, s0, 7 121; GFX10-NEXT: ; return to shader part epilog 122 %result = lshr i8 %value, 7 123 ret i8 %result 124} 125 126 127define i24 @v_lshr_i24(i24 %value, i24 %amount) { 128; GCN-LABEL: v_lshr_i24: 129; GCN: ; %bb.0: 130; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 131; GCN-NEXT: s_mov_b32 s4, 0xffffff 132; GCN-NEXT: v_and_b32_e32 v1, s4, v1 133; GCN-NEXT: v_and_b32_e32 v0, s4, v0 134; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0 135; GCN-NEXT: s_setpc_b64 s[30:31] 136; 137; GFX10-LABEL: v_lshr_i24: 138; GFX10: ; %bb.0: 139; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 140; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 141; GFX10-NEXT: s_mov_b32 s4, 0xffffff 142; GFX10-NEXT: v_and_b32_e32 v1, s4, v1 143; GFX10-NEXT: v_and_b32_e32 v0, s4, v0 144; GFX10-NEXT: v_lshrrev_b32_e32 v0, v1, v0 145; GFX10-NEXT: s_setpc_b64 s[30:31] 146 %result = lshr i24 %value, %amount 147 ret i24 %result 148} 149 150define i24 @v_lshr_i24_7(i24 %value) { 151; GCN-LABEL: v_lshr_i24_7: 152; GCN: ; %bb.0: 153; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 154; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 155; GCN-NEXT: v_lshrrev_b32_e32 v0, 7, v0 156; GCN-NEXT: s_setpc_b64 s[30:31] 157; 158; GFX10-LABEL: v_lshr_i24_7: 159; GFX10: ; %bb.0: 160; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 161; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 162; GFX10-NEXT: v_and_b32_e32 v0, 0xffffff, v0 163; GFX10-NEXT: v_lshrrev_b32_e32 v0, 7, v0 164; GFX10-NEXT: s_setpc_b64 s[30:31] 165 %result = lshr i24 %value, 7 166 ret i24 %result 167} 168 169define amdgpu_ps i24 @s_lshr_i24(i24 inreg %value, i24 inreg %amount) { 170; GCN-LABEL: s_lshr_i24: 171; GCN: ; %bb.0: 172; GCN-NEXT: s_mov_b32 s2, 0xffffff 173; GCN-NEXT: s_and_b32 s1, s1, s2 174; GCN-NEXT: s_and_b32 s0, s0, s2 175; GCN-NEXT: s_lshr_b32 s0, s0, s1 176; GCN-NEXT: ; return to shader part epilog 177; 178; GFX10-LABEL: s_lshr_i24: 179; GFX10: ; %bb.0: 180; GFX10-NEXT: s_mov_b32 s2, 0xffffff 181; GFX10-NEXT: s_and_b32 s1, s1, s2 182; GFX10-NEXT: s_and_b32 s0, s0, s2 183; GFX10-NEXT: s_lshr_b32 s0, s0, s1 184; GFX10-NEXT: ; return to shader part epilog 185 %result = lshr i24 %value, %amount 186 ret i24 %result 187} 188 189define amdgpu_ps i24 @s_lshr_i24_7(i24 inreg %value) { 190; GCN-LABEL: s_lshr_i24_7: 191; GCN: ; %bb.0: 192; GCN-NEXT: s_and_b32 s0, s0, 0xffffff 193; GCN-NEXT: s_lshr_b32 s0, s0, 7 194; GCN-NEXT: ; return to shader part epilog 195; 196; GFX10-LABEL: s_lshr_i24_7: 197; GFX10: ; %bb.0: 198; GFX10-NEXT: s_and_b32 s0, s0, 0xffffff 199; GFX10-NEXT: s_lshr_b32 s0, s0, 7 200; GFX10-NEXT: ; return to shader part epilog 201 %result = lshr i24 %value, 7 202 ret i24 %result 203} 204 205define i32 @v_lshr_i32(i32 %value, i32 %amount) { 206; GCN-LABEL: v_lshr_i32: 207; GCN: ; %bb.0: 208; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 209; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0 210; GCN-NEXT: s_setpc_b64 s[30:31] 211; 212; GFX10-LABEL: v_lshr_i32: 213; GFX10: ; %bb.0: 214; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 215; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 216; GFX10-NEXT: v_lshrrev_b32_e32 v0, v1, v0 217; GFX10-NEXT: s_setpc_b64 s[30:31] 218 %result = lshr i32 %value, %amount 219 ret i32 %result 220} 221 222define i32 @v_lshr_i32_31(i32 %value) { 223; GCN-LABEL: v_lshr_i32_31: 224; GCN: ; %bb.0: 225; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 226; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0 227; GCN-NEXT: s_setpc_b64 s[30:31] 228; 229; GFX10-LABEL: v_lshr_i32_31: 230; GFX10: ; %bb.0: 231; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 232; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 233; GFX10-NEXT: v_lshrrev_b32_e32 v0, 31, v0 234; GFX10-NEXT: s_setpc_b64 s[30:31] 235 %result = lshr i32 %value, 31 236 ret i32 %result 237} 238 239define amdgpu_ps i32 @s_lshr_i32(i32 inreg %value, i32 inreg %amount) { 240; GCN-LABEL: s_lshr_i32: 241; GCN: ; %bb.0: 242; GCN-NEXT: s_lshr_b32 s0, s0, s1 243; GCN-NEXT: ; return to shader part epilog 244; 245; GFX10-LABEL: s_lshr_i32: 246; GFX10: ; %bb.0: 247; GFX10-NEXT: s_lshr_b32 s0, s0, s1 248; GFX10-NEXT: ; return to shader part epilog 249 %result = lshr i32 %value, %amount 250 ret i32 %result 251} 252 253define amdgpu_ps i32 @s_lshr_i32_31(i32 inreg %value) { 254; GCN-LABEL: s_lshr_i32_31: 255; GCN: ; %bb.0: 256; GCN-NEXT: s_lshr_b32 s0, s0, 31 257; GCN-NEXT: ; return to shader part epilog 258; 259; GFX10-LABEL: s_lshr_i32_31: 260; GFX10: ; %bb.0: 261; GFX10-NEXT: s_lshr_b32 s0, s0, 31 262; GFX10-NEXT: ; return to shader part epilog 263 %result = lshr i32 %value, 31 264 ret i32 %result 265} 266 267define amdgpu_ps float @lshr_i32_sv(i32 inreg %value, i32 %amount) { 268; GFX6-LABEL: lshr_i32_sv: 269; GFX6: ; %bb.0: 270; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0 271; GFX6-NEXT: ; return to shader part epilog 272; 273; GFX8-LABEL: lshr_i32_sv: 274; GFX8: ; %bb.0: 275; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s0 276; GFX8-NEXT: ; return to shader part epilog 277; 278; GFX9-LABEL: lshr_i32_sv: 279; GFX9: ; %bb.0: 280; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s0 281; GFX9-NEXT: ; return to shader part epilog 282; 283; GFX10-LABEL: lshr_i32_sv: 284; GFX10: ; %bb.0: 285; GFX10-NEXT: v_lshrrev_b32_e64 v0, v0, s0 286; GFX10-NEXT: ; return to shader part epilog 287 %result = lshr i32 %value, %amount 288 %cast = bitcast i32 %result to float 289 ret float %cast 290} 291 292define amdgpu_ps float @lshr_i32_vs(i32 %value, i32 inreg %amount) { 293; GCN-LABEL: lshr_i32_vs: 294; GCN: ; %bb.0: 295; GCN-NEXT: v_lshrrev_b32_e32 v0, s0, v0 296; GCN-NEXT: ; return to shader part epilog 297; 298; GFX10-LABEL: lshr_i32_vs: 299; GFX10: ; %bb.0: 300; GFX10-NEXT: v_lshrrev_b32_e32 v0, s0, v0 301; GFX10-NEXT: ; return to shader part epilog 302 %result = lshr i32 %value, %amount 303 %cast = bitcast i32 %result to float 304 ret float %cast 305} 306 307define <2 x i32> @v_lshr_v2i32(<2 x i32> %value, <2 x i32> %amount) { 308; GCN-LABEL: v_lshr_v2i32: 309; GCN: ; %bb.0: 310; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 311; GCN-NEXT: v_lshrrev_b32_e32 v0, v2, v0 312; GCN-NEXT: v_lshrrev_b32_e32 v1, v3, v1 313; GCN-NEXT: s_setpc_b64 s[30:31] 314; 315; GFX10-LABEL: v_lshr_v2i32: 316; GFX10: ; %bb.0: 317; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 318; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 319; GFX10-NEXT: v_lshrrev_b32_e32 v0, v2, v0 320; GFX10-NEXT: v_lshrrev_b32_e32 v1, v3, v1 321; GFX10-NEXT: s_setpc_b64 s[30:31] 322 %result = lshr <2 x i32> %value, %amount 323 ret <2 x i32> %result 324} 325 326define <2 x i32> @v_lshr_v2i32_31(<2 x i32> %value) { 327; GCN-LABEL: v_lshr_v2i32_31: 328; GCN: ; %bb.0: 329; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 330; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0 331; GCN-NEXT: v_lshrrev_b32_e32 v1, 31, v1 332; GCN-NEXT: s_setpc_b64 s[30:31] 333; 334; GFX10-LABEL: v_lshr_v2i32_31: 335; GFX10: ; %bb.0: 336; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 337; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 338; GFX10-NEXT: v_lshrrev_b32_e32 v0, 31, v0 339; GFX10-NEXT: v_lshrrev_b32_e32 v1, 31, v1 340; GFX10-NEXT: s_setpc_b64 s[30:31] 341 %result = lshr <2 x i32> %value, <i32 31, i32 31> 342 ret <2 x i32> %result 343} 344 345define amdgpu_ps <2 x i32> @s_lshr_v2i32(<2 x i32> inreg %value, <2 x i32> inreg %amount) { 346; GCN-LABEL: s_lshr_v2i32: 347; GCN: ; %bb.0: 348; GCN-NEXT: s_lshr_b32 s0, s0, s2 349; GCN-NEXT: s_lshr_b32 s1, s1, s3 350; GCN-NEXT: ; return to shader part epilog 351; 352; GFX10-LABEL: s_lshr_v2i32: 353; GFX10: ; %bb.0: 354; GFX10-NEXT: s_lshr_b32 s0, s0, s2 355; GFX10-NEXT: s_lshr_b32 s1, s1, s3 356; GFX10-NEXT: ; return to shader part epilog 357 %result = lshr <2 x i32> %value, %amount 358 ret <2 x i32> %result 359} 360 361define <3 x i32> @v_lshr_v3i32(<3 x i32> %value, <3 x i32> %amount) { 362; GCN-LABEL: v_lshr_v3i32: 363; GCN: ; %bb.0: 364; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 365; GCN-NEXT: v_lshrrev_b32_e32 v0, v3, v0 366; GCN-NEXT: v_lshrrev_b32_e32 v1, v4, v1 367; GCN-NEXT: v_lshrrev_b32_e32 v2, v5, v2 368; GCN-NEXT: s_setpc_b64 s[30:31] 369; 370; GFX10-LABEL: v_lshr_v3i32: 371; GFX10: ; %bb.0: 372; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 373; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 374; GFX10-NEXT: v_lshrrev_b32_e32 v0, v3, v0 375; GFX10-NEXT: v_lshrrev_b32_e32 v1, v4, v1 376; GFX10-NEXT: v_lshrrev_b32_e32 v2, v5, v2 377; GFX10-NEXT: s_setpc_b64 s[30:31] 378 %result = lshr <3 x i32> %value, %amount 379 ret <3 x i32> %result 380} 381 382define amdgpu_ps <3 x i32> @s_lshr_v3i32(<3 x i32> inreg %value, <3 x i32> inreg %amount) { 383; GCN-LABEL: s_lshr_v3i32: 384; GCN: ; %bb.0: 385; GCN-NEXT: s_lshr_b32 s0, s0, s3 386; GCN-NEXT: s_lshr_b32 s1, s1, s4 387; GCN-NEXT: s_lshr_b32 s2, s2, s5 388; GCN-NEXT: ; return to shader part epilog 389; 390; GFX10-LABEL: s_lshr_v3i32: 391; GFX10: ; %bb.0: 392; GFX10-NEXT: s_lshr_b32 s0, s0, s3 393; GFX10-NEXT: s_lshr_b32 s1, s1, s4 394; GFX10-NEXT: s_lshr_b32 s2, s2, s5 395; GFX10-NEXT: ; return to shader part epilog 396 %result = lshr <3 x i32> %value, %amount 397 ret <3 x i32> %result 398} 399 400define <4 x i32> @v_lshr_v4i32(<4 x i32> %value, <4 x i32> %amount) { 401; GCN-LABEL: v_lshr_v4i32: 402; GCN: ; %bb.0: 403; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 404; GCN-NEXT: v_lshrrev_b32_e32 v0, v4, v0 405; GCN-NEXT: v_lshrrev_b32_e32 v1, v5, v1 406; GCN-NEXT: v_lshrrev_b32_e32 v2, v6, v2 407; GCN-NEXT: v_lshrrev_b32_e32 v3, v7, v3 408; GCN-NEXT: s_setpc_b64 s[30:31] 409; 410; GFX10-LABEL: v_lshr_v4i32: 411; GFX10: ; %bb.0: 412; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 413; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 414; GFX10-NEXT: v_lshrrev_b32_e32 v0, v4, v0 415; GFX10-NEXT: v_lshrrev_b32_e32 v1, v5, v1 416; GFX10-NEXT: v_lshrrev_b32_e32 v2, v6, v2 417; GFX10-NEXT: v_lshrrev_b32_e32 v3, v7, v3 418; GFX10-NEXT: s_setpc_b64 s[30:31] 419 %result = lshr <4 x i32> %value, %amount 420 ret <4 x i32> %result 421} 422 423define amdgpu_ps <4 x i32> @s_lshr_v4i32(<4 x i32> inreg %value, <4 x i32> inreg %amount) { 424; GCN-LABEL: s_lshr_v4i32: 425; GCN: ; %bb.0: 426; GCN-NEXT: s_lshr_b32 s0, s0, s4 427; GCN-NEXT: s_lshr_b32 s1, s1, s5 428; GCN-NEXT: s_lshr_b32 s2, s2, s6 429; GCN-NEXT: s_lshr_b32 s3, s3, s7 430; GCN-NEXT: ; return to shader part epilog 431; 432; GFX10-LABEL: s_lshr_v4i32: 433; GFX10: ; %bb.0: 434; GFX10-NEXT: s_lshr_b32 s0, s0, s4 435; GFX10-NEXT: s_lshr_b32 s1, s1, s5 436; GFX10-NEXT: s_lshr_b32 s2, s2, s6 437; GFX10-NEXT: s_lshr_b32 s3, s3, s7 438; GFX10-NEXT: ; return to shader part epilog 439 %result = lshr <4 x i32> %value, %amount 440 ret <4 x i32> %result 441} 442 443define <5 x i32> @v_lshr_v5i32(<5 x i32> %value, <5 x i32> %amount) { 444; GCN-LABEL: v_lshr_v5i32: 445; GCN: ; %bb.0: 446; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 447; GCN-NEXT: v_lshrrev_b32_e32 v0, v5, v0 448; GCN-NEXT: v_lshrrev_b32_e32 v1, v6, v1 449; GCN-NEXT: v_lshrrev_b32_e32 v2, v7, v2 450; GCN-NEXT: v_lshrrev_b32_e32 v3, v8, v3 451; GCN-NEXT: v_lshrrev_b32_e32 v4, v9, v4 452; GCN-NEXT: s_setpc_b64 s[30:31] 453; 454; GFX10-LABEL: v_lshr_v5i32: 455; GFX10: ; %bb.0: 456; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 457; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 458; GFX10-NEXT: v_lshrrev_b32_e32 v0, v5, v0 459; GFX10-NEXT: v_lshrrev_b32_e32 v1, v6, v1 460; GFX10-NEXT: v_lshrrev_b32_e32 v2, v7, v2 461; GFX10-NEXT: v_lshrrev_b32_e32 v3, v8, v3 462; GFX10-NEXT: v_lshrrev_b32_e32 v4, v9, v4 463; GFX10-NEXT: s_setpc_b64 s[30:31] 464 %result = lshr <5 x i32> %value, %amount 465 ret <5 x i32> %result 466} 467 468define amdgpu_ps <5 x i32> @s_lshr_v5i32(<5 x i32> inreg %value, <5 x i32> inreg %amount) { 469; GCN-LABEL: s_lshr_v5i32: 470; GCN: ; %bb.0: 471; GCN-NEXT: s_lshr_b32 s0, s0, s5 472; GCN-NEXT: s_lshr_b32 s1, s1, s6 473; GCN-NEXT: s_lshr_b32 s2, s2, s7 474; GCN-NEXT: s_lshr_b32 s3, s3, s8 475; GCN-NEXT: s_lshr_b32 s4, s4, s9 476; GCN-NEXT: ; return to shader part epilog 477; 478; GFX10-LABEL: s_lshr_v5i32: 479; GFX10: ; %bb.0: 480; GFX10-NEXT: s_lshr_b32 s0, s0, s5 481; GFX10-NEXT: s_lshr_b32 s1, s1, s6 482; GFX10-NEXT: s_lshr_b32 s2, s2, s7 483; GFX10-NEXT: s_lshr_b32 s3, s3, s8 484; GFX10-NEXT: s_lshr_b32 s4, s4, s9 485; GFX10-NEXT: ; return to shader part epilog 486 %result = lshr <5 x i32> %value, %amount 487 ret <5 x i32> %result 488} 489 490define <16 x i32> @v_lshr_v16i32(<16 x i32> %value, <16 x i32> %amount) { 491; GCN-LABEL: v_lshr_v16i32: 492; GCN: ; %bb.0: 493; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 494; GCN-NEXT: v_lshrrev_b32_e32 v0, v16, v0 495; GCN-NEXT: v_lshrrev_b32_e32 v1, v17, v1 496; GCN-NEXT: v_lshrrev_b32_e32 v2, v18, v2 497; GCN-NEXT: v_lshrrev_b32_e32 v3, v19, v3 498; GCN-NEXT: v_lshrrev_b32_e32 v4, v20, v4 499; GCN-NEXT: v_lshrrev_b32_e32 v5, v21, v5 500; GCN-NEXT: v_lshrrev_b32_e32 v6, v22, v6 501; GCN-NEXT: v_lshrrev_b32_e32 v7, v23, v7 502; GCN-NEXT: v_lshrrev_b32_e32 v8, v24, v8 503; GCN-NEXT: v_lshrrev_b32_e32 v9, v25, v9 504; GCN-NEXT: v_lshrrev_b32_e32 v10, v26, v10 505; GCN-NEXT: v_lshrrev_b32_e32 v11, v27, v11 506; GCN-NEXT: v_lshrrev_b32_e32 v12, v28, v12 507; GCN-NEXT: v_lshrrev_b32_e32 v13, v29, v13 508; GCN-NEXT: v_lshrrev_b32_e32 v14, v30, v14 509; GCN-NEXT: v_lshrrev_b32_e32 v15, v31, v15 510; GCN-NEXT: s_setpc_b64 s[30:31] 511; 512; GFX10-LABEL: v_lshr_v16i32: 513; GFX10: ; %bb.0: 514; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 515; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 516; GFX10-NEXT: v_lshrrev_b32_e32 v0, v16, v0 517; GFX10-NEXT: v_lshrrev_b32_e32 v1, v17, v1 518; GFX10-NEXT: v_lshrrev_b32_e32 v2, v18, v2 519; GFX10-NEXT: v_lshrrev_b32_e32 v3, v19, v3 520; GFX10-NEXT: v_lshrrev_b32_e32 v4, v20, v4 521; GFX10-NEXT: v_lshrrev_b32_e32 v5, v21, v5 522; GFX10-NEXT: v_lshrrev_b32_e32 v6, v22, v6 523; GFX10-NEXT: v_lshrrev_b32_e32 v7, v23, v7 524; GFX10-NEXT: v_lshrrev_b32_e32 v8, v24, v8 525; GFX10-NEXT: v_lshrrev_b32_e32 v9, v25, v9 526; GFX10-NEXT: v_lshrrev_b32_e32 v10, v26, v10 527; GFX10-NEXT: v_lshrrev_b32_e32 v11, v27, v11 528; GFX10-NEXT: v_lshrrev_b32_e32 v12, v28, v12 529; GFX10-NEXT: v_lshrrev_b32_e32 v13, v29, v13 530; GFX10-NEXT: v_lshrrev_b32_e32 v14, v30, v14 531; GFX10-NEXT: v_lshrrev_b32_e32 v15, v31, v15 532; GFX10-NEXT: s_setpc_b64 s[30:31] 533 %result = lshr <16 x i32> %value, %amount 534 ret <16 x i32> %result 535} 536 537define amdgpu_ps <16 x i32> @s_lshr_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) { 538; GCN-LABEL: s_lshr_v16i32: 539; GCN: ; %bb.0: 540; GCN-NEXT: s_lshr_b32 s0, s0, s16 541; GCN-NEXT: s_lshr_b32 s1, s1, s17 542; GCN-NEXT: s_lshr_b32 s2, s2, s18 543; GCN-NEXT: s_lshr_b32 s3, s3, s19 544; GCN-NEXT: s_lshr_b32 s4, s4, s20 545; GCN-NEXT: s_lshr_b32 s5, s5, s21 546; GCN-NEXT: s_lshr_b32 s6, s6, s22 547; GCN-NEXT: s_lshr_b32 s7, s7, s23 548; GCN-NEXT: s_lshr_b32 s8, s8, s24 549; GCN-NEXT: s_lshr_b32 s9, s9, s25 550; GCN-NEXT: s_lshr_b32 s10, s10, s26 551; GCN-NEXT: s_lshr_b32 s11, s11, s27 552; GCN-NEXT: s_lshr_b32 s12, s12, s28 553; GCN-NEXT: s_lshr_b32 s13, s13, s29 554; GCN-NEXT: s_lshr_b32 s14, s14, s30 555; GCN-NEXT: s_lshr_b32 s15, s15, s31 556; GCN-NEXT: ; return to shader part epilog 557; 558; GFX10-LABEL: s_lshr_v16i32: 559; GFX10: ; %bb.0: 560; GFX10-NEXT: s_lshr_b32 s0, s0, s16 561; GFX10-NEXT: s_lshr_b32 s1, s1, s17 562; GFX10-NEXT: s_lshr_b32 s2, s2, s18 563; GFX10-NEXT: s_lshr_b32 s3, s3, s19 564; GFX10-NEXT: s_lshr_b32 s4, s4, s20 565; GFX10-NEXT: s_lshr_b32 s5, s5, s21 566; GFX10-NEXT: s_lshr_b32 s6, s6, s22 567; GFX10-NEXT: s_lshr_b32 s7, s7, s23 568; GFX10-NEXT: s_lshr_b32 s8, s8, s24 569; GFX10-NEXT: s_lshr_b32 s9, s9, s25 570; GFX10-NEXT: s_lshr_b32 s10, s10, s26 571; GFX10-NEXT: s_lshr_b32 s11, s11, s27 572; GFX10-NEXT: s_lshr_b32 s12, s12, s28 573; GFX10-NEXT: s_lshr_b32 s13, s13, s29 574; GFX10-NEXT: s_lshr_b32 s14, s14, s30 575; GFX10-NEXT: s_lshr_b32 s15, s15, s31 576; GFX10-NEXT: ; return to shader part epilog 577 %result = lshr <16 x i32> %value, %amount 578 ret <16 x i32> %result 579} 580 581define i16 @v_lshr_i16(i16 %value, i16 %amount) { 582; GFX6-LABEL: v_lshr_i16: 583; GFX6: ; %bb.0: 584; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 585; GFX6-NEXT: s_mov_b32 s4, 0xffff 586; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 587; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 588; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0 589; GFX6-NEXT: s_setpc_b64 s[30:31] 590; 591; GFX8-LABEL: v_lshr_i16: 592; GFX8: ; %bb.0: 593; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 594; GFX8-NEXT: v_lshrrev_b16_e32 v0, v1, v0 595; GFX8-NEXT: s_setpc_b64 s[30:31] 596; 597; GFX9-LABEL: v_lshr_i16: 598; GFX9: ; %bb.0: 599; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 600; GFX9-NEXT: v_lshrrev_b16_e32 v0, v1, v0 601; GFX9-NEXT: s_setpc_b64 s[30:31] 602; 603; GFX10-LABEL: v_lshr_i16: 604; GFX10: ; %bb.0: 605; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 606; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 607; GFX10-NEXT: v_lshrrev_b16 v0, v1, v0 608; GFX10-NEXT: s_setpc_b64 s[30:31] 609 %result = lshr i16 %value, %amount 610 ret i16 %result 611} 612 613define i16 @v_lshr_i16_31(i16 %value) { 614; GCN-LABEL: v_lshr_i16_31: 615; GCN: ; %bb.0: 616; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 617; GCN-NEXT: s_setpc_b64 s[30:31] 618; 619; GFX10-LABEL: v_lshr_i16_31: 620; GFX10: ; %bb.0: 621; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 622; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 623; GFX10-NEXT: s_setpc_b64 s[30:31] 624 %result = lshr i16 %value, 31 625 ret i16 %result 626} 627 628define amdgpu_ps i16 @s_lshr_i16(i16 inreg %value, i16 inreg %amount) { 629; GFX6-LABEL: s_lshr_i16: 630; GFX6: ; %bb.0: 631; GFX6-NEXT: s_mov_b32 s2, 0xffff 632; GFX6-NEXT: s_and_b32 s1, s1, s2 633; GFX6-NEXT: s_and_b32 s0, s0, s2 634; GFX6-NEXT: s_lshr_b32 s0, s0, s1 635; GFX6-NEXT: ; return to shader part epilog 636; 637; GFX8-LABEL: s_lshr_i16: 638; GFX8: ; %bb.0: 639; GFX8-NEXT: s_mov_b32 s2, 0xffff 640; GFX8-NEXT: s_and_b32 s0, s0, s2 641; GFX8-NEXT: s_and_b32 s1, s1, s2 642; GFX8-NEXT: s_lshr_b32 s0, s0, s1 643; GFX8-NEXT: ; return to shader part epilog 644; 645; GFX9-LABEL: s_lshr_i16: 646; GFX9: ; %bb.0: 647; GFX9-NEXT: s_mov_b32 s2, 0xffff 648; GFX9-NEXT: s_and_b32 s0, s0, s2 649; GFX9-NEXT: s_and_b32 s1, s1, s2 650; GFX9-NEXT: s_lshr_b32 s0, s0, s1 651; GFX9-NEXT: ; return to shader part epilog 652; 653; GFX10-LABEL: s_lshr_i16: 654; GFX10: ; %bb.0: 655; GFX10-NEXT: s_mov_b32 s2, 0xffff 656; GFX10-NEXT: s_and_b32 s0, s0, s2 657; GFX10-NEXT: s_and_b32 s1, s1, s2 658; GFX10-NEXT: s_lshr_b32 s0, s0, s1 659; GFX10-NEXT: ; return to shader part epilog 660 %result = lshr i16 %value, %amount 661 ret i16 %result 662} 663 664define amdgpu_ps i16 @s_lshr_i16_15(i16 inreg %value) { 665; GCN-LABEL: s_lshr_i16_15: 666; GCN: ; %bb.0: 667; GCN-NEXT: s_and_b32 s0, s0, 0xffff 668; GCN-NEXT: s_lshr_b32 s0, s0, 15 669; GCN-NEXT: ; return to shader part epilog 670; 671; GFX10-LABEL: s_lshr_i16_15: 672; GFX10: ; %bb.0: 673; GFX10-NEXT: s_and_b32 s0, s0, 0xffff 674; GFX10-NEXT: s_lshr_b32 s0, s0, 15 675; GFX10-NEXT: ; return to shader part epilog 676 %result = lshr i16 %value, 15 677 ret i16 %result 678} 679 680define amdgpu_ps half @lshr_i16_sv(i16 inreg %value, i16 %amount) { 681; GFX6-LABEL: lshr_i16_sv: 682; GFX6: ; %bb.0: 683; GFX6-NEXT: s_mov_b32 s1, 0xffff 684; GFX6-NEXT: v_and_b32_e32 v0, s1, v0 685; GFX6-NEXT: s_and_b32 s0, s0, s1 686; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0 687; GFX6-NEXT: ; return to shader part epilog 688; 689; GFX8-LABEL: lshr_i16_sv: 690; GFX8: ; %bb.0: 691; GFX8-NEXT: v_lshrrev_b16_e64 v0, v0, s0 692; GFX8-NEXT: ; return to shader part epilog 693; 694; GFX9-LABEL: lshr_i16_sv: 695; GFX9: ; %bb.0: 696; GFX9-NEXT: v_lshrrev_b16_e64 v0, v0, s0 697; GFX9-NEXT: ; return to shader part epilog 698; 699; GFX10-LABEL: lshr_i16_sv: 700; GFX10: ; %bb.0: 701; GFX10-NEXT: v_lshrrev_b16 v0, v0, s0 702; GFX10-NEXT: ; return to shader part epilog 703 %result = lshr i16 %value, %amount 704 %cast = bitcast i16 %result to half 705 ret half %cast 706} 707 708define amdgpu_ps half @lshr_i16_vs(i16 %value, i16 inreg %amount) { 709; GFX6-LABEL: lshr_i16_vs: 710; GFX6: ; %bb.0: 711; GFX6-NEXT: s_mov_b32 s1, 0xffff 712; GFX6-NEXT: s_and_b32 s0, s0, s1 713; GFX6-NEXT: v_and_b32_e32 v0, s1, v0 714; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0 715; GFX6-NEXT: ; return to shader part epilog 716; 717; GFX8-LABEL: lshr_i16_vs: 718; GFX8: ; %bb.0: 719; GFX8-NEXT: v_lshrrev_b16_e32 v0, s0, v0 720; GFX8-NEXT: ; return to shader part epilog 721; 722; GFX9-LABEL: lshr_i16_vs: 723; GFX9: ; %bb.0: 724; GFX9-NEXT: v_lshrrev_b16_e32 v0, s0, v0 725; GFX9-NEXT: ; return to shader part epilog 726; 727; GFX10-LABEL: lshr_i16_vs: 728; GFX10: ; %bb.0: 729; GFX10-NEXT: v_lshrrev_b16 v0, s0, v0 730; GFX10-NEXT: ; return to shader part epilog 731 %result = lshr i16 %value, %amount 732 %cast = bitcast i16 %result to half 733 ret half %cast 734} 735 736define <2 x i16> @v_lshr_v2i16(<2 x i16> %value, <2 x i16> %amount) { 737; GFX6-LABEL: v_lshr_v2i16: 738; GFX6: ; %bb.0: 739; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 740; GFX6-NEXT: s_mov_b32 s4, 0xffff 741; GFX6-NEXT: v_and_b32_e32 v2, s4, v2 742; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 743; GFX6-NEXT: v_lshrrev_b32_e32 v0, v2, v0 744; GFX6-NEXT: v_and_b32_e32 v2, s4, v3 745; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 746; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1 747; GFX6-NEXT: s_setpc_b64 s[30:31] 748; 749; GFX8-LABEL: v_lshr_v2i16: 750; GFX8: ; %bb.0: 751; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 752; GFX8-NEXT: v_lshrrev_b16_e32 v2, v1, v0 753; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 754; GFX8-NEXT: v_or_b32_e32 v0, v2, v0 755; GFX8-NEXT: s_setpc_b64 s[30:31] 756; 757; GFX9-LABEL: v_lshr_v2i16: 758; GFX9: ; %bb.0: 759; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 760; GFX9-NEXT: v_pk_lshrrev_b16 v0, v1, v0 761; GFX9-NEXT: s_setpc_b64 s[30:31] 762; 763; GFX10-LABEL: v_lshr_v2i16: 764; GFX10: ; %bb.0: 765; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 766; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 767; GFX10-NEXT: v_pk_lshrrev_b16 v0, v1, v0 768; GFX10-NEXT: s_setpc_b64 s[30:31] 769 %result = lshr <2 x i16> %value, %amount 770 ret <2 x i16> %result 771} 772 773define <2 x i16> @v_lshr_v2i16_15(<2 x i16> %value) { 774; GFX6-LABEL: v_lshr_v2i16_15: 775; GFX6: ; %bb.0: 776; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 777; GFX6-NEXT: s_mov_b32 s4, 0xffff 778; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 779; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 780; GFX6-NEXT: v_lshrrev_b32_e32 v0, 15, v0 781; GFX6-NEXT: v_lshrrev_b32_e32 v1, 15, v1 782; GFX6-NEXT: s_setpc_b64 s[30:31] 783; 784; GFX8-LABEL: v_lshr_v2i16_15: 785; GFX8: ; %bb.0: 786; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 787; GFX8-NEXT: v_mov_b32_e32 v2, 15 788; GFX8-NEXT: v_lshrrev_b16_e32 v1, 15, v0 789; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 790; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 791; GFX8-NEXT: s_setpc_b64 s[30:31] 792; 793; GFX9-LABEL: v_lshr_v2i16_15: 794; GFX9: ; %bb.0: 795; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 796; GFX9-NEXT: v_pk_lshrrev_b16 v0, 15, v0 op_sel_hi:[0,1] 797; GFX9-NEXT: s_setpc_b64 s[30:31] 798; 799; GFX10-LABEL: v_lshr_v2i16_15: 800; GFX10: ; %bb.0: 801; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 802; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 803; GFX10-NEXT: v_pk_lshrrev_b16 v0, 15, v0 op_sel_hi:[0,1] 804; GFX10-NEXT: s_setpc_b64 s[30:31] 805 %result = lshr <2 x i16> %value, <i16 15, i16 15> 806 ret <2 x i16> %result 807} 808 809define amdgpu_ps i32 @s_lshr_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) { 810; GFX6-LABEL: s_lshr_v2i16: 811; GFX6: ; %bb.0: 812; GFX6-NEXT: s_mov_b32 s4, 0xffff 813; GFX6-NEXT: s_and_b32 s2, s2, s4 814; GFX6-NEXT: s_and_b32 s0, s0, s4 815; GFX6-NEXT: s_lshr_b32 s0, s0, s2 816; GFX6-NEXT: s_and_b32 s2, s3, s4 817; GFX6-NEXT: s_and_b32 s1, s1, s4 818; GFX6-NEXT: s_lshr_b32 s1, s1, s2 819; GFX6-NEXT: s_lshl_b32 s1, s1, 16 820; GFX6-NEXT: s_or_b32 s0, s0, s1 821; GFX6-NEXT: ; return to shader part epilog 822; 823; GFX8-LABEL: s_lshr_v2i16: 824; GFX8: ; %bb.0: 825; GFX8-NEXT: s_mov_b32 s3, 0xffff 826; GFX8-NEXT: s_lshr_b32 s2, s0, 16 827; GFX8-NEXT: s_and_b32 s0, s0, s3 828; GFX8-NEXT: s_lshr_b32 s4, s1, 16 829; GFX8-NEXT: s_and_b32 s1, s1, s3 830; GFX8-NEXT: s_lshr_b32 s0, s0, s1 831; GFX8-NEXT: s_lshr_b32 s1, s2, s4 832; GFX8-NEXT: s_lshl_b32 s1, s1, 16 833; GFX8-NEXT: s_and_b32 s0, s0, s3 834; GFX8-NEXT: s_or_b32 s0, s1, s0 835; GFX8-NEXT: ; return to shader part epilog 836; 837; GFX9-LABEL: s_lshr_v2i16: 838; GFX9: ; %bb.0: 839; GFX9-NEXT: s_mov_b32 s3, 0xffff 840; GFX9-NEXT: s_lshr_b32 s2, s0, 16 841; GFX9-NEXT: s_and_b32 s0, s0, s3 842; GFX9-NEXT: s_lshr_b32 s4, s1, 16 843; GFX9-NEXT: s_and_b32 s1, s1, s3 844; GFX9-NEXT: s_lshr_b32 s0, s0, s1 845; GFX9-NEXT: s_lshr_b32 s1, s2, s4 846; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1 847; GFX9-NEXT: ; return to shader part epilog 848; 849; GFX10-LABEL: s_lshr_v2i16: 850; GFX10: ; %bb.0: 851; GFX10-NEXT: s_mov_b32 s2, 0xffff 852; GFX10-NEXT: s_lshr_b32 s3, s0, 16 853; GFX10-NEXT: s_and_b32 s0, s0, s2 854; GFX10-NEXT: s_and_b32 s2, s1, s2 855; GFX10-NEXT: s_lshr_b32 s1, s1, 16 856; GFX10-NEXT: s_lshr_b32 s0, s0, s2 857; GFX10-NEXT: s_lshr_b32 s1, s3, s1 858; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1 859; GFX10-NEXT: ; return to shader part epilog 860 %result = lshr <2 x i16> %value, %amount 861 %cast = bitcast <2 x i16> %result to i32 862 ret i32 %cast 863} 864 865define amdgpu_ps float @lshr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) { 866; GFX6-LABEL: lshr_v2i16_sv: 867; GFX6: ; %bb.0: 868; GFX6-NEXT: s_mov_b32 s2, 0xffff 869; GFX6-NEXT: v_and_b32_e32 v0, s2, v0 870; GFX6-NEXT: s_and_b32 s0, s0, s2 871; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0 872; GFX6-NEXT: v_and_b32_e32 v1, s2, v1 873; GFX6-NEXT: s_and_b32 s0, s1, s2 874; GFX6-NEXT: v_lshr_b32_e32 v1, s0, v1 875; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 876; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 877; GFX6-NEXT: ; return to shader part epilog 878; 879; GFX8-LABEL: lshr_v2i16_sv: 880; GFX8: ; %bb.0: 881; GFX8-NEXT: s_lshr_b32 s1, s0, 16 882; GFX8-NEXT: v_mov_b32_e32 v2, s1 883; GFX8-NEXT: v_lshrrev_b16_e64 v1, v0, s0 884; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 885; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 886; GFX8-NEXT: ; return to shader part epilog 887; 888; GFX9-LABEL: lshr_v2i16_sv: 889; GFX9: ; %bb.0: 890; GFX9-NEXT: v_pk_lshrrev_b16 v0, v0, s0 891; GFX9-NEXT: ; return to shader part epilog 892; 893; GFX10-LABEL: lshr_v2i16_sv: 894; GFX10: ; %bb.0: 895; GFX10-NEXT: v_pk_lshrrev_b16 v0, v0, s0 896; GFX10-NEXT: ; return to shader part epilog 897 %result = lshr <2 x i16> %value, %amount 898 %cast = bitcast <2 x i16> %result to float 899 ret float %cast 900} 901 902define amdgpu_ps float @lshr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) { 903; GFX6-LABEL: lshr_v2i16_vs: 904; GFX6: ; %bb.0: 905; GFX6-NEXT: s_mov_b32 s2, 0xffff 906; GFX6-NEXT: s_and_b32 s0, s0, s2 907; GFX6-NEXT: v_and_b32_e32 v0, s2, v0 908; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0 909; GFX6-NEXT: s_and_b32 s0, s1, s2 910; GFX6-NEXT: v_and_b32_e32 v1, s2, v1 911; GFX6-NEXT: v_lshrrev_b32_e32 v1, s0, v1 912; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 913; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 914; GFX6-NEXT: ; return to shader part epilog 915; 916; GFX8-LABEL: lshr_v2i16_vs: 917; GFX8: ; %bb.0: 918; GFX8-NEXT: s_lshr_b32 s1, s0, 16 919; GFX8-NEXT: v_mov_b32_e32 v2, s1 920; GFX8-NEXT: v_lshrrev_b16_e32 v1, s0, v0 921; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 922; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 923; GFX8-NEXT: ; return to shader part epilog 924; 925; GFX9-LABEL: lshr_v2i16_vs: 926; GFX9: ; %bb.0: 927; GFX9-NEXT: v_pk_lshrrev_b16 v0, s0, v0 928; GFX9-NEXT: ; return to shader part epilog 929; 930; GFX10-LABEL: lshr_v2i16_vs: 931; GFX10: ; %bb.0: 932; GFX10-NEXT: v_pk_lshrrev_b16 v0, s0, v0 933; GFX10-NEXT: ; return to shader part epilog 934 %result = lshr <2 x i16> %value, %amount 935 %cast = bitcast <2 x i16> %result to float 936 ret float %cast 937} 938 939; FIXME 940; define <3 x i16> @v_lshr_v3i16(<3 x i16> %value, <3 x i16> %amount) { 941; %result = lshr <3 x i16> %value, %amount 942; ret <3 x i16> %result 943; } 944 945; define amdgpu_ps <3 x i16> @s_lshr_v3i16(<3 x i16> inreg %value, <3 x i16> inreg %amount) { 946; %result = lshr <3 x i16> %value, %amount 947; ret <3 x i16> %result 948; } 949 950define <2 x float> @v_lshr_v4i16(<4 x i16> %value, <4 x i16> %amount) { 951; GFX6-LABEL: v_lshr_v4i16: 952; GFX6: ; %bb.0: 953; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 954; GFX6-NEXT: s_mov_b32 s4, 0xffff 955; GFX6-NEXT: v_and_b32_e32 v4, s4, v4 956; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 957; GFX6-NEXT: v_lshrrev_b32_e32 v0, v4, v0 958; GFX6-NEXT: v_and_b32_e32 v4, s4, v5 959; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 960; GFX6-NEXT: v_lshrrev_b32_e32 v1, v4, v1 961; GFX6-NEXT: v_and_b32_e32 v4, s4, v6 962; GFX6-NEXT: v_and_b32_e32 v2, s4, v2 963; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2 964; GFX6-NEXT: v_and_b32_e32 v4, s4, v7 965; GFX6-NEXT: v_and_b32_e32 v3, s4, v3 966; GFX6-NEXT: v_lshrrev_b32_e32 v3, v4, v3 967; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 968; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 969; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3 970; GFX6-NEXT: v_or_b32_e32 v1, v2, v1 971; GFX6-NEXT: s_setpc_b64 s[30:31] 972; 973; GFX8-LABEL: v_lshr_v4i16: 974; GFX8: ; %bb.0: 975; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 976; GFX8-NEXT: v_lshrrev_b16_e32 v4, v2, v0 977; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 978; GFX8-NEXT: v_lshrrev_b16_e32 v2, v3, v1 979; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 980; GFX8-NEXT: v_or_b32_e32 v0, v4, v0 981; GFX8-NEXT: v_or_b32_e32 v1, v2, v1 982; GFX8-NEXT: s_setpc_b64 s[30:31] 983; 984; GFX9-LABEL: v_lshr_v4i16: 985; GFX9: ; %bb.0: 986; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 987; GFX9-NEXT: v_pk_lshrrev_b16 v0, v2, v0 988; GFX9-NEXT: v_pk_lshrrev_b16 v1, v3, v1 989; GFX9-NEXT: s_setpc_b64 s[30:31] 990; 991; GFX10-LABEL: v_lshr_v4i16: 992; GFX10: ; %bb.0: 993; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 994; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 995; GFX10-NEXT: v_pk_lshrrev_b16 v0, v2, v0 996; GFX10-NEXT: v_pk_lshrrev_b16 v1, v3, v1 997; GFX10-NEXT: s_setpc_b64 s[30:31] 998 %result = lshr <4 x i16> %value, %amount 999 %cast = bitcast <4 x i16> %result to <2 x float> 1000 ret <2 x float> %cast 1001} 1002 1003define amdgpu_ps <2 x i32> @s_lshr_v4i16(<4 x i16> inreg %value, <4 x i16> inreg %amount) { 1004; GFX6-LABEL: s_lshr_v4i16: 1005; GFX6: ; %bb.0: 1006; GFX6-NEXT: s_mov_b32 s8, 0xffff 1007; GFX6-NEXT: s_and_b32 s4, s4, s8 1008; GFX6-NEXT: s_and_b32 s0, s0, s8 1009; GFX6-NEXT: s_lshr_b32 s0, s0, s4 1010; GFX6-NEXT: s_and_b32 s4, s5, s8 1011; GFX6-NEXT: s_and_b32 s1, s1, s8 1012; GFX6-NEXT: s_lshr_b32 s1, s1, s4 1013; GFX6-NEXT: s_and_b32 s4, s6, s8 1014; GFX6-NEXT: s_and_b32 s2, s2, s8 1015; GFX6-NEXT: s_lshr_b32 s2, s2, s4 1016; GFX6-NEXT: s_and_b32 s4, s7, s8 1017; GFX6-NEXT: s_and_b32 s3, s3, s8 1018; GFX6-NEXT: s_lshr_b32 s3, s3, s4 1019; GFX6-NEXT: s_lshl_b32 s1, s1, 16 1020; GFX6-NEXT: s_or_b32 s0, s0, s1 1021; GFX6-NEXT: s_lshl_b32 s1, s3, 16 1022; GFX6-NEXT: s_or_b32 s1, s2, s1 1023; GFX6-NEXT: ; return to shader part epilog 1024; 1025; GFX8-LABEL: s_lshr_v4i16: 1026; GFX8: ; %bb.0: 1027; GFX8-NEXT: s_mov_b32 s6, 0xffff 1028; GFX8-NEXT: s_lshr_b32 s4, s0, 16 1029; GFX8-NEXT: s_and_b32 s0, s0, s6 1030; GFX8-NEXT: s_lshr_b32 s7, s2, 16 1031; GFX8-NEXT: s_and_b32 s2, s2, s6 1032; GFX8-NEXT: s_lshr_b32 s5, s1, 16 1033; GFX8-NEXT: s_and_b32 s1, s1, s6 1034; GFX8-NEXT: s_lshr_b32 s8, s3, 16 1035; GFX8-NEXT: s_and_b32 s3, s3, s6 1036; GFX8-NEXT: s_lshr_b32 s0, s0, s2 1037; GFX8-NEXT: s_lshr_b32 s2, s4, s7 1038; GFX8-NEXT: s_lshr_b32 s1, s1, s3 1039; GFX8-NEXT: s_lshr_b32 s3, s5, s8 1040; GFX8-NEXT: s_lshl_b32 s2, s2, 16 1041; GFX8-NEXT: s_and_b32 s0, s0, s6 1042; GFX8-NEXT: s_or_b32 s0, s2, s0 1043; GFX8-NEXT: s_lshl_b32 s2, s3, 16 1044; GFX8-NEXT: s_and_b32 s1, s1, s6 1045; GFX8-NEXT: s_or_b32 s1, s2, s1 1046; GFX8-NEXT: ; return to shader part epilog 1047; 1048; GFX9-LABEL: s_lshr_v4i16: 1049; GFX9: ; %bb.0: 1050; GFX9-NEXT: s_mov_b32 s5, 0xffff 1051; GFX9-NEXT: s_lshr_b32 s4, s0, 16 1052; GFX9-NEXT: s_and_b32 s0, s0, s5 1053; GFX9-NEXT: s_lshr_b32 s6, s2, 16 1054; GFX9-NEXT: s_and_b32 s2, s2, s5 1055; GFX9-NEXT: s_lshr_b32 s0, s0, s2 1056; GFX9-NEXT: s_lshr_b32 s2, s4, s6 1057; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2 1058; GFX9-NEXT: s_lshr_b32 s2, s1, 16 1059; GFX9-NEXT: s_and_b32 s1, s1, s5 1060; GFX9-NEXT: s_lshr_b32 s4, s3, 16 1061; GFX9-NEXT: s_and_b32 s3, s3, s5 1062; GFX9-NEXT: s_lshr_b32 s1, s1, s3 1063; GFX9-NEXT: s_lshr_b32 s2, s2, s4 1064; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2 1065; GFX9-NEXT: ; return to shader part epilog 1066; 1067; GFX10-LABEL: s_lshr_v4i16: 1068; GFX10: ; %bb.0: 1069; GFX10-NEXT: s_mov_b32 s4, 0xffff 1070; GFX10-NEXT: s_lshr_b32 s5, s0, 16 1071; GFX10-NEXT: s_and_b32 s6, s2, s4 1072; GFX10-NEXT: s_lshr_b32 s2, s2, 16 1073; GFX10-NEXT: s_and_b32 s0, s0, s4 1074; GFX10-NEXT: s_lshr_b32 s2, s5, s2 1075; GFX10-NEXT: s_lshr_b32 s5, s1, 16 1076; GFX10-NEXT: s_and_b32 s1, s1, s4 1077; GFX10-NEXT: s_and_b32 s4, s3, s4 1078; GFX10-NEXT: s_lshr_b32 s3, s3, 16 1079; GFX10-NEXT: s_lshr_b32 s0, s0, s6 1080; GFX10-NEXT: s_lshr_b32 s1, s1, s4 1081; GFX10-NEXT: s_lshr_b32 s3, s5, s3 1082; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2 1083; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3 1084; GFX10-NEXT: ; return to shader part epilog 1085 %result = lshr <4 x i16> %value, %amount 1086 %cast = bitcast <4 x i16> %result to <2 x i32> 1087 ret <2 x i32> %cast 1088} 1089 1090; FIXME 1091; define <5 x i16> @v_lshr_v5i16(<5 x i16> %value, <5 x i16> %amount) { 1092; %result = lshr <5 x i16> %value, %amount 1093; ret <5 x i16> %result 1094; } 1095 1096; define amdgpu_ps <5 x i16> @s_lshr_v5i16(<5 x i16> inreg %value, <5 x i16> inreg %amount) { 1097; %result = lshr <5 x i16> %value, %amount 1098; ret <5 x i16> %result 1099; } 1100 1101; define <3 x float> @v_lshr_v6i16(<6 x i16> %value, <6 x i16> %amount) { 1102; %result = lshr <6 x i16> %value, %amount 1103; %cast = bitcast <6 x i16> %result to <3 x float> 1104; ret <3 x float> %cast 1105; } 1106 1107; define amdgpu_ps <3 x i32> @s_lshr_v6i16(<6 x i16> inreg %value, <6 x i16> inreg %amount) { 1108; %result = lshr <6 x i16> %value, %amount 1109; %cast = bitcast <6 x i16> %result to <3 x i32> 1110; ret <3 x i32> %cast 1111; } 1112 1113define <4 x float> @v_lshr_v8i16(<8 x i16> %value, <8 x i16> %amount) { 1114; GFX6-LABEL: v_lshr_v8i16: 1115; GFX6: ; %bb.0: 1116; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1117; GFX6-NEXT: s_mov_b32 s4, 0xffff 1118; GFX6-NEXT: v_and_b32_e32 v8, s4, v8 1119; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 1120; GFX6-NEXT: v_lshrrev_b32_e32 v0, v8, v0 1121; GFX6-NEXT: v_and_b32_e32 v8, s4, v9 1122; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 1123; GFX6-NEXT: v_lshrrev_b32_e32 v1, v8, v1 1124; GFX6-NEXT: v_and_b32_e32 v8, s4, v10 1125; GFX6-NEXT: v_and_b32_e32 v2, s4, v2 1126; GFX6-NEXT: v_lshrrev_b32_e32 v2, v8, v2 1127; GFX6-NEXT: v_and_b32_e32 v8, s4, v11 1128; GFX6-NEXT: v_and_b32_e32 v3, s4, v3 1129; GFX6-NEXT: v_lshrrev_b32_e32 v3, v8, v3 1130; GFX6-NEXT: v_and_b32_e32 v8, s4, v12 1131; GFX6-NEXT: v_and_b32_e32 v4, s4, v4 1132; GFX6-NEXT: v_lshrrev_b32_e32 v4, v8, v4 1133; GFX6-NEXT: v_and_b32_e32 v8, s4, v13 1134; GFX6-NEXT: v_and_b32_e32 v5, s4, v5 1135; GFX6-NEXT: v_mov_b32_e32 v16, 0xffff 1136; GFX6-NEXT: v_lshrrev_b32_e32 v5, v8, v5 1137; GFX6-NEXT: v_and_b32_e32 v8, s4, v14 1138; GFX6-NEXT: v_and_b32_e32 v6, s4, v6 1139; GFX6-NEXT: v_lshrrev_b32_e32 v6, v8, v6 1140; GFX6-NEXT: v_and_b32_e32 v8, v15, v16 1141; GFX6-NEXT: v_and_b32_e32 v7, v7, v16 1142; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1143; GFX6-NEXT: v_lshrrev_b32_e32 v7, v8, v7 1144; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 1145; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3 1146; GFX6-NEXT: v_or_b32_e32 v1, v2, v1 1147; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v5 1148; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v7 1149; GFX6-NEXT: v_or_b32_e32 v2, v4, v2 1150; GFX6-NEXT: v_or_b32_e32 v3, v6, v3 1151; GFX6-NEXT: s_setpc_b64 s[30:31] 1152; 1153; GFX8-LABEL: v_lshr_v8i16: 1154; GFX8: ; %bb.0: 1155; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1156; GFX8-NEXT: v_lshrrev_b16_e32 v8, v4, v0 1157; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1158; GFX8-NEXT: v_lshrrev_b16_e32 v4, v5, v1 1159; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1160; GFX8-NEXT: v_or_b32_e32 v1, v4, v1 1161; GFX8-NEXT: v_lshrrev_b16_e32 v4, v6, v2 1162; GFX8-NEXT: v_lshrrev_b16_sdwa v2, v6, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1163; GFX8-NEXT: v_or_b32_e32 v2, v4, v2 1164; GFX8-NEXT: v_lshrrev_b16_e32 v4, v7, v3 1165; GFX8-NEXT: v_lshrrev_b16_sdwa v3, v7, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1166; GFX8-NEXT: v_or_b32_e32 v0, v8, v0 1167; GFX8-NEXT: v_or_b32_e32 v3, v4, v3 1168; GFX8-NEXT: s_setpc_b64 s[30:31] 1169; 1170; GFX9-LABEL: v_lshr_v8i16: 1171; GFX9: ; %bb.0: 1172; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1173; GFX9-NEXT: v_pk_lshrrev_b16 v0, v4, v0 1174; GFX9-NEXT: v_pk_lshrrev_b16 v1, v5, v1 1175; GFX9-NEXT: v_pk_lshrrev_b16 v2, v6, v2 1176; GFX9-NEXT: v_pk_lshrrev_b16 v3, v7, v3 1177; GFX9-NEXT: s_setpc_b64 s[30:31] 1178; 1179; GFX10-LABEL: v_lshr_v8i16: 1180; GFX10: ; %bb.0: 1181; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1182; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1183; GFX10-NEXT: v_pk_lshrrev_b16 v0, v4, v0 1184; GFX10-NEXT: v_pk_lshrrev_b16 v1, v5, v1 1185; GFX10-NEXT: v_pk_lshrrev_b16 v2, v6, v2 1186; GFX10-NEXT: v_pk_lshrrev_b16 v3, v7, v3 1187; GFX10-NEXT: s_setpc_b64 s[30:31] 1188 %result = lshr <8 x i16> %value, %amount 1189 %cast = bitcast <8 x i16> %result to <4 x float> 1190 ret <4 x float> %cast 1191} 1192 1193define amdgpu_ps <4 x i32> @s_lshr_v8i16(<8 x i16> inreg %value, <8 x i16> inreg %amount) { 1194; GFX6-LABEL: s_lshr_v8i16: 1195; GFX6: ; %bb.0: 1196; GFX6-NEXT: s_mov_b32 s16, 0xffff 1197; GFX6-NEXT: s_and_b32 s8, s8, s16 1198; GFX6-NEXT: s_and_b32 s0, s0, s16 1199; GFX6-NEXT: s_lshr_b32 s0, s0, s8 1200; GFX6-NEXT: s_and_b32 s8, s9, s16 1201; GFX6-NEXT: s_and_b32 s1, s1, s16 1202; GFX6-NEXT: s_lshr_b32 s1, s1, s8 1203; GFX6-NEXT: s_and_b32 s8, s10, s16 1204; GFX6-NEXT: s_and_b32 s2, s2, s16 1205; GFX6-NEXT: s_lshr_b32 s2, s2, s8 1206; GFX6-NEXT: s_and_b32 s8, s11, s16 1207; GFX6-NEXT: s_and_b32 s3, s3, s16 1208; GFX6-NEXT: s_lshr_b32 s3, s3, s8 1209; GFX6-NEXT: s_and_b32 s8, s12, s16 1210; GFX6-NEXT: s_and_b32 s4, s4, s16 1211; GFX6-NEXT: s_lshr_b32 s4, s4, s8 1212; GFX6-NEXT: s_and_b32 s8, s13, s16 1213; GFX6-NEXT: s_and_b32 s5, s5, s16 1214; GFX6-NEXT: s_lshr_b32 s5, s5, s8 1215; GFX6-NEXT: s_and_b32 s8, s14, s16 1216; GFX6-NEXT: s_and_b32 s6, s6, s16 1217; GFX6-NEXT: s_lshr_b32 s6, s6, s8 1218; GFX6-NEXT: s_and_b32 s8, s15, s16 1219; GFX6-NEXT: s_and_b32 s7, s7, s16 1220; GFX6-NEXT: s_lshl_b32 s1, s1, 16 1221; GFX6-NEXT: s_lshr_b32 s7, s7, s8 1222; GFX6-NEXT: s_or_b32 s0, s0, s1 1223; GFX6-NEXT: s_lshl_b32 s1, s3, 16 1224; GFX6-NEXT: s_or_b32 s1, s2, s1 1225; GFX6-NEXT: s_lshl_b32 s2, s5, 16 1226; GFX6-NEXT: s_lshl_b32 s3, s7, 16 1227; GFX6-NEXT: s_or_b32 s2, s4, s2 1228; GFX6-NEXT: s_or_b32 s3, s6, s3 1229; GFX6-NEXT: ; return to shader part epilog 1230; 1231; GFX8-LABEL: s_lshr_v8i16: 1232; GFX8: ; %bb.0: 1233; GFX8-NEXT: s_mov_b32 s12, 0xffff 1234; GFX8-NEXT: s_lshr_b32 s8, s0, 16 1235; GFX8-NEXT: s_and_b32 s0, s0, s12 1236; GFX8-NEXT: s_lshr_b32 s13, s4, 16 1237; GFX8-NEXT: s_and_b32 s4, s4, s12 1238; GFX8-NEXT: s_lshr_b32 s9, s1, 16 1239; GFX8-NEXT: s_and_b32 s1, s1, s12 1240; GFX8-NEXT: s_lshr_b32 s14, s5, 16 1241; GFX8-NEXT: s_and_b32 s5, s5, s12 1242; GFX8-NEXT: s_lshr_b32 s0, s0, s4 1243; GFX8-NEXT: s_lshr_b32 s4, s8, s13 1244; GFX8-NEXT: s_lshr_b32 s10, s2, 16 1245; GFX8-NEXT: s_and_b32 s2, s2, s12 1246; GFX8-NEXT: s_lshr_b32 s15, s6, 16 1247; GFX8-NEXT: s_and_b32 s6, s6, s12 1248; GFX8-NEXT: s_lshr_b32 s1, s1, s5 1249; GFX8-NEXT: s_lshr_b32 s5, s9, s14 1250; GFX8-NEXT: s_lshl_b32 s4, s4, 16 1251; GFX8-NEXT: s_and_b32 s0, s0, s12 1252; GFX8-NEXT: s_lshr_b32 s11, s3, 16 1253; GFX8-NEXT: s_and_b32 s3, s3, s12 1254; GFX8-NEXT: s_lshr_b32 s16, s7, 16 1255; GFX8-NEXT: s_and_b32 s7, s7, s12 1256; GFX8-NEXT: s_lshr_b32 s2, s2, s6 1257; GFX8-NEXT: s_lshr_b32 s6, s10, s15 1258; GFX8-NEXT: s_or_b32 s0, s4, s0 1259; GFX8-NEXT: s_lshl_b32 s4, s5, 16 1260; GFX8-NEXT: s_and_b32 s1, s1, s12 1261; GFX8-NEXT: s_lshr_b32 s3, s3, s7 1262; GFX8-NEXT: s_lshr_b32 s7, s11, s16 1263; GFX8-NEXT: s_or_b32 s1, s4, s1 1264; GFX8-NEXT: s_lshl_b32 s4, s6, 16 1265; GFX8-NEXT: s_and_b32 s2, s2, s12 1266; GFX8-NEXT: s_or_b32 s2, s4, s2 1267; GFX8-NEXT: s_lshl_b32 s4, s7, 16 1268; GFX8-NEXT: s_and_b32 s3, s3, s12 1269; GFX8-NEXT: s_or_b32 s3, s4, s3 1270; GFX8-NEXT: ; return to shader part epilog 1271; 1272; GFX9-LABEL: s_lshr_v8i16: 1273; GFX9: ; %bb.0: 1274; GFX9-NEXT: s_mov_b32 s9, 0xffff 1275; GFX9-NEXT: s_lshr_b32 s8, s0, 16 1276; GFX9-NEXT: s_and_b32 s0, s0, s9 1277; GFX9-NEXT: s_lshr_b32 s10, s4, 16 1278; GFX9-NEXT: s_and_b32 s4, s4, s9 1279; GFX9-NEXT: s_lshr_b32 s0, s0, s4 1280; GFX9-NEXT: s_lshr_b32 s4, s8, s10 1281; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s4 1282; GFX9-NEXT: s_lshr_b32 s4, s1, 16 1283; GFX9-NEXT: s_and_b32 s1, s1, s9 1284; GFX9-NEXT: s_lshr_b32 s8, s5, 16 1285; GFX9-NEXT: s_and_b32 s5, s5, s9 1286; GFX9-NEXT: s_lshr_b32 s1, s1, s5 1287; GFX9-NEXT: s_lshr_b32 s4, s4, s8 1288; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4 1289; GFX9-NEXT: s_lshr_b32 s4, s2, 16 1290; GFX9-NEXT: s_and_b32 s2, s2, s9 1291; GFX9-NEXT: s_lshr_b32 s5, s6, 16 1292; GFX9-NEXT: s_and_b32 s6, s6, s9 1293; GFX9-NEXT: s_lshr_b32 s2, s2, s6 1294; GFX9-NEXT: s_lshr_b32 s4, s4, s5 1295; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4 1296; GFX9-NEXT: s_lshr_b32 s4, s3, 16 1297; GFX9-NEXT: s_and_b32 s3, s3, s9 1298; GFX9-NEXT: s_lshr_b32 s5, s7, 16 1299; GFX9-NEXT: s_and_b32 s6, s7, s9 1300; GFX9-NEXT: s_lshr_b32 s3, s3, s6 1301; GFX9-NEXT: s_lshr_b32 s4, s4, s5 1302; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4 1303; GFX9-NEXT: ; return to shader part epilog 1304; 1305; GFX10-LABEL: s_lshr_v8i16: 1306; GFX10: ; %bb.0: 1307; GFX10-NEXT: s_mov_b32 s8, 0xffff 1308; GFX10-NEXT: s_lshr_b32 s9, s0, 16 1309; GFX10-NEXT: s_and_b32 s0, s0, s8 1310; GFX10-NEXT: s_and_b32 s10, s4, s8 1311; GFX10-NEXT: s_lshr_b32 s4, s4, 16 1312; GFX10-NEXT: s_lshr_b32 s0, s0, s10 1313; GFX10-NEXT: s_lshr_b32 s4, s9, s4 1314; GFX10-NEXT: s_lshr_b32 s9, s1, 16 1315; GFX10-NEXT: s_and_b32 s1, s1, s8 1316; GFX10-NEXT: s_and_b32 s10, s5, s8 1317; GFX10-NEXT: s_lshr_b32 s5, s5, 16 1318; GFX10-NEXT: s_lshr_b32 s1, s1, s10 1319; GFX10-NEXT: s_lshr_b32 s5, s9, s5 1320; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s4 1321; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s5 1322; GFX10-NEXT: s_lshr_b32 s4, s2, 16 1323; GFX10-NEXT: s_and_b32 s2, s2, s8 1324; GFX10-NEXT: s_and_b32 s5, s6, s8 1325; GFX10-NEXT: s_lshr_b32 s6, s6, 16 1326; GFX10-NEXT: s_lshr_b32 s2, s2, s5 1327; GFX10-NEXT: s_lshr_b32 s4, s4, s6 1328; GFX10-NEXT: s_lshr_b32 s5, s3, 16 1329; GFX10-NEXT: s_and_b32 s3, s3, s8 1330; GFX10-NEXT: s_and_b32 s6, s7, s8 1331; GFX10-NEXT: s_lshr_b32 s7, s7, 16 1332; GFX10-NEXT: s_lshr_b32 s3, s3, s6 1333; GFX10-NEXT: s_lshr_b32 s5, s5, s7 1334; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s4 1335; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s5 1336; GFX10-NEXT: ; return to shader part epilog 1337 %result = lshr <8 x i16> %value, %amount 1338 %cast = bitcast <8 x i16> %result to <4 x i32> 1339 ret <4 x i32> %cast 1340} 1341 1342define i64 @v_lshr_i64(i64 %value, i64 %amount) { 1343; GFX6-LABEL: v_lshr_i64: 1344; GFX6: ; %bb.0: 1345; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1346; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], v2 1347; GFX6-NEXT: s_setpc_b64 s[30:31] 1348; 1349; GFX8-LABEL: v_lshr_i64: 1350; GFX8: ; %bb.0: 1351; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1352; GFX8-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 1353; GFX8-NEXT: s_setpc_b64 s[30:31] 1354; 1355; GFX9-LABEL: v_lshr_i64: 1356; GFX9: ; %bb.0: 1357; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1358; GFX9-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 1359; GFX9-NEXT: s_setpc_b64 s[30:31] 1360; 1361; GFX10-LABEL: v_lshr_i64: 1362; GFX10: ; %bb.0: 1363; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1364; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1365; GFX10-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 1366; GFX10-NEXT: s_setpc_b64 s[30:31] 1367 %result = lshr i64 %value, %amount 1368 ret i64 %result 1369} 1370 1371define i64 @v_lshr_i64_63(i64 %value) { 1372; GCN-LABEL: v_lshr_i64_63: 1373; GCN: ; %bb.0: 1374; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1375; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v1 1376; GCN-NEXT: v_mov_b32_e32 v1, 0 1377; GCN-NEXT: s_setpc_b64 s[30:31] 1378; 1379; GFX10-LABEL: v_lshr_i64_63: 1380; GFX10: ; %bb.0: 1381; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1382; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1383; GFX10-NEXT: v_lshrrev_b32_e32 v0, 31, v1 1384; GFX10-NEXT: v_mov_b32_e32 v1, 0 1385; GFX10-NEXT: s_setpc_b64 s[30:31] 1386 %result = lshr i64 %value, 63 1387 ret i64 %result 1388} 1389 1390define i64 @v_lshr_i64_33(i64 %value) { 1391; GCN-LABEL: v_lshr_i64_33: 1392; GCN: ; %bb.0: 1393; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1394; GCN-NEXT: v_lshrrev_b32_e32 v0, 1, v1 1395; GCN-NEXT: v_mov_b32_e32 v1, 0 1396; GCN-NEXT: s_setpc_b64 s[30:31] 1397; 1398; GFX10-LABEL: v_lshr_i64_33: 1399; GFX10: ; %bb.0: 1400; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1401; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1402; GFX10-NEXT: v_lshrrev_b32_e32 v0, 1, v1 1403; GFX10-NEXT: v_mov_b32_e32 v1, 0 1404; GFX10-NEXT: s_setpc_b64 s[30:31] 1405 %result = lshr i64 %value, 33 1406 ret i64 %result 1407} 1408 1409define i64 @v_lshr_i64_32(i64 %value) { 1410; GCN-LABEL: v_lshr_i64_32: 1411; GCN: ; %bb.0: 1412; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1413; GCN-NEXT: v_mov_b32_e32 v0, v1 1414; GCN-NEXT: v_mov_b32_e32 v1, 0 1415; GCN-NEXT: s_setpc_b64 s[30:31] 1416; 1417; GFX10-LABEL: v_lshr_i64_32: 1418; GFX10: ; %bb.0: 1419; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1420; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1421; GFX10-NEXT: v_mov_b32_e32 v0, v1 1422; GFX10-NEXT: v_mov_b32_e32 v1, 0 1423; GFX10-NEXT: s_setpc_b64 s[30:31] 1424 %result = lshr i64 %value, 32 1425 ret i64 %result 1426} 1427 1428define i64 @v_lshr_i64_31(i64 %value) { 1429; GFX6-LABEL: v_lshr_i64_31: 1430; GFX6: ; %bb.0: 1431; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1432; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 31 1433; GFX6-NEXT: s_setpc_b64 s[30:31] 1434; 1435; GFX8-LABEL: v_lshr_i64_31: 1436; GFX8: ; %bb.0: 1437; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1438; GFX8-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1439; GFX8-NEXT: s_setpc_b64 s[30:31] 1440; 1441; GFX9-LABEL: v_lshr_i64_31: 1442; GFX9: ; %bb.0: 1443; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1444; GFX9-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1445; GFX9-NEXT: s_setpc_b64 s[30:31] 1446; 1447; GFX10-LABEL: v_lshr_i64_31: 1448; GFX10: ; %bb.0: 1449; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1450; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1451; GFX10-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1452; GFX10-NEXT: s_setpc_b64 s[30:31] 1453 %result = lshr i64 %value, 31 1454 ret i64 %result 1455} 1456 1457define amdgpu_ps i64 @s_lshr_i64(i64 inreg %value, i64 inreg %amount) { 1458; GCN-LABEL: s_lshr_i64: 1459; GCN: ; %bb.0: 1460; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], s2 1461; GCN-NEXT: ; return to shader part epilog 1462; 1463; GFX10-LABEL: s_lshr_i64: 1464; GFX10: ; %bb.0: 1465; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], s2 1466; GFX10-NEXT: ; return to shader part epilog 1467 %result = lshr i64 %value, %amount 1468 ret i64 %result 1469} 1470 1471define amdgpu_ps i64 @s_lshr_i64_63(i64 inreg %value) { 1472; GCN-LABEL: s_lshr_i64_63: 1473; GCN: ; %bb.0: 1474; GCN-NEXT: s_lshr_b32 s0, s1, 31 1475; GCN-NEXT: s_mov_b32 s1, 0 1476; GCN-NEXT: ; return to shader part epilog 1477; 1478; GFX10-LABEL: s_lshr_i64_63: 1479; GFX10: ; %bb.0: 1480; GFX10-NEXT: s_lshr_b32 s0, s1, 31 1481; GFX10-NEXT: s_mov_b32 s1, 0 1482; GFX10-NEXT: ; return to shader part epilog 1483 %result = lshr i64 %value, 63 1484 ret i64 %result 1485} 1486 1487define amdgpu_ps i64 @s_lshr_i64_33(i64 inreg %value) { 1488; GCN-LABEL: s_lshr_i64_33: 1489; GCN: ; %bb.0: 1490; GCN-NEXT: s_lshr_b32 s0, s1, 1 1491; GCN-NEXT: s_mov_b32 s1, 0 1492; GCN-NEXT: ; return to shader part epilog 1493; 1494; GFX10-LABEL: s_lshr_i64_33: 1495; GFX10: ; %bb.0: 1496; GFX10-NEXT: s_lshr_b32 s0, s1, 1 1497; GFX10-NEXT: s_mov_b32 s1, 0 1498; GFX10-NEXT: ; return to shader part epilog 1499 %result = lshr i64 %value, 33 1500 ret i64 %result 1501} 1502 1503define amdgpu_ps i64 @s_lshr_i64_32(i64 inreg %value) { 1504; GCN-LABEL: s_lshr_i64_32: 1505; GCN: ; %bb.0: 1506; GCN-NEXT: s_mov_b32 s0, s1 1507; GCN-NEXT: s_mov_b32 s1, 0 1508; GCN-NEXT: ; return to shader part epilog 1509; 1510; GFX10-LABEL: s_lshr_i64_32: 1511; GFX10: ; %bb.0: 1512; GFX10-NEXT: s_mov_b32 s0, s1 1513; GFX10-NEXT: s_mov_b32 s1, 0 1514; GFX10-NEXT: ; return to shader part epilog 1515 %result = lshr i64 %value, 32 1516 ret i64 %result 1517} 1518 1519define amdgpu_ps i64 @s_lshr_i64_31(i64 inreg %value) { 1520; GCN-LABEL: s_lshr_i64_31: 1521; GCN: ; %bb.0: 1522; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], 31 1523; GCN-NEXT: ; return to shader part epilog 1524; 1525; GFX10-LABEL: s_lshr_i64_31: 1526; GFX10: ; %bb.0: 1527; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], 31 1528; GFX10-NEXT: ; return to shader part epilog 1529 %result = lshr i64 %value, 31 1530 ret i64 %result 1531} 1532 1533define amdgpu_ps <2 x float> @lshr_i64_sv(i64 inreg %value, i64 %amount) { 1534; GFX6-LABEL: lshr_i64_sv: 1535; GFX6: ; %bb.0: 1536; GFX6-NEXT: v_lshr_b64 v[0:1], s[0:1], v0 1537; GFX6-NEXT: ; return to shader part epilog 1538; 1539; GFX8-LABEL: lshr_i64_sv: 1540; GFX8: ; %bb.0: 1541; GFX8-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1] 1542; GFX8-NEXT: ; return to shader part epilog 1543; 1544; GFX9-LABEL: lshr_i64_sv: 1545; GFX9: ; %bb.0: 1546; GFX9-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1] 1547; GFX9-NEXT: ; return to shader part epilog 1548; 1549; GFX10-LABEL: lshr_i64_sv: 1550; GFX10: ; %bb.0: 1551; GFX10-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1] 1552; GFX10-NEXT: ; return to shader part epilog 1553 %result = lshr i64 %value, %amount 1554 %cast = bitcast i64 %result to <2 x float> 1555 ret <2 x float> %cast 1556} 1557 1558define amdgpu_ps <2 x float> @lshr_i64_vs(i64 %value, i64 inreg %amount) { 1559; GFX6-LABEL: lshr_i64_vs: 1560; GFX6: ; %bb.0: 1561; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], s0 1562; GFX6-NEXT: ; return to shader part epilog 1563; 1564; GFX8-LABEL: lshr_i64_vs: 1565; GFX8: ; %bb.0: 1566; GFX8-NEXT: v_lshrrev_b64 v[0:1], s0, v[0:1] 1567; GFX8-NEXT: ; return to shader part epilog 1568; 1569; GFX9-LABEL: lshr_i64_vs: 1570; GFX9: ; %bb.0: 1571; GFX9-NEXT: v_lshrrev_b64 v[0:1], s0, v[0:1] 1572; GFX9-NEXT: ; return to shader part epilog 1573; 1574; GFX10-LABEL: lshr_i64_vs: 1575; GFX10: ; %bb.0: 1576; GFX10-NEXT: v_lshrrev_b64 v[0:1], s0, v[0:1] 1577; GFX10-NEXT: ; return to shader part epilog 1578 %result = lshr i64 %value, %amount 1579 %cast = bitcast i64 %result to <2 x float> 1580 ret <2 x float> %cast 1581} 1582 1583define <2 x i64> @v_lshr_v2i64(<2 x i64> %value, <2 x i64> %amount) { 1584; GFX6-LABEL: v_lshr_v2i64: 1585; GFX6: ; %bb.0: 1586; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1587; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], v4 1588; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], v6 1589; GFX6-NEXT: s_setpc_b64 s[30:31] 1590; 1591; GFX8-LABEL: v_lshr_v2i64: 1592; GFX8: ; %bb.0: 1593; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1594; GFX8-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1] 1595; GFX8-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3] 1596; GFX8-NEXT: s_setpc_b64 s[30:31] 1597; 1598; GFX9-LABEL: v_lshr_v2i64: 1599; GFX9: ; %bb.0: 1600; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1601; GFX9-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1] 1602; GFX9-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3] 1603; GFX9-NEXT: s_setpc_b64 s[30:31] 1604; 1605; GFX10-LABEL: v_lshr_v2i64: 1606; GFX10: ; %bb.0: 1607; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1608; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1609; GFX10-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1] 1610; GFX10-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3] 1611; GFX10-NEXT: s_setpc_b64 s[30:31] 1612 %result = lshr <2 x i64> %value, %amount 1613 ret <2 x i64> %result 1614} 1615 1616define <2 x i64> @v_lshr_v2i64_31(<2 x i64> %value) { 1617; GFX6-LABEL: v_lshr_v2i64_31: 1618; GFX6: ; %bb.0: 1619; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1620; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 31 1621; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], 31 1622; GFX6-NEXT: s_setpc_b64 s[30:31] 1623; 1624; GFX8-LABEL: v_lshr_v2i64_31: 1625; GFX8: ; %bb.0: 1626; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1627; GFX8-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1628; GFX8-NEXT: v_lshrrev_b64 v[2:3], 31, v[2:3] 1629; GFX8-NEXT: s_setpc_b64 s[30:31] 1630; 1631; GFX9-LABEL: v_lshr_v2i64_31: 1632; GFX9: ; %bb.0: 1633; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1634; GFX9-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1635; GFX9-NEXT: v_lshrrev_b64 v[2:3], 31, v[2:3] 1636; GFX9-NEXT: s_setpc_b64 s[30:31] 1637; 1638; GFX10-LABEL: v_lshr_v2i64_31: 1639; GFX10: ; %bb.0: 1640; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1641; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1642; GFX10-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1643; GFX10-NEXT: v_lshrrev_b64 v[2:3], 31, v[2:3] 1644; GFX10-NEXT: s_setpc_b64 s[30:31] 1645 %result = lshr <2 x i64> %value, <i64 31, i64 31> 1646 ret <2 x i64> %result 1647} 1648 1649define amdgpu_ps <2 x i64> @s_lshr_v2i64(<2 x i64> inreg %value, <2 x i64> inreg %amount) { 1650; GCN-LABEL: s_lshr_v2i64: 1651; GCN: ; %bb.0: 1652; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], s4 1653; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], s6 1654; GCN-NEXT: ; return to shader part epilog 1655; 1656; GFX10-LABEL: s_lshr_v2i64: 1657; GFX10: ; %bb.0: 1658; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], s4 1659; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s6 1660; GFX10-NEXT: ; return to shader part epilog 1661 %result = lshr <2 x i64> %value, %amount 1662 ret <2 x i64> %result 1663} 1664