1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s 3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s 4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s 5; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s 6 7define i8 @v_lshr_i8(i8 %value, i8 %amount) { 8; GFX6-LABEL: v_lshr_i8: 9; GFX6: ; %bb.0: 10; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 11; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1 12; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0 13; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0 14; GFX6-NEXT: s_setpc_b64 s[30:31] 15; 16; GFX8-LABEL: v_lshr_i8: 17; GFX8: ; %bb.0: 18; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 19; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 20; GFX8-NEXT: s_setpc_b64 s[30:31] 21; 22; GFX9-LABEL: v_lshr_i8: 23; GFX9: ; %bb.0: 24; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 25; GFX9-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 26; GFX9-NEXT: s_setpc_b64 s[30:31] 27; 28; GFX10-LABEL: v_lshr_i8: 29; GFX10: ; %bb.0: 30; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 31; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 32; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1 33; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0 34; GFX10-NEXT: v_lshrrev_b16 v0, v1, v0 35; GFX10-NEXT: s_setpc_b64 s[30:31] 36 %result = lshr i8 %value, %amount 37 ret i8 %result 38} 39 40define i8 @v_lshr_i8_7(i8 %value) { 41; GFX6-LABEL: v_lshr_i8_7: 42; GFX6: ; %bb.0: 43; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 44; GFX6-NEXT: v_bfe_u32 v0, v0, 7, 1 45; GFX6-NEXT: s_setpc_b64 s[30:31] 46; 47; GFX8-LABEL: v_lshr_i8_7: 48; GFX8: ; %bb.0: 49; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 50; GFX8-NEXT: v_mov_b32_e32 v1, 7 51; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 52; GFX8-NEXT: s_setpc_b64 s[30:31] 53; 54; GFX9-LABEL: v_lshr_i8_7: 55; GFX9: ; %bb.0: 56; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 57; GFX9-NEXT: v_mov_b32_e32 v1, 7 58; GFX9-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 59; GFX9-NEXT: s_setpc_b64 s[30:31] 60; 61; GFX10-LABEL: v_lshr_i8_7: 62; GFX10: ; %bb.0: 63; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 64; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 65; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0 66; GFX10-NEXT: v_lshrrev_b16 v0, 7, v0 67; GFX10-NEXT: s_setpc_b64 s[30:31] 68 %result = lshr i8 %value, 7 69 ret i8 %result 70} 71 72define amdgpu_ps i8 @s_lshr_i8(i8 inreg %value, i8 inreg %amount) { 73; GCN-LABEL: s_lshr_i8: 74; GCN: ; %bb.0: 75; GCN-NEXT: s_and_b32 s0, s0, 0xff 76; GCN-NEXT: s_lshr_b32 s0, s0, s1 77; GCN-NEXT: ; return to shader part epilog 78; 79; GFX10-LABEL: s_lshr_i8: 80; GFX10: ; %bb.0: 81; GFX10-NEXT: s_and_b32 s0, s0, 0xff 82; GFX10-NEXT: s_lshr_b32 s0, s0, s1 83; GFX10-NEXT: ; return to shader part epilog 84 %result = lshr i8 %value, %amount 85 ret i8 %result 86} 87 88define amdgpu_ps i8 @s_lshr_i8_7(i8 inreg %value) { 89; GCN-LABEL: s_lshr_i8_7: 90; GCN: ; %bb.0: 91; GCN-NEXT: s_bfe_u32 s0, s0, 0x10007 92; GCN-NEXT: ; return to shader part epilog 93; 94; GFX10-LABEL: s_lshr_i8_7: 95; GFX10: ; %bb.0: 96; GFX10-NEXT: s_bfe_u32 s0, s0, 0x10007 97; GFX10-NEXT: ; return to shader part epilog 98 %result = lshr i8 %value, 7 99 ret i8 %result 100} 101 102 103define i24 @v_lshr_i24(i24 %value, i24 %amount) { 104; GCN-LABEL: v_lshr_i24: 105; GCN: ; %bb.0: 106; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 107; GCN-NEXT: v_and_b32_e32 v1, 0xffffff, v1 108; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 109; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0 110; GCN-NEXT: s_setpc_b64 s[30:31] 111; 112; GFX10-LABEL: v_lshr_i24: 113; GFX10: ; %bb.0: 114; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 115; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 116; GFX10-NEXT: v_and_b32_e32 v1, 0xffffff, v1 117; GFX10-NEXT: v_and_b32_e32 v0, 0xffffff, v0 118; GFX10-NEXT: v_lshrrev_b32_e32 v0, v1, v0 119; GFX10-NEXT: s_setpc_b64 s[30:31] 120 %result = lshr i24 %value, %amount 121 ret i24 %result 122} 123 124define i24 @v_lshr_i24_7(i24 %value) { 125; GCN-LABEL: v_lshr_i24_7: 126; GCN: ; %bb.0: 127; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 128; GCN-NEXT: v_bfe_u32 v0, v0, 7, 17 129; GCN-NEXT: s_setpc_b64 s[30:31] 130; 131; GFX10-LABEL: v_lshr_i24_7: 132; GFX10: ; %bb.0: 133; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 134; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 135; GFX10-NEXT: v_bfe_u32 v0, v0, 7, 17 136; GFX10-NEXT: s_setpc_b64 s[30:31] 137 %result = lshr i24 %value, 7 138 ret i24 %result 139} 140 141define amdgpu_ps i24 @s_lshr_i24(i24 inreg %value, i24 inreg %amount) { 142; GCN-LABEL: s_lshr_i24: 143; GCN: ; %bb.0: 144; GCN-NEXT: s_and_b32 s0, s0, 0xffffff 145; GCN-NEXT: s_lshr_b32 s0, s0, s1 146; GCN-NEXT: ; return to shader part epilog 147; 148; GFX10-LABEL: s_lshr_i24: 149; GFX10: ; %bb.0: 150; GFX10-NEXT: s_and_b32 s0, s0, 0xffffff 151; GFX10-NEXT: s_lshr_b32 s0, s0, s1 152; GFX10-NEXT: ; return to shader part epilog 153 %result = lshr i24 %value, %amount 154 ret i24 %result 155} 156 157define amdgpu_ps i24 @s_lshr_i24_7(i24 inreg %value) { 158; GCN-LABEL: s_lshr_i24_7: 159; GCN: ; %bb.0: 160; GCN-NEXT: s_bfe_u32 s0, s0, 0x110007 161; GCN-NEXT: ; return to shader part epilog 162; 163; GFX10-LABEL: s_lshr_i24_7: 164; GFX10: ; %bb.0: 165; GFX10-NEXT: s_bfe_u32 s0, s0, 0x110007 166; GFX10-NEXT: ; return to shader part epilog 167 %result = lshr i24 %value, 7 168 ret i24 %result 169} 170 171define i32 @v_lshr_i32(i32 %value, i32 %amount) { 172; GCN-LABEL: v_lshr_i32: 173; GCN: ; %bb.0: 174; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 175; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0 176; GCN-NEXT: s_setpc_b64 s[30:31] 177; 178; GFX10-LABEL: v_lshr_i32: 179; GFX10: ; %bb.0: 180; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 181; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 182; GFX10-NEXT: v_lshrrev_b32_e32 v0, v1, v0 183; GFX10-NEXT: s_setpc_b64 s[30:31] 184 %result = lshr i32 %value, %amount 185 ret i32 %result 186} 187 188define i32 @v_lshr_i32_31(i32 %value) { 189; GCN-LABEL: v_lshr_i32_31: 190; GCN: ; %bb.0: 191; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 192; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0 193; GCN-NEXT: s_setpc_b64 s[30:31] 194; 195; GFX10-LABEL: v_lshr_i32_31: 196; GFX10: ; %bb.0: 197; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 198; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 199; GFX10-NEXT: v_lshrrev_b32_e32 v0, 31, v0 200; GFX10-NEXT: s_setpc_b64 s[30:31] 201 %result = lshr i32 %value, 31 202 ret i32 %result 203} 204 205define amdgpu_ps i32 @s_lshr_i32(i32 inreg %value, i32 inreg %amount) { 206; GCN-LABEL: s_lshr_i32: 207; GCN: ; %bb.0: 208; GCN-NEXT: s_lshr_b32 s0, s0, s1 209; GCN-NEXT: ; return to shader part epilog 210; 211; GFX10-LABEL: s_lshr_i32: 212; GFX10: ; %bb.0: 213; GFX10-NEXT: s_lshr_b32 s0, s0, s1 214; GFX10-NEXT: ; return to shader part epilog 215 %result = lshr i32 %value, %amount 216 ret i32 %result 217} 218 219define amdgpu_ps i32 @s_lshr_i32_31(i32 inreg %value) { 220; GCN-LABEL: s_lshr_i32_31: 221; GCN: ; %bb.0: 222; GCN-NEXT: s_lshr_b32 s0, s0, 31 223; GCN-NEXT: ; return to shader part epilog 224; 225; GFX10-LABEL: s_lshr_i32_31: 226; GFX10: ; %bb.0: 227; GFX10-NEXT: s_lshr_b32 s0, s0, 31 228; GFX10-NEXT: ; return to shader part epilog 229 %result = lshr i32 %value, 31 230 ret i32 %result 231} 232 233define amdgpu_ps float @lshr_i32_sv(i32 inreg %value, i32 %amount) { 234; GFX6-LABEL: lshr_i32_sv: 235; GFX6: ; %bb.0: 236; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0 237; GFX6-NEXT: ; return to shader part epilog 238; 239; GFX8-LABEL: lshr_i32_sv: 240; GFX8: ; %bb.0: 241; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s0 242; GFX8-NEXT: ; return to shader part epilog 243; 244; GFX9-LABEL: lshr_i32_sv: 245; GFX9: ; %bb.0: 246; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s0 247; GFX9-NEXT: ; return to shader part epilog 248; 249; GFX10-LABEL: lshr_i32_sv: 250; GFX10: ; %bb.0: 251; GFX10-NEXT: v_lshrrev_b32_e64 v0, v0, s0 252; GFX10-NEXT: ; return to shader part epilog 253 %result = lshr i32 %value, %amount 254 %cast = bitcast i32 %result to float 255 ret float %cast 256} 257 258define amdgpu_ps float @lshr_i32_vs(i32 %value, i32 inreg %amount) { 259; GCN-LABEL: lshr_i32_vs: 260; GCN: ; %bb.0: 261; GCN-NEXT: v_lshrrev_b32_e32 v0, s0, v0 262; GCN-NEXT: ; return to shader part epilog 263; 264; GFX10-LABEL: lshr_i32_vs: 265; GFX10: ; %bb.0: 266; GFX10-NEXT: v_lshrrev_b32_e32 v0, s0, v0 267; GFX10-NEXT: ; return to shader part epilog 268 %result = lshr i32 %value, %amount 269 %cast = bitcast i32 %result to float 270 ret float %cast 271} 272 273define <2 x i32> @v_lshr_v2i32(<2 x i32> %value, <2 x i32> %amount) { 274; GCN-LABEL: v_lshr_v2i32: 275; GCN: ; %bb.0: 276; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 277; GCN-NEXT: v_lshrrev_b32_e32 v0, v2, v0 278; GCN-NEXT: v_lshrrev_b32_e32 v1, v3, v1 279; GCN-NEXT: s_setpc_b64 s[30:31] 280; 281; GFX10-LABEL: v_lshr_v2i32: 282; GFX10: ; %bb.0: 283; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 284; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 285; GFX10-NEXT: v_lshrrev_b32_e32 v0, v2, v0 286; GFX10-NEXT: v_lshrrev_b32_e32 v1, v3, v1 287; GFX10-NEXT: s_setpc_b64 s[30:31] 288 %result = lshr <2 x i32> %value, %amount 289 ret <2 x i32> %result 290} 291 292define <2 x i32> @v_lshr_v2i32_31(<2 x i32> %value) { 293; GCN-LABEL: v_lshr_v2i32_31: 294; GCN: ; %bb.0: 295; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 296; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0 297; GCN-NEXT: v_lshrrev_b32_e32 v1, 31, v1 298; GCN-NEXT: s_setpc_b64 s[30:31] 299; 300; GFX10-LABEL: v_lshr_v2i32_31: 301; GFX10: ; %bb.0: 302; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 303; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 304; GFX10-NEXT: v_lshrrev_b32_e32 v0, 31, v0 305; GFX10-NEXT: v_lshrrev_b32_e32 v1, 31, v1 306; GFX10-NEXT: s_setpc_b64 s[30:31] 307 %result = lshr <2 x i32> %value, <i32 31, i32 31> 308 ret <2 x i32> %result 309} 310 311define amdgpu_ps <2 x i32> @s_lshr_v2i32(<2 x i32> inreg %value, <2 x i32> inreg %amount) { 312; GCN-LABEL: s_lshr_v2i32: 313; GCN: ; %bb.0: 314; GCN-NEXT: s_lshr_b32 s0, s0, s2 315; GCN-NEXT: s_lshr_b32 s1, s1, s3 316; GCN-NEXT: ; return to shader part epilog 317; 318; GFX10-LABEL: s_lshr_v2i32: 319; GFX10: ; %bb.0: 320; GFX10-NEXT: s_lshr_b32 s0, s0, s2 321; GFX10-NEXT: s_lshr_b32 s1, s1, s3 322; GFX10-NEXT: ; return to shader part epilog 323 %result = lshr <2 x i32> %value, %amount 324 ret <2 x i32> %result 325} 326 327define <3 x i32> @v_lshr_v3i32(<3 x i32> %value, <3 x i32> %amount) { 328; GCN-LABEL: v_lshr_v3i32: 329; GCN: ; %bb.0: 330; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 331; GCN-NEXT: v_lshrrev_b32_e32 v0, v3, v0 332; GCN-NEXT: v_lshrrev_b32_e32 v1, v4, v1 333; GCN-NEXT: v_lshrrev_b32_e32 v2, v5, v2 334; GCN-NEXT: s_setpc_b64 s[30:31] 335; 336; GFX10-LABEL: v_lshr_v3i32: 337; GFX10: ; %bb.0: 338; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 339; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 340; GFX10-NEXT: v_lshrrev_b32_e32 v0, v3, v0 341; GFX10-NEXT: v_lshrrev_b32_e32 v1, v4, v1 342; GFX10-NEXT: v_lshrrev_b32_e32 v2, v5, v2 343; GFX10-NEXT: s_setpc_b64 s[30:31] 344 %result = lshr <3 x i32> %value, %amount 345 ret <3 x i32> %result 346} 347 348define amdgpu_ps <3 x i32> @s_lshr_v3i32(<3 x i32> inreg %value, <3 x i32> inreg %amount) { 349; GCN-LABEL: s_lshr_v3i32: 350; GCN: ; %bb.0: 351; GCN-NEXT: s_lshr_b32 s0, s0, s3 352; GCN-NEXT: s_lshr_b32 s1, s1, s4 353; GCN-NEXT: s_lshr_b32 s2, s2, s5 354; GCN-NEXT: ; return to shader part epilog 355; 356; GFX10-LABEL: s_lshr_v3i32: 357; GFX10: ; %bb.0: 358; GFX10-NEXT: s_lshr_b32 s0, s0, s3 359; GFX10-NEXT: s_lshr_b32 s1, s1, s4 360; GFX10-NEXT: s_lshr_b32 s2, s2, s5 361; GFX10-NEXT: ; return to shader part epilog 362 %result = lshr <3 x i32> %value, %amount 363 ret <3 x i32> %result 364} 365 366define <4 x i32> @v_lshr_v4i32(<4 x i32> %value, <4 x i32> %amount) { 367; GCN-LABEL: v_lshr_v4i32: 368; GCN: ; %bb.0: 369; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 370; GCN-NEXT: v_lshrrev_b32_e32 v0, v4, v0 371; GCN-NEXT: v_lshrrev_b32_e32 v1, v5, v1 372; GCN-NEXT: v_lshrrev_b32_e32 v2, v6, v2 373; GCN-NEXT: v_lshrrev_b32_e32 v3, v7, v3 374; GCN-NEXT: s_setpc_b64 s[30:31] 375; 376; GFX10-LABEL: v_lshr_v4i32: 377; GFX10: ; %bb.0: 378; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 379; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 380; GFX10-NEXT: v_lshrrev_b32_e32 v0, v4, v0 381; GFX10-NEXT: v_lshrrev_b32_e32 v1, v5, v1 382; GFX10-NEXT: v_lshrrev_b32_e32 v2, v6, v2 383; GFX10-NEXT: v_lshrrev_b32_e32 v3, v7, v3 384; GFX10-NEXT: s_setpc_b64 s[30:31] 385 %result = lshr <4 x i32> %value, %amount 386 ret <4 x i32> %result 387} 388 389define amdgpu_ps <4 x i32> @s_lshr_v4i32(<4 x i32> inreg %value, <4 x i32> inreg %amount) { 390; GCN-LABEL: s_lshr_v4i32: 391; GCN: ; %bb.0: 392; GCN-NEXT: s_lshr_b32 s0, s0, s4 393; GCN-NEXT: s_lshr_b32 s1, s1, s5 394; GCN-NEXT: s_lshr_b32 s2, s2, s6 395; GCN-NEXT: s_lshr_b32 s3, s3, s7 396; GCN-NEXT: ; return to shader part epilog 397; 398; GFX10-LABEL: s_lshr_v4i32: 399; GFX10: ; %bb.0: 400; GFX10-NEXT: s_lshr_b32 s0, s0, s4 401; GFX10-NEXT: s_lshr_b32 s1, s1, s5 402; GFX10-NEXT: s_lshr_b32 s2, s2, s6 403; GFX10-NEXT: s_lshr_b32 s3, s3, s7 404; GFX10-NEXT: ; return to shader part epilog 405 %result = lshr <4 x i32> %value, %amount 406 ret <4 x i32> %result 407} 408 409define <5 x i32> @v_lshr_v5i32(<5 x i32> %value, <5 x i32> %amount) { 410; GCN-LABEL: v_lshr_v5i32: 411; GCN: ; %bb.0: 412; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 413; GCN-NEXT: v_lshrrev_b32_e32 v0, v5, v0 414; GCN-NEXT: v_lshrrev_b32_e32 v1, v6, v1 415; GCN-NEXT: v_lshrrev_b32_e32 v2, v7, v2 416; GCN-NEXT: v_lshrrev_b32_e32 v3, v8, v3 417; GCN-NEXT: v_lshrrev_b32_e32 v4, v9, v4 418; GCN-NEXT: s_setpc_b64 s[30:31] 419; 420; GFX10-LABEL: v_lshr_v5i32: 421; GFX10: ; %bb.0: 422; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 423; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 424; GFX10-NEXT: v_lshrrev_b32_e32 v0, v5, v0 425; GFX10-NEXT: v_lshrrev_b32_e32 v1, v6, v1 426; GFX10-NEXT: v_lshrrev_b32_e32 v2, v7, v2 427; GFX10-NEXT: v_lshrrev_b32_e32 v3, v8, v3 428; GFX10-NEXT: v_lshrrev_b32_e32 v4, v9, v4 429; GFX10-NEXT: s_setpc_b64 s[30:31] 430 %result = lshr <5 x i32> %value, %amount 431 ret <5 x i32> %result 432} 433 434define amdgpu_ps <5 x i32> @s_lshr_v5i32(<5 x i32> inreg %value, <5 x i32> inreg %amount) { 435; GCN-LABEL: s_lshr_v5i32: 436; GCN: ; %bb.0: 437; GCN-NEXT: s_lshr_b32 s0, s0, s5 438; GCN-NEXT: s_lshr_b32 s1, s1, s6 439; GCN-NEXT: s_lshr_b32 s2, s2, s7 440; GCN-NEXT: s_lshr_b32 s3, s3, s8 441; GCN-NEXT: s_lshr_b32 s4, s4, s9 442; GCN-NEXT: ; return to shader part epilog 443; 444; GFX10-LABEL: s_lshr_v5i32: 445; GFX10: ; %bb.0: 446; GFX10-NEXT: s_lshr_b32 s0, s0, s5 447; GFX10-NEXT: s_lshr_b32 s1, s1, s6 448; GFX10-NEXT: s_lshr_b32 s2, s2, s7 449; GFX10-NEXT: s_lshr_b32 s3, s3, s8 450; GFX10-NEXT: s_lshr_b32 s4, s4, s9 451; GFX10-NEXT: ; return to shader part epilog 452 %result = lshr <5 x i32> %value, %amount 453 ret <5 x i32> %result 454} 455 456define <16 x i32> @v_lshr_v16i32(<16 x i32> %value, <16 x i32> %amount) { 457; GCN-LABEL: v_lshr_v16i32: 458; GCN: ; %bb.0: 459; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 460; GCN-NEXT: v_lshrrev_b32_e32 v0, v16, v0 461; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 462; GCN-NEXT: v_lshrrev_b32_e32 v1, v17, v1 463; GCN-NEXT: v_lshrrev_b32_e32 v2, v18, v2 464; GCN-NEXT: v_lshrrev_b32_e32 v3, v19, v3 465; GCN-NEXT: v_lshrrev_b32_e32 v4, v20, v4 466; GCN-NEXT: v_lshrrev_b32_e32 v5, v21, v5 467; GCN-NEXT: v_lshrrev_b32_e32 v6, v22, v6 468; GCN-NEXT: v_lshrrev_b32_e32 v7, v23, v7 469; GCN-NEXT: v_lshrrev_b32_e32 v8, v24, v8 470; GCN-NEXT: v_lshrrev_b32_e32 v9, v25, v9 471; GCN-NEXT: v_lshrrev_b32_e32 v10, v26, v10 472; GCN-NEXT: v_lshrrev_b32_e32 v11, v27, v11 473; GCN-NEXT: v_lshrrev_b32_e32 v12, v28, v12 474; GCN-NEXT: v_lshrrev_b32_e32 v13, v29, v13 475; GCN-NEXT: v_lshrrev_b32_e32 v14, v30, v14 476; GCN-NEXT: s_waitcnt vmcnt(0) 477; GCN-NEXT: v_lshrrev_b32_e32 v15, v16, v15 478; GCN-NEXT: s_setpc_b64 s[30:31] 479; 480; GFX10-LABEL: v_lshr_v16i32: 481; GFX10: ; %bb.0: 482; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 483; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 484; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32 485; GFX10-NEXT: v_lshrrev_b32_e32 v0, v16, v0 486; GFX10-NEXT: v_lshrrev_b32_e32 v1, v17, v1 487; GFX10-NEXT: v_lshrrev_b32_e32 v2, v18, v2 488; GFX10-NEXT: v_lshrrev_b32_e32 v3, v19, v3 489; GFX10-NEXT: v_lshrrev_b32_e32 v4, v20, v4 490; GFX10-NEXT: v_lshrrev_b32_e32 v5, v21, v5 491; GFX10-NEXT: v_lshrrev_b32_e32 v6, v22, v6 492; GFX10-NEXT: v_lshrrev_b32_e32 v7, v23, v7 493; GFX10-NEXT: v_lshrrev_b32_e32 v8, v24, v8 494; GFX10-NEXT: v_lshrrev_b32_e32 v9, v25, v9 495; GFX10-NEXT: v_lshrrev_b32_e32 v10, v26, v10 496; GFX10-NEXT: v_lshrrev_b32_e32 v11, v27, v11 497; GFX10-NEXT: v_lshrrev_b32_e32 v12, v28, v12 498; GFX10-NEXT: v_lshrrev_b32_e32 v13, v29, v13 499; GFX10-NEXT: v_lshrrev_b32_e32 v14, v30, v14 500; GFX10-NEXT: s_waitcnt vmcnt(0) 501; GFX10-NEXT: v_lshrrev_b32_e32 v15, v31, v15 502; GFX10-NEXT: s_setpc_b64 s[30:31] 503 %result = lshr <16 x i32> %value, %amount 504 ret <16 x i32> %result 505} 506 507define amdgpu_ps <16 x i32> @s_lshr_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) { 508; GCN-LABEL: s_lshr_v16i32: 509; GCN: ; %bb.0: 510; GCN-NEXT: s_lshr_b32 s0, s0, s16 511; GCN-NEXT: s_lshr_b32 s1, s1, s17 512; GCN-NEXT: s_lshr_b32 s2, s2, s18 513; GCN-NEXT: s_lshr_b32 s3, s3, s19 514; GCN-NEXT: s_lshr_b32 s4, s4, s20 515; GCN-NEXT: s_lshr_b32 s5, s5, s21 516; GCN-NEXT: s_lshr_b32 s6, s6, s22 517; GCN-NEXT: s_lshr_b32 s7, s7, s23 518; GCN-NEXT: s_lshr_b32 s8, s8, s24 519; GCN-NEXT: s_lshr_b32 s9, s9, s25 520; GCN-NEXT: s_lshr_b32 s10, s10, s26 521; GCN-NEXT: s_lshr_b32 s11, s11, s27 522; GCN-NEXT: s_lshr_b32 s12, s12, s28 523; GCN-NEXT: s_lshr_b32 s13, s13, s29 524; GCN-NEXT: s_lshr_b32 s14, s14, s30 525; GCN-NEXT: s_lshr_b32 s15, s15, s31 526; GCN-NEXT: ; return to shader part epilog 527; 528; GFX10-LABEL: s_lshr_v16i32: 529; GFX10: ; %bb.0: 530; GFX10-NEXT: s_lshr_b32 s0, s0, s16 531; GFX10-NEXT: s_lshr_b32 s1, s1, s17 532; GFX10-NEXT: s_lshr_b32 s2, s2, s18 533; GFX10-NEXT: s_lshr_b32 s3, s3, s19 534; GFX10-NEXT: s_lshr_b32 s4, s4, s20 535; GFX10-NEXT: s_lshr_b32 s5, s5, s21 536; GFX10-NEXT: s_lshr_b32 s6, s6, s22 537; GFX10-NEXT: s_lshr_b32 s7, s7, s23 538; GFX10-NEXT: s_lshr_b32 s8, s8, s24 539; GFX10-NEXT: s_lshr_b32 s9, s9, s25 540; GFX10-NEXT: s_lshr_b32 s10, s10, s26 541; GFX10-NEXT: s_lshr_b32 s11, s11, s27 542; GFX10-NEXT: s_lshr_b32 s12, s12, s28 543; GFX10-NEXT: s_lshr_b32 s13, s13, s29 544; GFX10-NEXT: s_lshr_b32 s14, s14, s30 545; GFX10-NEXT: s_lshr_b32 s15, s15, s31 546; GFX10-NEXT: ; return to shader part epilog 547 %result = lshr <16 x i32> %value, %amount 548 ret <16 x i32> %result 549} 550 551define i16 @v_lshr_i16(i16 %value, i16 %amount) { 552; GFX6-LABEL: v_lshr_i16: 553; GFX6: ; %bb.0: 554; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 555; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 556; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 557; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0 558; GFX6-NEXT: s_setpc_b64 s[30:31] 559; 560; GFX8-LABEL: v_lshr_i16: 561; GFX8: ; %bb.0: 562; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 563; GFX8-NEXT: v_lshrrev_b16_e32 v0, v1, v0 564; GFX8-NEXT: s_setpc_b64 s[30:31] 565; 566; GFX9-LABEL: v_lshr_i16: 567; GFX9: ; %bb.0: 568; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 569; GFX9-NEXT: v_lshrrev_b16_e32 v0, v1, v0 570; GFX9-NEXT: s_setpc_b64 s[30:31] 571; 572; GFX10-LABEL: v_lshr_i16: 573; GFX10: ; %bb.0: 574; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 575; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 576; GFX10-NEXT: v_lshrrev_b16 v0, v1, v0 577; GFX10-NEXT: s_setpc_b64 s[30:31] 578 %result = lshr i16 %value, %amount 579 ret i16 %result 580} 581 582define i16 @v_lshr_i16_31(i16 %value) { 583; GCN-LABEL: v_lshr_i16_31: 584; GCN: ; %bb.0: 585; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 586; GCN-NEXT: s_setpc_b64 s[30:31] 587; 588; GFX10-LABEL: v_lshr_i16_31: 589; GFX10: ; %bb.0: 590; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 591; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 592; GFX10-NEXT: s_setpc_b64 s[30:31] 593 %result = lshr i16 %value, 31 594 ret i16 %result 595} 596 597define amdgpu_ps i16 @s_lshr_i16(i16 inreg %value, i16 inreg %amount) { 598; GCN-LABEL: s_lshr_i16: 599; GCN: ; %bb.0: 600; GCN-NEXT: s_and_b32 s0, s0, 0xffff 601; GCN-NEXT: s_lshr_b32 s0, s0, s1 602; GCN-NEXT: ; return to shader part epilog 603; 604; GFX10-LABEL: s_lshr_i16: 605; GFX10: ; %bb.0: 606; GFX10-NEXT: s_and_b32 s0, s0, 0xffff 607; GFX10-NEXT: s_lshr_b32 s0, s0, s1 608; GFX10-NEXT: ; return to shader part epilog 609 %result = lshr i16 %value, %amount 610 ret i16 %result 611} 612 613define amdgpu_ps i16 @s_lshr_i16_15(i16 inreg %value) { 614; GCN-LABEL: s_lshr_i16_15: 615; GCN: ; %bb.0: 616; GCN-NEXT: s_bfe_u32 s0, s0, 0x1000f 617; GCN-NEXT: ; return to shader part epilog 618; 619; GFX10-LABEL: s_lshr_i16_15: 620; GFX10: ; %bb.0: 621; GFX10-NEXT: s_bfe_u32 s0, s0, 0x1000f 622; GFX10-NEXT: ; return to shader part epilog 623 %result = lshr i16 %value, 15 624 ret i16 %result 625} 626 627define amdgpu_ps half @lshr_i16_sv(i16 inreg %value, i16 %amount) { 628; GFX6-LABEL: lshr_i16_sv: 629; GFX6: ; %bb.0: 630; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 631; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 632; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0 633; GFX6-NEXT: ; return to shader part epilog 634; 635; GFX8-LABEL: lshr_i16_sv: 636; GFX8: ; %bb.0: 637; GFX8-NEXT: v_lshrrev_b16_e64 v0, v0, s0 638; GFX8-NEXT: ; return to shader part epilog 639; 640; GFX9-LABEL: lshr_i16_sv: 641; GFX9: ; %bb.0: 642; GFX9-NEXT: v_lshrrev_b16_e64 v0, v0, s0 643; GFX9-NEXT: ; return to shader part epilog 644; 645; GFX10-LABEL: lshr_i16_sv: 646; GFX10: ; %bb.0: 647; GFX10-NEXT: v_lshrrev_b16 v0, v0, s0 648; GFX10-NEXT: ; return to shader part epilog 649 %result = lshr i16 %value, %amount 650 %cast = bitcast i16 %result to half 651 ret half %cast 652} 653 654define amdgpu_ps half @lshr_i16_vs(i16 %value, i16 inreg %amount) { 655; GFX6-LABEL: lshr_i16_vs: 656; GFX6: ; %bb.0: 657; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 658; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 659; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0 660; GFX6-NEXT: ; return to shader part epilog 661; 662; GFX8-LABEL: lshr_i16_vs: 663; GFX8: ; %bb.0: 664; GFX8-NEXT: v_lshrrev_b16_e32 v0, s0, v0 665; GFX8-NEXT: ; return to shader part epilog 666; 667; GFX9-LABEL: lshr_i16_vs: 668; GFX9: ; %bb.0: 669; GFX9-NEXT: v_lshrrev_b16_e32 v0, s0, v0 670; GFX9-NEXT: ; return to shader part epilog 671; 672; GFX10-LABEL: lshr_i16_vs: 673; GFX10: ; %bb.0: 674; GFX10-NEXT: v_lshrrev_b16 v0, s0, v0 675; GFX10-NEXT: ; return to shader part epilog 676 %result = lshr i16 %value, %amount 677 %cast = bitcast i16 %result to half 678 ret half %cast 679} 680 681define <2 x i16> @v_lshr_v2i16(<2 x i16> %value, <2 x i16> %amount) { 682; GFX6-LABEL: v_lshr_v2i16: 683; GFX6: ; %bb.0: 684; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 685; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2 686; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 687; GFX6-NEXT: v_lshrrev_b32_e32 v0, v2, v0 688; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3 689; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 690; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1 691; GFX6-NEXT: s_setpc_b64 s[30:31] 692; 693; GFX8-LABEL: v_lshr_v2i16: 694; GFX8: ; %bb.0: 695; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 696; GFX8-NEXT: v_lshrrev_b16_e32 v2, v1, v0 697; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 698; GFX8-NEXT: v_or_b32_e32 v0, v2, v0 699; GFX8-NEXT: s_setpc_b64 s[30:31] 700; 701; GFX9-LABEL: v_lshr_v2i16: 702; GFX9: ; %bb.0: 703; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 704; GFX9-NEXT: v_pk_lshrrev_b16 v0, v1, v0 705; GFX9-NEXT: s_setpc_b64 s[30:31] 706; 707; GFX10-LABEL: v_lshr_v2i16: 708; GFX10: ; %bb.0: 709; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 710; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 711; GFX10-NEXT: v_pk_lshrrev_b16 v0, v1, v0 712; GFX10-NEXT: s_setpc_b64 s[30:31] 713 %result = lshr <2 x i16> %value, %amount 714 ret <2 x i16> %result 715} 716 717define <2 x i16> @v_lshr_v2i16_15(<2 x i16> %value) { 718; GFX6-LABEL: v_lshr_v2i16_15: 719; GFX6: ; %bb.0: 720; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 721; GFX6-NEXT: v_bfe_u32 v0, v0, 15, 1 722; GFX6-NEXT: v_bfe_u32 v1, v1, 15, 1 723; GFX6-NEXT: s_setpc_b64 s[30:31] 724; 725; GFX8-LABEL: v_lshr_v2i16_15: 726; GFX8: ; %bb.0: 727; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 728; GFX8-NEXT: v_mov_b32_e32 v2, 15 729; GFX8-NEXT: v_lshrrev_b16_e32 v1, 15, v0 730; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 731; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 732; GFX8-NEXT: s_setpc_b64 s[30:31] 733; 734; GFX9-LABEL: v_lshr_v2i16_15: 735; GFX9: ; %bb.0: 736; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 737; GFX9-NEXT: v_pk_lshrrev_b16 v0, 15, v0 op_sel_hi:[0,1] 738; GFX9-NEXT: s_setpc_b64 s[30:31] 739; 740; GFX10-LABEL: v_lshr_v2i16_15: 741; GFX10: ; %bb.0: 742; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 743; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 744; GFX10-NEXT: v_pk_lshrrev_b16 v0, 15, v0 op_sel_hi:[0,1] 745; GFX10-NEXT: s_setpc_b64 s[30:31] 746 %result = lshr <2 x i16> %value, <i16 15, i16 15> 747 ret <2 x i16> %result 748} 749 750define amdgpu_ps i32 @s_lshr_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) { 751; GFX6-LABEL: s_lshr_v2i16: 752; GFX6: ; %bb.0: 753; GFX6-NEXT: s_and_b32 s1, s1, 0xffff 754; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 755; GFX6-NEXT: s_lshr_b32 s1, s1, s3 756; GFX6-NEXT: s_lshr_b32 s0, s0, s2 757; GFX6-NEXT: s_lshl_b32 s1, s1, 16 758; GFX6-NEXT: s_or_b32 s0, s0, s1 759; GFX6-NEXT: ; return to shader part epilog 760; 761; GFX8-LABEL: s_lshr_v2i16: 762; GFX8: ; %bb.0: 763; GFX8-NEXT: s_lshr_b32 s2, s0, 16 764; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 765; GFX8-NEXT: s_lshr_b32 s3, s1, 16 766; GFX8-NEXT: s_lshr_b32 s0, s0, s1 767; GFX8-NEXT: s_lshr_b32 s1, s2, s3 768; GFX8-NEXT: s_lshl_b32 s1, s1, 16 769; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 770; GFX8-NEXT: s_or_b32 s0, s1, s0 771; GFX8-NEXT: ; return to shader part epilog 772; 773; GFX9-LABEL: s_lshr_v2i16: 774; GFX9: ; %bb.0: 775; GFX9-NEXT: s_lshr_b32 s2, s0, 16 776; GFX9-NEXT: s_and_b32 s0, s0, 0xffff 777; GFX9-NEXT: s_lshr_b32 s3, s1, 16 778; GFX9-NEXT: s_lshr_b32 s0, s0, s1 779; GFX9-NEXT: s_lshr_b32 s1, s2, s3 780; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1 781; GFX9-NEXT: ; return to shader part epilog 782; 783; GFX10-LABEL: s_lshr_v2i16: 784; GFX10: ; %bb.0: 785; GFX10-NEXT: s_lshr_b32 s2, s0, 16 786; GFX10-NEXT: s_and_b32 s0, s0, 0xffff 787; GFX10-NEXT: s_lshr_b32 s3, s1, 16 788; GFX10-NEXT: s_lshr_b32 s0, s0, s1 789; GFX10-NEXT: s_lshr_b32 s1, s2, s3 790; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1 791; GFX10-NEXT: ; return to shader part epilog 792 %result = lshr <2 x i16> %value, %amount 793 %cast = bitcast <2 x i16> %result to i32 794 ret i32 %cast 795} 796 797define amdgpu_ps float @lshr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) { 798; GFX6-LABEL: lshr_v2i16_sv: 799; GFX6: ; %bb.0: 800; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 801; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 802; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0 803; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 804; GFX6-NEXT: s_and_b32 s0, s1, 0xffff 805; GFX6-NEXT: v_lshr_b32_e32 v1, s0, v1 806; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 807; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 808; GFX6-NEXT: ; return to shader part epilog 809; 810; GFX8-LABEL: lshr_v2i16_sv: 811; GFX8: ; %bb.0: 812; GFX8-NEXT: s_lshr_b32 s1, s0, 16 813; GFX8-NEXT: v_mov_b32_e32 v2, s1 814; GFX8-NEXT: v_lshrrev_b16_e64 v1, v0, s0 815; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 816; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 817; GFX8-NEXT: ; return to shader part epilog 818; 819; GFX9-LABEL: lshr_v2i16_sv: 820; GFX9: ; %bb.0: 821; GFX9-NEXT: v_pk_lshrrev_b16 v0, v0, s0 822; GFX9-NEXT: ; return to shader part epilog 823; 824; GFX10-LABEL: lshr_v2i16_sv: 825; GFX10: ; %bb.0: 826; GFX10-NEXT: v_pk_lshrrev_b16 v0, v0, s0 827; GFX10-NEXT: ; return to shader part epilog 828 %result = lshr <2 x i16> %value, %amount 829 %cast = bitcast <2 x i16> %result to float 830 ret float %cast 831} 832 833define amdgpu_ps float @lshr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) { 834; GFX6-LABEL: lshr_v2i16_vs: 835; GFX6: ; %bb.0: 836; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 837; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 838; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0 839; GFX6-NEXT: s_and_b32 s0, s1, 0xffff 840; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 841; GFX6-NEXT: v_lshrrev_b32_e32 v1, s0, v1 842; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 843; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 844; GFX6-NEXT: ; return to shader part epilog 845; 846; GFX8-LABEL: lshr_v2i16_vs: 847; GFX8: ; %bb.0: 848; GFX8-NEXT: s_lshr_b32 s1, s0, 16 849; GFX8-NEXT: v_mov_b32_e32 v2, s1 850; GFX8-NEXT: v_lshrrev_b16_e32 v1, s0, v0 851; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 852; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 853; GFX8-NEXT: ; return to shader part epilog 854; 855; GFX9-LABEL: lshr_v2i16_vs: 856; GFX9: ; %bb.0: 857; GFX9-NEXT: v_pk_lshrrev_b16 v0, s0, v0 858; GFX9-NEXT: ; return to shader part epilog 859; 860; GFX10-LABEL: lshr_v2i16_vs: 861; GFX10: ; %bb.0: 862; GFX10-NEXT: v_pk_lshrrev_b16 v0, s0, v0 863; GFX10-NEXT: ; return to shader part epilog 864 %result = lshr <2 x i16> %value, %amount 865 %cast = bitcast <2 x i16> %result to float 866 ret float %cast 867} 868 869; FIXME 870; define <3 x i16> @v_lshr_v3i16(<3 x i16> %value, <3 x i16> %amount) { 871; %result = lshr <3 x i16> %value, %amount 872; ret <3 x i16> %result 873; } 874 875; define amdgpu_ps <3 x i16> @s_lshr_v3i16(<3 x i16> inreg %value, <3 x i16> inreg %amount) { 876; %result = lshr <3 x i16> %value, %amount 877; ret <3 x i16> %result 878; } 879 880define <2 x float> @v_lshr_v4i16(<4 x i16> %value, <4 x i16> %amount) { 881; GFX6-LABEL: v_lshr_v4i16: 882; GFX6: ; %bb.0: 883; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 884; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4 885; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 886; GFX6-NEXT: v_lshrrev_b32_e32 v0, v4, v0 887; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v5 888; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 889; GFX6-NEXT: v_lshrrev_b32_e32 v1, v4, v1 890; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v6 891; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2 892; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2 893; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v7 894; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3 895; GFX6-NEXT: v_lshrrev_b32_e32 v3, v4, v3 896; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 897; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 898; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3 899; GFX6-NEXT: v_or_b32_e32 v1, v2, v1 900; GFX6-NEXT: s_setpc_b64 s[30:31] 901; 902; GFX8-LABEL: v_lshr_v4i16: 903; GFX8: ; %bb.0: 904; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 905; GFX8-NEXT: v_lshrrev_b16_e32 v4, v2, v0 906; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 907; GFX8-NEXT: v_lshrrev_b16_e32 v2, v3, v1 908; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 909; GFX8-NEXT: v_or_b32_e32 v0, v4, v0 910; GFX8-NEXT: v_or_b32_e32 v1, v2, v1 911; GFX8-NEXT: s_setpc_b64 s[30:31] 912; 913; GFX9-LABEL: v_lshr_v4i16: 914; GFX9: ; %bb.0: 915; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 916; GFX9-NEXT: v_pk_lshrrev_b16 v0, v2, v0 917; GFX9-NEXT: v_pk_lshrrev_b16 v1, v3, v1 918; GFX9-NEXT: s_setpc_b64 s[30:31] 919; 920; GFX10-LABEL: v_lshr_v4i16: 921; GFX10: ; %bb.0: 922; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 923; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 924; GFX10-NEXT: v_pk_lshrrev_b16 v0, v2, v0 925; GFX10-NEXT: v_pk_lshrrev_b16 v1, v3, v1 926; GFX10-NEXT: s_setpc_b64 s[30:31] 927 %result = lshr <4 x i16> %value, %amount 928 %cast = bitcast <4 x i16> %result to <2 x float> 929 ret <2 x float> %cast 930} 931 932define amdgpu_ps <2 x i32> @s_lshr_v4i16(<4 x i16> inreg %value, <4 x i16> inreg %amount) { 933; GFX6-LABEL: s_lshr_v4i16: 934; GFX6: ; %bb.0: 935; GFX6-NEXT: s_and_b32 s1, s1, 0xffff 936; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 937; GFX6-NEXT: s_lshr_b32 s1, s1, s5 938; GFX6-NEXT: s_and_b32 s3, s3, 0xffff 939; GFX6-NEXT: s_lshr_b32 s0, s0, s4 940; GFX6-NEXT: s_and_b32 s2, s2, 0xffff 941; GFX6-NEXT: s_lshr_b32 s3, s3, s7 942; GFX6-NEXT: s_lshl_b32 s1, s1, 16 943; GFX6-NEXT: s_lshr_b32 s2, s2, s6 944; GFX6-NEXT: s_or_b32 s0, s0, s1 945; GFX6-NEXT: s_lshl_b32 s1, s3, 16 946; GFX6-NEXT: s_or_b32 s1, s2, s1 947; GFX6-NEXT: ; return to shader part epilog 948; 949; GFX8-LABEL: s_lshr_v4i16: 950; GFX8: ; %bb.0: 951; GFX8-NEXT: s_lshr_b32 s4, s0, 16 952; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 953; GFX8-NEXT: s_lshr_b32 s6, s2, 16 954; GFX8-NEXT: s_lshr_b32 s5, s1, 16 955; GFX8-NEXT: s_and_b32 s1, s1, 0xffff 956; GFX8-NEXT: s_lshr_b32 s7, s3, 16 957; GFX8-NEXT: s_lshr_b32 s0, s0, s2 958; GFX8-NEXT: s_lshr_b32 s2, s4, s6 959; GFX8-NEXT: s_lshr_b32 s1, s1, s3 960; GFX8-NEXT: s_lshr_b32 s3, s5, s7 961; GFX8-NEXT: s_lshl_b32 s2, s2, 16 962; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 963; GFX8-NEXT: s_or_b32 s0, s2, s0 964; GFX8-NEXT: s_lshl_b32 s2, s3, 16 965; GFX8-NEXT: s_and_b32 s1, s1, 0xffff 966; GFX8-NEXT: s_or_b32 s1, s2, s1 967; GFX8-NEXT: ; return to shader part epilog 968; 969; GFX9-LABEL: s_lshr_v4i16: 970; GFX9: ; %bb.0: 971; GFX9-NEXT: s_lshr_b32 s4, s0, 16 972; GFX9-NEXT: s_and_b32 s0, s0, 0xffff 973; GFX9-NEXT: s_lshr_b32 s5, s2, 16 974; GFX9-NEXT: s_lshr_b32 s0, s0, s2 975; GFX9-NEXT: s_lshr_b32 s2, s4, s5 976; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2 977; GFX9-NEXT: s_lshr_b32 s2, s1, 16 978; GFX9-NEXT: s_and_b32 s1, s1, 0xffff 979; GFX9-NEXT: s_lshr_b32 s4, s3, 16 980; GFX9-NEXT: s_lshr_b32 s1, s1, s3 981; GFX9-NEXT: s_lshr_b32 s2, s2, s4 982; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2 983; GFX9-NEXT: ; return to shader part epilog 984; 985; GFX10-LABEL: s_lshr_v4i16: 986; GFX10: ; %bb.0: 987; GFX10-NEXT: s_lshr_b32 s4, s0, 16 988; GFX10-NEXT: s_and_b32 s0, s0, 0xffff 989; GFX10-NEXT: s_lshr_b32 s5, s2, 16 990; GFX10-NEXT: s_lshr_b32 s0, s0, s2 991; GFX10-NEXT: s_lshr_b32 s2, s4, s5 992; GFX10-NEXT: s_lshr_b32 s4, s1, 16 993; GFX10-NEXT: s_and_b32 s1, s1, 0xffff 994; GFX10-NEXT: s_lshr_b32 s5, s3, 16 995; GFX10-NEXT: s_lshr_b32 s1, s1, s3 996; GFX10-NEXT: s_lshr_b32 s3, s4, s5 997; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2 998; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3 999; GFX10-NEXT: ; return to shader part epilog 1000 %result = lshr <4 x i16> %value, %amount 1001 %cast = bitcast <4 x i16> %result to <2 x i32> 1002 ret <2 x i32> %cast 1003} 1004 1005; FIXME 1006; define <5 x i16> @v_lshr_v5i16(<5 x i16> %value, <5 x i16> %amount) { 1007; %result = lshr <5 x i16> %value, %amount 1008; ret <5 x i16> %result 1009; } 1010 1011; define amdgpu_ps <5 x i16> @s_lshr_v5i16(<5 x i16> inreg %value, <5 x i16> inreg %amount) { 1012; %result = lshr <5 x i16> %value, %amount 1013; ret <5 x i16> %result 1014; } 1015 1016; define <3 x float> @v_lshr_v6i16(<6 x i16> %value, <6 x i16> %amount) { 1017; %result = lshr <6 x i16> %value, %amount 1018; %cast = bitcast <6 x i16> %result to <3 x float> 1019; ret <3 x float> %cast 1020; } 1021 1022; define amdgpu_ps <3 x i32> @s_lshr_v6i16(<6 x i16> inreg %value, <6 x i16> inreg %amount) { 1023; %result = lshr <6 x i16> %value, %amount 1024; %cast = bitcast <6 x i16> %result to <3 x i32> 1025; ret <3 x i32> %cast 1026; } 1027 1028define <4 x float> @v_lshr_v8i16(<8 x i16> %value, <8 x i16> %amount) { 1029; GFX6-LABEL: v_lshr_v8i16: 1030; GFX6: ; %bb.0: 1031; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1032; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v8 1033; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 1034; GFX6-NEXT: v_lshrrev_b32_e32 v0, v8, v0 1035; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v9 1036; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 1037; GFX6-NEXT: v_lshrrev_b32_e32 v1, v8, v1 1038; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v10 1039; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2 1040; GFX6-NEXT: v_lshrrev_b32_e32 v2, v8, v2 1041; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v11 1042; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3 1043; GFX6-NEXT: v_lshrrev_b32_e32 v3, v8, v3 1044; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v12 1045; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4 1046; GFX6-NEXT: v_lshrrev_b32_e32 v4, v8, v4 1047; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v13 1048; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v5 1049; GFX6-NEXT: v_lshrrev_b32_e32 v5, v8, v5 1050; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v14 1051; GFX6-NEXT: v_and_b32_e32 v6, 0xffff, v6 1052; GFX6-NEXT: v_lshrrev_b32_e32 v6, v8, v6 1053; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v15 1054; GFX6-NEXT: v_and_b32_e32 v7, 0xffff, v7 1055; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1056; GFX6-NEXT: v_lshrrev_b32_e32 v7, v8, v7 1057; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 1058; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3 1059; GFX6-NEXT: v_or_b32_e32 v1, v2, v1 1060; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v5 1061; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v7 1062; GFX6-NEXT: v_or_b32_e32 v2, v4, v2 1063; GFX6-NEXT: v_or_b32_e32 v3, v6, v3 1064; GFX6-NEXT: s_setpc_b64 s[30:31] 1065; 1066; GFX8-LABEL: v_lshr_v8i16: 1067; GFX8: ; %bb.0: 1068; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1069; GFX8-NEXT: v_lshrrev_b16_e32 v8, v4, v0 1070; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1071; GFX8-NEXT: v_lshrrev_b16_e32 v4, v5, v1 1072; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1073; GFX8-NEXT: v_or_b32_e32 v1, v4, v1 1074; GFX8-NEXT: v_lshrrev_b16_e32 v4, v6, v2 1075; GFX8-NEXT: v_lshrrev_b16_sdwa v2, v6, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1076; GFX8-NEXT: v_or_b32_e32 v2, v4, v2 1077; GFX8-NEXT: v_lshrrev_b16_e32 v4, v7, v3 1078; GFX8-NEXT: v_lshrrev_b16_sdwa v3, v7, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1079; GFX8-NEXT: v_or_b32_e32 v0, v8, v0 1080; GFX8-NEXT: v_or_b32_e32 v3, v4, v3 1081; GFX8-NEXT: s_setpc_b64 s[30:31] 1082; 1083; GFX9-LABEL: v_lshr_v8i16: 1084; GFX9: ; %bb.0: 1085; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1086; GFX9-NEXT: v_pk_lshrrev_b16 v0, v4, v0 1087; GFX9-NEXT: v_pk_lshrrev_b16 v1, v5, v1 1088; GFX9-NEXT: v_pk_lshrrev_b16 v2, v6, v2 1089; GFX9-NEXT: v_pk_lshrrev_b16 v3, v7, v3 1090; GFX9-NEXT: s_setpc_b64 s[30:31] 1091; 1092; GFX10-LABEL: v_lshr_v8i16: 1093; GFX10: ; %bb.0: 1094; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1095; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1096; GFX10-NEXT: v_pk_lshrrev_b16 v0, v4, v0 1097; GFX10-NEXT: v_pk_lshrrev_b16 v1, v5, v1 1098; GFX10-NEXT: v_pk_lshrrev_b16 v2, v6, v2 1099; GFX10-NEXT: v_pk_lshrrev_b16 v3, v7, v3 1100; GFX10-NEXT: s_setpc_b64 s[30:31] 1101 %result = lshr <8 x i16> %value, %amount 1102 %cast = bitcast <8 x i16> %result to <4 x float> 1103 ret <4 x float> %cast 1104} 1105 1106define amdgpu_ps <4 x i32> @s_lshr_v8i16(<8 x i16> inreg %value, <8 x i16> inreg %amount) { 1107; GFX6-LABEL: s_lshr_v8i16: 1108; GFX6: ; %bb.0: 1109; GFX6-NEXT: s_and_b32 s1, s1, 0xffff 1110; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 1111; GFX6-NEXT: s_lshr_b32 s1, s1, s9 1112; GFX6-NEXT: s_and_b32 s3, s3, 0xffff 1113; GFX6-NEXT: s_lshr_b32 s0, s0, s8 1114; GFX6-NEXT: s_and_b32 s2, s2, 0xffff 1115; GFX6-NEXT: s_lshr_b32 s3, s3, s11 1116; GFX6-NEXT: s_and_b32 s5, s5, 0xffff 1117; GFX6-NEXT: s_and_b32 s7, s7, 0xffff 1118; GFX6-NEXT: s_lshl_b32 s1, s1, 16 1119; GFX6-NEXT: s_lshr_b32 s2, s2, s10 1120; GFX6-NEXT: s_and_b32 s4, s4, 0xffff 1121; GFX6-NEXT: s_lshr_b32 s5, s5, s13 1122; GFX6-NEXT: s_and_b32 s6, s6, 0xffff 1123; GFX6-NEXT: s_lshr_b32 s7, s7, s15 1124; GFX6-NEXT: s_or_b32 s0, s0, s1 1125; GFX6-NEXT: s_lshl_b32 s1, s3, 16 1126; GFX6-NEXT: s_lshr_b32 s4, s4, s12 1127; GFX6-NEXT: s_lshr_b32 s6, s6, s14 1128; GFX6-NEXT: s_or_b32 s1, s2, s1 1129; GFX6-NEXT: s_lshl_b32 s2, s5, 16 1130; GFX6-NEXT: s_lshl_b32 s3, s7, 16 1131; GFX6-NEXT: s_or_b32 s2, s4, s2 1132; GFX6-NEXT: s_or_b32 s3, s6, s3 1133; GFX6-NEXT: ; return to shader part epilog 1134; 1135; GFX8-LABEL: s_lshr_v8i16: 1136; GFX8: ; %bb.0: 1137; GFX8-NEXT: s_lshr_b32 s8, s0, 16 1138; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 1139; GFX8-NEXT: s_lshr_b32 s12, s4, 16 1140; GFX8-NEXT: s_lshr_b32 s9, s1, 16 1141; GFX8-NEXT: s_and_b32 s1, s1, 0xffff 1142; GFX8-NEXT: s_lshr_b32 s13, s5, 16 1143; GFX8-NEXT: s_lshr_b32 s0, s0, s4 1144; GFX8-NEXT: s_lshr_b32 s4, s8, s12 1145; GFX8-NEXT: s_lshr_b32 s10, s2, 16 1146; GFX8-NEXT: s_and_b32 s2, s2, 0xffff 1147; GFX8-NEXT: s_lshr_b32 s14, s6, 16 1148; GFX8-NEXT: s_lshr_b32 s1, s1, s5 1149; GFX8-NEXT: s_lshr_b32 s5, s9, s13 1150; GFX8-NEXT: s_lshl_b32 s4, s4, 16 1151; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 1152; GFX8-NEXT: s_lshr_b32 s11, s3, 16 1153; GFX8-NEXT: s_and_b32 s3, s3, 0xffff 1154; GFX8-NEXT: s_lshr_b32 s15, s7, 16 1155; GFX8-NEXT: s_lshr_b32 s2, s2, s6 1156; GFX8-NEXT: s_lshr_b32 s6, s10, s14 1157; GFX8-NEXT: s_or_b32 s0, s4, s0 1158; GFX8-NEXT: s_lshl_b32 s4, s5, 16 1159; GFX8-NEXT: s_and_b32 s1, s1, 0xffff 1160; GFX8-NEXT: s_lshr_b32 s3, s3, s7 1161; GFX8-NEXT: s_lshr_b32 s7, s11, s15 1162; GFX8-NEXT: s_or_b32 s1, s4, s1 1163; GFX8-NEXT: s_lshl_b32 s4, s6, 16 1164; GFX8-NEXT: s_and_b32 s2, s2, 0xffff 1165; GFX8-NEXT: s_or_b32 s2, s4, s2 1166; GFX8-NEXT: s_lshl_b32 s4, s7, 16 1167; GFX8-NEXT: s_and_b32 s3, s3, 0xffff 1168; GFX8-NEXT: s_or_b32 s3, s4, s3 1169; GFX8-NEXT: ; return to shader part epilog 1170; 1171; GFX9-LABEL: s_lshr_v8i16: 1172; GFX9: ; %bb.0: 1173; GFX9-NEXT: s_lshr_b32 s8, s0, 16 1174; GFX9-NEXT: s_and_b32 s0, s0, 0xffff 1175; GFX9-NEXT: s_lshr_b32 s9, s4, 16 1176; GFX9-NEXT: s_lshr_b32 s0, s0, s4 1177; GFX9-NEXT: s_lshr_b32 s4, s8, s9 1178; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s4 1179; GFX9-NEXT: s_lshr_b32 s4, s1, 16 1180; GFX9-NEXT: s_and_b32 s1, s1, 0xffff 1181; GFX9-NEXT: s_lshr_b32 s8, s5, 16 1182; GFX9-NEXT: s_lshr_b32 s1, s1, s5 1183; GFX9-NEXT: s_lshr_b32 s4, s4, s8 1184; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4 1185; GFX9-NEXT: s_lshr_b32 s4, s2, 16 1186; GFX9-NEXT: s_and_b32 s2, s2, 0xffff 1187; GFX9-NEXT: s_lshr_b32 s5, s6, 16 1188; GFX9-NEXT: s_lshr_b32 s2, s2, s6 1189; GFX9-NEXT: s_lshr_b32 s4, s4, s5 1190; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4 1191; GFX9-NEXT: s_lshr_b32 s4, s3, 16 1192; GFX9-NEXT: s_and_b32 s3, s3, 0xffff 1193; GFX9-NEXT: s_lshr_b32 s5, s7, 16 1194; GFX9-NEXT: s_lshr_b32 s3, s3, s7 1195; GFX9-NEXT: s_lshr_b32 s4, s4, s5 1196; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4 1197; GFX9-NEXT: ; return to shader part epilog 1198; 1199; GFX10-LABEL: s_lshr_v8i16: 1200; GFX10: ; %bb.0: 1201; GFX10-NEXT: s_lshr_b32 s8, s0, 16 1202; GFX10-NEXT: s_and_b32 s0, s0, 0xffff 1203; GFX10-NEXT: s_lshr_b32 s9, s4, 16 1204; GFX10-NEXT: s_lshr_b32 s0, s0, s4 1205; GFX10-NEXT: s_lshr_b32 s4, s8, s9 1206; GFX10-NEXT: s_lshr_b32 s8, s1, 16 1207; GFX10-NEXT: s_and_b32 s1, s1, 0xffff 1208; GFX10-NEXT: s_lshr_b32 s9, s5, 16 1209; GFX10-NEXT: s_lshr_b32 s1, s1, s5 1210; GFX10-NEXT: s_lshr_b32 s5, s8, s9 1211; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s4 1212; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s5 1213; GFX10-NEXT: s_lshr_b32 s4, s2, 16 1214; GFX10-NEXT: s_and_b32 s2, s2, 0xffff 1215; GFX10-NEXT: s_lshr_b32 s5, s6, 16 1216; GFX10-NEXT: s_lshr_b32 s2, s2, s6 1217; GFX10-NEXT: s_lshr_b32 s4, s4, s5 1218; GFX10-NEXT: s_lshr_b32 s5, s3, 16 1219; GFX10-NEXT: s_and_b32 s3, s3, 0xffff 1220; GFX10-NEXT: s_lshr_b32 s6, s7, 16 1221; GFX10-NEXT: s_lshr_b32 s3, s3, s7 1222; GFX10-NEXT: s_lshr_b32 s5, s5, s6 1223; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s4 1224; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s5 1225; GFX10-NEXT: ; return to shader part epilog 1226 %result = lshr <8 x i16> %value, %amount 1227 %cast = bitcast <8 x i16> %result to <4 x i32> 1228 ret <4 x i32> %cast 1229} 1230 1231define i64 @v_lshr_i64(i64 %value, i64 %amount) { 1232; GFX6-LABEL: v_lshr_i64: 1233; GFX6: ; %bb.0: 1234; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1235; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], v2 1236; GFX6-NEXT: s_setpc_b64 s[30:31] 1237; 1238; GFX8-LABEL: v_lshr_i64: 1239; GFX8: ; %bb.0: 1240; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1241; GFX8-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 1242; GFX8-NEXT: s_setpc_b64 s[30:31] 1243; 1244; GFX9-LABEL: v_lshr_i64: 1245; GFX9: ; %bb.0: 1246; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1247; GFX9-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 1248; GFX9-NEXT: s_setpc_b64 s[30:31] 1249; 1250; GFX10-LABEL: v_lshr_i64: 1251; GFX10: ; %bb.0: 1252; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1253; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1254; GFX10-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 1255; GFX10-NEXT: s_setpc_b64 s[30:31] 1256 %result = lshr i64 %value, %amount 1257 ret i64 %result 1258} 1259 1260define i64 @v_lshr_i64_63(i64 %value) { 1261; GCN-LABEL: v_lshr_i64_63: 1262; GCN: ; %bb.0: 1263; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1264; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v1 1265; GCN-NEXT: v_mov_b32_e32 v1, 0 1266; GCN-NEXT: s_setpc_b64 s[30:31] 1267; 1268; GFX10-LABEL: v_lshr_i64_63: 1269; GFX10: ; %bb.0: 1270; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1271; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1272; GFX10-NEXT: v_lshrrev_b32_e32 v0, 31, v1 1273; GFX10-NEXT: v_mov_b32_e32 v1, 0 1274; GFX10-NEXT: s_setpc_b64 s[30:31] 1275 %result = lshr i64 %value, 63 1276 ret i64 %result 1277} 1278 1279define i64 @v_lshr_i64_33(i64 %value) { 1280; GCN-LABEL: v_lshr_i64_33: 1281; GCN: ; %bb.0: 1282; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1283; GCN-NEXT: v_lshrrev_b32_e32 v0, 1, v1 1284; GCN-NEXT: v_mov_b32_e32 v1, 0 1285; GCN-NEXT: s_setpc_b64 s[30:31] 1286; 1287; GFX10-LABEL: v_lshr_i64_33: 1288; GFX10: ; %bb.0: 1289; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1290; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1291; GFX10-NEXT: v_lshrrev_b32_e32 v0, 1, v1 1292; GFX10-NEXT: v_mov_b32_e32 v1, 0 1293; GFX10-NEXT: s_setpc_b64 s[30:31] 1294 %result = lshr i64 %value, 33 1295 ret i64 %result 1296} 1297 1298define i64 @v_lshr_i64_32(i64 %value) { 1299; GCN-LABEL: v_lshr_i64_32: 1300; GCN: ; %bb.0: 1301; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1302; GCN-NEXT: v_mov_b32_e32 v0, v1 1303; GCN-NEXT: v_mov_b32_e32 v1, 0 1304; GCN-NEXT: s_setpc_b64 s[30:31] 1305; 1306; GFX10-LABEL: v_lshr_i64_32: 1307; GFX10: ; %bb.0: 1308; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1309; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1310; GFX10-NEXT: v_mov_b32_e32 v0, v1 1311; GFX10-NEXT: v_mov_b32_e32 v1, 0 1312; GFX10-NEXT: s_setpc_b64 s[30:31] 1313 %result = lshr i64 %value, 32 1314 ret i64 %result 1315} 1316 1317define i64 @v_lshr_i64_31(i64 %value) { 1318; GFX6-LABEL: v_lshr_i64_31: 1319; GFX6: ; %bb.0: 1320; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1321; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 31 1322; GFX6-NEXT: s_setpc_b64 s[30:31] 1323; 1324; GFX8-LABEL: v_lshr_i64_31: 1325; GFX8: ; %bb.0: 1326; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1327; GFX8-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1328; GFX8-NEXT: s_setpc_b64 s[30:31] 1329; 1330; GFX9-LABEL: v_lshr_i64_31: 1331; GFX9: ; %bb.0: 1332; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1333; GFX9-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1334; GFX9-NEXT: s_setpc_b64 s[30:31] 1335; 1336; GFX10-LABEL: v_lshr_i64_31: 1337; GFX10: ; %bb.0: 1338; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1339; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1340; GFX10-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1341; GFX10-NEXT: s_setpc_b64 s[30:31] 1342 %result = lshr i64 %value, 31 1343 ret i64 %result 1344} 1345 1346define amdgpu_ps i64 @s_lshr_i64(i64 inreg %value, i64 inreg %amount) { 1347; GCN-LABEL: s_lshr_i64: 1348; GCN: ; %bb.0: 1349; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], s2 1350; GCN-NEXT: ; return to shader part epilog 1351; 1352; GFX10-LABEL: s_lshr_i64: 1353; GFX10: ; %bb.0: 1354; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], s2 1355; GFX10-NEXT: ; return to shader part epilog 1356 %result = lshr i64 %value, %amount 1357 ret i64 %result 1358} 1359 1360define amdgpu_ps i64 @s_lshr_i64_63(i64 inreg %value) { 1361; GCN-LABEL: s_lshr_i64_63: 1362; GCN: ; %bb.0: 1363; GCN-NEXT: s_lshr_b32 s0, s1, 31 1364; GCN-NEXT: s_mov_b32 s1, 0 1365; GCN-NEXT: ; return to shader part epilog 1366; 1367; GFX10-LABEL: s_lshr_i64_63: 1368; GFX10: ; %bb.0: 1369; GFX10-NEXT: s_lshr_b32 s0, s1, 31 1370; GFX10-NEXT: s_mov_b32 s1, 0 1371; GFX10-NEXT: ; return to shader part epilog 1372 %result = lshr i64 %value, 63 1373 ret i64 %result 1374} 1375 1376define amdgpu_ps i64 @s_lshr_i64_33(i64 inreg %value) { 1377; GCN-LABEL: s_lshr_i64_33: 1378; GCN: ; %bb.0: 1379; GCN-NEXT: s_lshr_b32 s0, s1, 1 1380; GCN-NEXT: s_mov_b32 s1, 0 1381; GCN-NEXT: ; return to shader part epilog 1382; 1383; GFX10-LABEL: s_lshr_i64_33: 1384; GFX10: ; %bb.0: 1385; GFX10-NEXT: s_lshr_b32 s0, s1, 1 1386; GFX10-NEXT: s_mov_b32 s1, 0 1387; GFX10-NEXT: ; return to shader part epilog 1388 %result = lshr i64 %value, 33 1389 ret i64 %result 1390} 1391 1392define amdgpu_ps i64 @s_lshr_i64_32(i64 inreg %value) { 1393; GCN-LABEL: s_lshr_i64_32: 1394; GCN: ; %bb.0: 1395; GCN-NEXT: s_mov_b32 s0, s1 1396; GCN-NEXT: s_mov_b32 s1, 0 1397; GCN-NEXT: ; return to shader part epilog 1398; 1399; GFX10-LABEL: s_lshr_i64_32: 1400; GFX10: ; %bb.0: 1401; GFX10-NEXT: s_mov_b32 s0, s1 1402; GFX10-NEXT: s_mov_b32 s1, 0 1403; GFX10-NEXT: ; return to shader part epilog 1404 %result = lshr i64 %value, 32 1405 ret i64 %result 1406} 1407 1408define amdgpu_ps i64 @s_lshr_i64_31(i64 inreg %value) { 1409; GCN-LABEL: s_lshr_i64_31: 1410; GCN: ; %bb.0: 1411; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], 31 1412; GCN-NEXT: ; return to shader part epilog 1413; 1414; GFX10-LABEL: s_lshr_i64_31: 1415; GFX10: ; %bb.0: 1416; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], 31 1417; GFX10-NEXT: ; return to shader part epilog 1418 %result = lshr i64 %value, 31 1419 ret i64 %result 1420} 1421 1422define amdgpu_ps <2 x float> @lshr_i64_sv(i64 inreg %value, i64 %amount) { 1423; GFX6-LABEL: lshr_i64_sv: 1424; GFX6: ; %bb.0: 1425; GFX6-NEXT: v_lshr_b64 v[0:1], s[0:1], v0 1426; GFX6-NEXT: ; return to shader part epilog 1427; 1428; GFX8-LABEL: lshr_i64_sv: 1429; GFX8: ; %bb.0: 1430; GFX8-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1] 1431; GFX8-NEXT: ; return to shader part epilog 1432; 1433; GFX9-LABEL: lshr_i64_sv: 1434; GFX9: ; %bb.0: 1435; GFX9-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1] 1436; GFX9-NEXT: ; return to shader part epilog 1437; 1438; GFX10-LABEL: lshr_i64_sv: 1439; GFX10: ; %bb.0: 1440; GFX10-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1] 1441; GFX10-NEXT: ; return to shader part epilog 1442 %result = lshr i64 %value, %amount 1443 %cast = bitcast i64 %result to <2 x float> 1444 ret <2 x float> %cast 1445} 1446 1447define amdgpu_ps <2 x float> @lshr_i64_vs(i64 %value, i64 inreg %amount) { 1448; GFX6-LABEL: lshr_i64_vs: 1449; GFX6: ; %bb.0: 1450; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], s0 1451; GFX6-NEXT: ; return to shader part epilog 1452; 1453; GFX8-LABEL: lshr_i64_vs: 1454; GFX8: ; %bb.0: 1455; GFX8-NEXT: v_lshrrev_b64 v[0:1], s0, v[0:1] 1456; GFX8-NEXT: ; return to shader part epilog 1457; 1458; GFX9-LABEL: lshr_i64_vs: 1459; GFX9: ; %bb.0: 1460; GFX9-NEXT: v_lshrrev_b64 v[0:1], s0, v[0:1] 1461; GFX9-NEXT: ; return to shader part epilog 1462; 1463; GFX10-LABEL: lshr_i64_vs: 1464; GFX10: ; %bb.0: 1465; GFX10-NEXT: v_lshrrev_b64 v[0:1], s0, v[0:1] 1466; GFX10-NEXT: ; return to shader part epilog 1467 %result = lshr i64 %value, %amount 1468 %cast = bitcast i64 %result to <2 x float> 1469 ret <2 x float> %cast 1470} 1471 1472define <2 x i64> @v_lshr_v2i64(<2 x i64> %value, <2 x i64> %amount) { 1473; GFX6-LABEL: v_lshr_v2i64: 1474; GFX6: ; %bb.0: 1475; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1476; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], v4 1477; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], v6 1478; GFX6-NEXT: s_setpc_b64 s[30:31] 1479; 1480; GFX8-LABEL: v_lshr_v2i64: 1481; GFX8: ; %bb.0: 1482; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1483; GFX8-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1] 1484; GFX8-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3] 1485; GFX8-NEXT: s_setpc_b64 s[30:31] 1486; 1487; GFX9-LABEL: v_lshr_v2i64: 1488; GFX9: ; %bb.0: 1489; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1490; GFX9-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1] 1491; GFX9-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3] 1492; GFX9-NEXT: s_setpc_b64 s[30:31] 1493; 1494; GFX10-LABEL: v_lshr_v2i64: 1495; GFX10: ; %bb.0: 1496; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1497; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1498; GFX10-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1] 1499; GFX10-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3] 1500; GFX10-NEXT: s_setpc_b64 s[30:31] 1501 %result = lshr <2 x i64> %value, %amount 1502 ret <2 x i64> %result 1503} 1504 1505define <2 x i64> @v_lshr_v2i64_31(<2 x i64> %value) { 1506; GFX6-LABEL: v_lshr_v2i64_31: 1507; GFX6: ; %bb.0: 1508; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1509; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 31 1510; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], 31 1511; GFX6-NEXT: s_setpc_b64 s[30:31] 1512; 1513; GFX8-LABEL: v_lshr_v2i64_31: 1514; GFX8: ; %bb.0: 1515; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1516; GFX8-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1517; GFX8-NEXT: v_lshrrev_b64 v[2:3], 31, v[2:3] 1518; GFX8-NEXT: s_setpc_b64 s[30:31] 1519; 1520; GFX9-LABEL: v_lshr_v2i64_31: 1521; GFX9: ; %bb.0: 1522; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1523; GFX9-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1524; GFX9-NEXT: v_lshrrev_b64 v[2:3], 31, v[2:3] 1525; GFX9-NEXT: s_setpc_b64 s[30:31] 1526; 1527; GFX10-LABEL: v_lshr_v2i64_31: 1528; GFX10: ; %bb.0: 1529; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1530; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1531; GFX10-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1] 1532; GFX10-NEXT: v_lshrrev_b64 v[2:3], 31, v[2:3] 1533; GFX10-NEXT: s_setpc_b64 s[30:31] 1534 %result = lshr <2 x i64> %value, <i64 31, i64 31> 1535 ret <2 x i64> %result 1536} 1537 1538define amdgpu_ps <2 x i64> @s_lshr_v2i64(<2 x i64> inreg %value, <2 x i64> inreg %amount) { 1539; GCN-LABEL: s_lshr_v2i64: 1540; GCN: ; %bb.0: 1541; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], s4 1542; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], s6 1543; GCN-NEXT: ; return to shader part epilog 1544; 1545; GFX10-LABEL: s_lshr_v2i64: 1546; GFX10: ; %bb.0: 1547; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], s4 1548; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s6 1549; GFX10-NEXT: ; return to shader part epilog 1550 %result = lshr <2 x i64> %value, %amount 1551 ret <2 x i64> %result 1552} 1553 1554define i65 @v_lshr_i65(i65 %value, i65 %amount) { 1555; GFX6-LABEL: v_lshr_i65: 1556; GFX6: ; %bb.0: 1557; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1558; GFX6-NEXT: v_and_b32_e32 v4, 1, v2 1559; GFX6-NEXT: v_mov_b32_e32 v5, 0 1560; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 64, v3 1561; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 64, v3 1562; GFX6-NEXT: v_lshr_b64 v[6:7], v[0:1], v3 1563; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], v8 1564; GFX6-NEXT: v_lshr_b64 v[10:11], v[4:5], v3 1565; GFX6-NEXT: v_lshr_b64 v[4:5], v[4:5], v2 1566; GFX6-NEXT: v_or_b32_e32 v6, v6, v8 1567; GFX6-NEXT: v_or_b32_e32 v7, v7, v9 1568; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3 1569; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc 1570; GFX6-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc 1571; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3 1572; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5] 1573; GFX6-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5] 1574; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc 1575; GFX6-NEXT: s_setpc_b64 s[30:31] 1576; 1577; GFX8-LABEL: v_lshr_i65: 1578; GFX8: ; %bb.0: 1579; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1580; GFX8-NEXT: v_and_b32_e32 v4, 1, v2 1581; GFX8-NEXT: v_mov_b32_e32 v5, 0 1582; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 64, v3 1583; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 64, v3 1584; GFX8-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1] 1585; GFX8-NEXT: v_lshlrev_b64 v[8:9], v8, v[4:5] 1586; GFX8-NEXT: v_lshrrev_b64 v[10:11], v3, v[4:5] 1587; GFX8-NEXT: v_lshrrev_b64 v[4:5], v2, v[4:5] 1588; GFX8-NEXT: v_or_b32_e32 v6, v6, v8 1589; GFX8-NEXT: v_or_b32_e32 v7, v7, v9 1590; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3 1591; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc 1592; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc 1593; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3 1594; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5] 1595; GFX8-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5] 1596; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc 1597; GFX8-NEXT: s_setpc_b64 s[30:31] 1598; 1599; GFX9-LABEL: v_lshr_i65: 1600; GFX9: ; %bb.0: 1601; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1602; GFX9-NEXT: v_and_b32_e32 v4, 1, v2 1603; GFX9-NEXT: v_mov_b32_e32 v5, 0 1604; GFX9-NEXT: v_sub_u32_e32 v8, 64, v3 1605; GFX9-NEXT: v_subrev_u32_e32 v2, 64, v3 1606; GFX9-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1] 1607; GFX9-NEXT: v_lshlrev_b64 v[8:9], v8, v[4:5] 1608; GFX9-NEXT: v_lshrrev_b64 v[10:11], v3, v[4:5] 1609; GFX9-NEXT: v_lshrrev_b64 v[4:5], v2, v[4:5] 1610; GFX9-NEXT: v_or_b32_e32 v6, v6, v8 1611; GFX9-NEXT: v_or_b32_e32 v7, v7, v9 1612; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3 1613; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc 1614; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc 1615; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3 1616; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5] 1617; GFX9-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5] 1618; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc 1619; GFX9-NEXT: s_setpc_b64 s[30:31] 1620; 1621; GFX10-LABEL: v_lshr_i65: 1622; GFX10: ; %bb.0: 1623; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1624; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1625; GFX10-NEXT: v_mov_b32_e32 v5, 0 1626; GFX10-NEXT: v_and_b32_e32 v4, 1, v2 1627; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v3 1628; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 64, v3 1629; GFX10-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1] 1630; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v3 1631; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v3 1632; GFX10-NEXT: v_lshlrev_b64 v[8:9], v2, v[4:5] 1633; GFX10-NEXT: v_lshrrev_b64 v[10:11], v10, v[4:5] 1634; GFX10-NEXT: v_lshrrev_b64 v[4:5], v3, v[4:5] 1635; GFX10-NEXT: v_or_b32_e32 v2, v6, v8 1636; GFX10-NEXT: v_or_b32_e32 v6, v7, v9 1637; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo 1638; GFX10-NEXT: v_cndmask_b32_e32 v5, v11, v6, vcc_lo 1639; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v0, s4 1640; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s4 1641; GFX10-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc_lo 1642; GFX10-NEXT: s_setpc_b64 s[30:31] 1643 %result = lshr i65 %value, %amount 1644 ret i65 %result 1645} 1646 1647define i65 @v_lshr_i65_33(i65 %value) { 1648; GFX6-LABEL: v_lshr_i65_33: 1649; GFX6: ; %bb.0: 1650; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1651; GFX6-NEXT: v_mov_b32_e32 v3, v1 1652; GFX6-NEXT: v_and_b32_e32 v0, 1, v2 1653; GFX6-NEXT: v_mov_b32_e32 v1, 0 1654; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 31 1655; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v3 1656; GFX6-NEXT: v_or_b32_e32 v0, v2, v0 1657; GFX6-NEXT: v_mov_b32_e32 v2, 0 1658; GFX6-NEXT: s_setpc_b64 s[30:31] 1659; 1660; GFX8-LABEL: v_lshr_i65_33: 1661; GFX8: ; %bb.0: 1662; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1663; GFX8-NEXT: v_mov_b32_e32 v3, v1 1664; GFX8-NEXT: v_and_b32_e32 v0, 1, v2 1665; GFX8-NEXT: v_mov_b32_e32 v1, 0 1666; GFX8-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1] 1667; GFX8-NEXT: v_lshrrev_b32_e32 v2, 1, v3 1668; GFX8-NEXT: v_or_b32_e32 v0, v2, v0 1669; GFX8-NEXT: v_mov_b32_e32 v2, 0 1670; GFX8-NEXT: s_setpc_b64 s[30:31] 1671; 1672; GFX9-LABEL: v_lshr_i65_33: 1673; GFX9: ; %bb.0: 1674; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1675; GFX9-NEXT: v_mov_b32_e32 v3, v1 1676; GFX9-NEXT: v_and_b32_e32 v0, 1, v2 1677; GFX9-NEXT: v_mov_b32_e32 v1, 0 1678; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1] 1679; GFX9-NEXT: v_lshrrev_b32_e32 v2, 1, v3 1680; GFX9-NEXT: v_or_b32_e32 v0, v2, v0 1681; GFX9-NEXT: v_mov_b32_e32 v2, 0 1682; GFX9-NEXT: s_setpc_b64 s[30:31] 1683; 1684; GFX10-LABEL: v_lshr_i65_33: 1685; GFX10: ; %bb.0: 1686; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1687; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1688; GFX10-NEXT: v_mov_b32_e32 v3, v1 1689; GFX10-NEXT: v_mov_b32_e32 v1, 0 1690; GFX10-NEXT: v_and_b32_e32 v0, 1, v2 1691; GFX10-NEXT: v_lshrrev_b32_e32 v2, 1, v3 1692; GFX10-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1] 1693; GFX10-NEXT: v_or_b32_e32 v0, v2, v0 1694; GFX10-NEXT: v_mov_b32_e32 v2, 0 1695; GFX10-NEXT: s_setpc_b64 s[30:31] 1696 %result = lshr i65 %value, 33 1697 ret i65 %result 1698} 1699 1700define amdgpu_ps i65 @s_lshr_i65(i65 inreg %value, i65 inreg %amount) { 1701; GCN-LABEL: s_lshr_i65: 1702; GCN: ; %bb.0: 1703; GCN-NEXT: s_and_b64 s[4:5], s[2:3], 1 1704; GCN-NEXT: s_sub_i32 s10, s3, 64 1705; GCN-NEXT: s_sub_i32 s8, 64, s3 1706; GCN-NEXT: s_cmp_lt_u32 s3, 64 1707; GCN-NEXT: s_cselect_b32 s11, 1, 0 1708; GCN-NEXT: s_cmp_eq_u32 s3, 0 1709; GCN-NEXT: s_cselect_b32 s12, 1, 0 1710; GCN-NEXT: s_lshr_b64 s[6:7], s[4:5], s3 1711; GCN-NEXT: s_lshr_b64 s[2:3], s[0:1], s3 1712; GCN-NEXT: s_lshl_b64 s[8:9], s[4:5], s8 1713; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] 1714; GCN-NEXT: s_lshr_b64 s[4:5], s[4:5], s10 1715; GCN-NEXT: s_cmp_lg_u32 s11, 0 1716; GCN-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5] 1717; GCN-NEXT: s_cmp_lg_u32 s12, 0 1718; GCN-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] 1719; GCN-NEXT: s_cmp_lg_u32 s11, 0 1720; GCN-NEXT: s_cselect_b64 s[2:3], s[6:7], 0 1721; GCN-NEXT: ; return to shader part epilog 1722; 1723; GFX10-LABEL: s_lshr_i65: 1724; GFX10: ; %bb.0: 1725; GFX10-NEXT: s_and_b64 s[4:5], s[2:3], 1 1726; GFX10-NEXT: s_sub_i32 s10, s3, 64 1727; GFX10-NEXT: s_sub_i32 s2, 64, s3 1728; GFX10-NEXT: s_cmp_lt_u32 s3, 64 1729; GFX10-NEXT: s_cselect_b32 s11, 1, 0 1730; GFX10-NEXT: s_cmp_eq_u32 s3, 0 1731; GFX10-NEXT: s_cselect_b32 s12, 1, 0 1732; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s3 1733; GFX10-NEXT: s_lshl_b64 s[8:9], s[4:5], s2 1734; GFX10-NEXT: s_lshr_b64 s[2:3], s[4:5], s3 1735; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] 1736; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], s10 1737; GFX10-NEXT: s_cmp_lg_u32 s11, 0 1738; GFX10-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5] 1739; GFX10-NEXT: s_cmp_lg_u32 s12, 0 1740; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] 1741; GFX10-NEXT: s_cmp_lg_u32 s11, 0 1742; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], 0 1743; GFX10-NEXT: ; return to shader part epilog 1744 %result = lshr i65 %value, %amount 1745 ret i65 %result 1746} 1747 1748define amdgpu_ps i65 @s_lshr_i65_33(i65 inreg %value) { 1749; GCN-LABEL: s_lshr_i65_33: 1750; GCN: ; %bb.0: 1751; GCN-NEXT: s_and_b64 s[2:3], s[2:3], 1 1752; GCN-NEXT: s_lshr_b32 s0, s1, 1 1753; GCN-NEXT: s_mov_b32 s1, 0 1754; GCN-NEXT: s_lshl_b64 s[4:5], s[2:3], 31 1755; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] 1756; GCN-NEXT: s_lshr_b32 s2, s3, 1 1757; GCN-NEXT: ; return to shader part epilog 1758; 1759; GFX10-LABEL: s_lshr_i65_33: 1760; GFX10: ; %bb.0: 1761; GFX10-NEXT: s_and_b64 s[2:3], s[2:3], 1 1762; GFX10-NEXT: s_lshr_b32 s0, s1, 1 1763; GFX10-NEXT: s_mov_b32 s1, 0 1764; GFX10-NEXT: s_lshl_b64 s[4:5], s[2:3], 31 1765; GFX10-NEXT: s_lshr_b32 s2, s3, 1 1766; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] 1767; GFX10-NEXT: ; return to shader part epilog 1768 %result = lshr i65 %value, 33 1769 ret i65 %result 1770} 1771 1772; FIXME: Argument lowering asserts 1773; define <2 x i65> @v_lshr_v2i65(<2 x i65> %value, <2 x i65> %amount) { 1774; %result = lshr <2 x i65> %value, %amount 1775; ret <2 x i65> %result 1776; } 1777 1778; define amdgpu_ps <2 x i65> @s_lshr_v2i65(<2 x i65> inreg %value, <2 x i65> inreg %amount) { 1779; %result = lshr <2 x i65> %value, %amount 1780; ret <2 x i65> %result 1781; } 1782