1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+unaligned-access-mode -verify-machineinstrs < %s | FileCheck --check-prefix=GFX9 %s
3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -mattr=+unaligned-access-mode -verify-machineinstrs < %s | FileCheck --check-prefix=GFX7 %s
4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -mattr=+unaligned-access-mode -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
5
6; Unaligned DS access in available from GFX9 onwards.
7; LDS alignment enforcement is controlled by a configuration register:
8; SH_MEM_CONFIG.alignment_mode
9
10define <4 x i32> @load_lds_v4i32_align1(<4 x i32> addrspace(3)* %ptr) {
11; GFX9-LABEL: load_lds_v4i32_align1:
12; GFX9:       ; %bb.0:
13; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
14; GFX9-NEXT:    ds_read2_b64 v[0:3], v0 offset1:1
15; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
16; GFX9-NEXT:    s_setpc_b64 s[30:31]
17;
18; GFX7-LABEL: load_lds_v4i32_align1:
19; GFX7:       ; %bb.0:
20; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
21; GFX7-NEXT:    ds_read_u8 v1, v0
22; GFX7-NEXT:    ds_read_u8 v2, v0 offset:1
23; GFX7-NEXT:    ds_read_u8 v3, v0 offset:2
24; GFX7-NEXT:    ds_read_u8 v4, v0 offset:3
25; GFX7-NEXT:    ds_read_u8 v5, v0 offset:4
26; GFX7-NEXT:    ds_read_u8 v6, v0 offset:5
27; GFX7-NEXT:    ds_read_u8 v7, v0 offset:6
28; GFX7-NEXT:    ds_read_u8 v8, v0 offset:7
29; GFX7-NEXT:    s_waitcnt lgkmcnt(6)
30; GFX7-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
31; GFX7-NEXT:    v_or_b32_e32 v1, v1, v2
32; GFX7-NEXT:    s_waitcnt lgkmcnt(5)
33; GFX7-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
34; GFX7-NEXT:    v_or_b32_e32 v1, v1, v2
35; GFX7-NEXT:    s_waitcnt lgkmcnt(4)
36; GFX7-NEXT:    v_lshlrev_b32_e32 v2, 24, v4
37; GFX7-NEXT:    v_or_b32_e32 v4, v1, v2
38; GFX7-NEXT:    s_waitcnt lgkmcnt(2)
39; GFX7-NEXT:    v_lshlrev_b32_e32 v1, 8, v6
40; GFX7-NEXT:    v_or_b32_e32 v1, v5, v1
41; GFX7-NEXT:    s_waitcnt lgkmcnt(1)
42; GFX7-NEXT:    v_lshlrev_b32_e32 v2, 16, v7
43; GFX7-NEXT:    v_or_b32_e32 v1, v1, v2
44; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
45; GFX7-NEXT:    v_lshlrev_b32_e32 v2, 24, v8
46; GFX7-NEXT:    v_or_b32_e32 v1, v1, v2
47; GFX7-NEXT:    ds_read_u8 v2, v0 offset:8
48; GFX7-NEXT:    ds_read_u8 v3, v0 offset:9
49; GFX7-NEXT:    ds_read_u8 v5, v0 offset:10
50; GFX7-NEXT:    ds_read_u8 v6, v0 offset:11
51; GFX7-NEXT:    ds_read_u8 v7, v0 offset:12
52; GFX7-NEXT:    ds_read_u8 v8, v0 offset:13
53; GFX7-NEXT:    ds_read_u8 v9, v0 offset:14
54; GFX7-NEXT:    ds_read_u8 v0, v0 offset:15
55; GFX7-NEXT:    s_waitcnt lgkmcnt(6)
56; GFX7-NEXT:    v_lshlrev_b32_e32 v3, 8, v3
57; GFX7-NEXT:    v_or_b32_e32 v2, v2, v3
58; GFX7-NEXT:    s_waitcnt lgkmcnt(5)
59; GFX7-NEXT:    v_lshlrev_b32_e32 v3, 16, v5
60; GFX7-NEXT:    v_or_b32_e32 v2, v2, v3
61; GFX7-NEXT:    s_waitcnt lgkmcnt(4)
62; GFX7-NEXT:    v_lshlrev_b32_e32 v3, 24, v6
63; GFX7-NEXT:    v_or_b32_e32 v2, v2, v3
64; GFX7-NEXT:    s_waitcnt lgkmcnt(2)
65; GFX7-NEXT:    v_lshlrev_b32_e32 v3, 8, v8
66; GFX7-NEXT:    v_or_b32_e32 v3, v7, v3
67; GFX7-NEXT:    s_waitcnt lgkmcnt(1)
68; GFX7-NEXT:    v_lshlrev_b32_e32 v5, 16, v9
69; GFX7-NEXT:    v_or_b32_e32 v3, v3, v5
70; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
71; GFX7-NEXT:    v_lshlrev_b32_e32 v0, 24, v0
72; GFX7-NEXT:    v_or_b32_e32 v3, v3, v0
73; GFX7-NEXT:    v_mov_b32_e32 v0, v4
74; GFX7-NEXT:    s_setpc_b64 s[30:31]
75;
76; GFX10-LABEL: load_lds_v4i32_align1:
77; GFX10:       ; %bb.0:
78; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
79; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
80; GFX10-NEXT:    ds_read_u8 v1, v0
81; GFX10-NEXT:    ds_read_u8 v2, v0 offset:1
82; GFX10-NEXT:    ds_read_u8 v3, v0 offset:2
83; GFX10-NEXT:    ds_read_u8 v4, v0 offset:3
84; GFX10-NEXT:    ds_read_u8 v5, v0 offset:4
85; GFX10-NEXT:    ds_read_u8 v6, v0 offset:5
86; GFX10-NEXT:    ds_read_u8 v7, v0 offset:6
87; GFX10-NEXT:    ds_read_u8 v8, v0 offset:7
88; GFX10-NEXT:    ds_read_u8 v9, v0 offset:8
89; GFX10-NEXT:    ds_read_u8 v10, v0 offset:9
90; GFX10-NEXT:    ds_read_u8 v11, v0 offset:10
91; GFX10-NEXT:    ds_read_u8 v12, v0 offset:11
92; GFX10-NEXT:    ds_read_u8 v13, v0 offset:12
93; GFX10-NEXT:    ds_read_u8 v14, v0 offset:13
94; GFX10-NEXT:    ds_read_u8 v15, v0 offset:14
95; GFX10-NEXT:    ds_read_u8 v0, v0 offset:15
96; GFX10-NEXT:    s_waitcnt lgkmcnt(14)
97; GFX10-NEXT:    v_lshl_or_b32 v1, v2, 8, v1
98; GFX10-NEXT:    s_waitcnt lgkmcnt(13)
99; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
100; GFX10-NEXT:    s_waitcnt lgkmcnt(12)
101; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 24, v4
102; GFX10-NEXT:    s_waitcnt lgkmcnt(10)
103; GFX10-NEXT:    v_lshl_or_b32 v4, v6, 8, v5
104; GFX10-NEXT:    s_waitcnt lgkmcnt(9)
105; GFX10-NEXT:    v_lshlrev_b32_e32 v5, 16, v7
106; GFX10-NEXT:    s_waitcnt lgkmcnt(8)
107; GFX10-NEXT:    v_lshlrev_b32_e32 v6, 24, v8
108; GFX10-NEXT:    s_waitcnt lgkmcnt(6)
109; GFX10-NEXT:    v_lshl_or_b32 v7, v10, 8, v9
110; GFX10-NEXT:    s_waitcnt lgkmcnt(5)
111; GFX10-NEXT:    v_lshlrev_b32_e32 v8, 16, v11
112; GFX10-NEXT:    s_waitcnt lgkmcnt(4)
113; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 24, v12
114; GFX10-NEXT:    s_waitcnt lgkmcnt(2)
115; GFX10-NEXT:    v_lshl_or_b32 v10, v14, 8, v13
116; GFX10-NEXT:    s_waitcnt lgkmcnt(1)
117; GFX10-NEXT:    v_lshlrev_b32_e32 v11, 16, v15
118; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
119; GFX10-NEXT:    v_lshlrev_b32_e32 v12, 24, v0
120; GFX10-NEXT:    v_or3_b32 v0, v1, v2, v3
121; GFX10-NEXT:    v_or3_b32 v1, v4, v5, v6
122; GFX10-NEXT:    v_or3_b32 v2, v7, v8, v9
123; GFX10-NEXT:    v_or3_b32 v3, v10, v11, v12
124; GFX10-NEXT:    s_setpc_b64 s[30:31]
125  %load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 1
126  ret <4 x i32> %load
127}
128
129define <3 x i32> @load_lds_v3i32_align1(<3 x i32> addrspace(3)* %ptr) {
130; GFX9-LABEL: load_lds_v3i32_align1:
131; GFX9:       ; %bb.0:
132; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
133; GFX9-NEXT:    ds_read_b96 v[0:2], v0
134; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
135; GFX9-NEXT:    s_setpc_b64 s[30:31]
136;
137; GFX7-LABEL: load_lds_v3i32_align1:
138; GFX7:       ; %bb.0:
139; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
140; GFX7-NEXT:    ds_read_u8 v1, v0
141; GFX7-NEXT:    ds_read_u8 v2, v0 offset:1
142; GFX7-NEXT:    ds_read_u8 v3, v0 offset:2
143; GFX7-NEXT:    ds_read_u8 v4, v0 offset:3
144; GFX7-NEXT:    ds_read_u8 v5, v0 offset:4
145; GFX7-NEXT:    ds_read_u8 v6, v0 offset:5
146; GFX7-NEXT:    ds_read_u8 v7, v0 offset:6
147; GFX7-NEXT:    ds_read_u8 v8, v0 offset:7
148; GFX7-NEXT:    s_waitcnt lgkmcnt(6)
149; GFX7-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
150; GFX7-NEXT:    v_or_b32_e32 v1, v1, v2
151; GFX7-NEXT:    s_waitcnt lgkmcnt(5)
152; GFX7-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
153; GFX7-NEXT:    v_or_b32_e32 v1, v1, v2
154; GFX7-NEXT:    s_waitcnt lgkmcnt(4)
155; GFX7-NEXT:    v_lshlrev_b32_e32 v2, 24, v4
156; GFX7-NEXT:    v_or_b32_e32 v3, v1, v2
157; GFX7-NEXT:    s_waitcnt lgkmcnt(2)
158; GFX7-NEXT:    v_lshlrev_b32_e32 v1, 8, v6
159; GFX7-NEXT:    v_or_b32_e32 v1, v5, v1
160; GFX7-NEXT:    s_waitcnt lgkmcnt(1)
161; GFX7-NEXT:    v_lshlrev_b32_e32 v2, 16, v7
162; GFX7-NEXT:    v_or_b32_e32 v1, v1, v2
163; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
164; GFX7-NEXT:    v_lshlrev_b32_e32 v2, 24, v8
165; GFX7-NEXT:    v_or_b32_e32 v1, v1, v2
166; GFX7-NEXT:    ds_read_u8 v2, v0 offset:8
167; GFX7-NEXT:    ds_read_u8 v4, v0 offset:9
168; GFX7-NEXT:    ds_read_u8 v5, v0 offset:10
169; GFX7-NEXT:    ds_read_u8 v0, v0 offset:11
170; GFX7-NEXT:    s_waitcnt lgkmcnt(2)
171; GFX7-NEXT:    v_lshlrev_b32_e32 v4, 8, v4
172; GFX7-NEXT:    v_or_b32_e32 v2, v2, v4
173; GFX7-NEXT:    s_waitcnt lgkmcnt(1)
174; GFX7-NEXT:    v_lshlrev_b32_e32 v4, 16, v5
175; GFX7-NEXT:    v_or_b32_e32 v2, v2, v4
176; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
177; GFX7-NEXT:    v_lshlrev_b32_e32 v0, 24, v0
178; GFX7-NEXT:    v_or_b32_e32 v2, v2, v0
179; GFX7-NEXT:    v_mov_b32_e32 v0, v3
180; GFX7-NEXT:    s_setpc_b64 s[30:31]
181;
182; GFX10-LABEL: load_lds_v3i32_align1:
183; GFX10:       ; %bb.0:
184; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
185; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
186; GFX10-NEXT:    ds_read_u8 v1, v0
187; GFX10-NEXT:    ds_read_u8 v2, v0 offset:1
188; GFX10-NEXT:    ds_read_u8 v3, v0 offset:2
189; GFX10-NEXT:    ds_read_u8 v4, v0 offset:3
190; GFX10-NEXT:    ds_read_u8 v5, v0 offset:4
191; GFX10-NEXT:    ds_read_u8 v6, v0 offset:5
192; GFX10-NEXT:    ds_read_u8 v7, v0 offset:6
193; GFX10-NEXT:    ds_read_u8 v8, v0 offset:7
194; GFX10-NEXT:    ds_read_u8 v9, v0 offset:8
195; GFX10-NEXT:    ds_read_u8 v10, v0 offset:9
196; GFX10-NEXT:    ds_read_u8 v11, v0 offset:10
197; GFX10-NEXT:    ds_read_u8 v0, v0 offset:11
198; GFX10-NEXT:    s_waitcnt lgkmcnt(10)
199; GFX10-NEXT:    v_lshl_or_b32 v1, v2, 8, v1
200; GFX10-NEXT:    s_waitcnt lgkmcnt(9)
201; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
202; GFX10-NEXT:    s_waitcnt lgkmcnt(8)
203; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 24, v4
204; GFX10-NEXT:    s_waitcnt lgkmcnt(6)
205; GFX10-NEXT:    v_lshl_or_b32 v4, v6, 8, v5
206; GFX10-NEXT:    s_waitcnt lgkmcnt(5)
207; GFX10-NEXT:    v_lshlrev_b32_e32 v5, 16, v7
208; GFX10-NEXT:    s_waitcnt lgkmcnt(4)
209; GFX10-NEXT:    v_lshlrev_b32_e32 v6, 24, v8
210; GFX10-NEXT:    s_waitcnt lgkmcnt(2)
211; GFX10-NEXT:    v_lshl_or_b32 v7, v10, 8, v9
212; GFX10-NEXT:    s_waitcnt lgkmcnt(1)
213; GFX10-NEXT:    v_lshlrev_b32_e32 v8, 16, v11
214; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
215; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 24, v0
216; GFX10-NEXT:    v_or3_b32 v0, v1, v2, v3
217; GFX10-NEXT:    v_or3_b32 v1, v4, v5, v6
218; GFX10-NEXT:    v_or3_b32 v2, v7, v8, v9
219; GFX10-NEXT:    s_setpc_b64 s[30:31]
220  %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 1
221  ret <3 x i32> %load
222}
223
224define void @store_lds_v4i32_align1(<4 x i32> addrspace(3)* %out, <4 x i32> %x) {
225; GFX9-LABEL: store_lds_v4i32_align1:
226; GFX9:       ; %bb.0:
227; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
228; GFX9-NEXT:    ds_write2_b64 v0, v[1:2], v[3:4] offset1:1
229; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
230; GFX9-NEXT:    s_setpc_b64 s[30:31]
231;
232; GFX7-LABEL: store_lds_v4i32_align1:
233; GFX7:       ; %bb.0:
234; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
235; GFX7-NEXT:    s_mov_b32 m0, -1
236; GFX7-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
237; GFX7-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
238; GFX7-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
239; GFX7-NEXT:    ds_write_b8 v0, v1
240; GFX7-NEXT:    ds_write_b8 v0, v5 offset:1
241; GFX7-NEXT:    ds_write_b8 v0, v6 offset:2
242; GFX7-NEXT:    ds_write_b8 v0, v7 offset:3
243; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
244; GFX7-NEXT:    v_lshrrev_b32_e32 v5, 16, v2
245; GFX7-NEXT:    v_lshrrev_b32_e32 v6, 24, v2
246; GFX7-NEXT:    ds_write_b8 v0, v2 offset:4
247; GFX7-NEXT:    ds_write_b8 v0, v1 offset:5
248; GFX7-NEXT:    ds_write_b8 v0, v5 offset:6
249; GFX7-NEXT:    ds_write_b8 v0, v6 offset:7
250; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 8, v3
251; GFX7-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
252; GFX7-NEXT:    v_lshrrev_b32_e32 v5, 24, v3
253; GFX7-NEXT:    ds_write_b8 v0, v3 offset:8
254; GFX7-NEXT:    ds_write_b8 v0, v1 offset:9
255; GFX7-NEXT:    ds_write_b8 v0, v2 offset:10
256; GFX7-NEXT:    ds_write_b8 v0, v5 offset:11
257; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 8, v4
258; GFX7-NEXT:    v_lshrrev_b32_e32 v2, 16, v4
259; GFX7-NEXT:    v_lshrrev_b32_e32 v3, 24, v4
260; GFX7-NEXT:    ds_write_b8 v0, v4 offset:12
261; GFX7-NEXT:    ds_write_b8 v0, v1 offset:13
262; GFX7-NEXT:    ds_write_b8 v0, v2 offset:14
263; GFX7-NEXT:    ds_write_b8 v0, v3 offset:15
264; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
265; GFX7-NEXT:    s_setpc_b64 s[30:31]
266;
267; GFX10-LABEL: store_lds_v4i32_align1:
268; GFX10:       ; %bb.0:
269; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
270; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
271; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
272; GFX10-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
273; GFX10-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
274; GFX10-NEXT:    ds_write_b8 v0, v1
275; GFX10-NEXT:    ds_write_b8 v0, v5 offset:1
276; GFX10-NEXT:    ds_write_b8 v0, v6 offset:2
277; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
278; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 16, v2
279; GFX10-NEXT:    v_lshrrev_b32_e32 v6, 24, v2
280; GFX10-NEXT:    ds_write_b8 v0, v7 offset:3
281; GFX10-NEXT:    ds_write_b8 v0, v2 offset:4
282; GFX10-NEXT:    ds_write_b8 v0, v1 offset:5
283; GFX10-NEXT:    ds_write_b8 v0, v5 offset:6
284; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 8, v3
285; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
286; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 24, v3
287; GFX10-NEXT:    ds_write_b8 v0, v6 offset:7
288; GFX10-NEXT:    ds_write_b8 v0, v3 offset:8
289; GFX10-NEXT:    ds_write_b8 v0, v1 offset:9
290; GFX10-NEXT:    ds_write_b8 v0, v2 offset:10
291; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 8, v4
292; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v4
293; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 24, v4
294; GFX10-NEXT:    ds_write_b8 v0, v5 offset:11
295; GFX10-NEXT:    ds_write_b8 v0, v4 offset:12
296; GFX10-NEXT:    ds_write_b8 v0, v1 offset:13
297; GFX10-NEXT:    ds_write_b8 v0, v2 offset:14
298; GFX10-NEXT:    ds_write_b8 v0, v3 offset:15
299; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
300; GFX10-NEXT:    s_setpc_b64 s[30:31]
301  store <4 x i32> %x, <4 x i32> addrspace(3)* %out, align 1
302  ret void
303}
304
305define void @store_lds_v3i32_align1(<3 x i32> addrspace(3)* %out, <3 x i32> %x) {
306; GFX9-LABEL: store_lds_v3i32_align1:
307; GFX9:       ; %bb.0:
308; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
309; GFX9-NEXT:    ds_write_b96 v0, v[1:3]
310; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
311; GFX9-NEXT:    s_setpc_b64 s[30:31]
312;
313; GFX7-LABEL: store_lds_v3i32_align1:
314; GFX7:       ; %bb.0:
315; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
316; GFX7-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
317; GFX7-NEXT:    s_mov_b32 m0, -1
318; GFX7-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
319; GFX7-NEXT:    v_lshrrev_b32_e32 v6, 24, v1
320; GFX7-NEXT:    ds_write_b8 v0, v1
321; GFX7-NEXT:    ds_write_b8 v0, v4 offset:1
322; GFX7-NEXT:    ds_write_b8 v0, v5 offset:2
323; GFX7-NEXT:    ds_write_b8 v0, v6 offset:3
324; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
325; GFX7-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
326; GFX7-NEXT:    v_lshrrev_b32_e32 v5, 24, v2
327; GFX7-NEXT:    ds_write_b8 v0, v2 offset:4
328; GFX7-NEXT:    ds_write_b8 v0, v1 offset:5
329; GFX7-NEXT:    ds_write_b8 v0, v4 offset:6
330; GFX7-NEXT:    ds_write_b8 v0, v5 offset:7
331; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 8, v3
332; GFX7-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
333; GFX7-NEXT:    v_lshrrev_b32_e32 v4, 24, v3
334; GFX7-NEXT:    ds_write_b8 v0, v3 offset:8
335; GFX7-NEXT:    ds_write_b8 v0, v1 offset:9
336; GFX7-NEXT:    ds_write_b8 v0, v2 offset:10
337; GFX7-NEXT:    ds_write_b8 v0, v4 offset:11
338; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
339; GFX7-NEXT:    s_setpc_b64 s[30:31]
340;
341; GFX10-LABEL: store_lds_v3i32_align1:
342; GFX10:       ; %bb.0:
343; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
344; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
345; GFX10-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
346; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
347; GFX10-NEXT:    v_lshrrev_b32_e32 v6, 24, v1
348; GFX10-NEXT:    ds_write_b8 v0, v1
349; GFX10-NEXT:    ds_write_b8 v0, v4 offset:1
350; GFX10-NEXT:    ds_write_b8 v0, v5 offset:2
351; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
352; GFX10-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
353; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 24, v2
354; GFX10-NEXT:    ds_write_b8 v0, v6 offset:3
355; GFX10-NEXT:    ds_write_b8 v0, v2 offset:4
356; GFX10-NEXT:    ds_write_b8 v0, v1 offset:5
357; GFX10-NEXT:    ds_write_b8 v0, v4 offset:6
358; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 8, v3
359; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
360; GFX10-NEXT:    v_lshrrev_b32_e32 v4, 24, v3
361; GFX10-NEXT:    ds_write_b8 v0, v5 offset:7
362; GFX10-NEXT:    ds_write_b8 v0, v3 offset:8
363; GFX10-NEXT:    ds_write_b8 v0, v1 offset:9
364; GFX10-NEXT:    ds_write_b8 v0, v2 offset:10
365; GFX10-NEXT:    ds_write_b8 v0, v4 offset:11
366; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
367; GFX10-NEXT:    s_setpc_b64 s[30:31]
368  store <3 x i32> %x, <3 x i32> addrspace(3)* %out, align 1
369  ret void
370}
371
372define amdgpu_ps void @test_s_load_constant_v8i32_align1(<8 x i32> addrspace(4)* inreg %ptr, <8 x i32> addrspace(1)* inreg %out) {
373; GFX9-LABEL: test_s_load_constant_v8i32_align1:
374; GFX9:       ; %bb.0:
375; GFX9-NEXT:    v_mov_b32_e32 v8, 0
376; GFX9-NEXT:    global_load_dwordx4 v[0:3], v8, s[0:1]
377; GFX9-NEXT:    global_load_dwordx4 v[4:7], v8, s[0:1] offset:16
378; GFX9-NEXT:    s_waitcnt vmcnt(1)
379; GFX9-NEXT:    global_store_dwordx4 v8, v[0:3], s[2:3]
380; GFX9-NEXT:    s_waitcnt vmcnt(1)
381; GFX9-NEXT:    global_store_dwordx4 v8, v[4:7], s[2:3] offset:16
382; GFX9-NEXT:    s_endpgm
383;
384; GFX7-LABEL: test_s_load_constant_v8i32_align1:
385; GFX7:       ; %bb.0:
386; GFX7-NEXT:    s_mov_b32 s4, s2
387; GFX7-NEXT:    s_mov_b32 s5, s3
388; GFX7-NEXT:    s_mov_b32 s2, -1
389; GFX7-NEXT:    s_mov_b32 s3, 0xf000
390; GFX7-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
391; GFX7-NEXT:    buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
392; GFX7-NEXT:    s_mov_b64 s[6:7], s[2:3]
393; GFX7-NEXT:    s_waitcnt vmcnt(1)
394; GFX7-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
395; GFX7-NEXT:    s_waitcnt vmcnt(1)
396; GFX7-NEXT:    buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
397; GFX7-NEXT:    s_endpgm
398;
399; GFX10-LABEL: test_s_load_constant_v8i32_align1:
400; GFX10:       ; %bb.0:
401; GFX10-NEXT:    v_mov_b32_e32 v8, 0
402; GFX10-NEXT:    s_clause 0x1
403; GFX10-NEXT:    global_load_dwordx4 v[0:3], v8, s[0:1]
404; GFX10-NEXT:    global_load_dwordx4 v[4:7], v8, s[0:1] offset:16
405; GFX10-NEXT:    s_waitcnt vmcnt(1)
406; GFX10-NEXT:    global_store_dwordx4 v8, v[0:3], s[2:3]
407; GFX10-NEXT:    s_waitcnt vmcnt(0)
408; GFX10-NEXT:    global_store_dwordx4 v8, v[4:7], s[2:3] offset:16
409; GFX10-NEXT:    s_endpgm
410  %load = load <8 x i32>, <8 x i32> addrspace(4)* %ptr, align 1
411  store <8 x i32> %load, <8 x i32> addrspace(1)* %out
412  ret void
413}
414